* Remaining VLV patches
@ 2012-06-12 21:47 Jesse Barnes
2012-06-12 21:47 ` [PATCH 1/7] drm/i915: ValleyView mode setting limits and PLL functions Jesse Barnes
` (6 more replies)
0 siblings, 7 replies; 16+ messages in thread
From: Jesse Barnes @ 2012-06-12 21:47 UTC (permalink / raw)
To: intel-gfx
I've long since forgotten any comments or requests, so these patches may
be missing some changes people wanted. However, they've been updated to
the latest drm-intel-next branch and work on my system here, so of no
one has objections, it would be nice if they could be integrated.
Thanks,
Jesse
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 1/7] drm/i915: ValleyView mode setting limits and PLL functions 2012-06-12 21:47 Remaining VLV patches Jesse Barnes @ 2012-06-12 21:47 ` Jesse Barnes 2012-06-13 8:06 ` Daniel Vetter 2012-06-12 21:47 ` [PATCH 2/7] drm/i915: Enable DP panel power sequencing for ValleyView Jesse Barnes ` (5 subsequent siblings) 6 siblings, 1 reply; 16+ messages in thread From: Jesse Barnes @ 2012-06-12 21:47 UTC (permalink / raw) To: intel-gfx Add some VLV limit structures and update the PLL code. v2: resolve conflicts, Vijay to re-post with PLL valid checks and fixed limits v3: re-add dpio write function Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_display.c | 250 +++++++++++++++++++++++++++++++++- 2 files changed, 249 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 7dcc04f..281446d 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -900,6 +900,7 @@ #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ +#define DPLL_LOCK_VLV (1<<15) #define DPLL_INTEGRATED_CLOCK_VLV (1<<13) #define SRX_INDEX 0x3c4 diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 0161d94..5006928 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -98,6 +98,11 @@ intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc, int target, int refclk, intel_clock_t *match_clock, intel_clock_t *best_clock); +static bool +intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc, + int target, int refclk, intel_clock_t *match_clock, + intel_clock_t *best_clock); + static inline u32 /* units of 100MHz */ intel_fdi_link_freq(struct drm_device *dev) { @@ -359,6 +364,48 @@ static const intel_limit_t intel_limits_ironlake_display_port = { .find_pll = intel_find_pll_ironlake_dp, }; +static const intel_limit_t intel_limits_vlv_dac = { + .dot = { .min = 25000, .max = 270000 }, + .vco = { .min = 4000000, .max = 6000000 }, + .n = { .min = 1, .max = 7 }, + .m = { .min = 22, .max = 450 }, /* guess */ + .m1 = { .min = 2, .max = 3 }, + .m2 = { .min = 11, .max = 156 }, + .p = { .min = 10, .max = 30 }, + .p1 = { .min = 2, .max = 3 }, + .p2 = { .dot_limit = 270000, + .p2_slow = 10, .p2_fast = 5 }, + .find_pll = intel_vlv_find_best_pll, +}; + +static const intel_limit_t intel_limits_vlv_hdmi = { + .dot = { .min = 20000, .max = 165000 }, + .vco = { .min = 5994000, .max = 4000000 }, + .n = { .min = 1, .max = 7 }, + .m = { .min = 60, .max = 300 }, /* guess */ + .m1 = { .min = 2, .max = 3 }, + .m2 = { .min = 11, .max = 156 }, + .p = { .min = 10, .max = 30 }, + .p1 = { .min = 2, .max = 3 }, + .p2 = { .dot_limit = 270000, + .p2_slow = 10, .p2_fast = 5 }, + .find_pll = intel_vlv_find_best_pll, +}; + +static const intel_limit_t intel_limits_vlv_dp = { + .dot = { .min = 162000, .max = 270000 }, + .vco = { .min = 5994000, .max = 4000000 }, + .n = { .min = 1, .max = 7 }, + .m = { .min = 60, .max = 300 }, /* guess */ + .m1 = { .min = 2, .max = 3 }, + .m2 = { .min = 11, .max = 156 }, + .p = { .min = 10, .max = 30 }, + .p1 = { .min = 2, .max = 3 }, + .p2 = { .dot_limit = 270000, + .p2_slow = 10, .p2_fast = 5 }, + .find_pll = intel_vlv_find_best_pll, +}; + u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg) { unsigned long flags; @@ -384,6 +431,28 @@ out_unlock: return val; } +static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, + u32 val) +{ + unsigned long flags; + + spin_lock_irqsave(&dev_priv->dpio_lock, flags); + if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) { + DRM_ERROR("DPIO idle wait timed out\n"); + goto out_unlock; + } + + I915_WRITE(DPIO_DATA, val); + I915_WRITE(DPIO_REG, reg); + I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID | + DPIO_BYTE); + if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) + DRM_ERROR("DPIO write wait timed out\n"); + +out_unlock: + spin_unlock_irqrestore(&dev_priv->dpio_lock, flags); +} + static void vlv_init_dpio(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; @@ -510,6 +579,13 @@ static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) limit = &intel_limits_pineview_lvds; else limit = &intel_limits_pineview_sdvo; + } else if (IS_VALLEYVIEW(dev)) { + if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) + limit = &intel_limits_vlv_dac; + else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) + limit = &intel_limits_vlv_hdmi; + else + limit = &intel_limits_vlv_dp; } else if (!IS_GEN2(dev)) { if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) limit = &intel_limits_i9xx_lvds; @@ -783,6 +859,83 @@ intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc, memcpy(best_clock, &clock, sizeof(intel_clock_t)); return true; } +static bool +intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc, + int target, int refclk, intel_clock_t *match_clock, + intel_clock_t *best_clock) +{ + u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2; + u32 m, n, fastclk, minvco, maxvco; + u32 updrate, minupdate, fracbits, p; + unsigned long bestppm, ppm, absppm; + int dotclk; + + dotclk = target * 1000; + + bestppm = 1000000; + ppm = 0; + absppm = 0; + + fastclk = dotclk / (2*100); + minvco = limit->vco.min; + maxvco = limit->vco.max; + updrate = 0; + minupdate = 19200; + fracbits = 1; + + n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0; + bestm1 = bestm2 = bestp1 = bestp2 = 0; + + for(n = 1; n <= ((refclk) / minupdate); n++) { + updrate = refclk / n; + for (p1 = 3; p1 > 1; p1--) { + for (p2 = 21; p2 > 0; p2--) { + if (p2 > 10) + p2 = p2 - 1; + p = p1 * p2; + + for( m1=2; m1 <= 3; m1++) { + m2 = (((2*(fastclk * p * n / m1 )) + + refclk) / (2*refclk)); + m = m1 * m2; + vco = updrate * m; + if(vco >= minvco && vco < maxvco) { + ppm = 1000000 *((vco / p) - + fastclk) / + fastclk; + absppm = (ppm > 0)? ppm: (-ppm); + if (absppm < 100 && + ((p1 * p2) > + (bestp1 * bestp2))) { + bestppm = 0; + bestn = n; + bestm1 = m1; + bestm2 = m2; + bestp1 = p1; + bestp2 = p2; + } + if (absppm < bestppm - 10) { + bestppm = absppm; + bestn = n; + bestm1 = m1; + bestm2 = m2; + bestp1 = p1; + bestp2 = p2; + } + } + } + } /* Next p2 */ + } /* Next p1 */ + }/* Next n */ + + best_clock->n = bestn; + best_clock->m1 = bestm1; + best_clock->m2 = bestm2; + best_clock->p1 = bestp1; + best_clock->p2 = bestp2; + + return true; +} static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe) { @@ -1287,7 +1440,7 @@ static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) u32 val; /* No really, not for ILK+ */ - BUG_ON(dev_priv->info->gen >= 5); + BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5); /* PLL is protected by panel, make sure we can write it */ if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) @@ -3666,13 +3819,37 @@ static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc, return display_bpc != bpc; } +static int vlv_get_refclk(struct drm_crtc *crtc) +{ + struct drm_device *dev = crtc->dev; + struct drm_i915_private *dev_priv = dev->dev_private; + int refclk = 27000; /* for DP & HDMI */ + + return 100000; /* only one validated so far */ + + if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { + refclk = 96000; + } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { + if (intel_panel_use_ssc(dev_priv)) + refclk = 100000; + else + refclk = 96000; + } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) { + refclk = 100000; + } + + return refclk; +} + static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) { struct drm_device *dev = crtc->dev; struct drm_i915_private *dev_priv = dev->dev_private; int refclk; - if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && + if (IS_VALLEYVIEW(dev)) { + refclk = vlv_get_refclk(crtc); + } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { refclk = dev_priv->lvds_ssc_freq * 1000; DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", @@ -3787,6 +3964,72 @@ static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock, I915_WRITE(LVDS, temp); } +static void vlv_update_pll(struct drm_crtc *crtc, + struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode, + intel_clock_t *clock, intel_clock_t *reduced_clock, + int refclk, int num_connectors) +{ + struct drm_device *dev = crtc->dev; + struct drm_i915_private *dev_priv = dev->dev_private; + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + int pipe = intel_crtc->pipe; + u32 dpll, mdiv, pdiv; + u32 bestn, bestm1, bestm2, bestp1, bestp2; + bool is_hdmi; + + is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI); + + bestn = clock->n; + bestm1 = clock->m1; + bestm2 = clock->m2; + bestp1 = clock->p1; + bestp2 = clock->p2; + + /* Enable DPIO clock input */ + dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | + DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; + I915_WRITE(DPLL(pipe), dpll); + POSTING_READ(DPLL(pipe)); + + mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); + mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); + mdiv |= ((bestn << DPIO_N_SHIFT)); + mdiv |= (1 << DPIO_POST_DIV_SHIFT); + mdiv |= (1 << DPIO_K_SHIFT); + mdiv |= DPIO_ENABLE_CALIBRATION; + intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv); + + intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000); + + pdiv = DPIO_REFSEL_OVERRIDE | (5 << DPIO_PLL_MODESEL_SHIFT) | + (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) | + (8 << DPIO_DRIVER_CTL_SHIFT) | (5 << DPIO_CLK_BIAS_CTL_SHIFT); + intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv); + + intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051); + + dpll |= DPLL_VCO_ENABLE; + I915_WRITE(DPLL(pipe), dpll); + POSTING_READ(DPLL(pipe)); + if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) + DRM_ERROR("DPLL %d failed to lock\n", pipe); + + if (is_hdmi) { + u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode); + + if (temp > 1) + temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; + else + temp = 0; + + I915_WRITE(DPLL_MD(pipe), temp); + POSTING_READ(DPLL_MD(pipe)); + } + + intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x641); /* ??? */ +} + static void i9xx_update_pll(struct drm_crtc *crtc, struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode, @@ -4044,6 +4287,9 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, if (IS_GEN2(dev)) i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors); + else if (IS_VALLEYVIEW(dev)) + vlv_update_pll(crtc, mode,adjusted_mode, &clock, NULL, + refclk, num_connectors); else i9xx_update_pll(crtc, mode, adjusted_mode, &clock, has_reduced_clock ? &reduced_clock : NULL, -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH 1/7] drm/i915: ValleyView mode setting limits and PLL functions 2012-06-12 21:47 ` [PATCH 1/7] drm/i915: ValleyView mode setting limits and PLL functions Jesse Barnes @ 2012-06-13 8:06 ` Daniel Vetter 2012-06-13 15:04 ` Purushothaman, Vijay A 0 siblings, 1 reply; 16+ messages in thread From: Daniel Vetter @ 2012-06-13 8:06 UTC (permalink / raw) To: Jesse Barnes; +Cc: intel-gfx On Tue, Jun 12, 2012 at 02:47:29PM -0700, Jesse Barnes wrote: > Add some VLV limit structures and update the PLL code. > > v2: resolve conflicts, Vijay to re-post with PLL valid checks and fixed limits > v3: re-add dpio write function > > Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com> > Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com> Your sob-line is missing, and iirc a few people puked over that massively-nested pll computation loop. I dunno what we've ultimately decided about it, though. -Daniel > --- > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/intel_display.c | 250 +++++++++++++++++++++++++++++++++- > 2 files changed, 249 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 7dcc04f..281446d 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -900,6 +900,7 @@ > #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ > #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ > #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ > +#define DPLL_LOCK_VLV (1<<15) > #define DPLL_INTEGRATED_CLOCK_VLV (1<<13) > > #define SRX_INDEX 0x3c4 > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 0161d94..5006928 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -98,6 +98,11 @@ intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc, > int target, int refclk, intel_clock_t *match_clock, > intel_clock_t *best_clock); > > +static bool > +intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc, > + int target, int refclk, intel_clock_t *match_clock, > + intel_clock_t *best_clock); > + > static inline u32 /* units of 100MHz */ > intel_fdi_link_freq(struct drm_device *dev) > { > @@ -359,6 +364,48 @@ static const intel_limit_t intel_limits_ironlake_display_port = { > .find_pll = intel_find_pll_ironlake_dp, > }; > > +static const intel_limit_t intel_limits_vlv_dac = { > + .dot = { .min = 25000, .max = 270000 }, > + .vco = { .min = 4000000, .max = 6000000 }, > + .n = { .min = 1, .max = 7 }, > + .m = { .min = 22, .max = 450 }, /* guess */ > + .m1 = { .min = 2, .max = 3 }, > + .m2 = { .min = 11, .max = 156 }, > + .p = { .min = 10, .max = 30 }, > + .p1 = { .min = 2, .max = 3 }, > + .p2 = { .dot_limit = 270000, > + .p2_slow = 10, .p2_fast = 5 }, > + .find_pll = intel_vlv_find_best_pll, > +}; > + > +static const intel_limit_t intel_limits_vlv_hdmi = { > + .dot = { .min = 20000, .max = 165000 }, > + .vco = { .min = 5994000, .max = 4000000 }, > + .n = { .min = 1, .max = 7 }, > + .m = { .min = 60, .max = 300 }, /* guess */ > + .m1 = { .min = 2, .max = 3 }, > + .m2 = { .min = 11, .max = 156 }, > + .p = { .min = 10, .max = 30 }, > + .p1 = { .min = 2, .max = 3 }, > + .p2 = { .dot_limit = 270000, > + .p2_slow = 10, .p2_fast = 5 }, > + .find_pll = intel_vlv_find_best_pll, > +}; > + > +static const intel_limit_t intel_limits_vlv_dp = { > + .dot = { .min = 162000, .max = 270000 }, > + .vco = { .min = 5994000, .max = 4000000 }, > + .n = { .min = 1, .max = 7 }, > + .m = { .min = 60, .max = 300 }, /* guess */ > + .m1 = { .min = 2, .max = 3 }, > + .m2 = { .min = 11, .max = 156 }, > + .p = { .min = 10, .max = 30 }, > + .p1 = { .min = 2, .max = 3 }, > + .p2 = { .dot_limit = 270000, > + .p2_slow = 10, .p2_fast = 5 }, > + .find_pll = intel_vlv_find_best_pll, > +}; > + > u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg) > { > unsigned long flags; > @@ -384,6 +431,28 @@ out_unlock: > return val; > } > > +static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, > + u32 val) > +{ > + unsigned long flags; > + > + spin_lock_irqsave(&dev_priv->dpio_lock, flags); > + if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) { > + DRM_ERROR("DPIO idle wait timed out\n"); > + goto out_unlock; > + } > + > + I915_WRITE(DPIO_DATA, val); > + I915_WRITE(DPIO_REG, reg); > + I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID | > + DPIO_BYTE); > + if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) > + DRM_ERROR("DPIO write wait timed out\n"); > + > +out_unlock: > + spin_unlock_irqrestore(&dev_priv->dpio_lock, flags); > +} > + > static void vlv_init_dpio(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = dev->dev_private; > @@ -510,6 +579,13 @@ static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) > limit = &intel_limits_pineview_lvds; > else > limit = &intel_limits_pineview_sdvo; > + } else if (IS_VALLEYVIEW(dev)) { > + if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) > + limit = &intel_limits_vlv_dac; > + else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) > + limit = &intel_limits_vlv_hdmi; > + else > + limit = &intel_limits_vlv_dp; > } else if (!IS_GEN2(dev)) { > if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) > limit = &intel_limits_i9xx_lvds; > @@ -783,6 +859,83 @@ intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc, > memcpy(best_clock, &clock, sizeof(intel_clock_t)); > return true; > } > +static bool > +intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc, > + int target, int refclk, intel_clock_t *match_clock, > + intel_clock_t *best_clock) > +{ > + u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2; > + u32 m, n, fastclk, minvco, maxvco; > + u32 updrate, minupdate, fracbits, p; > + unsigned long bestppm, ppm, absppm; > + int dotclk; > + > + dotclk = target * 1000; > + > + bestppm = 1000000; > + ppm = 0; > + absppm = 0; > + > + fastclk = dotclk / (2*100); > + minvco = limit->vco.min; > + maxvco = limit->vco.max; > + updrate = 0; > + minupdate = 19200; > + fracbits = 1; > + > + n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0; > + bestm1 = bestm2 = bestp1 = bestp2 = 0; > + > + for(n = 1; n <= ((refclk) / minupdate); n++) { > + updrate = refclk / n; > + for (p1 = 3; p1 > 1; p1--) { > + for (p2 = 21; p2 > 0; p2--) { > + if (p2 > 10) > + p2 = p2 - 1; > + p = p1 * p2; > + > + for( m1=2; m1 <= 3; m1++) { > + m2 = (((2*(fastclk * p * n / m1 )) + > + refclk) / (2*refclk)); > + m = m1 * m2; > + vco = updrate * m; > + if(vco >= minvco && vco < maxvco) { > + ppm = 1000000 *((vco / p) - > + fastclk) / > + fastclk; > + absppm = (ppm > 0)? ppm: (-ppm); > + if (absppm < 100 && > + ((p1 * p2) > > + (bestp1 * bestp2))) { > + bestppm = 0; > + bestn = n; > + bestm1 = m1; > + bestm2 = m2; > + bestp1 = p1; > + bestp2 = p2; > + } > + if (absppm < bestppm - 10) { > + bestppm = absppm; > + bestn = n; > + bestm1 = m1; > + bestm2 = m2; > + bestp1 = p1; > + bestp2 = p2; > + } > + } > + } > + } /* Next p2 */ > + } /* Next p1 */ > + }/* Next n */ > + > + best_clock->n = bestn; > + best_clock->m1 = bestm1; > + best_clock->m2 = bestm2; > + best_clock->p1 = bestp1; > + best_clock->p2 = bestp2; > + > + return true; > +} > > static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe) > { > @@ -1287,7 +1440,7 @@ static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) > u32 val; > > /* No really, not for ILK+ */ > - BUG_ON(dev_priv->info->gen >= 5); > + BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5); > > /* PLL is protected by panel, make sure we can write it */ > if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) > @@ -3666,13 +3819,37 @@ static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc, > return display_bpc != bpc; > } > > +static int vlv_get_refclk(struct drm_crtc *crtc) > +{ > + struct drm_device *dev = crtc->dev; > + struct drm_i915_private *dev_priv = dev->dev_private; > + int refclk = 27000; /* for DP & HDMI */ > + > + return 100000; /* only one validated so far */ > + > + if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { > + refclk = 96000; > + } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { > + if (intel_panel_use_ssc(dev_priv)) > + refclk = 100000; > + else > + refclk = 96000; > + } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) { > + refclk = 100000; > + } > + > + return refclk; > +} > + > static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) > { > struct drm_device *dev = crtc->dev; > struct drm_i915_private *dev_priv = dev->dev_private; > int refclk; > > - if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && > + if (IS_VALLEYVIEW(dev)) { > + refclk = vlv_get_refclk(crtc); > + } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && > intel_panel_use_ssc(dev_priv) && num_connectors < 2) { > refclk = dev_priv->lvds_ssc_freq * 1000; > DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", > @@ -3787,6 +3964,72 @@ static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock, > I915_WRITE(LVDS, temp); > } > > +static void vlv_update_pll(struct drm_crtc *crtc, > + struct drm_display_mode *mode, > + struct drm_display_mode *adjusted_mode, > + intel_clock_t *clock, intel_clock_t *reduced_clock, > + int refclk, int num_connectors) > +{ > + struct drm_device *dev = crtc->dev; > + struct drm_i915_private *dev_priv = dev->dev_private; > + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); > + int pipe = intel_crtc->pipe; > + u32 dpll, mdiv, pdiv; > + u32 bestn, bestm1, bestm2, bestp1, bestp2; > + bool is_hdmi; > + > + is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI); > + > + bestn = clock->n; > + bestm1 = clock->m1; > + bestm2 = clock->m2; > + bestp1 = clock->p1; > + bestp2 = clock->p2; > + > + /* Enable DPIO clock input */ > + dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | > + DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; > + I915_WRITE(DPLL(pipe), dpll); > + POSTING_READ(DPLL(pipe)); > + > + mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); > + mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); > + mdiv |= ((bestn << DPIO_N_SHIFT)); > + mdiv |= (1 << DPIO_POST_DIV_SHIFT); > + mdiv |= (1 << DPIO_K_SHIFT); > + mdiv |= DPIO_ENABLE_CALIBRATION; > + intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv); > + > + intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000); > + > + pdiv = DPIO_REFSEL_OVERRIDE | (5 << DPIO_PLL_MODESEL_SHIFT) | > + (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) | > + (8 << DPIO_DRIVER_CTL_SHIFT) | (5 << DPIO_CLK_BIAS_CTL_SHIFT); > + intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv); > + > + intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051); > + > + dpll |= DPLL_VCO_ENABLE; > + I915_WRITE(DPLL(pipe), dpll); > + POSTING_READ(DPLL(pipe)); > + if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) > + DRM_ERROR("DPLL %d failed to lock\n", pipe); > + > + if (is_hdmi) { > + u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode); > + > + if (temp > 1) > + temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; > + else > + temp = 0; > + > + I915_WRITE(DPLL_MD(pipe), temp); > + POSTING_READ(DPLL_MD(pipe)); > + } > + > + intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x641); /* ??? */ > +} > + > static void i9xx_update_pll(struct drm_crtc *crtc, > struct drm_display_mode *mode, > struct drm_display_mode *adjusted_mode, > @@ -4044,6 +4287,9 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, > > if (IS_GEN2(dev)) > i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors); > + else if (IS_VALLEYVIEW(dev)) > + vlv_update_pll(crtc, mode,adjusted_mode, &clock, NULL, > + refclk, num_connectors); > else > i9xx_update_pll(crtc, mode, adjusted_mode, &clock, > has_reduced_clock ? &reduced_clock : NULL, > -- > 1.7.9.5 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Mail: daniel@ffwll.ch Mobile: +41 (0)79 365 57 48 ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/7] drm/i915: ValleyView mode setting limits and PLL functions 2012-06-13 8:06 ` Daniel Vetter @ 2012-06-13 15:04 ` Purushothaman, Vijay A 0 siblings, 0 replies; 16+ messages in thread From: Purushothaman, Vijay A @ 2012-06-13 15:04 UTC (permalink / raw) To: Daniel Vetter, Jesse Barnes; +Cc: intel-gfx > -----Original Message----- > From: intel-gfx- > bounces+vijay.a.purushothaman=intel.com@lists.freedesktop.org [mailto:intel- > gfx-bounces+vijay.a.purushothaman=intel.com@lists.freedesktop.org] On > Behalf Of Daniel Vetter > Sent: Wednesday, June 13, 2012 1:37 PM > To: Jesse Barnes > Cc: intel-gfx@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH 1/7] drm/i915: ValleyView mode setting limits > and PLL functions > > On Tue, Jun 12, 2012 at 02:47:29PM -0700, Jesse Barnes wrote: > > Add some VLV limit structures and update the PLL code. > > > > v2: resolve conflicts, Vijay to re-post with PLL valid checks and > > fixed limits > > v3: re-add dpio write function > > > > Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com> > > Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com> > > Your sob-line is missing, and iirc a few people puked over that massively-nested > pll computation loop. I dunno what we've ultimately decided about it, though. > -Daniel > We decided to rework this patch once we have a platform to test. Just today I was able to bring up my system with a test bios version - Thanks to Jesse. I will post a cleaned up version of this patch soon. Thanks, Vijay > > --- > > drivers/gpu/drm/i915/i915_reg.h | 1 + > > drivers/gpu/drm/i915/intel_display.c | 250 > > +++++++++++++++++++++++++++++++++- > > 2 files changed, 249 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > > b/drivers/gpu/drm/i915/i915_reg.h index 7dcc04f..281446d 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -900,6 +900,7 @@ > > #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ > > #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ > > #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* > Pineview */ > > +#define DPLL_LOCK_VLV (1<<15) > > #define DPLL_INTEGRATED_CLOCK_VLV (1<<13) > > > > #define SRX_INDEX 0x3c4 > > diff --git a/drivers/gpu/drm/i915/intel_display.c > > b/drivers/gpu/drm/i915/intel_display.c > > index 0161d94..5006928 100644 > > --- a/drivers/gpu/drm/i915/intel_display.c > > +++ b/drivers/gpu/drm/i915/intel_display.c > > @@ -98,6 +98,11 @@ intel_find_pll_ironlake_dp(const intel_limit_t *, struct > drm_crtc *crtc, > > int target, int refclk, intel_clock_t *match_clock, > > intel_clock_t *best_clock); > > > > +static bool > > +intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc, > > + int target, int refclk, intel_clock_t *match_clock, > > + intel_clock_t *best_clock); > > + > > static inline u32 /* units of 100MHz */ intel_fdi_link_freq(struct > > drm_device *dev) { @@ -359,6 +364,48 @@ static const intel_limit_t > > intel_limits_ironlake_display_port = { > > .find_pll = intel_find_pll_ironlake_dp, }; > > > > +static const intel_limit_t intel_limits_vlv_dac = { > > + .dot = { .min = 25000, .max = 270000 }, > > + .vco = { .min = 4000000, .max = 6000000 }, > > + .n = { .min = 1, .max = 7 }, > > + .m = { .min = 22, .max = 450 }, /* guess */ > > + .m1 = { .min = 2, .max = 3 }, > > + .m2 = { .min = 11, .max = 156 }, > > + .p = { .min = 10, .max = 30 }, > > + .p1 = { .min = 2, .max = 3 }, > > + .p2 = { .dot_limit = 270000, > > + .p2_slow = 10, .p2_fast = 5 }, > > + .find_pll = intel_vlv_find_best_pll, }; > > + > > +static const intel_limit_t intel_limits_vlv_hdmi = { > > + .dot = { .min = 20000, .max = 165000 }, > > + .vco = { .min = 5994000, .max = 4000000 }, > > + .n = { .min = 1, .max = 7 }, > > + .m = { .min = 60, .max = 300 }, /* guess */ > > + .m1 = { .min = 2, .max = 3 }, > > + .m2 = { .min = 11, .max = 156 }, > > + .p = { .min = 10, .max = 30 }, > > + .p1 = { .min = 2, .max = 3 }, > > + .p2 = { .dot_limit = 270000, > > + .p2_slow = 10, .p2_fast = 5 }, > > + .find_pll = intel_vlv_find_best_pll, }; > > + > > +static const intel_limit_t intel_limits_vlv_dp = { > > + .dot = { .min = 162000, .max = 270000 }, > > + .vco = { .min = 5994000, .max = 4000000 }, > > + .n = { .min = 1, .max = 7 }, > > + .m = { .min = 60, .max = 300 }, /* guess */ > > + .m1 = { .min = 2, .max = 3 }, > > + .m2 = { .min = 11, .max = 156 }, > > + .p = { .min = 10, .max = 30 }, > > + .p1 = { .min = 2, .max = 3 }, > > + .p2 = { .dot_limit = 270000, > > + .p2_slow = 10, .p2_fast = 5 }, > > + .find_pll = intel_vlv_find_best_pll, }; > > + > > u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg) { > > unsigned long flags; > > @@ -384,6 +431,28 @@ out_unlock: > > return val; > > } > > > > +static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, > > + u32 val) > > +{ > > + unsigned long flags; > > + > > + spin_lock_irqsave(&dev_priv->dpio_lock, flags); > > + if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, > 100)) { > > + DRM_ERROR("DPIO idle wait timed out\n"); > > + goto out_unlock; > > + } > > + > > + I915_WRITE(DPIO_DATA, val); > > + I915_WRITE(DPIO_REG, reg); > > + I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID | > > + DPIO_BYTE); > > + if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, > 100)) > > + DRM_ERROR("DPIO write wait timed out\n"); > > + > > +out_unlock: > > + spin_unlock_irqrestore(&dev_priv->dpio_lock, flags); } > > + > > static void vlv_init_dpio(struct drm_device *dev) { > > struct drm_i915_private *dev_priv = dev->dev_private; @@ -510,6 > > +579,13 @@ static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int > refclk) > > limit = &intel_limits_pineview_lvds; > > else > > limit = &intel_limits_pineview_sdvo; > > + } else if (IS_VALLEYVIEW(dev)) { > > + if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) > > + limit = &intel_limits_vlv_dac; > > + else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) > > + limit = &intel_limits_vlv_hdmi; > > + else > > + limit = &intel_limits_vlv_dp; > > } else if (!IS_GEN2(dev)) { > > if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) > > limit = &intel_limits_i9xx_lvds; > > @@ -783,6 +859,83 @@ intel_find_pll_g4x_dp(const intel_limit_t *limit, struct > drm_crtc *crtc, > > memcpy(best_clock, &clock, sizeof(intel_clock_t)); > > return true; > > } > > +static bool > > +intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc, > > + int target, int refclk, intel_clock_t *match_clock, > > + intel_clock_t *best_clock) > > +{ > > + u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2; > > + u32 m, n, fastclk, minvco, maxvco; > > + u32 updrate, minupdate, fracbits, p; > > + unsigned long bestppm, ppm, absppm; > > + int dotclk; > > + > > + dotclk = target * 1000; > > + > > + bestppm = 1000000; > > + ppm = 0; > > + absppm = 0; > > + > > + fastclk = dotclk / (2*100); > > + minvco = limit->vco.min; > > + maxvco = limit->vco.max; > > + updrate = 0; > > + minupdate = 19200; > > + fracbits = 1; > > + > > + n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0; > > + bestm1 = bestm2 = bestp1 = bestp2 = 0; > > + > > + for(n = 1; n <= ((refclk) / minupdate); n++) { > > + updrate = refclk / n; > > + for (p1 = 3; p1 > 1; p1--) { > > + for (p2 = 21; p2 > 0; p2--) { > > + if (p2 > 10) > > + p2 = p2 - 1; > > + p = p1 * p2; > > + > > + for( m1=2; m1 <= 3; m1++) { > > + m2 = (((2*(fastclk * p * n / m1 )) + > > + refclk) / (2*refclk)); > > + m = m1 * m2; > > + vco = updrate * m; > > + if(vco >= minvco && vco < maxvco) { > > + ppm = 1000000 *((vco / p) - > > + fastclk) / > > + fastclk; > > + absppm = (ppm > 0)? ppm: (- > ppm); > > + if (absppm < 100 && > > + ((p1 * p2) > > > + (bestp1 * bestp2))) { > > + bestppm = 0; > > + bestn = n; > > + bestm1 = m1; > > + bestm2 = m2; > > + bestp1 = p1; > > + bestp2 = p2; > > + } > > + if (absppm < bestppm - 10) { > > + bestppm = absppm; > > + bestn = n; > > + bestm1 = m1; > > + bestm2 = m2; > > + bestp1 = p1; > > + bestp2 = p2; > > + } > > + } > > + } > > + } /* Next p2 */ > > + } /* Next p1 */ > > + }/* Next n */ > > + > > + best_clock->n = bestn; > > + best_clock->m1 = bestm1; > > + best_clock->m2 = bestm2; > > + best_clock->p1 = bestp1; > > + best_clock->p2 = bestp2; > > + > > + return true; > > +} > > > > static void ironlake_wait_for_vblank(struct drm_device *dev, int > > pipe) { @@ -1287,7 +1440,7 @@ static void intel_enable_pll(struct > > drm_i915_private *dev_priv, enum pipe pipe) > > u32 val; > > > > /* No really, not for ILK+ */ > > - BUG_ON(dev_priv->info->gen >= 5); > > + BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= > 5); > > > > /* PLL is protected by panel, make sure we can write it */ > > if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) @@ -3666,13 > > +3819,37 @@ static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc, > > return display_bpc != bpc; > > } > > > > +static int vlv_get_refclk(struct drm_crtc *crtc) { > > + struct drm_device *dev = crtc->dev; > > + struct drm_i915_private *dev_priv = dev->dev_private; > > + int refclk = 27000; /* for DP & HDMI */ > > + > > + return 100000; /* only one validated so far */ > > + > > + if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { > > + refclk = 96000; > > + } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { > > + if (intel_panel_use_ssc(dev_priv)) > > + refclk = 100000; > > + else > > + refclk = 96000; > > + } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) { > > + refclk = 100000; > > + } > > + > > + return refclk; > > +} > > + > > static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) > > { > > struct drm_device *dev = crtc->dev; > > struct drm_i915_private *dev_priv = dev->dev_private; > > int refclk; > > > > - if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && > > + if (IS_VALLEYVIEW(dev)) { > > + refclk = vlv_get_refclk(crtc); > > + } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && > > intel_panel_use_ssc(dev_priv) && num_connectors < 2) { > > refclk = dev_priv->lvds_ssc_freq * 1000; > > DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", > @@ -3787,6 > > +3964,72 @@ static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t > *clock, > > I915_WRITE(LVDS, temp); > > } > > > > +static void vlv_update_pll(struct drm_crtc *crtc, > > + struct drm_display_mode *mode, > > + struct drm_display_mode *adjusted_mode, > > + intel_clock_t *clock, intel_clock_t *reduced_clock, > > + int refclk, int num_connectors) { > > + struct drm_device *dev = crtc->dev; > > + struct drm_i915_private *dev_priv = dev->dev_private; > > + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); > > + int pipe = intel_crtc->pipe; > > + u32 dpll, mdiv, pdiv; > > + u32 bestn, bestm1, bestm2, bestp1, bestp2; > > + bool is_hdmi; > > + > > + is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI); > > + > > + bestn = clock->n; > > + bestm1 = clock->m1; > > + bestm2 = clock->m2; > > + bestp1 = clock->p1; > > + bestp2 = clock->p2; > > + > > + /* Enable DPIO clock input */ > > + dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV > | > > + DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; > > + I915_WRITE(DPLL(pipe), dpll); > > + POSTING_READ(DPLL(pipe)); > > + > > + mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & > DPIO_M2DIV_MASK)); > > + mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); > > + mdiv |= ((bestn << DPIO_N_SHIFT)); > > + mdiv |= (1 << DPIO_POST_DIV_SHIFT); > > + mdiv |= (1 << DPIO_K_SHIFT); > > + mdiv |= DPIO_ENABLE_CALIBRATION; > > + intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv); > > + > > + intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000); > > + > > + pdiv = DPIO_REFSEL_OVERRIDE | (5 << DPIO_PLL_MODESEL_SHIFT) | > > + (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) | > > + (8 << DPIO_DRIVER_CTL_SHIFT) | (5 << > DPIO_CLK_BIAS_CTL_SHIFT); > > + intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv); > > + > > + intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051); > > + > > + dpll |= DPLL_VCO_ENABLE; > > + I915_WRITE(DPLL(pipe), dpll); > > + POSTING_READ(DPLL(pipe)); > > + if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == > DPLL_LOCK_VLV), 1)) > > + DRM_ERROR("DPLL %d failed to lock\n", pipe); > > + > > + if (is_hdmi) { > > + u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode); > > + > > + if (temp > 1) > > + temp = (temp - 1) << > DPLL_MD_UDI_MULTIPLIER_SHIFT; > > + else > > + temp = 0; > > + > > + I915_WRITE(DPLL_MD(pipe), temp); > > + POSTING_READ(DPLL_MD(pipe)); > > + } > > + > > + intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x641); /* ??? */ } > > + > > static void i9xx_update_pll(struct drm_crtc *crtc, > > struct drm_display_mode *mode, > > struct drm_display_mode *adjusted_mode, @@ - > 4044,6 +4287,9 @@ > > static int i9xx_crtc_mode_set(struct drm_crtc *crtc, > > > > if (IS_GEN2(dev)) > > i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors); > > + else if (IS_VALLEYVIEW(dev)) > > + vlv_update_pll(crtc, mode,adjusted_mode, &clock, NULL, > > + refclk, num_connectors); > > else > > i9xx_update_pll(crtc, mode, adjusted_mode, &clock, > > has_reduced_clock ? &reduced_clock : NULL, > > -- > > 1.7.9.5 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Daniel Vetter > Mail: daniel@ffwll.ch > Mobile: +41 (0)79 365 57 48 > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 2/7] drm/i915: Enable DP panel power sequencing for ValleyView 2012-06-12 21:47 Remaining VLV patches Jesse Barnes 2012-06-12 21:47 ` [PATCH 1/7] drm/i915: ValleyView mode setting limits and PLL functions Jesse Barnes @ 2012-06-12 21:47 ` Jesse Barnes 2012-06-13 8:05 ` Daniel Vetter 2012-06-12 21:47 ` [PATCH 3/7] drm/i915: add ValleyView specific CRT detect function Jesse Barnes ` (4 subsequent siblings) 6 siblings, 1 reply; 16+ messages in thread From: Jesse Barnes @ 2012-06-12 21:47 UTC (permalink / raw) To: intel-gfx; +Cc: Beeresh G From: Shobhit Kumar <shobhit.kumar@intel.com> VLV supports two dp panels, there are two set of panel power sequence registers which needed to be programmed based on the configured pipe. This patch add supports for the same Acked-by: Acked-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Beeresh G <beeresh.g@intel.com> Reviewed-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com> Reviewed-by: Jesse Barnes <jesse.barnes@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> --- drivers/gpu/drm/i915/i915_reg.h | 12 ++++++++++++ drivers/gpu/drm/i915/intel_dp.c | 8 +++++++- 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 281446d..a9e9d92 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3854,6 +3854,18 @@ #define BLC_PWM_PCH_CTL2 0xc8254 +#define PIPEA_PP_STATUS 0x61200 +#define PIPEA_PP_CONTROL 0x61204 +#define PIPEA_PP_ON_DELAYS 0x61208 +#define PIPEA_PP_OFF_DELAYS 0x6120c +#define PIPEA_PP_DIVISOR 0x61210 + +#define PIPEB_PP_STATUS 0x61300 +#define PIPEB_PP_CONTROL 0x61304 +#define PIPEB_PP_ON_DELAYS 0x61308 +#define PIPEB_PP_OFF_DELAYS 0x6130c +#define PIPEB_PP_DIVISOR 0x61310 + #define PCH_PP_STATUS 0xc7200 #define PCH_PP_CONTROL 0xc7204 #define PANEL_UNLOCK_REGS (0xabcd << 16) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 6538c46..d59af24 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -342,7 +342,13 @@ static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp) struct drm_device *dev = intel_dp->base.base.dev; struct drm_i915_private *dev_priv = dev->dev_private; - return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0; + if (IS_VALLEYVIEW(dev)) { + if (I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) + return (I915_READ(PIPEB_PP_STATUS) & PP_ON) != 0; + else + return (I915_READ(PIPEA_PP_STATUS) & PP_ON) != 0; + } else + return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0; } static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp) -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH 2/7] drm/i915: Enable DP panel power sequencing for ValleyView 2012-06-12 21:47 ` [PATCH 2/7] drm/i915: Enable DP panel power sequencing for ValleyView Jesse Barnes @ 2012-06-13 8:05 ` Daniel Vetter 2012-06-13 16:10 ` Shobhit Kumar 0 siblings, 1 reply; 16+ messages in thread From: Daniel Vetter @ 2012-06-13 8:05 UTC (permalink / raw) To: Jesse Barnes; +Cc: Beeresh G, intel-gfx On Tue, Jun 12, 2012 at 02:47:30PM -0700, Jesse Barnes wrote: > From: Shobhit Kumar <shobhit.kumar@intel.com> > > VLV supports two dp panels, there are two set of panel power sequence > registers which needed to be programmed based on the configured > pipe. This patch add supports for the same > > Acked-by: Acked-by: Ben Widawsky <ben@bwidawsk.net> > Signed-off-by: Beeresh G <beeresh.g@intel.com> > Reviewed-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com> > Reviewed-by: Jesse Barnes <jesse.barnes@intel.com> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> > --- > drivers/gpu/drm/i915/i915_reg.h | 12 ++++++++++++ > drivers/gpu/drm/i915/intel_dp.c | 8 +++++++- > 2 files changed, 19 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 281446d..a9e9d92 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -3854,6 +3854,18 @@ > > #define BLC_PWM_PCH_CTL2 0xc8254 > > +#define PIPEA_PP_STATUS 0x61200 > +#define PIPEA_PP_CONTROL 0x61204 > +#define PIPEA_PP_ON_DELAYS 0x61208 > +#define PIPEA_PP_OFF_DELAYS 0x6120c > +#define PIPEA_PP_DIVISOR 0x61210 > + > +#define PIPEB_PP_STATUS 0x61300 > +#define PIPEB_PP_CONTROL 0x61304 > +#define PIPEB_PP_ON_DELAYS 0x61308 > +#define PIPEB_PP_OFF_DELAYS 0x6130c > +#define PIPEB_PP_DIVISOR 0x61310 > + > #define PCH_PP_STATUS 0xc7200 > #define PCH_PP_CONTROL 0xc7204 > #define PANEL_UNLOCK_REGS (0xabcd << 16) > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index 6538c46..d59af24 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -342,7 +342,13 @@ static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp) > struct drm_device *dev = intel_dp->base.base.dev; > struct drm_i915_private *dev_priv = dev->dev_private; > > - return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0; > + if (IS_VALLEYVIEW(dev)) { > + if (I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) > + return (I915_READ(PIPEB_PP_STATUS) & PP_ON) != 0; > + else > + return (I915_READ(PIPEA_PP_STATUS) & PP_ON) != 0; > + } else > + return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0; > } > > static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp) ... I have a feeling that this patch should be much longer ;-) -Daniel -- Daniel Vetter Mail: daniel@ffwll.ch Mobile: +41 (0)79 365 57 48 ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 2/7] drm/i915: Enable DP panel power sequencing for ValleyView 2012-06-13 8:05 ` Daniel Vetter @ 2012-06-13 16:10 ` Shobhit Kumar 0 siblings, 0 replies; 16+ messages in thread From: Shobhit Kumar @ 2012-06-13 16:10 UTC (permalink / raw) To: Daniel Vetter; +Cc: Beeresh G, intel-gfx On 06/13/2012 01:35 PM, Daniel Vetter wrote: > On Tue, Jun 12, 2012 at 02:47:30PM -0700, Jesse Barnes wrote: >> From: Shobhit Kumar<shobhit.kumar@intel.com> >> >> VLV supports two dp panels, there are two set of panel power sequence >> registers which needed to be programmed based on the configured >> pipe. This patch add supports for the same >> >> Acked-by: Acked-by: Ben Widawsky<ben@bwidawsk.net> >> Signed-off-by: Beeresh G<beeresh.g@intel.com> >> Reviewed-by: Vijay Purushothaman<vijay.a.purushothaman@intel.com> >> Reviewed-by: Jesse Barnes<jesse.barnes@intel.com> >> Signed-off-by: Jesse Barnes<jbarnes@virtuousgeek.org> >> --- >> drivers/gpu/drm/i915/i915_reg.h | 12 ++++++++++++ >> drivers/gpu/drm/i915/intel_dp.c | 8 +++++++- >> 2 files changed, 19 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h >> index 281446d..a9e9d92 100644 >> --- a/drivers/gpu/drm/i915/i915_reg.h >> +++ b/drivers/gpu/drm/i915/i915_reg.h >> @@ -3854,6 +3854,18 @@ >> >> #define BLC_PWM_PCH_CTL2 0xc8254 >> >> +#define PIPEA_PP_STATUS 0x61200 >> +#define PIPEA_PP_CONTROL 0x61204 >> +#define PIPEA_PP_ON_DELAYS 0x61208 >> +#define PIPEA_PP_OFF_DELAYS 0x6120c >> +#define PIPEA_PP_DIVISOR 0x61210 >> + >> +#define PIPEB_PP_STATUS 0x61300 >> +#define PIPEB_PP_CONTROL 0x61304 >> +#define PIPEB_PP_ON_DELAYS 0x61308 >> +#define PIPEB_PP_OFF_DELAYS 0x6130c >> +#define PIPEB_PP_DIVISOR 0x61310 >> + >> #define PCH_PP_STATUS 0xc7200 >> #define PCH_PP_CONTROL 0xc7204 >> #define PANEL_UNLOCK_REGS (0xabcd<< 16) >> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c >> index 6538c46..d59af24 100644 >> --- a/drivers/gpu/drm/i915/intel_dp.c >> +++ b/drivers/gpu/drm/i915/intel_dp.c >> @@ -342,7 +342,13 @@ static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp) >> struct drm_device *dev = intel_dp->base.base.dev; >> struct drm_i915_private *dev_priv = dev->dev_private; >> >> - return (I915_READ(PCH_PP_STATUS)& PP_ON) != 0; >> + if (IS_VALLEYVIEW(dev)) { >> + if (I915_READ(intel_dp->output_reg)& DP_PIPEB_SELECT) >> + return (I915_READ(PIPEB_PP_STATUS)& PP_ON) != 0; >> + else >> + return (I915_READ(PIPEA_PP_STATUS)& PP_ON) != 0; >> + } else >> + return (I915_READ(PCH_PP_STATUS)& PP_ON) != 0; >> } >> >> static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp) > > ... I have a feeling that this patch should be much longer ;-) > -Daniel Yeah :) This patch was just to just add the new registers for VLV with the intention of adding incremental patches for enabling the feature. Somehow this did not go beyond what it is right now. Will be sending more patches as part of the DP/eDP enabling effort on VLV Regards Shobhit ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 3/7] drm/i915: add ValleyView specific CRT detect function 2012-06-12 21:47 Remaining VLV patches Jesse Barnes 2012-06-12 21:47 ` [PATCH 1/7] drm/i915: ValleyView mode setting limits and PLL functions Jesse Barnes 2012-06-12 21:47 ` [PATCH 2/7] drm/i915: Enable DP panel power sequencing for ValleyView Jesse Barnes @ 2012-06-12 21:47 ` Jesse Barnes 2012-06-12 21:47 ` [PATCH 4/7] drm/i915: add HDMI and DP port enumeration on ValleyView Jesse Barnes ` (3 subsequent siblings) 6 siblings, 0 replies; 16+ messages in thread From: Jesse Barnes @ 2012-06-12 21:47 UTC (permalink / raw) To: intel-gfx Might be able to merge this back in at some point, but we're seeing bugs with ADPA based detection, so keep it separate for now with explicit hotplug trigger usage. v2: drop superfluous debug message v3: comment forced detection, need to debug (Eugeni) Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> --- drivers/gpu/drm/i915/intel_crt.c | 39 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c index 75a70c4..1333a65 100644 --- a/drivers/gpu/drm/i915/intel_crt.c +++ b/drivers/gpu/drm/i915/intel_crt.c @@ -230,6 +230,42 @@ static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) return ret; } +static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) +{ + struct drm_device *dev = connector->dev; + struct drm_i915_private *dev_priv = dev->dev_private; + u32 adpa; + bool ret; + u32 save_adpa; + + save_adpa = adpa = I915_READ(ADPA); + DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); + + adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; + + I915_WRITE(ADPA, adpa); + + if (wait_for((I915_READ(ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, + 1000)) { + DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); + I915_WRITE(ADPA, save_adpa); + } + + /* Check the status to see if both blue and green are on now */ + adpa = I915_READ(ADPA); + if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) + ret = true; + else + ret = false; + + DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret); + + /* FIXME: debug force function and remove */ + ret = true; + + return ret; +} + /** * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence. * @@ -249,6 +285,9 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector) if (HAS_PCH_SPLIT(dev)) return intel_ironlake_crt_detect_hotplug(connector); + if (IS_VALLEYVIEW(dev)) + return valleyview_crt_detect_hotplug(connector); + /* * On 4 series desktop, CRT detect sequence need to be done twice * to get a reliable result. -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 4/7] drm/i915: add HDMI and DP port enumeration on ValleyView 2012-06-12 21:47 Remaining VLV patches Jesse Barnes ` (2 preceding siblings ...) 2012-06-12 21:47 ` [PATCH 3/7] drm/i915: add ValleyView specific CRT detect function Jesse Barnes @ 2012-06-12 21:47 ` Jesse Barnes 2012-06-13 8:11 ` Daniel Vetter 2012-06-12 21:47 ` [PATCH 5/7] drm/i915: access VLV regs through read/write switch Jesse Barnes ` (2 subsequent siblings) 6 siblings, 1 reply; 16+ messages in thread From: Jesse Barnes @ 2012-06-12 21:47 UTC (permalink / raw) To: intel-gfx ValleyView is similar to IbexPeak here, but with different register offsets. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> --- drivers/gpu/drm/i915/intel_display.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 5006928..2a677f8 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -6772,7 +6772,24 @@ static void intel_setup_outputs(struct drm_device *dev) if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED)) intel_dp_init(dev, PCH_DP_D); + } else if (IS_VALLEYVIEW(dev)) { + int found; + + if (I915_READ(VLV_HDMIB) & PORT_DETECTED) { + /* SDVOB multiplex with HDMIB */ + found = intel_sdvo_init(dev, VLV_HDMIB, true); + if (!found) + intel_hdmi_init(dev, VLV_HDMIB); + if (!found && (I915_READ(DP_B) & DP_DETECTED)) + intel_dp_init(dev, DP_B); + } + + if (I915_READ(SDVOC) & PORT_DETECTED) + intel_hdmi_init(dev, SDVOC); + /* Shares lanes with HDMI on SDVOC */ + if (!dpd_is_edp && (I915_READ(DP_C) & DP_DETECTED)) + intel_dp_init(dev, DP_C); } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { bool found = false; -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH 4/7] drm/i915: add HDMI and DP port enumeration on ValleyView 2012-06-12 21:47 ` [PATCH 4/7] drm/i915: add HDMI and DP port enumeration on ValleyView Jesse Barnes @ 2012-06-13 8:11 ` Daniel Vetter 2012-06-13 17:19 ` Jesse Barnes 0 siblings, 1 reply; 16+ messages in thread From: Daniel Vetter @ 2012-06-13 8:11 UTC (permalink / raw) To: Jesse Barnes; +Cc: intel-gfx On Tue, Jun 12, 2012 at 02:47:32PM -0700, Jesse Barnes wrote: > ValleyView is similar to IbexPeak here, but with different register > offsets. > > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> > --- > drivers/gpu/drm/i915/intel_display.c | 17 +++++++++++++++++ > 1 file changed, 17 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 5006928..2a677f8 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -6772,7 +6772,24 @@ static void intel_setup_outputs(struct drm_device *dev) > > if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED)) > intel_dp_init(dev, PCH_DP_D); > + } else if (IS_VALLEYVIEW(dev)) { > + int found; > + > + if (I915_READ(VLV_HDMIB) & PORT_DETECTED) { VLV_HDMIB == SDVOB, which royally confused me, especially since below you use SDVOC for VLV_HDMC. Yeah, pre-pch_split we just use the SDVO names for the HDMI registers. I guess I'll just wait for Paulo to clean up this mess. > + /* SDVOB multiplex with HDMIB */ > + found = intel_sdvo_init(dev, VLV_HDMIB, true); > + if (!found) > + intel_hdmi_init(dev, VLV_HDMIB); > + if (!found && (I915_READ(DP_B) & DP_DETECTED)) > + intel_dp_init(dev, DP_B); > + } > + > + if (I915_READ(SDVOC) & PORT_DETECTED) > + intel_hdmi_init(dev, SDVOC); > > + /* Shares lanes with HDMI on SDVOC */ > + if (!dpd_is_edp && (I915_READ(DP_C) & DP_DETECTED)) > + intel_dp_init(dev, DP_C); This !dpd_is_edp check here looks fishy for DP_C, copy&paste fail? Also, I wonder where you set up the vlv eDP panels? > } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { > bool found = false; > > -- > 1.7.9.5 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Mail: daniel@ffwll.ch Mobile: +41 (0)79 365 57 48 ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 4/7] drm/i915: add HDMI and DP port enumeration on ValleyView 2012-06-13 8:11 ` Daniel Vetter @ 2012-06-13 17:19 ` Jesse Barnes 0 siblings, 0 replies; 16+ messages in thread From: Jesse Barnes @ 2012-06-13 17:19 UTC (permalink / raw) To: Daniel Vetter; +Cc: intel-gfx On Wed, 13 Jun 2012 10:11:09 +0200 Daniel Vetter <daniel@ffwll.ch> wrote: > On Tue, Jun 12, 2012 at 02:47:32PM -0700, Jesse Barnes wrote: > > ValleyView is similar to IbexPeak here, but with different register > > offsets. > > > > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> > > --- > > drivers/gpu/drm/i915/intel_display.c | 17 +++++++++++++++++ > > 1 file changed, 17 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > > index 5006928..2a677f8 100644 > > --- a/drivers/gpu/drm/i915/intel_display.c > > +++ b/drivers/gpu/drm/i915/intel_display.c > > @@ -6772,7 +6772,24 @@ static void intel_setup_outputs(struct drm_device *dev) > > > > if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED)) > > intel_dp_init(dev, PCH_DP_D); > > + } else if (IS_VALLEYVIEW(dev)) { > > + int found; > > + > > + if (I915_READ(VLV_HDMIB) & PORT_DETECTED) { > > VLV_HDMIB == SDVOB, which royally confused me, especially since below you > use SDVOC for VLV_HDMC. Yeah, pre-pch_split we just use the SDVO names for > the HDMI registers. I guess I'll just wait for Paulo to clean up this > mess. I dropped this and just use SDVOB now; the docs look the same as Cantiga, so we may as well keep it looking similar. > > > + /* SDVOB multiplex with HDMIB */ > > + found = intel_sdvo_init(dev, VLV_HDMIB, true); > > + if (!found) > > + intel_hdmi_init(dev, VLV_HDMIB); > > + if (!found && (I915_READ(DP_B) & DP_DETECTED)) > > + intel_dp_init(dev, DP_B); > > + } > > + > > + if (I915_READ(SDVOC) & PORT_DETECTED) > > + intel_hdmi_init(dev, SDVOC); > > > > + /* Shares lanes with HDMI on SDVOC */ > > + if (!dpd_is_edp && (I915_READ(DP_C) & DP_DETECTED)) > > + intel_dp_init(dev, DP_C); > > This !dpd_is_edp check here looks fishy for DP_C, copy&paste fail? Ah yeah, merge error on my part. Fixed. > Also, I wonder where you set up the vlv eDP panels? That'll be coming with Shobit's eDP patchset. Thanks, -- Jesse Barnes, Intel Open Source Technology Center ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 5/7] drm/i915: access VLV regs through read/write switch 2012-06-12 21:47 Remaining VLV patches Jesse Barnes ` (3 preceding siblings ...) 2012-06-12 21:47 ` [PATCH 4/7] drm/i915: add HDMI and DP port enumeration on ValleyView Jesse Barnes @ 2012-06-12 21:47 ` Jesse Barnes 2012-06-13 8:14 ` Daniel Vetter 2012-06-12 21:47 ` [PATCH 6/7] drm/i915: bind driver to ValleyView chipsets Jesse Barnes 2012-06-12 21:47 ` [PATCH 7/7] drm/i915: VLV VGA port only handles on & off, like PCH VGA Jesse Barnes 6 siblings, 1 reply; 16+ messages in thread From: Jesse Barnes @ 2012-06-12 21:47 UTC (permalink / raw) To: intel-gfx Since the offsets have all moved around. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> --- drivers/gpu/drm/i915/i915_drv.c | 80 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 78 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 238a521..747dc8d 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1144,6 +1144,77 @@ MODULE_LICENSE("GPL and additional rights"); ((reg) != FORCEWAKE)) && \ (!IS_VALLEYVIEW((dev_priv)->dev)) +static bool IS_DISPLAYREG(u32 reg) +{ + if (reg >= RENDER_RING_BASE && + reg < RENDER_RING_BASE + 0xff) + return false; + if (reg >= GEN6_BSD_RING_BASE && + reg < GEN6_BSD_RING_BASE + 0xff) + return false; + if (reg >= BLT_RING_BASE && + reg < BLT_RING_BASE + 0xff) + return false; + + if (reg == PGTBL_ER) + return false; + + if (reg >= IPEIR_I965 && + reg < HWSTAM) + return false; + + if (reg == MI_MODE) + return false; + + if (reg == GFX_MODE_GEN7) + return false; + + if (reg == RENDER_HWS_PGA_GEN7 || + reg == BSD_HWS_PGA_GEN7 || + reg == BLT_HWS_PGA_GEN7) + return false; + + if (reg == GEN6_BSD_SLEEP_PSMI_CONTROL || + reg == GEN6_BSD_RNCID) + return false; + + if (reg == GEN6_BLITTER_ECOSKPD) + return false; + + if (reg >= 0x4000c && + reg <= 0x4002c) + return false; + + if (reg >= 0x4f000 && + reg <= 0x4f08f) + return false; + + if (reg >= 0x4f100 && + reg <= 0x4f11f) + return false; + + if (reg >= VLV_MASTER_IER && + reg <= GEN6_PMIER) + return false; + + if (reg >= FENCE_REG_SANDYBRIDGE_0 && + reg < (FENCE_REG_SANDYBRIDGE_0 + (16*8))) + return false; + + if (reg >= VLV_IIR_RW && + reg <= VLV_ISR) + return false; + + if (reg == FORCEWAKE_VLV || + reg == FORCEWAKE_ACK_VLV) + return false; + + if (reg == GEN6_GDRST) + return false; + + return true; +} + #define __i915_read(x, y) \ u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ u##x val = 0; \ @@ -1156,6 +1227,8 @@ u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ if (dev_priv->forcewake_count == 0) \ dev_priv->display.force_wake_put(dev_priv); \ spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \ + } else if (IS_DISPLAYREG(reg) && IS_VALLEYVIEW(dev_priv->dev)) { \ + val = read##y(dev_priv->regs + reg + 0x180000); \ } else { \ val = read##y(dev_priv->regs + reg); \ } \ @@ -1175,8 +1248,11 @@ void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \ trace_i915_reg_rw(true, reg, val, sizeof(val)); \ if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ - } \ - write##y(val, dev_priv->regs + reg); \ + } else if (IS_DISPLAYREG(reg) && IS_VALLEYVIEW(dev_priv->dev)) { \ + write##y(val, dev_priv->regs + reg + 0x180000); \ + } else { \ + write##y(val, dev_priv->regs + reg); \ + } \ if (unlikely(__fifo_ret)) { \ gen6_gt_check_fifodbg(dev_priv); \ } \ -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH 5/7] drm/i915: access VLV regs through read/write switch 2012-06-12 21:47 ` [PATCH 5/7] drm/i915: access VLV regs through read/write switch Jesse Barnes @ 2012-06-13 8:14 ` Daniel Vetter 0 siblings, 0 replies; 16+ messages in thread From: Daniel Vetter @ 2012-06-13 8:14 UTC (permalink / raw) To: Jesse Barnes; +Cc: intel-gfx On Tue, Jun 12, 2012 at 02:47:33PM -0700, Jesse Barnes wrote: > Since the offsets have all moved around. > > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Oh dear, I guess we'll just life with ugly then. Just to check so that we can still sensibly move forward with register base addresses: Would if (reg >= 0x180000) return false; in that function be enough to prevent this hack from adjusting display registers that have already been adjusted for the new vlv display base address? If so, please add that check so that we can move things to something slightly more sensible piece-by-piece. -Daniel > --- > drivers/gpu/drm/i915/i915_drv.c | 80 ++++++++++++++++++++++++++++++++++++++- > 1 file changed, 78 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c > index 238a521..747dc8d 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -1144,6 +1144,77 @@ MODULE_LICENSE("GPL and additional rights"); > ((reg) != FORCEWAKE)) && \ > (!IS_VALLEYVIEW((dev_priv)->dev)) > > +static bool IS_DISPLAYREG(u32 reg) > +{ > + if (reg >= RENDER_RING_BASE && > + reg < RENDER_RING_BASE + 0xff) > + return false; > + if (reg >= GEN6_BSD_RING_BASE && > + reg < GEN6_BSD_RING_BASE + 0xff) > + return false; > + if (reg >= BLT_RING_BASE && > + reg < BLT_RING_BASE + 0xff) > + return false; > + > + if (reg == PGTBL_ER) > + return false; > + > + if (reg >= IPEIR_I965 && > + reg < HWSTAM) > + return false; > + > + if (reg == MI_MODE) > + return false; > + > + if (reg == GFX_MODE_GEN7) > + return false; > + > + if (reg == RENDER_HWS_PGA_GEN7 || > + reg == BSD_HWS_PGA_GEN7 || > + reg == BLT_HWS_PGA_GEN7) > + return false; > + > + if (reg == GEN6_BSD_SLEEP_PSMI_CONTROL || > + reg == GEN6_BSD_RNCID) > + return false; > + > + if (reg == GEN6_BLITTER_ECOSKPD) > + return false; > + > + if (reg >= 0x4000c && > + reg <= 0x4002c) > + return false; > + > + if (reg >= 0x4f000 && > + reg <= 0x4f08f) > + return false; > + > + if (reg >= 0x4f100 && > + reg <= 0x4f11f) > + return false; > + > + if (reg >= VLV_MASTER_IER && > + reg <= GEN6_PMIER) > + return false; > + > + if (reg >= FENCE_REG_SANDYBRIDGE_0 && > + reg < (FENCE_REG_SANDYBRIDGE_0 + (16*8))) > + return false; > + > + if (reg >= VLV_IIR_RW && > + reg <= VLV_ISR) > + return false; > + > + if (reg == FORCEWAKE_VLV || > + reg == FORCEWAKE_ACK_VLV) > + return false; > + > + if (reg == GEN6_GDRST) > + return false; > + > + return true; > +} > + > #define __i915_read(x, y) \ > u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ > u##x val = 0; \ > @@ -1156,6 +1227,8 @@ u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ > if (dev_priv->forcewake_count == 0) \ > dev_priv->display.force_wake_put(dev_priv); \ > spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \ > + } else if (IS_DISPLAYREG(reg) && IS_VALLEYVIEW(dev_priv->dev)) { \ > + val = read##y(dev_priv->regs + reg + 0x180000); \ > } else { \ > val = read##y(dev_priv->regs + reg); \ > } \ > @@ -1175,8 +1248,11 @@ void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \ > trace_i915_reg_rw(true, reg, val, sizeof(val)); \ > if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ > __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ > - } \ > - write##y(val, dev_priv->regs + reg); \ > + } else if (IS_DISPLAYREG(reg) && IS_VALLEYVIEW(dev_priv->dev)) { \ > + write##y(val, dev_priv->regs + reg + 0x180000); \ > + } else { \ > + write##y(val, dev_priv->regs + reg); \ > + } \ > if (unlikely(__fifo_ret)) { \ > gen6_gt_check_fifodbg(dev_priv); \ > } \ > -- > 1.7.9.5 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Mail: daniel@ffwll.ch Mobile: +41 (0)79 365 57 48 ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 6/7] drm/i915: bind driver to ValleyView chipsets 2012-06-12 21:47 Remaining VLV patches Jesse Barnes ` (4 preceding siblings ...) 2012-06-12 21:47 ` [PATCH 5/7] drm/i915: access VLV regs through read/write switch Jesse Barnes @ 2012-06-12 21:47 ` Jesse Barnes 2012-06-12 21:47 ` [PATCH 7/7] drm/i915: VLV VGA port only handles on & off, like PCH VGA Jesse Barnes 6 siblings, 0 replies; 16+ messages in thread From: Jesse Barnes @ 2012-06-12 21:47 UTC (permalink / raw) To: intel-gfx With the code in place, we can bind the driver, should make bisect possible. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> --- drivers/gpu/drm/i915/i915_drv.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 747dc8d..8bdb000 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -352,6 +352,9 @@ static const struct pci_device_id pciidlist[] = { /* aka */ INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */ INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */ INTEL_VGA_DEVICE(0x0c16, &intel_haswell_d_info), /* SDV */ + INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info), + INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info), + INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info), {0, 0, 0} }; -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 7/7] drm/i915: VLV VGA port only handles on & off, like PCH VGA 2012-06-12 21:47 Remaining VLV patches Jesse Barnes ` (5 preceding siblings ...) 2012-06-12 21:47 ` [PATCH 6/7] drm/i915: bind driver to ValleyView chipsets Jesse Barnes @ 2012-06-12 21:47 ` Jesse Barnes 2012-06-13 8:36 ` Daniel Vetter 6 siblings, 1 reply; 16+ messages in thread From: Jesse Barnes @ 2012-06-12 21:47 UTC (permalink / raw) To: intel-gfx Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> --- drivers/gpu/drm/i915/intel_crt.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c index 1333a65..ac62f24 100644 --- a/drivers/gpu/drm/i915/intel_crt.c +++ b/drivers/gpu/drm/i915/intel_crt.c @@ -88,6 +88,9 @@ static void gmch_crt_dpms(struct drm_encoder *encoder, int mode) temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE); temp &= ~ADPA_DAC_ENABLE; + if (IS_VALLEYVIEW(dev) && mode != DRM_MODE_DPMS_ON) + mode = DRM_MODE_DPMS_OFF; + switch (mode) { case DRM_MODE_DPMS_ON: temp |= ADPA_DAC_ENABLE; -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH 7/7] drm/i915: VLV VGA port only handles on & off, like PCH VGA 2012-06-12 21:47 ` [PATCH 7/7] drm/i915: VLV VGA port only handles on & off, like PCH VGA Jesse Barnes @ 2012-06-13 8:36 ` Daniel Vetter 0 siblings, 0 replies; 16+ messages in thread From: Daniel Vetter @ 2012-06-13 8:36 UTC (permalink / raw) To: Jesse Barnes; +Cc: intel-gfx On Tue, Jun 12, 2012 at 02:47:35PM -0700, Jesse Barnes wrote: > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Meh, nicely splitting out pch_crt_dpms and now this. Disappointing ;-) But I guess we've reached the limit of the dpms helpers anyway, and with a few changes in drm_crtc_helper.c to fix up a few past mistakes we can make the dpms handling part fully optional and replace it with something else that fits us better. Sometimes, maybe. -Daniel > --- > drivers/gpu/drm/i915/intel_crt.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c > index 1333a65..ac62f24 100644 > --- a/drivers/gpu/drm/i915/intel_crt.c > +++ b/drivers/gpu/drm/i915/intel_crt.c > @@ -88,6 +88,9 @@ static void gmch_crt_dpms(struct drm_encoder *encoder, int mode) > temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE); > temp &= ~ADPA_DAC_ENABLE; > > + if (IS_VALLEYVIEW(dev) && mode != DRM_MODE_DPMS_ON) > + mode = DRM_MODE_DPMS_OFF; > + > switch (mode) { > case DRM_MODE_DPMS_ON: > temp |= ADPA_DAC_ENABLE; > -- > 1.7.9.5 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Mail: daniel@ffwll.ch Mobile: +41 (0)79 365 57 48 ^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2012-06-13 17:19 UTC | newest] Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2012-06-12 21:47 Remaining VLV patches Jesse Barnes 2012-06-12 21:47 ` [PATCH 1/7] drm/i915: ValleyView mode setting limits and PLL functions Jesse Barnes 2012-06-13 8:06 ` Daniel Vetter 2012-06-13 15:04 ` Purushothaman, Vijay A 2012-06-12 21:47 ` [PATCH 2/7] drm/i915: Enable DP panel power sequencing for ValleyView Jesse Barnes 2012-06-13 8:05 ` Daniel Vetter 2012-06-13 16:10 ` Shobhit Kumar 2012-06-12 21:47 ` [PATCH 3/7] drm/i915: add ValleyView specific CRT detect function Jesse Barnes 2012-06-12 21:47 ` [PATCH 4/7] drm/i915: add HDMI and DP port enumeration on ValleyView Jesse Barnes 2012-06-13 8:11 ` Daniel Vetter 2012-06-13 17:19 ` Jesse Barnes 2012-06-12 21:47 ` [PATCH 5/7] drm/i915: access VLV regs through read/write switch Jesse Barnes 2012-06-13 8:14 ` Daniel Vetter 2012-06-12 21:47 ` [PATCH 6/7] drm/i915: bind driver to ValleyView chipsets Jesse Barnes 2012-06-12 21:47 ` [PATCH 7/7] drm/i915: VLV VGA port only handles on & off, like PCH VGA Jesse Barnes 2012-06-13 8:36 ` Daniel Vetter
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