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From: Andi Kleen <andi@firstfloor.org>
To: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Andi Kleen <andi@firstfloor.org>,
	x86@kernel.org, linux-kernel@vger.kernel.org,
	Andi Kleen <ak@linux.intel.com>
Subject: Re: [PATCH 1/5] perf, x86: Improve basic Ivy Bridge support v3
Date: Mon, 2 Jul 2012 21:58:55 +0200	[thread overview]
Message-ID: <20120702195855.GH11413@one.firstfloor.org> (raw)
In-Reply-To: <1341257194.23484.16.camel@twins>

On Mon, Jul 02, 2012 at 09:26:34PM +0200, Peter Zijlstra wrote:
> On Mon, 2012-07-02 at 11:43 -0700, Andi Kleen wrote:
> > - As Stephane pointed out .code=0xb1, .umask=0x01 is gone from the
> > event list,
> > so don't do a generic backend stall event on IvyBridge. 
> 
> 325462-043US, May 2012:
> 
> Page 3135, Table 19-2. Non-Architectural Performance Events In the
> Processor Core of Third Generation Intel Core i7, i5, i3 Processors

The table is outdated.

But if you insist can readd it. It's just unlikely to work.

-Andi

  reply	other threads:[~2012-07-02 19:59 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-07-02 18:43 Updated and combined Sandy Bridge/Ivy Bridge perf patchkits Andi Kleen
2012-07-02 18:43 ` [PATCH 1/5] perf, x86: Improve basic Ivy Bridge support v3 Andi Kleen
2012-07-02 19:26   ` Peter Zijlstra
2012-07-02 19:58     ` Andi Kleen [this message]
2012-07-02 20:18       ` Peter Zijlstra
2012-07-02 18:43 ` [PATCH 2/5] perf, x86: Enable PDIR precise instruction profiling on IvyBridge Andi Kleen
2012-07-02 19:18   ` Peter Zijlstra
2012-07-02 19:57     ` Andi Kleen
2012-07-02 20:22       ` Peter Zijlstra
2012-07-02 21:00         ` Andi Kleen
2012-07-02 21:36           ` Peter Zijlstra
2012-07-02 21:57             ` Andi Kleen
2012-07-02 23:13               ` Stephane Eranian
2012-07-03  4:04                 ` Andi Kleen
2012-07-05 15:45                   ` Stephane Eranian
2012-07-05 17:26                     ` Andi Kleen
2012-07-06  1:04                       ` Stephane Eranian
2012-07-02 18:43 ` [PATCH 3/5] x86: Do microcode updates at CPU_STARTING, not CPU_ONLINE v2 Andi Kleen
2012-07-02 18:43 ` [PATCH 4/5] perf, x86: check ucode before disabling PEBS on SandyBridge v4 Andi Kleen
2012-07-02 18:43 ` [PATCH 5/5] perf, x86: Spell Romley correctly Andi Kleen

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