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From: Stephane Eranian <eranian@google.com>
To: Andi Kleen <ak@linux.intel.com>
Cc: Andi Kleen <andi@firstfloor.org>,
	Peter Zijlstra <a.p.zijlstra@chello.nl>,
	x86@kernel.org, linux-kernel@vger.kernel.org,
	Jiri Olsa <jolsa@redhat.com>
Subject: Re: [PATCH 2/5] perf, x86: Enable PDIR precise instruction profiling on IvyBridge
Date: Fri, 6 Jul 2012 03:04:29 +0200	[thread overview]
Message-ID: <CABPqkBQS5gs7F41-Q4gUoURujst0RpJmn5iwUeUYjFUsFkhPBw@mail.gmail.com> (raw)
In-Reply-To: <20120705172654.GG32640@tassilo.jf.intel.com>

On Thu, Jul 5, 2012 at 7:26 PM, Andi Kleen <ak@linux.intel.com> wrote:
> On Thu, Jul 05, 2012 at 05:45:16PM +0200, Stephane Eranian wrote:
>> On Tue, Jul 3, 2012 at 6:04 AM, Andi Kleen <andi@firstfloor.org> wrote:
>> >> Well, the only way I can think of would be to request that the
>> >> event be programmed with exclusive mode ALWAYS. That
>> >> should not be to hard to add.
>> >
>> > I suspect it would need some special callbacks from the events core,
>> > that's why I only tried on IvyBridge.
>> >x
>> You could simply add a check in the x86 init code like what is done
>> with the pebs events and precise mode.
>
> Ah requiring the user to set exclusive? Maybe. Right now perf does not even
> have an option to set it. Would seem user unfriendly to me though.

Yes, that's what I meant since the beginning. Require exclusive mode
on the event is all we need to enforce the restriction. The scheduling
would still only work on counter 1.

I know that perf record/stat do not support this but given the new event
parser it should not too hard to add an excl term to the syntax. I have
that in libpfm4 now as an option on events. That's clearly a perf_event
option like period or freq and not a HW option like inv, edge.

  reply	other threads:[~2012-07-06  1:04 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-07-02 18:43 Updated and combined Sandy Bridge/Ivy Bridge perf patchkits Andi Kleen
2012-07-02 18:43 ` [PATCH 1/5] perf, x86: Improve basic Ivy Bridge support v3 Andi Kleen
2012-07-02 19:26   ` Peter Zijlstra
2012-07-02 19:58     ` Andi Kleen
2012-07-02 20:18       ` Peter Zijlstra
2012-07-02 18:43 ` [PATCH 2/5] perf, x86: Enable PDIR precise instruction profiling on IvyBridge Andi Kleen
2012-07-02 19:18   ` Peter Zijlstra
2012-07-02 19:57     ` Andi Kleen
2012-07-02 20:22       ` Peter Zijlstra
2012-07-02 21:00         ` Andi Kleen
2012-07-02 21:36           ` Peter Zijlstra
2012-07-02 21:57             ` Andi Kleen
2012-07-02 23:13               ` Stephane Eranian
2012-07-03  4:04                 ` Andi Kleen
2012-07-05 15:45                   ` Stephane Eranian
2012-07-05 17:26                     ` Andi Kleen
2012-07-06  1:04                       ` Stephane Eranian [this message]
2012-07-02 18:43 ` [PATCH 3/5] x86: Do microcode updates at CPU_STARTING, not CPU_ONLINE v2 Andi Kleen
2012-07-02 18:43 ` [PATCH 4/5] perf, x86: check ucode before disabling PEBS on SandyBridge v4 Andi Kleen
2012-07-02 18:43 ` [PATCH 5/5] perf, x86: Spell Romley correctly Andi Kleen
2012-07-02 20:40 Another IvyBridge/SandyBridge patchkit Andi Kleen
2012-07-02 20:40 ` [PATCH 2/5] perf, x86: Enable PDIR precise instruction profiling on IvyBridge Andi Kleen

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