[PATCH 00/21] More Haswell patches

[PATCH 00/21] More Haswell patches

[Eugeni Dodonov]

Hi,

Those are the patches which I had in my queue for past few weeks, which I am
sending now for your bikeshedding pleasure :).

As major changes, this patch series adds support for DP, eDP and RC6
features for Haswell. Some of the DP-related patches were already posted
here, but I am resending them as part of this larger series for giving them
proper context.

Also, for DP and eDP, Paulo Zanoni and Shobhit Kumar are already working on a
larger series of patches which should appear in the next few days as well.  So
while the patches in this series should work on most configurations,
considerable amount of improvements are still to come.

(And yes, our entire intel_dp dungeon is getting too dangerous for mere
mortals to enter, so I think a refactoring of its internals is highly
needed.)

Moving to RC6, I've added the new forcewake sequence (which is mostly
similar to gen6), and a new enable/disable set of routines. Most of the
sequence is similar to what we had on SNB/IVB, but there are some changes in
registers and values. So instead of adding another layer of if(IS_HASWELL())
checks all around splitting it into a separate set of functions seems
cleaner. This also prepares the ground for additional patches which are yet
to come.

I've also added haswell_init_clock_gating routine, which is almost identical
to Ivy Bridge. The reason for this was the same as with RC6 - to avoid a
large nesting IS_HASWELL chunks on top of older code.

For both those cases, I'd be interested in your opinion on which approach
you prefer - reusing GEN6 stuff with IS_HASWELL() chunks; or splitting the
functionality into Haswell-specific routines. I can see pros and contras
with both approaches, so I am open to suggestions.

Finally, there are some small cleanup patches for LPT debug/error messages a
small fix for bogus FBC update messages, and a fix for a broken
PIPE_WM_LINETIME register from Paulo which we all overlooked somehow.

So in overall, with those patches, the status of Haswell support should be more
or less on-par with Ivy Bridge kernel-wise. Most things that were working on
IVB should be available on HSW - and if they don't work it is probably a bug,
so please let me know about it.

As usual, bikesheds, comments and suggestions are highly welcome :).

Eugeni



Eugeni Dodonov (10):
  drm/i915: re-initialize DDI buffer translations after resume
  drm/i915: simplify FDI RX check for LPT
  drm/i915: account for only one transcoder on LPT
  drm/i915: introduce lpt_enable_pch and cpt_enable_pch
  drm/i915: program FDI_RX TP and FDI delays
  drm/i915: support Haswell-style force waking
  drm/i915: add RPS configuration for Haswell
  drm/i915: introduce haswell_init_clock_gating
  drm/i915: prevent bogus intel_update_fbc notifications
  drm/i915: enable RC6 workaround on Haswell

Paulo Zanoni (1):
  drm/i915: fix PIPE_WM_LINETIME definition

Shobhit Kumar (10):
  drm/i915: Move DP structs to shared location
  drm/i915: Add support for DDI control DP outputs
  drm/i915: Add DP Helper functions for Haswell
  drm/i915: Haswell specific code for the DP Link Training
  drm/i915: Disable DDI Pipe Control on HSW while disabling pipe
  drm/i915: Hook DP init in ddi module
  drm/i915: Add EDP Registers for Haswell
  drm/i915: Timing initialization for eDP on HSW
  drm/i915: Modesetting for eDP on HSw
  drm/i915: Hook eDP initialization on DDI A

 drivers/gpu/drm/i915/i915_drv.c      |  36 +++++-
 drivers/gpu/drm/i915/i915_drv.h      |   3 +
 drivers/gpu/drm/i915/i915_reg.h      |  74 ++++++++++-
 drivers/gpu/drm/i915/intel_ddi.c     | 235 +++++++++++++++++++++++++++++++++--
 drivers/gpu/drm/i915/intel_display.c | 194 ++++++++++++++++++++++-------
 drivers/gpu/drm/i915/intel_dp.c      | 171 +++++++++++++++++--------
 drivers/gpu/drm/i915/intel_drv.h     |  48 +++++++
 drivers/gpu/drm/i915/intel_pm.c      | 231 ++++++++++++++++++++++++++++++++--
 8 files changed, 878 insertions(+), 114 deletions(-)

-- 
1.7.11.1

[PATCH 01/21] drm/i915: Move DP structs to shared location

[Eugeni Dodonov]

From: Shobhit Kumar <shobhit.kumar@intel.com>

Move the DP structure to shared location so that it can be used from
within ddi module

Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c  | 34 ----------------------------------
 drivers/gpu/drm/i915/intel_drv.h | 35 +++++++++++++++++++++++++++++++++++
 2 files changed, 35 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 76a7080..65280a0a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -38,40 +38,6 @@
 #include "i915_drv.h"
 #include "drm_dp_helper.h"
 
-#define DP_RECEIVER_CAP_SIZE	0xf
-#define DP_LINK_STATUS_SIZE	6
-#define DP_LINK_CHECK_TIMEOUT	(10 * 1000)
-
-#define DP_LINK_CONFIGURATION_SIZE	9
-
-struct intel_dp {
-	struct intel_encoder base;
-	uint32_t output_reg;
-	uint32_t DP;
-	uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
-	bool has_audio;
-	enum hdmi_force_audio force_audio;
-	uint32_t color_range;
-	int dpms_mode;
-	uint8_t link_bw;
-	uint8_t lane_count;
-	uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
-	struct i2c_adapter adapter;
-	struct i2c_algo_dp_aux_data algo;
-	bool is_pch_edp;
-	uint8_t	train_set[4];
-	int panel_power_up_delay;
-	int panel_power_down_delay;
-	int panel_power_cycle_delay;
-	int backlight_on_delay;
-	int backlight_off_delay;
-	struct drm_display_mode *panel_fixed_mode;  /* for eDP */
-	struct delayed_work panel_vdd_work;
-	bool want_panel_vdd;
-	struct edid *edid; /* cached EDID for eDP */
-	int edid_mode_count;
-};
-
 /**
  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  * @intel_dp: DP struct
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index cc1573b..4047b68 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -31,6 +31,7 @@
 #include "drm_crtc.h"
 #include "drm_crtc_helper.h"
 #include "drm_fb_helper.h"
+#include "drm_dp_helper.h"
 
 #define _wait_for(COND, MS, W) ({ \
 	unsigned long timeout__ = jiffies + msecs_to_jiffies(MS);	\
@@ -305,6 +306,40 @@ struct intel_hdmi {
 			       struct drm_display_mode *adjusted_mode);
 };
 
+#define DP_RECEIVER_CAP_SIZE	0xf
+#define DP_LINK_STATUS_SIZE	6
+#define DP_LINK_CHECK_TIMEOUT	(10 * 1000)
+
+#define DP_LINK_CONFIGURATION_SIZE	9
+
+struct intel_dp {
+	struct intel_encoder base;
+	uint32_t output_reg;
+	uint32_t DP;
+	uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
+	bool has_audio;
+	enum hdmi_force_audio force_audio;
+	uint32_t color_range;
+	int dpms_mode;
+	uint8_t link_bw;
+	uint8_t lane_count;
+	uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
+	struct i2c_adapter adapter;
+	struct i2c_algo_dp_aux_data algo;
+	bool is_pch_edp;
+	uint8_t	train_set[4];
+	int panel_power_up_delay;
+	int panel_power_down_delay;
+	int panel_power_cycle_delay;
+	int backlight_on_delay;
+	int backlight_off_delay;
+	struct drm_display_mode *panel_fixed_mode;  /* for eDP */
+	struct delayed_work panel_vdd_work;
+	bool want_panel_vdd;
+	struct edid *edid; /* cached EDID for eDP */
+	int edid_mode_count;
+};
+
 static inline struct drm_crtc *
 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
 {
-- 
1.7.11.1

[PATCH 02/21] drm/i915: Add support for DDI control DP outputs

[Eugeni Dodonov]

From: Shobhit Kumar <shobhit.kumar@intel.com>

These are driven by DDIs on Haswell architecture, so we need to keep
track of which DDI is being used on each output.

Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c  | 10 +++++++---
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 2 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 65280a0a..e324c7a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2458,12 +2458,16 @@ intel_dp_init(struct drm_device *dev, int output_reg)
 
 	connector->polled = DRM_CONNECTOR_POLL_HPD;
 
-	if (output_reg == DP_B || output_reg == PCH_DP_B)
+	if (output_reg == DP_B || output_reg == PCH_DP_B) {
 		intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
-	else if (output_reg == DP_C || output_reg == PCH_DP_C)
+		intel_dp->ddi_port = PORT_B;
+	} else if (output_reg == DP_C || output_reg == PCH_DP_C) {
 		intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
-	else if (output_reg == DP_D || output_reg == PCH_DP_D)
+		intel_dp->ddi_port = PORT_C;
+	} else if (output_reg == DP_D || output_reg == PCH_DP_D) {
 		intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
+		intel_dp->ddi_port = PORT_D;
+	}
 
 	if (is_edp(intel_dp)) {
 		intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 4047b68..7cffb12 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -319,6 +319,7 @@ struct intel_dp {
 	uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
 	bool has_audio;
 	enum hdmi_force_audio force_audio;
+	int ddi_port;
 	uint32_t color_range;
 	int dpms_mode;
 	uint8_t link_bw;
-- 
1.7.11.1

[PATCH 03/21] drm/i915: Add DP Helper functions for Haswell

[Eugeni Dodonov]

From: Shobhit Kumar <shobhit.kumar@intel.com>

Need to program new helpers for mode set and dpms as most of the stuff is done
using DDI port. The current commit uses SPLL clock for SCC enabled panel and
LCPLL for Non-SSC.

Also Haswell has LPT and DDIs are moved on CPU side and has DP_BUF_CTL and
DP_TP_CTL so added a new TP (Transport) holder as well along with DP in intel_dp

Main stream attributes have to be set explicitely from HSW onwrads. So
programmed the same.

Note that in DP mode the value of port width must match the one in the
DDI_BUF_CTL for the DDI port attached to the pipe.

Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Signed-off-by: Sateesh Kavuri <sateesh.kavuri@intel.com>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |  26 +++++-
 drivers/gpu/drm/i915/intel_ddi.c | 167 +++++++++++++++++++++++++++++++++++++--
 drivers/gpu/drm/i915/intel_dp.c  |  18 ++++-
 drivers/gpu/drm/i915/intel_drv.h |   8 ++
 4 files changed, 210 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9dfc4c5..51398a8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4289,6 +4289,7 @@
 #define  PIPE_DDI_BPC_6					(2<<20)
 #define  PIPE_DDI_BPC_12				(3<<20)
 #define  PIPE_DDI_BFI_ENABLE			(1<<4)
+#define  PIPE_DDI_PORT_WIDTH_MASK		(7<<1)
 #define  PIPE_DDI_PORT_WIDTH_X1			(0<<1)
 #define  PIPE_DDI_PORT_WIDTH_X2			(1<<1)
 #define  PIPE_DDI_PORT_WIDTH_X4			(3<<1)
@@ -4335,6 +4336,7 @@
 #define  DDI_BUF_EMP_800MV_3_5DB_HSW	(8<<24)   /* Sel8 */
 #define  DDI_BUF_EMP_MASK				(0xf<<24)
 #define  DDI_BUF_IS_IDLE				(1<<7)
+#define  DDI_PORT_WIDTH_MASK		(7<<1)
 #define  DDI_PORT_WIDTH_X1				(0<<1)
 #define  DDI_PORT_WIDTH_X2				(1<<1)
 #define  DDI_PORT_WIDTH_X4				(3<<1)
@@ -4427,9 +4429,31 @@
 #define LCPLL_CTL				0x130040
 #define  LCPLL_PLL_DISABLE		(1<<31)
 #define  LCPLL_PLL_LOCK			(1<<30)
-#define  LCPLL_CD_CLOCK_DISABLE	(1<<25)
+
+#define  LCPLL_PLL_REFERENCE_BLK	(2<<28)
+#define  LCPLL_PLL_REFERENCE_SSC	(3<<28)
+#define  LCPLL_PLL_REFERENCE_NON_SSC	(0<<28)
+#define	 LCPLL_PLL_REFERENCE_MASK	(0x3<<28)
+
+#define  LCPLL_CD_FREQ_SELECT_MASK      (0x3<<26)
+#define  LCPLL_CD_FREQ_450MHZ		(0x0<<26)
+#define  LCPLL_CD_FREQ_550MHZ		(0x1<<26)
+
+#define  LCPLL_CD_CLOCK_DISABLE		(1<<25)
+#define  LCPLL_ROOT_CD2X_CLOCK_DISABLE  (1<<24)
 #define  LCPLL_CD2X_CLOCK_DISABLE	(1<<23)
 
+#define HSW_MSA_CTL			0x60410
+#define  HSW_MSA_SYNC_CLK		(1<<0)
+#define  HSW_MSA_DYNAMIC_RANGE		(1<<3)
+#define  HSW_MSA_COLORIMETRY		(1<<4)
+#define  HSW_MSA_BPC_MASK		(7<<5)
+#define  HSW_MSA_BPC_6_BITS		(0<<5)
+#define  HSW_MSA_BPC_8_BITS		(1<<5)
+#define  HSW_MSA_BPC_10_BITS		(2<<5)
+#define  HSW_MSA_BPC_12_BITS		(3<<5)
+#define  HSW_MSA_BPC_16_BITS		(4<<5)
+
 /* Pipe WM_LINETIME - watermark line time */
 #define PIPE_WM_LINETIME_A		0x45270
 #define PIPE_WM_LINETIME_B		0x45274
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index f33fe1a..91ed708 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -729,10 +729,159 @@ void intel_ddi_mode_set(struct drm_encoder *encoder,
 	intel_hdmi->set_infoframes(encoder, adjusted_mode);
 }
 
+void
+intel_ddi_mode_set_dp(struct drm_encoder *encoder,
+		struct drm_display_mode *mode,
+		struct drm_display_mode *adjusted_mode)
+{
+	struct drm_device *dev = encoder->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+	struct drm_crtc *crtc = intel_dp->base.base.crtc;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	int port = intel_dp->ddi_port;
+	int pipe = intel_crtc->pipe;
+	int port_width = PIPE_DDI_PORT_WIDTH_X1;
+	int temp;
+
+	DRM_DEBUG_KMS("Preparing DP DDI mode for Haswell on port %c, pipe %c\n",
+					port_name(port), pipe_name(pipe));
+
+	/* Turn on the eDP PLL if needed */
+	/* TBD: */
+
+	/*
+	 * There are two kinds of DP registers in HSW:
+	 * DDI CPU
+	 * LPT PCH
+	 */
+	/* Preserve the BIOS-computed detected bit. This is
+	 * supposed to be read-only.
+	 */
+	intel_dp->DP = I915_READ(DDI_BUF_CTL(intel_dp->ddi_port));
+	intel_dp->DP |= DDI_BUF_EMP_400MV_0DB_HSW;
+	intel_dp->TP = I915_READ(DP_TP_CTL(intel_dp->ddi_port));
+
+	intel_dp->DP &= ~(DDI_PORT_WIDTH_MASK);
+	switch (intel_dp->lane_count) {
+	case 1:
+		intel_dp->DP |= DDI_PORT_WIDTH_X1;
+		port_width = PIPE_DDI_PORT_WIDTH_X1;
+		break;
+	case 2:
+		intel_dp->DP |= DDI_PORT_WIDTH_X2;
+		port_width = PIPE_DDI_PORT_WIDTH_X2;
+		break;
+	case 4:
+		intel_dp->DP |= DDI_PORT_WIDTH_X4;
+		port_width = PIPE_DDI_PORT_WIDTH_X4;
+		break;
+	default:
+		BUG();
+	}
+
+	if (intel_dp->has_audio)
+		DRM_DEBUG_DRIVER("HSW DP Audio not yet supported\n");
+
+	memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
+	intel_dp->link_configuration[0] = intel_dp->link_bw;
+	intel_dp->link_configuration[1] = intel_dp->lane_count;
+	intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
+	/*
+	 * Check for DPCD version > 1.1 and enhanced framing support
+	 */
+	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
+	    (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
+		intel_dp->link_configuration[1] |=
+			DP_LANE_COUNT_ENHANCED_FRAME_EN;
+	}
+
+	/* Enable LCPLL if disabled; required in all cases */
+	temp = I915_READ(LCPLL_CTL);
+	if (temp & LCPLL_PLL_DISABLE) {
+		temp &= ~LCPLL_PLL_DISABLE;
+		temp &= ~LCPLL_CD2X_CLOCK_DISABLE;
+		temp &= ~LCPLL_ROOT_CD2X_CLOCK_DISABLE;
+		temp &= ~LCPLL_CD_CLOCK_DISABLE;
+		temp = (temp & ~LCPLL_CD_FREQ_SELECT_MASK) |
+			LCPLL_CD_FREQ_450MHZ;
+		I915_WRITE(LCPLL_CTL, temp);
+		udelay(20);
+	}
+
+	if (IS_HASWELL(dev)) {
+		if (intel_dp->link_configuration[1] &
+				DP_LANE_COUNT_ENHANCED_FRAME_EN)
+			intel_dp->TP |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
+
+		/* Set the MSA bits, since from HSW onwards,
+		 * this has to be explictly set */
+		temp = I915_READ(HSW_MSA_CTL);
+		temp |= HSW_MSA_SYNC_CLK;
+		temp &= ~HSW_MSA_DYNAMIC_RANGE;
+		temp &= ~HSW_MSA_COLORIMETRY;
+		temp &= ~HSW_MSA_BPC_MASK;
+		temp |= HSW_MSA_BPC_8_BITS; /* Color depth */
+
+		I915_WRITE(HSW_MSA_CTL, temp);
+
+		if ((intel_dp->dpcd[DP_MAX_DOWNSPREAD] & 0x1) == 0x1) {
+			/* SSC Enabled Panel */
+			/* Configure SPLL, program the correct divider values
+			 * for the desired frequency and wait for warmup */
+			I915_WRITE(SPLL_CTL,
+					SPLL_PLL_ENABLE |
+					SPLL_PLL_SCC |
+					SPLL_PLL_FREQ_1350MHz);
+			udelay(20);
+
+			/* Use SPLL clock to drive the output to the dp port,
+			 * and tell the pipe to use this port for connection.
+			 */
+			I915_WRITE(PORT_CLK_SEL(port),
+					PORT_CLK_SEL_SPLL);
+			I915_WRITE(PIPE_CLK_SEL(pipe),
+					PIPE_CLK_SEL_PORT(port));
+		} else {
+			/* Non SSC Panel */
+			/* configure LCPLL for NON-SSC */
+			temp = I915_READ(LCPLL_CTL);
+			temp = (temp & ~LCPLL_PLL_REFERENCE_MASK) |
+				LCPLL_PLL_REFERENCE_NON_SSC;
+			I915_WRITE(LCPLL_CTL, temp);
+			udelay(20);
+
+			/* Use LCPLL clock to drive the output to the dp port,
+			 * and tell the pipe to use this port for connection.
+			 */
+			I915_WRITE(PORT_CLK_SEL(port),
+					PORT_CLK_SEL_LCPLL_1350);
+			I915_WRITE(PIPE_CLK_SEL(pipe),
+					PIPE_CLK_SEL_PORT(port));
+		}
+
+		/* Enable PIPE_DDI_FUNC_CTL for the pipe to work in DP mode */
+		temp = I915_READ(DDI_FUNC_CTL(pipe));
+		temp &= ~PIPE_DDI_PORT_MASK;
+		temp &= ~PIPE_DDI_BPC_12;
+		temp &= ~PIPE_DDI_PORT_WIDTH_MASK;
+		temp |= PIPE_DDI_SELECT_PORT(port) |
+			PIPE_DDI_MODE_SELECT_DP_SST |
+			port_width |
+			((intel_crtc->bpp > 24) ?
+			 PIPE_DDI_BPC_12 :
+			 PIPE_DDI_BPC_8) |
+			PIPE_DDI_FUNC_ENABLE;
+
+		I915_WRITE(DDI_FUNC_CTL(pipe), temp);
+	}
+}
+
 void intel_ddi_dpms(struct drm_encoder *encoder, int mode)
 {
 	struct drm_device *dev = encoder->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
 	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 	int port = intel_hdmi->ddi_port;
 	u32 temp;
@@ -745,10 +894,16 @@ void intel_ddi_dpms(struct drm_encoder *encoder, int mode)
 		temp |= DDI_BUF_CTL_ENABLE;
 	}
 
-	/* Enable DDI_BUF_CTL. In HDMI/DVI mode, the port width,
-	 * and swing/emphasis values are ignored so nothing special needs
-	 * to be done besides enabling the port.
-	 */
-	I915_WRITE(DDI_BUF_CTL(port),
-			temp);
+	if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
+		DRM_DEBUG_DRIVER("DPMS is not yet enabled on DP port\n");
+		return;
+	} else {
+
+		/* Enable DDI_BUF_CTL. In HDMI/DVI mode, the port width,
+		 * and swing/emphasis values are ignored so nothing special
+		 * needs to be done besides enabling the port.
+		 */
+		I915_WRITE(DDI_BUF_CTL(port),
+				temp);
+	}
 }
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index e324c7a..f4c6e98 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -74,7 +74,7 @@ static bool is_cpu_edp(struct intel_dp *intel_dp)
 	return is_edp(intel_dp) && !is_pch_edp(intel_dp);
 }
 
-static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
+struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
 {
 	return container_of(encoder, struct intel_dp, base.base);
 }
@@ -2339,6 +2339,14 @@ static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
 	.commit = intel_dp_commit,
 };
 
+static const struct drm_encoder_helper_funcs intel_dp_helper_funcs_hsw = {
+	.dpms = intel_ddi_dpms,
+	.mode_fixup = intel_dp_mode_fixup,
+	.prepare = intel_dp_prepare,
+	.mode_set = intel_ddi_mode_set_dp,
+	.commit = intel_dp_commit,
+};
+
 static const struct drm_connector_funcs intel_dp_connector_funcs = {
 	.dpms = drm_helper_connector_dpms,
 	.detect = intel_dp_detect,
@@ -2482,7 +2490,13 @@ intel_dp_init(struct drm_device *dev, int output_reg)
 
 	drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
 			 DRM_MODE_ENCODER_TMDS);
-	drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
+
+	if (IS_HASWELL(dev))
+		drm_encoder_helper_add(&intel_encoder->base,
+						&intel_dp_helper_funcs_hsw);
+	else
+		drm_encoder_helper_add(&intel_encoder->base,
+						&intel_dp_helper_funcs);
 
 	intel_connector_attach_encoder(intel_connector, intel_encoder);
 	drm_sysfs_connector_add(connector);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 7cffb12..65b5b7c 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -316,6 +316,7 @@ struct intel_dp {
 	struct intel_encoder base;
 	uint32_t output_reg;
 	uint32_t DP;
+	uint32_t TP;
 	uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
 	bool has_audio;
 	enum hdmi_force_audio force_audio;
@@ -390,6 +391,8 @@ extern void intel_mark_busy(struct drm_device *dev,
 			    struct drm_i915_gem_object *obj);
 extern bool intel_lvds_init(struct drm_device *dev);
 extern void intel_dp_init(struct drm_device *dev, int dp_reg);
+extern struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder);
+
 void
 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
 		 struct drm_display_mode *adjusted_mode);
@@ -534,5 +537,10 @@ extern void intel_ddi_dpms(struct drm_encoder *encoder, int mode);
 extern void intel_ddi_mode_set(struct drm_encoder *encoder,
 				struct drm_display_mode *mode,
 				struct drm_display_mode *adjusted_mode);
+void
+intel_ddi_mode_set_dp(struct drm_encoder *encoder,
+			struct drm_display_mode *mode,
+			struct drm_display_mode *adjusted_mode);
+
 
 #endif /* __INTEL_DRV_H__ */
-- 
1.7.11.1

[PATCH 04/21] drm/i915: Haswell specific code for the DP Link Training

[Eugeni Dodonov]

From: Shobhit Kumar <shobhit.kumar@intel.com>

In Haswell the DDIs have moved on to CPU. The AUX control is on LPT. Had
to split the code in such a way so as to be able to do source training
using DDI_BUF_CTL and DP_TP_CTL and sink side using AUX on LPT.

Also added new routine to get the Volatge and pre-emphashis values. This
is now done for DDI_BUF_CTL which now has common bits indicating a
combination of voltage and pre-emphasis values

Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |   4 ++
 drivers/gpu/drm/i915/intel_ddi.c |  23 +++++++++
 drivers/gpu/drm/i915/intel_dp.c  | 100 ++++++++++++++++++++++++++++++++++++---
 drivers/gpu/drm/i915/intel_drv.h |   3 ++
 4 files changed, 123 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 51398a8..5b0c5f6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4308,7 +4308,10 @@
 #define  DP_TP_CTL_LINK_TRAIN_MASK		(7<<8)
 #define  DP_TP_CTL_LINK_TRAIN_PAT1		(0<<8)
 #define  DP_TP_CTL_LINK_TRAIN_PAT2		(1<<8)
+#define  DP_TP_CTL_LINK_TRAIN_IDLE		(2<<8)
 #define  DP_TP_CTL_LINK_TRAIN_NORMAL	(3<<8)
+#define  DP_TP_CTL_LINK_TRAIN_PAT3	(4<<8)
+#define	 DP_TP_CTL_SCRAMBLE_DISABLE	(1<<7)
 
 /* DisplayPort Transport Status */
 #define DP_TP_STATUS_A			0x64044
@@ -4317,6 +4320,7 @@
 					DP_TP_STATUS_A, \
 					DP_TP_STATUS_B)
 #define  DP_TP_STATUS_AUTOTRAIN_DONE	(1<<12)
+#define DP_TP_STATUS_IDLE_DONE		(1<<25)
 
 /* DDI Buffer Control */
 #define DDI_BUF_CTL_A				0x64000
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 91ed708..f08ce6c 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -907,3 +907,26 @@ void intel_ddi_dpms(struct drm_encoder *encoder, int mode)
 				temp);
 	}
 }
+
+void intel_ddi_dp_set_link_train_src(struct intel_dp *intel_dp, u32 dp_reg_value)
+{
+	struct drm_device *dev = intel_dp->base.base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int port = intel_dp->ddi_port;
+
+	/* Configure DP_TP_CTL with training pattern
+	 * TBD: Only SST now; Enable MST later
+	 * */
+
+	I915_WRITE(DP_TP_CTL(port),
+			intel_dp->TP | DP_TP_CTL_SCRAMBLE_DISABLE |
+			DP_TP_CTL_MODE_SST |
+			DP_TP_CTL_ENABLE);
+
+	/* Configure and enable DDI_BUF_CTL for DDI with next voltage */
+	I915_WRITE(DDI_BUF_CTL(port),
+			DDI_BUF_CTL_ENABLE |
+			dp_reg_value);
+
+	udelay(600);
+}
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f4c6e98..38a1d3b 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1437,6 +1437,18 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
 		default:
 			return DP_TRAIN_PRE_EMPHASIS_0;
 		}
+	} else if (IS_HASWELL(dev)) {
+		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
+		case DP_TRAIN_VOLTAGE_SWING_400:
+			return DP_TRAIN_PRE_EMPHASIS_9_5;
+		case DP_TRAIN_VOLTAGE_SWING_600:
+			return DP_TRAIN_PRE_EMPHASIS_6;
+		case DP_TRAIN_VOLTAGE_SWING_800:
+			return DP_TRAIN_PRE_EMPHASIS_3_5;
+		case DP_TRAIN_VOLTAGE_SWING_1200:
+		default:
+			return DP_TRAIN_PRE_EMPHASIS_0;
+		}
 	} else {
 		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
 		case DP_TRAIN_VOLTAGE_SWING_400:
@@ -1581,6 +1593,40 @@ intel_gen7_edp_signal_levels(uint8_t train_set)
 	}
 }
 
+/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
+static uint32_t
+intel_dp_signal_levels_hsw(uint8_t train_set)
+{
+	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
+					 DP_TRAIN_PRE_EMPHASIS_MASK);
+	switch (signal_levels) {
+	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
+		return DDI_BUF_EMP_400MV_0DB_HSW;
+	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
+		return DDI_BUF_EMP_400MV_3_5DB_HSW;
+	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
+		return DDI_BUF_EMP_400MV_6DB_HSW;
+	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
+		return DDI_BUF_EMP_400MV_9_5DB_HSW;
+
+	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
+		return DDI_BUF_EMP_600MV_0DB_HSW;
+	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
+		return DDI_BUF_EMP_600MV_3_5DB_HSW;
+	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
+		return DDI_BUF_EMP_600MV_6DB_HSW;
+
+	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
+		return DDI_BUF_EMP_800MV_0DB_HSW;
+	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
+		return DDI_BUF_EMP_800MV_3_5DB_HSW;
+	default:
+		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
+			      "0x%x\n", signal_levels);
+		return DDI_BUF_EMP_400MV_0DB_HSW;
+	}
+}
+
 static uint8_t
 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
 		      int lane)
@@ -1638,8 +1684,12 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int ret;
 
-	I915_WRITE(intel_dp->output_reg, dp_reg_value);
-	POSTING_READ(intel_dp->output_reg);
+	if (IS_HASWELL(dev))
+		intel_ddi_dp_set_link_train_src(intel_dp, dp_reg_value);
+	else {
+		I915_WRITE(intel_dp->output_reg, dp_reg_value);
+		POSTING_READ(intel_dp->output_reg);
+	}
 
 	intel_dp_aux_native_write_1(intel_dp,
 				    DP_TRAINING_PATTERN_SET,
@@ -1674,7 +1724,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
 	 * will happen below in intel_dp_set_link_train.  Otherwise, enable
 	 * the port and wait for it to become active.
 	 */
-	if (!HAS_PCH_CPT(dev)) {
+	if (!HAS_PCH_CPT(dev) && !IS_HASWELL(dev)) {
 		I915_WRITE(intel_dp->output_reg, intel_dp->DP);
 		POSTING_READ(intel_dp->output_reg);
 		intel_wait_for_vblank(dev, intel_crtc->pipe);
@@ -1689,8 +1739,9 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
 
 	if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
 		DP &= ~DP_LINK_TRAIN_MASK_CPT;
-	else
+	else if (!IS_HASWELL(dev))
 		DP &= ~DP_LINK_TRAIN_MASK;
+
 	memset(intel_dp->train_set, 0, 4);
 	voltage = 0xff;
 	voltage_tries = 0;
@@ -1708,6 +1759,10 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
 		} else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
 			signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
 			DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
+		} else if (IS_HASWELL(dev)) {
+			signal_levels = intel_dp_signal_levels_hsw(intel_dp->train_set[0]);
+			DRM_DEBUG_KMS("training pattern 1 signal levels hsw %08x\n", signal_levels);
+			DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
 		} else {
 			signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
 			DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels);
@@ -1716,6 +1771,10 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
 
 		if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
 			reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
+		else if (IS_HASWELL(dev)) {
+			reg = DP;
+			intel_dp->TP = (intel_dp->TP & ~DP_TP_CTL_LINK_TRAIN_MASK) | DP_TP_CTL_LINK_TRAIN_PAT1;
+		}
 		else
 			reg = DP | DP_LINK_TRAIN_PAT_1;
 
@@ -1779,6 +1838,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
 	int tries, cr_tries;
 	u32 reg;
 	uint32_t DP = intel_dp->DP;
+	uint32_t TP = intel_dp->TP;
 
 	/* channel equalization */
 	tries = 0;
@@ -1801,6 +1861,9 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
 		} else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
 			signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
 			DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
+		} else if (IS_HASWELL(dev)) {
+			signal_levels = intel_dp_signal_levels_hsw(intel_dp->train_set[0]);
+			DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
 		} else {
 			signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
 			DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
@@ -1808,6 +1871,10 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
 
 		if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
 			reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
+		else if (IS_HASWELL(dev)) {
+			reg = DP;
+			intel_dp->TP = (intel_dp->TP & ~DP_TP_CTL_LINK_TRAIN_MASK) | DP_TP_CTL_LINK_TRAIN_PAT2;
+		}
 		else
 			reg = DP | DP_LINK_TRAIN_PAT_2;
 
@@ -1847,15 +1914,34 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
 		++tries;
 	}
 
+	if (channel_eq)
+		DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
+
 	if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
 		reg = DP | DP_LINK_TRAIN_OFF_CPT;
+	else if (IS_HASWELL(dev)) {
+		TP &= ~DP_TP_CTL_LINK_TRAIN_MASK;
+		reg = TP | DP_TP_CTL_LINK_TRAIN_IDLE;
+		I915_WRITE(DP_TP_CTL(intel_dp->ddi_port), reg);
+		if (wait_for((I915_READ(DP_TP_STATUS(intel_dp->ddi_port)) & DP_TP_STATUS_IDLE_DONE) == 0,
+				800))
+			DRM_ERROR("Timed out waiting for DP min idle patterns\n");
+
+		TP &= ~DP_TP_CTL_LINK_TRAIN_MASK;
+		reg = TP | DP_TP_CTL_LINK_TRAIN_NORMAL;
+		I915_WRITE(DP_TP_CTL(intel_dp->ddi_port), reg);
+	}
 	else
 		reg = DP | DP_LINK_TRAIN_OFF;
 
-	I915_WRITE(intel_dp->output_reg, reg);
-	POSTING_READ(intel_dp->output_reg);
+	if (!IS_HASWELL(dev)) {
+		I915_WRITE(intel_dp->output_reg, reg);
+		POSTING_READ(intel_dp->output_reg);
+	}
+
 	intel_dp_aux_native_write_1(intel_dp,
-				    DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
+			DP_TRAINING_PATTERN_SET,
+			DP_TRAINING_PATTERN_DISABLE);
 }
 
 static void
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 65b5b7c..5ca133d 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -543,4 +543,7 @@ intel_ddi_mode_set_dp(struct drm_encoder *encoder,
 			struct drm_display_mode *adjusted_mode);
 
 
+extern void intel_ddi_dp_set_link_train_src(struct intel_dp *intel_dp,
+				u32 dp_reg_value);
+
 #endif /* __INTEL_DRV_H__ */
-- 
1.7.11.1

[PATCH 05/21] drm/i915: Disable DDI Pipe Control on HSW while disabling pipe

[Eugeni Dodonov]

From: Shobhit Kumar <shobhit.kumar@intel.com>

In Haswell while disabling a pipe, we need to disable the DDI control as
well along with the PIPECONF. Otherwise we will hit assertions during crtc
disable

Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3fbc802..28bee8a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1794,6 +1794,13 @@ static void intel_disable_pipe(struct drm_i915_private *dev_priv,
 
 	I915_WRITE(reg, val & ~PIPECONF_ENABLE);
 	intel_wait_for_pipe_off(dev_priv->dev, pipe);
+
+	/* On HSW DDI Pipe control has to be disabled as well */
+	if (IS_HASWELL(dev_priv->dev)) {
+		val = I915_READ(DDI_FUNC_CTL(pipe));
+		val = val  & (~PIPE_DDI_FUNC_ENABLE);
+		I915_WRITE(DDI_FUNC_CTL(pipe), val);
+	}
 }
 
 /*
-- 
1.7.11.1

[PATCH 06/21] drm/i915: Hook DP init in ddi module

[Eugeni Dodonov]

From: Shobhit Kumar <shobhit.kumar@intel.com>

TBD: As of now just initializes DP connectors. Later we need to detect the
actual output connected on the port(HDMI or DP) using AUX channel detection and
appropriately call the initialization routines

v2: Init DP connector on DDIB and DDID, and HDMI on DDIC.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index f08ce6c..effb263 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -239,10 +239,14 @@ void intel_ddi_init(struct drm_device *dev, enum port port)
 		break;
 	/* Assume that the  ports B, C and D are working in HDMI mode for now */
 	case PORT_B:
+		intel_dp_init(dev, PCH_DP_B);
+		break;
 	case PORT_C:
-	case PORT_D:
 		intel_hdmi_init(dev, DDI_BUF_CTL(port));
 		break;
+	case PORT_D:
+		intel_dp_init(dev, PCH_DP_D);
+		break;
 	default:
 		DRM_DEBUG_DRIVER("No handlers defined for port %d, skipping DDI initialization\n",
 				port);
-- 
1.7.11.1

[PATCH 07/21] drm/i915: re-initialize DDI buffer translations after resume

[Eugeni Dodonov]

This is necessary for the modesetting to work correctly after a
suspend-resume cycle. Without this, the pipes and clocks got the correct
configuration, but the underlying DDI buffers configuration was lost.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 28bee8a..76508a7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7179,6 +7179,8 @@ static void ivb_pch_pwm_override(struct drm_device *dev)
 
 void intel_modeset_init_hw(struct drm_device *dev)
 {
+	intel_prepare_ddi(dev);
+
 	intel_init_clock_gating(dev);
 
 	mutex_lock(&dev->struct_mutex);
@@ -7208,8 +7210,6 @@ void intel_modeset_init(struct drm_device *dev)
 
 	intel_init_pm(dev);
 
-	intel_prepare_ddi(dev);
-
 	intel_init_display(dev);
 
 	if (IS_GEN2(dev)) {
-- 
1.7.11.1

[PATCH 08/21] drm/i915: simplify FDI RX check for LPT

[Eugeni Dodonov]

On LPT onwards, there is only one FDI receiver, but any pipe can drive it.
For now, we consider that only pipeA can work in CRT mode, so if any other
pipe attempts to enable FDI receiver it is considered invalid behavior.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 36 ++++++++++++++++++++++++++----------
 1 file changed, 26 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 76508a7..e8fd6cc 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1128,14 +1128,23 @@ static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 	u32 val;
 	bool cur_state;
 
-	if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
-			DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
+	/* On LPT, there is only one FDI RX that can be used.  At the same
+	 * time, any pipe can connect to it, but only one at a time.  To
+	 * simplify the enabling, we consider that only pipeA can be used in
+	 * FDI configuration.
+	 */
+	if (HAS_PCH_LPT(dev_priv->dev)) {
+		if (pipe > 0) {
+			DRM_ERROR("Attempting to %s FDI_RX on Haswell pipe > 0\n",
+					(state==true) ? "enable" : "disable");
 			return;
-	} else {
-		reg = FDI_RX_CTL(pipe);
-		val = I915_READ(reg);
-		cur_state = !!(val & FDI_RX_ENABLE);
+		}
 	}
+
+	reg = FDI_RX_CTL(pipe);
+	val = I915_READ(reg);
+	cur_state = !!(val & FDI_RX_ENABLE);
+
 	WARN(cur_state != state,
 	     "FDI RX state assertion failure (expected %s, current %s)\n",
 	     state_string(state), state_string(cur_state));
@@ -1651,6 +1660,17 @@ static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
 	/* PCH only available on ILK+ */
 	BUG_ON(dev_priv->info->gen < 5);
 
+	if (HAS_PCH_LPT(dev_priv->dev)) {
+		/* On LPT, there is only one transcoder, but any pipe can be used with it.
+		 * To simplify things, we consider that only pipeA can be used with CRT,
+		 * so we handle this check in the same way as with the FDI receiver.
+		 */
+		if (pipe > 0) {
+			DRM_ERROR("Attempting to enable transcoder on Lynx point with pipe > 0\n");
+			return;
+		}
+	}
+
 	/* Make sure PCH DPLL is enabled */
 	assert_pch_pll_enabled(dev_priv,
 			       to_intel_crtc(crtc)->pch_pll,
@@ -1660,10 +1680,6 @@ static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
 	assert_fdi_tx_enabled(dev_priv, pipe);
 	assert_fdi_rx_enabled(dev_priv, pipe);
 
-	if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
-		DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
-		return;
-	}
 	reg = TRANSCONF(pipe);
 	val = I915_READ(reg);
 	pipeconf_val = I915_READ(PIPECONF(pipe));
-- 
1.7.11.1

[PATCH 09/21] drm/i915: account for only one transcoder on LPT

[Eugeni Dodonov]

Same as with FDI RX, Lynx point only has one transcoder, which can be
driven by any pipe. So consider that only pipeA will be used with CRT for
now.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 19 +++++++++++++++----
 1 file changed, 15 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e8fd6cc..d7b337b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1660,11 +1660,12 @@ static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
 	/* PCH only available on ILK+ */
 	BUG_ON(dev_priv->info->gen < 5);
 
+	/* On LPT, there is only one transcoder, but any pipe can be used with
+	 * it.  To simplify things, we consider that only pipeA can be used
+	 * with CRT, so we handle this check in the same way as with the FDI
+	 * receiver.
+	 */
 	if (HAS_PCH_LPT(dev_priv->dev)) {
-		/* On LPT, there is only one transcoder, but any pipe can be used with it.
-		 * To simplify things, we consider that only pipeA can be used with CRT,
-		 * so we handle this check in the same way as with the FDI receiver.
-		 */
 		if (pipe > 0) {
 			DRM_ERROR("Attempting to enable transcoder on Lynx point with pipe > 0\n");
 			return;
@@ -1714,6 +1715,16 @@ static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
 	int reg;
 	u32 val;
 
+	/* On Lynx Point, there is only one transcoder, which we assume it is
+	 * mapped into pipe 0 for simplicity.
+	 */
+	if (HAS_PCH_LPT(dev_priv->dev)) {
+		if (pipe > 0) {
+			DRM_ERROR("Attempting to disable transcoder on Lynx Point with pipe > 0\n");
+			return;
+		}
+	}
+
 	/* FDI relies on the transcoder */
 	assert_fdi_tx_disabled(dev_priv, pipe);
 	assert_fdi_rx_disabled(dev_priv, pipe);
-- 
1.7.11.1

[PATCH 10/21] drm/i915: introduce lpt_enable_pch and cpt_enable_pch

[Eugeni Dodonov]

CPT/PPT and LPT have different functionality. So we introduce specific
functions to handle each of them instead of using multiple if..
statements.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 70 ++++++++++++++++++++++++++++++++----
 1 file changed, 63 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d7b337b..9a695ab 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2968,6 +2968,51 @@ static void lpt_program_iclkip(struct drm_crtc *crtc)
 	I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
 }
 
+/* On Lynx Point, the PCH part is different, as it has one FDI RX, one
+ * transcoder, and the clock is driven by iCLKIP.
+ */
+static void lpt_pch_enable(struct drm_crtc *crtc)
+{
+	struct drm_device *dev = crtc->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	int pipe = intel_crtc->pipe;
+
+	/* On LPT, there is only one FDI RX and transcoder, which can be driven
+	 * by any pipe. To simplify, we consider that only pipeA can be used in
+	 * such mode.
+	 */
+	if (HAS_PCH_LPT(dev_priv->dev)) {
+		if (pipe > 0) {
+			DRM_ERROR("Attempting to enable PCH port with pipe > 0\n");
+			return;
+		}
+	}
+
+	assert_transcoder_disabled(dev_priv, pipe);
+
+	/* For PCH output, training FDI link */
+	dev_priv->display.fdi_link_train(crtc);
+
+	intel_enable_pch_pll(intel_crtc);
+
+	DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
+	lpt_program_iclkip(crtc);
+
+	/* set transcoder timing, panel must allow it */
+	assert_panel_unlocked(dev_priv, pipe);
+	I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
+	I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
+	I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
+
+	I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
+	I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
+	I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
+	I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
+
+	intel_enable_transcoder(dev_priv, pipe);
+}
+
 /*
  * Enable PCH resources required for PCH ports:
  *   - PCH PLLs
@@ -2976,7 +3021,7 @@ static void lpt_program_iclkip(struct drm_crtc *crtc)
  *   - DP transcoding bits
  *   - transcoder
  */
-static void ironlake_pch_enable(struct drm_crtc *crtc)
+static void cpt_pch_enable(struct drm_crtc *crtc)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -2991,10 +3036,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
 
 	intel_enable_pch_pll(intel_crtc);
 
-	if (HAS_PCH_LPT(dev)) {
-		DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
-		lpt_program_iclkip(crtc);
-	} else if (HAS_PCH_CPT(dev)) {
+	if (HAS_PCH_CPT(dev)) {
 		u32 sel;
 
 		temp = I915_READ(PCH_DPLL_SEL);
@@ -3031,8 +3073,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
 	I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
 	I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
 
-	if (!IS_HASWELL(dev))
-		intel_fdi_normal_train(crtc);
+	intel_fdi_normal_train(crtc);
 
 	/* For PCH DP, enable TRANS_DP_CTL */
 	if (HAS_PCH_CPT(dev) &&
@@ -3075,6 +3116,21 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
 	intel_enable_transcoder(dev_priv, pipe);
 }
 
+/*
+ * When we need to use a PCH port, we can go through different paths on CPT/PPT
+ * and LPT chipsets.
+ */
+static void ironlake_pch_enable(struct drm_crtc *crtc)
+{
+	struct drm_device *dev = crtc->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	if (HAS_PCH_LPT(dev_priv->dev))
+		return lpt_pch_enable(crtc);
+	else
+		return cpt_pch_enable(crtc);
+}
+
 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
 {
 	struct intel_pch_pll *pll = intel_crtc->pch_pll;
-- 
1.7.11.1

[PATCH 11/21] drm/i915: program FDI_RX TP and FDI delays

[Eugeni Dodonov]

This is required for a stable FDI connection.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |  3 +++
 drivers/gpu/drm/i915/intel_ddi.c | 10 ++++++++++
 2 files changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5b0c5f6..284965b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3849,6 +3849,9 @@
 #define _FDI_RXA_TUSIZE2         0xf0038
 #define _FDI_RXB_TUSIZE1         0xf1030
 #define _FDI_RXB_TUSIZE2         0xf1038
+#define  FDI_RX_TP1_TO_TP2_48	(10<<20)
+#define  FDI_RX_TP1_TO_TP2_64	(11<<20)
+#define  FDI_RX_FDI_DELAY_90	(0x90<<0)
 #define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
 #define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
 #define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index effb263..1c76d20 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -170,6 +170,16 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
 
 		udelay(600);
 
+		/* We need to program FDI_RX_MISC with the default TP1 to TP2
+		 * values before enabling the receiver, and configure the delay
+		 * for the FDI timing generator to 90h.
+		 */
+		reg = FDI_RX_MISC(pipe);
+		temp = I915_READ(reg);
+		temp |= FDI_RX_TP1_TO_TP2_48 |
+			FDI_RX_FDI_DELAY_90;
+		I915_WRITE(reg, temp);
+
 		/* Enable CPU FDI Receiver with auto-training */
 		reg = FDI_RX_CTL(pipe);
 		I915_WRITE(reg,
-- 
1.7.11.1

[PATCH 12/21] drm/i915: support Haswell-style force waking

[Eugeni Dodonov]

On Haswell, there is a different register for reading force wake ACKs, and
all the writes should go into the multi-threaded register, even for the
legacy force wake.

Also, we have a theorical possibility for the force wake sequence to
awaken the GT, but return while it hasn't finished bringing up the queue.
So we properly check those bits as well, to ensure we won't end up in
half-woken situation.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 36 +++++++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/i915_drv.h |  3 +++
 drivers/gpu/drm/i915/i915_reg.h |  1 +
 drivers/gpu/drm/i915/intel_pm.c |  4 +++-
 4 files changed, 42 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 79be879..73fd38a 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -536,6 +536,39 @@ int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
 	return ret;
 }
 
+static inline void __hsw_wait_gt_awake(struct drm_i915_private *dev_priv)
+{
+	int count = 0;
+
+	while (count++ < 50) {
+		u32 tmp = I915_READ_NOTRACE(FORCEWAKE_ACK_HSW);
+		if ((tmp & 1) && !(tmp & _MASKED_BIT_ENABLE(~7)))
+			break;
+		udelay(10);
+	}
+}
+
+
+void hsw_gt_force_wake_get(struct drm_i915_private *dev_priv)
+{
+	__hsw_wait_gt_awake(dev_priv);
+
+	I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(1));
+	POSTING_READ(FORCEWAKE_MT);
+
+	__hsw_wait_gt_awake(dev_priv);
+}
+
+void hsw_gt_force_wake_put(struct drm_i915_private *dev_priv)
+{
+	I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(1));
+
+	__hsw_wait_gt_awake(dev_priv);
+
+	/* The below doubles as a POSTING_READ */
+	gen6_gt_check_fifodbg(dev_priv);
+}
+
 void vlv_force_wake_get(struct drm_i915_private *dev_priv)
 {
 	int count;
@@ -1161,7 +1194,8 @@ MODULE_LICENSE("GPL and additional rights");
 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
 	((HAS_FORCE_WAKE((dev_priv)->dev)) && \
 	 ((reg) < 0x40000) &&            \
-	 ((reg) != FORCEWAKE))
+	 ((reg) != FORCEWAKE) &&         \
+	 ((reg) != FORCEWAKE_MT))
 
 static bool IS_DISPLAYREG(u32 reg)
 {
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a0c15ab..e4916a0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1525,6 +1525,9 @@ extern void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv);
 extern void vlv_force_wake_get(struct drm_i915_private *dev_priv);
 extern void vlv_force_wake_put(struct drm_i915_private *dev_priv);
 
+extern void hsw_gt_force_wake_get(struct drm_i915_private *dev_priv);
+extern void hsw_gt_force_wake_put(struct drm_i915_private *dev_priv);
+
 /* overlay */
 #ifdef CONFIG_DEBUG_FS
 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 284965b..2c4be2e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4070,6 +4070,7 @@
 #define  FORCEWAKE				0xA18C
 #define  FORCEWAKE_VLV				0x1300b0
 #define  FORCEWAKE_ACK_VLV			0x1300b4
+#define  FORCEWAKE_ACK_HSW			0x130044
 #define  FORCEWAKE_ACK				0x130090
 #define  FORCEWAKE_MT				0xa188 /* multi-threaded */
 #define  FORCEWAKE_MT_ACK			0x130040
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 99bc1f3..0334e42 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3769,7 +3769,7 @@ void intel_init_pm(struct drm_device *dev)
 		dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
 
 		/* IVB configs may use multi-threaded forcewake */
-		if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
+		if (IS_IVYBRIDGE(dev)) {
 			u32	ecobus;
 
 			/* A small trick here - if the bios hasn't configured MT forcewake,
@@ -3842,6 +3842,8 @@ void intel_init_pm(struct drm_device *dev)
 			}
 			dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
 			dev_priv->display.sanitize_pm = gen6_sanitize_pm;
+			dev_priv->display.force_wake_get = hsw_gt_force_wake_get;
+			dev_priv->display.force_wake_put = hsw_gt_force_wake_put;
 		} else
 			dev_priv->display.update_wm = NULL;
 	} else if (IS_VALLEYVIEW(dev)) {
-- 
1.7.11.1

[PATCH 13/21] drm/i915: add RPS configuration for Haswell

[Eugeni Dodonov]

Split Haswell-specific GT algorithms into its own function.

Note that Haswell only has RC6, so account for that as well.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |   1 +
 drivers/gpu/drm/i915/intel_pm.c | 160 ++++++++++++++++++++++++++++++++++++++--
 2 files changed, 155 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2c4be2e..0c53e4a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4131,6 +4131,7 @@
 #define   GEN6_RP_UP_IDLE_MIN			(0x1<<3)
 #define   GEN6_RP_UP_BUSY_AVG			(0x2<<3)
 #define   GEN6_RP_UP_BUSY_CONT			(0x4<<3)
+#define   GEN7_RP_DOWN_IDLE_AVG			(0x2<<0)
 #define   GEN6_RP_DOWN_IDLE_CONT		(0x1<<0)
 #define GEN6_RP_UP_THRESHOLD			0xA02C
 #define GEN6_RP_DOWN_THRESHOLD			0xA030
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0334e42..0733f16 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2301,6 +2301,26 @@ void gen6_set_rps(struct drm_device *dev, u8 val)
 	dev_priv->cur_delay = val;
 }
 
+static void hsw_disable_rps(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	I915_WRITE(GEN6_RC_CONTROL, 0);
+	I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
+	I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
+	I915_WRITE(GEN6_PMIER, 0);
+	/* Complete PM interrupt masking here doesn't race with the rps work
+	 * item again unmasking PM interrupts because that is using a different
+	 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
+	 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
+
+	spin_lock_irq(&dev_priv->rps_lock);
+	dev_priv->pm_iir = 0;
+	spin_unlock_irq(&dev_priv->rps_lock);
+
+	I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
+}
+
 static void gen6_disable_rps(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -2334,9 +2354,10 @@ int intel_enable_rc6(const struct drm_device *dev)
 	if (INTEL_INFO(dev)->gen == 5)
 		return 0;
 
-	/* Sorry Haswell, no RC6 for you for now. */
+	/* Haswell does not has RC6p nor RC6pp
+	 */
 	if (IS_HASWELL(dev))
-		return 0;
+		return INTEL_RC6_ENABLE;
 
 	/*
 	 * Disable rc6 on Sandybridge
@@ -2349,6 +2370,130 @@ int intel_enable_rc6(const struct drm_device *dev)
 	return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
 }
 
+static void hsw_enable_rps(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_ring_buffer *ring;
+	u32 pcu_mbox, rc6_mask = 0;
+	int rc6_mode;
+	int i;
+
+	WARN_ON(!mutex_is_locked(&dev->struct_mutex));
+
+	/* Here begins a magic sequence of register writes to enable
+	 * auto-downclocking.
+	 *
+	 * Perhaps there might be some value in exposing these to
+	 * userspace...
+	 */
+	I915_WRITE(GEN6_RC_STATE, 0);
+
+	gen6_gt_force_wake_get(dev_priv);
+
+	/* In units of 100MHz */
+	dev_priv->max_delay = 18;
+	dev_priv->min_delay = 6;
+	dev_priv->cur_delay = 0;
+
+	/* disable the counters and set deterministic thresholds */
+	I915_WRITE(GEN6_RC_CONTROL, 0);
+
+	I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
+	I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
+	I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
+	I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
+
+	for_each_ring(ring, dev_priv, i)
+		I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
+
+	I915_WRITE(GEN6_RC_SLEEP, 0);
+	I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
+	I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
+
+	rc6_mode = intel_enable_rc6(dev_priv->dev);
+
+	if (rc6_mode & INTEL_RC6_ENABLE)
+		rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
+
+	DRM_INFO("Enabling RC6 states on Haswell: RC6 %s\n",
+			(rc6_mode & INTEL_RC6_ENABLE) ? "on" : "off");
+
+	I915_WRITE(GEN6_RC_CONTROL,
+		   rc6_mask |
+		   GEN6_RC_CTL_EI_MODE(1) |
+		   GEN6_RC_CTL_HW_ENABLE);
+
+	I915_WRITE(GEN6_RPNSWREQ,
+		   GEN6_FREQUENCY(10) |
+		   GEN6_OFFSET(0) |
+		   GEN6_AGGRESSIVE_TURBO);
+	I915_WRITE(GEN6_RC_VIDEO_FREQ,
+		   GEN6_FREQUENCY(12));
+
+	I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
+	I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
+		   dev_priv->max_delay << 24 |
+		   dev_priv->min_delay << 16);
+	I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
+	I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
+	I915_WRITE(GEN6_RP_UP_EI, 66000);
+	I915_WRITE(GEN6_RP_DOWN_EI, 350000);
+	I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
+	I915_WRITE(GEN6_RP_CONTROL,
+		   GEN6_RP_MEDIA_TURBO |
+		   GEN6_RP_MEDIA_HW_MODE |
+		   GEN6_RP_MEDIA_IS_GFX |
+		   GEN6_RP_ENABLE |
+		   GEN6_RP_UP_BUSY_AVG |
+		   GEN7_RP_DOWN_IDLE_AVG);
+
+	if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
+		     500))
+		DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
+
+	I915_WRITE(GEN6_PCODE_DATA, 0);
+	I915_WRITE(GEN6_PCODE_MAILBOX,
+		   GEN6_PCODE_READY |
+		   GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
+	if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
+		     500))
+		DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
+
+	/* Check for overclock support */
+	if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
+		     500))
+		DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
+	I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
+	pcu_mbox = I915_READ(GEN6_PCODE_DATA);
+	if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
+		     500))
+		DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
+	if (pcu_mbox & (1<<31)) { /* OC supported */
+		dev_priv->max_delay = pcu_mbox & 0xff;
+		DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
+	}
+
+	/* requires MSI enabled */
+	I915_WRITE(GEN6_PMIER,
+		   GEN6_PM_MBOX_EVENT |
+		   GEN6_PM_THERMAL_EVENT |
+		   GEN6_PM_RP_DOWN_TIMEOUT |
+		   GEN6_PM_RP_UP_THRESHOLD |
+		   GEN6_PM_RP_DOWN_THRESHOLD |
+		   GEN6_PM_RP_UP_EI_EXPIRED |
+		   GEN6_PM_RP_DOWN_EI_EXPIRED);
+
+	spin_lock_irq(&dev_priv->rps_lock);
+	WARN_ON(dev_priv->pm_iir != 0);
+	I915_WRITE(GEN6_PMIMR, 0);
+	spin_unlock_irq(&dev_priv->rps_lock);
+
+	/* enable all PM interrupts */
+	I915_WRITE(GEN6_PMINTRMSK, 0);
+
+	gen6_gt_force_wake_put(dev_priv);
+}
+
 static void gen6_enable_rps(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3227,7 +3372,9 @@ void intel_disable_gt_powersave(struct drm_device *dev)
 {
 	if (IS_IRONLAKE_M(dev))
 		ironlake_disable_drps(dev);
-	if (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev))
+	else if (IS_HASWELL(dev))
+		hsw_disable_rps(dev);
+	else if (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev))
 		gen6_disable_rps(dev);
 }
 
@@ -3237,9 +3384,10 @@ void intel_enable_gt_powersave(struct drm_device *dev)
 		ironlake_enable_drps(dev);
 		ironlake_enable_rc6(dev);
 		intel_init_emon(dev);
-	}
-
-	if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
+	} else if (IS_HASWELL(dev)) {
+		hsw_enable_rps(dev);
+		gen6_update_ring_freq(dev);
+	} else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
 		gen6_enable_rps(dev);
 		gen6_update_ring_freq(dev);
 	}
-- 
1.7.11.1

[PATCH 14/21] drm/i915: Add EDP Registers for Haswell

[Eugeni Dodonov]

From: Shobhit Kumar <shobhit.kumar@intel.com>

PIPE EDP registers and timing registers are different for EDP on HSW

Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Signed-off-by: Sateesh Kavuri <sateesh.kavuri@intel.com>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0c53e4a..1e70fae 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1528,6 +1528,14 @@
 #define _BCLRPAT_B	0x61020
 #define _VSYNCSHIFT_B	0x61028
 
+/* Pipe EDP timing regs */
+#define HTOTAL_EDP	0x6F000
+#define HBLANK_EDP	0x6F004
+#define HSYNC_EDP	0x6F008
+#define VTOTAL_EDP	0x6F00C
+#define VBLANK_EDP	0x6F010
+#define VSYNC_EDP	0x6F014
+#define VSYNCSHIFT_EDP	0x6F028
 
 #define HTOTAL(pipe) _PIPE(pipe, _HTOTAL_A, _HTOTAL_B)
 #define HBLANK(pipe) _PIPE(pipe, _HBLANK_A, _HBLANK_B)
@@ -3243,6 +3251,19 @@
 #define _PIPEB_LINK_M2           0x61048
 #define _PIPEB_LINK_N2           0x6104c
 
+/* PIPE EDP timing regs */
+#define PIPEEDP_DATA_M1	0x6F030
+#define PIPEEDP_DATA_N1	0x6F034
+
+#define PIPDEDP_DATA_M2	0x6F038
+#define PIPEEDP_DATA_N2	0x6F03C
+
+#define PIPEEDP_LINK_M1	0x6F040
+#define PIPEEDP_LINK_N1	0x6F044
+
+#define PIPEEDP_LINK_M2	0x6F048
+#define PIPEEDP_LINK_N2	0x6F04C
+
 #define PIPE_DATA_M1(pipe) _PIPE(pipe, _PIPEA_DATA_M1, _PIPEB_DATA_M1)
 #define PIPE_DATA_N1(pipe) _PIPE(pipe, _PIPEA_DATA_N1, _PIPEB_DATA_N1)
 #define PIPE_DATA_M2(pipe) _PIPE(pipe, _PIPEA_DATA_M2, _PIPEB_DATA_M2)
@@ -4277,6 +4298,12 @@
 #define PIPE_DDI_FUNC_CTL_B			0x61400
 #define PIPE_DDI_FUNC_CTL_C			0x62400
 #define PIPE_DDI_FUNC_CTL_EDP		0x6F400
+#define PIPE_DDI_EDP_INPUT_SRC_MASK			(7<<12)
+#define PIPE_DDI_EDI_INPUT_SRC_A_ON			(0<<12)
+#define PIPE_DDI_EDI_INPUT_SRC_A_ON_OFF		(4<<12)
+#define PIPE_DDI_EDI_INPUT_SRC_B_ON_OFF		(5<<12)
+#define PIPE_DDI_EDI_INPUT_SRC_C_ON_OFF		(6<<12)
+
 #define DDI_FUNC_CTL(pipe) _PIPE(pipe, \
 					PIPE_DDI_FUNC_CTL_A, \
 					PIPE_DDI_FUNC_CTL_B)
@@ -4345,6 +4372,8 @@
 #define  DDI_BUF_EMP_800MV_3_5DB_HSW	(8<<24)   /* Sel8 */
 #define  DDI_BUF_EMP_MASK				(0xf<<24)
 #define  DDI_BUF_IS_IDLE				(1<<7)
+#define  DDI_PORT_LANE_CAP_DDIA_4		(1<<4)
+#define  DDI_PORT_LANE_CAP_DDIA_2		(0<<4)
 #define  DDI_PORT_WIDTH_MASK		(7<<1)
 #define  DDI_PORT_WIDTH_X1				(0<<1)
 #define  DDI_PORT_WIDTH_X2				(1<<1)
@@ -4463,6 +4492,8 @@
 #define  HSW_MSA_BPC_12_BITS		(3<<5)
 #define  HSW_MSA_BPC_16_BITS		(4<<5)
 
+#define HSW_MSA_EDP_CTL		0x6F410
+
 /* Pipe WM_LINETIME - watermark line time */
 #define PIPE_WM_LINETIME_A		0x45270
 #define PIPE_WM_LINETIME_B		0x45274
-- 
1.7.11.1

[PATCH 15/21] drm/i915: Timing initialization for eDP on HSW

[Eugeni Dodonov]

From: Shobhit Kumar <shobhit.kumar@intel.com>

v2: simplify horizontal and vertical timings calculations

Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Signed-off-by: Sateesh Kavuri <sateesh.kavuri@intel.com>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 66 +++++++++++++++++++++++-------------
 1 file changed, 42 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 9a695ab..0438a10 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4669,6 +4669,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 	unsigned int pipe_bpp;
 	bool dither;
 	bool is_cpu_edp = false, is_pch_edp = false;
+	u32 htotal, hblank, hsync, vtotal, vblank, vsync;
 
 	list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
 		if (encoder->base.crtc != crtc)
@@ -4949,7 +4950,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 		pipeconf |= PIPECONF_DITHER_EN;
 		pipeconf |= PIPECONF_DITHER_TYPE_SP;
 	}
-	if (is_dp && !is_cpu_edp) {
+	if ((IS_HASWELL(dev) && is_cpu_edp) || (is_dp && !is_cpu_edp)) {
 		intel_dp_set_m_n(crtc, mode, adjusted_mode);
 	} else {
 		/* For non-DP output, clear any trans DP clock recovery setting.*/
@@ -4998,25 +4999,40 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 		I915_WRITE(VSYNCSHIFT(pipe), 0);
 	}
 
-	I915_WRITE(HTOTAL(pipe),
-		   (adjusted_mode->crtc_hdisplay - 1) |
-		   ((adjusted_mode->crtc_htotal - 1) << 16));
-	I915_WRITE(HBLANK(pipe),
-		   (adjusted_mode->crtc_hblank_start - 1) |
-		   ((adjusted_mode->crtc_hblank_end - 1) << 16));
-	I915_WRITE(HSYNC(pipe),
-		   (adjusted_mode->crtc_hsync_start - 1) |
-		   ((adjusted_mode->crtc_hsync_end - 1) << 16));
-
-	I915_WRITE(VTOTAL(pipe),
-		   (adjusted_mode->crtc_vdisplay - 1) |
-		   ((adjusted_mode->crtc_vtotal - 1) << 16));
-	I915_WRITE(VBLANK(pipe),
-		   (adjusted_mode->crtc_vblank_start - 1) |
-		   ((adjusted_mode->crtc_vblank_end - 1) << 16));
-	I915_WRITE(VSYNC(pipe),
-		   (adjusted_mode->crtc_vsync_start - 1) |
-		   ((adjusted_mode->crtc_vsync_end - 1) << 16));
+	if (is_cpu_edp && IS_HASWELL(dev)) {
+		htotal = HTOTAL_EDP;
+		hblank = HBLANK_EDP;
+		hsync = HSYNC_EDP;
+		vtotal = VTOTAL_EDP;
+		vblank = VBLANK_EDP;
+		vsync = VSYNC_EDP;
+	} else {
+		htotal = HTOTAL(pipe);
+		hblank = HBLANK(pipe);
+		hsync = HSYNC(pipe);
+		vtotal = VTOTAL(pipe);
+		vblank = VBLANK(pipe);
+		vsync = VSYNC(pipe);
+	}
+	I915_WRITE(htotal,
+		(adjusted_mode->crtc_hdisplay - 1) |
+		((adjusted_mode->crtc_htotal - 1) << 16));
+	I915_WRITE(hblank,
+		(adjusted_mode->crtc_hblank_start - 1) |
+		((adjusted_mode->crtc_hblank_end - 1) << 16));
+	I915_WRITE(hsync,
+		(adjusted_mode->crtc_hsync_start - 1) |
+		((adjusted_mode->crtc_hsync_end - 1) << 16));
+
+	I915_WRITE(vtotal,
+		(adjusted_mode->crtc_vdisplay - 1) |
+		((adjusted_mode->crtc_vtotal - 1) << 16));
+	I915_WRITE(vblank,
+		(adjusted_mode->crtc_vblank_start - 1) |
+		((adjusted_mode->crtc_vblank_end - 1) << 16));
+	I915_WRITE(vsync,
+		(adjusted_mode->crtc_vsync_start - 1) |
+		((adjusted_mode->crtc_vsync_end - 1) << 16));
 
 	/* pipesrc controls the size that is scaled from, which should
 	 * always be the user's requested size.
@@ -5024,10 +5040,12 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 	I915_WRITE(PIPESRC(pipe),
 		   ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
 
-	I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
-	I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
-	I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
-	I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
+	if (!is_cpu_edp) {
+		I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
+		I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
+		I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
+		I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
+	}
 
 	if (is_cpu_edp)
 		ironlake_set_pll_edp(crtc, adjusted_mode->clock);
-- 
1.7.11.1

[PATCH 16/21] drm/i915: Modesetting for eDP on HSw

[Eugeni Dodonov]

From: Shobhit Kumar <shobhit.kumar@intel.com>

The MSA register and PIPE EDP register are differnet than that of DP.
Also link training flow though similar for DP had been corrected to
follow DP path

Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Signed-off-by: Sateesh Kavuri <sateesh.kavuri@intel.com>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |  1 +
 drivers/gpu/drm/i915/intel_ddi.c | 70 ++++++++++++++++++++++++++++------------
 drivers/gpu/drm/i915/intel_dp.c  |  8 ++---
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 4 files changed, 55 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1e70fae..1165d2e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4316,6 +4316,7 @@
 #define  PIPE_DDI_MODE_SELECT_DP_SST	(2<<24)
 #define  PIPE_DDI_MODE_SELECT_DP_MST	(3<<24)
 #define  PIPE_DDI_MODE_SELECT_FDI		(4<<24)
+#define  PIPE_DDI_BPC_MASK		(0x7<<20)
 #define  PIPE_DDI_BPC_8					(0<<20)
 #define  PIPE_DDI_BPC_10				(1<<20)
 #define  PIPE_DDI_BPC_6					(2<<20)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 1c76d20..9d09f38 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -756,22 +756,16 @@ intel_ddi_mode_set_dp(struct drm_encoder *encoder,
 	int port = intel_dp->ddi_port;
 	int pipe = intel_crtc->pipe;
 	int port_width = PIPE_DDI_PORT_WIDTH_X1;
-	int temp;
+	int temp, reg;
 
 	DRM_DEBUG_KMS("Preparing DP DDI mode for Haswell on port %c, pipe %c\n",
 					port_name(port), pipe_name(pipe));
 
-	/* Turn on the eDP PLL if needed */
-	/* TBD: */
-
 	/*
 	 * There are two kinds of DP registers in HSW:
 	 * DDI CPU
 	 * LPT PCH
 	 */
-	/* Preserve the BIOS-computed detected bit. This is
-	 * supposed to be read-only.
-	 */
 	intel_dp->DP = I915_READ(DDI_BUF_CTL(intel_dp->ddi_port));
 	intel_dp->DP |= DDI_BUF_EMP_400MV_0DB_HSW;
 	intel_dp->TP = I915_READ(DP_TP_CTL(intel_dp->ddi_port));
@@ -794,6 +788,10 @@ intel_ddi_mode_set_dp(struct drm_encoder *encoder,
 		BUG();
 	}
 
+	/* Assuming all 4 lanes available to DDI A for eDP */
+	if (is_edp(intel_dp))
+		intel_dp->DP |= DDI_PORT_LANE_CAP_DDIA_4;
+
 	if (intel_dp->has_audio)
 		DRM_DEBUG_DRIVER("HSW DP Audio not yet supported\n");
 
@@ -830,14 +828,24 @@ intel_ddi_mode_set_dp(struct drm_encoder *encoder,
 
 		/* Set the MSA bits, since from HSW onwards,
 		 * this has to be explictly set */
-		temp = I915_READ(HSW_MSA_CTL);
+		if (is_edp(intel_dp))
+			temp = I915_READ(HSW_MSA_EDP_CTL);
+		else
+			temp = I915_READ(HSW_MSA_CTL);
+
 		temp |= HSW_MSA_SYNC_CLK;
 		temp &= ~HSW_MSA_DYNAMIC_RANGE;
 		temp &= ~HSW_MSA_COLORIMETRY;
 		temp &= ~HSW_MSA_BPC_MASK;
-		temp |= HSW_MSA_BPC_8_BITS; /* Color depth */
 
-		I915_WRITE(HSW_MSA_CTL, temp);
+		if (is_edp(intel_dp)) {
+			temp |= HSW_MSA_BPC_6_BITS; /* Color depth */
+			I915_WRITE(HSW_MSA_EDP_CTL, temp);
+		}
+		else {
+			temp |= HSW_MSA_BPC_8_BITS; /* Color depth */
+			I915_WRITE(HSW_MSA_CTL, temp);
+		}
 
 		if ((intel_dp->dpcd[DP_MAX_DOWNSPREAD] & 0x1) == 0x1) {
 			/* SSC Enabled Panel */
@@ -854,8 +862,9 @@ intel_ddi_mode_set_dp(struct drm_encoder *encoder,
 			 */
 			I915_WRITE(PORT_CLK_SEL(port),
 					PORT_CLK_SEL_SPLL);
-			I915_WRITE(PIPE_CLK_SEL(pipe),
-					PIPE_CLK_SEL_PORT(port));
+			if (!is_edp(intel_dp))
+				I915_WRITE(PIPE_CLK_SEL(pipe),
+						PIPE_CLK_SEL_PORT(port));
 		} else {
 			/* Non SSC Panel */
 			/* configure LCPLL for NON-SSC */
@@ -864,30 +873,49 @@ intel_ddi_mode_set_dp(struct drm_encoder *encoder,
 				LCPLL_PLL_REFERENCE_NON_SSC;
 			I915_WRITE(LCPLL_CTL, temp);
 			udelay(20);
-
 			/* Use LCPLL clock to drive the output to the dp port,
 			 * and tell the pipe to use this port for connection.
 			 */
 			I915_WRITE(PORT_CLK_SEL(port),
 					PORT_CLK_SEL_LCPLL_1350);
-			I915_WRITE(PIPE_CLK_SEL(pipe),
-					PIPE_CLK_SEL_PORT(port));
+			if (!is_edp(intel_dp))
+				I915_WRITE(PIPE_CLK_SEL(pipe),
+						PIPE_CLK_SEL_PORT(port));
 		}
 
 		/* Enable PIPE_DDI_FUNC_CTL for the pipe to work in DP mode */
-		temp = I915_READ(DDI_FUNC_CTL(pipe));
+		if(is_edp(intel_dp)) {
+			reg = PIPE_DDI_FUNC_CTL_EDP;
+			temp = I915_READ(reg);
+			temp &= ~PIPE_DDI_EDP_INPUT_SRC_MASK ;
+
+			/* Use On/Off for now to address all cases; later we
+			 * need to also add support for always on without panel
+			 * fitter in case of native mode to save power
+			 */
+			temp &= ~PIPE_DDI_BPC_MASK;
+			temp |= PIPE_DDI_EDI_INPUT_SRC_A_ON_OFF;
+			temp |= ((intel_crtc->bpp > 24) ?
+				PIPE_DDI_BPC_12 :
+				PIPE_DDI_BPC_6);
+		}
+		else {
+			reg = DDI_FUNC_CTL(pipe);
+			temp = I915_READ(reg);
+			temp &= ~PIPE_DDI_BPC_MASK;
+			temp |= ((intel_crtc->bpp > 24) ?
+				PIPE_DDI_BPC_12 :
+				PIPE_DDI_BPC_8);
+		}
+
 		temp &= ~PIPE_DDI_PORT_MASK;
-		temp &= ~PIPE_DDI_BPC_12;
 		temp &= ~PIPE_DDI_PORT_WIDTH_MASK;
 		temp |= PIPE_DDI_SELECT_PORT(port) |
 			PIPE_DDI_MODE_SELECT_DP_SST |
 			port_width |
-			((intel_crtc->bpp > 24) ?
-			 PIPE_DDI_BPC_12 :
-			 PIPE_DDI_BPC_8) |
 			PIPE_DDI_FUNC_ENABLE;
 
-		I915_WRITE(DDI_FUNC_CTL(pipe), temp);
+		I915_WRITE(reg, temp);
 	}
 }
 
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 38a1d3b..f086944 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -45,7 +45,7 @@
  * If a CPU or PCH DP output is attached to an eDP panel, this function
  * will return true, and false otherwise.
  */
-static bool is_edp(struct intel_dp *intel_dp)
+bool is_edp(struct intel_dp *intel_dp)
 {
 	return intel_dp->base.type == INTEL_OUTPUT_EDP;
 }
@@ -363,7 +363,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
 	 * clock divider.
 	 */
 	if (is_cpu_edp(intel_dp)) {
-		if (IS_GEN6(dev) || IS_GEN7(dev))
+		if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_HASWELL(dev))
 			aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
 		else
 			aux_clock_divider = 225; /* eDP input clock at 450Mhz */
@@ -1753,7 +1753,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
 		uint32_t    signal_levels;
 
 
-		if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
+		if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_HASWELL(dev)) {
 			signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
 			DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
 		} else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
@@ -1855,7 +1855,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
 			break;
 		}
 
-		if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
+		if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_HASWELL(dev)) {
 			signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
 			DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
 		} else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 5ca133d..a741a02 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -392,6 +392,7 @@ extern void intel_mark_busy(struct drm_device *dev,
 extern bool intel_lvds_init(struct drm_device *dev);
 extern void intel_dp_init(struct drm_device *dev, int dp_reg);
 extern struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder);
+extern bool is_edp(struct intel_dp *intel_dp);
 
 void
 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
-- 
1.7.11.1

[PATCH 17/21] drm/i915: Hook eDP initialization on DDI A

[Eugeni Dodonov]

From: Shobhit Kumar <shobhit.kumar@intel.com>

Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Signed-off-by: Sateesh Kavuri <sateesh.kavuri@intel.com>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 3 +--
 drivers/gpu/drm/i915/intel_dp.c  | 1 +
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 9d09f38..e8a5b80 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -244,8 +244,7 @@ void intel_ddi_init(struct drm_device *dev, enum port port)
 
 	switch(port){
 	case PORT_A:
-		/* We don't handle eDP and DP yet */
-		DRM_DEBUG_DRIVER("Found digital output on DDI port A\n");
+		intel_dp_init(dev, DP_A);
 		break;
 	/* Assume that the  ports B, C and D are working in HDMI mode for now */
 	case PORT_B:
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f086944..7b5da87 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2541,6 +2541,7 @@ intel_dp_init(struct drm_device *dev, int output_reg)
 	if (output_reg == DP_A || is_pch_edp(intel_dp)) {
 		type = DRM_MODE_CONNECTOR_eDP;
 		intel_encoder->type = INTEL_OUTPUT_EDP;
+		intel_dp->ddi_port = PORT_A;
 	} else {
 		type = DRM_MODE_CONNECTOR_DisplayPort;
 		intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
-- 
1.7.11.1

[PATCH 18/21] drm/i915: introduce haswell_init_clock_gating

[Eugeni Dodonov]

This is based on Ivy Bridge clock gating for now, but is subject to
changes in the future.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 54 ++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 53 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0733f16..a4372b3 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3551,6 +3551,58 @@ static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
 	I915_WRITE(GEN7_FF_THREAD_MODE, reg);
 }
 
+static void haswell_init_clock_gating(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int pipe;
+	uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
+
+	I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
+
+	I915_WRITE(WM3_LP_ILK, 0);
+	I915_WRITE(WM2_LP_ILK, 0);
+	I915_WRITE(WM1_LP_ILK, 0);
+
+	/* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
+	 * This implements the WaDisableRCZUnitClockGating workaround.
+	 */
+	I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
+
+	I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
+
+	I915_WRITE(IVB_CHICKEN3,
+		   CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
+		   CHICKEN3_DGMG_DONE_FIX_DISABLE);
+
+	/* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
+	I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
+		   GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
+
+	/* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
+	I915_WRITE(GEN7_L3CNTLREG1,
+			GEN7_WA_FOR_GEN7_L3_CONTROL);
+	I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
+			GEN7_WA_L3_CHICKEN_MODE);
+
+	/* This is required by WaCatErrorRejectionIssue */
+	I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
+			I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
+			GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
+
+	for_each_pipe(pipe) {
+		I915_WRITE(DSPCNTR(pipe),
+			   I915_READ(DSPCNTR(pipe)) |
+			   DISPPLANE_TRICKLE_FEED_DISABLE);
+		intel_flush_display_plane(dev_priv, pipe);
+	}
+
+	gen7_setup_fixed_func_scheduler(dev_priv);
+
+	/* WaDisable4x2SubspanOptimization */
+	I915_WRITE(CACHE_MODE_1,
+		   _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
+}
+
 static void ivybridge_init_clock_gating(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3988,7 +4040,7 @@ void intel_init_pm(struct drm_device *dev)
 					      "Disable CxSR\n");
 				dev_priv->display.update_wm = NULL;
 			}
-			dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
+			dev_priv->display.init_clock_gating = haswell_init_clock_gating;
 			dev_priv->display.sanitize_pm = gen6_sanitize_pm;
 			dev_priv->display.force_wake_get = hsw_gt_force_wake_get;
 			dev_priv->display.force_wake_put = hsw_gt_force_wake_put;
-- 
1.7.11.1

[PATCH 19/21] drm/i915: prevent bogus intel_update_fbc notifications

[Eugeni Dodonov]

This pollutes dmesg output even if we do not have FBC for the device, so
move the DRM_DEBUG_KMS statement lower.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a4372b3..0ccdb96 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -387,14 +387,14 @@ void intel_update_fbc(struct drm_device *dev)
 	struct drm_i915_gem_object *obj;
 	int enable_fbc;
 
-	DRM_DEBUG_KMS("\n");
-
 	if (!i915_powersave)
 		return;
 
 	if (!I915_HAS_FBC(dev))
 		return;
 
+	DRM_DEBUG_KMS("\n");
+
 	/*
 	 * If FBC is already on, we just have to verify that we can
 	 * keep it that way...
-- 
1.7.11.1

[PATCH 20/21] drm/i915: fix PIPE_WM_LINETIME definition

[Eugeni Dodonov]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

Looks like a copy/paste error.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1165d2e..78b6ba4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4500,7 +4500,7 @@
 #define PIPE_WM_LINETIME_B		0x45274
 #define PIPE_WM_LINETIME(pipe) _PIPE(pipe, \
 					PIPE_WM_LINETIME_A, \
-					PIPE_WM_LINETIME_A)
+					PIPE_WM_LINETIME_B)
 #define   PIPE_WM_LINETIME_MASK		(0x1ff)
 #define   PIPE_WM_LINETIME_TIME(x)			((x))
 #define   PIPE_WM_LINETIME_IPS_LINETIME_MASK	(0x1ff<<16)
-- 
1.7.11.1

[PATCH 21/21] drm/i915: enable RC6 workaround on Haswell

[Eugeni Dodonov]

For Haswell, on some of the early hardware revisions, it is possible to
run into issues when RC6 state is enabled and when pipes change state.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 5 +++++
 drivers/gpu/drm/i915/intel_pm.c | 9 +++++++++
 2 files changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 78b6ba4..fd55e91 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4512,4 +4512,9 @@
 #define  SFUSE_STRAP_DDIC_DETECTED	(1<<1)
 #define  SFUSE_STRAP_DDID_DETECTED	(1<<0)
 
+#define WM_DBG				0x45280
+#define  WM_DBG_DISALLOW_MULTIPLE_LP	(1<<0)
+#define  WM_DBG_DISALLOW_MAXFIFO	(1<<1)
+#define  WM_DBG_DISALLOW_SPRITE		(1<<2)
+
 #endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0ccdb96..cc8628c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3601,6 +3601,15 @@ static void haswell_init_clock_gating(struct drm_device *dev)
 	/* WaDisable4x2SubspanOptimization */
 	I915_WRITE(CACHE_MODE_1,
 		   _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
+
+	/* Work-around rc6 issue */
+	I915_WRITE(WM_DBG,
+			I915_READ(WM_DBG) |
+			WM_DBG_DISALLOW_MULTIPLE_LP |
+			WM_DBG_DISALLOW_SPRITE |
+			WM_DBG_DISALLOW_MAXFIFO
+		  );
+
 }
 
 static void ivybridge_init_clock_gating(struct drm_device *dev)
-- 
1.7.11.1

Re: [PATCH 00/21] More Haswell patches

[Paulo Zanoni]

2012/6/28 Eugeni Dodonov <eugeni.dodonov@intel.com>:>
> Also, for DP and eDP, Paulo Zanoni and Shobhit Kumar are already working on a
> larger series of patches which should appear in the next few days as well.  So
> while the patches in this series should work on most configurations,
> considerable amount of improvements are still to come.
>

DP patches are 1->6 and eDP patches are 14->17. We could try to get
patches 7->13 and 18->21 merged first if they don't receive
objections. DP/eDP then can come on top of those. It seems there's no
conflict in reordering the patches.


-- 
Paulo Zanoni

Re: [PATCH 21/21] drm/i915: enable RC6 workaround on Haswell

[Daniel Vetter]

On Thu, Jun 28, 2012 at 03:55:49PM -0300, Eugeni Dodonov wrote:
> For Haswell, on some of the early hardware revisions, it is possible to
> run into issues when RC6 state is enabled and when pipes change state.
> 
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>

Given that this is a w/a that only applies for early silicon, please add a
comment that this should get nuked once production stuff ships.
-Daniel

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 5 +++++
>  drivers/gpu/drm/i915/intel_pm.c | 9 +++++++++
>  2 files changed, 14 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 78b6ba4..fd55e91 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4512,4 +4512,9 @@
>  #define  SFUSE_STRAP_DDIC_DETECTED	(1<<1)
>  #define  SFUSE_STRAP_DDID_DETECTED	(1<<0)
>  
> +#define WM_DBG				0x45280
> +#define  WM_DBG_DISALLOW_MULTIPLE_LP	(1<<0)
> +#define  WM_DBG_DISALLOW_MAXFIFO	(1<<1)
> +#define  WM_DBG_DISALLOW_SPRITE		(1<<2)
> +
>  #endif /* _I915_REG_H_ */
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 0ccdb96..cc8628c 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3601,6 +3601,15 @@ static void haswell_init_clock_gating(struct drm_device *dev)
>  	/* WaDisable4x2SubspanOptimization */
>  	I915_WRITE(CACHE_MODE_1,
>  		   _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
> +
> +	/* Work-around rc6 issue */
> +	I915_WRITE(WM_DBG,
> +			I915_READ(WM_DBG) |
> +			WM_DBG_DISALLOW_MULTIPLE_LP |
> +			WM_DBG_DISALLOW_SPRITE |
> +			WM_DBG_DISALLOW_MAXFIFO
> +		  );
> +
>  }
>  
>  static void ivybridge_init_clock_gating(struct drm_device *dev)
> -- 
> 1.7.11.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH 19/21] drm/i915: prevent bogus intel_update_fbc notifications

[Daniel Vetter]

On Thu, Jun 28, 2012 at 03:55:47PM -0300, Eugeni Dodonov wrote:
> This pollutes dmesg output even if we do not have FBC for the device, so
> move the DRM_DEBUG_KMS statement lower.
> 
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>

I suggest we just kill this right away ;-)
-Daniel
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index a4372b3..0ccdb96 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -387,14 +387,14 @@ void intel_update_fbc(struct drm_device *dev)
>  	struct drm_i915_gem_object *obj;
>  	int enable_fbc;
>  
> -	DRM_DEBUG_KMS("\n");
> -
>  	if (!i915_powersave)
>  		return;
>  
>  	if (!I915_HAS_FBC(dev))
>  		return;
>  
> +	DRM_DEBUG_KMS("\n");
> +
>  	/*
>  	 * If FBC is already on, we just have to verify that we can
>  	 * keep it that way...
> -- 
> 1.7.11.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH 12/21] drm/i915: support Haswell-style force waking

[Daniel Vetter]

On Thu, Jun 28, 2012 at 03:55:40PM -0300, Eugeni Dodonov wrote:
> On Haswell, there is a different register for reading force wake ACKs, and
> all the writes should go into the multi-threaded register, even for the
> legacy force wake.
> 
> Also, we have a theorical possibility for the force wake sequence to
> awaken the GT, but return while it hasn't finished bringing up the queue.
> So we properly check those bits as well, to ensure we won't end up in
> half-woken situation.
> 
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>

This patch didn't survive review with the *shhh* intel top secret *ssshhh*
power docs ;-) It looks like we're supposed to poll for the ack from the
hw on the _same_ reg as we've used in the MT forcewake register until the
bit is set (for get) or cleared (for put).

Also, calling the helper function hsw_wait_gt_ack makes more sense then.
-Daniel


> ---
>  drivers/gpu/drm/i915/i915_drv.c | 36 +++++++++++++++++++++++++++++++++++-
>  drivers/gpu/drm/i915/i915_drv.h |  3 +++
>  drivers/gpu/drm/i915/i915_reg.h |  1 +
>  drivers/gpu/drm/i915/intel_pm.c |  4 +++-
>  4 files changed, 42 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 79be879..73fd38a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -536,6 +536,39 @@ int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
>  	return ret;
>  }
>  
> +static inline void __hsw_wait_gt_awake(struct drm_i915_private *dev_priv)
> +{
> +	int count = 0;
> +
> +	while (count++ < 50) {
> +		u32 tmp = I915_READ_NOTRACE(FORCEWAKE_ACK_HSW);
> +		if ((tmp & 1) && !(tmp & _MASKED_BIT_ENABLE(~7)))
> +			break;
> +		udelay(10);
> +	}
> +}
> +
> +
> +void hsw_gt_force_wake_get(struct drm_i915_private *dev_priv)
> +{
> +	__hsw_wait_gt_awake(dev_priv);
> +
> +	I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(1));
> +	POSTING_READ(FORCEWAKE_MT);
> +
> +	__hsw_wait_gt_awake(dev_priv);
> +}
> +
> +void hsw_gt_force_wake_put(struct drm_i915_private *dev_priv)
> +{
> +	I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(1));
> +
> +	__hsw_wait_gt_awake(dev_priv);
> +
> +	/* The below doubles as a POSTING_READ */
> +	gen6_gt_check_fifodbg(dev_priv);
> +}
> +
>  void vlv_force_wake_get(struct drm_i915_private *dev_priv)
>  {
>  	int count;
> @@ -1161,7 +1194,8 @@ MODULE_LICENSE("GPL and additional rights");
>  #define NEEDS_FORCE_WAKE(dev_priv, reg) \
>  	((HAS_FORCE_WAKE((dev_priv)->dev)) && \
>  	 ((reg) < 0x40000) &&            \
> -	 ((reg) != FORCEWAKE))
> +	 ((reg) != FORCEWAKE) &&         \
> +	 ((reg) != FORCEWAKE_MT))
>  
>  static bool IS_DISPLAYREG(u32 reg)
>  {
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index a0c15ab..e4916a0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1525,6 +1525,9 @@ extern void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv);
>  extern void vlv_force_wake_get(struct drm_i915_private *dev_priv);
>  extern void vlv_force_wake_put(struct drm_i915_private *dev_priv);
>  
> +extern void hsw_gt_force_wake_get(struct drm_i915_private *dev_priv);
> +extern void hsw_gt_force_wake_put(struct drm_i915_private *dev_priv);
> +
>  /* overlay */
>  #ifdef CONFIG_DEBUG_FS
>  extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 284965b..2c4be2e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4070,6 +4070,7 @@
>  #define  FORCEWAKE				0xA18C
>  #define  FORCEWAKE_VLV				0x1300b0
>  #define  FORCEWAKE_ACK_VLV			0x1300b4
> +#define  FORCEWAKE_ACK_HSW			0x130044
>  #define  FORCEWAKE_ACK				0x130090
>  #define  FORCEWAKE_MT				0xa188 /* multi-threaded */
>  #define  FORCEWAKE_MT_ACK			0x130040
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 99bc1f3..0334e42 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3769,7 +3769,7 @@ void intel_init_pm(struct drm_device *dev)
>  		dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
>  
>  		/* IVB configs may use multi-threaded forcewake */
> -		if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
> +		if (IS_IVYBRIDGE(dev)) {
>  			u32	ecobus;
>  
>  			/* A small trick here - if the bios hasn't configured MT forcewake,
> @@ -3842,6 +3842,8 @@ void intel_init_pm(struct drm_device *dev)
>  			}
>  			dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
>  			dev_priv->display.sanitize_pm = gen6_sanitize_pm;
> +			dev_priv->display.force_wake_get = hsw_gt_force_wake_get;
> +			dev_priv->display.force_wake_put = hsw_gt_force_wake_put;
>  		} else
>  			dev_priv->display.update_wm = NULL;
>  	} else if (IS_VALLEYVIEW(dev)) {
> -- 
> 1.7.11.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH 20/21] drm/i915: fix PIPE_WM_LINETIME definition

[Daniel Vetter]

On Thu, Jun 28, 2012 at 03:55:48PM -0300, Eugeni Dodonov wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> Looks like a copy/paste error.
> 
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Queued for -next, thanks for the patch.
-Daniel
-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

[PATCH 12/21] drm/i915: support Haswell-style force waking

[Eugeni Dodonov]

On Haswell, there is a different register for reading force wake ACKs.

v2: simplify forcewake dance and therefore the commit message as noticed
by Daniel Vetter.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 10 ++++++++--
 drivers/gpu/drm/i915/i915_reg.h |  1 +
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 79be879..23ae450 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -451,16 +451,22 @@ void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
 void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
 {
 	int count;
+	u32 forcewake_ack;
+
+	if (IS_HASWELL(dev_priv->dev))
+		forcewake_ack = FORCEWAKE_ACK_HSW;
+	else
+		forcewake_ack = FORCEWAKE_MT_ACK;
 
 	count = 0;
-	while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1))
+	while (count++ < 50 && (I915_READ_NOTRACE(forcewake_ack) & 1))
 		udelay(10);
 
 	I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(1));
 	POSTING_READ(FORCEWAKE_MT);
 
 	count = 0;
-	while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1) == 0)
+	while (count++ < 50 && (I915_READ_NOTRACE(forcewake_ack) & 1) == 0)
 		udelay(10);
 }
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 284965b..2c4be2e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4070,6 +4070,7 @@
 #define  FORCEWAKE				0xA18C
 #define  FORCEWAKE_VLV				0x1300b0
 #define  FORCEWAKE_ACK_VLV			0x1300b4
+#define  FORCEWAKE_ACK_HSW			0x130044
 #define  FORCEWAKE_ACK				0x130090
 #define  FORCEWAKE_MT				0xa188 /* multi-threaded */
 #define  FORCEWAKE_MT_ACK			0x130040
-- 
1.7.11.1

[PATCH 21/21] drm/i915: enable RC6 workaround on Haswell

[Eugeni Dodonov]

For Haswell, on some of the early hardware revisions, it is possible to
run into issues when RC6 state is enabled and when pipes change state.

v2: add comment saying that this is for early revisions only.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |  5 +++++
 drivers/gpu/drm/i915/intel_pm.c | 12 ++++++++++++
 2 files changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 78b6ba4..fd55e91 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4512,4 +4512,9 @@
 #define  SFUSE_STRAP_DDIC_DETECTED	(1<<1)
 #define  SFUSE_STRAP_DDID_DETECTED	(1<<0)
 
+#define WM_DBG				0x45280
+#define  WM_DBG_DISALLOW_MULTIPLE_LP	(1<<0)
+#define  WM_DBG_DISALLOW_MAXFIFO	(1<<1)
+#define  WM_DBG_DISALLOW_SPRITE		(1<<2)
+
 #endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0422e2d..40f2f53 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3601,6 +3601,18 @@ static void haswell_init_clock_gating(struct drm_device *dev)
 	/* WaDisable4x2SubspanOptimization */
 	I915_WRITE(CACHE_MODE_1,
 		   _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
+
+	/* Work-around rc6 issue */
+	/* XXX: This is a workaround for early silicon revisions and should be
+	 * removed later
+	 */
+	I915_WRITE(WM_DBG,
+			I915_READ(WM_DBG) |
+			WM_DBG_DISALLOW_MULTIPLE_LP |
+			WM_DBG_DISALLOW_SPRITE |
+			WM_DBG_DISALLOW_MAXFIFO
+		  );
+
 }
 
 static void ivybridge_init_clock_gating(struct drm_device *dev)
-- 
1.7.11.1

[PATCH 19/21] drm/i915: prevent bogus intel_update_fbc notifications

[Eugeni Dodonov]

This pollutes dmesg output even if we do not have FBC for the device, so
move the DRM_DEBUG_KMS statement lower.

v2: just kill the message as suggested by Daniel.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 53645f1..42e847c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -387,8 +387,6 @@ void intel_update_fbc(struct drm_device *dev)
 	struct drm_i915_gem_object *obj;
 	int enable_fbc;
 
-	DRM_DEBUG_KMS("\n");
-
 	if (!i915_powersave)
 		return;
 
-- 
1.7.11.1

Re: [PATCH 13/21] drm/i915: add RPS configuration for Haswell

[Daniel Vetter]

On Thu, Jun 28, 2012 at 03:55:41PM -0300, Eugeni Dodonov wrote:
> Split Haswell-specific GT algorithms into its own function.
> 
> Note that Haswell only has RC6, so account for that as well.
> 
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h |   1 +
>  drivers/gpu/drm/i915/intel_pm.c | 160 ++++++++++++++++++++++++++++++++++++++--
>  2 files changed, 155 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 2c4be2e..0c53e4a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4131,6 +4131,7 @@
>  #define   GEN6_RP_UP_IDLE_MIN			(0x1<<3)
>  #define   GEN6_RP_UP_BUSY_AVG			(0x2<<3)
>  #define   GEN6_RP_UP_BUSY_CONT			(0x4<<3)
> +#define   GEN7_RP_DOWN_IDLE_AVG			(0x2<<0)
>  #define   GEN6_RP_DOWN_IDLE_CONT		(0x1<<0)
>  #define GEN6_RP_UP_THRESHOLD			0xA02C
>  #define GEN6_RP_DOWN_THRESHOLD			0xA030
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 0334e42..0733f16 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2301,6 +2301,26 @@ void gen6_set_rps(struct drm_device *dev, u8 val)
>  	dev_priv->cur_delay = val;
>  }
>  
> +static void hsw_disable_rps(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +
> +	I915_WRITE(GEN6_RC_CONTROL, 0);
> +	I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
> +	I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
> +	I915_WRITE(GEN6_PMIER, 0);
> +	/* Complete PM interrupt masking here doesn't race with the rps work
> +	 * item again unmasking PM interrupts because that is using a different
> +	 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
> +	 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
> +
> +	spin_lock_irq(&dev_priv->rps_lock);
> +	dev_priv->pm_iir = 0;
> +	spin_unlock_irq(&dev_priv->rps_lock);
> +
> +	I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
> +}

The only difference I can see wrt gen6_disable_rps is clearing the
RC_CONTROL reg. And that looks like a bugfix that gen6+ should get, too.
Imo copy&pasting this function hence doesn't make sense.

> +
>  static void gen6_disable_rps(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -2334,9 +2354,10 @@ int intel_enable_rc6(const struct drm_device *dev)
>  	if (INTEL_INFO(dev)->gen == 5)
>  		return 0;
>  
> -	/* Sorry Haswell, no RC6 for you for now. */
> +	/* Haswell does not has RC6p nor RC6pp
> +	 */
>  	if (IS_HASWELL(dev))
> -		return 0;
> +		return INTEL_RC6_ENABLE;
>  
>  	/*
>  	 * Disable rc6 on Sandybridge
> @@ -2349,6 +2370,130 @@ int intel_enable_rc6(const struct drm_device *dev)
>  	return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
>  }
>  
> +static void hsw_enable_rps(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_ring_buffer *ring;
> +	u32 pcu_mbox, rc6_mask = 0;
> +	int rc6_mode;
> +	int i;
> +
> +	WARN_ON(!mutex_is_locked(&dev->struct_mutex));
> +
> +	/* Here begins a magic sequence of register writes to enable
> +	 * auto-downclocking.
> +	 *
> +	 * Perhaps there might be some value in exposing these to
> +	 * userspace...
> +	 */
> +	I915_WRITE(GEN6_RC_STATE, 0);
> +
> +	gen6_gt_force_wake_get(dev_priv);
> +
> +	/* In units of 100MHz */
> +	dev_priv->max_delay = 18;
> +	dev_priv->min_delay = 6;
> +	dev_priv->cur_delay = 0;

gen6 enable_rps reads these magic values from regs. Shouldn't we do that
for hsw, too?

> +
> +	/* disable the counters and set deterministic thresholds */
> +	I915_WRITE(GEN6_RC_CONTROL, 0);
> +
> +	I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
> +	I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
> +	I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
> +	I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
> +
> +	for_each_ring(ring, dev_priv, i)
> +		I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
> +
> +	I915_WRITE(GEN6_RC_SLEEP, 0);
> +	I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
> +	I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
> +
> +	rc6_mode = intel_enable_rc6(dev_priv->dev);
> +
> +	if (rc6_mode & INTEL_RC6_ENABLE)
> +		rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
> +
> +	DRM_INFO("Enabling RC6 states on Haswell: RC6 %s\n",
> +			(rc6_mode & INTEL_RC6_ENABLE) ? "on" : "off");
> +
> +	I915_WRITE(GEN6_RC_CONTROL,
> +		   rc6_mask |
> +		   GEN6_RC_CTL_EI_MODE(1) |
> +		   GEN6_RC_CTL_HW_ENABLE);
> +
> +	I915_WRITE(GEN6_RPNSWREQ,
> +		   GEN6_FREQUENCY(10) |
> +		   GEN6_OFFSET(0) |
> +		   GEN6_AGGRESSIVE_TURBO);
> +	I915_WRITE(GEN6_RC_VIDEO_FREQ,
> +		   GEN6_FREQUENCY(12));
> +
> +	I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
> +	I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
> +		   dev_priv->max_delay << 24 |
> +		   dev_priv->min_delay << 16);
> +	I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
> +	I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
> +	I915_WRITE(GEN6_RP_UP_EI, 66000);
> +	I915_WRITE(GEN6_RP_DOWN_EI, 350000);
> +	I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
> +	I915_WRITE(GEN6_RP_CONTROL,
> +		   GEN6_RP_MEDIA_TURBO |
> +		   GEN6_RP_MEDIA_HW_MODE |

I figure this should be changed like the gen6 rps code in 89ba829e ...

> +		   GEN6_RP_MEDIA_IS_GFX |
> +		   GEN6_RP_ENABLE |
> +		   GEN6_RP_UP_BUSY_AVG |
> +		   GEN7_RP_DOWN_IDLE_AVG);
> +
> +	if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
> +		     500))
> +		DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
> +
> +	I915_WRITE(GEN6_PCODE_DATA, 0);
> +	I915_WRITE(GEN6_PCODE_MAILBOX,
> +		   GEN6_PCODE_READY |
> +		   GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
> +	if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
> +		     500))
> +		DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
> +
> +	/* Check for overclock support */
> +	if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
> +		     500))
> +		DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
> +	I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
> +	pcu_mbox = I915_READ(GEN6_PCODE_DATA);
> +	if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
> +		     500))
> +		DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
> +	if (pcu_mbox & (1<<31)) { /* OC supported */
> +		dev_priv->max_delay = pcu_mbox & 0xff;
> +		DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
> +	}
> +
> +	/* requires MSI enabled */
> +	I915_WRITE(GEN6_PMIER,
> +		   GEN6_PM_MBOX_EVENT |
> +		   GEN6_PM_THERMAL_EVENT |
> +		   GEN6_PM_RP_DOWN_TIMEOUT |
> +		   GEN6_PM_RP_UP_THRESHOLD |
> +		   GEN6_PM_RP_DOWN_THRESHOLD |
> +		   GEN6_PM_RP_UP_EI_EXPIRED |
> +		   GEN6_PM_RP_DOWN_EI_EXPIRED);
> +
> +	spin_lock_irq(&dev_priv->rps_lock);
> +	WARN_ON(dev_priv->pm_iir != 0);
> +	I915_WRITE(GEN6_PMIMR, 0);
> +	spin_unlock_irq(&dev_priv->rps_lock);
> +
> +	/* enable all PM interrupts */
> +	I915_WRITE(GEN6_PMINTRMSK, 0);
> +
> +	gen6_gt_force_wake_put(dev_priv);
> +}

Ok, after reviewing this with the gen6 code and hsw power doc I see very
few differences (besides the 2 things that look like mistakes):
- we don't set a few things related to rc6p&rc6pp
- we have slightly different timeout/threshold values.

When copy&pasting code we should balance the risk of introducing
regressions with the risk to not apply bugfixes everywhere they're needed.
Given that you've missed Jesse's fix while hacking on this and that this
seems to work very much like rps on snb/ivb I'd vote for sprinkling a few
ifs into gen6_enable_rps. Maybe set the timing values in local variables
at the beginning of the function.
-Daniel

> +
>  static void gen6_enable_rps(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -3227,7 +3372,9 @@ void intel_disable_gt_powersave(struct drm_device *dev)
>  {
>  	if (IS_IRONLAKE_M(dev))
>  		ironlake_disable_drps(dev);
> -	if (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev))
> +	else if (IS_HASWELL(dev))
> +		hsw_disable_rps(dev);
> +	else if (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev))
>  		gen6_disable_rps(dev);
>  }
>  
> @@ -3237,9 +3384,10 @@ void intel_enable_gt_powersave(struct drm_device *dev)
>  		ironlake_enable_drps(dev);
>  		ironlake_enable_rc6(dev);
>  		intel_init_emon(dev);
> -	}
> -
> -	if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
> +	} else if (IS_HASWELL(dev)) {
> +		hsw_enable_rps(dev);
> +		gen6_update_ring_freq(dev);
> +	} else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
>  		gen6_enable_rps(dev);
>  		gen6_update_ring_freq(dev);
>  	}
> -- 
> 1.7.11.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH 13/21] drm/i915: add RPS configuration for Haswell

[Eugeni Dodonov]

On 06/29/2012 06:56 AM, Daniel Vetter wrote:
> Ok, after reviewing this with the gen6 code and hsw power doc I see very
> few differences (besides the 2 things that look like mistakes):
> - we don't set a few things related to rc6p&rc6pp
> - we have slightly different timeout/threshold values.
> 
> When copy&pasting code we should balance the risk of introducing
> regressions with the risk to not apply bugfixes everywhere they're needed.
> Given that you've missed Jesse's fix while hacking on this and that this
> seems to work very much like rps on snb/ivb I'd vote for sprinkling a few
> ifs into gen6_enable_rps. Maybe set the timing values in local variables
> at the beginning of the function.

Sure, I'll do this and send the patch.

Eugeni

Re: [PATCH 19/21] drm/i915: prevent bogus intel_update_fbc notifications

[Paulo Zanoni]

2012/6/28 Eugeni Dodonov <eugeni.dodonov@intel.com>:
> This pollutes dmesg output even if we do not have FBC for the device, so
> move the DRM_DEBUG_KMS statement lower.
>
> v2: just kill the message as suggested by Daniel.
>
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>

The message first says we "move the statement lower", but then later
it says we kill the message :)
With that fixed:

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

I'm happy with both v1 and v2.

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 2 --
>  1 file changed, 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 53645f1..42e847c 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -387,8 +387,6 @@ void intel_update_fbc(struct drm_device *dev)
>         struct drm_i915_gem_object *obj;
>         int enable_fbc;
>
> -       DRM_DEBUG_KMS("\n");
> -
>         if (!i915_powersave)
>                 return;
>
> --
> 1.7.11.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Paulo Zanoni

Re: [PATCH 10/21] drm/i915: introduce lpt_enable_pch and cpt_enable_pch

[Paulo Zanoni]

Hi

I certainly like this function split. Reviews inline:

2012/6/28 Eugeni Dodonov <eugeni.dodonov@intel.com>:
> CPT/PPT and LPT have different functionality. So we introduce specific
> functions to handle each of them instead of using multiple if..
> statements.
>
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 70 ++++++++++++++++++++++++++++++++----
>  1 file changed, 63 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index d7b337b..9a695ab 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2968,6 +2968,51 @@ static void lpt_program_iclkip(struct drm_crtc *crtc)
>         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
>  }
>
> +/* On Lynx Point, the PCH part is different, as it has one FDI RX, one
> + * transcoder, and the clock is driven by iCLKIP.
> + */
> +static void lpt_pch_enable(struct drm_crtc *crtc)
> +{
> +       struct drm_device *dev = crtc->dev;
> +       struct drm_i915_private *dev_priv = dev->dev_private;
> +       struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> +       int pipe = intel_crtc->pipe;
> +
> +       /* On LPT, there is only one FDI RX and transcoder, which can be driven
> +        * by any pipe. To simplify, we consider that only pipeA can be used in
> +        * such mode.
> +        */
> +       if (HAS_PCH_LPT(dev_priv->dev)) {
> +               if (pipe > 0) {
> +                       DRM_ERROR("Attempting to enable PCH port with pipe > 0\n");
> +                       return;
> +               }
> +       }

It looks like the check above could go on a separate commit. The first
commit just moves code around, the second one adds the check.

I may have misunderstood something about this code which is not
familiar to me, but instead of limiting everything to pipe 0, can't we
just iterate through all pipes, read DDI_FUNC_CTL(pipe) and see if
there's any other enabled pipe on FDI mode?

> +
> +       assert_transcoder_disabled(dev_priv, pipe);
> +
> +       /* For PCH output, training FDI link */
> +       dev_priv->display.fdi_link_train(crtc);
> +
> +       intel_enable_pch_pll(intel_crtc);
> +
> +       DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");

This message could go inside lpt_program_iclkip :) We should also
paint it green.

> +       lpt_program_iclkip(crtc);
> +
> +       /* set transcoder timing, panel must allow it */
> +       assert_panel_unlocked(dev_priv, pipe);
> +       I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
> +       I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
> +       I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
> +
> +       I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
> +       I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
> +       I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
> +       I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
> +
> +       intel_enable_transcoder(dev_priv, pipe);
> +}
> +
>  /*
>   * Enable PCH resources required for PCH ports:
>   *   - PCH PLLs
> @@ -2976,7 +3021,7 @@ static void lpt_program_iclkip(struct drm_crtc *crtc)
>   *   - DP transcoding bits
>   *   - transcoder
>   */
> -static void ironlake_pch_enable(struct drm_crtc *crtc)
> +static void cpt_pch_enable(struct drm_crtc *crtc)

Since this will run on both IBX and CPT, shouldn't we call it
ibx_pch_enable? At least on intel_hdmi.c, the functions are named
after the earliest generation that can run them.

>  {
>         struct drm_device *dev = crtc->dev;
>         struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -2991,10 +3036,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
>
>         intel_enable_pch_pll(intel_crtc);
>
> -       if (HAS_PCH_LPT(dev)) {
> -               DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
> -               lpt_program_iclkip(crtc);
> -       } else if (HAS_PCH_CPT(dev)) {
> +       if (HAS_PCH_CPT(dev)) {
>                 u32 sel;
>
>                 temp = I915_READ(PCH_DPLL_SEL);
> @@ -3031,8 +3073,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
>         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
>         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
>
> -       if (!IS_HASWELL(dev))
> -               intel_fdi_normal_train(crtc);
> +       intel_fdi_normal_train(crtc);
>
>         /* For PCH DP, enable TRANS_DP_CTL */
>         if (HAS_PCH_CPT(dev) &&
> @@ -3075,6 +3116,21 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
>         intel_enable_transcoder(dev_priv, pipe);
>  }
>
> +/*
> + * When we need to use a PCH port, we can go through different paths on CPT/PPT
> + * and LPT chipsets.
> + */
> +static void ironlake_pch_enable(struct drm_crtc *crtc)
> +{
> +       struct drm_device *dev = crtc->dev;
> +       struct drm_i915_private *dev_priv = dev->dev_private;
> +
> +       if (HAS_PCH_LPT(dev_priv->dev))
> +               return lpt_pch_enable(crtc);
> +       else
> +               return cpt_pch_enable(crtc);
> +}
> +
>  static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
>  {
>         struct intel_pch_pll *pll = intel_crtc->pch_pll;
> --
> 1.7.11.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Paulo Zanoni

Re: [PATCH 07/21] drm/i915: re-initialize DDI buffer translations after resume

[Paulo Zanoni]

2012/6/28 Eugeni Dodonov <eugeni.dodonov@intel.com>:
> This is necessary for the modesetting to work correctly after a
> suspend-resume cycle. Without this, the pipes and clocks got the correct
> configuration, but the underlying DDI buffers configuration was lost.
>
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>

I couldn't make suspend/resume work on my machine yet, but running
intel_prepare_ddi again after resume won't hurt us, so:

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_display.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 28bee8a..76508a7 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -7179,6 +7179,8 @@ static void ivb_pch_pwm_override(struct drm_device *dev)
>
>  void intel_modeset_init_hw(struct drm_device *dev)
>  {
> +       intel_prepare_ddi(dev);
> +
>         intel_init_clock_gating(dev);
>
>         mutex_lock(&dev->struct_mutex);
> @@ -7208,8 +7210,6 @@ void intel_modeset_init(struct drm_device *dev)
>
>         intel_init_pm(dev);
>
> -       intel_prepare_ddi(dev);
> -
>         intel_init_display(dev);
>
>         if (IS_GEN2(dev)) {
> --
> 1.7.11.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Paulo Zanoni

Re: [PATCH 07/21] drm/i915: re-initialize DDI buffer translations after resume

[Daniel Vetter]

On Wed, Jul 04, 2012 at 05:07:39PM -0300, Paulo Zanoni wrote:
> 2012/6/28 Eugeni Dodonov <eugeni.dodonov@intel.com>:
> > This is necessary for the modesetting to work correctly after a
> > suspend-resume cycle. Without this, the pipes and clocks got the correct
> > configuration, but the underlying DDI buffers configuration was lost.
> >
> > Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
> 
> I couldn't make suspend/resume work on my machine yet, but running
> intel_prepare_ddi again after resume won't hurt us, so:
> 
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

Queued for -next, thanks for the patch. Quick aside: I think we have a
similar issue with the hsw power well init code.
-Daniel
> 
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 28bee8a..76508a7 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -7179,6 +7179,8 @@ static void ivb_pch_pwm_override(struct drm_device *dev)
> >
> >  void intel_modeset_init_hw(struct drm_device *dev)
> >  {
> > +       intel_prepare_ddi(dev);
> > +
> >         intel_init_clock_gating(dev);
> >
> >         mutex_lock(&dev->struct_mutex);
> > @@ -7208,8 +7210,6 @@ void intel_modeset_init(struct drm_device *dev)
> >
> >         intel_init_pm(dev);
> >
> > -       intel_prepare_ddi(dev);
> > -
> >         intel_init_display(dev);
> >
> >         if (IS_GEN2(dev)) {
> > --
> > 1.7.11.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> 
> 
> -- 
> Paulo Zanoni
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH 11/21] drm/i915: program FDI_RX TP and FDI delays

[Paulo Zanoni]

Hi

2012/6/28 Eugeni Dodonov <eugeni.dodonov@intel.com>:
> This is required for a stable FDI connection.
>
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h  |  3 +++
>  drivers/gpu/drm/i915/intel_ddi.c | 10 ++++++++++
>  2 files changed, 13 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5b0c5f6..284965b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3849,6 +3849,9 @@
>  #define _FDI_RXA_TUSIZE2         0xf0038
>  #define _FDI_RXB_TUSIZE1         0xf1030
>  #define _FDI_RXB_TUSIZE2         0xf1038
> +#define  FDI_RX_TP1_TO_TP2_48  (10<<20)
> +#define  FDI_RX_TP1_TO_TP2_64  (11<<20)

Isn't this supposed to be (2 << 20) and (3 << 20)?

> +#define  FDI_RX_FDI_DELAY_90   (0x90<<0)
>  #define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
>  #define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
>  #define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index effb263..1c76d20 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -170,6 +170,16 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
>
>                 udelay(600);
>
> +               /* We need to program FDI_RX_MISC with the default TP1 to TP2
> +                * values before enabling the receiver, and configure the delay
> +                * for the FDI timing generator to 90h.
> +                */
> +               reg = FDI_RX_MISC(pipe);
> +               temp = I915_READ(reg);
> +               temp |= FDI_RX_TP1_TO_TP2_48 |
> +                       FDI_RX_FDI_DELAY_90;

Shouldn't we mask bits 27:26, 25:24, 21:20 and 12:0 first?

> +               I915_WRITE(reg, temp);
> +
>                 /* Enable CPU FDI Receiver with auto-training */
>                 reg = FDI_RX_CTL(pipe);
>                 I915_WRITE(reg,
> --
> 1.7.11.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Paulo Zanoni

Re: [PATCH 07/21] drm/i915: re-initialize DDI buffer translations after resume

[Eugeni Dodonov]

On 07/04/2012 05:35 PM, Daniel Vetter wrote:
> On Wed, Jul 04, 2012 at 05:07:39PM -0300, Paulo Zanoni wrote:
>> 2012/6/28 Eugeni Dodonov <eugeni.dodonov@intel.com>:
>>> This is necessary for the modesetting to work correctly after a
>>> suspend-resume cycle. Without this, the pipes and clocks got the correct
>>> configuration, but the underlying DDI buffers configuration was lost.
>>>
>>> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
>>
>> I couldn't make suspend/resume work on my machine yet, but running
>> intel_prepare_ddi again after resume won't hurt us, so:
>>
>> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> Queued for -next, thanks for the patch. Quick aside: I think we have a
> similar issue with the hsw power well init code.

Yes, I'll send the power wells patch until the end of the week as well,
sorry for taking that long!

Eugeni

[PATCH 10/31] drm/i915: program FDI_RX TP and FDI delays

[Eugeni Dodonov]

This is required for a stable FDI connection.

v2: fix and simplify the FDI_RX_MISC bits as noticed by Paulo Zanoni.

CC: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  | 3 +++
 drivers/gpu/drm/i915/intel_ddi.c | 9 +++++++++
 2 files changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5b0c5f6..287d277 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3849,6 +3849,9 @@
 #define _FDI_RXA_TUSIZE2         0xf0038
 #define _FDI_RXB_TUSIZE1         0xf1030
 #define _FDI_RXB_TUSIZE2         0xf1038
+#define  FDI_RX_TP1_TO_TP2_48	(2<<20)
+#define  FDI_RX_TP1_TO_TP2_64	(3<<20)
+#define  FDI_RX_FDI_DELAY_90	(0x90<<0)
 #define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
 #define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
 #define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index effb263..2d5acd2 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -170,6 +170,15 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
 
 		udelay(600);
 
+		/* We need to program FDI_RX_MISC with the default TP1 to TP2
+		 * values before enabling the receiver, and configure the delay
+		 * for the FDI timing generator to 90h. Luckily, all the other
+		 * bits are supposed to be zeroed, so we can write those values
+		 * directly.
+		 */
+		I915_WRITE(FDI_RX_MISC(pipe), FDI_RX_TP1_TO_TP2_48 |
+				FDI_RX_FDI_DELAY_90);
+
 		/* Enable CPU FDI Receiver with auto-training */
 		reg = FDI_RX_CTL(pipe);
 		I915_WRITE(reg,
-- 
1.7.11.1

Re: [PATCH 19/21] drm/i915: prevent bogus intel_update_fbc notifications

[Eugeni Dodonov]

On 07/04/2012 02:41 PM, Paulo Zanoni wrote:
> 2012/6/28 Eugeni Dodonov <eugeni.dodonov@intel.com>:
>> This pollutes dmesg output even if we do not have FBC for the device, so
>> move the DRM_DEBUG_KMS statement lower.
>>
>> v2: just kill the message as suggested by Daniel.
>>
>> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
> 
> The message first says we "move the statement lower", but then later
> it says we kill the message :)
> With that fixed:
> 
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> I'm happy with both v1 and v2.

I'll let Daniel decide the bike shed color on this one :). We can always
say that 'move it down' was a slang term for 'killing' later :).

Eugeni

Re: [PATCH 19/21] drm/i915: prevent bogus intel_update_fbc notifications

[Daniel Vetter]

On Wed, Jul 04, 2012 at 08:19:24PM -0300, Eugeni Dodonov wrote:
> On 07/04/2012 02:41 PM, Paulo Zanoni wrote:
> > 2012/6/28 Eugeni Dodonov <eugeni.dodonov@intel.com>:
> >> This pollutes dmesg output even if we do not have FBC for the device, so
> >> move the DRM_DEBUG_KMS statement lower.
> >>
> >> v2: just kill the message as suggested by Daniel.
> >>
> >> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
> > 
> > The message first says we "move the statement lower", but then later
> > it says we kill the message :)
> > With that fixed:
> > 
> > Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > 
> > I'm happy with both v1 and v2.
> 
> I'll let Daniel decide the bike shed color on this one :). We can always
> say that 'move it down' was a slang term for 'killing' later :).

I've already merged it, but forgot to send out the ack mail ;-)
-Daniel
-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH 10/31] drm/i915: program FDI_RX TP and FDI delays

[Paulo Zanoni]

2012/7/4 Eugeni Dodonov <eugeni.dodonov@intel.com>:
> This is required for a stable FDI connection.
>
> v2: fix and simplify the FDI_RX_MISC bits as noticed by Paulo Zanoni.
>
> CC: Paulo Zanoni <paulo.r.zanoni@intel.com>

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h  | 3 +++
>  drivers/gpu/drm/i915/intel_ddi.c | 9 +++++++++
>  2 files changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5b0c5f6..287d277 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3849,6 +3849,9 @@
>  #define _FDI_RXA_TUSIZE2         0xf0038
>  #define _FDI_RXB_TUSIZE1         0xf1030
>  #define _FDI_RXB_TUSIZE2         0xf1038
> +#define  FDI_RX_TP1_TO_TP2_48  (2<<20)
> +#define  FDI_RX_TP1_TO_TP2_64  (3<<20)
> +#define  FDI_RX_FDI_DELAY_90   (0x90<<0)
>  #define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
>  #define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
>  #define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index effb263..2d5acd2 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -170,6 +170,15 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
>
>                 udelay(600);
>
> +               /* We need to program FDI_RX_MISC with the default TP1 to TP2
> +                * values before enabling the receiver, and configure the delay
> +                * for the FDI timing generator to 90h. Luckily, all the other
> +                * bits are supposed to be zeroed, so we can write those values
> +                * directly.
> +                */
> +               I915_WRITE(FDI_RX_MISC(pipe), FDI_RX_TP1_TO_TP2_48 |
> +                               FDI_RX_FDI_DELAY_90);
> +
>                 /* Enable CPU FDI Receiver with auto-training */
>                 reg = FDI_RX_CTL(pipe);
>                 I915_WRITE(reg,
> --
> 1.7.11.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Paulo Zanoni

Re: [PATCH 10/31] drm/i915: program FDI_RX TP and FDI delays

[Daniel Vetter]

On Thu, Jul 05, 2012 at 09:58:53AM -0300, Paulo Zanoni wrote:
> 2012/7/4 Eugeni Dodonov <eugeni.dodonov@intel.com>:
> > This is required for a stable FDI connection.
> >
> > v2: fix and simplify the FDI_RX_MISC bits as noticed by Paulo Zanoni.
> >
> > CC: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Patch queued for -next, thanks.
-Daniel
-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH 10/21] drm/i915: introduce lpt_enable_pch and cpt_enable_pch

[Eugeni Dodonov]

On 07/04/2012 03:21 PM, Paulo Zanoni wrote:
> It looks like the check above could go on a separate commit. The first
> commit just moves code around, the second one adds the check.

This patch attempts to reset cpt_pch_enable to what ironlake_pch_enable
was before we added LPT support into it; and make lpt_pch_enable account
for LPT checks and such.

But yes, I can split it into several commits.

> I may have misunderstood something about this code which is not
> familiar to me, but instead of limiting everything to pipe 0, can't we
> just iterate through all pipes, read DDI_FUNC_CTL(pipe) and see if
> there's any other enabled pipe on FDI mode?

Yes, the idea in those asserts and checks was that as only 1 pipe can
work in FDI mode, and as we only have 1 FDI RX, 1 PCH Transcoder and so
on, we simple forced pipe1 to work in this mode, as this way most of
older code which uses macros still works.

But there is certainly a room for improvements.

>> -static void ironlake_pch_enable(struct drm_crtc *crtc)
>> +static void cpt_pch_enable(struct drm_crtc *crtc)
> 
> Since this will run on both IBX and CPT, shouldn't we call it
> ibx_pch_enable? At least on intel_hdmi.c, the functions are named
> after the earliest generation that can run them.

Yes, I can rename it to ibx_pch_enable.

I'll do those changes and split this one into smaller commits and will
resend later.

Thanks!
Eugeni