From: Grant Likely <grant.likely-s3s/WqlpOiPyB63q8FvJNQ@public.gmane.org> To: iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Cc: Andreas Herrmann <andreas.herrmann-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org>, devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org, Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org Subject: Re: [PATCH 7/9] documentation: iommu: add description of ARM System MMU binding Date: Wed, 12 Jun 2013 09:44:15 +0100 [thread overview] Message-ID: <20130612084415.834ED3E0A56@localhost> (raw) In-Reply-To: <1370889285-22799-8-git-send-email-will.deacon-5wv7dgnIgG8@public.gmane.org> On Mon, 10 Jun 2013 19:34:43 +0100, Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org> wrote: > This patch adds a description of the device tree binding for the ARM > System MMU architecture. > > Cc: Rob Herring <robherring2-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> > Cc: Andreas Herrmann <andreas.herrmann-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org> > Cc: Joerg Roedel <joro-zLv9SwRftAIdnm+yROfE0A@public.gmane.org> > Signed-off-by: Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org> Acked-by: Grant Likely <grant.likely-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> > --- > .../devicetree/bindings/iommu/arm,smmu.txt | 70 ++++++++++++++++++++++ > 1 file changed, 70 insertions(+) > create mode 100644 Documentation/devicetree/bindings/iommu/arm,smmu.txt > > diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt > new file mode 100644 > index 0000000..e34c6cd > --- /dev/null > +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt > @@ -0,0 +1,70 @@ > +* ARM System MMU Architecture Implementation > + > +ARM SoCs may contain an implementation of the ARM System Memory > +Management Unit Architecture, which can be used to provide 1 or 2 stages > +of address translation to bus masters external to the CPU. > + > +The SMMU may also raise interrupts in response to various fault > +conditions. > + > +** System MMU required properties: > + > +- compatible : Should be one of: > + > + "arm,smmu-v1" > + "arm,smmu-v2" > + "arm,mmu-400" > + "arm,mmu-500" > + > + depending on the particular implementation and/or the > + version of the architecture implemented. > + > +- reg : Base address and size of the SMMU. > + > +- #global-interrupts : The number of global interrupts exposed by the > + device. > + > +- interrupts : Interrupt list, with the first #global-irqs entries > + corresponding to the global interrupts and any > + following entries corresponding to context interrupts, > + specified in order of their indexing by the SMMU. > + > + For SMMUv2 implementations, there must be exactly one > + interrupt per context bank. In the case of a single, > + combined interrupt, it must be listed multiple times. > + > +- mmu-masters : A list of phandles to device nodes representing bus > + masters for which the SMMU can provide a translation > + and their corresponding StreamIDs (see example below). > + Each device node linked from this list must have a > + "#stream-id-cells" property, indicating the number of > + StreamIDs associated with it. > + > +** System MMU optional properties: > + > +- smmu-parent : When multiple SMMUs are chained together, this > + property can be used to provide a phandle to the > + parent SMMU (that is the next SMMU on the path going > + from the mmu-masters towards memory) node for this > + SMMU. > + > +Example: > + > + smmu { > + compatible = "arm,smmu-v1"; > + reg = <0xba5e0000 0x10000>; > + #global-interrupts = <2>; > + interrupts = <0 32 4>, > + <0 33 4>, > + <0 34 4>, /* This is the first context interrupt */ > + <0 35 4>, > + <0 36 4>, > + <0 37 4>; > + > + /* > + * Two DMA controllers, the first with two StreamIDs (0xd01d > + * and 0xd01e) and the second with only one (0xd11c). > + */ > + mmu-masters = <&dma0 0xd01d 0xd01e>, > + <&dma1 0xd11c>; > + }; > -- > 1.8.2.2 > > _______________________________________________ > devicetree-discuss mailing list > devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org > https://lists.ozlabs.org/listinfo/devicetree-discuss -- Grant Likely, B.Sc, P.Eng. Secret Lab Technologies, Ltd.
WARNING: multiple messages have this Message-ID (diff)
From: grant.likely@secretlab.ca (Grant Likely) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 7/9] documentation: iommu: add description of ARM System MMU binding Date: Wed, 12 Jun 2013 09:44:15 +0100 [thread overview] Message-ID: <20130612084415.834ED3E0A56@localhost> (raw) In-Reply-To: <1370889285-22799-8-git-send-email-will.deacon@arm.com> On Mon, 10 Jun 2013 19:34:43 +0100, Will Deacon <will.deacon@arm.com> wrote: > This patch adds a description of the device tree binding for the ARM > System MMU architecture. > > Cc: Rob Herring <robherring2@gmail.com> > Cc: Andreas Herrmann <andreas.herrmann@calxeda.com> > Cc: Joerg Roedel <joro@8bytes.org> > Signed-off-by: Will Deacon <will.deacon@arm.com> Acked-by: Grant Likely <grant.likely@linaro.org> > --- > .../devicetree/bindings/iommu/arm,smmu.txt | 70 ++++++++++++++++++++++ > 1 file changed, 70 insertions(+) > create mode 100644 Documentation/devicetree/bindings/iommu/arm,smmu.txt > > diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt > new file mode 100644 > index 0000000..e34c6cd > --- /dev/null > +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt > @@ -0,0 +1,70 @@ > +* ARM System MMU Architecture Implementation > + > +ARM SoCs may contain an implementation of the ARM System Memory > +Management Unit Architecture, which can be used to provide 1 or 2 stages > +of address translation to bus masters external to the CPU. > + > +The SMMU may also raise interrupts in response to various fault > +conditions. > + > +** System MMU required properties: > + > +- compatible : Should be one of: > + > + "arm,smmu-v1" > + "arm,smmu-v2" > + "arm,mmu-400" > + "arm,mmu-500" > + > + depending on the particular implementation and/or the > + version of the architecture implemented. > + > +- reg : Base address and size of the SMMU. > + > +- #global-interrupts : The number of global interrupts exposed by the > + device. > + > +- interrupts : Interrupt list, with the first #global-irqs entries > + corresponding to the global interrupts and any > + following entries corresponding to context interrupts, > + specified in order of their indexing by the SMMU. > + > + For SMMUv2 implementations, there must be exactly one > + interrupt per context bank. In the case of a single, > + combined interrupt, it must be listed multiple times. > + > +- mmu-masters : A list of phandles to device nodes representing bus > + masters for which the SMMU can provide a translation > + and their corresponding StreamIDs (see example below). > + Each device node linked from this list must have a > + "#stream-id-cells" property, indicating the number of > + StreamIDs associated with it. > + > +** System MMU optional properties: > + > +- smmu-parent : When multiple SMMUs are chained together, this > + property can be used to provide a phandle to the > + parent SMMU (that is the next SMMU on the path going > + from the mmu-masters towards memory) node for this > + SMMU. > + > +Example: > + > + smmu { > + compatible = "arm,smmu-v1"; > + reg = <0xba5e0000 0x10000>; > + #global-interrupts = <2>; > + interrupts = <0 32 4>, > + <0 33 4>, > + <0 34 4>, /* This is the first context interrupt */ > + <0 35 4>, > + <0 36 4>, > + <0 37 4>; > + > + /* > + * Two DMA controllers, the first with two StreamIDs (0xd01d > + * and 0xd01e) and the second with only one (0xd11c). > + */ > + mmu-masters = <&dma0 0xd01d 0xd01e>, > + <&dma1 0xd11c>; > + }; > -- > 1.8.2.2 > > _______________________________________________ > devicetree-discuss mailing list > devicetree-discuss at lists.ozlabs.org > https://lists.ozlabs.org/listinfo/devicetree-discuss -- Grant Likely, B.Sc, P.Eng. Secret Lab Technologies, Ltd.
next prev parent reply other threads:[~2013-06-12 8:44 UTC|newest] Thread overview: 97+ messages / expand[flat|nested] mbox.gz Atom feed top 2013-06-10 18:34 [PATCH 0/9] Add support for ARM SMMU architectures 1 and 2 Will Deacon 2013-06-10 18:34 ` Will Deacon [not found] ` <1370889285-22799-1-git-send-email-will.deacon-5wv7dgnIgG8@public.gmane.org> 2013-06-10 18:34 ` [PATCH 1/9] dma: pl330: rip out broken, redundant ID probing Will Deacon 2013-06-10 18:34 ` Will Deacon [not found] ` <1370889285-22799-2-git-send-email-will.deacon-5wv7dgnIgG8@public.gmane.org> 2013-06-11 4:37 ` Jassi Brar 2013-06-11 22:31 ` Grant Likely 2013-06-11 22:31 ` Grant Likely 2013-06-12 5:31 ` Vinod Koul 2013-06-12 5:31 ` Vinod Koul 2013-06-11 4:40 ` Jassi Brar 2013-06-11 4:40 ` Jassi Brar [not found] ` <CAJe_Zhc1UoTC4q4oaW=dzyi_10Q7EoezoT=G8_v+yCmBxV75+A-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 2013-06-11 8:45 ` Will Deacon 2013-06-11 8:45 ` Will Deacon 2013-06-10 18:34 ` [PATCH 2/9] dma: pl330: use dma_addr_t for describing bus addresses Will Deacon 2013-06-10 18:34 ` Will Deacon [not found] ` <1370889285-22799-3-git-send-email-will.deacon-5wv7dgnIgG8@public.gmane.org> 2013-06-11 4:37 ` Jassi Brar [not found] ` <CAJe_ZheKMVQgq42Vx5N1TXXdgFJ2sp50ixU30A7beXhmSVHnZQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 2013-06-12 5:31 ` Vinod Koul 2013-06-12 5:31 ` Vinod Koul 2013-06-11 22:32 ` Grant Likely 2013-06-11 22:32 ` Grant Likely 2013-06-11 4:39 ` Jassi Brar 2013-06-11 4:39 ` Jassi Brar 2013-06-10 18:34 ` [PATCH 3/9] ARM: dma-mapping: convert DMA direction into IOMMU protection attributes Will Deacon 2013-06-10 18:34 ` Will Deacon 2013-06-19 8:37 ` Marek Szyprowski 2013-06-19 8:37 ` Marek Szyprowski [not found] ` <51C16DAF.1090205-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> 2013-06-19 8:52 ` Will Deacon 2013-06-19 8:52 ` Will Deacon [not found] ` <20130619085202.GC20351-MRww78TxoiP5vMa5CHWGZ34zcgK1vI+I0E9HWUfgJXw@public.gmane.org> 2013-06-19 8:57 ` Marek Szyprowski 2013-06-19 8:57 ` Marek Szyprowski [not found] ` <1370889285-22799-4-git-send-email-will.deacon-5wv7dgnIgG8@public.gmane.org> 2013-06-25 10:12 ` Hiroshi Doyu 2013-06-25 10:12 ` Hiroshi Doyu [not found] ` <20130625131215.d3cea2a5668a3d41dbbeb064-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2013-06-25 11:37 ` Will Deacon 2013-06-25 11:37 ` Will Deacon [not found] ` <20130625113714.GF31838-MRww78TxoiP5vMa5CHWGZ34zcgK1vI+I0E9HWUfgJXw@public.gmane.org> 2013-06-25 11:52 ` Hiroshi Doyu 2013-06-25 11:52 ` Hiroshi Doyu 2013-06-25 11:52 ` Hiroshi Doyu [not found] ` <20130625.145226.1632119404634300971.hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2013-06-25 12:34 ` Will Deacon 2013-06-25 12:34 ` Will Deacon 2013-06-10 18:34 ` [PATCH 4/9] ARM: dma-mapping: NULLify dev->archdata.mapping pointer on detach Will Deacon 2013-06-10 18:34 ` Will Deacon [not found] ` <1370889285-22799-5-git-send-email-will.deacon-5wv7dgnIgG8@public.gmane.org> 2013-06-11 5:34 ` Hiroshi Doyu 2013-06-11 5:34 ` Hiroshi Doyu [not found] ` <20130611.083455.1500863288897785600.hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2013-06-11 8:50 ` Will Deacon 2013-06-11 8:50 ` Will Deacon [not found] ` <20130611085015.GC24729-MRww78TxoiP5vMa5CHWGZ34zcgK1vI+I0E9HWUfgJXw@public.gmane.org> 2013-06-11 9:39 ` Hiroshi Doyu 2013-06-11 9:39 ` Hiroshi Doyu [not found] ` <20130611123933.4d278ff4e056f395788ad060-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2013-06-19 8:59 ` Marek Szyprowski 2013-06-19 8:59 ` Marek Szyprowski 2013-06-10 18:34 ` [PATCH 5/9] arm64: pgtable: use pte_index instead of __pte_index Will Deacon 2013-06-10 18:34 ` Will Deacon 2013-06-10 18:34 ` [PATCH 6/9] arm64: device: add iommu pointer to device archdata Will Deacon 2013-06-10 18:34 ` Will Deacon 2013-06-10 18:34 ` [PATCH 7/9] documentation: iommu: add description of ARM System MMU binding Will Deacon 2013-06-10 18:34 ` Will Deacon [not found] ` <1370889285-22799-8-git-send-email-will.deacon-5wv7dgnIgG8@public.gmane.org> 2013-06-12 8:44 ` Grant Likely [this message] 2013-06-12 8:44 ` Grant Likely 2013-06-20 20:08 ` Joerg Roedel 2013-06-20 20:08 ` Joerg Roedel [not found] ` <20130620200845.GF11309-zLv9SwRftAIdnm+yROfE0A@public.gmane.org> 2013-06-21 9:57 ` Will Deacon 2013-06-21 9:57 ` Will Deacon [not found] ` <20130621095729.GA7766-MRww78TxoiP5vMa5CHWGZ34zcgK1vI+I0E9HWUfgJXw@public.gmane.org> 2013-06-21 13:55 ` Joerg Roedel 2013-06-21 13:55 ` Joerg Roedel [not found] ` <20130621135507.GI11309-zLv9SwRftAIdnm+yROfE0A@public.gmane.org> 2013-06-21 16:41 ` Will Deacon 2013-06-21 16:41 ` Will Deacon 2013-06-25 19:18 ` Stuart Yoder 2013-06-25 19:18 ` Stuart Yoder [not found] ` <CALRxmdBxFWoRKv+bUu8VEwNNcAJUej9jM2V8N0rrqrr_Vpe8fQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 2013-06-26 13:39 ` Will Deacon 2013-06-26 13:39 ` Will Deacon [not found] ` <20130626133941.GD7417-MRww78TxoiP5vMa5CHWGZ34zcgK1vI+I0E9HWUfgJXw@public.gmane.org> 2013-06-26 16:19 ` Stuart Yoder 2013-06-26 16:19 ` Stuart Yoder [not found] ` <CALRxmdCycFK2wW=C4aU79mudSaT+2vU8nzXxepdstubg+YSdQg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 2013-06-26 17:42 ` Will Deacon 2013-06-26 17:42 ` Will Deacon [not found] ` <20130626174231.GH10333-MRww78TxoiP5vMa5CHWGZ34zcgK1vI+I0E9HWUfgJXw@public.gmane.org> 2013-06-27 18:22 ` Stuart Yoder 2013-06-27 18:22 ` Stuart Yoder [not found] ` <CALRxmdD5fyp06xW+z=rWagJc_bcJmpr1H9Zbdf=xbg9cCzvVfw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 2013-06-28 9:06 ` Will Deacon 2013-06-28 9:06 ` Will Deacon [not found] ` <20130628090635.GB29002-MRww78TxoiP5vMa5CHWGZ34zcgK1vI+I0E9HWUfgJXw@public.gmane.org> 2013-06-28 16:03 ` Stuart Yoder 2013-06-28 16:03 ` Stuart Yoder 2013-06-10 18:34 ` [PATCH 8/9] iommu: add support for ARM Ltd. System MMU architecture Will Deacon 2013-06-10 18:34 ` Will Deacon [not found] ` <1370889285-22799-9-git-send-email-will.deacon-5wv7dgnIgG8@public.gmane.org> 2013-06-20 21:26 ` Joerg Roedel 2013-06-20 21:26 ` Joerg Roedel [not found] ` <20130620212646.GG11309-zLv9SwRftAIdnm+yROfE0A@public.gmane.org> 2013-06-21 10:23 ` Will Deacon 2013-06-21 10:23 ` Will Deacon [not found] ` <20130621102318.GB7766-MRww78TxoiP5vMa5CHWGZ34zcgK1vI+I0E9HWUfgJXw@public.gmane.org> 2013-06-21 14:13 ` Joerg Roedel 2013-06-21 14:13 ` Joerg Roedel 2013-06-21 15:00 ` Will Deacon 2013-06-21 15:00 ` Will Deacon [not found] ` <20130621150006.GG7766-MRww78TxoiP5vMa5CHWGZ34zcgK1vI+I0E9HWUfgJXw@public.gmane.org> 2013-06-21 15:30 ` Joerg Roedel 2013-06-21 15:30 ` Joerg Roedel [not found] ` <20130621153044.GL11309-zLv9SwRftAIdnm+yROfE0A@public.gmane.org> 2013-06-21 16:40 ` Will Deacon 2013-06-21 16:40 ` Will Deacon 2013-06-10 18:34 ` [PATCH 9/9] MAINTAINERS: add entry for ARM system MMU driver Will Deacon 2013-06-10 18:34 ` Will Deacon [not found] ` <1370889285-22799-10-git-send-email-will.deacon-5wv7dgnIgG8@public.gmane.org> 2013-06-12 8:45 ` Grant Likely 2013-06-12 8:45 ` Grant Likely
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