* [PATCH] drm/i915: correct intel_dp_get_config() function for DevCPT
@ 2013-06-27 5:25 Xiong Zhang
2013-06-27 10:30 ` Daniel Vetter
0 siblings, 1 reply; 4+ messages in thread
From: Xiong Zhang @ 2013-06-27 5:25 UTC (permalink / raw)
To: intel-gfx
On DevCPT, the control register for Transcoder DP Sync Polarity is
TRANS_DP_CTL, not DP_CTL.
Without this patch, Many OOP occur on CPT machine with DP monitor.The OOP
is like: *ERROR* mismatch in adjusted_mode.flags(expected X,found X)
Signed-off-by: Xiong Zhang <xiong.y.zhang@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 57 ++++++++++++++++++++++++++++++++-------
1 file changed, 47 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 8708a0c..16c5803 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1324,20 +1324,57 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
struct intel_crtc_config *pipe_config)
{
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
- struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
u32 tmp, flags = 0;
+ struct drm_device *dev = encoder->base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ enum port port = dp_to_dig_port(intel_dp)->port;
- tmp = I915_READ(intel_dp->output_reg);
+ if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
+ tmp = I915_READ(intel_dp->output_reg);
+ if (tmp & DP_SYNC_HS_HIGH)
+ flags |= DRM_MODE_FLAG_PHSYNC;
+ else
+ flags |= DRM_MODE_FLAG_NHSYNC;
- if (tmp & DP_SYNC_HS_HIGH)
- flags |= DRM_MODE_FLAG_PHSYNC;
- else
- flags |= DRM_MODE_FLAG_NHSYNC;
+ if (tmp & DP_SYNC_VS_HIGH)
+ flags |= DRM_MODE_FLAG_PVSYNC;
+ else
+ flags |= DRM_MODE_FLAG_NVSYNC;
+ } else {
+ u32 trans_sel = 0;
+ int i;
- if (tmp & DP_SYNC_VS_HIGH)
- flags |= DRM_MODE_FLAG_PVSYNC;
- else
- flags |= DRM_MODE_FLAG_NVSYNC;
+ switch (intel_dp->output_reg) {
+ case PCH_DP_B:
+ trans_sel = TRANS_DP_PORT_SEL_B;
+ break;
+ case PCH_DP_C:
+ trans_sel = TRANS_DP_PORT_SEL_C;
+ break;
+ case PCH_DP_D:
+ trans_sel = TRANS_DP_PORT_SEL_D;
+ break;
+ default:
+ break;
+ }
+
+ for_each_pipe(i) {
+ tmp = I915_READ(TRANS_DP_CTL(i));
+ if ((tmp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
+ if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
+ flags |= DRM_MODE_FLAG_PHSYNC;
+ else
+ flags |= DRM_MODE_FLAG_NHSYNC;
+
+ if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
+ flags |= DRM_MODE_FLAG_PVSYNC;
+ else
+ flags |= DRM_MODE_FLAG_NVSYNC;
+
+ break;
+ }
+ }
+ }
pipe_config->adjusted_mode.flags |= flags;
}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] drm/i915: correct intel_dp_get_config() function for DevCPT
2013-06-27 5:25 [PATCH] drm/i915: correct intel_dp_get_config() function for DevCPT Xiong Zhang
@ 2013-06-27 10:30 ` Daniel Vetter
0 siblings, 0 replies; 4+ messages in thread
From: Daniel Vetter @ 2013-06-27 10:30 UTC (permalink / raw)
To: Xiong Zhang; +Cc: intel-gfx
On Thu, Jun 27, 2013 at 01:25:17PM +0800, Xiong Zhang wrote:
> On DevCPT, the control register for Transcoder DP Sync Polarity is
> TRANS_DP_CTL, not DP_CTL.
> Without this patch, Many OOP occur on CPT machine with DP monitor.The OOP
> is like: *ERROR* mismatch in adjusted_mode.flags(expected X,found X)
>
> Signed-off-by: Xiong Zhang <xiong.y.zhang@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 57 ++++++++++++++++++++++++++++++++-------
> 1 file changed, 47 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 8708a0c..16c5803 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1324,20 +1324,57 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
> struct intel_crtc_config *pipe_config)
> {
> struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> - struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> u32 tmp, flags = 0;
> + struct drm_device *dev = encoder->base.dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + enum port port = dp_to_dig_port(intel_dp)->port;
>
> - tmp = I915_READ(intel_dp->output_reg);
> + if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
> + tmp = I915_READ(intel_dp->output_reg);
> + if (tmp & DP_SYNC_HS_HIGH)
> + flags |= DRM_MODE_FLAG_PHSYNC;
> + else
> + flags |= DRM_MODE_FLAG_NHSYNC;
>
> - if (tmp & DP_SYNC_HS_HIGH)
> - flags |= DRM_MODE_FLAG_PHSYNC;
> - else
> - flags |= DRM_MODE_FLAG_NHSYNC;
> + if (tmp & DP_SYNC_VS_HIGH)
> + flags |= DRM_MODE_FLAG_PVSYNC;
> + else
> + flags |= DRM_MODE_FLAG_NVSYNC;
> + } else {
> + u32 trans_sel = 0;
> + int i;
>
> - if (tmp & DP_SYNC_VS_HIGH)
> - flags |= DRM_MODE_FLAG_PVSYNC;
> - else
> - flags |= DRM_MODE_FLAG_NVSYNC;
> + switch (intel_dp->output_reg) {
> + case PCH_DP_B:
> + trans_sel = TRANS_DP_PORT_SEL_B;
> + break;
> + case PCH_DP_C:
> + trans_sel = TRANS_DP_PORT_SEL_C;
> + break;
> + case PCH_DP_D:
> + trans_sel = TRANS_DP_PORT_SEL_D;
> + break;
> + default:
> + break;
> + }
> +
> + for_each_pipe(i) {
> + tmp = I915_READ(TRANS_DP_CTL(i));
> + if ((tmp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
> + if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
> + flags |= DRM_MODE_FLAG_PHSYNC;
> + else
> + flags |= DRM_MODE_FLAG_NHSYNC;
> +
> + if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
> + flags |= DRM_MODE_FLAG_PVSYNC;
> + else
> + flags |= DRM_MODE_FLAG_NVSYNC;
> +
> + break;
> + }
> + }
> + }
Instead of duplicating the encoder->pipe mapping code here again (from the
get_hw_state function) I think it'd be better to add a enum pipe pipe
argument to encoder->get_config functions. Or maybe we should pass in the
intel_crtc *crtc pointer right away, in case we ever need other things
from the connected crtc.
So one patch to extend the get_config function:
/* Reconstructs the equivalent mode flags for the current hardware
* state. This must be called _after_ display->get_pipe_config has
* pre-filled the pipe config. */
void (*get_config)(struct intel_encoder *,
struct intel_crtc *,
struct intel_crtc_config *pipe_config);
And then your patch should reduce a lot.
Cheers, Daniel
>
> pipe_config->adjusted_mode.flags |= flags;
> }
> --
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] drm/i915: correct intel_dp_get_config() function for DevCPT
2013-06-28 4:59 Xiong Zhang
@ 2013-06-28 8:28 ` Daniel Vetter
0 siblings, 0 replies; 4+ messages in thread
From: Daniel Vetter @ 2013-06-28 8:28 UTC (permalink / raw)
To: Xiong Zhang; +Cc: intel-gfx
On Fri, Jun 28, 2013 at 12:59:06PM +0800, Xiong Zhang wrote:
> On DevCPT, the control register for Transcoder DP Sync Polarity is
> TRANS_DP_CTL, not DP_CTL.
> Without this patch, Many call trace occur on CPT machine with DP monitor.
> The call trace is like: *ERROR* mismatch in adjusted_mode.flags(expected X,found X)
>
> v2: use intel-crtc to simple patch, suggested by Daniel.
>
> Signed-off-by: Xiong Zhang <xiong.y.zhang@intel.com>
Queued for -next (with some tiny bikeshedding), thanks for the patch.
-Daniel
> ---
> drivers/gpu/drm/i915/intel_dp.c | 35 +++++++++++++++++++++++++----------
> 1 file changed, 25 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 8708a0c..c3ff8ac 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1324,20 +1324,35 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
> struct intel_crtc_config *pipe_config)
> {
> struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> - struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> u32 tmp, flags = 0;
> + struct drm_device *dev = encoder->base.dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + enum port port = dp_to_dig_port(intel_dp)->port;
> + struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
>
> - tmp = I915_READ(intel_dp->output_reg);
> + if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
> + tmp = I915_READ(intel_dp->output_reg);
> + if (tmp & DP_SYNC_HS_HIGH)
> + flags |= DRM_MODE_FLAG_PHSYNC;
> + else
> + flags |= DRM_MODE_FLAG_NHSYNC;
>
> - if (tmp & DP_SYNC_HS_HIGH)
> - flags |= DRM_MODE_FLAG_PHSYNC;
> - else
> - flags |= DRM_MODE_FLAG_NHSYNC;
> + if (tmp & DP_SYNC_VS_HIGH)
> + flags |= DRM_MODE_FLAG_PVSYNC;
> + else
> + flags |= DRM_MODE_FLAG_NVSYNC;
> + } else {
> + tmp = I915_READ(TRANS_DP_CTL(intel_crtc->pipe));
> + if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
> + flags |= DRM_MODE_FLAG_PHSYNC;
> + else
> + flags |= DRM_MODE_FLAG_NHSYNC;
>
> - if (tmp & DP_SYNC_VS_HIGH)
> - flags |= DRM_MODE_FLAG_PVSYNC;
> - else
> - flags |= DRM_MODE_FLAG_NVSYNC;
> + if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
> + flags |= DRM_MODE_FLAG_PVSYNC;
> + else
> + flags |= DRM_MODE_FLAG_NVSYNC;
> + }
>
> pipe_config->adjusted_mode.flags |= flags;
> }
> --
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH] drm/i915: correct intel_dp_get_config() function for DevCPT
@ 2013-06-28 4:59 Xiong Zhang
2013-06-28 8:28 ` Daniel Vetter
0 siblings, 1 reply; 4+ messages in thread
From: Xiong Zhang @ 2013-06-28 4:59 UTC (permalink / raw)
To: intel-gfx
On DevCPT, the control register for Transcoder DP Sync Polarity is
TRANS_DP_CTL, not DP_CTL.
Without this patch, Many call trace occur on CPT machine with DP monitor.
The call trace is like: *ERROR* mismatch in adjusted_mode.flags(expected X,found X)
v2: use intel-crtc to simple patch, suggested by Daniel.
Signed-off-by: Xiong Zhang <xiong.y.zhang@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 35 +++++++++++++++++++++++++----------
1 file changed, 25 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 8708a0c..c3ff8ac 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1324,20 +1324,35 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
struct intel_crtc_config *pipe_config)
{
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
- struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
u32 tmp, flags = 0;
+ struct drm_device *dev = encoder->base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ enum port port = dp_to_dig_port(intel_dp)->port;
+ struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
- tmp = I915_READ(intel_dp->output_reg);
+ if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
+ tmp = I915_READ(intel_dp->output_reg);
+ if (tmp & DP_SYNC_HS_HIGH)
+ flags |= DRM_MODE_FLAG_PHSYNC;
+ else
+ flags |= DRM_MODE_FLAG_NHSYNC;
- if (tmp & DP_SYNC_HS_HIGH)
- flags |= DRM_MODE_FLAG_PHSYNC;
- else
- flags |= DRM_MODE_FLAG_NHSYNC;
+ if (tmp & DP_SYNC_VS_HIGH)
+ flags |= DRM_MODE_FLAG_PVSYNC;
+ else
+ flags |= DRM_MODE_FLAG_NVSYNC;
+ } else {
+ tmp = I915_READ(TRANS_DP_CTL(intel_crtc->pipe));
+ if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
+ flags |= DRM_MODE_FLAG_PHSYNC;
+ else
+ flags |= DRM_MODE_FLAG_NHSYNC;
- if (tmp & DP_SYNC_VS_HIGH)
- flags |= DRM_MODE_FLAG_PVSYNC;
- else
- flags |= DRM_MODE_FLAG_NVSYNC;
+ if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
+ flags |= DRM_MODE_FLAG_PVSYNC;
+ else
+ flags |= DRM_MODE_FLAG_NVSYNC;
+ }
pipe_config->adjusted_mode.flags |= flags;
}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 4+ messages in thread
end of thread, other threads:[~2013-06-28 8:28 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2013-06-27 5:25 [PATCH] drm/i915: correct intel_dp_get_config() function for DevCPT Xiong Zhang
2013-06-27 10:30 ` Daniel Vetter
2013-06-28 4:59 Xiong Zhang
2013-06-28 8:28 ` Daniel Vetter
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