* [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
@ 2013-09-25 8:48 ` Tero Kristo
0 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-omap-u79uwXL29TY76Z2rM5mHXA, paul-DWxLp4Yu+b8AvxtiuMwx3w,
tony-4v6yS6AI5VpBDgjK7y7TUQ, nm-l0cyMroinI0, rnayak-l0cyMroinI0,
bcousson-rdvid1DuHRBWk0Htik3J/w,
mturquette-QSEj5FYQhm4dnm+yROfE0A
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
Hi all,
Version 7 contains following high level changes:
- Dropped support for basic bindings from Mike Turquette, instead using
vendor specific bindings for all clocks
- Mux clock + divider clock vendor specific bindings get rid of use
of the bit-masks, instead these are generated runtime based on parent
clock / divider min/max info, see individual patches for details
- Added support for dummy_ck nodes, was missing from previous version
- Fixed support for omap3630
- Added support for new clock node type: ti,mux-gate-clock (using composite
clock type)
- OMAP4 / OMAP5 only build fixes (compiler flag checks added to some files)
- most of the of_omap_* calls renamed to of_ti_*
- Rebased on top of v3.12-rc2
Some detailed comments about patch level changes (if no mention, no major
changes):
- Patch #1:
* removed use of reg-names property, instead registers mapped using
compatible string
* removed ti,modes property, instead uses DPLL mode flags now
* separated AM33XX DPLLs under their own compatible strings
- Patch #4 & #5: new patches
- Patch #6: merged basic gate support from Mike to this patch as vendor
specific gate clock support
- Patch #9 & #10: new patches
- Patch #11: dummy clocks added, USB / ABE DPLL setup ordering changed
- Patch #14: dummy clocks added
- Patch #20: dropped usage of reg-names property
- Patch #21: dummy clocks added
- Patch #22 & #23: new patches
- Patch #30: AM35XX clock data added to this patch
- Patch #31:
* dummy clocks added
* added missing 3630 clocks
Test branch available here:
https://github.com/t-kristo/linux-pm.git
branch: mainline-3.12-rc2-ti-dt-clks-v7
Testing done:
- am335x-bone : boot only
- omap5-sevm : boot only
- dra7-evm : boot only
- omap3-beagle : boot + suspend/resume (ret + off)
- omap4-panda-es : boot + suspend/resume
Nishanth has also been doing some tests with omap3-beagle-xm with some WIP
versions of this branch, but not with this latest one. Nishanth, maybe you
can provide test results to this one also?
-Tero
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^ permalink raw reply [flat|nested] 136+ messages in thread
* [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
@ 2013-09-25 8:48 ` Tero Kristo
0 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-arm-kernel
Hi all,
Version 7 contains following high level changes:
- Dropped support for basic bindings from Mike Turquette, instead using
vendor specific bindings for all clocks
- Mux clock + divider clock vendor specific bindings get rid of use
of the bit-masks, instead these are generated runtime based on parent
clock / divider min/max info, see individual patches for details
- Added support for dummy_ck nodes, was missing from previous version
- Fixed support for omap3630
- Added support for new clock node type: ti,mux-gate-clock (using composite
clock type)
- OMAP4 / OMAP5 only build fixes (compiler flag checks added to some files)
- most of the of_omap_* calls renamed to of_ti_*
- Rebased on top of v3.12-rc2
Some detailed comments about patch level changes (if no mention, no major
changes):
- Patch #1:
* removed use of reg-names property, instead registers mapped using
compatible string
* removed ti,modes property, instead uses DPLL mode flags now
* separated AM33XX DPLLs under their own compatible strings
- Patch #4 & #5: new patches
- Patch #6: merged basic gate support from Mike to this patch as vendor
specific gate clock support
- Patch #9 & #10: new patches
- Patch #11: dummy clocks added, USB / ABE DPLL setup ordering changed
- Patch #14: dummy clocks added
- Patch #20: dropped usage of reg-names property
- Patch #21: dummy clocks added
- Patch #22 & #23: new patches
- Patch #30: AM35XX clock data added to this patch
- Patch #31:
* dummy clocks added
* added missing 3630 clocks
Test branch available here:
https://github.com/t-kristo/linux-pm.git
branch: mainline-3.12-rc2-ti-dt-clks-v7
Testing done:
- am335x-bone : boot only
- omap5-sevm : boot only
- dra7-evm : boot only
- omap3-beagle : boot + suspend/resume (ret + off)
- omap4-panda-es : boot + suspend/resume
Nishanth has also been doing some tests with omap3-beagle-xm with some WIP
versions of this branch, but not with this latest one. Nishanth, maybe you
can provide test results to this one also?
-Tero
^ permalink raw reply [flat|nested] 136+ messages in thread
* [PATCHv7 01/36] CLK: TI: Add DPLL clock support
2013-09-25 8:48 ` Tero Kristo
@ 2013-09-25 8:48 ` Tero Kristo
-1 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-omap, paul, tony, nm, rnayak, bcousson, mturquette
Cc: linux-arm-kernel, devicetree
The OMAP clock driver now supports DPLL clock type. This patch also
adds support for DT DPLL nodes.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
.../devicetree/bindings/clock/ti/dpll.txt | 80 +++
arch/arm/mach-omap2/clock.h | 144 +----
arch/arm/mach-omap2/clock3xxx.h | 2 -
drivers/clk/Makefile | 1 +
drivers/clk/ti/Makefile | 3 +
drivers/clk/ti/dpll.c | 580 ++++++++++++++++++++
include/linux/clk/ti.h | 164 ++++++
7 files changed, 829 insertions(+), 145 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/ti/dpll.txt
create mode 100644 drivers/clk/ti/Makefile
create mode 100644 drivers/clk/ti/dpll.c
create mode 100644 include/linux/clk/ti.h
diff --git a/Documentation/devicetree/bindings/clock/ti/dpll.txt b/Documentation/devicetree/bindings/clock/ti/dpll.txt
new file mode 100644
index 0000000..993879f
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/dpll.txt
@@ -0,0 +1,80 @@
+Binding for Texas Instruments DPLL clock.
+
+This binding uses the common clock binding[1]. It assumes a
+register-mapped DPLL with usually two selectable input clocks
+(reference clock and bypass clock), with digital phase locked
+loop logic for multiplying the input clock to a desired output
+clock. This clock also typically supports different operation
+modes (locked, low power stop etc.) This binding has several
+sub-types, which effectively result in slightly different setup
+for the actual DPLL clock.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be one of:
+ "ti,omap3-dpll-clock",
+ "ti,omap3-dpll-core-clock",
+ "ti,omap3-dpll-per-clock",
+ "ti,omap3-dpll-per-j-type-clock",
+ "ti,omap4-dpll-clock",
+ "ti,omap4-dpll-x2-clock",
+ "ti,omap4-dpll-core-clock",
+ "ti,omap4-dpll-m4xen-clock",
+ "ti,omap4-dpll-j-type-clock",
+ "ti,am3-dpll-no-gate-clock",
+ "ti,am3-dpll-no-gate-j-type-clock",
+ "ti,am3-dpll-clock",
+ "ti,am3-dpll-core-clock",
+ "ti,am3-dpll-x2-clock",
+
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : link phandles of parent clocks, first entry lists reference clock
+ and second entry bypass clock
+- reg : address and length of the register set for controlling the DPLL.
+ Registers are listed in following order:
+ "control" - contains the control register base address
+ "idlest" - contains the idle status register base address
+ "autoidle" - contains the autoidle register base address
+ "mult-div1" - contains the multiplier / divider register base address
+ ti,am3-* dpll types list the registers in the same order, except "autoidle"
+ register is left out as this hardware does not have it, e.g.:
+ reg = <0x4000 0x4>, <0x5000 0x4>, <0x6000 0x4>;
+ results in following register map:
+ 0x4000 - control
+ 0x5000 - idlest
+ 0x6000 - mult-div1
+
+Optional properties:
+- DPLL mode setting - defining any one or more of the following overrides
+ default setting.
+ - ti,low-power-stop : DPLL supports low power stop mode, gating output
+ - ti,low-power-bypass : DPLL output matches rate of parent bypass clock
+ - ti,lock : DPLL locks in programmed rate
+
+Examples:
+ dpll_core_ck: dpll_core_ck@44e00490 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-core-clock";
+ clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+ reg = <0x44e00490 0x4>, <0x44e0045c 0x4>, <0x0 0x4>,
+ <0x44e00468 0x4>;
+ };
+
+ dpll2_ck: dpll2_ck@48004004 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-dpll-clock";
+ clocks = <&sys_ck>, <&dpll2_fck>;
+ ti,low-power-stop;
+ ti,low-power-bypass;
+ ti,lock;
+ reg = <0x48004004 0x4>, <0x48004024 0x4>, <0x48004034 0x4>,
+ <0x48004040 0x4>;
+ };
+
+ dpll_core_ck: dpll_core_ck@44e00490 {
+ #clock-cells = <0>;
+ compatible = "ti,am3-dpll-core-clock";
+ clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+ reg = <0x44e00490 0x4>, <0x44e0045c 0x4>, <0x44e00468 0x4>;
+ };
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 7aa32cd..079536a 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -21,6 +21,7 @@
#include <linux/clkdev.h>
#include <linux/clk-provider.h>
+#include <linux/clk/ti.h>
struct omap_clk {
u16 cpu;
@@ -178,83 +179,6 @@ struct clksel {
const struct clksel_rate *rates;
};
-/**
- * struct dpll_data - DPLL registers and integration data
- * @mult_div1_reg: register containing the DPLL M and N bitfields
- * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
- * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
- * @clk_bypass: struct clk pointer to the clock's bypass clock input
- * @clk_ref: struct clk pointer to the clock's reference clock input
- * @control_reg: register containing the DPLL mode bitfield
- * @enable_mask: mask of the DPLL mode bitfield in @control_reg
- * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
- * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
- * @last_rounded_m4xen: cache of the last M4X result of
- * omap4_dpll_regm4xen_round_rate()
- * @last_rounded_lpmode: cache of the last lpmode result of
- * omap4_dpll_lpmode_recalc()
- * @max_multiplier: maximum valid non-bypass multiplier value (actual)
- * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
- * @min_divider: minimum valid non-bypass divider value (actual)
- * @max_divider: maximum valid non-bypass divider value (actual)
- * @modes: possible values of @enable_mask
- * @autoidle_reg: register containing the DPLL autoidle mode bitfield
- * @idlest_reg: register containing the DPLL idle status bitfield
- * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
- * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
- * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
- * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
- * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
- * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
- * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
- * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
- * @flags: DPLL type/features (see below)
- *
- * Possible values for @flags:
- * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
- *
- * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
- *
- * XXX Some DPLLs have multiple bypass inputs, so it's not technically
- * correct to only have one @clk_bypass pointer.
- *
- * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
- * @last_rounded_n) should be separated from the runtime-fixed fields
- * and placed into a different structure, so that the runtime-fixed data
- * can be placed into read-only space.
- */
-struct dpll_data {
- void __iomem *mult_div1_reg;
- u32 mult_mask;
- u32 div1_mask;
- struct clk *clk_bypass;
- struct clk *clk_ref;
- void __iomem *control_reg;
- u32 enable_mask;
- unsigned long last_rounded_rate;
- u16 last_rounded_m;
- u8 last_rounded_m4xen;
- u8 last_rounded_lpmode;
- u16 max_multiplier;
- u8 last_rounded_n;
- u8 min_divider;
- u16 max_divider;
- u8 modes;
- void __iomem *autoidle_reg;
- void __iomem *idlest_reg;
- u32 autoidle_mask;
- u32 freqsel_mask;
- u32 idlest_mask;
- u32 dco_mask;
- u32 sddiv_mask;
- u32 lpmode_mask;
- u32 m4xen_mask;
- u8 auto_recal_bit;
- u8 recal_en_bit;
- u8 recal_st_bit;
- u8 flags;
-};
-
/*
* struct clk.flags possibilities
*
@@ -274,45 +198,6 @@ struct dpll_data {
#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */
#define CLOCK_CLKOUTX2 (1 << 5)
-/**
- * struct clk_hw_omap - OMAP struct clk
- * @node: list_head connecting this clock into the full clock list
- * @enable_reg: register to write to enable the clock (see @enable_bit)
- * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
- * @flags: see "struct clk.flags possibilities" above
- * @clksel_reg: for clksel clks, register va containing src/divisor select
- * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
- * @clksel: for clksel clks, pointer to struct clksel for this clock
- * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
- * @clkdm_name: clockdomain name that this clock is contained in
- * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
- * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
- * @src_offset: bitshift for source selection bitfield (OMAP1 only)
- *
- * XXX @rate_offset, @src_offset should probably be removed and OMAP1
- * clock code converted to use clksel.
- *
- */
-
-struct clk_hw_omap_ops;
-
-struct clk_hw_omap {
- struct clk_hw hw;
- struct list_head node;
- unsigned long fixed_rate;
- u8 fixed_div;
- void __iomem *enable_reg;
- u8 enable_bit;
- u8 flags;
- void __iomem *clksel_reg;
- u32 clksel_mask;
- const struct clksel *clksel;
- struct dpll_data *dpll_data;
- const char *clkdm_name;
- struct clockdomain *clkdm;
- const struct clk_hw_omap_ops *ops;
-};
-
struct clk_hw_omap_ops {
void (*find_idlest)(struct clk_hw_omap *oclk,
void __iomem **idlest_reg,
@@ -348,36 +233,13 @@ unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
#define OMAP4XXX_EN_DPLL_FRBYPASS 0x6
#define OMAP4XXX_EN_DPLL_LOCKED 0x7
-/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
-#define DPLL_LOW_POWER_STOP 0x1
-#define DPLL_LOW_POWER_BYPASS 0x5
-#define DPLL_LOCKED 0x7
-
-/* DPLL Type and DCO Selection Flags */
-#define DPLL_J_TYPE 0x1
-
-long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
- unsigned long *parent_rate);
-unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
-int omap3_noncore_dpll_enable(struct clk_hw *hw);
-void omap3_noncore_dpll_disable(struct clk_hw *hw);
-int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long parent_rate);
u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
void omap3_dpll_allow_idle(struct clk_hw_omap *clk);
void omap3_dpll_deny_idle(struct clk_hw_omap *clk);
-unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
- unsigned long parent_rate);
int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk);
void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk);
void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk);
-unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
- unsigned long parent_rate);
-long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
- unsigned long target_rate,
- unsigned long *parent_rate);
-void omap2_init_clk_clkdm(struct clk_hw *clk);
void __init omap2_clk_disable_clkdm_control(void);
/* clkt_clksel.c public functions */
@@ -396,7 +258,6 @@ int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val);
extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk);
extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);
-u8 omap2_init_dpll_parent(struct clk_hw *hw);
unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
int omap2_dflt_clk_enable(struct clk_hw *hw);
@@ -408,7 +269,6 @@ void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
void __iomem **idlest_reg,
u8 *idlest_bit, u8 *idlest_val);
-void omap2_init_clk_hw_omap_clocks(struct clk *clk);
int omap2_clk_enable_autoidle_all(void);
int omap2_clk_disable_autoidle_all(void);
void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
@@ -431,10 +291,8 @@ extern const struct clksel_rate gfx_l3_rates[];
extern const struct clksel_rate dsp_ick_rates[];
extern struct clk dummy_ck;
-extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
extern const struct clk_hw_omap_ops clkhwops_wait;
-extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
extern const struct clk_hw_omap_ops clkhwops_iclk;
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait;
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
diff --git a/arch/arm/mach-omap2/clock3xxx.h b/arch/arm/mach-omap2/clock3xxx.h
index 8cd4b0a..dab90e2 100644
--- a/arch/arm/mach-omap2/clock3xxx.h
+++ b/arch/arm/mach-omap2/clock3xxx.h
@@ -9,8 +9,6 @@
#define __ARCH_ARM_MACH_OMAP2_CLOCK3XXX_H
int omap3xxx_clk_init(void);
-int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
- unsigned long parent_rate);
int omap3_core_dpll_m2_set_rate(struct clk_hw *clk, unsigned long rate,
unsigned long parent_rate);
void omap3_clk_lock_dpll5(void);
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 7b11106..981e14ac 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -32,6 +32,7 @@ obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
obj-$(CONFIG_ARCH_ZYNQ) += zynq/
obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-$(CONFIG_PLAT_SAMSUNG) += samsung/
+obj-$(CONFIG_ARCH_OMAP) += ti/
obj-$(CONFIG_X86) += x86/
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
new file mode 100644
index 0000000..93177987
--- /dev/null
+++ b/drivers/clk/ti/Makefile
@@ -0,0 +1,3 @@
+ifneq ($(CONFIG_OF),)
+obj-y += dpll.o
+endif
diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c
new file mode 100644
index 0000000..f75864e
--- /dev/null
+++ b/drivers/clk/ti/dpll.c
@@ -0,0 +1,580 @@
+/*
+ * OMAP DPLL clock support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo <t-kristo@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk/ti.h>
+
+#define DPLL_HAS_AUTOIDLE 0x1
+
+#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
+ defined(CONFIG_SOC_DRA7XX)
+static const struct clk_ops dpll_m4xen_ck_ops = {
+ .enable = &omap3_noncore_dpll_enable,
+ .disable = &omap3_noncore_dpll_disable,
+ .recalc_rate = &omap4_dpll_regm4xen_recalc,
+ .round_rate = &omap4_dpll_regm4xen_round_rate,
+ .set_rate = &omap3_noncore_dpll_set_rate,
+ .get_parent = &omap2_init_dpll_parent,
+};
+#endif
+
+static const struct clk_ops dpll_core_ck_ops = {
+ .recalc_rate = &omap3_dpll_recalc,
+ .get_parent = &omap2_init_dpll_parent,
+};
+
+#ifdef CONFIG_ARCH_OMAP3
+static const struct clk_ops omap3_dpll_core_ck_ops = {
+ .get_parent = &omap2_init_dpll_parent,
+ .recalc_rate = &omap3_dpll_recalc,
+ .round_rate = &omap2_dpll_round_rate,
+};
+#endif
+
+static const struct clk_ops dpll_ck_ops = {
+ .enable = &omap3_noncore_dpll_enable,
+ .disable = &omap3_noncore_dpll_disable,
+ .recalc_rate = &omap3_dpll_recalc,
+ .round_rate = &omap2_dpll_round_rate,
+ .set_rate = &omap3_noncore_dpll_set_rate,
+ .get_parent = &omap2_init_dpll_parent,
+};
+
+static const struct clk_ops dpll_no_gate_ck_ops = {
+ .recalc_rate = &omap3_dpll_recalc,
+ .get_parent = &omap2_init_dpll_parent,
+ .round_rate = &omap2_dpll_round_rate,
+ .set_rate = &omap3_noncore_dpll_set_rate,
+};
+
+#ifdef CONFIG_ARCH_OMAP3
+static const struct clk_ops omap3_dpll_ck_ops = {
+ .enable = &omap3_noncore_dpll_enable,
+ .disable = &omap3_noncore_dpll_disable,
+ .get_parent = &omap2_init_dpll_parent,
+ .recalc_rate = &omap3_dpll_recalc,
+ .set_rate = &omap3_noncore_dpll_set_rate,
+ .round_rate = &omap2_dpll_round_rate,
+};
+
+static const struct clk_ops omap3_dpll_per_ck_ops = {
+ .enable = &omap3_noncore_dpll_enable,
+ .disable = &omap3_noncore_dpll_disable,
+ .get_parent = &omap2_init_dpll_parent,
+ .recalc_rate = &omap3_dpll_recalc,
+ .set_rate = &omap3_dpll4_set_rate,
+ .round_rate = &omap2_dpll_round_rate,
+};
+#endif
+
+static const struct clk_ops dpll_x2_ck_ops = {
+ .recalc_rate = &omap3_clkoutx2_recalc,
+};
+
+/**
+ * ti_clk_register_dpll() - Registers the DPLL clock
+ * @dev: device pointer (if any)
+ * @name: Name of the clock node
+ * @parent_names: list of parent names
+ * @num_parents: num of parents in parent_names
+ * @flags: init flags
+ * @dpll_data: DPLL data
+ * @ops: ops for DPLL
+ */
+static struct clk *ti_clk_register_dpll(struct device *dev, const char *name,
+ const char **parent_names,
+ int num_parents, unsigned long flags,
+ struct dpll_data *dpll_data,
+ const struct clk_ops *ops)
+{
+ struct clk *clk;
+ struct clk_init_data init = { NULL };
+ struct clk_hw_omap *clk_hw;
+
+ /* allocate the divider */
+ clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
+ if (!clk_hw) {
+ pr_err("%s: could not allocate clk_hw_omap\n", __func__);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ clk_hw->dpll_data = dpll_data;
+ clk_hw->ops = &clkhwops_omap3_dpll;
+ clk_hw->hw.init = &init;
+
+ init.name = name;
+ init.ops = ops;
+ init.flags = flags;
+ init.parent_names = parent_names;
+ init.num_parents = num_parents;
+
+ /* register the clock */
+ clk = clk_register(dev, &clk_hw->hw);
+
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed clk_register for %s (%ld)\n", __func__, name,
+ PTR_ERR(clk));
+ kfree(clk_hw);
+ } else {
+ omap2_init_clk_hw_omap_clocks(clk);
+ }
+
+ return clk;
+}
+
+#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
+ defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM33XX)
+/**
+ * ti_clk_register_dpll_x2() - Registers the DPLLx2 clock
+ * @dev: device pointer (if any)
+ * @name: Name of the clock node
+ * @parent_name: parent name (only 1 parent)
+ * @reg: register address for DPLL
+ * @ops: ops for DPLL
+ */
+static struct clk *ti_clk_register_dpll_x2(struct device *dev, const char *name,
+ const char *parent_name,
+ void __iomem *reg,
+ const struct clk_ops *ops,
+ const struct clk_hw_omap_ops *hw_ops)
+{
+ struct clk *clk;
+ struct clk_init_data init = { NULL };
+ struct clk_hw_omap *clk_hw;
+
+ if (!parent_name) {
+ pr_err("%s: dpll_x2 must have parent\n", __func__);
+ return ERR_PTR(-EINVAL);
+ }
+
+ clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
+ if (!clk_hw) {
+ pr_err("%s: could not allocate clk_hw_omap\n", __func__);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ clk_hw->ops = hw_ops;
+ clk_hw->clksel_reg = reg;
+ clk_hw->hw.init = &init;
+
+ init.name = name;
+ init.ops = ops;
+ init.parent_names = &parent_name;
+ init.num_parents = 1;
+
+ /* register the clock */
+ clk = clk_register(dev, &clk_hw->hw);
+
+ if (IS_ERR(clk))
+ kfree(clk_hw);
+ else
+ omap2_init_clk_hw_omap_clocks(clk);
+
+ return clk;
+}
+#endif
+
+/**
+ * of_ti_dpll_setup() - Setup function for OMAP DPLL clocks
+ *
+ * @node: device node containing the DPLL info
+ * @ops: ops for the DPLL
+ * @ddt: DPLL data template to use
+ * @init_flags: flags for controlling init types
+ */
+static void __init of_ti_dpll_setup(struct device_node *node,
+ const struct clk_ops *ops,
+ const struct dpll_data *ddt,
+ u8 init_flags)
+{
+ struct clk *clk;
+ const char *clk_name = node->name;
+ int num_parents;
+ const char **parent_names = NULL;
+ u8 dpll_flags = 0;
+ struct dpll_data *dd;
+ int i;
+ u8 dpll_mode = 0;
+
+ dd = kzalloc(sizeof(*dd), GFP_KERNEL);
+ if (!dd) {
+ pr_err("%s: could not allocate dpll_data\n", __func__);
+ return;
+ }
+
+ memcpy(dd, ddt, sizeof(*dd));
+
+ of_property_read_string(node, "clock-output-names", &clk_name);
+
+ num_parents = of_clk_get_parent_count(node);
+ if (num_parents < 1) {
+ pr_err("%s: omap dpll %s must have parent(s)\n",
+ __func__, node->name);
+ goto cleanup;
+ }
+
+ parent_names = kzalloc(sizeof(char *) * num_parents, GFP_KERNEL);
+
+ for (i = 0; i < num_parents; i++)
+ parent_names[i] = of_clk_get_parent_name(node, i);
+
+ dd->clk_ref = of_clk_get(node, 0);
+ dd->clk_bypass = of_clk_get(node, 1);
+
+ if (IS_ERR(dd->clk_ref)) {
+ pr_err("%s: ti,clk-ref for %s not found\n", __func__,
+ clk_name);
+ goto cleanup;
+ }
+
+ if (IS_ERR(dd->clk_bypass)) {
+ pr_err("%s: ti,clk-bypass for %s not found\n", __func__,
+ clk_name);
+ goto cleanup;
+ }
+
+ if (init_flags & DPLL_HAS_AUTOIDLE) {
+ dd->control_reg = of_iomap(node, 0);
+ dd->idlest_reg = of_iomap(node, 1);
+ dd->autoidle_reg = of_iomap(node, 2);
+ dd->mult_div1_reg = of_iomap(node, 3);
+ } else {
+ dd->control_reg = of_iomap(node, 0);
+ dd->idlest_reg = of_iomap(node, 1);
+ dd->mult_div1_reg = of_iomap(node, 2);
+ }
+
+ if (of_property_read_bool(node, "ti,low-power-stop"))
+ dpll_mode |= 1 << DPLL_LOW_POWER_STOP;
+
+ if (of_property_read_bool(node, "ti,low-power-bypass"))
+ dpll_mode |= 1 << DPLL_LOW_POWER_STOP;
+
+ if (of_property_read_bool(node, "ti,lock"))
+ dpll_mode |= 1 << DPLL_LOCKED;
+
+ if (dpll_mode)
+ dd->modes = dpll_mode;
+
+ clk = ti_clk_register_dpll(NULL, clk_name, parent_names, num_parents,
+ dpll_flags, dd, ops);
+
+ if (!IS_ERR(clk))
+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
+ return;
+
+cleanup:
+ kfree(dd);
+ kfree(parent_names);
+ return;
+}
+
+#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
+ defined(CONFIG_SOC_DRA7XX)
+static void __init of_ti_omap4_dpll_x2_setup(struct device_node *node)
+{
+ struct clk *clk;
+ const char *clk_name = node->name;
+ void __iomem *reg;
+ const char *parent_name;
+
+ of_property_read_string(node, "clock-output-names", &clk_name);
+
+ parent_name = of_clk_get_parent_name(node, 0);
+
+ reg = of_iomap(node, 0);
+
+ clk = ti_clk_register_dpll_x2(NULL, clk_name, parent_name,
+ reg, &dpll_x2_ck_ops, &clkhwops_omap4_dpllmx);
+
+ if (!IS_ERR(clk))
+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
+}
+CLK_OF_DECLARE(ti_omap4_dpll_x2_clock, "ti,omap4-dpll-x2-clock",
+ of_ti_omap4_dpll_x2_setup);
+#endif
+
+#ifdef CONFIG_SOC_AM33XX
+static void __init of_ti_am3_dpll_x2_setup(struct device_node *node)
+{
+ struct clk *clk;
+ const char *clk_name = node->name;
+ void __iomem *reg;
+ const char *parent_name;
+
+ of_property_read_string(node, "clock-output-names", &clk_name);
+
+ parent_name = of_clk_get_parent_name(node, 0);
+
+ reg = of_iomap(node, 0);
+
+ clk = ti_clk_register_dpll_x2(NULL, clk_name, parent_name,
+ reg, &dpll_x2_ck_ops, NULL);
+
+ if (!IS_ERR(clk))
+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
+}
+CLK_OF_DECLARE(ti_am3_dpll_x2_clock, "ti,am3-dpll-x2-clock",
+ of_ti_am3_dpll_x2_setup);
+#endif
+
+#ifdef CONFIG_ARCH_OMAP3
+static void __init of_ti_omap3_dpll_setup(struct device_node *node)
+{
+ const struct dpll_data dd = {
+ .idlest_mask = 0x1,
+ .enable_mask = 0x7,
+ .autoidle_mask = 0x7,
+ .mult_mask = 0x7ff << 8,
+ .div1_mask = 0x7f,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+ .freqsel_mask = 0xf0,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ };
+
+ of_ti_dpll_setup(node, &omap3_dpll_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
+}
+CLK_OF_DECLARE(ti_omap3_dpll_clock, "ti,omap3-dpll-clock",
+ of_ti_omap3_dpll_setup);
+
+static void __init of_ti_omap3_core_dpll_setup(struct device_node *node)
+{
+ const struct dpll_data dd = {
+ .idlest_mask = 0x1,
+ .enable_mask = 0x7,
+ .autoidle_mask = 0x7,
+ .mult_mask = 0x7ff << 16,
+ .div1_mask = 0x7f << 8,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+ .freqsel_mask = 0xf0,
+ };
+
+ of_ti_dpll_setup(node, &omap3_dpll_core_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
+}
+CLK_OF_DECLARE(ti_omap3_core_dpll_clock, "ti,omap3-dpll-core-clock",
+ of_ti_omap3_core_dpll_setup);
+
+static void __init of_ti_omap3_per_dpll_setup(struct device_node *node)
+{
+ const struct dpll_data dd = {
+ .idlest_mask = 0x1 << 1,
+ .enable_mask = 0x7 << 16,
+ .autoidle_mask = 0x7 << 3,
+ .mult_mask = 0x7ff << 8,
+ .div1_mask = 0x7f,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+ .freqsel_mask = 0xf00000,
+ .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
+ };
+
+ of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
+}
+CLK_OF_DECLARE(ti_omap3_per_dpll_clock, "ti,omap3-dpll-per-clock",
+ of_ti_omap3_per_dpll_setup);
+
+static void __init of_ti_omap3_per_jtype_dpll_setup(struct device_node *node)
+{
+ const struct dpll_data dd = {
+ .idlest_mask = 0x1 << 1,
+ .enable_mask = 0x7 << 16,
+ .autoidle_mask = 0x7 << 3,
+ .mult_mask = 0xfff << 8,
+ .div1_mask = 0x7f,
+ .max_multiplier = 4095,
+ .max_divider = 128,
+ .min_divider = 1,
+ .sddiv_mask = 0xff << 24,
+ .dco_mask = 0xe << 20,
+ .flags = DPLL_J_TYPE,
+ .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
+ };
+
+ of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
+}
+CLK_OF_DECLARE(ti_omap3_per_jtype_dpll_clock, "ti,omap3-dpll-per-j-type-clock",
+ of_ti_omap3_per_jtype_dpll_setup);
+#endif
+
+static void __init of_ti_omap4_dpll_setup(struct device_node *node)
+{
+ const struct dpll_data dd = {
+ .idlest_mask = 0x1,
+ .enable_mask = 0x7,
+ .autoidle_mask = 0x7,
+ .mult_mask = 0x7ff << 8,
+ .div1_mask = 0x7f,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ };
+
+ of_ti_dpll_setup(node, &dpll_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
+}
+CLK_OF_DECLARE(ti_omap4_dpll_clock, "ti,omap4-dpll-clock",
+ of_ti_omap4_dpll_setup);
+
+static void __init of_ti_omap4_core_dpll_setup(struct device_node *node)
+{
+ const struct dpll_data dd = {
+ .idlest_mask = 0x1,
+ .enable_mask = 0x7,
+ .autoidle_mask = 0x7,
+ .mult_mask = 0x7ff << 8,
+ .div1_mask = 0x7f,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ };
+
+ of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
+}
+CLK_OF_DECLARE(ti_omap4_core_dpll_clock, "ti,omap4-dpll-core-clock",
+ of_ti_omap4_core_dpll_setup);
+
+#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
+ defined(CONFIG_SOC_DRA7XX)
+static void __init of_ti_omap4_m4xen_dpll_setup(struct device_node *node)
+{
+ const struct dpll_data dd = {
+ .idlest_mask = 0x1,
+ .enable_mask = 0x7,
+ .autoidle_mask = 0x7,
+ .mult_mask = 0x7ff << 8,
+ .div1_mask = 0x7f,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+ .m4xen_mask = 0x800,
+ .lpmode_mask = 1 << 10,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ };
+
+ of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
+}
+CLK_OF_DECLARE(ti_omap4_m4xen_dpll_clock, "ti,omap4-dpll-m4xen-clock",
+ of_ti_omap4_m4xen_dpll_setup);
+
+static void __init of_ti_omap4_jtype_dpll_setup(struct device_node *node)
+{
+ const struct dpll_data dd = {
+ .idlest_mask = 0x1,
+ .enable_mask = 0x7,
+ .autoidle_mask = 0x7,
+ .mult_mask = 0xfff << 8,
+ .div1_mask = 0xff,
+ .max_multiplier = 4095,
+ .max_divider = 256,
+ .min_divider = 1,
+ .sddiv_mask = 0xff << 24,
+ .flags = DPLL_J_TYPE,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ };
+
+ of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
+}
+CLK_OF_DECLARE(ti_omap4_jtype_dpll_clock, "ti,omap4-dpll-j-type-clock",
+ of_ti_omap4_jtype_dpll_setup);
+#endif
+
+static void __init of_ti_am3_no_gate_dpll_setup(struct device_node *node)
+{
+ const struct dpll_data dd = {
+ .idlest_mask = 0x1,
+ .enable_mask = 0x7,
+ .autoidle_mask = 0x7,
+ .mult_mask = 0x7ff << 8,
+ .div1_mask = 0x7f,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ };
+
+ of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd, 0);
+}
+CLK_OF_DECLARE(ti_am3_no_gate_dpll_clock, "ti,am3-dpll-no-gate-clock",
+ of_ti_am3_no_gate_dpll_setup);
+
+static void __init of_ti_am3_no_gate_jtype_dpll_setup(struct device_node *node)
+{
+ const struct dpll_data dd = {
+ .idlest_mask = 0x1,
+ .enable_mask = 0x7,
+ .autoidle_mask = 0x7,
+ .mult_mask = 0x7ff << 8,
+ .div1_mask = 0x7f,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+ .flags = DPLL_J_TYPE,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ };
+
+ of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd, 0);
+}
+CLK_OF_DECLARE(ti_am3_no_gate_jtype_dpll_clock,
+ "ti,am3-dpll-no-gate-j-type-clock",
+ of_ti_am3_no_gate_jtype_dpll_setup);
+
+static void __init of_ti_am3_dpll_setup(struct device_node *node)
+{
+ const struct dpll_data dd = {
+ .idlest_mask = 0x1,
+ .enable_mask = 0x7,
+ .autoidle_mask = 0x7,
+ .mult_mask = 0x7ff << 8,
+ .div1_mask = 0x7f,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ };
+
+ of_ti_dpll_setup(node, &dpll_ck_ops, &dd, 0);
+}
+CLK_OF_DECLARE(ti_am3_dpll_clock, "ti,am3-dpll-clock", of_ti_am3_dpll_setup);
+
+static void __init of_ti_am3_core_dpll_setup(struct device_node *node)
+{
+ const struct dpll_data dd = {
+ .idlest_mask = 0x1,
+ .enable_mask = 0x7,
+ .autoidle_mask = 0x7,
+ .mult_mask = 0x7ff << 8,
+ .div1_mask = 0x7f,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ };
+
+ of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd, 0);
+}
+CLK_OF_DECLARE(ti_am3_core_dpll_clock, "ti,am3-dpll-core-clock",
+ of_ti_am3_core_dpll_setup);
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
new file mode 100644
index 0000000..385384a
--- /dev/null
+++ b/include/linux/clk/ti.h
@@ -0,0 +1,164 @@
+/*
+ * TI clock drivers support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef __LINUX_CLK_TI_H__
+#define __LINUX_CLK_TI_H__
+
+/**
+ * struct dpll_data - DPLL registers and integration data
+ * @mult_div1_reg: register containing the DPLL M and N bitfields
+ * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
+ * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
+ * @clk_bypass: struct clk pointer to the clock's bypass clock input
+ * @clk_ref: struct clk pointer to the clock's reference clock input
+ * @control_reg: register containing the DPLL mode bitfield
+ * @enable_mask: mask of the DPLL mode bitfield in @control_reg
+ * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
+ * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
+ * @last_rounded_m4xen: cache of the last M4X result of
+ * omap4_dpll_regm4xen_round_rate()
+ * @last_rounded_lpmode: cache of the last lpmode result of
+ * omap4_dpll_lpmode_recalc()
+ * @max_multiplier: maximum valid non-bypass multiplier value (actual)
+ * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
+ * @min_divider: minimum valid non-bypass divider value (actual)
+ * @max_divider: maximum valid non-bypass divider value (actual)
+ * @modes: possible values of @enable_mask
+ * @autoidle_reg: register containing the DPLL autoidle mode bitfield
+ * @idlest_reg: register containing the DPLL idle status bitfield
+ * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
+ * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
+ * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
+ * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
+ * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
+ * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
+ * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
+ * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
+ * @flags: DPLL type/features (see below)
+ *
+ * Possible values for @flags:
+ * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
+ *
+ * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
+ *
+ * XXX Some DPLLs have multiple bypass inputs, so it's not technically
+ * correct to only have one @clk_bypass pointer.
+ *
+ * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
+ * @last_rounded_n) should be separated from the runtime-fixed fields
+ * and placed into a different structure, so that the runtime-fixed data
+ * can be placed into read-only space.
+ */
+struct dpll_data {
+ void __iomem *mult_div1_reg;
+ u32 mult_mask;
+ u32 div1_mask;
+ struct clk *clk_bypass;
+ struct clk *clk_ref;
+ void __iomem *control_reg;
+ u32 enable_mask;
+ unsigned long last_rounded_rate;
+ u16 last_rounded_m;
+ u8 last_rounded_m4xen;
+ u8 last_rounded_lpmode;
+ u16 max_multiplier;
+ u8 last_rounded_n;
+ u8 min_divider;
+ u16 max_divider;
+ u8 modes;
+ void __iomem *autoidle_reg;
+ void __iomem *idlest_reg;
+ u32 autoidle_mask;
+ u32 freqsel_mask;
+ u32 idlest_mask;
+ u32 dco_mask;
+ u32 sddiv_mask;
+ u32 lpmode_mask;
+ u32 m4xen_mask;
+ u8 auto_recal_bit;
+ u8 recal_en_bit;
+ u8 recal_st_bit;
+ u8 flags;
+};
+
+struct clk_hw_omap_ops;
+
+/**
+ * struct clk_hw_omap - OMAP struct clk
+ * @node: list_head connecting this clock into the full clock list
+ * @enable_reg: register to write to enable the clock (see @enable_bit)
+ * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
+ * @flags: see "struct clk.flags possibilities" above
+ * @clksel_reg: for clksel clks, register va containing src/divisor select
+ * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
+ * @clksel: for clksel clks, pointer to struct clksel for this clock
+ * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
+ * @clkdm_name: clockdomain name that this clock is contained in
+ * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
+ * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
+ * @src_offset: bitshift for source selection bitfield (OMAP1 only)
+ *
+ * XXX @rate_offset, @src_offset should probably be removed and OMAP1
+ * clock code converted to use clksel.
+ *
+ */
+struct clk_hw_omap {
+ struct clk_hw hw;
+ struct list_head node;
+ unsigned long fixed_rate;
+ u8 fixed_div;
+ void __iomem *enable_reg;
+ u8 enable_bit;
+ u8 flags;
+ void __iomem *clksel_reg;
+ u32 clksel_mask;
+ const struct clksel *clksel;
+ struct dpll_data *dpll_data;
+ const char *clkdm_name;
+ struct clockdomain *clkdm;
+ const struct clk_hw_omap_ops *ops;
+};
+
+/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
+#define DPLL_LOW_POWER_STOP 0x1
+#define DPLL_LOW_POWER_BYPASS 0x5
+#define DPLL_LOCKED 0x7
+
+/* DPLL Type and DCO Selection Flags */
+#define DPLL_J_TYPE 0x1
+
+void omap2_init_clk_hw_omap_clocks(struct clk *clk);
+int omap3_noncore_dpll_enable(struct clk_hw *hw);
+void omap3_noncore_dpll_disable(struct clk_hw *hw);
+int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate);
+unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
+ unsigned long parent_rate);
+long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
+ unsigned long target_rate,
+ unsigned long *parent_rate);
+u8 omap2_init_dpll_parent(struct clk_hw *hw);
+unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
+long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
+ unsigned long *parent_rate);
+void omap2_init_clk_clkdm(struct clk_hw *clk);
+unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
+ unsigned long parent_rate);
+int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
+ unsigned long parent_rate);
+
+extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
+extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
+
+#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 01/36] CLK: TI: Add DPLL clock support
@ 2013-09-25 8:48 ` Tero Kristo
0 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-arm-kernel
The OMAP clock driver now supports DPLL clock type. This patch also
adds support for DT DPLL nodes.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
.../devicetree/bindings/clock/ti/dpll.txt | 80 +++
arch/arm/mach-omap2/clock.h | 144 +----
arch/arm/mach-omap2/clock3xxx.h | 2 -
drivers/clk/Makefile | 1 +
drivers/clk/ti/Makefile | 3 +
drivers/clk/ti/dpll.c | 580 ++++++++++++++++++++
include/linux/clk/ti.h | 164 ++++++
7 files changed, 829 insertions(+), 145 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/ti/dpll.txt
create mode 100644 drivers/clk/ti/Makefile
create mode 100644 drivers/clk/ti/dpll.c
create mode 100644 include/linux/clk/ti.h
diff --git a/Documentation/devicetree/bindings/clock/ti/dpll.txt b/Documentation/devicetree/bindings/clock/ti/dpll.txt
new file mode 100644
index 0000000..993879f
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/dpll.txt
@@ -0,0 +1,80 @@
+Binding for Texas Instruments DPLL clock.
+
+This binding uses the common clock binding[1]. It assumes a
+register-mapped DPLL with usually two selectable input clocks
+(reference clock and bypass clock), with digital phase locked
+loop logic for multiplying the input clock to a desired output
+clock. This clock also typically supports different operation
+modes (locked, low power stop etc.) This binding has several
+sub-types, which effectively result in slightly different setup
+for the actual DPLL clock.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be one of:
+ "ti,omap3-dpll-clock",
+ "ti,omap3-dpll-core-clock",
+ "ti,omap3-dpll-per-clock",
+ "ti,omap3-dpll-per-j-type-clock",
+ "ti,omap4-dpll-clock",
+ "ti,omap4-dpll-x2-clock",
+ "ti,omap4-dpll-core-clock",
+ "ti,omap4-dpll-m4xen-clock",
+ "ti,omap4-dpll-j-type-clock",
+ "ti,am3-dpll-no-gate-clock",
+ "ti,am3-dpll-no-gate-j-type-clock",
+ "ti,am3-dpll-clock",
+ "ti,am3-dpll-core-clock",
+ "ti,am3-dpll-x2-clock",
+
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : link phandles of parent clocks, first entry lists reference clock
+ and second entry bypass clock
+- reg : address and length of the register set for controlling the DPLL.
+ Registers are listed in following order:
+ "control" - contains the control register base address
+ "idlest" - contains the idle status register base address
+ "autoidle" - contains the autoidle register base address
+ "mult-div1" - contains the multiplier / divider register base address
+ ti,am3-* dpll types list the registers in the same order, except "autoidle"
+ register is left out as this hardware does not have it, e.g.:
+ reg = <0x4000 0x4>, <0x5000 0x4>, <0x6000 0x4>;
+ results in following register map:
+ 0x4000 - control
+ 0x5000 - idlest
+ 0x6000 - mult-div1
+
+Optional properties:
+- DPLL mode setting - defining any one or more of the following overrides
+ default setting.
+ - ti,low-power-stop : DPLL supports low power stop mode, gating output
+ - ti,low-power-bypass : DPLL output matches rate of parent bypass clock
+ - ti,lock : DPLL locks in programmed rate
+
+Examples:
+ dpll_core_ck: dpll_core_ck at 44e00490 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-core-clock";
+ clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+ reg = <0x44e00490 0x4>, <0x44e0045c 0x4>, <0x0 0x4>,
+ <0x44e00468 0x4>;
+ };
+
+ dpll2_ck: dpll2_ck at 48004004 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-dpll-clock";
+ clocks = <&sys_ck>, <&dpll2_fck>;
+ ti,low-power-stop;
+ ti,low-power-bypass;
+ ti,lock;
+ reg = <0x48004004 0x4>, <0x48004024 0x4>, <0x48004034 0x4>,
+ <0x48004040 0x4>;
+ };
+
+ dpll_core_ck: dpll_core_ck at 44e00490 {
+ #clock-cells = <0>;
+ compatible = "ti,am3-dpll-core-clock";
+ clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+ reg = <0x44e00490 0x4>, <0x44e0045c 0x4>, <0x44e00468 0x4>;
+ };
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 7aa32cd..079536a 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -21,6 +21,7 @@
#include <linux/clkdev.h>
#include <linux/clk-provider.h>
+#include <linux/clk/ti.h>
struct omap_clk {
u16 cpu;
@@ -178,83 +179,6 @@ struct clksel {
const struct clksel_rate *rates;
};
-/**
- * struct dpll_data - DPLL registers and integration data
- * @mult_div1_reg: register containing the DPLL M and N bitfields
- * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
- * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
- * @clk_bypass: struct clk pointer to the clock's bypass clock input
- * @clk_ref: struct clk pointer to the clock's reference clock input
- * @control_reg: register containing the DPLL mode bitfield
- * @enable_mask: mask of the DPLL mode bitfield in @control_reg
- * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
- * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
- * @last_rounded_m4xen: cache of the last M4X result of
- * omap4_dpll_regm4xen_round_rate()
- * @last_rounded_lpmode: cache of the last lpmode result of
- * omap4_dpll_lpmode_recalc()
- * @max_multiplier: maximum valid non-bypass multiplier value (actual)
- * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
- * @min_divider: minimum valid non-bypass divider value (actual)
- * @max_divider: maximum valid non-bypass divider value (actual)
- * @modes: possible values of @enable_mask
- * @autoidle_reg: register containing the DPLL autoidle mode bitfield
- * @idlest_reg: register containing the DPLL idle status bitfield
- * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
- * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
- * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
- * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
- * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
- * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
- * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
- * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
- * @flags: DPLL type/features (see below)
- *
- * Possible values for @flags:
- * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
- *
- * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
- *
- * XXX Some DPLLs have multiple bypass inputs, so it's not technically
- * correct to only have one @clk_bypass pointer.
- *
- * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
- * @last_rounded_n) should be separated from the runtime-fixed fields
- * and placed into a different structure, so that the runtime-fixed data
- * can be placed into read-only space.
- */
-struct dpll_data {
- void __iomem *mult_div1_reg;
- u32 mult_mask;
- u32 div1_mask;
- struct clk *clk_bypass;
- struct clk *clk_ref;
- void __iomem *control_reg;
- u32 enable_mask;
- unsigned long last_rounded_rate;
- u16 last_rounded_m;
- u8 last_rounded_m4xen;
- u8 last_rounded_lpmode;
- u16 max_multiplier;
- u8 last_rounded_n;
- u8 min_divider;
- u16 max_divider;
- u8 modes;
- void __iomem *autoidle_reg;
- void __iomem *idlest_reg;
- u32 autoidle_mask;
- u32 freqsel_mask;
- u32 idlest_mask;
- u32 dco_mask;
- u32 sddiv_mask;
- u32 lpmode_mask;
- u32 m4xen_mask;
- u8 auto_recal_bit;
- u8 recal_en_bit;
- u8 recal_st_bit;
- u8 flags;
-};
-
/*
* struct clk.flags possibilities
*
@@ -274,45 +198,6 @@ struct dpll_data {
#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */
#define CLOCK_CLKOUTX2 (1 << 5)
-/**
- * struct clk_hw_omap - OMAP struct clk
- * @node: list_head connecting this clock into the full clock list
- * @enable_reg: register to write to enable the clock (see @enable_bit)
- * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
- * @flags: see "struct clk.flags possibilities" above
- * @clksel_reg: for clksel clks, register va containing src/divisor select
- * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
- * @clksel: for clksel clks, pointer to struct clksel for this clock
- * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
- * @clkdm_name: clockdomain name that this clock is contained in
- * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
- * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
- * @src_offset: bitshift for source selection bitfield (OMAP1 only)
- *
- * XXX @rate_offset, @src_offset should probably be removed and OMAP1
- * clock code converted to use clksel.
- *
- */
-
-struct clk_hw_omap_ops;
-
-struct clk_hw_omap {
- struct clk_hw hw;
- struct list_head node;
- unsigned long fixed_rate;
- u8 fixed_div;
- void __iomem *enable_reg;
- u8 enable_bit;
- u8 flags;
- void __iomem *clksel_reg;
- u32 clksel_mask;
- const struct clksel *clksel;
- struct dpll_data *dpll_data;
- const char *clkdm_name;
- struct clockdomain *clkdm;
- const struct clk_hw_omap_ops *ops;
-};
-
struct clk_hw_omap_ops {
void (*find_idlest)(struct clk_hw_omap *oclk,
void __iomem **idlest_reg,
@@ -348,36 +233,13 @@ unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
#define OMAP4XXX_EN_DPLL_FRBYPASS 0x6
#define OMAP4XXX_EN_DPLL_LOCKED 0x7
-/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
-#define DPLL_LOW_POWER_STOP 0x1
-#define DPLL_LOW_POWER_BYPASS 0x5
-#define DPLL_LOCKED 0x7
-
-/* DPLL Type and DCO Selection Flags */
-#define DPLL_J_TYPE 0x1
-
-long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
- unsigned long *parent_rate);
-unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
-int omap3_noncore_dpll_enable(struct clk_hw *hw);
-void omap3_noncore_dpll_disable(struct clk_hw *hw);
-int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long parent_rate);
u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
void omap3_dpll_allow_idle(struct clk_hw_omap *clk);
void omap3_dpll_deny_idle(struct clk_hw_omap *clk);
-unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
- unsigned long parent_rate);
int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk);
void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk);
void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk);
-unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
- unsigned long parent_rate);
-long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
- unsigned long target_rate,
- unsigned long *parent_rate);
-void omap2_init_clk_clkdm(struct clk_hw *clk);
void __init omap2_clk_disable_clkdm_control(void);
/* clkt_clksel.c public functions */
@@ -396,7 +258,6 @@ int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val);
extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk);
extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);
-u8 omap2_init_dpll_parent(struct clk_hw *hw);
unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
int omap2_dflt_clk_enable(struct clk_hw *hw);
@@ -408,7 +269,6 @@ void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
void __iomem **idlest_reg,
u8 *idlest_bit, u8 *idlest_val);
-void omap2_init_clk_hw_omap_clocks(struct clk *clk);
int omap2_clk_enable_autoidle_all(void);
int omap2_clk_disable_autoidle_all(void);
void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
@@ -431,10 +291,8 @@ extern const struct clksel_rate gfx_l3_rates[];
extern const struct clksel_rate dsp_ick_rates[];
extern struct clk dummy_ck;
-extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
extern const struct clk_hw_omap_ops clkhwops_wait;
-extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
extern const struct clk_hw_omap_ops clkhwops_iclk;
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait;
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
diff --git a/arch/arm/mach-omap2/clock3xxx.h b/arch/arm/mach-omap2/clock3xxx.h
index 8cd4b0a..dab90e2 100644
--- a/arch/arm/mach-omap2/clock3xxx.h
+++ b/arch/arm/mach-omap2/clock3xxx.h
@@ -9,8 +9,6 @@
#define __ARCH_ARM_MACH_OMAP2_CLOCK3XXX_H
int omap3xxx_clk_init(void);
-int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
- unsigned long parent_rate);
int omap3_core_dpll_m2_set_rate(struct clk_hw *clk, unsigned long rate,
unsigned long parent_rate);
void omap3_clk_lock_dpll5(void);
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 7b11106..981e14ac 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -32,6 +32,7 @@ obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
obj-$(CONFIG_ARCH_ZYNQ) += zynq/
obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-$(CONFIG_PLAT_SAMSUNG) += samsung/
+obj-$(CONFIG_ARCH_OMAP) += ti/
obj-$(CONFIG_X86) += x86/
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
new file mode 100644
index 0000000..93177987
--- /dev/null
+++ b/drivers/clk/ti/Makefile
@@ -0,0 +1,3 @@
+ifneq ($(CONFIG_OF),)
+obj-y += dpll.o
+endif
diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c
new file mode 100644
index 0000000..f75864e
--- /dev/null
+++ b/drivers/clk/ti/dpll.c
@@ -0,0 +1,580 @@
+/*
+ * OMAP DPLL clock support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo <t-kristo@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk/ti.h>
+
+#define DPLL_HAS_AUTOIDLE 0x1
+
+#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
+ defined(CONFIG_SOC_DRA7XX)
+static const struct clk_ops dpll_m4xen_ck_ops = {
+ .enable = &omap3_noncore_dpll_enable,
+ .disable = &omap3_noncore_dpll_disable,
+ .recalc_rate = &omap4_dpll_regm4xen_recalc,
+ .round_rate = &omap4_dpll_regm4xen_round_rate,
+ .set_rate = &omap3_noncore_dpll_set_rate,
+ .get_parent = &omap2_init_dpll_parent,
+};
+#endif
+
+static const struct clk_ops dpll_core_ck_ops = {
+ .recalc_rate = &omap3_dpll_recalc,
+ .get_parent = &omap2_init_dpll_parent,
+};
+
+#ifdef CONFIG_ARCH_OMAP3
+static const struct clk_ops omap3_dpll_core_ck_ops = {
+ .get_parent = &omap2_init_dpll_parent,
+ .recalc_rate = &omap3_dpll_recalc,
+ .round_rate = &omap2_dpll_round_rate,
+};
+#endif
+
+static const struct clk_ops dpll_ck_ops = {
+ .enable = &omap3_noncore_dpll_enable,
+ .disable = &omap3_noncore_dpll_disable,
+ .recalc_rate = &omap3_dpll_recalc,
+ .round_rate = &omap2_dpll_round_rate,
+ .set_rate = &omap3_noncore_dpll_set_rate,
+ .get_parent = &omap2_init_dpll_parent,
+};
+
+static const struct clk_ops dpll_no_gate_ck_ops = {
+ .recalc_rate = &omap3_dpll_recalc,
+ .get_parent = &omap2_init_dpll_parent,
+ .round_rate = &omap2_dpll_round_rate,
+ .set_rate = &omap3_noncore_dpll_set_rate,
+};
+
+#ifdef CONFIG_ARCH_OMAP3
+static const struct clk_ops omap3_dpll_ck_ops = {
+ .enable = &omap3_noncore_dpll_enable,
+ .disable = &omap3_noncore_dpll_disable,
+ .get_parent = &omap2_init_dpll_parent,
+ .recalc_rate = &omap3_dpll_recalc,
+ .set_rate = &omap3_noncore_dpll_set_rate,
+ .round_rate = &omap2_dpll_round_rate,
+};
+
+static const struct clk_ops omap3_dpll_per_ck_ops = {
+ .enable = &omap3_noncore_dpll_enable,
+ .disable = &omap3_noncore_dpll_disable,
+ .get_parent = &omap2_init_dpll_parent,
+ .recalc_rate = &omap3_dpll_recalc,
+ .set_rate = &omap3_dpll4_set_rate,
+ .round_rate = &omap2_dpll_round_rate,
+};
+#endif
+
+static const struct clk_ops dpll_x2_ck_ops = {
+ .recalc_rate = &omap3_clkoutx2_recalc,
+};
+
+/**
+ * ti_clk_register_dpll() - Registers the DPLL clock
+ * @dev: device pointer (if any)
+ * @name: Name of the clock node
+ * @parent_names: list of parent names
+ * @num_parents: num of parents in parent_names
+ * @flags: init flags
+ * @dpll_data: DPLL data
+ * @ops: ops for DPLL
+ */
+static struct clk *ti_clk_register_dpll(struct device *dev, const char *name,
+ const char **parent_names,
+ int num_parents, unsigned long flags,
+ struct dpll_data *dpll_data,
+ const struct clk_ops *ops)
+{
+ struct clk *clk;
+ struct clk_init_data init = { NULL };
+ struct clk_hw_omap *clk_hw;
+
+ /* allocate the divider */
+ clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
+ if (!clk_hw) {
+ pr_err("%s: could not allocate clk_hw_omap\n", __func__);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ clk_hw->dpll_data = dpll_data;
+ clk_hw->ops = &clkhwops_omap3_dpll;
+ clk_hw->hw.init = &init;
+
+ init.name = name;
+ init.ops = ops;
+ init.flags = flags;
+ init.parent_names = parent_names;
+ init.num_parents = num_parents;
+
+ /* register the clock */
+ clk = clk_register(dev, &clk_hw->hw);
+
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed clk_register for %s (%ld)\n", __func__, name,
+ PTR_ERR(clk));
+ kfree(clk_hw);
+ } else {
+ omap2_init_clk_hw_omap_clocks(clk);
+ }
+
+ return clk;
+}
+
+#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
+ defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM33XX)
+/**
+ * ti_clk_register_dpll_x2() - Registers the DPLLx2 clock
+ * @dev: device pointer (if any)
+ * @name: Name of the clock node
+ * @parent_name: parent name (only 1 parent)
+ * @reg: register address for DPLL
+ * @ops: ops for DPLL
+ */
+static struct clk *ti_clk_register_dpll_x2(struct device *dev, const char *name,
+ const char *parent_name,
+ void __iomem *reg,
+ const struct clk_ops *ops,
+ const struct clk_hw_omap_ops *hw_ops)
+{
+ struct clk *clk;
+ struct clk_init_data init = { NULL };
+ struct clk_hw_omap *clk_hw;
+
+ if (!parent_name) {
+ pr_err("%s: dpll_x2 must have parent\n", __func__);
+ return ERR_PTR(-EINVAL);
+ }
+
+ clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
+ if (!clk_hw) {
+ pr_err("%s: could not allocate clk_hw_omap\n", __func__);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ clk_hw->ops = hw_ops;
+ clk_hw->clksel_reg = reg;
+ clk_hw->hw.init = &init;
+
+ init.name = name;
+ init.ops = ops;
+ init.parent_names = &parent_name;
+ init.num_parents = 1;
+
+ /* register the clock */
+ clk = clk_register(dev, &clk_hw->hw);
+
+ if (IS_ERR(clk))
+ kfree(clk_hw);
+ else
+ omap2_init_clk_hw_omap_clocks(clk);
+
+ return clk;
+}
+#endif
+
+/**
+ * of_ti_dpll_setup() - Setup function for OMAP DPLL clocks
+ *
+ * @node: device node containing the DPLL info
+ * @ops: ops for the DPLL
+ * @ddt: DPLL data template to use
+ * @init_flags: flags for controlling init types
+ */
+static void __init of_ti_dpll_setup(struct device_node *node,
+ const struct clk_ops *ops,
+ const struct dpll_data *ddt,
+ u8 init_flags)
+{
+ struct clk *clk;
+ const char *clk_name = node->name;
+ int num_parents;
+ const char **parent_names = NULL;
+ u8 dpll_flags = 0;
+ struct dpll_data *dd;
+ int i;
+ u8 dpll_mode = 0;
+
+ dd = kzalloc(sizeof(*dd), GFP_KERNEL);
+ if (!dd) {
+ pr_err("%s: could not allocate dpll_data\n", __func__);
+ return;
+ }
+
+ memcpy(dd, ddt, sizeof(*dd));
+
+ of_property_read_string(node, "clock-output-names", &clk_name);
+
+ num_parents = of_clk_get_parent_count(node);
+ if (num_parents < 1) {
+ pr_err("%s: omap dpll %s must have parent(s)\n",
+ __func__, node->name);
+ goto cleanup;
+ }
+
+ parent_names = kzalloc(sizeof(char *) * num_parents, GFP_KERNEL);
+
+ for (i = 0; i < num_parents; i++)
+ parent_names[i] = of_clk_get_parent_name(node, i);
+
+ dd->clk_ref = of_clk_get(node, 0);
+ dd->clk_bypass = of_clk_get(node, 1);
+
+ if (IS_ERR(dd->clk_ref)) {
+ pr_err("%s: ti,clk-ref for %s not found\n", __func__,
+ clk_name);
+ goto cleanup;
+ }
+
+ if (IS_ERR(dd->clk_bypass)) {
+ pr_err("%s: ti,clk-bypass for %s not found\n", __func__,
+ clk_name);
+ goto cleanup;
+ }
+
+ if (init_flags & DPLL_HAS_AUTOIDLE) {
+ dd->control_reg = of_iomap(node, 0);
+ dd->idlest_reg = of_iomap(node, 1);
+ dd->autoidle_reg = of_iomap(node, 2);
+ dd->mult_div1_reg = of_iomap(node, 3);
+ } else {
+ dd->control_reg = of_iomap(node, 0);
+ dd->idlest_reg = of_iomap(node, 1);
+ dd->mult_div1_reg = of_iomap(node, 2);
+ }
+
+ if (of_property_read_bool(node, "ti,low-power-stop"))
+ dpll_mode |= 1 << DPLL_LOW_POWER_STOP;
+
+ if (of_property_read_bool(node, "ti,low-power-bypass"))
+ dpll_mode |= 1 << DPLL_LOW_POWER_STOP;
+
+ if (of_property_read_bool(node, "ti,lock"))
+ dpll_mode |= 1 << DPLL_LOCKED;
+
+ if (dpll_mode)
+ dd->modes = dpll_mode;
+
+ clk = ti_clk_register_dpll(NULL, clk_name, parent_names, num_parents,
+ dpll_flags, dd, ops);
+
+ if (!IS_ERR(clk))
+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
+ return;
+
+cleanup:
+ kfree(dd);
+ kfree(parent_names);
+ return;
+}
+
+#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
+ defined(CONFIG_SOC_DRA7XX)
+static void __init of_ti_omap4_dpll_x2_setup(struct device_node *node)
+{
+ struct clk *clk;
+ const char *clk_name = node->name;
+ void __iomem *reg;
+ const char *parent_name;
+
+ of_property_read_string(node, "clock-output-names", &clk_name);
+
+ parent_name = of_clk_get_parent_name(node, 0);
+
+ reg = of_iomap(node, 0);
+
+ clk = ti_clk_register_dpll_x2(NULL, clk_name, parent_name,
+ reg, &dpll_x2_ck_ops, &clkhwops_omap4_dpllmx);
+
+ if (!IS_ERR(clk))
+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
+}
+CLK_OF_DECLARE(ti_omap4_dpll_x2_clock, "ti,omap4-dpll-x2-clock",
+ of_ti_omap4_dpll_x2_setup);
+#endif
+
+#ifdef CONFIG_SOC_AM33XX
+static void __init of_ti_am3_dpll_x2_setup(struct device_node *node)
+{
+ struct clk *clk;
+ const char *clk_name = node->name;
+ void __iomem *reg;
+ const char *parent_name;
+
+ of_property_read_string(node, "clock-output-names", &clk_name);
+
+ parent_name = of_clk_get_parent_name(node, 0);
+
+ reg = of_iomap(node, 0);
+
+ clk = ti_clk_register_dpll_x2(NULL, clk_name, parent_name,
+ reg, &dpll_x2_ck_ops, NULL);
+
+ if (!IS_ERR(clk))
+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
+}
+CLK_OF_DECLARE(ti_am3_dpll_x2_clock, "ti,am3-dpll-x2-clock",
+ of_ti_am3_dpll_x2_setup);
+#endif
+
+#ifdef CONFIG_ARCH_OMAP3
+static void __init of_ti_omap3_dpll_setup(struct device_node *node)
+{
+ const struct dpll_data dd = {
+ .idlest_mask = 0x1,
+ .enable_mask = 0x7,
+ .autoidle_mask = 0x7,
+ .mult_mask = 0x7ff << 8,
+ .div1_mask = 0x7f,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+ .freqsel_mask = 0xf0,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ };
+
+ of_ti_dpll_setup(node, &omap3_dpll_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
+}
+CLK_OF_DECLARE(ti_omap3_dpll_clock, "ti,omap3-dpll-clock",
+ of_ti_omap3_dpll_setup);
+
+static void __init of_ti_omap3_core_dpll_setup(struct device_node *node)
+{
+ const struct dpll_data dd = {
+ .idlest_mask = 0x1,
+ .enable_mask = 0x7,
+ .autoidle_mask = 0x7,
+ .mult_mask = 0x7ff << 16,
+ .div1_mask = 0x7f << 8,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+ .freqsel_mask = 0xf0,
+ };
+
+ of_ti_dpll_setup(node, &omap3_dpll_core_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
+}
+CLK_OF_DECLARE(ti_omap3_core_dpll_clock, "ti,omap3-dpll-core-clock",
+ of_ti_omap3_core_dpll_setup);
+
+static void __init of_ti_omap3_per_dpll_setup(struct device_node *node)
+{
+ const struct dpll_data dd = {
+ .idlest_mask = 0x1 << 1,
+ .enable_mask = 0x7 << 16,
+ .autoidle_mask = 0x7 << 3,
+ .mult_mask = 0x7ff << 8,
+ .div1_mask = 0x7f,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+ .freqsel_mask = 0xf00000,
+ .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
+ };
+
+ of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
+}
+CLK_OF_DECLARE(ti_omap3_per_dpll_clock, "ti,omap3-dpll-per-clock",
+ of_ti_omap3_per_dpll_setup);
+
+static void __init of_ti_omap3_per_jtype_dpll_setup(struct device_node *node)
+{
+ const struct dpll_data dd = {
+ .idlest_mask = 0x1 << 1,
+ .enable_mask = 0x7 << 16,
+ .autoidle_mask = 0x7 << 3,
+ .mult_mask = 0xfff << 8,
+ .div1_mask = 0x7f,
+ .max_multiplier = 4095,
+ .max_divider = 128,
+ .min_divider = 1,
+ .sddiv_mask = 0xff << 24,
+ .dco_mask = 0xe << 20,
+ .flags = DPLL_J_TYPE,
+ .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
+ };
+
+ of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
+}
+CLK_OF_DECLARE(ti_omap3_per_jtype_dpll_clock, "ti,omap3-dpll-per-j-type-clock",
+ of_ti_omap3_per_jtype_dpll_setup);
+#endif
+
+static void __init of_ti_omap4_dpll_setup(struct device_node *node)
+{
+ const struct dpll_data dd = {
+ .idlest_mask = 0x1,
+ .enable_mask = 0x7,
+ .autoidle_mask = 0x7,
+ .mult_mask = 0x7ff << 8,
+ .div1_mask = 0x7f,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ };
+
+ of_ti_dpll_setup(node, &dpll_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
+}
+CLK_OF_DECLARE(ti_omap4_dpll_clock, "ti,omap4-dpll-clock",
+ of_ti_omap4_dpll_setup);
+
+static void __init of_ti_omap4_core_dpll_setup(struct device_node *node)
+{
+ const struct dpll_data dd = {
+ .idlest_mask = 0x1,
+ .enable_mask = 0x7,
+ .autoidle_mask = 0x7,
+ .mult_mask = 0x7ff << 8,
+ .div1_mask = 0x7f,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ };
+
+ of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
+}
+CLK_OF_DECLARE(ti_omap4_core_dpll_clock, "ti,omap4-dpll-core-clock",
+ of_ti_omap4_core_dpll_setup);
+
+#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
+ defined(CONFIG_SOC_DRA7XX)
+static void __init of_ti_omap4_m4xen_dpll_setup(struct device_node *node)
+{
+ const struct dpll_data dd = {
+ .idlest_mask = 0x1,
+ .enable_mask = 0x7,
+ .autoidle_mask = 0x7,
+ .mult_mask = 0x7ff << 8,
+ .div1_mask = 0x7f,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+ .m4xen_mask = 0x800,
+ .lpmode_mask = 1 << 10,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ };
+
+ of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
+}
+CLK_OF_DECLARE(ti_omap4_m4xen_dpll_clock, "ti,omap4-dpll-m4xen-clock",
+ of_ti_omap4_m4xen_dpll_setup);
+
+static void __init of_ti_omap4_jtype_dpll_setup(struct device_node *node)
+{
+ const struct dpll_data dd = {
+ .idlest_mask = 0x1,
+ .enable_mask = 0x7,
+ .autoidle_mask = 0x7,
+ .mult_mask = 0xfff << 8,
+ .div1_mask = 0xff,
+ .max_multiplier = 4095,
+ .max_divider = 256,
+ .min_divider = 1,
+ .sddiv_mask = 0xff << 24,
+ .flags = DPLL_J_TYPE,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ };
+
+ of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
+}
+CLK_OF_DECLARE(ti_omap4_jtype_dpll_clock, "ti,omap4-dpll-j-type-clock",
+ of_ti_omap4_jtype_dpll_setup);
+#endif
+
+static void __init of_ti_am3_no_gate_dpll_setup(struct device_node *node)
+{
+ const struct dpll_data dd = {
+ .idlest_mask = 0x1,
+ .enable_mask = 0x7,
+ .autoidle_mask = 0x7,
+ .mult_mask = 0x7ff << 8,
+ .div1_mask = 0x7f,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ };
+
+ of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd, 0);
+}
+CLK_OF_DECLARE(ti_am3_no_gate_dpll_clock, "ti,am3-dpll-no-gate-clock",
+ of_ti_am3_no_gate_dpll_setup);
+
+static void __init of_ti_am3_no_gate_jtype_dpll_setup(struct device_node *node)
+{
+ const struct dpll_data dd = {
+ .idlest_mask = 0x1,
+ .enable_mask = 0x7,
+ .autoidle_mask = 0x7,
+ .mult_mask = 0x7ff << 8,
+ .div1_mask = 0x7f,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+ .flags = DPLL_J_TYPE,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ };
+
+ of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd, 0);
+}
+CLK_OF_DECLARE(ti_am3_no_gate_jtype_dpll_clock,
+ "ti,am3-dpll-no-gate-j-type-clock",
+ of_ti_am3_no_gate_jtype_dpll_setup);
+
+static void __init of_ti_am3_dpll_setup(struct device_node *node)
+{
+ const struct dpll_data dd = {
+ .idlest_mask = 0x1,
+ .enable_mask = 0x7,
+ .autoidle_mask = 0x7,
+ .mult_mask = 0x7ff << 8,
+ .div1_mask = 0x7f,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ };
+
+ of_ti_dpll_setup(node, &dpll_ck_ops, &dd, 0);
+}
+CLK_OF_DECLARE(ti_am3_dpll_clock, "ti,am3-dpll-clock", of_ti_am3_dpll_setup);
+
+static void __init of_ti_am3_core_dpll_setup(struct device_node *node)
+{
+ const struct dpll_data dd = {
+ .idlest_mask = 0x1,
+ .enable_mask = 0x7,
+ .autoidle_mask = 0x7,
+ .mult_mask = 0x7ff << 8,
+ .div1_mask = 0x7f,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ };
+
+ of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd, 0);
+}
+CLK_OF_DECLARE(ti_am3_core_dpll_clock, "ti,am3-dpll-core-clock",
+ of_ti_am3_core_dpll_setup);
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
new file mode 100644
index 0000000..385384a
--- /dev/null
+++ b/include/linux/clk/ti.h
@@ -0,0 +1,164 @@
+/*
+ * TI clock drivers support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef __LINUX_CLK_TI_H__
+#define __LINUX_CLK_TI_H__
+
+/**
+ * struct dpll_data - DPLL registers and integration data
+ * @mult_div1_reg: register containing the DPLL M and N bitfields
+ * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
+ * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
+ * @clk_bypass: struct clk pointer to the clock's bypass clock input
+ * @clk_ref: struct clk pointer to the clock's reference clock input
+ * @control_reg: register containing the DPLL mode bitfield
+ * @enable_mask: mask of the DPLL mode bitfield in @control_reg
+ * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
+ * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
+ * @last_rounded_m4xen: cache of the last M4X result of
+ * omap4_dpll_regm4xen_round_rate()
+ * @last_rounded_lpmode: cache of the last lpmode result of
+ * omap4_dpll_lpmode_recalc()
+ * @max_multiplier: maximum valid non-bypass multiplier value (actual)
+ * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
+ * @min_divider: minimum valid non-bypass divider value (actual)
+ * @max_divider: maximum valid non-bypass divider value (actual)
+ * @modes: possible values of @enable_mask
+ * @autoidle_reg: register containing the DPLL autoidle mode bitfield
+ * @idlest_reg: register containing the DPLL idle status bitfield
+ * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
+ * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
+ * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
+ * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
+ * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
+ * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
+ * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
+ * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
+ * @flags: DPLL type/features (see below)
+ *
+ * Possible values for @flags:
+ * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
+ *
+ * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
+ *
+ * XXX Some DPLLs have multiple bypass inputs, so it's not technically
+ * correct to only have one @clk_bypass pointer.
+ *
+ * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
+ * @last_rounded_n) should be separated from the runtime-fixed fields
+ * and placed into a different structure, so that the runtime-fixed data
+ * can be placed into read-only space.
+ */
+struct dpll_data {
+ void __iomem *mult_div1_reg;
+ u32 mult_mask;
+ u32 div1_mask;
+ struct clk *clk_bypass;
+ struct clk *clk_ref;
+ void __iomem *control_reg;
+ u32 enable_mask;
+ unsigned long last_rounded_rate;
+ u16 last_rounded_m;
+ u8 last_rounded_m4xen;
+ u8 last_rounded_lpmode;
+ u16 max_multiplier;
+ u8 last_rounded_n;
+ u8 min_divider;
+ u16 max_divider;
+ u8 modes;
+ void __iomem *autoidle_reg;
+ void __iomem *idlest_reg;
+ u32 autoidle_mask;
+ u32 freqsel_mask;
+ u32 idlest_mask;
+ u32 dco_mask;
+ u32 sddiv_mask;
+ u32 lpmode_mask;
+ u32 m4xen_mask;
+ u8 auto_recal_bit;
+ u8 recal_en_bit;
+ u8 recal_st_bit;
+ u8 flags;
+};
+
+struct clk_hw_omap_ops;
+
+/**
+ * struct clk_hw_omap - OMAP struct clk
+ * @node: list_head connecting this clock into the full clock list
+ * @enable_reg: register to write to enable the clock (see @enable_bit)
+ * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
+ * @flags: see "struct clk.flags possibilities" above
+ * @clksel_reg: for clksel clks, register va containing src/divisor select
+ * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
+ * @clksel: for clksel clks, pointer to struct clksel for this clock
+ * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
+ * @clkdm_name: clockdomain name that this clock is contained in
+ * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name@runtime
+ * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
+ * @src_offset: bitshift for source selection bitfield (OMAP1 only)
+ *
+ * XXX @rate_offset, @src_offset should probably be removed and OMAP1
+ * clock code converted to use clksel.
+ *
+ */
+struct clk_hw_omap {
+ struct clk_hw hw;
+ struct list_head node;
+ unsigned long fixed_rate;
+ u8 fixed_div;
+ void __iomem *enable_reg;
+ u8 enable_bit;
+ u8 flags;
+ void __iomem *clksel_reg;
+ u32 clksel_mask;
+ const struct clksel *clksel;
+ struct dpll_data *dpll_data;
+ const char *clkdm_name;
+ struct clockdomain *clkdm;
+ const struct clk_hw_omap_ops *ops;
+};
+
+/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
+#define DPLL_LOW_POWER_STOP 0x1
+#define DPLL_LOW_POWER_BYPASS 0x5
+#define DPLL_LOCKED 0x7
+
+/* DPLL Type and DCO Selection Flags */
+#define DPLL_J_TYPE 0x1
+
+void omap2_init_clk_hw_omap_clocks(struct clk *clk);
+int omap3_noncore_dpll_enable(struct clk_hw *hw);
+void omap3_noncore_dpll_disable(struct clk_hw *hw);
+int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate);
+unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
+ unsigned long parent_rate);
+long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
+ unsigned long target_rate,
+ unsigned long *parent_rate);
+u8 omap2_init_dpll_parent(struct clk_hw *hw);
+unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
+long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
+ unsigned long *parent_rate);
+void omap2_init_clk_clkdm(struct clk_hw *clk);
+unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
+ unsigned long parent_rate);
+int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
+ unsigned long parent_rate);
+
+extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
+extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
+
+#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 02/36] CLK: TI: add DT alias clock registration mechanism
2013-09-25 8:48 ` Tero Kristo
@ 2013-09-25 8:48 ` Tero Kristo
-1 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-omap-u79uwXL29TY76Z2rM5mHXA, paul-DWxLp4Yu+b8AvxtiuMwx3w,
tony-4v6yS6AI5VpBDgjK7y7TUQ, nm-l0cyMroinI0, rnayak-l0cyMroinI0,
bcousson-rdvid1DuHRBWk0Htik3J/w,
mturquette-QSEj5FYQhm4dnm+yROfE0A
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
Some devices require their clocks to be available with a specific
dev-id con-id mapping. With DT, the clocks can be found by default
only with their name, or alternatively through the device node of
the consumer. With drivers, that don't support DT fully yet, add
mechanism to register specific clock names.
Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
drivers/clk/ti/Makefile | 2 +-
drivers/clk/ti/clk.c | 52 +++++++++++++++++++++++++++++++++++++++++++++++
include/linux/clk/ti.h | 23 +++++++++++++++++++++
3 files changed, 76 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/ti/clk.c
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 93177987..05af5d8 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,3 +1,3 @@
ifneq ($(CONFIG_OF),)
-obj-y += dpll.o
+obj-y += clk.o dpll.o
endif
diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c
new file mode 100644
index 0000000..ad58b01
--- /dev/null
+++ b/drivers/clk/ti/clk.c
@@ -0,0 +1,52 @@
+/*
+ * TI clock support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/clk/ti.h>
+#include <linux/of.h>
+
+/**
+ * ti_dt_clocks_register - register DT duplicate clocks during boot
+ * @oclks: list of clocks to register
+ *
+ * Register duplicate or non-standard DT clock entries during boot. By
+ * default, DT clocks are found based on their node name. If any
+ * additional con-id / dev-id -> clock mapping is required, use this
+ * function to list these.
+ */
+void __init ti_dt_clocks_register(struct ti_dt_clk oclks[])
+{
+ struct ti_dt_clk *c;
+ struct device_node *node;
+ struct clk *clk;
+ struct of_phandle_args clkspec;
+
+ for (c = oclks; c->node_name != NULL; c++) {
+ node = of_find_node_by_name(NULL, c->node_name);
+ clkspec.np = node;
+ clk = of_clk_get_from_provider(&clkspec);
+
+ if (!IS_ERR(clk)) {
+ c->lk.clk = clk;
+ clkdev_add(&c->lk);
+ } else {
+ pr_warn("%s: failed to lookup clock node %s\n",
+ __func__, c->node_name);
+ }
+ }
+}
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 385384a..c89574e 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -15,6 +15,8 @@
#ifndef __LINUX_CLK_TI_H__
#define __LINUX_CLK_TI_H__
+#include <linux/clkdev.h>
+
/**
* struct dpll_data - DPLL registers and integration data
* @mult_div1_reg: register containing the DPLL M and N bitfields
@@ -138,6 +140,25 @@ struct clk_hw_omap {
/* DPLL Type and DCO Selection Flags */
#define DPLL_J_TYPE 0x1
+/**
+ * struct ti_dt_clk - OMAP DT clock alias declarations
+ * @lk: clock lookup definition
+ * @node_name: clock DT node to map to
+ */
+struct ti_dt_clk {
+ struct clk_lookup lk;
+ char *node_name;
+};
+
+#define DT_CLK(dev, con, name) \
+ { \
+ .lk = { \
+ .dev_id = dev, \
+ .con_id = con, \
+ }, \
+ .node_name = name, \
+ }
+
void omap2_init_clk_hw_omap_clocks(struct clk *clk);
int omap3_noncore_dpll_enable(struct clk_hw *hw);
void omap3_noncore_dpll_disable(struct clk_hw *hw);
@@ -158,6 +179,8 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
unsigned long parent_rate);
+void ti_dt_clocks_register(struct ti_dt_clk *oclks);
+
extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
--
1.7.9.5
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 02/36] CLK: TI: add DT alias clock registration mechanism
@ 2013-09-25 8:48 ` Tero Kristo
0 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-arm-kernel
Some devices require their clocks to be available with a specific
dev-id con-id mapping. With DT, the clocks can be found by default
only with their name, or alternatively through the device node of
the consumer. With drivers, that don't support DT fully yet, add
mechanism to register specific clock names.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
drivers/clk/ti/Makefile | 2 +-
drivers/clk/ti/clk.c | 52 +++++++++++++++++++++++++++++++++++++++++++++++
include/linux/clk/ti.h | 23 +++++++++++++++++++++
3 files changed, 76 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/ti/clk.c
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 93177987..05af5d8 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,3 +1,3 @@
ifneq ($(CONFIG_OF),)
-obj-y += dpll.o
+obj-y += clk.o dpll.o
endif
diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c
new file mode 100644
index 0000000..ad58b01
--- /dev/null
+++ b/drivers/clk/ti/clk.c
@@ -0,0 +1,52 @@
+/*
+ * TI clock support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo <t-kristo@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/clk/ti.h>
+#include <linux/of.h>
+
+/**
+ * ti_dt_clocks_register - register DT duplicate clocks during boot
+ * @oclks: list of clocks to register
+ *
+ * Register duplicate or non-standard DT clock entries during boot. By
+ * default, DT clocks are found based on their node name. If any
+ * additional con-id / dev-id -> clock mapping is required, use this
+ * function to list these.
+ */
+void __init ti_dt_clocks_register(struct ti_dt_clk oclks[])
+{
+ struct ti_dt_clk *c;
+ struct device_node *node;
+ struct clk *clk;
+ struct of_phandle_args clkspec;
+
+ for (c = oclks; c->node_name != NULL; c++) {
+ node = of_find_node_by_name(NULL, c->node_name);
+ clkspec.np = node;
+ clk = of_clk_get_from_provider(&clkspec);
+
+ if (!IS_ERR(clk)) {
+ c->lk.clk = clk;
+ clkdev_add(&c->lk);
+ } else {
+ pr_warn("%s: failed to lookup clock node %s\n",
+ __func__, c->node_name);
+ }
+ }
+}
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 385384a..c89574e 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -15,6 +15,8 @@
#ifndef __LINUX_CLK_TI_H__
#define __LINUX_CLK_TI_H__
+#include <linux/clkdev.h>
+
/**
* struct dpll_data - DPLL registers and integration data
* @mult_div1_reg: register containing the DPLL M and N bitfields
@@ -138,6 +140,25 @@ struct clk_hw_omap {
/* DPLL Type and DCO Selection Flags */
#define DPLL_J_TYPE 0x1
+/**
+ * struct ti_dt_clk - OMAP DT clock alias declarations
+ * @lk: clock lookup definition
+ * @node_name: clock DT node to map to
+ */
+struct ti_dt_clk {
+ struct clk_lookup lk;
+ char *node_name;
+};
+
+#define DT_CLK(dev, con, name) \
+ { \
+ .lk = { \
+ .dev_id = dev, \
+ .con_id = con, \
+ }, \
+ .node_name = name, \
+ }
+
void omap2_init_clk_hw_omap_clocks(struct clk *clk);
int omap3_noncore_dpll_enable(struct clk_hw *hw);
void omap3_noncore_dpll_disable(struct clk_hw *hw);
@@ -158,6 +179,8 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
unsigned long parent_rate);
+void ti_dt_clocks_register(struct ti_dt_clk *oclks);
+
extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 03/36] CLK: TI: add autoidle support
2013-09-25 8:48 ` Tero Kristo
@ 2013-09-25 8:48 ` Tero Kristo
-1 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-omap-u79uwXL29TY76Z2rM5mHXA, paul-DWxLp4Yu+b8AvxtiuMwx3w,
tony-4v6yS6AI5VpBDgjK7y7TUQ, nm-l0cyMroinI0, rnayak-l0cyMroinI0,
bcousson-rdvid1DuHRBWk0Htik3J/w,
mturquette-QSEj5FYQhm4dnm+yROfE0A
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
TI clk driver now routes some of the basic clocks through own
registration routine to allow autoidle support. This routine just
checks a couple of device node properties and adds autoidle support
if required, and just passes the registration forward to basic clocks.
Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
arch/arm/mach-omap2/clock.c | 6 +++
drivers/clk/ti/Makefile | 2 +-
drivers/clk/ti/autoidle.c | 107 +++++++++++++++++++++++++++++++++++++++++++
include/linux/clk/ti.h | 9 ++++
4 files changed, 123 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/ti/autoidle.c
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 0c38ca9..223f432b 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -520,6 +520,9 @@ int omap2_clk_enable_autoidle_all(void)
list_for_each_entry(c, &clk_hw_omap_clocks, node)
if (c->ops && c->ops->allow_idle)
c->ops->allow_idle(c);
+
+ of_ti_clk_allow_autoidle_all();
+
return 0;
}
@@ -539,6 +542,9 @@ int omap2_clk_disable_autoidle_all(void)
list_for_each_entry(c, &clk_hw_omap_clocks, node)
if (c->ops && c->ops->deny_idle)
c->ops->deny_idle(c);
+
+ of_ti_clk_deny_autoidle_all();
+
return 0;
}
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 05af5d8..533efb4 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,3 +1,3 @@
ifneq ($(CONFIG_OF),)
-obj-y += clk.o dpll.o
+obj-y += clk.o dpll.o autoidle.o
endif
diff --git a/drivers/clk/ti/autoidle.c b/drivers/clk/ti/autoidle.c
new file mode 100644
index 0000000..ccac33c
--- /dev/null
+++ b/drivers/clk/ti/autoidle.c
@@ -0,0 +1,107 @@
+/*
+ * TI clock autoidle support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk/ti.h>
+
+struct clk_ti_autoidle {
+ void __iomem *reg;
+ u8 shift;
+ u8 flags;
+ const char *name;
+ struct list_head node;
+};
+
+#define AUTOIDLE_LOW 0x1
+
+static LIST_HEAD(autoidle_clks);
+
+static void ti_allow_autoidle(struct clk_ti_autoidle *clk)
+{
+ u32 val;
+
+ val = readl(clk->reg);
+
+ if (clk->flags & AUTOIDLE_LOW)
+ val &= ~(1 << clk->shift);
+ else
+ val |= (1 << clk->shift);
+
+ writel(val, clk->reg);
+}
+
+static void ti_deny_autoidle(struct clk_ti_autoidle *clk)
+{
+ u32 val;
+
+ val = readl(clk->reg);
+
+ if (clk->flags & AUTOIDLE_LOW)
+ val |= (1 << clk->shift);
+ else
+ val &= ~(1 << clk->shift);
+
+ writel(val, clk->reg);
+}
+
+void of_ti_clk_allow_autoidle_all(void)
+{
+ struct clk_ti_autoidle *c;
+
+ list_for_each_entry(c, &autoidle_clks, node)
+ ti_allow_autoidle(c);
+}
+
+void of_ti_clk_deny_autoidle_all(void)
+{
+ struct clk_ti_autoidle *c;
+
+ list_for_each_entry(c, &autoidle_clks, node)
+ ti_deny_autoidle(c);
+}
+
+void __init of_ti_autoidle_setup(struct device_node *node)
+{
+ u32 shift;
+ void __iomem *reg;
+ struct clk_ti_autoidle *clk;
+
+ if (of_property_read_u32(node, "ti,autoidle-shift", &shift))
+ return;
+
+ reg = of_iomap(node, 0);
+
+ clk = kzalloc(sizeof(*clk), GFP_KERNEL);
+
+ if (!clk) {
+ pr_err("%s: kzalloc failed\n", __func__);
+ return;
+ }
+
+ clk->shift = shift;
+ clk->name = node->name;
+ clk->reg = reg;
+
+ if (of_property_read_bool(node, "ti,autoidle-low"))
+ clk->flags |= AUTOIDLE_LOW;
+
+ list_add(&clk->node, &autoidle_clks);
+}
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index c89574e..6d552c1 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -180,6 +180,15 @@ int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
unsigned long parent_rate);
void ti_dt_clocks_register(struct ti_dt_clk *oclks);
+void of_ti_autoidle_setup(struct device_node *node);
+
+#ifdef CONFIG_OF
+void of_ti_clk_allow_autoidle_all(void);
+void of_ti_clk_deny_autoidle_all(void);
+#else
+static inline void of_ti_clk_allow_autoidle_all(void) { }
+static inline void of_ti_clk_deny_autoidle_all(void) { }
+#endif
extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
--
1.7.9.5
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 03/36] CLK: TI: add autoidle support
@ 2013-09-25 8:48 ` Tero Kristo
0 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-arm-kernel
TI clk driver now routes some of the basic clocks through own
registration routine to allow autoidle support. This routine just
checks a couple of device node properties and adds autoidle support
if required, and just passes the registration forward to basic clocks.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/mach-omap2/clock.c | 6 +++
drivers/clk/ti/Makefile | 2 +-
drivers/clk/ti/autoidle.c | 107 +++++++++++++++++++++++++++++++++++++++++++
include/linux/clk/ti.h | 9 ++++
4 files changed, 123 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/ti/autoidle.c
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 0c38ca9..223f432b 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -520,6 +520,9 @@ int omap2_clk_enable_autoidle_all(void)
list_for_each_entry(c, &clk_hw_omap_clocks, node)
if (c->ops && c->ops->allow_idle)
c->ops->allow_idle(c);
+
+ of_ti_clk_allow_autoidle_all();
+
return 0;
}
@@ -539,6 +542,9 @@ int omap2_clk_disable_autoidle_all(void)
list_for_each_entry(c, &clk_hw_omap_clocks, node)
if (c->ops && c->ops->deny_idle)
c->ops->deny_idle(c);
+
+ of_ti_clk_deny_autoidle_all();
+
return 0;
}
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 05af5d8..533efb4 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,3 +1,3 @@
ifneq ($(CONFIG_OF),)
-obj-y += clk.o dpll.o
+obj-y += clk.o dpll.o autoidle.o
endif
diff --git a/drivers/clk/ti/autoidle.c b/drivers/clk/ti/autoidle.c
new file mode 100644
index 0000000..ccac33c
--- /dev/null
+++ b/drivers/clk/ti/autoidle.c
@@ -0,0 +1,107 @@
+/*
+ * TI clock autoidle support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo <t-kristo@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk/ti.h>
+
+struct clk_ti_autoidle {
+ void __iomem *reg;
+ u8 shift;
+ u8 flags;
+ const char *name;
+ struct list_head node;
+};
+
+#define AUTOIDLE_LOW 0x1
+
+static LIST_HEAD(autoidle_clks);
+
+static void ti_allow_autoidle(struct clk_ti_autoidle *clk)
+{
+ u32 val;
+
+ val = readl(clk->reg);
+
+ if (clk->flags & AUTOIDLE_LOW)
+ val &= ~(1 << clk->shift);
+ else
+ val |= (1 << clk->shift);
+
+ writel(val, clk->reg);
+}
+
+static void ti_deny_autoidle(struct clk_ti_autoidle *clk)
+{
+ u32 val;
+
+ val = readl(clk->reg);
+
+ if (clk->flags & AUTOIDLE_LOW)
+ val |= (1 << clk->shift);
+ else
+ val &= ~(1 << clk->shift);
+
+ writel(val, clk->reg);
+}
+
+void of_ti_clk_allow_autoidle_all(void)
+{
+ struct clk_ti_autoidle *c;
+
+ list_for_each_entry(c, &autoidle_clks, node)
+ ti_allow_autoidle(c);
+}
+
+void of_ti_clk_deny_autoidle_all(void)
+{
+ struct clk_ti_autoidle *c;
+
+ list_for_each_entry(c, &autoidle_clks, node)
+ ti_deny_autoidle(c);
+}
+
+void __init of_ti_autoidle_setup(struct device_node *node)
+{
+ u32 shift;
+ void __iomem *reg;
+ struct clk_ti_autoidle *clk;
+
+ if (of_property_read_u32(node, "ti,autoidle-shift", &shift))
+ return;
+
+ reg = of_iomap(node, 0);
+
+ clk = kzalloc(sizeof(*clk), GFP_KERNEL);
+
+ if (!clk) {
+ pr_err("%s: kzalloc failed\n", __func__);
+ return;
+ }
+
+ clk->shift = shift;
+ clk->name = node->name;
+ clk->reg = reg;
+
+ if (of_property_read_bool(node, "ti,autoidle-low"))
+ clk->flags |= AUTOIDLE_LOW;
+
+ list_add(&clk->node, &autoidle_clks);
+}
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index c89574e..6d552c1 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -180,6 +180,15 @@ int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
unsigned long parent_rate);
void ti_dt_clocks_register(struct ti_dt_clk *oclks);
+void of_ti_autoidle_setup(struct device_node *node);
+
+#ifdef CONFIG_OF
+void of_ti_clk_allow_autoidle_all(void);
+void of_ti_clk_deny_autoidle_all(void);
+#else
+static inline void of_ti_clk_allow_autoidle_all(void) { }
+static inline void of_ti_clk_deny_autoidle_all(void) { }
+#endif
extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 04/36] CLK: ti: add support for ti divider-clock
2013-09-25 8:48 ` Tero Kristo
@ 2013-09-25 8:48 ` Tero Kristo
-1 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-omap, paul, tony, nm, rnayak, bcousson, mturquette
Cc: linux-arm-kernel, devicetree
This patch adds support for TI divider clock binding, which simply uses
the basic clock divider to provide the features needed.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
.../devicetree/bindings/clock/ti/divider.txt | 85 ++++++++++
drivers/clk/ti/Makefile | 2 +-
drivers/clk/ti/divider.c | 164 ++++++++++++++++++++
include/linux/clk/ti.h | 2 +
4 files changed, 252 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/clock/ti/divider.txt
create mode 100644 drivers/clk/ti/divider.c
diff --git a/Documentation/devicetree/bindings/clock/ti/divider.txt b/Documentation/devicetree/bindings/clock/ti/divider.txt
new file mode 100644
index 0000000..c5eb1f3
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/divider.txt
@@ -0,0 +1,85 @@
+Binding for TI divider clock
+
+This binding uses the common clock binding[1]. It assumes a
+register-mapped adjustable clock rate divider that does not gate and has
+only one input clock or parent. By default the value programmed into
+the register is one less than the actual divisor value. E.g:
+
+register value actual divisor value
+0 1
+1 2
+2 3
+
+This assumption may be modified by the following optional properties:
+
+ti,index-starts-at-one - valid divisor values start at 1, not the default
+of 0. E.g:
+register value actual divisor value
+1 1
+2 2
+3 3
+
+ti,index-power-of-two - valid divisor values are powers of two. E.g:
+register value actual divisor value
+0 1
+1 2
+2 4
+
+Additionally an array of valid dividers may be supplied like so:
+
+ dividers = <4>, <8>, <0>, <16>;
+
+Which will map the resulting values to a divisor table by their index:
+register value actual divisor value
+0 4
+1 8
+2 <invalid divisor, skipped>
+3 16
+
+Any zero value in this array means the corresponding bit-value is invalid
+and must not be used.
+
+The binding must also provide the register to control the divider and
+unless the divider array is provided, min and max dividers. Optionally
+the number of bits to shift that mask, if necessary. If the shift value
+is missing it is the same as supplying a zero shift.
+
+Required properties:
+- compatible : shall be "divider-clock".
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : link to phandle of parent clock
+- reg : base address for register controlling adjustable divider
+- ti,bit-mask : arbitrary bitmask for programming the adjustable divider
+
+Optional properties:
+- clock-output-names : from common clock binding.
+- ti,dividers : array of integers defining divisors
+- ti,bit-shift : number of bits to shift the divider value, defaults to 0
+- ti,min-div : min divisor for dividing the input clock rate, only
+ needed if the first divisor is offset from the default value (1)
+- ti,max-div : max divisor for dividing the input clock rate, only needed
+ if ti,dividers is not defined.
+- ti,index-starts-at-one : valid divisor programming starts at 1, not zero
+- ti,index-power-of-two : valid divisor programming must be a power of two
+- ti,autoidle-shift : bit shift of the autoidle enable bit for the clock
+- ti,autoidle-low : autoidle is enabled by setting the bit to 0
+- ti,set-rate-parent : clk_set_rate is propagated to parent
+
+Examples:
+dpll_usb_m2_ck: dpll_usb_m2_ck@4a008190 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_usb_ck>;
+ ti,max-div = <127>;
+ reg = <0x4a008190 0x4>;
+ ti,index-starts-at-one;
+};
+
+aess_fclk: aess_fclk@4a004528 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&abe_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a004528 0x4>;
+ ti,max-div = <2>;
+};
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 533efb4..72a410b 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,3 +1,3 @@
ifneq ($(CONFIG_OF),)
-obj-y += clk.o dpll.o autoidle.o
+obj-y += clk.o dpll.o autoidle.o divider.o
endif
diff --git a/drivers/clk/ti/divider.c b/drivers/clk/ti/divider.c
new file mode 100644
index 0000000..a97a5d6
--- /dev/null
+++ b/drivers/clk/ti/divider.c
@@ -0,0 +1,164 @@
+/*
+ * TI Divider Clock
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo <t-kristo@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk/ti.h>
+
+struct clk_div_table __init *ti_clk_get_div_table(struct device_node *node)
+{
+ struct clk_div_table *table;
+ const __be32 *divspec;
+ u32 val;
+ u32 num_div;
+ u32 valid_div;
+ int i;
+
+ divspec = of_get_property(node, "ti,dividers", &num_div);
+
+ if (!divspec)
+ return NULL;
+
+ valid_div = 0;
+
+ /* Determine required size for divider table */
+ for (i = 0; i < num_div; i++) {
+ of_property_read_u32_index(node, "ti,dividers", i, &val);
+ if (val)
+ valid_div++;
+ }
+
+ if (!valid_div) {
+ pr_err("%s: no valid dividers for %s table\n", __func__,
+ node->name);
+ return ERR_PTR(-EINVAL);
+ }
+
+ table = kzalloc(sizeof(*table) * (valid_div + 1), GFP_KERNEL);
+
+ if (!table) {
+ pr_err("%s: unable to allocate memory for %s table\n", __func__,
+ node->name);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ valid_div = 0;
+
+ for (i = 0; i < num_div; i++) {
+ of_property_read_u32_index(node, "dividers", i, &val);
+ if (val) {
+ table[valid_div].div = val;
+ table[valid_div].val = i;
+ valid_div++;
+ }
+ }
+
+ return table;
+}
+
+/**
+ * of_ti_divider_clk_setup() - Setup function for simple div rate clock
+ */
+static void __init of_ti_divider_clk_setup(struct device_node *node)
+{
+ struct clk *clk;
+ const char *clk_name = node->name;
+ void __iomem *reg;
+ const char *parent_name;
+ u8 clk_divider_flags = 0;
+ u32 width = 0;
+ u32 shift = 0;
+ struct clk_div_table *table;
+ int min_div, max_div, div;
+ u32 val = 0;
+ u32 flags = 0;
+
+ parent_name = of_clk_get_parent_name(node, 0);
+
+ reg = of_iomap(node, 0);
+ if (!reg) {
+ pr_err("%s: no memory mapped for property reg\n", __func__);
+ return;
+ }
+
+ of_property_read_u32(node, "ti,bit-shift", &shift);
+
+ if (of_property_read_bool(node, "ti,index-starts-at-one"))
+ clk_divider_flags |= CLK_DIVIDER_ONE_BASED;
+
+ if (of_property_read_bool(node, "ti,index-power-of-two"))
+ clk_divider_flags |= CLK_DIVIDER_POWER_OF_TWO;
+
+ if (of_property_read_bool(node, "ti,set-rate-parent"))
+ flags |= CLK_SET_RATE_PARENT;
+
+ table = ti_clk_get_div_table(node);
+
+ if (IS_ERR(table))
+ return;
+
+ if (!table) {
+ /* Clk divider table not provided, determine min/max divs */
+ if (of_property_read_u32(node, "ti,min-div", &min_div)) {
+ pr_debug("%s: ti,min-div not declared for %s, defaulting to 1\n", __func__,
+ node->name);
+ min_div = 1;
+ }
+
+ if (of_property_read_u32(node, "ti,max-div", &max_div)) {
+ pr_err("%s: ti,max-div not declared for %s\n", __func__,
+ node->name);
+ return;
+ }
+
+ /* Determine bit width for the field */
+ if (clk_divider_flags & CLK_DIVIDER_ONE_BASED)
+ val = 1;
+
+ div = min_div;
+
+ while (div < max_div) {
+ if (clk_divider_flags & CLK_DIVIDER_POWER_OF_TWO)
+ div <<= 1;
+ else
+ div++;
+ val++;
+ }
+ } else {
+ div = 0;
+
+ while (table[div].val) {
+ val = table[div].val;
+ div++;
+ }
+ }
+
+ width = fls(val);
+
+ clk = clk_register_divider_table(NULL, clk_name, parent_name, flags,
+ reg, shift, width, clk_divider_flags,
+ table, NULL);
+
+ if (!IS_ERR(clk)) {
+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
+ of_ti_autoidle_setup(node);
+ }
+}
+CLK_OF_DECLARE(divider_clk, "ti,divider-clock", of_ti_divider_clk_setup);
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 6d552c1..7f58f11 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -182,6 +182,8 @@ int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
void ti_dt_clocks_register(struct ti_dt_clk *oclks);
void of_ti_autoidle_setup(struct device_node *node);
+struct clk_div_table *ti_clk_get_div_table(struct device_node *node);
+
#ifdef CONFIG_OF
void of_ti_clk_allow_autoidle_all(void);
void of_ti_clk_deny_autoidle_all(void);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 04/36] CLK: ti: add support for ti divider-clock
@ 2013-09-25 8:48 ` Tero Kristo
0 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds support for TI divider clock binding, which simply uses
the basic clock divider to provide the features needed.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
.../devicetree/bindings/clock/ti/divider.txt | 85 ++++++++++
drivers/clk/ti/Makefile | 2 +-
drivers/clk/ti/divider.c | 164 ++++++++++++++++++++
include/linux/clk/ti.h | 2 +
4 files changed, 252 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/clock/ti/divider.txt
create mode 100644 drivers/clk/ti/divider.c
diff --git a/Documentation/devicetree/bindings/clock/ti/divider.txt b/Documentation/devicetree/bindings/clock/ti/divider.txt
new file mode 100644
index 0000000..c5eb1f3
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/divider.txt
@@ -0,0 +1,85 @@
+Binding for TI divider clock
+
+This binding uses the common clock binding[1]. It assumes a
+register-mapped adjustable clock rate divider that does not gate and has
+only one input clock or parent. By default the value programmed into
+the register is one less than the actual divisor value. E.g:
+
+register value actual divisor value
+0 1
+1 2
+2 3
+
+This assumption may be modified by the following optional properties:
+
+ti,index-starts-at-one - valid divisor values start at 1, not the default
+of 0. E.g:
+register value actual divisor value
+1 1
+2 2
+3 3
+
+ti,index-power-of-two - valid divisor values are powers of two. E.g:
+register value actual divisor value
+0 1
+1 2
+2 4
+
+Additionally an array of valid dividers may be supplied like so:
+
+ dividers = <4>, <8>, <0>, <16>;
+
+Which will map the resulting values to a divisor table by their index:
+register value actual divisor value
+0 4
+1 8
+2 <invalid divisor, skipped>
+3 16
+
+Any zero value in this array means the corresponding bit-value is invalid
+and must not be used.
+
+The binding must also provide the register to control the divider and
+unless the divider array is provided, min and max dividers. Optionally
+the number of bits to shift that mask, if necessary. If the shift value
+is missing it is the same as supplying a zero shift.
+
+Required properties:
+- compatible : shall be "divider-clock".
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : link to phandle of parent clock
+- reg : base address for register controlling adjustable divider
+- ti,bit-mask : arbitrary bitmask for programming the adjustable divider
+
+Optional properties:
+- clock-output-names : from common clock binding.
+- ti,dividers : array of integers defining divisors
+- ti,bit-shift : number of bits to shift the divider value, defaults to 0
+- ti,min-div : min divisor for dividing the input clock rate, only
+ needed if the first divisor is offset from the default value (1)
+- ti,max-div : max divisor for dividing the input clock rate, only needed
+ if ti,dividers is not defined.
+- ti,index-starts-at-one : valid divisor programming starts at 1, not zero
+- ti,index-power-of-two : valid divisor programming must be a power of two
+- ti,autoidle-shift : bit shift of the autoidle enable bit for the clock
+- ti,autoidle-low : autoidle is enabled by setting the bit to 0
+- ti,set-rate-parent : clk_set_rate is propagated to parent
+
+Examples:
+dpll_usb_m2_ck: dpll_usb_m2_ck at 4a008190 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_usb_ck>;
+ ti,max-div = <127>;
+ reg = <0x4a008190 0x4>;
+ ti,index-starts-at-one;
+};
+
+aess_fclk: aess_fclk at 4a004528 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&abe_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a004528 0x4>;
+ ti,max-div = <2>;
+};
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 533efb4..72a410b 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,3 +1,3 @@
ifneq ($(CONFIG_OF),)
-obj-y += clk.o dpll.o autoidle.o
+obj-y += clk.o dpll.o autoidle.o divider.o
endif
diff --git a/drivers/clk/ti/divider.c b/drivers/clk/ti/divider.c
new file mode 100644
index 0000000..a97a5d6
--- /dev/null
+++ b/drivers/clk/ti/divider.c
@@ -0,0 +1,164 @@
+/*
+ * TI Divider Clock
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo <t-kristo@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk/ti.h>
+
+struct clk_div_table __init *ti_clk_get_div_table(struct device_node *node)
+{
+ struct clk_div_table *table;
+ const __be32 *divspec;
+ u32 val;
+ u32 num_div;
+ u32 valid_div;
+ int i;
+
+ divspec = of_get_property(node, "ti,dividers", &num_div);
+
+ if (!divspec)
+ return NULL;
+
+ valid_div = 0;
+
+ /* Determine required size for divider table */
+ for (i = 0; i < num_div; i++) {
+ of_property_read_u32_index(node, "ti,dividers", i, &val);
+ if (val)
+ valid_div++;
+ }
+
+ if (!valid_div) {
+ pr_err("%s: no valid dividers for %s table\n", __func__,
+ node->name);
+ return ERR_PTR(-EINVAL);
+ }
+
+ table = kzalloc(sizeof(*table) * (valid_div + 1), GFP_KERNEL);
+
+ if (!table) {
+ pr_err("%s: unable to allocate memory for %s table\n", __func__,
+ node->name);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ valid_div = 0;
+
+ for (i = 0; i < num_div; i++) {
+ of_property_read_u32_index(node, "dividers", i, &val);
+ if (val) {
+ table[valid_div].div = val;
+ table[valid_div].val = i;
+ valid_div++;
+ }
+ }
+
+ return table;
+}
+
+/**
+ * of_ti_divider_clk_setup() - Setup function for simple div rate clock
+ */
+static void __init of_ti_divider_clk_setup(struct device_node *node)
+{
+ struct clk *clk;
+ const char *clk_name = node->name;
+ void __iomem *reg;
+ const char *parent_name;
+ u8 clk_divider_flags = 0;
+ u32 width = 0;
+ u32 shift = 0;
+ struct clk_div_table *table;
+ int min_div, max_div, div;
+ u32 val = 0;
+ u32 flags = 0;
+
+ parent_name = of_clk_get_parent_name(node, 0);
+
+ reg = of_iomap(node, 0);
+ if (!reg) {
+ pr_err("%s: no memory mapped for property reg\n", __func__);
+ return;
+ }
+
+ of_property_read_u32(node, "ti,bit-shift", &shift);
+
+ if (of_property_read_bool(node, "ti,index-starts-at-one"))
+ clk_divider_flags |= CLK_DIVIDER_ONE_BASED;
+
+ if (of_property_read_bool(node, "ti,index-power-of-two"))
+ clk_divider_flags |= CLK_DIVIDER_POWER_OF_TWO;
+
+ if (of_property_read_bool(node, "ti,set-rate-parent"))
+ flags |= CLK_SET_RATE_PARENT;
+
+ table = ti_clk_get_div_table(node);
+
+ if (IS_ERR(table))
+ return;
+
+ if (!table) {
+ /* Clk divider table not provided, determine min/max divs */
+ if (of_property_read_u32(node, "ti,min-div", &min_div)) {
+ pr_debug("%s: ti,min-div not declared for %s, defaulting to 1\n", __func__,
+ node->name);
+ min_div = 1;
+ }
+
+ if (of_property_read_u32(node, "ti,max-div", &max_div)) {
+ pr_err("%s: ti,max-div not declared for %s\n", __func__,
+ node->name);
+ return;
+ }
+
+ /* Determine bit width for the field */
+ if (clk_divider_flags & CLK_DIVIDER_ONE_BASED)
+ val = 1;
+
+ div = min_div;
+
+ while (div < max_div) {
+ if (clk_divider_flags & CLK_DIVIDER_POWER_OF_TWO)
+ div <<= 1;
+ else
+ div++;
+ val++;
+ }
+ } else {
+ div = 0;
+
+ while (table[div].val) {
+ val = table[div].val;
+ div++;
+ }
+ }
+
+ width = fls(val);
+
+ clk = clk_register_divider_table(NULL, clk_name, parent_name, flags,
+ reg, shift, width, clk_divider_flags,
+ table, NULL);
+
+ if (!IS_ERR(clk)) {
+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
+ of_ti_autoidle_setup(node);
+ }
+}
+CLK_OF_DECLARE(divider_clk, "ti,divider-clock", of_ti_divider_clk_setup);
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 6d552c1..7f58f11 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -182,6 +182,8 @@ int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
void ti_dt_clocks_register(struct ti_dt_clk *oclks);
void of_ti_autoidle_setup(struct device_node *node);
+struct clk_div_table *ti_clk_get_div_table(struct device_node *node);
+
#ifdef CONFIG_OF
void of_ti_clk_allow_autoidle_all(void);
void of_ti_clk_deny_autoidle_all(void);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 05/36] clk: ti: add support for TI fixed factor clock
2013-09-25 8:48 ` Tero Kristo
@ 2013-09-25 8:48 ` Tero Kristo
-1 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-omap-u79uwXL29TY76Z2rM5mHXA, paul-DWxLp4Yu+b8AvxtiuMwx3w,
tony-4v6yS6AI5VpBDgjK7y7TUQ, nm-l0cyMroinI0, rnayak-l0cyMroinI0,
bcousson-rdvid1DuHRBWk0Htik3J/w,
mturquette-QSEj5FYQhm4dnm+yROfE0A
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
This behaves exactly in similar manner to basic fixed-factor-clock, but
adds a few properties on top for handling clock hardware autoidling.
Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
.../bindings/clock/ti/fixed-factor-clock.txt | 27 +++++++++
drivers/clk/ti/Makefile | 3 +-
drivers/clk/ti/fixed-factor.c | 62 ++++++++++++++++++++
3 files changed, 91 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/clock/ti/fixed-factor-clock.txt
create mode 100644 drivers/clk/ti/fixed-factor.c
diff --git a/Documentation/devicetree/bindings/clock/ti/fixed-factor-clock.txt b/Documentation/devicetree/bindings/clock/ti/fixed-factor-clock.txt
new file mode 100644
index 0000000..e58762b
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/fixed-factor-clock.txt
@@ -0,0 +1,27 @@
+Binding for TI fixed factor rate clock sources.
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be "ti,fixed-factor-clock".
+- #clock-cells : from common clock binding; shall be set to 0.
+- ti,clock-div: fixed divider.
+- ti,clock-mult: fixed multiplier.
+- clocks: parent clock.
+
+Optional properties:
+- ti,autoidle-shift: bit shift of the autoidle enable bit for the clock
+- reg: base address for the autoidle register of this clock
+- ti,autoidle-low: autoidle is enabled by setting the bit to 0
+- ti,set-rate-parent: clk_set_rate is propagated to parent
+
+Example:
+ clock {
+ compatible = "ti,fixed-factor-clock";
+ clocks = <&parentclk>;
+ #clock-cells = <0>;
+ ti,clock-div = <2>;
+ ti,clock-mult = <1>;
+ };
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 72a410b..a9b986a 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,3 +1,4 @@
ifneq ($(CONFIG_OF),)
-obj-y += clk.o dpll.o autoidle.o divider.o
+obj-y += clk.o dpll.o autoidle.o divider.o \
+ fixed-factor.o
endif
diff --git a/drivers/clk/ti/fixed-factor.c b/drivers/clk/ti/fixed-factor.c
new file mode 100644
index 0000000..c3814ae
--- /dev/null
+++ b/drivers/clk/ti/fixed-factor.c
@@ -0,0 +1,62 @@
+/*
+ * TI Fixed Factor Clock
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk/ti.h>
+
+/**
+ * of_ti_fixed_factor_clk_setup() - Setup function for TI fixed factor clock
+ */
+static void __init of_ti_fixed_factor_clk_setup(struct device_node *node)
+{
+ struct clk *clk;
+ const char *clk_name = node->name;
+ const char *parent_name;
+ u32 div, mult;
+ u32 flags = 0;
+
+ if (of_property_read_u32(node, "ti,clock-div", &div)) {
+ pr_err("%s Fixed factor clock <%s> must have a clock-div property\n",
+ __func__, node->name);
+ return;
+ }
+
+ if (of_property_read_u32(node, "ti,clock-mult", &mult)) {
+ pr_err("%s Fixed factor clock <%s> must have a clokc-mult property\n",
+ __func__, node->name);
+ return;
+ }
+
+ if (of_property_read_bool(node, "ti,set-rate-parent"))
+ flags |= CLK_SET_RATE_PARENT;
+
+ parent_name = of_clk_get_parent_name(node, 0);
+
+ clk = clk_register_fixed_factor(NULL, clk_name, parent_name, flags,
+ mult, div);
+
+ if (!IS_ERR(clk)) {
+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
+ of_ti_autoidle_setup(node);
+ }
+}
+CLK_OF_DECLARE(ti_fixed_factor_clk, "ti,fixed-factor-clock",
+ of_ti_fixed_factor_clk_setup);
--
1.7.9.5
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 05/36] clk: ti: add support for TI fixed factor clock
@ 2013-09-25 8:48 ` Tero Kristo
0 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-arm-kernel
This behaves exactly in similar manner to basic fixed-factor-clock, but
adds a few properties on top for handling clock hardware autoidling.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
.../bindings/clock/ti/fixed-factor-clock.txt | 27 +++++++++
drivers/clk/ti/Makefile | 3 +-
drivers/clk/ti/fixed-factor.c | 62 ++++++++++++++++++++
3 files changed, 91 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/clock/ti/fixed-factor-clock.txt
create mode 100644 drivers/clk/ti/fixed-factor.c
diff --git a/Documentation/devicetree/bindings/clock/ti/fixed-factor-clock.txt b/Documentation/devicetree/bindings/clock/ti/fixed-factor-clock.txt
new file mode 100644
index 0000000..e58762b
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/fixed-factor-clock.txt
@@ -0,0 +1,27 @@
+Binding for TI fixed factor rate clock sources.
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be "ti,fixed-factor-clock".
+- #clock-cells : from common clock binding; shall be set to 0.
+- ti,clock-div: fixed divider.
+- ti,clock-mult: fixed multiplier.
+- clocks: parent clock.
+
+Optional properties:
+- ti,autoidle-shift: bit shift of the autoidle enable bit for the clock
+- reg: base address for the autoidle register of this clock
+- ti,autoidle-low: autoidle is enabled by setting the bit to 0
+- ti,set-rate-parent: clk_set_rate is propagated to parent
+
+Example:
+ clock {
+ compatible = "ti,fixed-factor-clock";
+ clocks = <&parentclk>;
+ #clock-cells = <0>;
+ ti,clock-div = <2>;
+ ti,clock-mult = <1>;
+ };
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 72a410b..a9b986a 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,3 +1,4 @@
ifneq ($(CONFIG_OF),)
-obj-y += clk.o dpll.o autoidle.o divider.o
+obj-y += clk.o dpll.o autoidle.o divider.o \
+ fixed-factor.o
endif
diff --git a/drivers/clk/ti/fixed-factor.c b/drivers/clk/ti/fixed-factor.c
new file mode 100644
index 0000000..c3814ae
--- /dev/null
+++ b/drivers/clk/ti/fixed-factor.c
@@ -0,0 +1,62 @@
+/*
+ * TI Fixed Factor Clock
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo <t-kristo@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk/ti.h>
+
+/**
+ * of_ti_fixed_factor_clk_setup() - Setup function for TI fixed factor clock
+ */
+static void __init of_ti_fixed_factor_clk_setup(struct device_node *node)
+{
+ struct clk *clk;
+ const char *clk_name = node->name;
+ const char *parent_name;
+ u32 div, mult;
+ u32 flags = 0;
+
+ if (of_property_read_u32(node, "ti,clock-div", &div)) {
+ pr_err("%s Fixed factor clock <%s> must have a clock-div property\n",
+ __func__, node->name);
+ return;
+ }
+
+ if (of_property_read_u32(node, "ti,clock-mult", &mult)) {
+ pr_err("%s Fixed factor clock <%s> must have a clokc-mult property\n",
+ __func__, node->name);
+ return;
+ }
+
+ if (of_property_read_bool(node, "ti,set-rate-parent"))
+ flags |= CLK_SET_RATE_PARENT;
+
+ parent_name = of_clk_get_parent_name(node, 0);
+
+ clk = clk_register_fixed_factor(NULL, clk_name, parent_name, flags,
+ mult, div);
+
+ if (!IS_ERR(clk)) {
+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
+ of_ti_autoidle_setup(node);
+ }
+}
+CLK_OF_DECLARE(ti_fixed_factor_clk, "ti,fixed-factor-clock",
+ of_ti_fixed_factor_clk_setup);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 06/36] CLK: TI: add support for OMAP gate clock
2013-09-25 8:48 ` Tero Kristo
@ 2013-09-25 8:48 ` Tero Kristo
-1 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-omap-u79uwXL29TY76Z2rM5mHXA, paul-DWxLp4Yu+b8AvxtiuMwx3w,
tony-4v6yS6AI5VpBDgjK7y7TUQ, nm-l0cyMroinI0, rnayak-l0cyMroinI0,
bcousson-rdvid1DuHRBWk0Htik3J/w,
mturquette-QSEj5FYQhm4dnm+yROfE0A
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
This patch adds support for TI specific gate clocks. These behave as basic
gate-clock, but have different ops / hw-ops for controlling the actual
gate, for example waiting until the clock is ready. Several sub-types
are supported:
- ti,gate-clock: basic gate clock with default ops/hwops
- ti,clkdm-gate-clock: clockdomain level gate control
- ti,dss-gate-clock: gate clock with DSS specific hardware handling
- ti,am35xx-gate-clock: gate clock with AM35xx specific hardware handling
- ti,hsdiv-gate-clock: gate clock with OMAP36xx hardware errata handling
Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
.../devicetree/bindings/clock/ti/gate.txt | 75 ++++++++
arch/arm/mach-omap2/clock.h | 28 ---
drivers/clk/ti/Makefile | 2 +-
drivers/clk/ti/gate.c | 184 ++++++++++++++++++++
include/linux/clk/ti.h | 35 ++++
5 files changed, 295 insertions(+), 29 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/ti/gate.txt
create mode 100644 drivers/clk/ti/gate.c
diff --git a/Documentation/devicetree/bindings/clock/ti/gate.txt b/Documentation/devicetree/bindings/clock/ti/gate.txt
new file mode 100644
index 0000000..cf17534
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/gate.txt
@@ -0,0 +1,75 @@
+Binding for Texas Instruments gate clock.
+
+This binding uses the common clock binding[1]. This clock is
+quite much similar to the basic gate-clock [2], however,
+it supports a number of additional features. If no register
+is provided for this clock, the code assumes that a clockdomain
+will be controlled instead and the corresponding hw-ops for
+that is used.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/clock/gate-clock.txt
+[3] Documentation/devicetree/bindings/clock/ti/clockdomain.txt
+
+Required properties:
+- compatible : shall be one of:
+ "ti,gate-clock" - basic gate clock
+ "ti,wait-gate-clock" - gate clock which waits until clock is active before
+ returning from clk_enable()
+ "ti,dss-gate-clock" - gate clock with DSS specific hardware handling
+ "ti,am35xx-gate-clock" - gate clock with AM35xx specific hardware handling
+ "ti,clkdm-gate-clock" - clockdomain gate clock, which derives its functional
+ clock directly from a clockdomain, see [3] how
+ to map clockdomains properly
+ "ti,hsdiv-gate-clock" - gate clock with OMAP36xx specific hardware handling,
+ required for a hardware errata
+- #clock-cells : from common clock binding; shall be set to 0
+- clocks : link to phandle of parent clock
+- reg : base address for register controlling adjustable gate, not needed for
+ ti,clkdm-gate-clock type
+- ti,bit-shift : bit shift for programming the clock gate, not needed for
+ ti,clkdm-gate-clock type
+
+Optional properties:
+- ti,set-bit-to-disable : inverts default gate programming. Setting the bit
+ gates the clock and clearing the bit ungates the clock.
+
+Examples:
+ mmchs2_fck: mmchs2_fck@48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&core_96m_fck>;
+ reg = <0x48004a00 0x4>;
+ ti,bit-shift = <25>;
+ };
+
+ dss1_alwon_fck_3430es2: dss1_alwon_fck_3430es2@48004e00 {
+ #clock-cells = <0>;
+ compatible = "ti,dss-gate-clock";
+ clocks = <&dpll4_m4x2_ck>;
+ reg = <0x48004e00 0x4>;
+ ti,bit-shift = <0>;
+ };
+
+ emac_ick: emac_ick@4800259c {
+ #clock-cells = <0>;
+ compatible = "ti,am35xx-gate-clock";
+ clocks = <&ipss_ick>;
+ reg = <0x4800259c 0x4>;
+ ti,bit-shift = <1>;
+ };
+
+ emu_src_ck: emu_src_ck {
+ #clock-cells = <0>;
+ compatible = "ti,clkdm-gate-clock";
+ clocks = <&emu_src_mux_ck>;
+ };
+
+ dpll4_m2x2_ck: dpll4_m2x2_ck@48004d00 {
+ #clock-cells = <0>;
+ compatible = "ti,hsdiv-gate-clock";
+ clocks = <&dpll4_m2x2_mul_ck>;
+ ti,bit-shift = <0x1b>;
+ reg = <0x48004d00 0x4>;
+ ti,set-bit-to-disable;
+ };
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 079536a..f0b7218 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -179,25 +179,6 @@ struct clksel {
const struct clksel_rate *rates;
};
-/*
- * struct clk.flags possibilities
- *
- * XXX document the rest of the clock flags here
- *
- * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
- * bits share the same register. This flag allows the
- * omap4_dpllmx*() code to determine which GATE_CTRL bit field
- * should be used. This is a temporary solution - a better approach
- * would be to associate clock type-specific data with the clock,
- * similar to the struct dpll_data approach.
- */
-#define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */
-#define CLOCK_IDLE_CONTROL (1 << 1)
-#define CLOCK_NO_IDLE_PARENT (1 << 2)
-#define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */
-#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */
-#define CLOCK_CLKOUTX2 (1 << 5)
-
struct clk_hw_omap_ops {
void (*find_idlest)(struct clk_hw_omap *oclk,
void __iomem **idlest_reg,
@@ -260,9 +241,6 @@ extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);
unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
-int omap2_dflt_clk_enable(struct clk_hw *hw);
-void omap2_dflt_clk_disable(struct clk_hw *hw);
-int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
void __iomem **other_reg,
u8 *other_bit);
@@ -292,15 +270,12 @@ extern const struct clksel_rate dsp_ick_rates[];
extern struct clk dummy_ck;
extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
-extern const struct clk_hw_omap_ops clkhwops_wait;
extern const struct clk_hw_omap_ops clkhwops_iclk;
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait;
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
-extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait;
-extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait;
extern const struct clk_hw_omap_ops clkhwops_apll54;
extern const struct clk_hw_omap_ops clkhwops_apll96;
@@ -318,8 +293,5 @@ extern const struct clksel_rate div31_1to31_rates[];
extern int am33xx_clk_init(void);
-extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);
-extern void omap2_clkops_disable_clkdm(struct clk_hw *hw);
-
extern void omap_clocks_register(struct omap_clk *oclks, int cnt);
#endif
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index a9b986a..63b1c45 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,4 +1,4 @@
ifneq ($(CONFIG_OF),)
obj-y += clk.o dpll.o autoidle.o divider.o \
- fixed-factor.o
+ fixed-factor.o gate.o
endif
diff --git a/drivers/clk/ti/gate.c b/drivers/clk/ti/gate.c
new file mode 100644
index 0000000..cc2a272
--- /dev/null
+++ b/drivers/clk/ti/gate.c
@@ -0,0 +1,184 @@
+/*
+ * OMAP gate clock support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk/ti.h>
+
+#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
+
+static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *clk);
+
+static const struct clk_ops omap_gate_clkdm_clk_ops = {
+ .init = &omap2_init_clk_clkdm,
+ .enable = &omap2_clkops_enable_clkdm,
+ .disable = &omap2_clkops_disable_clkdm,
+};
+
+static const struct clk_ops omap_gate_clk_ops = {
+ .init = &omap2_init_clk_clkdm,
+ .enable = &omap2_dflt_clk_enable,
+ .disable = &omap2_dflt_clk_disable,
+ .is_enabled = &omap2_dflt_clk_is_enabled,
+};
+
+static const struct clk_ops omap_gate_clk_hsdiv_restore_ops = {
+ .init = &omap2_init_clk_clkdm,
+ .enable = &omap36xx_gate_clk_enable_with_hsdiv_restore,
+ .disable = &omap2_dflt_clk_disable,
+ .is_enabled = &omap2_dflt_clk_is_enabled,
+};
+
+/**
+ * omap36xx_gate_clk_enable_with_hsdiv_restore - enable clocks suffering
+ * from HSDivider PWRDN problem Implements Errata ID: i556.
+ * @clk: DPLL output struct clk
+ *
+ * 3630 only: dpll3_m3_ck, dpll4_m2_ck, dpll4_m3_ck, dpll4_m4_ck,
+ * dpll4_m5_ck & dpll4_m6_ck dividers gets loaded with reset
+ * valueafter their respective PWRDN bits are set. Any dummy write
+ * (Any other value different from the Read value) to the
+ * corresponding CM_CLKSEL register will refresh the dividers.
+ */
+static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *clk)
+{
+ struct clk_divider *parent;
+ struct clk_hw *parent_hw;
+ u32 dummy_v, orig_v;
+ int ret;
+
+ /* Clear PWRDN bit of HSDIVIDER */
+ ret = omap2_dflt_clk_enable(clk);
+
+ /* Parent is the x2 node, get parent of parent for the m2 div */
+ parent_hw = __clk_get_hw(__clk_get_parent(__clk_get_parent(clk->clk)));
+ parent = to_clk_divider(parent_hw);
+
+ /* Restore the dividers */
+ if (!ret) {
+ orig_v = __raw_readl(parent->reg);
+ dummy_v = orig_v;
+
+ /* Write any other value different from the Read value */
+ dummy_v ^= (1 << parent->shift);
+ __raw_writel(dummy_v, parent->reg);
+
+ /* Write the original divider */
+ __raw_writel(orig_v, parent->reg);
+ }
+
+ return ret;
+}
+
+static void __init _of_ti_gate_clk_setup(struct device_node *node,
+ void __iomem *reg,
+ const struct clk_ops *ops,
+ const struct clk_hw_omap_ops *hw_ops)
+{
+ struct clk *clk;
+ struct clk_init_data init = { NULL };
+ struct clk_hw_omap *clk_hw;
+ const char *clk_name = node->name;
+ const char *parent_name;
+ u32 val;
+
+ clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
+ if (!clk_hw) {
+ pr_err("%s: could not allocate clk_hw_omap\n", __func__);
+ return;
+ }
+
+ clk_hw->hw.init = &init;
+
+ of_property_read_string(node, "clock-output-names", &clk_name);
+
+ init.name = clk_name;
+ init.ops = ops;
+ clk_hw->enable_reg = reg;
+ if (!of_property_read_u32(node, "ti,bit-shift", &val))
+ clk_hw->enable_bit = val;
+ clk_hw->ops = hw_ops;
+
+ parent_name = of_clk_get_parent_name(node, 0);
+ init.parent_names = &parent_name;
+ init.num_parents = 1;
+
+ if (of_property_read_bool(node, "ti,set-rate-parent"))
+ init.flags |= CLK_SET_RATE_PARENT;
+
+ if (of_property_read_bool(node, "ti,set-bit-to-disable"))
+ clk_hw->flags |= INVERT_ENABLE;
+
+ clk = clk_register(NULL, &clk_hw->hw);
+
+ if (!IS_ERR(clk))
+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
+}
+
+static void __init of_ti_clkdm_gate_clk_setup(struct device_node *node)
+{
+ _of_ti_gate_clk_setup(node, NULL, &omap_gate_clkdm_clk_ops, NULL);
+}
+CLK_OF_DECLARE(ti_clkdm_gate_clk, "ti,clkdm-gate-clock",
+ of_ti_clkdm_gate_clk_setup);
+
+static void __init of_ti_hsdiv_gate_clk_setup(struct device_node *node)
+{
+ void __iomem *reg = of_iomap(node, 0);
+ _of_ti_gate_clk_setup(node, reg, &omap_gate_clk_hsdiv_restore_ops,
+ &clkhwops_wait);
+}
+CLK_OF_DECLARE(ti_hsdiv_gate_clk, "ti,hsdiv-gate-clock",
+ of_ti_hsdiv_gate_clk_setup);
+
+static void __init of_ti_gate_clk_setup(struct device_node *node)
+{
+ void __iomem *reg = of_iomap(node, 0);
+ _of_ti_gate_clk_setup(node, reg, &omap_gate_clk_ops, NULL);
+}
+CLK_OF_DECLARE(ti_gate_clk, "ti,gate-clock", of_ti_gate_clk_setup)
+
+static void __init of_ti_wait_gate_clk_setup(struct device_node *node)
+{
+ void __iomem *reg = of_iomap(node, 0);
+ _of_ti_gate_clk_setup(node, reg, &omap_gate_clk_ops, &clkhwops_wait);
+}
+CLK_OF_DECLARE(ti_wait_gate_clk, "ti,wait-gate-clock",
+ of_ti_wait_gate_clk_setup);
+
+#ifdef CONFIG_ARCH_OMAP3
+static void __init of_ti_am35xx_gate_clk_setup(struct device_node *node)
+{
+ void __iomem *reg = of_iomap(node, 0);
+ _of_ti_gate_clk_setup(node, reg, &omap_gate_clk_ops,
+ &clkhwops_am35xx_ipss_module_wait);
+}
+CLK_OF_DECLARE(ti_am35xx_gate_clk, "ti,am35xx-gate-clock",
+ of_ti_am35xx_gate_clk_setup);
+
+static void __init of_ti_dss_gate_clk_setup(struct device_node *node)
+{
+ void __iomem *reg = of_iomap(node, 0);
+ _of_ti_gate_clk_setup(node, reg, &omap_gate_clk_ops,
+ &clkhwops_omap3430es2_dss_usbhost_wait);
+}
+CLK_OF_DECLARE(ti_dss_gate_clk, "ti,dss-gate-clock",
+ of_ti_dss_gate_clk_setup);
+#endif
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 7f58f11..e0a2d32 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -132,6 +132,33 @@ struct clk_hw_omap {
const struct clk_hw_omap_ops *ops;
};
+/*
+ * struct clk_hw_omap.flags possibilities
+ *
+ * XXX document the rest of the clock flags here
+ *
+ * ENABLE_REG_32BIT: (OMAP1 only) clock control register must be accessed
+ * with 32bit ops, by default OMAP1 uses 16bit ops.
+ * CLOCK_IDLE_CONTROL: (OMAP1 only) clock has autoidle support.
+ * CLOCK_NO_IDLE_PARENT: (OMAP1 only) when clock is enabled, its parent
+ * clock is put to no-idle mode.
+ * ENABLE_ON_INIT: Clock is enabled on init.
+ * INVERT_ENABLE: By default, clock enable bit behavior is '1' enable, '0'
+ * disable. This inverts the behavior making '0' enable and '1' disable.
+ * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
+ * bits share the same register. This flag allows the
+ * omap4_dpllmx*() code to determine which GATE_CTRL bit field
+ * should be used. This is a temporary solution - a better approach
+ * would be to associate clock type-specific data with the clock,
+ * similar to the struct dpll_data approach.
+ */
+#define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */
+#define CLOCK_IDLE_CONTROL (1 << 1)
+#define CLOCK_NO_IDLE_PARENT (1 << 2)
+#define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */
+#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */
+#define CLOCK_CLKOUTX2 (1 << 5)
+
/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
#define DPLL_LOW_POWER_STOP 0x1
#define DPLL_LOW_POWER_BYPASS 0x5
@@ -176,8 +203,13 @@ long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
void omap2_init_clk_clkdm(struct clk_hw *clk);
unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
unsigned long parent_rate);
+int omap2_clkops_enable_clkdm(struct clk_hw *hw);
+void omap2_clkops_disable_clkdm(struct clk_hw *hw);
int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
unsigned long parent_rate);
+int omap2_dflt_clk_enable(struct clk_hw *hw);
+void omap2_dflt_clk_disable(struct clk_hw *hw);
+int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
void ti_dt_clocks_register(struct ti_dt_clk *oclks);
void of_ti_autoidle_setup(struct device_node *node);
@@ -194,5 +226,8 @@ static inline void of_ti_clk_deny_autoidle_all(void) { }
extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
+extern const struct clk_hw_omap_ops clkhwops_wait;
+extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
+extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
#endif
--
1.7.9.5
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^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 06/36] CLK: TI: add support for OMAP gate clock
@ 2013-09-25 8:48 ` Tero Kristo
0 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds support for TI specific gate clocks. These behave as basic
gate-clock, but have different ops / hw-ops for controlling the actual
gate, for example waiting until the clock is ready. Several sub-types
are supported:
- ti,gate-clock: basic gate clock with default ops/hwops
- ti,clkdm-gate-clock: clockdomain level gate control
- ti,dss-gate-clock: gate clock with DSS specific hardware handling
- ti,am35xx-gate-clock: gate clock with AM35xx specific hardware handling
- ti,hsdiv-gate-clock: gate clock with OMAP36xx hardware errata handling
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
.../devicetree/bindings/clock/ti/gate.txt | 75 ++++++++
arch/arm/mach-omap2/clock.h | 28 ---
drivers/clk/ti/Makefile | 2 +-
drivers/clk/ti/gate.c | 184 ++++++++++++++++++++
include/linux/clk/ti.h | 35 ++++
5 files changed, 295 insertions(+), 29 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/ti/gate.txt
create mode 100644 drivers/clk/ti/gate.c
diff --git a/Documentation/devicetree/bindings/clock/ti/gate.txt b/Documentation/devicetree/bindings/clock/ti/gate.txt
new file mode 100644
index 0000000..cf17534
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/gate.txt
@@ -0,0 +1,75 @@
+Binding for Texas Instruments gate clock.
+
+This binding uses the common clock binding[1]. This clock is
+quite much similar to the basic gate-clock [2], however,
+it supports a number of additional features. If no register
+is provided for this clock, the code assumes that a clockdomain
+will be controlled instead and the corresponding hw-ops for
+that is used.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/clock/gate-clock.txt
+[3] Documentation/devicetree/bindings/clock/ti/clockdomain.txt
+
+Required properties:
+- compatible : shall be one of:
+ "ti,gate-clock" - basic gate clock
+ "ti,wait-gate-clock" - gate clock which waits until clock is active before
+ returning from clk_enable()
+ "ti,dss-gate-clock" - gate clock with DSS specific hardware handling
+ "ti,am35xx-gate-clock" - gate clock with AM35xx specific hardware handling
+ "ti,clkdm-gate-clock" - clockdomain gate clock, which derives its functional
+ clock directly from a clockdomain, see [3] how
+ to map clockdomains properly
+ "ti,hsdiv-gate-clock" - gate clock with OMAP36xx specific hardware handling,
+ required for a hardware errata
+- #clock-cells : from common clock binding; shall be set to 0
+- clocks : link to phandle of parent clock
+- reg : base address for register controlling adjustable gate, not needed for
+ ti,clkdm-gate-clock type
+- ti,bit-shift : bit shift for programming the clock gate, not needed for
+ ti,clkdm-gate-clock type
+
+Optional properties:
+- ti,set-bit-to-disable : inverts default gate programming. Setting the bit
+ gates the clock and clearing the bit ungates the clock.
+
+Examples:
+ mmchs2_fck: mmchs2_fck at 48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&core_96m_fck>;
+ reg = <0x48004a00 0x4>;
+ ti,bit-shift = <25>;
+ };
+
+ dss1_alwon_fck_3430es2: dss1_alwon_fck_3430es2 at 48004e00 {
+ #clock-cells = <0>;
+ compatible = "ti,dss-gate-clock";
+ clocks = <&dpll4_m4x2_ck>;
+ reg = <0x48004e00 0x4>;
+ ti,bit-shift = <0>;
+ };
+
+ emac_ick: emac_ick at 4800259c {
+ #clock-cells = <0>;
+ compatible = "ti,am35xx-gate-clock";
+ clocks = <&ipss_ick>;
+ reg = <0x4800259c 0x4>;
+ ti,bit-shift = <1>;
+ };
+
+ emu_src_ck: emu_src_ck {
+ #clock-cells = <0>;
+ compatible = "ti,clkdm-gate-clock";
+ clocks = <&emu_src_mux_ck>;
+ };
+
+ dpll4_m2x2_ck: dpll4_m2x2_ck at 48004d00 {
+ #clock-cells = <0>;
+ compatible = "ti,hsdiv-gate-clock";
+ clocks = <&dpll4_m2x2_mul_ck>;
+ ti,bit-shift = <0x1b>;
+ reg = <0x48004d00 0x4>;
+ ti,set-bit-to-disable;
+ };
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 079536a..f0b7218 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -179,25 +179,6 @@ struct clksel {
const struct clksel_rate *rates;
};
-/*
- * struct clk.flags possibilities
- *
- * XXX document the rest of the clock flags here
- *
- * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
- * bits share the same register. This flag allows the
- * omap4_dpllmx*() code to determine which GATE_CTRL bit field
- * should be used. This is a temporary solution - a better approach
- * would be to associate clock type-specific data with the clock,
- * similar to the struct dpll_data approach.
- */
-#define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */
-#define CLOCK_IDLE_CONTROL (1 << 1)
-#define CLOCK_NO_IDLE_PARENT (1 << 2)
-#define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */
-#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */
-#define CLOCK_CLKOUTX2 (1 << 5)
-
struct clk_hw_omap_ops {
void (*find_idlest)(struct clk_hw_omap *oclk,
void __iomem **idlest_reg,
@@ -260,9 +241,6 @@ extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);
unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
-int omap2_dflt_clk_enable(struct clk_hw *hw);
-void omap2_dflt_clk_disable(struct clk_hw *hw);
-int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
void __iomem **other_reg,
u8 *other_bit);
@@ -292,15 +270,12 @@ extern const struct clksel_rate dsp_ick_rates[];
extern struct clk dummy_ck;
extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
-extern const struct clk_hw_omap_ops clkhwops_wait;
extern const struct clk_hw_omap_ops clkhwops_iclk;
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait;
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
-extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait;
-extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait;
extern const struct clk_hw_omap_ops clkhwops_apll54;
extern const struct clk_hw_omap_ops clkhwops_apll96;
@@ -318,8 +293,5 @@ extern const struct clksel_rate div31_1to31_rates[];
extern int am33xx_clk_init(void);
-extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);
-extern void omap2_clkops_disable_clkdm(struct clk_hw *hw);
-
extern void omap_clocks_register(struct omap_clk *oclks, int cnt);
#endif
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index a9b986a..63b1c45 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,4 +1,4 @@
ifneq ($(CONFIG_OF),)
obj-y += clk.o dpll.o autoidle.o divider.o \
- fixed-factor.o
+ fixed-factor.o gate.o
endif
diff --git a/drivers/clk/ti/gate.c b/drivers/clk/ti/gate.c
new file mode 100644
index 0000000..cc2a272
--- /dev/null
+++ b/drivers/clk/ti/gate.c
@@ -0,0 +1,184 @@
+/*
+ * OMAP gate clock support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo <t-kristo@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk/ti.h>
+
+#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
+
+static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *clk);
+
+static const struct clk_ops omap_gate_clkdm_clk_ops = {
+ .init = &omap2_init_clk_clkdm,
+ .enable = &omap2_clkops_enable_clkdm,
+ .disable = &omap2_clkops_disable_clkdm,
+};
+
+static const struct clk_ops omap_gate_clk_ops = {
+ .init = &omap2_init_clk_clkdm,
+ .enable = &omap2_dflt_clk_enable,
+ .disable = &omap2_dflt_clk_disable,
+ .is_enabled = &omap2_dflt_clk_is_enabled,
+};
+
+static const struct clk_ops omap_gate_clk_hsdiv_restore_ops = {
+ .init = &omap2_init_clk_clkdm,
+ .enable = &omap36xx_gate_clk_enable_with_hsdiv_restore,
+ .disable = &omap2_dflt_clk_disable,
+ .is_enabled = &omap2_dflt_clk_is_enabled,
+};
+
+/**
+ * omap36xx_gate_clk_enable_with_hsdiv_restore - enable clocks suffering
+ * from HSDivider PWRDN problem Implements Errata ID: i556.
+ * @clk: DPLL output struct clk
+ *
+ * 3630 only: dpll3_m3_ck, dpll4_m2_ck, dpll4_m3_ck, dpll4_m4_ck,
+ * dpll4_m5_ck & dpll4_m6_ck dividers gets loaded with reset
+ * valueafter their respective PWRDN bits are set. Any dummy write
+ * (Any other value different from the Read value) to the
+ * corresponding CM_CLKSEL register will refresh the dividers.
+ */
+static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *clk)
+{
+ struct clk_divider *parent;
+ struct clk_hw *parent_hw;
+ u32 dummy_v, orig_v;
+ int ret;
+
+ /* Clear PWRDN bit of HSDIVIDER */
+ ret = omap2_dflt_clk_enable(clk);
+
+ /* Parent is the x2 node, get parent of parent for the m2 div */
+ parent_hw = __clk_get_hw(__clk_get_parent(__clk_get_parent(clk->clk)));
+ parent = to_clk_divider(parent_hw);
+
+ /* Restore the dividers */
+ if (!ret) {
+ orig_v = __raw_readl(parent->reg);
+ dummy_v = orig_v;
+
+ /* Write any other value different from the Read value */
+ dummy_v ^= (1 << parent->shift);
+ __raw_writel(dummy_v, parent->reg);
+
+ /* Write the original divider */
+ __raw_writel(orig_v, parent->reg);
+ }
+
+ return ret;
+}
+
+static void __init _of_ti_gate_clk_setup(struct device_node *node,
+ void __iomem *reg,
+ const struct clk_ops *ops,
+ const struct clk_hw_omap_ops *hw_ops)
+{
+ struct clk *clk;
+ struct clk_init_data init = { NULL };
+ struct clk_hw_omap *clk_hw;
+ const char *clk_name = node->name;
+ const char *parent_name;
+ u32 val;
+
+ clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
+ if (!clk_hw) {
+ pr_err("%s: could not allocate clk_hw_omap\n", __func__);
+ return;
+ }
+
+ clk_hw->hw.init = &init;
+
+ of_property_read_string(node, "clock-output-names", &clk_name);
+
+ init.name = clk_name;
+ init.ops = ops;
+ clk_hw->enable_reg = reg;
+ if (!of_property_read_u32(node, "ti,bit-shift", &val))
+ clk_hw->enable_bit = val;
+ clk_hw->ops = hw_ops;
+
+ parent_name = of_clk_get_parent_name(node, 0);
+ init.parent_names = &parent_name;
+ init.num_parents = 1;
+
+ if (of_property_read_bool(node, "ti,set-rate-parent"))
+ init.flags |= CLK_SET_RATE_PARENT;
+
+ if (of_property_read_bool(node, "ti,set-bit-to-disable"))
+ clk_hw->flags |= INVERT_ENABLE;
+
+ clk = clk_register(NULL, &clk_hw->hw);
+
+ if (!IS_ERR(clk))
+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
+}
+
+static void __init of_ti_clkdm_gate_clk_setup(struct device_node *node)
+{
+ _of_ti_gate_clk_setup(node, NULL, &omap_gate_clkdm_clk_ops, NULL);
+}
+CLK_OF_DECLARE(ti_clkdm_gate_clk, "ti,clkdm-gate-clock",
+ of_ti_clkdm_gate_clk_setup);
+
+static void __init of_ti_hsdiv_gate_clk_setup(struct device_node *node)
+{
+ void __iomem *reg = of_iomap(node, 0);
+ _of_ti_gate_clk_setup(node, reg, &omap_gate_clk_hsdiv_restore_ops,
+ &clkhwops_wait);
+}
+CLK_OF_DECLARE(ti_hsdiv_gate_clk, "ti,hsdiv-gate-clock",
+ of_ti_hsdiv_gate_clk_setup);
+
+static void __init of_ti_gate_clk_setup(struct device_node *node)
+{
+ void __iomem *reg = of_iomap(node, 0);
+ _of_ti_gate_clk_setup(node, reg, &omap_gate_clk_ops, NULL);
+}
+CLK_OF_DECLARE(ti_gate_clk, "ti,gate-clock", of_ti_gate_clk_setup)
+
+static void __init of_ti_wait_gate_clk_setup(struct device_node *node)
+{
+ void __iomem *reg = of_iomap(node, 0);
+ _of_ti_gate_clk_setup(node, reg, &omap_gate_clk_ops, &clkhwops_wait);
+}
+CLK_OF_DECLARE(ti_wait_gate_clk, "ti,wait-gate-clock",
+ of_ti_wait_gate_clk_setup);
+
+#ifdef CONFIG_ARCH_OMAP3
+static void __init of_ti_am35xx_gate_clk_setup(struct device_node *node)
+{
+ void __iomem *reg = of_iomap(node, 0);
+ _of_ti_gate_clk_setup(node, reg, &omap_gate_clk_ops,
+ &clkhwops_am35xx_ipss_module_wait);
+}
+CLK_OF_DECLARE(ti_am35xx_gate_clk, "ti,am35xx-gate-clock",
+ of_ti_am35xx_gate_clk_setup);
+
+static void __init of_ti_dss_gate_clk_setup(struct device_node *node)
+{
+ void __iomem *reg = of_iomap(node, 0);
+ _of_ti_gate_clk_setup(node, reg, &omap_gate_clk_ops,
+ &clkhwops_omap3430es2_dss_usbhost_wait);
+}
+CLK_OF_DECLARE(ti_dss_gate_clk, "ti,dss-gate-clock",
+ of_ti_dss_gate_clk_setup);
+#endif
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 7f58f11..e0a2d32 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -132,6 +132,33 @@ struct clk_hw_omap {
const struct clk_hw_omap_ops *ops;
};
+/*
+ * struct clk_hw_omap.flags possibilities
+ *
+ * XXX document the rest of the clock flags here
+ *
+ * ENABLE_REG_32BIT: (OMAP1 only) clock control register must be accessed
+ * with 32bit ops, by default OMAP1 uses 16bit ops.
+ * CLOCK_IDLE_CONTROL: (OMAP1 only) clock has autoidle support.
+ * CLOCK_NO_IDLE_PARENT: (OMAP1 only) when clock is enabled, its parent
+ * clock is put to no-idle mode.
+ * ENABLE_ON_INIT: Clock is enabled on init.
+ * INVERT_ENABLE: By default, clock enable bit behavior is '1' enable, '0'
+ * disable. This inverts the behavior making '0' enable and '1' disable.
+ * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
+ * bits share the same register. This flag allows the
+ * omap4_dpllmx*() code to determine which GATE_CTRL bit field
+ * should be used. This is a temporary solution - a better approach
+ * would be to associate clock type-specific data with the clock,
+ * similar to the struct dpll_data approach.
+ */
+#define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */
+#define CLOCK_IDLE_CONTROL (1 << 1)
+#define CLOCK_NO_IDLE_PARENT (1 << 2)
+#define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */
+#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */
+#define CLOCK_CLKOUTX2 (1 << 5)
+
/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
#define DPLL_LOW_POWER_STOP 0x1
#define DPLL_LOW_POWER_BYPASS 0x5
@@ -176,8 +203,13 @@ long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
void omap2_init_clk_clkdm(struct clk_hw *clk);
unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
unsigned long parent_rate);
+int omap2_clkops_enable_clkdm(struct clk_hw *hw);
+void omap2_clkops_disable_clkdm(struct clk_hw *hw);
int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
unsigned long parent_rate);
+int omap2_dflt_clk_enable(struct clk_hw *hw);
+void omap2_dflt_clk_disable(struct clk_hw *hw);
+int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
void ti_dt_clocks_register(struct ti_dt_clk *oclks);
void of_ti_autoidle_setup(struct device_node *node);
@@ -194,5 +226,8 @@ static inline void of_ti_clk_deny_autoidle_all(void) { }
extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
+extern const struct clk_hw_omap_ops clkhwops_wait;
+extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
+extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 07/36] CLK: TI: add support for clockdomain binding
2013-09-25 8:48 ` Tero Kristo
@ 2013-09-25 8:48 ` Tero Kristo
-1 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-omap, paul, tony, nm, rnayak, bcousson, mturquette
Cc: linux-arm-kernel, devicetree
Some OMAP clocks require knowledge about their parent clockdomain for
book keeping purposes. This patch creates a new DT binding for TI
clockdomains, which act as a collection of device clocks.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
.../devicetree/bindings/clock/ti/clockdomain.txt | 19 ++++++++
arch/arm/mach-omap2/clock.h | 1 -
drivers/clk/ti/Makefile | 2 +-
drivers/clk/ti/clockdomain.c | 46 ++++++++++++++++++++
include/linux/clk/ti.h | 2 +
5 files changed, 68 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/ti/clockdomain.txt
create mode 100644 drivers/clk/ti/clockdomain.c
diff --git a/Documentation/devicetree/bindings/clock/ti/clockdomain.txt b/Documentation/devicetree/bindings/clock/ti/clockdomain.txt
new file mode 100644
index 0000000..0dc5cd7
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/clockdomain.txt
@@ -0,0 +1,19 @@
+Binding for Texas Instruments clockdomain.
+
+This binding uses the common clock binding[1]. Every clock on
+TI SoC belongs to one clockdomain, but software only needs this
+information for specific clocks which require their parent
+clockdomain to be controlled when the clock is enabled/disabled.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be "ti,clockdomain"
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : link phandles of clocks within this domain
+
+Examples:
+ dss_clkdm: dss_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dss1_alwon_fck_3430es2>, <&dss_ick_3430es2>;
+ };
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index f0b7218..56d4664 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -38,7 +38,6 @@ struct omap_clk {
}
struct clockdomain;
-#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
#define DEFINE_STRUCT_CLK(_name, _parent_array_name, _clkops_name) \
static struct clk _name = { \
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 63b1c45..ce8bd06 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,4 +1,4 @@
ifneq ($(CONFIG_OF),)
obj-y += clk.o dpll.o autoidle.o divider.o \
- fixed-factor.o gate.o
+ fixed-factor.o gate.o clockdomain.o
endif
diff --git a/drivers/clk/ti/clockdomain.c b/drivers/clk/ti/clockdomain.c
new file mode 100644
index 0000000..3573bc9
--- /dev/null
+++ b/drivers/clk/ti/clockdomain.c
@@ -0,0 +1,46 @@
+/*
+ * OMAP clockdomain support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo <t-kristo@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk/ti.h>
+
+static void __init of_ti_clockdomain_setup(struct device_node *node)
+{
+ struct clk *clk;
+ struct clk_hw *clk_hw;
+ const char *clkdm_name = node->name;
+ int i;
+ int num_clks;
+
+ num_clks = of_count_phandle_with_args(node, "clocks", "#clock-cells");
+
+ for (i = 0; i < num_clks; i++) {
+ clk = of_clk_get(node, i);
+ if (__clk_get_flags(clk) & CLK_IS_BASIC) {
+ pr_warn("%s: can't setup clkdm for basic clk %s\n",
+ __func__, __clk_get_name(clk));
+ continue;
+ }
+ clk_hw = __clk_get_hw(clk);
+ to_clk_hw_omap(clk_hw)->clkdm_name = clkdm_name;
+ omap2_init_clk_clkdm(clk_hw);
+ }
+}
+CLK_OF_DECLARE(ti_clockdomain, "ti,clockdomain", of_ti_clockdomain_setup);
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index e0a2d32..e70a2eb 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -186,6 +186,8 @@ struct ti_dt_clk {
.node_name = name, \
}
+#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
+
void omap2_init_clk_hw_omap_clocks(struct clk *clk);
int omap3_noncore_dpll_enable(struct clk_hw *hw);
void omap3_noncore_dpll_disable(struct clk_hw *hw);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 07/36] CLK: TI: add support for clockdomain binding
@ 2013-09-25 8:48 ` Tero Kristo
0 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-arm-kernel
Some OMAP clocks require knowledge about their parent clockdomain for
book keeping purposes. This patch creates a new DT binding for TI
clockdomains, which act as a collection of device clocks.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
.../devicetree/bindings/clock/ti/clockdomain.txt | 19 ++++++++
arch/arm/mach-omap2/clock.h | 1 -
drivers/clk/ti/Makefile | 2 +-
drivers/clk/ti/clockdomain.c | 46 ++++++++++++++++++++
include/linux/clk/ti.h | 2 +
5 files changed, 68 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/ti/clockdomain.txt
create mode 100644 drivers/clk/ti/clockdomain.c
diff --git a/Documentation/devicetree/bindings/clock/ti/clockdomain.txt b/Documentation/devicetree/bindings/clock/ti/clockdomain.txt
new file mode 100644
index 0000000..0dc5cd7
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/clockdomain.txt
@@ -0,0 +1,19 @@
+Binding for Texas Instruments clockdomain.
+
+This binding uses the common clock binding[1]. Every clock on
+TI SoC belongs to one clockdomain, but software only needs this
+information for specific clocks which require their parent
+clockdomain to be controlled when the clock is enabled/disabled.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be "ti,clockdomain"
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : link phandles of clocks within this domain
+
+Examples:
+ dss_clkdm: dss_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dss1_alwon_fck_3430es2>, <&dss_ick_3430es2>;
+ };
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index f0b7218..56d4664 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -38,7 +38,6 @@ struct omap_clk {
}
struct clockdomain;
-#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
#define DEFINE_STRUCT_CLK(_name, _parent_array_name, _clkops_name) \
static struct clk _name = { \
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 63b1c45..ce8bd06 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,4 +1,4 @@
ifneq ($(CONFIG_OF),)
obj-y += clk.o dpll.o autoidle.o divider.o \
- fixed-factor.o gate.o
+ fixed-factor.o gate.o clockdomain.o
endif
diff --git a/drivers/clk/ti/clockdomain.c b/drivers/clk/ti/clockdomain.c
new file mode 100644
index 0000000..3573bc9
--- /dev/null
+++ b/drivers/clk/ti/clockdomain.c
@@ -0,0 +1,46 @@
+/*
+ * OMAP clockdomain support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo <t-kristo@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk/ti.h>
+
+static void __init of_ti_clockdomain_setup(struct device_node *node)
+{
+ struct clk *clk;
+ struct clk_hw *clk_hw;
+ const char *clkdm_name = node->name;
+ int i;
+ int num_clks;
+
+ num_clks = of_count_phandle_with_args(node, "clocks", "#clock-cells");
+
+ for (i = 0; i < num_clks; i++) {
+ clk = of_clk_get(node, i);
+ if (__clk_get_flags(clk) & CLK_IS_BASIC) {
+ pr_warn("%s: can't setup clkdm for basic clk %s\n",
+ __func__, __clk_get_name(clk));
+ continue;
+ }
+ clk_hw = __clk_get_hw(clk);
+ to_clk_hw_omap(clk_hw)->clkdm_name = clkdm_name;
+ omap2_init_clk_clkdm(clk_hw);
+ }
+}
+CLK_OF_DECLARE(ti_clockdomain, "ti,clockdomain", of_ti_clockdomain_setup);
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index e0a2d32..e70a2eb 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -186,6 +186,8 @@ struct ti_dt_clk {
.node_name = name, \
}
+#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
+
void omap2_init_clk_hw_omap_clocks(struct clk *clk);
int omap3_noncore_dpll_enable(struct clk_hw *hw);
void omap3_noncore_dpll_disable(struct clk_hw *hw);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 08/36] ARM: dts: omap4 clock data
2013-09-25 8:48 ` Tero Kristo
@ 2013-09-25 8:48 ` Tero Kristo
-1 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-omap, paul, tony, nm, rnayak, bcousson, mturquette
Cc: linux-arm-kernel, devicetree
This patch creates a unique node for each clock in the OMAP4 power,
reset and clock manager (PRCM). OMAP443x and OMAP446x have slightly
different clock tree which is taken into account in the data.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/boot/dts/omap443x-clocks.dtsi | 17 +
arch/arm/boot/dts/omap443x.dtsi | 20 +
arch/arm/boot/dts/omap4460.dtsi | 20 +
arch/arm/boot/dts/omap446x-clocks.dtsi | 26 +
arch/arm/boot/dts/omap44xx-clocks.dtsi | 1534 ++++++++++++++++++++++++++++++++
5 files changed, 1617 insertions(+)
create mode 100644 arch/arm/boot/dts/omap443x-clocks.dtsi
create mode 100644 arch/arm/boot/dts/omap446x-clocks.dtsi
create mode 100644 arch/arm/boot/dts/omap44xx-clocks.dtsi
diff --git a/arch/arm/boot/dts/omap443x-clocks.dtsi b/arch/arm/boot/dts/omap443x-clocks.dtsi
new file mode 100644
index 0000000..a538a07
--- /dev/null
+++ b/arch/arm/boot/dts/omap443x-clocks.dtsi
@@ -0,0 +1,17 @@
+/*
+ * Device Tree Source for OMAP443x clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+bandgap_fclk: bandgap_fclk@4a307888 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a307888 0x4>;
+};
diff --git a/arch/arm/boot/dts/omap443x.dtsi b/arch/arm/boot/dts/omap443x.dtsi
index bcf455e..68464c5 100644
--- a/arch/arm/boot/dts/omap443x.dtsi
+++ b/arch/arm/boot/dts/omap443x.dtsi
@@ -30,4 +30,24 @@
0x4a00232C 0x4>;
compatible = "ti,omap4430-bandgap";
};
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ /include/ "omap44xx-clocks.dtsi"
+ /include/ "omap443x-clocks.dtsi"
+ };
+
+ clockdomains {
+ l3_init_clkdm: l3_init_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&usb_host_fs_fck>, <&dpll_usb_ck>;
+ };
+
+ emu_sys_clkdm: emu_sys_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&trace_clk_div_ck>;
+ };
+ };
};
diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi
index c2f0f39..f3c48d0 100644
--- a/arch/arm/boot/dts/omap4460.dtsi
+++ b/arch/arm/boot/dts/omap4460.dtsi
@@ -38,4 +38,24 @@
interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; /* talert */
gpios = <&gpio3 22 0>; /* tshut */
};
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ /include/ "omap44xx-clocks.dtsi"
+ /include/ "omap446x-clocks.dtsi"
+ };
+
+ clockdomains {
+ l3_init_clkdm: l3_init_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&usb_host_fs_fck>, <&dpll_usb_ck>;
+ };
+
+ emu_sys_clkdm: emu_sys_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&trace_clk_div_ck>;
+ };
+ };
};
diff --git a/arch/arm/boot/dts/omap446x-clocks.dtsi b/arch/arm/boot/dts/omap446x-clocks.dtsi
new file mode 100644
index 0000000..96d5ddb
--- /dev/null
+++ b/arch/arm/boot/dts/omap446x-clocks.dtsi
@@ -0,0 +1,26 @@
+/*
+ * Device Tree Source for OMAP446x clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+div_ts_ck: div_ts_ck@4a307888 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&l4_wkup_clk_mux_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a307888 0x4>;
+ ti,dividers = <8>, <16>, <32>;
+};
+
+bandgap_ts_fclk: bandgap_ts_fclk@4a307888 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&div_ts_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a307888 0x4>;
+};
diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi b/arch/arm/boot/dts/omap44xx-clocks.dtsi
new file mode 100644
index 0000000..5644824
--- /dev/null
+++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi
@@ -0,0 +1,1534 @@
+/*
+ * Device Tree Source for OMAP4 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+extalt_clkin_ck: extalt_clkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <59000000>;
+};
+
+pad_clks_src_ck: pad_clks_src_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+};
+
+pad_clks_ck: pad_clks_ck@4a004108 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&pad_clks_src_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a004108 0x4>;
+};
+
+pad_slimbus_core_clks_ck: pad_slimbus_core_clks_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+};
+
+secure_32k_clk_src_ck: secure_32k_clk_src_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+};
+
+slimbus_src_clk: slimbus_src_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+};
+
+slimbus_clk: slimbus_clk@4a004108 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&slimbus_src_clk>;
+ ti,bit-shift = <10>;
+ reg = <0x4a004108 0x4>;
+};
+
+sys_32k_ck: sys_32k_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+};
+
+virt_12000000_ck: virt_12000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+};
+
+virt_13000000_ck: virt_13000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <13000000>;
+};
+
+virt_16800000_ck: virt_16800000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <16800000>;
+};
+
+virt_19200000_ck: virt_19200000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <19200000>;
+};
+
+virt_26000000_ck: virt_26000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <26000000>;
+};
+
+virt_27000000_ck: virt_27000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <27000000>;
+};
+
+virt_38400000_ck: virt_38400000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <38400000>;
+};
+
+sys_clkin_ck: sys_clkin_ck@4a306110 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
+ reg = <0x4a306110 0x4>;
+ ti,index-starts-at-one;
+};
+
+tie_low_clock_ck: tie_low_clock_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+utmi_phy_clkout_ck: utmi_phy_clkout_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <60000000>;
+};
+
+xclk60mhsp1_ck: xclk60mhsp1_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <60000000>;
+};
+
+xclk60mhsp2_ck: xclk60mhsp2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <60000000>;
+};
+
+xclk60motg_ck: xclk60motg_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <60000000>;
+};
+
+abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@4a306108 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a306108 0x4>;
+};
+
+abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck@4a30610c {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+ reg = <0x4a30610c 0x4>;
+};
+
+dpll_abe_ck: dpll_abe_ck@4a0041e0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-m4xen-clock";
+ clocks = <&abe_dpll_refclk_mux_ck>, <&abe_dpll_bypass_clk_mux_ck>;
+ reg = <0x4a0041e0 0x4>, <0x4a0041e4 0x4>, <0x4a0041e8 0x4>, <0x4a0041ec 0x4>;
+};
+
+dpll_abe_x2_ck: dpll_abe_x2_ck@4a0041f0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_abe_ck>;
+ reg = <0x4a0041f0 0x4>;
+};
+
+dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@4a0041f0 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0041f0 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+abe_24m_fclk: abe_24m_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_abe_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <8>;
+};
+
+abe_clk: abe_clk@4a004108 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_m2x2_ck>;
+ reg = <0x4a004108 0x4>;
+ ti,max-div = <4>;
+ ti,index-power-of-two;
+};
+
+aess_fclk: aess_fclk@4a004528 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&abe_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a004528 0x4>;
+ ti,max-div = <2>;
+};
+
+dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@4a0041f4 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0041f4 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+core_hsd_byp_clk_mux_ck: core_hsd_byp_clk_mux_ck@4a00412c {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin_ck>, <&dpll_abe_m3x2_ck>;
+ ti,bit-shift = <23>;
+ reg = <0x4a00412c 0x4>;
+};
+
+dpll_core_ck: dpll_core_ck@4a004120 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-core-clock";
+ clocks = <&sys_clkin_ck>, <&core_hsd_byp_clk_mux_ck>;
+ reg = <0x4a004120 0x4>, <0x4a004124 0x4>, <0x4a004128 0x4>, <0x4a00412c 0x4>;
+};
+
+dpll_core_x2_ck: dpll_core_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_core_ck>;
+};
+
+dpll_core_m6x2_ck: dpll_core_m6x2_ck@4a004140 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a004140 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dbgclk_mux_ck: dbgclk_mux_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dpll_core_m2_ck: dpll_core_m2_ck@4a004130 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a004130 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+ddrphy_ck: ddrphy_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+dpll_core_m5x2_ck: dpll_core_m5x2_ck@4a00413c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a00413c 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+div_core_ck: div_core_ck@4a004100 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_m5x2_ck>;
+ reg = <0x4a004100 0x4>;
+ ti,max-div = <2>;
+};
+
+div_iva_hs_clk: div_iva_hs_clk@4a0041dc {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_m5x2_ck>;
+ reg = <0x4a0041dc 0x4>;
+ ti,max-div = <4>;
+ ti,index-power-of-two;
+};
+
+div_mpu_hs_clk: div_mpu_hs_clk@4a00419c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_m5x2_ck>;
+ reg = <0x4a00419c 0x4>;
+ ti,max-div = <4>;
+ ti,index-power-of-two;
+};
+
+dpll_core_m4x2_ck: dpll_core_m4x2_ck@4a004138 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a004138 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dll_clk_div_ck: dll_clk_div_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m4x2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+dpll_abe_m2_ck: dpll_abe_m2_ck@4a0041f0 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_ck>;
+ reg = <0x4a0041f0 0x4>;
+ ti,max-div = <31>;
+ ti,index-starts-at-one;
+};
+
+dpll_core_m3x2_ck: dpll_core_m3x2_ck@4a004134 {
+ #clock-cells = <0>;
+ compatible = "ti,no-wait-mux-gate-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <31>;
+ reg-names = "gate-reg", "div-reg";
+ reg = <0x4a004134 0x4>, <0x4a004134 0x4>;
+ ti,gate-bit-shift = <8>;
+ ti,div-index-starts-at-one;
+};
+
+dpll_core_m7x2_ck: dpll_core_m7x2_ck@4a004144 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a004144 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+iva_hsd_byp_clk_mux_ck: iva_hsd_byp_clk_mux_ck@4a0041ac {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin_ck>, <&div_iva_hs_clk>;
+ ti,bit-shift = <23>;
+ reg = <0x4a0041ac 0x4>;
+};
+
+dpll_iva_ck: dpll_iva_ck@4a0041a0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin_ck>, <&iva_hsd_byp_clk_mux_ck>;
+ reg = <0x4a0041a0 0x4>, <0x4a0041a4 0x4>, <0x4a0041a8 0x4>, <0x4a0041ac 0x4>;
+};
+
+dpll_iva_x2_ck: dpll_iva_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_iva_ck>;
+};
+
+dpll_iva_m4x2_ck: dpll_iva_m4x2_ck@4a0041b8 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_iva_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0041b8 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_iva_m5x2_ck: dpll_iva_m5x2_ck@4a0041bc {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_iva_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0041bc 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_mpu_ck: dpll_mpu_ck@4a004160 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin_ck>, <&div_mpu_hs_clk>;
+ reg = <0x4a004160 0x4>, <0x4a004164 0x4>, <0x4a004168 0x4>, <0x4a00416c 0x4>;
+};
+
+dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a004170 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_mpu_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a004170 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+per_hs_clk_div_ck: per_hs_clk_div_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_abe_m3x2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+per_hsd_byp_clk_mux_ck: per_hsd_byp_clk_mux_ck@4a00814c {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin_ck>, <&per_hs_clk_div_ck>;
+ ti,bit-shift = <23>;
+ reg = <0x4a00814c 0x4>;
+};
+
+dpll_per_ck: dpll_per_ck@4a008140 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin_ck>, <&per_hsd_byp_clk_mux_ck>;
+ reg = <0x4a008140 0x4>, <0x4a008144 0x4>, <0x4a008148 0x4>, <0x4a00814c 0x4>;
+};
+
+dpll_per_m2_ck: dpll_per_m2_ck@4a008150 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_ck>;
+ reg = <0x4a008150 0x4>;
+ ti,max-div = <31>;
+ ti,index-starts-at-one;
+};
+
+dpll_per_x2_ck: dpll_per_x2_ck@4a008150 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_per_ck>;
+ reg = <0x4a008150 0x4>;
+};
+
+dpll_per_m2x2_ck: dpll_per_m2x2_ck@4a008150 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008150 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_per_m3x2_ck: dpll_per_m3x2_ck@4a008154 {
+ #clock-cells = <0>;
+ compatible = "ti,no-wait-mux-gate-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <31>;
+ reg-names = "gate-reg", "div-reg";
+ reg = <0x4a008154 0x4>, <0x4a008154 0x4>;
+ ti,gate-bit-shift = <8>;
+ ti,div-index-starts-at-one;
+};
+
+dpll_per_m4x2_ck: dpll_per_m4x2_ck@4a008158 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008158 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_per_m5x2_ck: dpll_per_m5x2_ck@4a00815c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a00815c 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_per_m6x2_ck: dpll_per_m6x2_ck@4a008160 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008160 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_per_m7x2_ck: dpll_per_m7x2_ck@4a008164 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008164 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+usb_hs_clk_div_ck: usb_hs_clk_div_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_abe_m3x2_ck>;
+ clock-mult = <1>;
+ clock-div = <3>;
+};
+
+dpll_usb_ck: dpll_usb_ck@4a008180 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-j-type-clock";
+ clocks = <&sys_clkin_ck>, <&usb_hs_clk_div_ck>;
+ reg = <0x4a008180 0x4>, <0x4a008184 0x4>, <0x4a008188 0x4>, <0x4a00818c 0x4>;
+};
+
+dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck@4a0081b4 {
+ #clock-cells = <0>;
+ compatible = "ti,fixed-factor-clock";
+ clocks = <&dpll_usb_ck>;
+ ti,clock-div = <1>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0081b4 0x4>;
+ ti,clock-mult = <1>;
+ ti,autoidle-low;
+};
+
+dpll_usb_m2_ck: dpll_usb_m2_ck@4a008190 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_usb_ck>;
+ ti,max-div = <127>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008190 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+ducati_clk_mux_ck: ducati_clk_mux_ck@4a008100 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&div_core_ck>, <&dpll_per_m6x2_ck>;
+ reg = <0x4a008100 0x4>;
+};
+
+func_12m_fclk: func_12m_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <16>;
+};
+
+func_24m_clk: func_24m_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+};
+
+func_24mc_fclk: func_24mc_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <8>;
+};
+
+func_48m_fclk: func_48m_fclk@4a008108 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ reg = <0x4a008108 0x4>;
+ ti,dividers = <4>, <8>;
+};
+
+func_48mc_fclk: func_48mc_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+};
+
+func_64m_fclk: func_64m_fclk@4a008108 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_m4x2_ck>;
+ reg = <0x4a008108 0x4>;
+ ti,dividers = <2>, <4>;
+};
+
+func_96m_fclk: func_96m_fclk@4a008108 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ reg = <0x4a008108 0x4>;
+ ti,dividers = <2>, <4>;
+};
+
+init_60m_fclk: init_60m_fclk@4a008104 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_usb_m2_ck>;
+ reg = <0x4a008104 0x4>;
+ ti,dividers = <1>, <8>;
+};
+
+l3_div_ck: l3_div_ck@4a004100 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&div_core_ck>;
+ ti,bit-shift = <4>;
+ reg = <0x4a004100 0x4>;
+ ti,max-div = <2>;
+};
+
+l4_div_ck: l4_div_ck@4a004100 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&l3_div_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a004100 0x4>;
+ ti,max-div = <2>;
+};
+
+lp_clk_div_ck: lp_clk_div_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_abe_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <16>;
+};
+
+l4_wkup_clk_mux_ck: l4_wkup_clk_mux_ck@4a306108 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin_ck>, <&lp_clk_div_ck>;
+ reg = <0x4a306108 0x4>;
+};
+
+mpu_periphclk: mpu_periphclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_mpu_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+ocp_abe_iclk: ocp_abe_iclk@4a004528 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&aess_fclk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a004528 0x4>;
+ ti,dividers = <2>, <1>;
+};
+
+per_abe_24m_fclk: per_abe_24m_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_abe_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+};
+
+per_abe_nc_fclk: per_abe_nc_fclk@4a008108 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_m2_ck>;
+ reg = <0x4a008108 0x4>;
+ ti,max-div = <2>;
+};
+
+syc_clk_div_ck: syc_clk_div_ck@4a306100 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&sys_clkin_ck>;
+ reg = <0x4a306100 0x4>;
+ ti,max-div = <2>;
+};
+
+aes1_fck: aes1_fck@4a0095a0 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l3_div_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x4a0095a0 0x4>;
+};
+
+aes2_fck: aes2_fck@4a0095a8 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l3_div_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x4a0095a8 0x4>;
+};
+
+dmic_sync_mux_ck: dmic_sync_mux_ck@4a004538 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+ ti,bit-shift = <25>;
+ reg = <0x4a004538 0x4>;
+};
+
+func_dmic_abe_gfclk: func_dmic_abe_gfclk@4a004538 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a004538 0x4>;
+};
+
+dss_sys_clk: dss_sys_clk@4a009120 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&syc_clk_div_ck>;
+ ti,bit-shift = <10>;
+ reg = <0x4a009120 0x4>;
+};
+
+dss_tv_clk: dss_tv_clk@4a009120 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&extalt_clkin_ck>;
+ ti,bit-shift = <11>;
+ reg = <0x4a009120 0x4>;
+};
+
+dss_dss_clk: dss_dss_clk@4a009120 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll_per_m5x2_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009120 0x4>;
+};
+
+dss_48mhz_clk: dss_48mhz_clk@4a009120 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&func_48mc_fclk>;
+ ti,bit-shift = <9>;
+ reg = <0x4a009120 0x4>;
+};
+
+dss_fck: dss_fck@4a009120 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l3_div_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x4a009120 0x4>;
+};
+
+fdif_fck: fdif_fck@4a009028 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_m4x2_ck>;
+ ti,bit-shift = <24>;
+ ti,max-div = <4>;
+ reg = <0x4a009028 0x4>;
+ ti,index-power-of-two;
+};
+
+gpio1_dbclk: gpio1_dbclk@4a307838 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a307838 0x4>;
+};
+
+gpio2_dbclk: gpio2_dbclk@4a009460 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009460 0x4>;
+};
+
+gpio3_dbclk: gpio3_dbclk@4a009468 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009468 0x4>;
+};
+
+gpio4_dbclk: gpio4_dbclk@4a009470 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009470 0x4>;
+};
+
+gpio5_dbclk: gpio5_dbclk@4a009478 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009478 0x4>;
+};
+
+gpio6_dbclk: gpio6_dbclk@4a009480 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009480 0x4>;
+};
+
+sgx_clk_mux: sgx_clk_mux@4a009220 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dpll_core_m7x2_ck>, <&dpll_per_m7x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009220 0x4>;
+};
+
+hsi_fck: hsi_fck@4a009338 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ ti,max-div = <4>;
+ reg = <0x4a009338 0x4>;
+ ti,index-power-of-two;
+};
+
+iss_ctrlclk: iss_ctrlclk@4a009020 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&func_96m_fclk>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009020 0x4>;
+};
+
+mcasp_sync_mux_ck: mcasp_sync_mux_ck@4a004540 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+ ti,bit-shift = <25>;
+ reg = <0x4a004540 0x4>;
+};
+
+func_mcasp_abe_gfclk: func_mcasp_abe_gfclk@4a004540 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a004540 0x4>;
+};
+
+mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck@4a004548 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+ ti,bit-shift = <25>;
+ reg = <0x4a004548 0x4>;
+};
+
+func_mcbsp1_gfclk: func_mcbsp1_gfclk@4a004548 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a004548 0x4>;
+};
+
+mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck@4a004550 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+ ti,bit-shift = <25>;
+ reg = <0x4a004550 0x4>;
+};
+
+func_mcbsp2_gfclk: func_mcbsp2_gfclk@4a004550 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a004550 0x4>;
+};
+
+mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck@4a004558 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+ ti,bit-shift = <25>;
+ reg = <0x4a004558 0x4>;
+};
+
+func_mcbsp3_gfclk: func_mcbsp3_gfclk@4a004558 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a004558 0x4>;
+};
+
+mcbsp4_sync_mux_ck: mcbsp4_sync_mux_ck@4a0094e0 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_96m_fclk>, <&per_abe_nc_fclk>;
+ ti,bit-shift = <25>;
+ reg = <0x4a0094e0 0x4>;
+};
+
+per_mcbsp4_gfclk: per_mcbsp4_gfclk@4a0094e0 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&mcbsp4_sync_mux_ck>, <&pad_clks_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a0094e0 0x4>;
+};
+
+hsmmc1_fclk: hsmmc1_fclk@4a009328 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_64m_fclk>, <&func_96m_fclk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009328 0x4>;
+};
+
+hsmmc2_fclk: hsmmc2_fclk@4a009330 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_64m_fclk>, <&func_96m_fclk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009330 0x4>;
+};
+
+ocp2scp_usb_phy_phy_48m: ocp2scp_usb_phy_phy_48m@4a0093e0 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&func_48m_fclk>;
+ ti,bit-shift = <8>;
+ reg = <0x4a0093e0 0x4>;
+};
+
+sha2md5_fck: sha2md5_fck@4a0095c8 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l3_div_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x4a0095c8 0x4>;
+};
+
+slimbus1_fclk_1: slimbus1_fclk_1@4a004560 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&func_24m_clk>;
+ ti,bit-shift = <9>;
+ reg = <0x4a004560 0x4>;
+};
+
+slimbus1_fclk_0: slimbus1_fclk_0@4a004560 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&abe_24m_fclk>;
+ ti,bit-shift = <8>;
+ reg = <0x4a004560 0x4>;
+};
+
+slimbus1_fclk_2: slimbus1_fclk_2@4a004560 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&pad_clks_ck>;
+ ti,bit-shift = <10>;
+ reg = <0x4a004560 0x4>;
+};
+
+slimbus1_slimbus_clk: slimbus1_slimbus_clk@4a004560 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&slimbus_clk>;
+ ti,bit-shift = <11>;
+ reg = <0x4a004560 0x4>;
+};
+
+slimbus2_fclk_1: slimbus2_fclk_1@4a009538 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&per_abe_24m_fclk>;
+ ti,bit-shift = <9>;
+ reg = <0x4a009538 0x4>;
+};
+
+slimbus2_fclk_0: slimbus2_fclk_0@4a009538 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&func_24mc_fclk>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009538 0x4>;
+};
+
+slimbus2_slimbus_clk: slimbus2_slimbus_clk@4a009538 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&pad_slimbus_core_clks_ck>;
+ ti,bit-shift = <10>;
+ reg = <0x4a009538 0x4>;
+};
+
+smartreflex_core_fck: smartreflex_core_fck@4a008638 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l4_wkup_clk_mux_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x4a008638 0x4>;
+};
+
+smartreflex_iva_fck: smartreflex_iva_fck@4a008630 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l4_wkup_clk_mux_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x4a008630 0x4>;
+};
+
+smartreflex_mpu_fck: smartreflex_mpu_fck@4a008628 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l4_wkup_clk_mux_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x4a008628 0x4>;
+};
+
+dmt1_clk_mux: dmt1_clk_mux@4a307840 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a307840 0x4>;
+};
+
+cm2_dm10_mux: cm2_dm10_mux@4a009428 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009428 0x4>;
+};
+
+cm2_dm11_mux: cm2_dm11_mux@4a009430 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009430 0x4>;
+};
+
+cm2_dm2_mux: cm2_dm2_mux@4a009438 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009438 0x4>;
+};
+
+cm2_dm3_mux: cm2_dm3_mux@4a009440 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009440 0x4>;
+};
+
+cm2_dm4_mux: cm2_dm4_mux@4a009448 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009448 0x4>;
+};
+
+timer5_sync_mux: timer5_sync_mux@4a004568 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a004568 0x4>;
+};
+
+timer6_sync_mux: timer6_sync_mux@4a004570 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a004570 0x4>;
+};
+
+timer7_sync_mux: timer7_sync_mux@4a004578 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a004578 0x4>;
+};
+
+timer8_sync_mux: timer8_sync_mux@4a004580 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a004580 0x4>;
+};
+
+cm2_dm9_mux: cm2_dm9_mux@4a009450 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009450 0x4>;
+};
+
+usb_host_fs_fck: usb_host_fs_fck@4a0093d0 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&func_48mc_fclk>;
+ ti,bit-shift = <1>;
+ reg = <0x4a0093d0 0x4>;
+};
+
+utmi_p1_gfclk: utmi_p1_gfclk@4a009358 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&init_60m_fclk>, <&xclk60mhsp1_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009358 0x4>;
+};
+
+usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk@4a009358 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&utmi_p1_gfclk>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009358 0x4>;
+};
+
+utmi_p2_gfclk: utmi_p2_gfclk@4a009358 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&init_60m_fclk>, <&xclk60mhsp2_ck>;
+ ti,bit-shift = <25>;
+ reg = <0x4a009358 0x4>;
+};
+
+usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk@4a009358 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&utmi_p2_gfclk>;
+ ti,bit-shift = <9>;
+ reg = <0x4a009358 0x4>;
+};
+
+usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk@4a009358 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&init_60m_fclk>;
+ ti,bit-shift = <10>;
+ reg = <0x4a009358 0x4>;
+};
+
+usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk@4a009358 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll_usb_m2_ck>;
+ ti,bit-shift = <13>;
+ reg = <0x4a009358 0x4>;
+};
+
+usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk@4a009358 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&init_60m_fclk>;
+ ti,bit-shift = <11>;
+ reg = <0x4a009358 0x4>;
+};
+
+usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk@4a009358 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&init_60m_fclk>;
+ ti,bit-shift = <12>;
+ reg = <0x4a009358 0x4>;
+};
+
+usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk@4a009358 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll_usb_m2_ck>;
+ ti,bit-shift = <14>;
+ reg = <0x4a009358 0x4>;
+};
+
+usb_host_hs_func48mclk: usb_host_hs_func48mclk@4a009358 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&func_48mc_fclk>;
+ ti,bit-shift = <15>;
+ reg = <0x4a009358 0x4>;
+};
+
+usb_host_hs_fck: usb_host_hs_fck@4a009358 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&init_60m_fclk>;
+ ti,bit-shift = <1>;
+ reg = <0x4a009358 0x4>;
+};
+
+otg_60m_gfclk: otg_60m_gfclk@4a009360 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&utmi_phy_clkout_ck>, <&xclk60motg_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009360 0x4>;
+};
+
+usb_otg_hs_xclk: usb_otg_hs_xclk@4a009360 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&otg_60m_gfclk>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009360 0x4>;
+};
+
+usb_otg_hs_ick: usb_otg_hs_ick@4a009360 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l3_div_ck>;
+ ti,bit-shift = <0>;
+ reg = <0x4a009360 0x4>;
+};
+
+usb_phy_cm_clk32k: usb_phy_cm_clk32k@4a008640 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a008640 0x4>;
+};
+
+usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk@4a009368 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&init_60m_fclk>;
+ ti,bit-shift = <10>;
+ reg = <0x4a009368 0x4>;
+};
+
+usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk@4a009368 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&init_60m_fclk>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009368 0x4>;
+};
+
+usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk@4a009368 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&init_60m_fclk>;
+ ti,bit-shift = <9>;
+ reg = <0x4a009368 0x4>;
+};
+
+usb_tll_hs_ick: usb_tll_hs_ick@4a009368 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l4_div_ck>;
+ ti,bit-shift = <0>;
+ reg = <0x4a009368 0x4>;
+};
+
+usim_ck: usim_ck@4a307858 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_m4x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a307858 0x4>;
+ ti,dividers = <14>, <18>;
+};
+
+usim_fclk: usim_fclk@4a307858 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&usim_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a307858 0x4>;
+};
+
+pmd_stm_clock_mux_ck: pmd_stm_clock_mux_ck@4a307a20 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin_ck>, <&dpll_core_m6x2_ck>, <&tie_low_clock_ck>;
+ ti,bit-shift = <20>;
+ reg = <0x4a307a20 0x4>;
+};
+
+pmd_trace_clk_mux_ck: pmd_trace_clk_mux_ck@4a307a20 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin_ck>, <&dpll_core_m6x2_ck>, <&tie_low_clock_ck>;
+ ti,bit-shift = <22>;
+ reg = <0x4a307a20 0x4>;
+};
+
+stm_clk_div_ck: stm_clk_div_ck@4a307a20 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&pmd_stm_clock_mux_ck>;
+ ti,bit-shift = <27>;
+ ti,max-div = <64>;
+ reg = <0x4a307a20 0x4>;
+ ti,index-power-of-two;
+};
+
+trace_clk_div_div_ck: trace_clk_div_div_ck@4a307a20 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ ti,bit-shift = <24>;
+ reg = <0x4a307a20 0x4>;
+ ti,max-div = <64>;
+ ti,index-power-of-two;
+};
+
+trace_clk_div_ck: trace_clk_div_ck {
+ #clock-cells = <0>;
+ compatible = "ti,clkdm-gate-clock";
+ clocks = <&trace_clk_div_div_ck>;
+};
+
+auxclk0_src_ck: auxclk0_src_ck@4a30a310 {
+ #clock-cells = <0>;
+ compatible = "ti,no-wait-mux-gate-clock";
+ clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ ti,gate-bit-shift = <8>;
+ reg = <0x4a30a310 0x4>, <0x4a30a310 0x4>;
+ ti,mux-bit-shift = <1>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+auxclk0_ck: auxclk0_ck@4a30a310 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&auxclk0_src_ck>;
+ ti,bit-shift = <16>;
+ reg = <0x4a30a310 0x4>;
+ ti,max-div = <16>;
+};
+
+auxclk1_src_ck: auxclk1_src_ck@4a30a314 {
+ #clock-cells = <0>;
+ compatible = "ti,no-wait-mux-gate-clock";
+ clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ ti,gate-bit-shift = <8>;
+ reg = <0x4a30a314 0x4>, <0x4a30a314 0x4>;
+ ti,mux-bit-shift = <1>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+auxclk1_ck: auxclk1_ck@4a30a314 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&auxclk1_src_ck>;
+ ti,bit-shift = <16>;
+ reg = <0x4a30a314 0x4>;
+ ti,max-div = <16>;
+};
+
+auxclk2_src_ck: auxclk2_src_ck@4a30a318 {
+ #clock-cells = <0>;
+ compatible = "ti,no-wait-mux-gate-clock";
+ clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ ti,gate-bit-shift = <8>;
+ reg = <0x4a30a318 0x4>, <0x4a30a318 0x4>;
+ ti,mux-bit-shift = <1>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+auxclk2_ck: auxclk2_ck@4a30a318 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&auxclk2_src_ck>;
+ ti,bit-shift = <16>;
+ reg = <0x4a30a318 0x4>;
+ ti,max-div = <16>;
+};
+
+auxclk3_src_ck: auxclk3_src_ck@4a30a31c {
+ #clock-cells = <0>;
+ compatible = "ti,no-wait-mux-gate-clock";
+ clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ ti,gate-bit-shift = <8>;
+ reg = <0x4a30a31c 0x4>, <0x4a30a31c 0x4>;
+ ti,mux-bit-shift = <1>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+auxclk3_ck: auxclk3_ck@4a30a31c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&auxclk3_src_ck>;
+ ti,bit-shift = <16>;
+ reg = <0x4a30a31c 0x4>;
+ ti,max-div = <16>;
+};
+
+auxclk4_src_ck: auxclk4_src_ck@4a30a320 {
+ #clock-cells = <0>;
+ compatible = "ti,no-wait-mux-gate-clock";
+ clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ ti,gate-bit-shift = <8>;
+ reg = <0x4a30a320 0x4>, <0x4a30a320 0x4>;
+ ti,mux-bit-shift = <1>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+auxclk4_ck: auxclk4_ck@4a30a320 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&auxclk4_src_ck>;
+ ti,bit-shift = <16>;
+ reg = <0x4a30a320 0x4>;
+ ti,max-div = <16>;
+};
+
+auxclk5_src_ck: auxclk5_src_ck@4a30a324 {
+ #clock-cells = <0>;
+ compatible = "ti,no-wait-mux-gate-clock";
+ clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ ti,gate-bit-shift = <8>;
+ reg = <0x4a30a324 0x4>, <0x4a30a324 0x4>;
+ ti,mux-bit-shift = <1>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+auxclk5_ck: auxclk5_ck@4a30a324 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&auxclk5_src_ck>;
+ ti,bit-shift = <16>;
+ reg = <0x4a30a324 0x4>;
+ ti,max-div = <16>;
+};
+
+auxclkreq0_ck: auxclkreq0_ck@4a30a210 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x4a30a210 0x4>;
+};
+
+auxclkreq1_ck: auxclkreq1_ck@4a30a214 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x4a30a214 0x4>;
+};
+
+auxclkreq2_ck: auxclkreq2_ck@4a30a218 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x4a30a218 0x4>;
+};
+
+auxclkreq3_ck: auxclkreq3_ck@4a30a21c {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x4a30a21c 0x4>;
+};
+
+auxclkreq4_ck: auxclkreq4_ck@4a30a220 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x4a30a220 0x4>;
+};
+
+auxclkreq5_ck: auxclkreq5_ck@4a30a224 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x4a30a224 0x4>;
+};
+
+dummy_ck: dummy_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
\ No newline at end of file
--
1.7.9.5
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 08/36] ARM: dts: omap4 clock data
@ 2013-09-25 8:48 ` Tero Kristo
0 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-arm-kernel
This patch creates a unique node for each clock in the OMAP4 power,
reset and clock manager (PRCM). OMAP443x and OMAP446x have slightly
different clock tree which is taken into account in the data.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/boot/dts/omap443x-clocks.dtsi | 17 +
arch/arm/boot/dts/omap443x.dtsi | 20 +
arch/arm/boot/dts/omap4460.dtsi | 20 +
arch/arm/boot/dts/omap446x-clocks.dtsi | 26 +
arch/arm/boot/dts/omap44xx-clocks.dtsi | 1534 ++++++++++++++++++++++++++++++++
5 files changed, 1617 insertions(+)
create mode 100644 arch/arm/boot/dts/omap443x-clocks.dtsi
create mode 100644 arch/arm/boot/dts/omap446x-clocks.dtsi
create mode 100644 arch/arm/boot/dts/omap44xx-clocks.dtsi
diff --git a/arch/arm/boot/dts/omap443x-clocks.dtsi b/arch/arm/boot/dts/omap443x-clocks.dtsi
new file mode 100644
index 0000000..a538a07
--- /dev/null
+++ b/arch/arm/boot/dts/omap443x-clocks.dtsi
@@ -0,0 +1,17 @@
+/*
+ * Device Tree Source for OMAP443x clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+bandgap_fclk: bandgap_fclk at 4a307888 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a307888 0x4>;
+};
diff --git a/arch/arm/boot/dts/omap443x.dtsi b/arch/arm/boot/dts/omap443x.dtsi
index bcf455e..68464c5 100644
--- a/arch/arm/boot/dts/omap443x.dtsi
+++ b/arch/arm/boot/dts/omap443x.dtsi
@@ -30,4 +30,24 @@
0x4a00232C 0x4>;
compatible = "ti,omap4430-bandgap";
};
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ /include/ "omap44xx-clocks.dtsi"
+ /include/ "omap443x-clocks.dtsi"
+ };
+
+ clockdomains {
+ l3_init_clkdm: l3_init_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&usb_host_fs_fck>, <&dpll_usb_ck>;
+ };
+
+ emu_sys_clkdm: emu_sys_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&trace_clk_div_ck>;
+ };
+ };
};
diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi
index c2f0f39..f3c48d0 100644
--- a/arch/arm/boot/dts/omap4460.dtsi
+++ b/arch/arm/boot/dts/omap4460.dtsi
@@ -38,4 +38,24 @@
interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; /* talert */
gpios = <&gpio3 22 0>; /* tshut */
};
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ /include/ "omap44xx-clocks.dtsi"
+ /include/ "omap446x-clocks.dtsi"
+ };
+
+ clockdomains {
+ l3_init_clkdm: l3_init_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&usb_host_fs_fck>, <&dpll_usb_ck>;
+ };
+
+ emu_sys_clkdm: emu_sys_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&trace_clk_div_ck>;
+ };
+ };
};
diff --git a/arch/arm/boot/dts/omap446x-clocks.dtsi b/arch/arm/boot/dts/omap446x-clocks.dtsi
new file mode 100644
index 0000000..96d5ddb
--- /dev/null
+++ b/arch/arm/boot/dts/omap446x-clocks.dtsi
@@ -0,0 +1,26 @@
+/*
+ * Device Tree Source for OMAP446x clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+div_ts_ck: div_ts_ck at 4a307888 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&l4_wkup_clk_mux_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a307888 0x4>;
+ ti,dividers = <8>, <16>, <32>;
+};
+
+bandgap_ts_fclk: bandgap_ts_fclk at 4a307888 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&div_ts_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a307888 0x4>;
+};
diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi b/arch/arm/boot/dts/omap44xx-clocks.dtsi
new file mode 100644
index 0000000..5644824
--- /dev/null
+++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi
@@ -0,0 +1,1534 @@
+/*
+ * Device Tree Source for OMAP4 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+extalt_clkin_ck: extalt_clkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <59000000>;
+};
+
+pad_clks_src_ck: pad_clks_src_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+};
+
+pad_clks_ck: pad_clks_ck at 4a004108 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&pad_clks_src_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a004108 0x4>;
+};
+
+pad_slimbus_core_clks_ck: pad_slimbus_core_clks_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+};
+
+secure_32k_clk_src_ck: secure_32k_clk_src_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+};
+
+slimbus_src_clk: slimbus_src_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+};
+
+slimbus_clk: slimbus_clk at 4a004108 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&slimbus_src_clk>;
+ ti,bit-shift = <10>;
+ reg = <0x4a004108 0x4>;
+};
+
+sys_32k_ck: sys_32k_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+};
+
+virt_12000000_ck: virt_12000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+};
+
+virt_13000000_ck: virt_13000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <13000000>;
+};
+
+virt_16800000_ck: virt_16800000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <16800000>;
+};
+
+virt_19200000_ck: virt_19200000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <19200000>;
+};
+
+virt_26000000_ck: virt_26000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <26000000>;
+};
+
+virt_27000000_ck: virt_27000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <27000000>;
+};
+
+virt_38400000_ck: virt_38400000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <38400000>;
+};
+
+sys_clkin_ck: sys_clkin_ck at 4a306110 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
+ reg = <0x4a306110 0x4>;
+ ti,index-starts-at-one;
+};
+
+tie_low_clock_ck: tie_low_clock_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+utmi_phy_clkout_ck: utmi_phy_clkout_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <60000000>;
+};
+
+xclk60mhsp1_ck: xclk60mhsp1_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <60000000>;
+};
+
+xclk60mhsp2_ck: xclk60mhsp2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <60000000>;
+};
+
+xclk60motg_ck: xclk60motg_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <60000000>;
+};
+
+abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck at 4a306108 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a306108 0x4>;
+};
+
+abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck at 4a30610c {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+ reg = <0x4a30610c 0x4>;
+};
+
+dpll_abe_ck: dpll_abe_ck at 4a0041e0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-m4xen-clock";
+ clocks = <&abe_dpll_refclk_mux_ck>, <&abe_dpll_bypass_clk_mux_ck>;
+ reg = <0x4a0041e0 0x4>, <0x4a0041e4 0x4>, <0x4a0041e8 0x4>, <0x4a0041ec 0x4>;
+};
+
+dpll_abe_x2_ck: dpll_abe_x2_ck at 4a0041f0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_abe_ck>;
+ reg = <0x4a0041f0 0x4>;
+};
+
+dpll_abe_m2x2_ck: dpll_abe_m2x2_ck at 4a0041f0 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0041f0 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+abe_24m_fclk: abe_24m_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_abe_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <8>;
+};
+
+abe_clk: abe_clk at 4a004108 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_m2x2_ck>;
+ reg = <0x4a004108 0x4>;
+ ti,max-div = <4>;
+ ti,index-power-of-two;
+};
+
+aess_fclk: aess_fclk at 4a004528 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&abe_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a004528 0x4>;
+ ti,max-div = <2>;
+};
+
+dpll_abe_m3x2_ck: dpll_abe_m3x2_ck at 4a0041f4 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0041f4 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+core_hsd_byp_clk_mux_ck: core_hsd_byp_clk_mux_ck at 4a00412c {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin_ck>, <&dpll_abe_m3x2_ck>;
+ ti,bit-shift = <23>;
+ reg = <0x4a00412c 0x4>;
+};
+
+dpll_core_ck: dpll_core_ck at 4a004120 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-core-clock";
+ clocks = <&sys_clkin_ck>, <&core_hsd_byp_clk_mux_ck>;
+ reg = <0x4a004120 0x4>, <0x4a004124 0x4>, <0x4a004128 0x4>, <0x4a00412c 0x4>;
+};
+
+dpll_core_x2_ck: dpll_core_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_core_ck>;
+};
+
+dpll_core_m6x2_ck: dpll_core_m6x2_ck at 4a004140 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a004140 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dbgclk_mux_ck: dbgclk_mux_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dpll_core_m2_ck: dpll_core_m2_ck at 4a004130 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a004130 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+ddrphy_ck: ddrphy_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+dpll_core_m5x2_ck: dpll_core_m5x2_ck at 4a00413c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a00413c 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+div_core_ck: div_core_ck at 4a004100 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_m5x2_ck>;
+ reg = <0x4a004100 0x4>;
+ ti,max-div = <2>;
+};
+
+div_iva_hs_clk: div_iva_hs_clk at 4a0041dc {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_m5x2_ck>;
+ reg = <0x4a0041dc 0x4>;
+ ti,max-div = <4>;
+ ti,index-power-of-two;
+};
+
+div_mpu_hs_clk: div_mpu_hs_clk at 4a00419c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_m5x2_ck>;
+ reg = <0x4a00419c 0x4>;
+ ti,max-div = <4>;
+ ti,index-power-of-two;
+};
+
+dpll_core_m4x2_ck: dpll_core_m4x2_ck at 4a004138 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a004138 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dll_clk_div_ck: dll_clk_div_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m4x2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+dpll_abe_m2_ck: dpll_abe_m2_ck at 4a0041f0 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_ck>;
+ reg = <0x4a0041f0 0x4>;
+ ti,max-div = <31>;
+ ti,index-starts-at-one;
+};
+
+dpll_core_m3x2_ck: dpll_core_m3x2_ck at 4a004134 {
+ #clock-cells = <0>;
+ compatible = "ti,no-wait-mux-gate-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <31>;
+ reg-names = "gate-reg", "div-reg";
+ reg = <0x4a004134 0x4>, <0x4a004134 0x4>;
+ ti,gate-bit-shift = <8>;
+ ti,div-index-starts-at-one;
+};
+
+dpll_core_m7x2_ck: dpll_core_m7x2_ck at 4a004144 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a004144 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+iva_hsd_byp_clk_mux_ck: iva_hsd_byp_clk_mux_ck at 4a0041ac {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin_ck>, <&div_iva_hs_clk>;
+ ti,bit-shift = <23>;
+ reg = <0x4a0041ac 0x4>;
+};
+
+dpll_iva_ck: dpll_iva_ck at 4a0041a0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin_ck>, <&iva_hsd_byp_clk_mux_ck>;
+ reg = <0x4a0041a0 0x4>, <0x4a0041a4 0x4>, <0x4a0041a8 0x4>, <0x4a0041ac 0x4>;
+};
+
+dpll_iva_x2_ck: dpll_iva_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_iva_ck>;
+};
+
+dpll_iva_m4x2_ck: dpll_iva_m4x2_ck at 4a0041b8 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_iva_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0041b8 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_iva_m5x2_ck: dpll_iva_m5x2_ck at 4a0041bc {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_iva_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0041bc 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_mpu_ck: dpll_mpu_ck at 4a004160 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin_ck>, <&div_mpu_hs_clk>;
+ reg = <0x4a004160 0x4>, <0x4a004164 0x4>, <0x4a004168 0x4>, <0x4a00416c 0x4>;
+};
+
+dpll_mpu_m2_ck: dpll_mpu_m2_ck at 4a004170 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_mpu_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a004170 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+per_hs_clk_div_ck: per_hs_clk_div_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_abe_m3x2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+per_hsd_byp_clk_mux_ck: per_hsd_byp_clk_mux_ck at 4a00814c {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin_ck>, <&per_hs_clk_div_ck>;
+ ti,bit-shift = <23>;
+ reg = <0x4a00814c 0x4>;
+};
+
+dpll_per_ck: dpll_per_ck at 4a008140 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin_ck>, <&per_hsd_byp_clk_mux_ck>;
+ reg = <0x4a008140 0x4>, <0x4a008144 0x4>, <0x4a008148 0x4>, <0x4a00814c 0x4>;
+};
+
+dpll_per_m2_ck: dpll_per_m2_ck at 4a008150 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_ck>;
+ reg = <0x4a008150 0x4>;
+ ti,max-div = <31>;
+ ti,index-starts-at-one;
+};
+
+dpll_per_x2_ck: dpll_per_x2_ck at 4a008150 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_per_ck>;
+ reg = <0x4a008150 0x4>;
+};
+
+dpll_per_m2x2_ck: dpll_per_m2x2_ck at 4a008150 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008150 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_per_m3x2_ck: dpll_per_m3x2_ck at 4a008154 {
+ #clock-cells = <0>;
+ compatible = "ti,no-wait-mux-gate-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <31>;
+ reg-names = "gate-reg", "div-reg";
+ reg = <0x4a008154 0x4>, <0x4a008154 0x4>;
+ ti,gate-bit-shift = <8>;
+ ti,div-index-starts-at-one;
+};
+
+dpll_per_m4x2_ck: dpll_per_m4x2_ck at 4a008158 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008158 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_per_m5x2_ck: dpll_per_m5x2_ck at 4a00815c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a00815c 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_per_m6x2_ck: dpll_per_m6x2_ck at 4a008160 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008160 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_per_m7x2_ck: dpll_per_m7x2_ck at 4a008164 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008164 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+usb_hs_clk_div_ck: usb_hs_clk_div_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_abe_m3x2_ck>;
+ clock-mult = <1>;
+ clock-div = <3>;
+};
+
+dpll_usb_ck: dpll_usb_ck at 4a008180 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-j-type-clock";
+ clocks = <&sys_clkin_ck>, <&usb_hs_clk_div_ck>;
+ reg = <0x4a008180 0x4>, <0x4a008184 0x4>, <0x4a008188 0x4>, <0x4a00818c 0x4>;
+};
+
+dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck at 4a0081b4 {
+ #clock-cells = <0>;
+ compatible = "ti,fixed-factor-clock";
+ clocks = <&dpll_usb_ck>;
+ ti,clock-div = <1>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0081b4 0x4>;
+ ti,clock-mult = <1>;
+ ti,autoidle-low;
+};
+
+dpll_usb_m2_ck: dpll_usb_m2_ck at 4a008190 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_usb_ck>;
+ ti,max-div = <127>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008190 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+ducati_clk_mux_ck: ducati_clk_mux_ck at 4a008100 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&div_core_ck>, <&dpll_per_m6x2_ck>;
+ reg = <0x4a008100 0x4>;
+};
+
+func_12m_fclk: func_12m_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <16>;
+};
+
+func_24m_clk: func_24m_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+};
+
+func_24mc_fclk: func_24mc_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <8>;
+};
+
+func_48m_fclk: func_48m_fclk at 4a008108 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ reg = <0x4a008108 0x4>;
+ ti,dividers = <4>, <8>;
+};
+
+func_48mc_fclk: func_48mc_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+};
+
+func_64m_fclk: func_64m_fclk at 4a008108 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_m4x2_ck>;
+ reg = <0x4a008108 0x4>;
+ ti,dividers = <2>, <4>;
+};
+
+func_96m_fclk: func_96m_fclk at 4a008108 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ reg = <0x4a008108 0x4>;
+ ti,dividers = <2>, <4>;
+};
+
+init_60m_fclk: init_60m_fclk at 4a008104 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_usb_m2_ck>;
+ reg = <0x4a008104 0x4>;
+ ti,dividers = <1>, <8>;
+};
+
+l3_div_ck: l3_div_ck at 4a004100 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&div_core_ck>;
+ ti,bit-shift = <4>;
+ reg = <0x4a004100 0x4>;
+ ti,max-div = <2>;
+};
+
+l4_div_ck: l4_div_ck at 4a004100 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&l3_div_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a004100 0x4>;
+ ti,max-div = <2>;
+};
+
+lp_clk_div_ck: lp_clk_div_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_abe_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <16>;
+};
+
+l4_wkup_clk_mux_ck: l4_wkup_clk_mux_ck at 4a306108 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin_ck>, <&lp_clk_div_ck>;
+ reg = <0x4a306108 0x4>;
+};
+
+mpu_periphclk: mpu_periphclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_mpu_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+ocp_abe_iclk: ocp_abe_iclk at 4a004528 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&aess_fclk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a004528 0x4>;
+ ti,dividers = <2>, <1>;
+};
+
+per_abe_24m_fclk: per_abe_24m_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_abe_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+};
+
+per_abe_nc_fclk: per_abe_nc_fclk at 4a008108 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_m2_ck>;
+ reg = <0x4a008108 0x4>;
+ ti,max-div = <2>;
+};
+
+syc_clk_div_ck: syc_clk_div_ck at 4a306100 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&sys_clkin_ck>;
+ reg = <0x4a306100 0x4>;
+ ti,max-div = <2>;
+};
+
+aes1_fck: aes1_fck at 4a0095a0 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l3_div_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x4a0095a0 0x4>;
+};
+
+aes2_fck: aes2_fck at 4a0095a8 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l3_div_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x4a0095a8 0x4>;
+};
+
+dmic_sync_mux_ck: dmic_sync_mux_ck at 4a004538 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+ ti,bit-shift = <25>;
+ reg = <0x4a004538 0x4>;
+};
+
+func_dmic_abe_gfclk: func_dmic_abe_gfclk at 4a004538 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a004538 0x4>;
+};
+
+dss_sys_clk: dss_sys_clk at 4a009120 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&syc_clk_div_ck>;
+ ti,bit-shift = <10>;
+ reg = <0x4a009120 0x4>;
+};
+
+dss_tv_clk: dss_tv_clk at 4a009120 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&extalt_clkin_ck>;
+ ti,bit-shift = <11>;
+ reg = <0x4a009120 0x4>;
+};
+
+dss_dss_clk: dss_dss_clk at 4a009120 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll_per_m5x2_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009120 0x4>;
+};
+
+dss_48mhz_clk: dss_48mhz_clk at 4a009120 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&func_48mc_fclk>;
+ ti,bit-shift = <9>;
+ reg = <0x4a009120 0x4>;
+};
+
+dss_fck: dss_fck at 4a009120 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l3_div_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x4a009120 0x4>;
+};
+
+fdif_fck: fdif_fck at 4a009028 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_m4x2_ck>;
+ ti,bit-shift = <24>;
+ ti,max-div = <4>;
+ reg = <0x4a009028 0x4>;
+ ti,index-power-of-two;
+};
+
+gpio1_dbclk: gpio1_dbclk at 4a307838 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a307838 0x4>;
+};
+
+gpio2_dbclk: gpio2_dbclk at 4a009460 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009460 0x4>;
+};
+
+gpio3_dbclk: gpio3_dbclk at 4a009468 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009468 0x4>;
+};
+
+gpio4_dbclk: gpio4_dbclk at 4a009470 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009470 0x4>;
+};
+
+gpio5_dbclk: gpio5_dbclk at 4a009478 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009478 0x4>;
+};
+
+gpio6_dbclk: gpio6_dbclk at 4a009480 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009480 0x4>;
+};
+
+sgx_clk_mux: sgx_clk_mux at 4a009220 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dpll_core_m7x2_ck>, <&dpll_per_m7x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009220 0x4>;
+};
+
+hsi_fck: hsi_fck at 4a009338 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ ti,max-div = <4>;
+ reg = <0x4a009338 0x4>;
+ ti,index-power-of-two;
+};
+
+iss_ctrlclk: iss_ctrlclk at 4a009020 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&func_96m_fclk>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009020 0x4>;
+};
+
+mcasp_sync_mux_ck: mcasp_sync_mux_ck at 4a004540 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+ ti,bit-shift = <25>;
+ reg = <0x4a004540 0x4>;
+};
+
+func_mcasp_abe_gfclk: func_mcasp_abe_gfclk at 4a004540 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a004540 0x4>;
+};
+
+mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck at 4a004548 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+ ti,bit-shift = <25>;
+ reg = <0x4a004548 0x4>;
+};
+
+func_mcbsp1_gfclk: func_mcbsp1_gfclk at 4a004548 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a004548 0x4>;
+};
+
+mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck at 4a004550 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+ ti,bit-shift = <25>;
+ reg = <0x4a004550 0x4>;
+};
+
+func_mcbsp2_gfclk: func_mcbsp2_gfclk at 4a004550 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a004550 0x4>;
+};
+
+mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck at 4a004558 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+ ti,bit-shift = <25>;
+ reg = <0x4a004558 0x4>;
+};
+
+func_mcbsp3_gfclk: func_mcbsp3_gfclk at 4a004558 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a004558 0x4>;
+};
+
+mcbsp4_sync_mux_ck: mcbsp4_sync_mux_ck at 4a0094e0 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_96m_fclk>, <&per_abe_nc_fclk>;
+ ti,bit-shift = <25>;
+ reg = <0x4a0094e0 0x4>;
+};
+
+per_mcbsp4_gfclk: per_mcbsp4_gfclk at 4a0094e0 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&mcbsp4_sync_mux_ck>, <&pad_clks_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a0094e0 0x4>;
+};
+
+hsmmc1_fclk: hsmmc1_fclk at 4a009328 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_64m_fclk>, <&func_96m_fclk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009328 0x4>;
+};
+
+hsmmc2_fclk: hsmmc2_fclk at 4a009330 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_64m_fclk>, <&func_96m_fclk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009330 0x4>;
+};
+
+ocp2scp_usb_phy_phy_48m: ocp2scp_usb_phy_phy_48m at 4a0093e0 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&func_48m_fclk>;
+ ti,bit-shift = <8>;
+ reg = <0x4a0093e0 0x4>;
+};
+
+sha2md5_fck: sha2md5_fck at 4a0095c8 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l3_div_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x4a0095c8 0x4>;
+};
+
+slimbus1_fclk_1: slimbus1_fclk_1 at 4a004560 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&func_24m_clk>;
+ ti,bit-shift = <9>;
+ reg = <0x4a004560 0x4>;
+};
+
+slimbus1_fclk_0: slimbus1_fclk_0 at 4a004560 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&abe_24m_fclk>;
+ ti,bit-shift = <8>;
+ reg = <0x4a004560 0x4>;
+};
+
+slimbus1_fclk_2: slimbus1_fclk_2 at 4a004560 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&pad_clks_ck>;
+ ti,bit-shift = <10>;
+ reg = <0x4a004560 0x4>;
+};
+
+slimbus1_slimbus_clk: slimbus1_slimbus_clk at 4a004560 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&slimbus_clk>;
+ ti,bit-shift = <11>;
+ reg = <0x4a004560 0x4>;
+};
+
+slimbus2_fclk_1: slimbus2_fclk_1 at 4a009538 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&per_abe_24m_fclk>;
+ ti,bit-shift = <9>;
+ reg = <0x4a009538 0x4>;
+};
+
+slimbus2_fclk_0: slimbus2_fclk_0 at 4a009538 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&func_24mc_fclk>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009538 0x4>;
+};
+
+slimbus2_slimbus_clk: slimbus2_slimbus_clk at 4a009538 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&pad_slimbus_core_clks_ck>;
+ ti,bit-shift = <10>;
+ reg = <0x4a009538 0x4>;
+};
+
+smartreflex_core_fck: smartreflex_core_fck at 4a008638 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l4_wkup_clk_mux_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x4a008638 0x4>;
+};
+
+smartreflex_iva_fck: smartreflex_iva_fck at 4a008630 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l4_wkup_clk_mux_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x4a008630 0x4>;
+};
+
+smartreflex_mpu_fck: smartreflex_mpu_fck at 4a008628 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l4_wkup_clk_mux_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x4a008628 0x4>;
+};
+
+dmt1_clk_mux: dmt1_clk_mux at 4a307840 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a307840 0x4>;
+};
+
+cm2_dm10_mux: cm2_dm10_mux at 4a009428 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009428 0x4>;
+};
+
+cm2_dm11_mux: cm2_dm11_mux at 4a009430 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009430 0x4>;
+};
+
+cm2_dm2_mux: cm2_dm2_mux at 4a009438 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009438 0x4>;
+};
+
+cm2_dm3_mux: cm2_dm3_mux at 4a009440 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009440 0x4>;
+};
+
+cm2_dm4_mux: cm2_dm4_mux at 4a009448 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009448 0x4>;
+};
+
+timer5_sync_mux: timer5_sync_mux at 4a004568 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a004568 0x4>;
+};
+
+timer6_sync_mux: timer6_sync_mux at 4a004570 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a004570 0x4>;
+};
+
+timer7_sync_mux: timer7_sync_mux at 4a004578 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a004578 0x4>;
+};
+
+timer8_sync_mux: timer8_sync_mux at 4a004580 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a004580 0x4>;
+};
+
+cm2_dm9_mux: cm2_dm9_mux at 4a009450 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009450 0x4>;
+};
+
+usb_host_fs_fck: usb_host_fs_fck at 4a0093d0 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&func_48mc_fclk>;
+ ti,bit-shift = <1>;
+ reg = <0x4a0093d0 0x4>;
+};
+
+utmi_p1_gfclk: utmi_p1_gfclk at 4a009358 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&init_60m_fclk>, <&xclk60mhsp1_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009358 0x4>;
+};
+
+usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk at 4a009358 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&utmi_p1_gfclk>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009358 0x4>;
+};
+
+utmi_p2_gfclk: utmi_p2_gfclk at 4a009358 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&init_60m_fclk>, <&xclk60mhsp2_ck>;
+ ti,bit-shift = <25>;
+ reg = <0x4a009358 0x4>;
+};
+
+usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk at 4a009358 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&utmi_p2_gfclk>;
+ ti,bit-shift = <9>;
+ reg = <0x4a009358 0x4>;
+};
+
+usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk at 4a009358 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&init_60m_fclk>;
+ ti,bit-shift = <10>;
+ reg = <0x4a009358 0x4>;
+};
+
+usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk at 4a009358 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll_usb_m2_ck>;
+ ti,bit-shift = <13>;
+ reg = <0x4a009358 0x4>;
+};
+
+usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk at 4a009358 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&init_60m_fclk>;
+ ti,bit-shift = <11>;
+ reg = <0x4a009358 0x4>;
+};
+
+usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk at 4a009358 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&init_60m_fclk>;
+ ti,bit-shift = <12>;
+ reg = <0x4a009358 0x4>;
+};
+
+usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk at 4a009358 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll_usb_m2_ck>;
+ ti,bit-shift = <14>;
+ reg = <0x4a009358 0x4>;
+};
+
+usb_host_hs_func48mclk: usb_host_hs_func48mclk at 4a009358 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&func_48mc_fclk>;
+ ti,bit-shift = <15>;
+ reg = <0x4a009358 0x4>;
+};
+
+usb_host_hs_fck: usb_host_hs_fck at 4a009358 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&init_60m_fclk>;
+ ti,bit-shift = <1>;
+ reg = <0x4a009358 0x4>;
+};
+
+otg_60m_gfclk: otg_60m_gfclk at 4a009360 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&utmi_phy_clkout_ck>, <&xclk60motg_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009360 0x4>;
+};
+
+usb_otg_hs_xclk: usb_otg_hs_xclk at 4a009360 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&otg_60m_gfclk>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009360 0x4>;
+};
+
+usb_otg_hs_ick: usb_otg_hs_ick at 4a009360 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l3_div_ck>;
+ ti,bit-shift = <0>;
+ reg = <0x4a009360 0x4>;
+};
+
+usb_phy_cm_clk32k: usb_phy_cm_clk32k at 4a008640 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a008640 0x4>;
+};
+
+usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk at 4a009368 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&init_60m_fclk>;
+ ti,bit-shift = <10>;
+ reg = <0x4a009368 0x4>;
+};
+
+usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk at 4a009368 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&init_60m_fclk>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009368 0x4>;
+};
+
+usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk at 4a009368 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&init_60m_fclk>;
+ ti,bit-shift = <9>;
+ reg = <0x4a009368 0x4>;
+};
+
+usb_tll_hs_ick: usb_tll_hs_ick at 4a009368 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l4_div_ck>;
+ ti,bit-shift = <0>;
+ reg = <0x4a009368 0x4>;
+};
+
+usim_ck: usim_ck at 4a307858 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_m4x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a307858 0x4>;
+ ti,dividers = <14>, <18>;
+};
+
+usim_fclk: usim_fclk at 4a307858 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&usim_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a307858 0x4>;
+};
+
+pmd_stm_clock_mux_ck: pmd_stm_clock_mux_ck at 4a307a20 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin_ck>, <&dpll_core_m6x2_ck>, <&tie_low_clock_ck>;
+ ti,bit-shift = <20>;
+ reg = <0x4a307a20 0x4>;
+};
+
+pmd_trace_clk_mux_ck: pmd_trace_clk_mux_ck at 4a307a20 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin_ck>, <&dpll_core_m6x2_ck>, <&tie_low_clock_ck>;
+ ti,bit-shift = <22>;
+ reg = <0x4a307a20 0x4>;
+};
+
+stm_clk_div_ck: stm_clk_div_ck at 4a307a20 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&pmd_stm_clock_mux_ck>;
+ ti,bit-shift = <27>;
+ ti,max-div = <64>;
+ reg = <0x4a307a20 0x4>;
+ ti,index-power-of-two;
+};
+
+trace_clk_div_div_ck: trace_clk_div_div_ck at 4a307a20 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ ti,bit-shift = <24>;
+ reg = <0x4a307a20 0x4>;
+ ti,max-div = <64>;
+ ti,index-power-of-two;
+};
+
+trace_clk_div_ck: trace_clk_div_ck {
+ #clock-cells = <0>;
+ compatible = "ti,clkdm-gate-clock";
+ clocks = <&trace_clk_div_div_ck>;
+};
+
+auxclk0_src_ck: auxclk0_src_ck at 4a30a310 {
+ #clock-cells = <0>;
+ compatible = "ti,no-wait-mux-gate-clock";
+ clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ ti,gate-bit-shift = <8>;
+ reg = <0x4a30a310 0x4>, <0x4a30a310 0x4>;
+ ti,mux-bit-shift = <1>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+auxclk0_ck: auxclk0_ck at 4a30a310 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&auxclk0_src_ck>;
+ ti,bit-shift = <16>;
+ reg = <0x4a30a310 0x4>;
+ ti,max-div = <16>;
+};
+
+auxclk1_src_ck: auxclk1_src_ck at 4a30a314 {
+ #clock-cells = <0>;
+ compatible = "ti,no-wait-mux-gate-clock";
+ clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ ti,gate-bit-shift = <8>;
+ reg = <0x4a30a314 0x4>, <0x4a30a314 0x4>;
+ ti,mux-bit-shift = <1>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+auxclk1_ck: auxclk1_ck at 4a30a314 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&auxclk1_src_ck>;
+ ti,bit-shift = <16>;
+ reg = <0x4a30a314 0x4>;
+ ti,max-div = <16>;
+};
+
+auxclk2_src_ck: auxclk2_src_ck at 4a30a318 {
+ #clock-cells = <0>;
+ compatible = "ti,no-wait-mux-gate-clock";
+ clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ ti,gate-bit-shift = <8>;
+ reg = <0x4a30a318 0x4>, <0x4a30a318 0x4>;
+ ti,mux-bit-shift = <1>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+auxclk2_ck: auxclk2_ck at 4a30a318 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&auxclk2_src_ck>;
+ ti,bit-shift = <16>;
+ reg = <0x4a30a318 0x4>;
+ ti,max-div = <16>;
+};
+
+auxclk3_src_ck: auxclk3_src_ck at 4a30a31c {
+ #clock-cells = <0>;
+ compatible = "ti,no-wait-mux-gate-clock";
+ clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ ti,gate-bit-shift = <8>;
+ reg = <0x4a30a31c 0x4>, <0x4a30a31c 0x4>;
+ ti,mux-bit-shift = <1>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+auxclk3_ck: auxclk3_ck at 4a30a31c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&auxclk3_src_ck>;
+ ti,bit-shift = <16>;
+ reg = <0x4a30a31c 0x4>;
+ ti,max-div = <16>;
+};
+
+auxclk4_src_ck: auxclk4_src_ck at 4a30a320 {
+ #clock-cells = <0>;
+ compatible = "ti,no-wait-mux-gate-clock";
+ clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ ti,gate-bit-shift = <8>;
+ reg = <0x4a30a320 0x4>, <0x4a30a320 0x4>;
+ ti,mux-bit-shift = <1>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+auxclk4_ck: auxclk4_ck at 4a30a320 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&auxclk4_src_ck>;
+ ti,bit-shift = <16>;
+ reg = <0x4a30a320 0x4>;
+ ti,max-div = <16>;
+};
+
+auxclk5_src_ck: auxclk5_src_ck at 4a30a324 {
+ #clock-cells = <0>;
+ compatible = "ti,no-wait-mux-gate-clock";
+ clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ ti,gate-bit-shift = <8>;
+ reg = <0x4a30a324 0x4>, <0x4a30a324 0x4>;
+ ti,mux-bit-shift = <1>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+auxclk5_ck: auxclk5_ck at 4a30a324 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&auxclk5_src_ck>;
+ ti,bit-shift = <16>;
+ reg = <0x4a30a324 0x4>;
+ ti,max-div = <16>;
+};
+
+auxclkreq0_ck: auxclkreq0_ck at 4a30a210 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x4a30a210 0x4>;
+};
+
+auxclkreq1_ck: auxclkreq1_ck at 4a30a214 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x4a30a214 0x4>;
+};
+
+auxclkreq2_ck: auxclkreq2_ck at 4a30a218 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x4a30a218 0x4>;
+};
+
+auxclkreq3_ck: auxclkreq3_ck at 4a30a21c {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x4a30a21c 0x4>;
+};
+
+auxclkreq4_ck: auxclkreq4_ck at 4a30a220 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x4a30a220 0x4>;
+};
+
+auxclkreq5_ck: auxclkreq5_ck at 4a30a224 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x4a30a224 0x4>;
+};
+
+dummy_ck: dummy_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
\ No newline at end of file
--
1.7.9.5
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 09/36] clk: ti: add mux-gate clock support
2013-09-25 8:48 ` Tero Kristo
@ 2013-09-25 8:48 ` Tero Kristo
-1 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-omap-u79uwXL29TY76Z2rM5mHXA, paul-DWxLp4Yu+b8AvxtiuMwx3w,
tony-4v6yS6AI5VpBDgjK7y7TUQ, nm-l0cyMroinI0, rnayak-l0cyMroinI0,
bcousson-rdvid1DuHRBWk0Htik3J/w,
mturquette-QSEj5FYQhm4dnm+yROfE0A
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
This is a multipurpose clock node, which contains support for multiple
sub-clocks. Uses composite clock type to implement the actual functionality.
Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
.../devicetree/bindings/clock/ti/mux-gate.txt | 98 +++++++++
drivers/clk/ti/Makefile | 3 +-
drivers/clk/ti/mux-gate.c | 214 ++++++++++++++++++++
include/linux/clk/ti.h | 1 +
4 files changed, 315 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/clock/ti/mux-gate.txt
create mode 100644 drivers/clk/ti/mux-gate.c
diff --git a/Documentation/devicetree/bindings/clock/ti/mux-gate.txt b/Documentation/devicetree/bindings/clock/ti/mux-gate.txt
new file mode 100644
index 0000000..bda2b4c
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/mux-gate.txt
@@ -0,0 +1,98 @@
+Binding for TI mux-gate clock.
+
+This binding uses the common clock binding[1]. It assumes a
+register-mapped composite clock with multiple different sub-types;
+
+a multiplexer clock with multiple input clock signals or parents, one
+of which can be selected as output, this behaves exactly as [2]
+
+an adjustable clock rate divider, this behaves exactly as [3]
+
+a gating function which can be used to enable and disable the output
+clock, this behaves exactly as [4]
+
+The binding must provide the register mapping to control the mux-gate.
+"reg-names" property is used to specify which sub-function are used
+for this composite clock, and to specify the corresponding control
+register addresses. Optional parameters are specified according to
+the sub-types used.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/clock/ti/mux.txt
+[3] Documentation/devicetree/bindings/clock/ti/divider.txt
+[4] Documentation/devicetree/bindings/clock/ti/gate.txt
+
+Required properties:
+- compatible : shall be one of:
+ "ti,mux-gate-clock" : mux-gate clock which waits until clock is active
+ before returning from clk_enable()
+ "ti,no-wait-mux-gate-clock" : mux-gate clock which does not wait for
+ clock activity
+ "ti,interface-mux-gate-clock" : mux-gate interface clock which waits until
+ clock is active before returning from
+ clk_enable()
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : link phandles of parent clocks
+- reg : base address array for registers controlling the mux-gate
+ sub-functions. Ordered according to "reg-names" property.
+- reg-names : register names property, can have following values:
+ "gate-reg" : base address for gate function control register
+ "mux-reg" : base address for mux function control register
+ "div-reg" : base address for divider function control register
+ Any of these values can be left out, and the corresponding function
+ will not be present in the composite clock either.
+
+Optional properties:
+- ti,gate-bit-shift : number of bits to shift the enable bit for gating
+ function, defaults to 0 if not present
+- ti,mux-bit-shift : number of bits to shift the bit-field for mux
+ function, defaults to 0 if not present
+- ti,div-index-starts-at-one : min-div is mapped to bit-value 1, default 0
+- ti,max-div : maximum divider value for the divider function
+- ti,min-div : minimum divider value for the divider function, defaults to
+ 1 if not present
+- ti,dividers : array of valid divider values for the clock
+
+Examples:
+
+dpll_core_m3x2_ck: dpll_core_m3x2_ck@4a004134 {
+ #clock-cells = <0>;
+ compatible = "ti,no-wait-mux-gate-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <31>;
+ reg-names = "gate-reg", "div-reg";
+ reg = <0x4a004134 0x4>, <0x4a004134 0x4>;
+ ti,gate-bit-shift = <8>;
+ ti,div-index-starts-at-one;
+};
+
+auxclk2_src_ck: auxclk2_src_ck@4a30a318 {
+ #clock-cells = <0>;
+ compatible = "ti,no-wait-mux-gate-clock";
+ clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ reg-names = "gate-reg", "mux-reg";
+ reg = <0x4a30a318 0x4>, <0x4a30a318 0x4>;
+ ti,gate-bit-shift = <8>;
+ ti,mux-bit-shift = <1>;
+};
+
+gpt10_fck: gpt10_fck@48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-gate-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ reg-names = "gate-reg", "mux-reg";
+ reg = <0x48004a00 0x4>, <0x48004a40 0x4>;
+ ti,gate-bit-shift = <11>;
+ ti,mux-bit-shift = <6>;
+};
+
+ssi_ssr_fck_3430es1: ssi_ssr_fck_3430es1@48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,no-wait-mux-gate-clock";
+ clocks = <&corex2_fck>;
+ ti,div-bit-shift = <8>;
+ ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
+ reg-names = "gate-reg", "div-reg";
+ reg = <0x48004a00 0x4>, <0x48004a40 0x4>;
+ ti,gate-bit-shift = <0>;
+};
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index ce8bd06..68d55c9 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,4 +1,5 @@
ifneq ($(CONFIG_OF),)
obj-y += clk.o dpll.o autoidle.o divider.o \
- fixed-factor.o gate.o clockdomain.o
+ fixed-factor.o gate.o clockdomain.o \
+ mux-gate.o
endif
diff --git a/drivers/clk/ti/mux-gate.c b/drivers/clk/ti/mux-gate.c
new file mode 100644
index 0000000..e7b5bd8
--- /dev/null
+++ b/drivers/clk/ti/mux-gate.c
@@ -0,0 +1,214 @@
+/*
+ * OMAP mux-gate clock support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk/ti.h>
+
+#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
+
+static unsigned long omap_mux_gate_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ return clk_divider_ops.recalc_rate(hw, parent_rate);
+}
+
+static long omap_mux_gate_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ return -EINVAL;
+}
+
+static int omap_mux_gate_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ return -EINVAL;
+}
+
+static const struct clk_ops omap_mux_gate_divider_ops = {
+ .recalc_rate = &omap_mux_gate_recalc_rate,
+ .round_rate = &omap_mux_gate_round_rate,
+ .set_rate = &omap_mux_gate_set_rate,
+};
+
+static const struct clk_ops omap_mux_gate_gate_ops = {
+ .enable = &omap2_dflt_clk_enable,
+ .disable = &omap2_dflt_clk_disable,
+ .is_enabled = &omap2_dflt_clk_is_enabled,
+};
+
+static void __init
+_of_ti_mux_gate_clk_setup(struct device_node *node,
+ const struct clk_hw_omap_ops *hw_ops)
+{
+ struct clk *clk;
+ const char *clk_name = node->name;
+ const char **parent_names = NULL;
+ int num_parents;
+ struct clk_hw_omap *gate = NULL;
+ struct clk_divider *div = NULL;
+ struct clk_mux *mux = NULL;
+ const struct clk_ops *mux_ops, *div_ops, *gate_ops;
+ u32 val;
+ int i;
+ u32 min_div, max_div, divider;
+
+ of_property_read_string(node, "clock-output-names", &clk_name);
+
+ num_parents = of_clk_get_parent_count(node);
+
+ if (num_parents < 1) {
+ pr_err("%s: omap-mux-clock %s must have parent(s)\n", __func__,
+ node->name);
+ return;
+ }
+
+ parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL);
+
+ for (i = 0; i < num_parents; i++)
+ parent_names[i] = of_clk_get_parent_name(node, i);
+
+ i = of_property_match_string(node, "reg-names", "gate-reg");
+ if (i >= 0) {
+ gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+ gate->enable_reg = of_iomap(node, i);
+ if (of_property_read_u32(node, "ti,gate-bit-shift", &val)) {
+ pr_err("%s: missing gate-bit-shift property for %s\n",
+ __func__, node->name);
+ goto cleanup;
+ }
+ gate->enable_bit = val;
+ gate->ops = hw_ops;
+
+ gate_ops = &omap_mux_gate_gate_ops;
+ }
+
+ i = of_property_match_string(node, "reg-names", "mux-reg");
+ if (i >= 0) {
+ mux = kzalloc(sizeof(*mux), GFP_KERNEL);
+ mux->reg = of_iomap(node, i);
+ mux_ops = &clk_mux_ops;
+ if (of_property_read_u32(node, "ti,mux-bit-shift", &val)) {
+ pr_debug("%s: missing mux-bit-shift property for %s, defaulting to 0\n",
+ __func__, node->name);
+ val = 0;
+ }
+ mux->shift = val;
+
+ mux->mask = num_parents - 1;
+ mux->mask = (1 << fls(mux->mask)) - 1;
+
+ mux_ops = &clk_mux_ops;
+ }
+
+ i = of_property_match_string(node, "reg-names", "div-reg");
+ if (i >= 0) {
+ div = kzalloc(sizeof(*div), GFP_KERNEL);
+ div->reg = of_iomap(node, i);
+
+ div->table = ti_clk_get_div_table(node);
+
+ if (of_property_read_bool(node, "ti,div-index-starts-at-one"))
+ div->flags |= CLK_DIVIDER_ONE_BASED;
+
+ if (!div->table) {
+ if (of_property_read_u32(node, "ti,min-div",
+ &min_div)) {
+ pr_debug("%s: ti,min-div not declared for %s, defaulting to 1\n",
+ __func__, node->name);
+ min_div = 1;
+ }
+
+ if (of_property_read_u32(node, "ti,max-div",
+ &max_div)) {
+ pr_err("%s: ti,max-div not declared for %s\n",
+ __func__, node->name);
+ goto cleanup;
+ }
+
+ val = 0;
+
+ if (div->flags & CLK_DIVIDER_ONE_BASED)
+ val = 1;
+
+ divider = min_div;
+
+ while (divider < max_div) {
+ divider++;
+ val++;
+ }
+ } else {
+ divider = 0;
+ while (div->table[divider].val) {
+ val = div->table[divider].val;
+ divider++;
+ }
+ }
+
+ div->width = fls(val);
+
+ if (of_property_read_u32(node, "ti,div-bit-shift", &val)) {
+ pr_debug("%s: missing div-bit-shift property for %s, defaulting to 0\n",
+ __func__, node->name);
+ val = 0;
+ }
+ div->shift = val;
+
+ div->table = ti_clk_get_div_table(node);
+
+ div_ops = &omap_mux_gate_divider_ops;
+ }
+
+ clk = clk_register_composite(NULL, clk_name,
+ parent_names, num_parents,
+ mux ? &mux->hw : NULL, mux_ops,
+ div ? &div->hw : NULL, div_ops,
+ gate ? &gate->hw : NULL, gate_ops, 0);
+
+ if (!IS_ERR(clk))
+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
+ return;
+cleanup:
+ kfree(mux);
+ kfree(div);
+ kfree(gate);
+ kfree(parent_names);
+}
+
+static void __init of_ti_no_wait_mux_gate_clk_setup(struct device_node *node)
+{
+ _of_ti_mux_gate_clk_setup(node, NULL);
+}
+CLK_OF_DECLARE(ti_no_wait_mux_gate_clk, "ti,no-wait-mux-gate-clock",
+ of_ti_no_wait_mux_gate_clk_setup);
+
+static void __init of_ti_interface_mux_gate_clk_setup(struct device_node *node)
+{
+ _of_ti_mux_gate_clk_setup(node, &clkhwops_iclk_wait);
+}
+CLK_OF_DECLARE(ti_interface_mux_gate_clk, "ti,interface-mux-gate-clock",
+ of_ti_interface_mux_gate_clk_setup);
+
+static void __init of_ti_mux_gate_clk_setup(struct device_node *node)
+{
+ _of_ti_mux_gate_clk_setup(node, &clkhwops_wait);
+}
+CLK_OF_DECLARE(ti_mux_gate_clk, "ti,mux-gate-clock",
+ of_ti_mux_gate_clk_setup);
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index e70a2eb..ed4b36e 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -229,6 +229,7 @@ static inline void of_ti_clk_deny_autoidle_all(void) { }
extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
extern const struct clk_hw_omap_ops clkhwops_wait;
+extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
--
1.7.9.5
--
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^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 09/36] clk: ti: add mux-gate clock support
@ 2013-09-25 8:48 ` Tero Kristo
0 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-arm-kernel
This is a multipurpose clock node, which contains support for multiple
sub-clocks. Uses composite clock type to implement the actual functionality.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
.../devicetree/bindings/clock/ti/mux-gate.txt | 98 +++++++++
drivers/clk/ti/Makefile | 3 +-
drivers/clk/ti/mux-gate.c | 214 ++++++++++++++++++++
include/linux/clk/ti.h | 1 +
4 files changed, 315 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/clock/ti/mux-gate.txt
create mode 100644 drivers/clk/ti/mux-gate.c
diff --git a/Documentation/devicetree/bindings/clock/ti/mux-gate.txt b/Documentation/devicetree/bindings/clock/ti/mux-gate.txt
new file mode 100644
index 0000000..bda2b4c
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/mux-gate.txt
@@ -0,0 +1,98 @@
+Binding for TI mux-gate clock.
+
+This binding uses the common clock binding[1]. It assumes a
+register-mapped composite clock with multiple different sub-types;
+
+a multiplexer clock with multiple input clock signals or parents, one
+of which can be selected as output, this behaves exactly as [2]
+
+an adjustable clock rate divider, this behaves exactly as [3]
+
+a gating function which can be used to enable and disable the output
+clock, this behaves exactly as [4]
+
+The binding must provide the register mapping to control the mux-gate.
+"reg-names" property is used to specify which sub-function are used
+for this composite clock, and to specify the corresponding control
+register addresses. Optional parameters are specified according to
+the sub-types used.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/clock/ti/mux.txt
+[3] Documentation/devicetree/bindings/clock/ti/divider.txt
+[4] Documentation/devicetree/bindings/clock/ti/gate.txt
+
+Required properties:
+- compatible : shall be one of:
+ "ti,mux-gate-clock" : mux-gate clock which waits until clock is active
+ before returning from clk_enable()
+ "ti,no-wait-mux-gate-clock" : mux-gate clock which does not wait for
+ clock activity
+ "ti,interface-mux-gate-clock" : mux-gate interface clock which waits until
+ clock is active before returning from
+ clk_enable()
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : link phandles of parent clocks
+- reg : base address array for registers controlling the mux-gate
+ sub-functions. Ordered according to "reg-names" property.
+- reg-names : register names property, can have following values:
+ "gate-reg" : base address for gate function control register
+ "mux-reg" : base address for mux function control register
+ "div-reg" : base address for divider function control register
+ Any of these values can be left out, and the corresponding function
+ will not be present in the composite clock either.
+
+Optional properties:
+- ti,gate-bit-shift : number of bits to shift the enable bit for gating
+ function, defaults to 0 if not present
+- ti,mux-bit-shift : number of bits to shift the bit-field for mux
+ function, defaults to 0 if not present
+- ti,div-index-starts-at-one : min-div is mapped to bit-value 1, default 0
+- ti,max-div : maximum divider value for the divider function
+- ti,min-div : minimum divider value for the divider function, defaults to
+ 1 if not present
+- ti,dividers : array of valid divider values for the clock
+
+Examples:
+
+dpll_core_m3x2_ck: dpll_core_m3x2_ck at 4a004134 {
+ #clock-cells = <0>;
+ compatible = "ti,no-wait-mux-gate-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <31>;
+ reg-names = "gate-reg", "div-reg";
+ reg = <0x4a004134 0x4>, <0x4a004134 0x4>;
+ ti,gate-bit-shift = <8>;
+ ti,div-index-starts-at-one;
+};
+
+auxclk2_src_ck: auxclk2_src_ck at 4a30a318 {
+ #clock-cells = <0>;
+ compatible = "ti,no-wait-mux-gate-clock";
+ clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ reg-names = "gate-reg", "mux-reg";
+ reg = <0x4a30a318 0x4>, <0x4a30a318 0x4>;
+ ti,gate-bit-shift = <8>;
+ ti,mux-bit-shift = <1>;
+};
+
+gpt10_fck: gpt10_fck at 48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-gate-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ reg-names = "gate-reg", "mux-reg";
+ reg = <0x48004a00 0x4>, <0x48004a40 0x4>;
+ ti,gate-bit-shift = <11>;
+ ti,mux-bit-shift = <6>;
+};
+
+ssi_ssr_fck_3430es1: ssi_ssr_fck_3430es1 at 48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,no-wait-mux-gate-clock";
+ clocks = <&corex2_fck>;
+ ti,div-bit-shift = <8>;
+ ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
+ reg-names = "gate-reg", "div-reg";
+ reg = <0x48004a00 0x4>, <0x48004a40 0x4>;
+ ti,gate-bit-shift = <0>;
+};
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index ce8bd06..68d55c9 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,4 +1,5 @@
ifneq ($(CONFIG_OF),)
obj-y += clk.o dpll.o autoidle.o divider.o \
- fixed-factor.o gate.o clockdomain.o
+ fixed-factor.o gate.o clockdomain.o \
+ mux-gate.o
endif
diff --git a/drivers/clk/ti/mux-gate.c b/drivers/clk/ti/mux-gate.c
new file mode 100644
index 0000000..e7b5bd8
--- /dev/null
+++ b/drivers/clk/ti/mux-gate.c
@@ -0,0 +1,214 @@
+/*
+ * OMAP mux-gate clock support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo <t-kristo@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk/ti.h>
+
+#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
+
+static unsigned long omap_mux_gate_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ return clk_divider_ops.recalc_rate(hw, parent_rate);
+}
+
+static long omap_mux_gate_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ return -EINVAL;
+}
+
+static int omap_mux_gate_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ return -EINVAL;
+}
+
+static const struct clk_ops omap_mux_gate_divider_ops = {
+ .recalc_rate = &omap_mux_gate_recalc_rate,
+ .round_rate = &omap_mux_gate_round_rate,
+ .set_rate = &omap_mux_gate_set_rate,
+};
+
+static const struct clk_ops omap_mux_gate_gate_ops = {
+ .enable = &omap2_dflt_clk_enable,
+ .disable = &omap2_dflt_clk_disable,
+ .is_enabled = &omap2_dflt_clk_is_enabled,
+};
+
+static void __init
+_of_ti_mux_gate_clk_setup(struct device_node *node,
+ const struct clk_hw_omap_ops *hw_ops)
+{
+ struct clk *clk;
+ const char *clk_name = node->name;
+ const char **parent_names = NULL;
+ int num_parents;
+ struct clk_hw_omap *gate = NULL;
+ struct clk_divider *div = NULL;
+ struct clk_mux *mux = NULL;
+ const struct clk_ops *mux_ops, *div_ops, *gate_ops;
+ u32 val;
+ int i;
+ u32 min_div, max_div, divider;
+
+ of_property_read_string(node, "clock-output-names", &clk_name);
+
+ num_parents = of_clk_get_parent_count(node);
+
+ if (num_parents < 1) {
+ pr_err("%s: omap-mux-clock %s must have parent(s)\n", __func__,
+ node->name);
+ return;
+ }
+
+ parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL);
+
+ for (i = 0; i < num_parents; i++)
+ parent_names[i] = of_clk_get_parent_name(node, i);
+
+ i = of_property_match_string(node, "reg-names", "gate-reg");
+ if (i >= 0) {
+ gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+ gate->enable_reg = of_iomap(node, i);
+ if (of_property_read_u32(node, "ti,gate-bit-shift", &val)) {
+ pr_err("%s: missing gate-bit-shift property for %s\n",
+ __func__, node->name);
+ goto cleanup;
+ }
+ gate->enable_bit = val;
+ gate->ops = hw_ops;
+
+ gate_ops = &omap_mux_gate_gate_ops;
+ }
+
+ i = of_property_match_string(node, "reg-names", "mux-reg");
+ if (i >= 0) {
+ mux = kzalloc(sizeof(*mux), GFP_KERNEL);
+ mux->reg = of_iomap(node, i);
+ mux_ops = &clk_mux_ops;
+ if (of_property_read_u32(node, "ti,mux-bit-shift", &val)) {
+ pr_debug("%s: missing mux-bit-shift property for %s, defaulting to 0\n",
+ __func__, node->name);
+ val = 0;
+ }
+ mux->shift = val;
+
+ mux->mask = num_parents - 1;
+ mux->mask = (1 << fls(mux->mask)) - 1;
+
+ mux_ops = &clk_mux_ops;
+ }
+
+ i = of_property_match_string(node, "reg-names", "div-reg");
+ if (i >= 0) {
+ div = kzalloc(sizeof(*div), GFP_KERNEL);
+ div->reg = of_iomap(node, i);
+
+ div->table = ti_clk_get_div_table(node);
+
+ if (of_property_read_bool(node, "ti,div-index-starts-at-one"))
+ div->flags |= CLK_DIVIDER_ONE_BASED;
+
+ if (!div->table) {
+ if (of_property_read_u32(node, "ti,min-div",
+ &min_div)) {
+ pr_debug("%s: ti,min-div not declared for %s, defaulting to 1\n",
+ __func__, node->name);
+ min_div = 1;
+ }
+
+ if (of_property_read_u32(node, "ti,max-div",
+ &max_div)) {
+ pr_err("%s: ti,max-div not declared for %s\n",
+ __func__, node->name);
+ goto cleanup;
+ }
+
+ val = 0;
+
+ if (div->flags & CLK_DIVIDER_ONE_BASED)
+ val = 1;
+
+ divider = min_div;
+
+ while (divider < max_div) {
+ divider++;
+ val++;
+ }
+ } else {
+ divider = 0;
+ while (div->table[divider].val) {
+ val = div->table[divider].val;
+ divider++;
+ }
+ }
+
+ div->width = fls(val);
+
+ if (of_property_read_u32(node, "ti,div-bit-shift", &val)) {
+ pr_debug("%s: missing div-bit-shift property for %s, defaulting to 0\n",
+ __func__, node->name);
+ val = 0;
+ }
+ div->shift = val;
+
+ div->table = ti_clk_get_div_table(node);
+
+ div_ops = &omap_mux_gate_divider_ops;
+ }
+
+ clk = clk_register_composite(NULL, clk_name,
+ parent_names, num_parents,
+ mux ? &mux->hw : NULL, mux_ops,
+ div ? &div->hw : NULL, div_ops,
+ gate ? &gate->hw : NULL, gate_ops, 0);
+
+ if (!IS_ERR(clk))
+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
+ return;
+cleanup:
+ kfree(mux);
+ kfree(div);
+ kfree(gate);
+ kfree(parent_names);
+}
+
+static void __init of_ti_no_wait_mux_gate_clk_setup(struct device_node *node)
+{
+ _of_ti_mux_gate_clk_setup(node, NULL);
+}
+CLK_OF_DECLARE(ti_no_wait_mux_gate_clk, "ti,no-wait-mux-gate-clock",
+ of_ti_no_wait_mux_gate_clk_setup);
+
+static void __init of_ti_interface_mux_gate_clk_setup(struct device_node *node)
+{
+ _of_ti_mux_gate_clk_setup(node, &clkhwops_iclk_wait);
+}
+CLK_OF_DECLARE(ti_interface_mux_gate_clk, "ti,interface-mux-gate-clock",
+ of_ti_interface_mux_gate_clk_setup);
+
+static void __init of_ti_mux_gate_clk_setup(struct device_node *node)
+{
+ _of_ti_mux_gate_clk_setup(node, &clkhwops_wait);
+}
+CLK_OF_DECLARE(ti_mux_gate_clk, "ti,mux-gate-clock",
+ of_ti_mux_gate_clk_setup);
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index e70a2eb..ed4b36e 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -229,6 +229,7 @@ static inline void of_ti_clk_deny_autoidle_all(void) { }
extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
extern const struct clk_hw_omap_ops clkhwops_wait;
+extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 10/36] clk: ti: add support for basic mux clock
2013-09-25 8:48 ` Tero Kristo
@ 2013-09-25 8:48 ` Tero Kristo
-1 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-omap, paul, tony, nm, rnayak, bcousson, mturquette
Cc: linux-arm-kernel, devicetree
ti,mux-clock provides now a binding for basic mux support. This is just
using the basic clock type.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
Documentation/devicetree/bindings/clock/ti/mux.txt | 65 +++++++++++++++
drivers/clk/ti/Makefile | 2 +-
drivers/clk/ti/mux.c | 83 ++++++++++++++++++++
3 files changed, 149 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/clock/ti/mux.txt
create mode 100644 drivers/clk/ti/mux.c
diff --git a/Documentation/devicetree/bindings/clock/ti/mux.txt b/Documentation/devicetree/bindings/clock/ti/mux.txt
new file mode 100644
index 0000000..5bb5fae
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/mux.txt
@@ -0,0 +1,65 @@
+Binding for TI mux clock.
+
+This binding uses the common clock binding[1]. It assumes a
+register-mapped multiplexer with multiple input clock signals or
+parents, one of which can be selected as output. This clock does not
+gate or adjust the parent rate via a divider or multiplier.
+
+By default the "clocks" property lists the parents in the same order
+as they are programmed into the regster. E.g:
+
+ clocks = <&foo_clock>, <&bar_clock>, <&baz_clock>;
+
+results in programming the register as follows:
+
+register value selected parent clock
+0 foo_clock
+1 bar_clock
+2 baz_clock
+
+Some clock controller IPs do not allow a value of zero to be programmed
+into the register, instead indexing begins at 1. The optional property
+"index-starts-at-one" modified the scheme as follows:
+
+register value selected clock parent
+1 foo_clock
+2 bar_clock
+3 baz_clock
+
+The binding must provide the register to control the mux. Optionally
+the number of bits to shift the control field in the register can be
+supplied. If the shift value is missing it is the same as supplying
+a zero shift.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be "mux-clock".
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : link phandles of parent clocks
+- reg : base address for register controlling adjustable mux
+
+Optional properties:
+- ti,bit-shift : number of bits to shift the bit-mask, defaults to
+ 0 if not present
+- ti,index-starts-at-one : valid input select programming starts at 1, not
+ zero
+- ti,set-rate-parent : clk_set_rate is propagated to parent clock
+
+Examples:
+
+sys_clkin_ck: sys_clkin_ck@4a306110 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
+ reg = <0x4a306110 0x4>;
+ ti,index-starts-at-one;
+};
+
+abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@4a306108 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a306108 0x4>;
+};
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 68d55c9..f0986a5 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,5 +1,5 @@
ifneq ($(CONFIG_OF),)
obj-y += clk.o dpll.o autoidle.o divider.o \
fixed-factor.o gate.o clockdomain.o \
- mux-gate.o
+ mux-gate.o mux.o
endif
diff --git a/drivers/clk/ti/mux.c b/drivers/clk/ti/mux.c
new file mode 100644
index 0000000..ed2aa36
--- /dev/null
+++ b/drivers/clk/ti/mux.c
@@ -0,0 +1,83 @@
+/*
+ * TI Multiplexer Clock
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo <t-kristo@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk/ti.h>
+
+/**
+ * of_mux_clk_setup() - Setup function for simple mux rate clock
+ */
+static void of_mux_clk_setup(struct device_node *node)
+{
+ struct clk *clk;
+ const char *clk_name = node->name;
+ void __iomem *reg;
+ int num_parents;
+ const char **parent_names;
+ int i;
+ u8 clk_mux_flags = 0;
+ u32 mask = 0;
+ u32 shift = 0;
+ u32 flags = 0;
+
+ num_parents = of_clk_get_parent_count(node);
+ if (num_parents < 1) {
+ pr_err("%s: mux-clock %s must have parent(s)\n",
+ __func__, node->name);
+ return;
+ }
+ parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL);
+
+ for (i = 0; i < num_parents; i++)
+ parent_names[i] = of_clk_get_parent_name(node, i);
+
+ reg = of_iomap(node, 0);
+ if (!reg) {
+ pr_err("%s: no memory mapped for property reg\n", __func__);
+ return;
+ }
+
+ if (of_property_read_u32(node, "ti,bit-shift", &shift)) {
+ pr_debug("%s: bit-shift property defaults to 0x%x for %s\n",
+ __func__, shift, node->name);
+ }
+
+ if (of_property_read_bool(node, "ti,index-starts-at-one"))
+ clk_mux_flags |= CLK_MUX_INDEX_ONE;
+
+ if (of_property_read_bool(node, "ti,set-rate-parent"))
+ flags |= CLK_SET_RATE_PARENT;
+
+ /* Generate bit-mask based on parent info */
+ mask = num_parents;
+ if (!(clk_mux_flags & CLK_MUX_INDEX_ONE))
+ mask--;
+
+ mask = (1 << fls(mask)) - 1;
+
+ clk = clk_register_mux_table(NULL, clk_name, parent_names, num_parents,
+ flags, reg, shift, mask, clk_mux_flags,
+ NULL, NULL);
+
+ if (!IS_ERR(clk))
+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
+}
+CLK_OF_DECLARE(mux_clk, "ti,mux-clock", of_mux_clk_setup);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 10/36] clk: ti: add support for basic mux clock
@ 2013-09-25 8:48 ` Tero Kristo
0 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-arm-kernel
ti,mux-clock provides now a binding for basic mux support. This is just
using the basic clock type.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
Documentation/devicetree/bindings/clock/ti/mux.txt | 65 +++++++++++++++
drivers/clk/ti/Makefile | 2 +-
drivers/clk/ti/mux.c | 83 ++++++++++++++++++++
3 files changed, 149 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/clock/ti/mux.txt
create mode 100644 drivers/clk/ti/mux.c
diff --git a/Documentation/devicetree/bindings/clock/ti/mux.txt b/Documentation/devicetree/bindings/clock/ti/mux.txt
new file mode 100644
index 0000000..5bb5fae
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/mux.txt
@@ -0,0 +1,65 @@
+Binding for TI mux clock.
+
+This binding uses the common clock binding[1]. It assumes a
+register-mapped multiplexer with multiple input clock signals or
+parents, one of which can be selected as output. This clock does not
+gate or adjust the parent rate via a divider or multiplier.
+
+By default the "clocks" property lists the parents in the same order
+as they are programmed into the regster. E.g:
+
+ clocks = <&foo_clock>, <&bar_clock>, <&baz_clock>;
+
+results in programming the register as follows:
+
+register value selected parent clock
+0 foo_clock
+1 bar_clock
+2 baz_clock
+
+Some clock controller IPs do not allow a value of zero to be programmed
+into the register, instead indexing begins at 1. The optional property
+"index-starts-at-one" modified the scheme as follows:
+
+register value selected clock parent
+1 foo_clock
+2 bar_clock
+3 baz_clock
+
+The binding must provide the register to control the mux. Optionally
+the number of bits to shift the control field in the register can be
+supplied. If the shift value is missing it is the same as supplying
+a zero shift.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be "mux-clock".
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : link phandles of parent clocks
+- reg : base address for register controlling adjustable mux
+
+Optional properties:
+- ti,bit-shift : number of bits to shift the bit-mask, defaults to
+ 0 if not present
+- ti,index-starts-at-one : valid input select programming starts at 1, not
+ zero
+- ti,set-rate-parent : clk_set_rate is propagated to parent clock
+
+Examples:
+
+sys_clkin_ck: sys_clkin_ck at 4a306110 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
+ reg = <0x4a306110 0x4>;
+ ti,index-starts-at-one;
+};
+
+abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck at 4a306108 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a306108 0x4>;
+};
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 68d55c9..f0986a5 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,5 +1,5 @@
ifneq ($(CONFIG_OF),)
obj-y += clk.o dpll.o autoidle.o divider.o \
fixed-factor.o gate.o clockdomain.o \
- mux-gate.o
+ mux-gate.o mux.o
endif
diff --git a/drivers/clk/ti/mux.c b/drivers/clk/ti/mux.c
new file mode 100644
index 0000000..ed2aa36
--- /dev/null
+++ b/drivers/clk/ti/mux.c
@@ -0,0 +1,83 @@
+/*
+ * TI Multiplexer Clock
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo <t-kristo@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk/ti.h>
+
+/**
+ * of_mux_clk_setup() - Setup function for simple mux rate clock
+ */
+static void of_mux_clk_setup(struct device_node *node)
+{
+ struct clk *clk;
+ const char *clk_name = node->name;
+ void __iomem *reg;
+ int num_parents;
+ const char **parent_names;
+ int i;
+ u8 clk_mux_flags = 0;
+ u32 mask = 0;
+ u32 shift = 0;
+ u32 flags = 0;
+
+ num_parents = of_clk_get_parent_count(node);
+ if (num_parents < 1) {
+ pr_err("%s: mux-clock %s must have parent(s)\n",
+ __func__, node->name);
+ return;
+ }
+ parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL);
+
+ for (i = 0; i < num_parents; i++)
+ parent_names[i] = of_clk_get_parent_name(node, i);
+
+ reg = of_iomap(node, 0);
+ if (!reg) {
+ pr_err("%s: no memory mapped for property reg\n", __func__);
+ return;
+ }
+
+ if (of_property_read_u32(node, "ti,bit-shift", &shift)) {
+ pr_debug("%s: bit-shift property defaults to 0x%x for %s\n",
+ __func__, shift, node->name);
+ }
+
+ if (of_property_read_bool(node, "ti,index-starts-at-one"))
+ clk_mux_flags |= CLK_MUX_INDEX_ONE;
+
+ if (of_property_read_bool(node, "ti,set-rate-parent"))
+ flags |= CLK_SET_RATE_PARENT;
+
+ /* Generate bit-mask based on parent info */
+ mask = num_parents;
+ if (!(clk_mux_flags & CLK_MUX_INDEX_ONE))
+ mask--;
+
+ mask = (1 << fls(mask)) - 1;
+
+ clk = clk_register_mux_table(NULL, clk_name, parent_names, num_parents,
+ flags, reg, shift, mask, clk_mux_flags,
+ NULL, NULL);
+
+ if (!IS_ERR(clk))
+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
+}
+CLK_OF_DECLARE(mux_clk, "ti,mux-clock", of_mux_clk_setup);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 11/36] CLK: TI: add omap4 clock init file
2013-09-25 8:48 ` Tero Kristo
@ 2013-09-25 8:48 ` Tero Kristo
-1 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-omap, paul, tony, nm, rnayak, bcousson, mturquette
Cc: linux-arm-kernel, devicetree
clk-44xx.c now contains the clock init functionality for omap4, including
DT clock registration and adding of static clkdev entries.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/mach-omap2/clock.h | 1 -
drivers/clk/ti/clk-44xx.c | 330 +++++++++++++++++++++++++++++++++++++++++++
include/linux/clk/ti.h | 3 +
3 files changed, 333 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/ti/clk-44xx.c
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 56d4664..106c5c2 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -247,7 +247,6 @@ void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
void __iomem **idlest_reg,
u8 *idlest_bit, u8 *idlest_val);
int omap2_clk_enable_autoidle_all(void);
-int omap2_clk_disable_autoidle_all(void);
void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
diff --git a/drivers/clk/ti/clk-44xx.c b/drivers/clk/ti/clk-44xx.c
new file mode 100644
index 0000000..7723087
--- /dev/null
+++ b/drivers/clk/ti/clk-44xx.c
@@ -0,0 +1,330 @@
+/*
+ * OMAP4 Clock data
+ *
+ * Copyright (C) 2009-2012 Texas Instruments, Inc.
+ * Copyright (C) 2009-2010 Nokia Corporation
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ * Mike Turquette (mturquette@ti.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * XXX Some of the ES1 clocks have been removed/changed; once support
+ * is added for discriminating clocks by ES level, these should be added back
+ * in.
+ *
+ * XXX All of the remaining MODULEMODE clock nodes should be removed
+ * once the drivers are updated to use pm_runtime or to use the appropriate
+ * upstream clock node for rate/parent selection.
+ */
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/clk-private.h>
+#include <linux/clkdev.h>
+#include <linux/clk/ti.h>
+
+/*
+ * OMAP4 ABE DPLL default frequency. In OMAP4460 TRM version V, section
+ * "3.6.3.2.3 CM1_ABE Clock Generator" states that the "DPLL_ABE_X2_CLK
+ * must be set to 196.608 MHz" and hence, the DPLL locked frequency is
+ * half of this value.
+ */
+#define OMAP4_DPLL_ABE_DEFFREQ 98304000
+
+/*
+ * OMAP4 USB DPLL default frequency. In OMAP4430 TRM version V, section
+ * "3.6.3.9.5 DPLL_USB Preferred Settings" shows that the preferred
+ * locked frequency for the USB DPLL is 960MHz.
+ */
+#define OMAP4_DPLL_USB_DEFFREQ 960000000
+
+static struct ti_dt_clk omap44xx_clks[] = {
+ DT_CLK(NULL, "extalt_clkin_ck", "extalt_clkin_ck"),
+ DT_CLK(NULL, "pad_clks_src_ck", "pad_clks_src_ck"),
+ DT_CLK(NULL, "pad_clks_ck", "pad_clks_ck"),
+ DT_CLK(NULL, "pad_slimbus_core_clks_ck", "pad_slimbus_core_clks_ck"),
+ DT_CLK(NULL, "secure_32k_clk_src_ck", "secure_32k_clk_src_ck"),
+ DT_CLK(NULL, "slimbus_src_clk", "slimbus_src_clk"),
+ DT_CLK(NULL, "slimbus_clk", "slimbus_clk"),
+ DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"),
+ DT_CLK(NULL, "virt_12000000_ck", "virt_12000000_ck"),
+ DT_CLK(NULL, "virt_13000000_ck", "virt_13000000_ck"),
+ DT_CLK(NULL, "virt_16800000_ck", "virt_16800000_ck"),
+ DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
+ DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
+ DT_CLK(NULL, "virt_27000000_ck", "virt_27000000_ck"),
+ DT_CLK(NULL, "virt_38400000_ck", "virt_38400000_ck"),
+ DT_CLK(NULL, "sys_clkin_ck", "sys_clkin_ck"),
+ DT_CLK(NULL, "tie_low_clock_ck", "tie_low_clock_ck"),
+ DT_CLK(NULL, "utmi_phy_clkout_ck", "utmi_phy_clkout_ck"),
+ DT_CLK(NULL, "xclk60mhsp1_ck", "xclk60mhsp1_ck"),
+ DT_CLK(NULL, "xclk60mhsp2_ck", "xclk60mhsp2_ck"),
+ DT_CLK(NULL, "xclk60motg_ck", "xclk60motg_ck"),
+ DT_CLK(NULL, "abe_dpll_bypass_clk_mux_ck", "abe_dpll_bypass_clk_mux_ck"),
+ DT_CLK(NULL, "abe_dpll_refclk_mux_ck", "abe_dpll_refclk_mux_ck"),
+ DT_CLK(NULL, "dpll_abe_ck", "dpll_abe_ck"),
+ DT_CLK(NULL, "dpll_abe_x2_ck", "dpll_abe_x2_ck"),
+ DT_CLK(NULL, "dpll_abe_m2x2_ck", "dpll_abe_m2x2_ck"),
+ DT_CLK(NULL, "abe_24m_fclk", "abe_24m_fclk"),
+ DT_CLK(NULL, "abe_clk", "abe_clk"),
+ DT_CLK(NULL, "aess_fclk", "aess_fclk"),
+ DT_CLK(NULL, "dpll_abe_m3x2_ck", "dpll_abe_m3x2_ck"),
+ DT_CLK(NULL, "core_hsd_byp_clk_mux_ck", "core_hsd_byp_clk_mux_ck"),
+ DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
+ DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
+ DT_CLK(NULL, "dpll_core_m6x2_ck", "dpll_core_m6x2_ck"),
+ DT_CLK(NULL, "dbgclk_mux_ck", "dbgclk_mux_ck"),
+ DT_CLK(NULL, "dpll_core_m2_ck", "dpll_core_m2_ck"),
+ DT_CLK(NULL, "ddrphy_ck", "ddrphy_ck"),
+ DT_CLK(NULL, "dpll_core_m5x2_ck", "dpll_core_m5x2_ck"),
+ DT_CLK(NULL, "div_core_ck", "div_core_ck"),
+ DT_CLK(NULL, "div_iva_hs_clk", "div_iva_hs_clk"),
+ DT_CLK(NULL, "div_mpu_hs_clk", "div_mpu_hs_clk"),
+ DT_CLK(NULL, "dpll_core_m4x2_ck", "dpll_core_m4x2_ck"),
+ DT_CLK(NULL, "dll_clk_div_ck", "dll_clk_div_ck"),
+ DT_CLK(NULL, "dpll_abe_m2_ck", "dpll_abe_m2_ck"),
+ DT_CLK(NULL, "dpll_core_m3x2_ck", "dpll_core_m3x2_ck"),
+ DT_CLK(NULL, "dpll_core_m7x2_ck", "dpll_core_m7x2_ck"),
+ DT_CLK(NULL, "iva_hsd_byp_clk_mux_ck", "iva_hsd_byp_clk_mux_ck"),
+ DT_CLK(NULL, "dpll_iva_ck", "dpll_iva_ck"),
+ DT_CLK(NULL, "dpll_iva_x2_ck", "dpll_iva_x2_ck"),
+ DT_CLK(NULL, "dpll_iva_m4x2_ck", "dpll_iva_m4x2_ck"),
+ DT_CLK(NULL, "dpll_iva_m5x2_ck", "dpll_iva_m5x2_ck"),
+ DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"),
+ DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"),
+ DT_CLK(NULL, "per_hs_clk_div_ck", "per_hs_clk_div_ck"),
+ DT_CLK(NULL, "per_hsd_byp_clk_mux_ck", "per_hsd_byp_clk_mux_ck"),
+ DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"),
+ DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"),
+ DT_CLK(NULL, "dpll_per_x2_ck", "dpll_per_x2_ck"),
+ DT_CLK(NULL, "dpll_per_m2x2_ck", "dpll_per_m2x2_ck"),
+ DT_CLK(NULL, "dpll_per_m3x2_ck", "dpll_per_m3x2_ck"),
+ DT_CLK(NULL, "dpll_per_m4x2_ck", "dpll_per_m4x2_ck"),
+ DT_CLK(NULL, "dpll_per_m5x2_ck", "dpll_per_m5x2_ck"),
+ DT_CLK(NULL, "dpll_per_m6x2_ck", "dpll_per_m6x2_ck"),
+ DT_CLK(NULL, "dpll_per_m7x2_ck", "dpll_per_m7x2_ck"),
+ DT_CLK(NULL, "usb_hs_clk_div_ck", "usb_hs_clk_div_ck"),
+ DT_CLK(NULL, "dpll_usb_ck", "dpll_usb_ck"),
+ DT_CLK(NULL, "dpll_usb_clkdcoldo_ck", "dpll_usb_clkdcoldo_ck"),
+ DT_CLK(NULL, "dpll_usb_m2_ck", "dpll_usb_m2_ck"),
+ DT_CLK(NULL, "ducati_clk_mux_ck", "ducati_clk_mux_ck"),
+ DT_CLK(NULL, "func_12m_fclk", "func_12m_fclk"),
+ DT_CLK(NULL, "func_24m_clk", "func_24m_clk"),
+ DT_CLK(NULL, "func_24mc_fclk", "func_24mc_fclk"),
+ DT_CLK(NULL, "func_48m_fclk", "func_48m_fclk"),
+ DT_CLK(NULL, "func_48mc_fclk", "func_48mc_fclk"),
+ DT_CLK(NULL, "func_64m_fclk", "func_64m_fclk"),
+ DT_CLK(NULL, "func_96m_fclk", "func_96m_fclk"),
+ DT_CLK(NULL, "init_60m_fclk", "init_60m_fclk"),
+ DT_CLK(NULL, "l3_div_ck", "l3_div_ck"),
+ DT_CLK(NULL, "l4_div_ck", "l4_div_ck"),
+ DT_CLK(NULL, "lp_clk_div_ck", "lp_clk_div_ck"),
+ DT_CLK(NULL, "l4_wkup_clk_mux_ck", "l4_wkup_clk_mux_ck"),
+ DT_CLK("smp_twd", NULL, "mpu_periphclk"),
+ DT_CLK(NULL, "ocp_abe_iclk", "ocp_abe_iclk"),
+ DT_CLK(NULL, "per_abe_24m_fclk", "per_abe_24m_fclk"),
+ DT_CLK(NULL, "per_abe_nc_fclk", "per_abe_nc_fclk"),
+ DT_CLK(NULL, "syc_clk_div_ck", "syc_clk_div_ck"),
+ DT_CLK(NULL, "aes1_fck", "aes1_fck"),
+ DT_CLK(NULL, "aes2_fck", "aes2_fck"),
+ DT_CLK(NULL, "dmic_sync_mux_ck", "dmic_sync_mux_ck"),
+ DT_CLK(NULL, "func_dmic_abe_gfclk", "func_dmic_abe_gfclk"),
+ DT_CLK(NULL, "dss_sys_clk", "dss_sys_clk"),
+ DT_CLK(NULL, "dss_tv_clk", "dss_tv_clk"),
+ DT_CLK(NULL, "dss_dss_clk", "dss_dss_clk"),
+ DT_CLK(NULL, "dss_48mhz_clk", "dss_48mhz_clk"),
+ DT_CLK(NULL, "dss_fck", "dss_fck"),
+ DT_CLK("omapdss_dss", "ick", "dss_fck"),
+ DT_CLK(NULL, "fdif_fck", "fdif_fck"),
+ DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
+ DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"),
+ DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"),
+ DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"),
+ DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"),
+ DT_CLK(NULL, "gpio6_dbclk", "gpio6_dbclk"),
+ DT_CLK(NULL, "sgx_clk_mux", "sgx_clk_mux"),
+ DT_CLK(NULL, "hsi_fck", "hsi_fck"),
+ DT_CLK(NULL, "iss_ctrlclk", "iss_ctrlclk"),
+ DT_CLK(NULL, "mcasp_sync_mux_ck", "mcasp_sync_mux_ck"),
+ DT_CLK(NULL, "func_mcasp_abe_gfclk", "func_mcasp_abe_gfclk"),
+ DT_CLK(NULL, "mcbsp1_sync_mux_ck", "mcbsp1_sync_mux_ck"),
+ DT_CLK(NULL, "func_mcbsp1_gfclk", "func_mcbsp1_gfclk"),
+ DT_CLK(NULL, "mcbsp2_sync_mux_ck", "mcbsp2_sync_mux_ck"),
+ DT_CLK(NULL, "func_mcbsp2_gfclk", "func_mcbsp2_gfclk"),
+ DT_CLK(NULL, "mcbsp3_sync_mux_ck", "mcbsp3_sync_mux_ck"),
+ DT_CLK(NULL, "func_mcbsp3_gfclk", "func_mcbsp3_gfclk"),
+ DT_CLK(NULL, "mcbsp4_sync_mux_ck", "mcbsp4_sync_mux_ck"),
+ DT_CLK(NULL, "per_mcbsp4_gfclk", "per_mcbsp4_gfclk"),
+ DT_CLK(NULL, "hsmmc1_fclk", "hsmmc1_fclk"),
+ DT_CLK(NULL, "hsmmc2_fclk", "hsmmc2_fclk"),
+ DT_CLK(NULL, "ocp2scp_usb_phy_phy_48m", "ocp2scp_usb_phy_phy_48m"),
+ DT_CLK(NULL, "sha2md5_fck", "sha2md5_fck"),
+ DT_CLK(NULL, "slimbus1_fclk_1", "slimbus1_fclk_1"),
+ DT_CLK(NULL, "slimbus1_fclk_0", "slimbus1_fclk_0"),
+ DT_CLK(NULL, "slimbus1_fclk_2", "slimbus1_fclk_2"),
+ DT_CLK(NULL, "slimbus1_slimbus_clk", "slimbus1_slimbus_clk"),
+ DT_CLK(NULL, "slimbus2_fclk_1", "slimbus2_fclk_1"),
+ DT_CLK(NULL, "slimbus2_fclk_0", "slimbus2_fclk_0"),
+ DT_CLK(NULL, "slimbus2_slimbus_clk", "slimbus2_slimbus_clk"),
+ DT_CLK(NULL, "smartreflex_core_fck", "smartreflex_core_fck"),
+ DT_CLK(NULL, "smartreflex_iva_fck", "smartreflex_iva_fck"),
+ DT_CLK(NULL, "smartreflex_mpu_fck", "smartreflex_mpu_fck"),
+ DT_CLK(NULL, "dmt1_clk_mux", "dmt1_clk_mux"),
+ DT_CLK(NULL, "cm2_dm10_mux", "cm2_dm10_mux"),
+ DT_CLK(NULL, "cm2_dm11_mux", "cm2_dm11_mux"),
+ DT_CLK(NULL, "cm2_dm2_mux", "cm2_dm2_mux"),
+ DT_CLK(NULL, "cm2_dm3_mux", "cm2_dm3_mux"),
+ DT_CLK(NULL, "cm2_dm4_mux", "cm2_dm4_mux"),
+ DT_CLK(NULL, "timer5_sync_mux", "timer5_sync_mux"),
+ DT_CLK(NULL, "timer6_sync_mux", "timer6_sync_mux"),
+ DT_CLK(NULL, "timer7_sync_mux", "timer7_sync_mux"),
+ DT_CLK(NULL, "timer8_sync_mux", "timer8_sync_mux"),
+ DT_CLK(NULL, "cm2_dm9_mux", "cm2_dm9_mux"),
+ DT_CLK(NULL, "usb_host_fs_fck", "usb_host_fs_fck"),
+ DT_CLK("usbhs_omap", "fs_fck", "usb_host_fs_fck"),
+ DT_CLK(NULL, "utmi_p1_gfclk", "utmi_p1_gfclk"),
+ DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "usb_host_hs_utmi_p1_clk"),
+ DT_CLK(NULL, "utmi_p2_gfclk", "utmi_p2_gfclk"),
+ DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "usb_host_hs_utmi_p2_clk"),
+ DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "usb_host_hs_utmi_p3_clk"),
+ DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "usb_host_hs_hsic480m_p1_clk"),
+ DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "usb_host_hs_hsic60m_p1_clk"),
+ DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "usb_host_hs_hsic60m_p2_clk"),
+ DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "usb_host_hs_hsic480m_p2_clk"),
+ DT_CLK(NULL, "usb_host_hs_func48mclk", "usb_host_hs_func48mclk"),
+ DT_CLK(NULL, "usb_host_hs_fck", "usb_host_hs_fck"),
+ DT_CLK("usbhs_omap", "hs_fck", "usb_host_hs_fck"),
+ DT_CLK(NULL, "otg_60m_gfclk", "otg_60m_gfclk"),
+ DT_CLK(NULL, "usb_otg_hs_xclk", "usb_otg_hs_xclk"),
+ DT_CLK(NULL, "usb_otg_hs_ick", "usb_otg_hs_ick"),
+ DT_CLK("musb-omap2430", "ick", "usb_otg_hs_ick"),
+ DT_CLK(NULL, "usb_phy_cm_clk32k", "usb_phy_cm_clk32k"),
+ DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "usb_tll_hs_usb_ch2_clk"),
+ DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "usb_tll_hs_usb_ch0_clk"),
+ DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "usb_tll_hs_usb_ch1_clk"),
+ DT_CLK(NULL, "usb_tll_hs_ick", "usb_tll_hs_ick"),
+ DT_CLK("usbhs_omap", "usbtll_ick", "usb_tll_hs_ick"),
+ DT_CLK("usbhs_tll", "usbtll_ick", "usb_tll_hs_ick"),
+ DT_CLK(NULL, "usim_ck", "usim_ck"),
+ DT_CLK(NULL, "usim_fclk", "usim_fclk"),
+ DT_CLK(NULL, "pmd_stm_clock_mux_ck", "pmd_stm_clock_mux_ck"),
+ DT_CLK(NULL, "pmd_trace_clk_mux_ck", "pmd_trace_clk_mux_ck"),
+ DT_CLK(NULL, "stm_clk_div_ck", "stm_clk_div_ck"),
+ DT_CLK(NULL, "trace_clk_div_ck", "trace_clk_div_ck"),
+ DT_CLK(NULL, "auxclk0_src_ck", "auxclk0_src_ck"),
+ DT_CLK(NULL, "auxclk0_ck", "auxclk0_ck"),
+ DT_CLK(NULL, "auxclkreq0_ck", "auxclkreq0_ck"),
+ DT_CLK(NULL, "auxclk1_src_ck", "auxclk1_src_ck"),
+ DT_CLK(NULL, "auxclk1_ck", "auxclk1_ck"),
+ DT_CLK(NULL, "auxclkreq1_ck", "auxclkreq1_ck"),
+ DT_CLK(NULL, "auxclk2_src_ck", "auxclk2_src_ck"),
+ DT_CLK(NULL, "auxclk2_ck", "auxclk2_ck"),
+ DT_CLK(NULL, "auxclkreq2_ck", "auxclkreq2_ck"),
+ DT_CLK(NULL, "auxclk3_src_ck", "auxclk3_src_ck"),
+ DT_CLK(NULL, "auxclk3_ck", "auxclk3_ck"),
+ DT_CLK(NULL, "auxclkreq3_ck", "auxclkreq3_ck"),
+ DT_CLK(NULL, "auxclk4_src_ck", "auxclk4_src_ck"),
+ DT_CLK(NULL, "auxclk4_ck", "auxclk4_ck"),
+ DT_CLK(NULL, "auxclkreq4_ck", "auxclkreq4_ck"),
+ DT_CLK(NULL, "auxclk5_src_ck", "auxclk5_src_ck"),
+ DT_CLK(NULL, "auxclk5_ck", "auxclk5_ck"),
+ DT_CLK(NULL, "auxclkreq5_ck", "auxclkreq5_ck"),
+ DT_CLK("50000000.gpmc", "fck", "dummy_ck"),
+ DT_CLK("omap_i2c.1", "ick", "dummy_ck"),
+ DT_CLK("omap_i2c.2", "ick", "dummy_ck"),
+ DT_CLK("omap_i2c.3", "ick", "dummy_ck"),
+ DT_CLK("omap_i2c.4", "ick", "dummy_ck"),
+ DT_CLK(NULL, "mailboxes_ick", "dummy_ck"),
+ DT_CLK("omap_hsmmc.0", "ick", "dummy_ck"),
+ DT_CLK("omap_hsmmc.1", "ick", "dummy_ck"),
+ DT_CLK("omap_hsmmc.2", "ick", "dummy_ck"),
+ DT_CLK("omap_hsmmc.3", "ick", "dummy_ck"),
+ DT_CLK("omap_hsmmc.4", "ick", "dummy_ck"),
+ DT_CLK("omap-mcbsp.1", "ick", "dummy_ck"),
+ DT_CLK("omap-mcbsp.2", "ick", "dummy_ck"),
+ DT_CLK("omap-mcbsp.3", "ick", "dummy_ck"),
+ DT_CLK("omap-mcbsp.4", "ick", "dummy_ck"),
+ DT_CLK("omap2_mcspi.1", "ick", "dummy_ck"),
+ DT_CLK("omap2_mcspi.2", "ick", "dummy_ck"),
+ DT_CLK("omap2_mcspi.3", "ick", "dummy_ck"),
+ DT_CLK("omap2_mcspi.4", "ick", "dummy_ck"),
+ DT_CLK(NULL, "uart1_ick", "dummy_ck"),
+ DT_CLK(NULL, "uart2_ick", "dummy_ck"),
+ DT_CLK(NULL, "uart3_ick", "dummy_ck"),
+ DT_CLK(NULL, "uart4_ick", "dummy_ck"),
+ DT_CLK("usbhs_omap", "usbhost_ick", "dummy_ck"),
+ DT_CLK("usbhs_omap", "usbtll_fck", "dummy_ck"),
+ DT_CLK("usbhs_tll", "usbtll_fck", "dummy_ck"),
+ DT_CLK("omap_wdt", "ick", "dummy_ck"),
+ DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
+ DT_CLK("omap_timer.1", "timer_sys_ck", "sys_clkin_ck"),
+ DT_CLK("omap_timer.2", "timer_sys_ck", "sys_clkin_ck"),
+ DT_CLK("omap_timer.3", "timer_sys_ck", "sys_clkin_ck"),
+ DT_CLK("omap_timer.4", "timer_sys_ck", "sys_clkin_ck"),
+ DT_CLK("omap_timer.9", "timer_sys_ck", "sys_clkin_ck"),
+ DT_CLK("omap_timer.10", "timer_sys_ck", "sys_clkin_ck"),
+ DT_CLK("omap_timer.11", "timer_sys_ck", "sys_clkin_ck"),
+ DT_CLK("omap_timer.5", "timer_sys_ck", "syc_clk_div_ck"),
+ DT_CLK("omap_timer.6", "timer_sys_ck", "syc_clk_div_ck"),
+ DT_CLK("omap_timer.7", "timer_sys_ck", "syc_clk_div_ck"),
+ DT_CLK("omap_timer.8", "timer_sys_ck", "syc_clk_div_ck"),
+ DT_CLK("4a318000.timer", "timer_sys_ck", "sys_clkin_ck"),
+ DT_CLK("48032000.timer", "timer_sys_ck", "sys_clkin_ck"),
+ DT_CLK("48034000.timer", "timer_sys_ck", "sys_clkin_ck"),
+ DT_CLK("48036000.timer", "timer_sys_ck", "sys_clkin_ck"),
+ DT_CLK("4803e000.timer", "timer_sys_ck", "sys_clkin_ck"),
+ DT_CLK("48086000.timer", "timer_sys_ck", "sys_clkin_ck"),
+ DT_CLK("48088000.timer", "timer_sys_ck", "sys_clkin_ck"),
+ DT_CLK("40138000.timer", "timer_sys_ck", "syc_clk_div_ck"),
+ DT_CLK("4013a000.timer", "timer_sys_ck", "syc_clk_div_ck"),
+ DT_CLK("4013c000.timer", "timer_sys_ck", "syc_clk_div_ck"),
+ DT_CLK("4013e000.timer", "timer_sys_ck", "syc_clk_div_ck"),
+ DT_CLK(NULL, "cpufreq_ck", "dpll_mpu_ck"),
+ DT_CLK(NULL, "bandgap_fclk", "bandgap_fclk"),
+ DT_CLK(NULL, "div_ts_ck", "div_ts_ck"),
+ DT_CLK(NULL, "bandgap_ts_fclk", "bandgap_ts_fclk"),
+ { .node_name = NULL },
+};
+
+int __init omap4xxx_clk_init(void)
+{
+ int rc;
+ struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll;
+
+ of_clk_init(NULL);
+
+ ti_dt_clocks_register(omap44xx_clks);
+
+ omap2_clk_disable_autoidle_all();
+
+ /*
+ * Lock USB DPLL on OMAP4 devices so that the L3INIT power
+ * domain can transition to retention state when not in use.
+ */
+ usb_dpll = clk_get_sys(NULL, "dpll_usb_ck");
+ rc = clk_set_rate(usb_dpll, OMAP4_DPLL_USB_DEFFREQ);
+ if (rc)
+ pr_err("%s: failed to configure USB DPLL!\n", __func__);
+
+ /*
+ * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power
+ * state when turning the ABE clock domain. Workaround this by
+ * locking the ABE DPLL on boot.
+ * Lock the ABE DPLL in any case to avoid issues with audio.
+ */
+ abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_refclk_mux_ck");
+ sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
+ rc = clk_set_parent(abe_dpll_ref, sys_32k_ck);
+ abe_dpll = clk_get_sys(NULL, "dpll_abe_ck");
+ if (!rc)
+ rc = clk_set_rate(abe_dpll, OMAP4_DPLL_ABE_DEFFREQ);
+ if (rc)
+ pr_err("%s: failed to configure ABE DPLL!\n", __func__);
+
+ return 0;
+}
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index ed4b36e..c9a18b9 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -207,6 +207,7 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
unsigned long parent_rate);
int omap2_clkops_enable_clkdm(struct clk_hw *hw);
void omap2_clkops_disable_clkdm(struct clk_hw *hw);
+int omap2_clk_disable_autoidle_all(void);
int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
unsigned long parent_rate);
int omap2_dflt_clk_enable(struct clk_hw *hw);
@@ -218,6 +219,8 @@ void of_ti_autoidle_setup(struct device_node *node);
struct clk_div_table *ti_clk_get_div_table(struct device_node *node);
+int omap4xxx_clk_init(void);
+
#ifdef CONFIG_OF
void of_ti_clk_allow_autoidle_all(void);
void of_ti_clk_deny_autoidle_all(void);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 11/36] CLK: TI: add omap4 clock init file
@ 2013-09-25 8:48 ` Tero Kristo
0 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-arm-kernel
clk-44xx.c now contains the clock init functionality for omap4, including
DT clock registration and adding of static clkdev entries.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/mach-omap2/clock.h | 1 -
drivers/clk/ti/clk-44xx.c | 330 +++++++++++++++++++++++++++++++++++++++++++
include/linux/clk/ti.h | 3 +
3 files changed, 333 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/ti/clk-44xx.c
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 56d4664..106c5c2 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -247,7 +247,6 @@ void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
void __iomem **idlest_reg,
u8 *idlest_bit, u8 *idlest_val);
int omap2_clk_enable_autoidle_all(void);
-int omap2_clk_disable_autoidle_all(void);
void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
diff --git a/drivers/clk/ti/clk-44xx.c b/drivers/clk/ti/clk-44xx.c
new file mode 100644
index 0000000..7723087
--- /dev/null
+++ b/drivers/clk/ti/clk-44xx.c
@@ -0,0 +1,330 @@
+/*
+ * OMAP4 Clock data
+ *
+ * Copyright (C) 2009-2012 Texas Instruments, Inc.
+ * Copyright (C) 2009-2010 Nokia Corporation
+ *
+ * Paul Walmsley (paul at pwsan.com)
+ * Rajendra Nayak (rnayak at ti.com)
+ * Benoit Cousson (b-cousson at ti.com)
+ * Mike Turquette (mturquette at ti.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * XXX Some of the ES1 clocks have been removed/changed; once support
+ * is added for discriminating clocks by ES level, these should be added back
+ * in.
+ *
+ * XXX All of the remaining MODULEMODE clock nodes should be removed
+ * once the drivers are updated to use pm_runtime or to use the appropriate
+ * upstream clock node for rate/parent selection.
+ */
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/clk-private.h>
+#include <linux/clkdev.h>
+#include <linux/clk/ti.h>
+
+/*
+ * OMAP4 ABE DPLL default frequency. In OMAP4460 TRM version V, section
+ * "3.6.3.2.3 CM1_ABE Clock Generator" states that the "DPLL_ABE_X2_CLK
+ * must be set to 196.608 MHz" and hence, the DPLL locked frequency is
+ * half of this value.
+ */
+#define OMAP4_DPLL_ABE_DEFFREQ 98304000
+
+/*
+ * OMAP4 USB DPLL default frequency. In OMAP4430 TRM version V, section
+ * "3.6.3.9.5 DPLL_USB Preferred Settings" shows that the preferred
+ * locked frequency for the USB DPLL is 960MHz.
+ */
+#define OMAP4_DPLL_USB_DEFFREQ 960000000
+
+static struct ti_dt_clk omap44xx_clks[] = {
+ DT_CLK(NULL, "extalt_clkin_ck", "extalt_clkin_ck"),
+ DT_CLK(NULL, "pad_clks_src_ck", "pad_clks_src_ck"),
+ DT_CLK(NULL, "pad_clks_ck", "pad_clks_ck"),
+ DT_CLK(NULL, "pad_slimbus_core_clks_ck", "pad_slimbus_core_clks_ck"),
+ DT_CLK(NULL, "secure_32k_clk_src_ck", "secure_32k_clk_src_ck"),
+ DT_CLK(NULL, "slimbus_src_clk", "slimbus_src_clk"),
+ DT_CLK(NULL, "slimbus_clk", "slimbus_clk"),
+ DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"),
+ DT_CLK(NULL, "virt_12000000_ck", "virt_12000000_ck"),
+ DT_CLK(NULL, "virt_13000000_ck", "virt_13000000_ck"),
+ DT_CLK(NULL, "virt_16800000_ck", "virt_16800000_ck"),
+ DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
+ DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
+ DT_CLK(NULL, "virt_27000000_ck", "virt_27000000_ck"),
+ DT_CLK(NULL, "virt_38400000_ck", "virt_38400000_ck"),
+ DT_CLK(NULL, "sys_clkin_ck", "sys_clkin_ck"),
+ DT_CLK(NULL, "tie_low_clock_ck", "tie_low_clock_ck"),
+ DT_CLK(NULL, "utmi_phy_clkout_ck", "utmi_phy_clkout_ck"),
+ DT_CLK(NULL, "xclk60mhsp1_ck", "xclk60mhsp1_ck"),
+ DT_CLK(NULL, "xclk60mhsp2_ck", "xclk60mhsp2_ck"),
+ DT_CLK(NULL, "xclk60motg_ck", "xclk60motg_ck"),
+ DT_CLK(NULL, "abe_dpll_bypass_clk_mux_ck", "abe_dpll_bypass_clk_mux_ck"),
+ DT_CLK(NULL, "abe_dpll_refclk_mux_ck", "abe_dpll_refclk_mux_ck"),
+ DT_CLK(NULL, "dpll_abe_ck", "dpll_abe_ck"),
+ DT_CLK(NULL, "dpll_abe_x2_ck", "dpll_abe_x2_ck"),
+ DT_CLK(NULL, "dpll_abe_m2x2_ck", "dpll_abe_m2x2_ck"),
+ DT_CLK(NULL, "abe_24m_fclk", "abe_24m_fclk"),
+ DT_CLK(NULL, "abe_clk", "abe_clk"),
+ DT_CLK(NULL, "aess_fclk", "aess_fclk"),
+ DT_CLK(NULL, "dpll_abe_m3x2_ck", "dpll_abe_m3x2_ck"),
+ DT_CLK(NULL, "core_hsd_byp_clk_mux_ck", "core_hsd_byp_clk_mux_ck"),
+ DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
+ DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
+ DT_CLK(NULL, "dpll_core_m6x2_ck", "dpll_core_m6x2_ck"),
+ DT_CLK(NULL, "dbgclk_mux_ck", "dbgclk_mux_ck"),
+ DT_CLK(NULL, "dpll_core_m2_ck", "dpll_core_m2_ck"),
+ DT_CLK(NULL, "ddrphy_ck", "ddrphy_ck"),
+ DT_CLK(NULL, "dpll_core_m5x2_ck", "dpll_core_m5x2_ck"),
+ DT_CLK(NULL, "div_core_ck", "div_core_ck"),
+ DT_CLK(NULL, "div_iva_hs_clk", "div_iva_hs_clk"),
+ DT_CLK(NULL, "div_mpu_hs_clk", "div_mpu_hs_clk"),
+ DT_CLK(NULL, "dpll_core_m4x2_ck", "dpll_core_m4x2_ck"),
+ DT_CLK(NULL, "dll_clk_div_ck", "dll_clk_div_ck"),
+ DT_CLK(NULL, "dpll_abe_m2_ck", "dpll_abe_m2_ck"),
+ DT_CLK(NULL, "dpll_core_m3x2_ck", "dpll_core_m3x2_ck"),
+ DT_CLK(NULL, "dpll_core_m7x2_ck", "dpll_core_m7x2_ck"),
+ DT_CLK(NULL, "iva_hsd_byp_clk_mux_ck", "iva_hsd_byp_clk_mux_ck"),
+ DT_CLK(NULL, "dpll_iva_ck", "dpll_iva_ck"),
+ DT_CLK(NULL, "dpll_iva_x2_ck", "dpll_iva_x2_ck"),
+ DT_CLK(NULL, "dpll_iva_m4x2_ck", "dpll_iva_m4x2_ck"),
+ DT_CLK(NULL, "dpll_iva_m5x2_ck", "dpll_iva_m5x2_ck"),
+ DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"),
+ DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"),
+ DT_CLK(NULL, "per_hs_clk_div_ck", "per_hs_clk_div_ck"),
+ DT_CLK(NULL, "per_hsd_byp_clk_mux_ck", "per_hsd_byp_clk_mux_ck"),
+ DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"),
+ DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"),
+ DT_CLK(NULL, "dpll_per_x2_ck", "dpll_per_x2_ck"),
+ DT_CLK(NULL, "dpll_per_m2x2_ck", "dpll_per_m2x2_ck"),
+ DT_CLK(NULL, "dpll_per_m3x2_ck", "dpll_per_m3x2_ck"),
+ DT_CLK(NULL, "dpll_per_m4x2_ck", "dpll_per_m4x2_ck"),
+ DT_CLK(NULL, "dpll_per_m5x2_ck", "dpll_per_m5x2_ck"),
+ DT_CLK(NULL, "dpll_per_m6x2_ck", "dpll_per_m6x2_ck"),
+ DT_CLK(NULL, "dpll_per_m7x2_ck", "dpll_per_m7x2_ck"),
+ DT_CLK(NULL, "usb_hs_clk_div_ck", "usb_hs_clk_div_ck"),
+ DT_CLK(NULL, "dpll_usb_ck", "dpll_usb_ck"),
+ DT_CLK(NULL, "dpll_usb_clkdcoldo_ck", "dpll_usb_clkdcoldo_ck"),
+ DT_CLK(NULL, "dpll_usb_m2_ck", "dpll_usb_m2_ck"),
+ DT_CLK(NULL, "ducati_clk_mux_ck", "ducati_clk_mux_ck"),
+ DT_CLK(NULL, "func_12m_fclk", "func_12m_fclk"),
+ DT_CLK(NULL, "func_24m_clk", "func_24m_clk"),
+ DT_CLK(NULL, "func_24mc_fclk", "func_24mc_fclk"),
+ DT_CLK(NULL, "func_48m_fclk", "func_48m_fclk"),
+ DT_CLK(NULL, "func_48mc_fclk", "func_48mc_fclk"),
+ DT_CLK(NULL, "func_64m_fclk", "func_64m_fclk"),
+ DT_CLK(NULL, "func_96m_fclk", "func_96m_fclk"),
+ DT_CLK(NULL, "init_60m_fclk", "init_60m_fclk"),
+ DT_CLK(NULL, "l3_div_ck", "l3_div_ck"),
+ DT_CLK(NULL, "l4_div_ck", "l4_div_ck"),
+ DT_CLK(NULL, "lp_clk_div_ck", "lp_clk_div_ck"),
+ DT_CLK(NULL, "l4_wkup_clk_mux_ck", "l4_wkup_clk_mux_ck"),
+ DT_CLK("smp_twd", NULL, "mpu_periphclk"),
+ DT_CLK(NULL, "ocp_abe_iclk", "ocp_abe_iclk"),
+ DT_CLK(NULL, "per_abe_24m_fclk", "per_abe_24m_fclk"),
+ DT_CLK(NULL, "per_abe_nc_fclk", "per_abe_nc_fclk"),
+ DT_CLK(NULL, "syc_clk_div_ck", "syc_clk_div_ck"),
+ DT_CLK(NULL, "aes1_fck", "aes1_fck"),
+ DT_CLK(NULL, "aes2_fck", "aes2_fck"),
+ DT_CLK(NULL, "dmic_sync_mux_ck", "dmic_sync_mux_ck"),
+ DT_CLK(NULL, "func_dmic_abe_gfclk", "func_dmic_abe_gfclk"),
+ DT_CLK(NULL, "dss_sys_clk", "dss_sys_clk"),
+ DT_CLK(NULL, "dss_tv_clk", "dss_tv_clk"),
+ DT_CLK(NULL, "dss_dss_clk", "dss_dss_clk"),
+ DT_CLK(NULL, "dss_48mhz_clk", "dss_48mhz_clk"),
+ DT_CLK(NULL, "dss_fck", "dss_fck"),
+ DT_CLK("omapdss_dss", "ick", "dss_fck"),
+ DT_CLK(NULL, "fdif_fck", "fdif_fck"),
+ DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
+ DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"),
+ DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"),
+ DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"),
+ DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"),
+ DT_CLK(NULL, "gpio6_dbclk", "gpio6_dbclk"),
+ DT_CLK(NULL, "sgx_clk_mux", "sgx_clk_mux"),
+ DT_CLK(NULL, "hsi_fck", "hsi_fck"),
+ DT_CLK(NULL, "iss_ctrlclk", "iss_ctrlclk"),
+ DT_CLK(NULL, "mcasp_sync_mux_ck", "mcasp_sync_mux_ck"),
+ DT_CLK(NULL, "func_mcasp_abe_gfclk", "func_mcasp_abe_gfclk"),
+ DT_CLK(NULL, "mcbsp1_sync_mux_ck", "mcbsp1_sync_mux_ck"),
+ DT_CLK(NULL, "func_mcbsp1_gfclk", "func_mcbsp1_gfclk"),
+ DT_CLK(NULL, "mcbsp2_sync_mux_ck", "mcbsp2_sync_mux_ck"),
+ DT_CLK(NULL, "func_mcbsp2_gfclk", "func_mcbsp2_gfclk"),
+ DT_CLK(NULL, "mcbsp3_sync_mux_ck", "mcbsp3_sync_mux_ck"),
+ DT_CLK(NULL, "func_mcbsp3_gfclk", "func_mcbsp3_gfclk"),
+ DT_CLK(NULL, "mcbsp4_sync_mux_ck", "mcbsp4_sync_mux_ck"),
+ DT_CLK(NULL, "per_mcbsp4_gfclk", "per_mcbsp4_gfclk"),
+ DT_CLK(NULL, "hsmmc1_fclk", "hsmmc1_fclk"),
+ DT_CLK(NULL, "hsmmc2_fclk", "hsmmc2_fclk"),
+ DT_CLK(NULL, "ocp2scp_usb_phy_phy_48m", "ocp2scp_usb_phy_phy_48m"),
+ DT_CLK(NULL, "sha2md5_fck", "sha2md5_fck"),
+ DT_CLK(NULL, "slimbus1_fclk_1", "slimbus1_fclk_1"),
+ DT_CLK(NULL, "slimbus1_fclk_0", "slimbus1_fclk_0"),
+ DT_CLK(NULL, "slimbus1_fclk_2", "slimbus1_fclk_2"),
+ DT_CLK(NULL, "slimbus1_slimbus_clk", "slimbus1_slimbus_clk"),
+ DT_CLK(NULL, "slimbus2_fclk_1", "slimbus2_fclk_1"),
+ DT_CLK(NULL, "slimbus2_fclk_0", "slimbus2_fclk_0"),
+ DT_CLK(NULL, "slimbus2_slimbus_clk", "slimbus2_slimbus_clk"),
+ DT_CLK(NULL, "smartreflex_core_fck", "smartreflex_core_fck"),
+ DT_CLK(NULL, "smartreflex_iva_fck", "smartreflex_iva_fck"),
+ DT_CLK(NULL, "smartreflex_mpu_fck", "smartreflex_mpu_fck"),
+ DT_CLK(NULL, "dmt1_clk_mux", "dmt1_clk_mux"),
+ DT_CLK(NULL, "cm2_dm10_mux", "cm2_dm10_mux"),
+ DT_CLK(NULL, "cm2_dm11_mux", "cm2_dm11_mux"),
+ DT_CLK(NULL, "cm2_dm2_mux", "cm2_dm2_mux"),
+ DT_CLK(NULL, "cm2_dm3_mux", "cm2_dm3_mux"),
+ DT_CLK(NULL, "cm2_dm4_mux", "cm2_dm4_mux"),
+ DT_CLK(NULL, "timer5_sync_mux", "timer5_sync_mux"),
+ DT_CLK(NULL, "timer6_sync_mux", "timer6_sync_mux"),
+ DT_CLK(NULL, "timer7_sync_mux", "timer7_sync_mux"),
+ DT_CLK(NULL, "timer8_sync_mux", "timer8_sync_mux"),
+ DT_CLK(NULL, "cm2_dm9_mux", "cm2_dm9_mux"),
+ DT_CLK(NULL, "usb_host_fs_fck", "usb_host_fs_fck"),
+ DT_CLK("usbhs_omap", "fs_fck", "usb_host_fs_fck"),
+ DT_CLK(NULL, "utmi_p1_gfclk", "utmi_p1_gfclk"),
+ DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "usb_host_hs_utmi_p1_clk"),
+ DT_CLK(NULL, "utmi_p2_gfclk", "utmi_p2_gfclk"),
+ DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "usb_host_hs_utmi_p2_clk"),
+ DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "usb_host_hs_utmi_p3_clk"),
+ DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "usb_host_hs_hsic480m_p1_clk"),
+ DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "usb_host_hs_hsic60m_p1_clk"),
+ DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "usb_host_hs_hsic60m_p2_clk"),
+ DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "usb_host_hs_hsic480m_p2_clk"),
+ DT_CLK(NULL, "usb_host_hs_func48mclk", "usb_host_hs_func48mclk"),
+ DT_CLK(NULL, "usb_host_hs_fck", "usb_host_hs_fck"),
+ DT_CLK("usbhs_omap", "hs_fck", "usb_host_hs_fck"),
+ DT_CLK(NULL, "otg_60m_gfclk", "otg_60m_gfclk"),
+ DT_CLK(NULL, "usb_otg_hs_xclk", "usb_otg_hs_xclk"),
+ DT_CLK(NULL, "usb_otg_hs_ick", "usb_otg_hs_ick"),
+ DT_CLK("musb-omap2430", "ick", "usb_otg_hs_ick"),
+ DT_CLK(NULL, "usb_phy_cm_clk32k", "usb_phy_cm_clk32k"),
+ DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "usb_tll_hs_usb_ch2_clk"),
+ DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "usb_tll_hs_usb_ch0_clk"),
+ DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "usb_tll_hs_usb_ch1_clk"),
+ DT_CLK(NULL, "usb_tll_hs_ick", "usb_tll_hs_ick"),
+ DT_CLK("usbhs_omap", "usbtll_ick", "usb_tll_hs_ick"),
+ DT_CLK("usbhs_tll", "usbtll_ick", "usb_tll_hs_ick"),
+ DT_CLK(NULL, "usim_ck", "usim_ck"),
+ DT_CLK(NULL, "usim_fclk", "usim_fclk"),
+ DT_CLK(NULL, "pmd_stm_clock_mux_ck", "pmd_stm_clock_mux_ck"),
+ DT_CLK(NULL, "pmd_trace_clk_mux_ck", "pmd_trace_clk_mux_ck"),
+ DT_CLK(NULL, "stm_clk_div_ck", "stm_clk_div_ck"),
+ DT_CLK(NULL, "trace_clk_div_ck", "trace_clk_div_ck"),
+ DT_CLK(NULL, "auxclk0_src_ck", "auxclk0_src_ck"),
+ DT_CLK(NULL, "auxclk0_ck", "auxclk0_ck"),
+ DT_CLK(NULL, "auxclkreq0_ck", "auxclkreq0_ck"),
+ DT_CLK(NULL, "auxclk1_src_ck", "auxclk1_src_ck"),
+ DT_CLK(NULL, "auxclk1_ck", "auxclk1_ck"),
+ DT_CLK(NULL, "auxclkreq1_ck", "auxclkreq1_ck"),
+ DT_CLK(NULL, "auxclk2_src_ck", "auxclk2_src_ck"),
+ DT_CLK(NULL, "auxclk2_ck", "auxclk2_ck"),
+ DT_CLK(NULL, "auxclkreq2_ck", "auxclkreq2_ck"),
+ DT_CLK(NULL, "auxclk3_src_ck", "auxclk3_src_ck"),
+ DT_CLK(NULL, "auxclk3_ck", "auxclk3_ck"),
+ DT_CLK(NULL, "auxclkreq3_ck", "auxclkreq3_ck"),
+ DT_CLK(NULL, "auxclk4_src_ck", "auxclk4_src_ck"),
+ DT_CLK(NULL, "auxclk4_ck", "auxclk4_ck"),
+ DT_CLK(NULL, "auxclkreq4_ck", "auxclkreq4_ck"),
+ DT_CLK(NULL, "auxclk5_src_ck", "auxclk5_src_ck"),
+ DT_CLK(NULL, "auxclk5_ck", "auxclk5_ck"),
+ DT_CLK(NULL, "auxclkreq5_ck", "auxclkreq5_ck"),
+ DT_CLK("50000000.gpmc", "fck", "dummy_ck"),
+ DT_CLK("omap_i2c.1", "ick", "dummy_ck"),
+ DT_CLK("omap_i2c.2", "ick", "dummy_ck"),
+ DT_CLK("omap_i2c.3", "ick", "dummy_ck"),
+ DT_CLK("omap_i2c.4", "ick", "dummy_ck"),
+ DT_CLK(NULL, "mailboxes_ick", "dummy_ck"),
+ DT_CLK("omap_hsmmc.0", "ick", "dummy_ck"),
+ DT_CLK("omap_hsmmc.1", "ick", "dummy_ck"),
+ DT_CLK("omap_hsmmc.2", "ick", "dummy_ck"),
+ DT_CLK("omap_hsmmc.3", "ick", "dummy_ck"),
+ DT_CLK("omap_hsmmc.4", "ick", "dummy_ck"),
+ DT_CLK("omap-mcbsp.1", "ick", "dummy_ck"),
+ DT_CLK("omap-mcbsp.2", "ick", "dummy_ck"),
+ DT_CLK("omap-mcbsp.3", "ick", "dummy_ck"),
+ DT_CLK("omap-mcbsp.4", "ick", "dummy_ck"),
+ DT_CLK("omap2_mcspi.1", "ick", "dummy_ck"),
+ DT_CLK("omap2_mcspi.2", "ick", "dummy_ck"),
+ DT_CLK("omap2_mcspi.3", "ick", "dummy_ck"),
+ DT_CLK("omap2_mcspi.4", "ick", "dummy_ck"),
+ DT_CLK(NULL, "uart1_ick", "dummy_ck"),
+ DT_CLK(NULL, "uart2_ick", "dummy_ck"),
+ DT_CLK(NULL, "uart3_ick", "dummy_ck"),
+ DT_CLK(NULL, "uart4_ick", "dummy_ck"),
+ DT_CLK("usbhs_omap", "usbhost_ick", "dummy_ck"),
+ DT_CLK("usbhs_omap", "usbtll_fck", "dummy_ck"),
+ DT_CLK("usbhs_tll", "usbtll_fck", "dummy_ck"),
+ DT_CLK("omap_wdt", "ick", "dummy_ck"),
+ DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
+ DT_CLK("omap_timer.1", "timer_sys_ck", "sys_clkin_ck"),
+ DT_CLK("omap_timer.2", "timer_sys_ck", "sys_clkin_ck"),
+ DT_CLK("omap_timer.3", "timer_sys_ck", "sys_clkin_ck"),
+ DT_CLK("omap_timer.4", "timer_sys_ck", "sys_clkin_ck"),
+ DT_CLK("omap_timer.9", "timer_sys_ck", "sys_clkin_ck"),
+ DT_CLK("omap_timer.10", "timer_sys_ck", "sys_clkin_ck"),
+ DT_CLK("omap_timer.11", "timer_sys_ck", "sys_clkin_ck"),
+ DT_CLK("omap_timer.5", "timer_sys_ck", "syc_clk_div_ck"),
+ DT_CLK("omap_timer.6", "timer_sys_ck", "syc_clk_div_ck"),
+ DT_CLK("omap_timer.7", "timer_sys_ck", "syc_clk_div_ck"),
+ DT_CLK("omap_timer.8", "timer_sys_ck", "syc_clk_div_ck"),
+ DT_CLK("4a318000.timer", "timer_sys_ck", "sys_clkin_ck"),
+ DT_CLK("48032000.timer", "timer_sys_ck", "sys_clkin_ck"),
+ DT_CLK("48034000.timer", "timer_sys_ck", "sys_clkin_ck"),
+ DT_CLK("48036000.timer", "timer_sys_ck", "sys_clkin_ck"),
+ DT_CLK("4803e000.timer", "timer_sys_ck", "sys_clkin_ck"),
+ DT_CLK("48086000.timer", "timer_sys_ck", "sys_clkin_ck"),
+ DT_CLK("48088000.timer", "timer_sys_ck", "sys_clkin_ck"),
+ DT_CLK("40138000.timer", "timer_sys_ck", "syc_clk_div_ck"),
+ DT_CLK("4013a000.timer", "timer_sys_ck", "syc_clk_div_ck"),
+ DT_CLK("4013c000.timer", "timer_sys_ck", "syc_clk_div_ck"),
+ DT_CLK("4013e000.timer", "timer_sys_ck", "syc_clk_div_ck"),
+ DT_CLK(NULL, "cpufreq_ck", "dpll_mpu_ck"),
+ DT_CLK(NULL, "bandgap_fclk", "bandgap_fclk"),
+ DT_CLK(NULL, "div_ts_ck", "div_ts_ck"),
+ DT_CLK(NULL, "bandgap_ts_fclk", "bandgap_ts_fclk"),
+ { .node_name = NULL },
+};
+
+int __init omap4xxx_clk_init(void)
+{
+ int rc;
+ struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll;
+
+ of_clk_init(NULL);
+
+ ti_dt_clocks_register(omap44xx_clks);
+
+ omap2_clk_disable_autoidle_all();
+
+ /*
+ * Lock USB DPLL on OMAP4 devices so that the L3INIT power
+ * domain can transition to retention state when not in use.
+ */
+ usb_dpll = clk_get_sys(NULL, "dpll_usb_ck");
+ rc = clk_set_rate(usb_dpll, OMAP4_DPLL_USB_DEFFREQ);
+ if (rc)
+ pr_err("%s: failed to configure USB DPLL!\n", __func__);
+
+ /*
+ * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power
+ * state when turning the ABE clock domain. Workaround this by
+ * locking the ABE DPLL on boot.
+ * Lock the ABE DPLL in any case to avoid issues with audio.
+ */
+ abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_refclk_mux_ck");
+ sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
+ rc = clk_set_parent(abe_dpll_ref, sys_32k_ck);
+ abe_dpll = clk_get_sys(NULL, "dpll_abe_ck");
+ if (!rc)
+ rc = clk_set_rate(abe_dpll, OMAP4_DPLL_ABE_DEFFREQ);
+ if (rc)
+ pr_err("%s: failed to configure ABE DPLL!\n", __func__);
+
+ return 0;
+}
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index ed4b36e..c9a18b9 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -207,6 +207,7 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
unsigned long parent_rate);
int omap2_clkops_enable_clkdm(struct clk_hw *hw);
void omap2_clkops_disable_clkdm(struct clk_hw *hw);
+int omap2_clk_disable_autoidle_all(void);
int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
unsigned long parent_rate);
int omap2_dflt_clk_enable(struct clk_hw *hw);
@@ -218,6 +219,8 @@ void of_ti_autoidle_setup(struct device_node *node);
struct clk_div_table *ti_clk_get_div_table(struct device_node *node);
+int omap4xxx_clk_init(void);
+
#ifdef CONFIG_OF
void of_ti_clk_allow_autoidle_all(void);
void of_ti_clk_deny_autoidle_all(void);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 12/36] ARM: OMAP4: remove old clock data and link in new clock init code
2013-09-25 8:48 ` Tero Kristo
@ 2013-09-25 8:48 ` Tero Kristo
-1 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-omap, paul, tony, nm, rnayak, bcousson, mturquette
Cc: linux-arm-kernel, devicetree
OMAP4 clocks have now been moved to DT, thus remove the old data file
and use the new init code under drivers/clk/omap/clk-44xx.c.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/mach-omap2/Makefile | 2 +-
arch/arm/mach-omap2/cclock44xx_data.c | 1734 ---------------------------------
drivers/clk/ti/Makefile | 1 +
3 files changed, 2 insertions(+), 1735 deletions(-)
delete mode 100644 arch/arm/mach-omap2/cclock44xx_data.c
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index afb457c..f518360 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -184,7 +184,7 @@ obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o
obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o
obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o cclock3xxx_data.o
obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o
-obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) cclock44xx_data.o
+obj-$(CONFIG_ARCH_OMAP4) += $(clock-common)
obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o
obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o
obj-$(CONFIG_SOC_AM33XX) += cclock33xx_data.o
diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c
deleted file mode 100644
index b237950..0000000
--- a/arch/arm/mach-omap2/cclock44xx_data.c
+++ /dev/null
@@ -1,1734 +0,0 @@
-/*
- * OMAP4 Clock data
- *
- * Copyright (C) 2009-2012 Texas Instruments, Inc.
- * Copyright (C) 2009-2010 Nokia Corporation
- *
- * Paul Walmsley (paul@pwsan.com)
- * Rajendra Nayak (rnayak@ti.com)
- * Benoit Cousson (b-cousson@ti.com)
- * Mike Turquette (mturquette@ti.com)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * XXX Some of the ES1 clocks have been removed/changed; once support
- * is added for discriminating clocks by ES level, these should be added back
- * in.
- *
- * XXX All of the remaining MODULEMODE clock nodes should be removed
- * once the drivers are updated to use pm_runtime or to use the appropriate
- * upstream clock node for rate/parent selection.
- */
-
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/clk-private.h>
-#include <linux/clkdev.h>
-#include <linux/io.h>
-
-#include "soc.h"
-#include "iomap.h"
-#include "clock.h"
-#include "clock44xx.h"
-#include "cm1_44xx.h"
-#include "cm2_44xx.h"
-#include "cm-regbits-44xx.h"
-#include "prm44xx.h"
-#include "prm-regbits-44xx.h"
-#include "control.h"
-#include "scrm44xx.h"
-
-/* OMAP4 modulemode control */
-#define OMAP4430_MODULEMODE_HWCTRL_SHIFT 0
-#define OMAP4430_MODULEMODE_SWCTRL_SHIFT 1
-
-/*
- * OMAP4 ABE DPLL default frequency. In OMAP4460 TRM version V, section
- * "3.6.3.2.3 CM1_ABE Clock Generator" states that the "DPLL_ABE_X2_CLK
- * must be set to 196.608 MHz" and hence, the DPLL locked frequency is
- * half of this value.
- */
-#define OMAP4_DPLL_ABE_DEFFREQ 98304000
-
-/*
- * OMAP4 USB DPLL default frequency. In OMAP4430 TRM version V, section
- * "3.6.3.9.5 DPLL_USB Preferred Settings" shows that the preferred
- * locked frequency for the USB DPLL is 960MHz.
- */
-#define OMAP4_DPLL_USB_DEFFREQ 960000000
-
-/* Root clocks */
-
-DEFINE_CLK_FIXED_RATE(extalt_clkin_ck, CLK_IS_ROOT, 59000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(pad_clks_src_ck, CLK_IS_ROOT, 12000000, 0x0);
-
-DEFINE_CLK_GATE(pad_clks_ck, "pad_clks_src_ck", &pad_clks_src_ck, 0x0,
- OMAP4430_CM_CLKSEL_ABE, OMAP4430_PAD_CLKS_GATE_SHIFT,
- 0x0, NULL);
-
-DEFINE_CLK_FIXED_RATE(pad_slimbus_core_clks_ck, CLK_IS_ROOT, 12000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(secure_32k_clk_src_ck, CLK_IS_ROOT, 32768, 0x0);
-
-DEFINE_CLK_FIXED_RATE(slimbus_src_clk, CLK_IS_ROOT, 12000000, 0x0);
-
-DEFINE_CLK_GATE(slimbus_clk, "slimbus_src_clk", &slimbus_src_clk, 0x0,
- OMAP4430_CM_CLKSEL_ABE, OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
- 0x0, NULL);
-
-DEFINE_CLK_FIXED_RATE(sys_32k_ck, CLK_IS_ROOT, 32768, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_12000000_ck, CLK_IS_ROOT, 12000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_13000000_ck, CLK_IS_ROOT, 13000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_16800000_ck, CLK_IS_ROOT, 16800000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_27000000_ck, CLK_IS_ROOT, 27000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_38400000_ck, CLK_IS_ROOT, 38400000, 0x0);
-
-static const char *sys_clkin_ck_parents[] = {
- "virt_12000000_ck", "virt_13000000_ck", "virt_16800000_ck",
- "virt_19200000_ck", "virt_26000000_ck", "virt_27000000_ck",
- "virt_38400000_ck",
-};
-
-DEFINE_CLK_MUX(sys_clkin_ck, sys_clkin_ck_parents, NULL, 0x0,
- OMAP4430_CM_SYS_CLKSEL, OMAP4430_SYS_CLKSEL_SHIFT,
- OMAP4430_SYS_CLKSEL_WIDTH, CLK_MUX_INDEX_ONE, NULL);
-
-DEFINE_CLK_FIXED_RATE(tie_low_clock_ck, CLK_IS_ROOT, 0, 0x0);
-
-DEFINE_CLK_FIXED_RATE(utmi_phy_clkout_ck, CLK_IS_ROOT, 60000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(xclk60mhsp1_ck, CLK_IS_ROOT, 60000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(xclk60mhsp2_ck, CLK_IS_ROOT, 60000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(xclk60motg_ck, CLK_IS_ROOT, 60000000, 0x0);
-
-/* Module clocks and DPLL outputs */
-
-static const char *abe_dpll_bypass_clk_mux_ck_parents[] = {
- "sys_clkin_ck", "sys_32k_ck",
-};
-
-DEFINE_CLK_MUX(abe_dpll_bypass_clk_mux_ck, abe_dpll_bypass_clk_mux_ck_parents,
- NULL, 0x0, OMAP4430_CM_L4_WKUP_CLKSEL, OMAP4430_CLKSEL_SHIFT,
- OMAP4430_CLKSEL_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_MUX(abe_dpll_refclk_mux_ck, abe_dpll_bypass_clk_mux_ck_parents, NULL,
- 0x0, OMAP4430_CM_ABE_PLL_REF_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
- OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
-
-/* DPLL_ABE */
-static struct dpll_data dpll_abe_dd = {
- .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_ABE,
- .clk_bypass = &abe_dpll_bypass_clk_mux_ck,
- .clk_ref = &abe_dpll_refclk_mux_ck,
- .control_reg = OMAP4430_CM_CLKMODE_DPLL_ABE,
- .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
- .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_ABE,
- .idlest_reg = OMAP4430_CM_IDLEST_DPLL_ABE,
- .mult_mask = OMAP4430_DPLL_MULT_MASK,
- .div1_mask = OMAP4430_DPLL_DIV_MASK,
- .enable_mask = OMAP4430_DPLL_EN_MASK,
- .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
- .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
- .m4xen_mask = OMAP4430_DPLL_REGM4XEN_MASK,
- .lpmode_mask = OMAP4430_DPLL_LPMODE_EN_MASK,
- .max_multiplier = 2047,
- .max_divider = 128,
- .min_divider = 1,
-};
-
-
-static const char *dpll_abe_ck_parents[] = {
- "abe_dpll_refclk_mux_ck",
-};
-
-static struct clk dpll_abe_ck;
-
-static const struct clk_ops dpll_abe_ck_ops = {
- .enable = &omap3_noncore_dpll_enable,
- .disable = &omap3_noncore_dpll_disable,
- .recalc_rate = &omap4_dpll_regm4xen_recalc,
- .round_rate = &omap4_dpll_regm4xen_round_rate,
- .set_rate = &omap3_noncore_dpll_set_rate,
- .get_parent = &omap2_init_dpll_parent,
-};
-
-static struct clk_hw_omap dpll_abe_ck_hw = {
- .hw = {
- .clk = &dpll_abe_ck,
- },
- .dpll_data = &dpll_abe_dd,
- .ops = &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_abe_ck, dpll_abe_ck_parents, dpll_abe_ck_ops);
-
-static const char *dpll_abe_x2_ck_parents[] = {
- "dpll_abe_ck",
-};
-
-static struct clk dpll_abe_x2_ck;
-
-static const struct clk_ops dpll_abe_x2_ck_ops = {
- .recalc_rate = &omap3_clkoutx2_recalc,
-};
-
-static struct clk_hw_omap dpll_abe_x2_ck_hw = {
- .hw = {
- .clk = &dpll_abe_x2_ck,
- },
- .flags = CLOCK_CLKOUTX2,
- .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
- .ops = &clkhwops_omap4_dpllmx,
-};
-
-DEFINE_STRUCT_CLK(dpll_abe_x2_ck, dpll_abe_x2_ck_parents, dpll_abe_x2_ck_ops);
-
-static const struct clk_ops omap_hsdivider_ops = {
- .set_rate = &omap2_clksel_set_rate,
- .recalc_rate = &omap2_clksel_recalc,
- .round_rate = &omap2_clksel_round_rate,
-};
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_abe_m2x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck,
- 0x0, OMAP4430_CM_DIV_M2_DPLL_ABE,
- OMAP4430_DPLL_CLKOUT_DIV_MASK);
-
-DEFINE_CLK_FIXED_FACTOR(abe_24m_fclk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck,
- 0x0, 1, 8);
-
-DEFINE_CLK_DIVIDER(abe_clk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, 0x0,
- OMAP4430_CM_CLKSEL_ABE, OMAP4430_CLKSEL_OPP_SHIFT,
- OMAP4430_CLKSEL_OPP_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
-
-DEFINE_CLK_DIVIDER(aess_fclk, "abe_clk", &abe_clk, 0x0,
- OMAP4430_CM1_ABE_AESS_CLKCTRL,
- OMAP4430_CLKSEL_AESS_FCLK_SHIFT,
- OMAP4430_CLKSEL_AESS_FCLK_WIDTH,
- 0x0, NULL);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_abe_m3x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck,
- 0x0, OMAP4430_CM_DIV_M3_DPLL_ABE,
- OMAP4430_DPLL_CLKOUTHIF_DIV_MASK);
-
-static const char *core_hsd_byp_clk_mux_ck_parents[] = {
- "sys_clkin_ck", "dpll_abe_m3x2_ck",
-};
-
-DEFINE_CLK_MUX(core_hsd_byp_clk_mux_ck, core_hsd_byp_clk_mux_ck_parents, NULL,
- 0x0, OMAP4430_CM_CLKSEL_DPLL_CORE,
- OMAP4430_DPLL_BYP_CLKSEL_SHIFT, OMAP4430_DPLL_BYP_CLKSEL_WIDTH,
- 0x0, NULL);
-
-/* DPLL_CORE */
-static struct dpll_data dpll_core_dd = {
- .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_CORE,
- .clk_bypass = &core_hsd_byp_clk_mux_ck,
- .clk_ref = &sys_clkin_ck,
- .control_reg = OMAP4430_CM_CLKMODE_DPLL_CORE,
- .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
- .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_CORE,
- .idlest_reg = OMAP4430_CM_IDLEST_DPLL_CORE,
- .mult_mask = OMAP4430_DPLL_MULT_MASK,
- .div1_mask = OMAP4430_DPLL_DIV_MASK,
- .enable_mask = OMAP4430_DPLL_EN_MASK,
- .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
- .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
- .max_multiplier = 2047,
- .max_divider = 128,
- .min_divider = 1,
-};
-
-
-static const char *dpll_core_ck_parents[] = {
- "sys_clkin_ck", "core_hsd_byp_clk_mux_ck"
-};
-
-static struct clk dpll_core_ck;
-
-static const struct clk_ops dpll_core_ck_ops = {
- .recalc_rate = &omap3_dpll_recalc,
- .get_parent = &omap2_init_dpll_parent,
-};
-
-static struct clk_hw_omap dpll_core_ck_hw = {
- .hw = {
- .clk = &dpll_core_ck,
- },
- .dpll_data = &dpll_core_dd,
- .ops = &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops);
-
-static const char *dpll_core_x2_ck_parents[] = {
- "dpll_core_ck",
-};
-
-static struct clk dpll_core_x2_ck;
-
-static struct clk_hw_omap dpll_core_x2_ck_hw = {
- .hw = {
- .clk = &dpll_core_x2_ck,
- },
-};
-
-DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_abe_x2_ck_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m6x2_ck, "dpll_core_x2_ck",
- &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M6_DPLL_CORE,
- OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m2_ck, "dpll_core_ck", &dpll_core_ck, 0x0,
- OMAP4430_CM_DIV_M2_DPLL_CORE,
- OMAP4430_DPLL_CLKOUT_DIV_MASK);
-
-DEFINE_CLK_FIXED_FACTOR(ddrphy_ck, "dpll_core_m2_ck", &dpll_core_m2_ck, 0x0, 1,
- 2);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m5x2_ck, "dpll_core_x2_ck",
- &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M5_DPLL_CORE,
- OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK);
-
-DEFINE_CLK_DIVIDER(div_core_ck, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, 0x0,
- OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_CORE_SHIFT,
- OMAP4430_CLKSEL_CORE_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_DIVIDER(div_iva_hs_clk, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck,
- 0x0, OMAP4430_CM_BYPCLK_DPLL_IVA, OMAP4430_CLKSEL_0_1_SHIFT,
- OMAP4430_CLKSEL_0_1_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
-
-DEFINE_CLK_DIVIDER(div_mpu_hs_clk, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck,
- 0x0, OMAP4430_CM_BYPCLK_DPLL_MPU, OMAP4430_CLKSEL_0_1_SHIFT,
- OMAP4430_CLKSEL_0_1_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m4x2_ck, "dpll_core_x2_ck",
- &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M4_DPLL_CORE,
- OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK);
-
-DEFINE_CLK_FIXED_FACTOR(dll_clk_div_ck, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck,
- 0x0, 1, 2);
-
-DEFINE_CLK_DIVIDER(dpll_abe_m2_ck, "dpll_abe_ck", &dpll_abe_ck, 0x0,
- OMAP4430_CM_DIV_M2_DPLL_ABE, OMAP4430_DPLL_CLKOUT_DIV_SHIFT,
- OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
-
-static const struct clk_ops dpll_hsd_ops = {
- .enable = &omap2_dflt_clk_enable,
- .disable = &omap2_dflt_clk_disable,
- .is_enabled = &omap2_dflt_clk_is_enabled,
- .recalc_rate = &omap2_clksel_recalc,
- .get_parent = &omap2_clksel_find_parent_index,
- .set_parent = &omap2_clksel_set_parent,
- .init = &omap2_init_clk_clkdm,
-};
-
-static const struct clk_ops func_dmic_abe_gfclk_ops = {
- .recalc_rate = &omap2_clksel_recalc,
- .get_parent = &omap2_clksel_find_parent_index,
- .set_parent = &omap2_clksel_set_parent,
-};
-
-static const char *dpll_core_m3x2_ck_parents[] = {
- "dpll_core_x2_ck",
-};
-
-static const struct clksel dpll_core_m3x2_div[] = {
- { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
- { .parent = NULL },
-};
-
-/* XXX Missing round_rate, set_rate in ops */
-DEFINE_CLK_OMAP_MUX_GATE(dpll_core_m3x2_ck, NULL, dpll_core_m3x2_div,
- OMAP4430_CM_DIV_M3_DPLL_CORE,
- OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
- OMAP4430_CM_DIV_M3_DPLL_CORE,
- OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL,
- dpll_core_m3x2_ck_parents, dpll_hsd_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m7x2_ck, "dpll_core_x2_ck",
- &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M7_DPLL_CORE,
- OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK);
-
-static const char *iva_hsd_byp_clk_mux_ck_parents[] = {
- "sys_clkin_ck", "div_iva_hs_clk",
-};
-
-DEFINE_CLK_MUX(iva_hsd_byp_clk_mux_ck, iva_hsd_byp_clk_mux_ck_parents, NULL,
- 0x0, OMAP4430_CM_CLKSEL_DPLL_IVA, OMAP4430_DPLL_BYP_CLKSEL_SHIFT,
- OMAP4430_DPLL_BYP_CLKSEL_WIDTH, 0x0, NULL);
-
-/* DPLL_IVA */
-static struct dpll_data dpll_iva_dd = {
- .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_IVA,
- .clk_bypass = &iva_hsd_byp_clk_mux_ck,
- .clk_ref = &sys_clkin_ck,
- .control_reg = OMAP4430_CM_CLKMODE_DPLL_IVA,
- .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
- .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_IVA,
- .idlest_reg = OMAP4430_CM_IDLEST_DPLL_IVA,
- .mult_mask = OMAP4430_DPLL_MULT_MASK,
- .div1_mask = OMAP4430_DPLL_DIV_MASK,
- .enable_mask = OMAP4430_DPLL_EN_MASK,
- .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
- .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
- .max_multiplier = 2047,
- .max_divider = 128,
- .min_divider = 1,
-};
-
-static const char *dpll_iva_ck_parents[] = {
- "sys_clkin_ck", "iva_hsd_byp_clk_mux_ck"
-};
-
-static struct clk dpll_iva_ck;
-
-static const struct clk_ops dpll_ck_ops = {
- .enable = &omap3_noncore_dpll_enable,
- .disable = &omap3_noncore_dpll_disable,
- .recalc_rate = &omap3_dpll_recalc,
- .round_rate = &omap2_dpll_round_rate,
- .set_rate = &omap3_noncore_dpll_set_rate,
- .get_parent = &omap2_init_dpll_parent,
-};
-
-static struct clk_hw_omap dpll_iva_ck_hw = {
- .hw = {
- .clk = &dpll_iva_ck,
- },
- .dpll_data = &dpll_iva_dd,
- .ops = &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_iva_ck, dpll_iva_ck_parents, dpll_ck_ops);
-
-static const char *dpll_iva_x2_ck_parents[] = {
- "dpll_iva_ck",
-};
-
-static struct clk dpll_iva_x2_ck;
-
-static struct clk_hw_omap dpll_iva_x2_ck_hw = {
- .hw = {
- .clk = &dpll_iva_x2_ck,
- },
-};
-
-DEFINE_STRUCT_CLK(dpll_iva_x2_ck, dpll_iva_x2_ck_parents, dpll_abe_x2_ck_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_iva_m4x2_ck, "dpll_iva_x2_ck", &dpll_iva_x2_ck,
- 0x0, OMAP4430_CM_DIV_M4_DPLL_IVA,
- OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_iva_m5x2_ck, "dpll_iva_x2_ck", &dpll_iva_x2_ck,
- 0x0, OMAP4430_CM_DIV_M5_DPLL_IVA,
- OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK);
-
-/* DPLL_MPU */
-static struct dpll_data dpll_mpu_dd = {
- .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_MPU,
- .clk_bypass = &div_mpu_hs_clk,
- .clk_ref = &sys_clkin_ck,
- .control_reg = OMAP4430_CM_CLKMODE_DPLL_MPU,
- .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
- .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_MPU,
- .idlest_reg = OMAP4430_CM_IDLEST_DPLL_MPU,
- .mult_mask = OMAP4430_DPLL_MULT_MASK,
- .div1_mask = OMAP4430_DPLL_DIV_MASK,
- .enable_mask = OMAP4430_DPLL_EN_MASK,
- .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
- .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
- .max_multiplier = 2047,
- .max_divider = 128,
- .min_divider = 1,
-};
-
-static const char *dpll_mpu_ck_parents[] = {
- "sys_clkin_ck", "div_mpu_hs_clk"
-};
-
-static struct clk dpll_mpu_ck;
-
-static struct clk_hw_omap dpll_mpu_ck_hw = {
- .hw = {
- .clk = &dpll_mpu_ck,
- },
- .dpll_data = &dpll_mpu_dd,
- .ops = &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_mpu_ck_parents, dpll_ck_ops);
-
-DEFINE_CLK_FIXED_FACTOR(mpu_periphclk, "dpll_mpu_ck", &dpll_mpu_ck, 0x0, 1, 2);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck, 0x0,
- OMAP4430_CM_DIV_M2_DPLL_MPU,
- OMAP4430_DPLL_CLKOUT_DIV_MASK);
-
-DEFINE_CLK_FIXED_FACTOR(per_hs_clk_div_ck, "dpll_abe_m3x2_ck",
- &dpll_abe_m3x2_ck, 0x0, 1, 2);
-
-static const char *per_hsd_byp_clk_mux_ck_parents[] = {
- "sys_clkin_ck", "per_hs_clk_div_ck",
-};
-
-DEFINE_CLK_MUX(per_hsd_byp_clk_mux_ck, per_hsd_byp_clk_mux_ck_parents, NULL,
- 0x0, OMAP4430_CM_CLKSEL_DPLL_PER, OMAP4430_DPLL_BYP_CLKSEL_SHIFT,
- OMAP4430_DPLL_BYP_CLKSEL_WIDTH, 0x0, NULL);
-
-/* DPLL_PER */
-static struct dpll_data dpll_per_dd = {
- .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_PER,
- .clk_bypass = &per_hsd_byp_clk_mux_ck,
- .clk_ref = &sys_clkin_ck,
- .control_reg = OMAP4430_CM_CLKMODE_DPLL_PER,
- .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
- .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_PER,
- .idlest_reg = OMAP4430_CM_IDLEST_DPLL_PER,
- .mult_mask = OMAP4430_DPLL_MULT_MASK,
- .div1_mask = OMAP4430_DPLL_DIV_MASK,
- .enable_mask = OMAP4430_DPLL_EN_MASK,
- .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
- .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
- .max_multiplier = 2047,
- .max_divider = 128,
- .min_divider = 1,
-};
-
-static const char *dpll_per_ck_parents[] = {
- "sys_clkin_ck", "per_hsd_byp_clk_mux_ck"
-};
-
-static struct clk dpll_per_ck;
-
-static struct clk_hw_omap dpll_per_ck_hw = {
- .hw = {
- .clk = &dpll_per_ck,
- },
- .dpll_data = &dpll_per_dd,
- .ops = &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_per_ck, dpll_per_ck_parents, dpll_ck_ops);
-
-DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0,
- OMAP4430_CM_DIV_M2_DPLL_PER, OMAP4430_DPLL_CLKOUT_DIV_SHIFT,
- OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
-
-static const char *dpll_per_x2_ck_parents[] = {
- "dpll_per_ck",
-};
-
-static struct clk dpll_per_x2_ck;
-
-static struct clk_hw_omap dpll_per_x2_ck_hw = {
- .hw = {
- .clk = &dpll_per_x2_ck,
- },
- .flags = CLOCK_CLKOUTX2,
- .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
- .ops = &clkhwops_omap4_dpllmx,
-};
-
-DEFINE_STRUCT_CLK(dpll_per_x2_ck, dpll_per_x2_ck_parents, dpll_abe_x2_ck_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m2x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
- 0x0, OMAP4430_CM_DIV_M2_DPLL_PER,
- OMAP4430_DPLL_CLKOUT_DIV_MASK);
-
-static const char *dpll_per_m3x2_ck_parents[] = {
- "dpll_per_x2_ck",
-};
-
-static const struct clksel dpll_per_m3x2_div[] = {
- { .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates },
- { .parent = NULL },
-};
-
-/* XXX Missing round_rate, set_rate in ops */
-DEFINE_CLK_OMAP_MUX_GATE(dpll_per_m3x2_ck, NULL, dpll_per_m3x2_div,
- OMAP4430_CM_DIV_M3_DPLL_PER,
- OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
- OMAP4430_CM_DIV_M3_DPLL_PER,
- OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL,
- dpll_per_m3x2_ck_parents, dpll_hsd_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m4x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
- 0x0, OMAP4430_CM_DIV_M4_DPLL_PER,
- OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m5x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
- 0x0, OMAP4430_CM_DIV_M5_DPLL_PER,
- OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m6x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
- 0x0, OMAP4430_CM_DIV_M6_DPLL_PER,
- OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m7x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
- 0x0, OMAP4430_CM_DIV_M7_DPLL_PER,
- OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK);
-
-DEFINE_CLK_FIXED_FACTOR(usb_hs_clk_div_ck, "dpll_abe_m3x2_ck",
- &dpll_abe_m3x2_ck, 0x0, 1, 3);
-
-/* DPLL_USB */
-static struct dpll_data dpll_usb_dd = {
- .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB,
- .clk_bypass = &usb_hs_clk_div_ck,
- .flags = DPLL_J_TYPE,
- .clk_ref = &sys_clkin_ck,
- .control_reg = OMAP4430_CM_CLKMODE_DPLL_USB,
- .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
- .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_USB,
- .idlest_reg = OMAP4430_CM_IDLEST_DPLL_USB,
- .mult_mask = OMAP4430_DPLL_MULT_USB_MASK,
- .div1_mask = OMAP4430_DPLL_DIV_0_7_MASK,
- .enable_mask = OMAP4430_DPLL_EN_MASK,
- .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
- .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
- .sddiv_mask = OMAP4430_DPLL_SD_DIV_MASK,
- .max_multiplier = 4095,
- .max_divider = 256,
- .min_divider = 1,
-};
-
-static const char *dpll_usb_ck_parents[] = {
- "sys_clkin_ck", "usb_hs_clk_div_ck"
-};
-
-static struct clk dpll_usb_ck;
-
-static const struct clk_ops dpll_usb_ck_ops = {
- .enable = &omap3_noncore_dpll_enable,
- .disable = &omap3_noncore_dpll_disable,
- .recalc_rate = &omap3_dpll_recalc,
- .round_rate = &omap2_dpll_round_rate,
- .set_rate = &omap3_noncore_dpll_set_rate,
- .get_parent = &omap2_init_dpll_parent,
- .init = &omap2_init_clk_clkdm,
-};
-
-static struct clk_hw_omap dpll_usb_ck_hw = {
- .hw = {
- .clk = &dpll_usb_ck,
- },
- .dpll_data = &dpll_usb_dd,
- .clkdm_name = "l3_init_clkdm",
- .ops = &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_usb_ck, dpll_usb_ck_parents, dpll_usb_ck_ops);
-
-static const char *dpll_usb_clkdcoldo_ck_parents[] = {
- "dpll_usb_ck",
-};
-
-static struct clk dpll_usb_clkdcoldo_ck;
-
-static const struct clk_ops dpll_usb_clkdcoldo_ck_ops = {
-};
-
-static struct clk_hw_omap dpll_usb_clkdcoldo_ck_hw = {
- .hw = {
- .clk = &dpll_usb_clkdcoldo_ck,
- },
- .clksel_reg = OMAP4430_CM_CLKDCOLDO_DPLL_USB,
- .ops = &clkhwops_omap4_dpllmx,
-};
-
-DEFINE_STRUCT_CLK(dpll_usb_clkdcoldo_ck, dpll_usb_clkdcoldo_ck_parents,
- dpll_usb_clkdcoldo_ck_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_usb_m2_ck, "dpll_usb_ck", &dpll_usb_ck, 0x0,
- OMAP4430_CM_DIV_M2_DPLL_USB,
- OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK);
-
-static const char *ducati_clk_mux_ck_parents[] = {
- "div_core_ck", "dpll_per_m6x2_ck",
-};
-
-DEFINE_CLK_MUX(ducati_clk_mux_ck, ducati_clk_mux_ck_parents, NULL, 0x0,
- OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT, OMAP4430_CLKSEL_0_0_SHIFT,
- OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_FIXED_FACTOR(func_12m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
- 0x0, 1, 16);
-
-DEFINE_CLK_FIXED_FACTOR(func_24m_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0,
- 1, 4);
-
-DEFINE_CLK_FIXED_FACTOR(func_24mc_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
- 0x0, 1, 8);
-
-static const struct clk_div_table func_48m_fclk_rates[] = {
- { .div = 4, .val = 0 },
- { .div = 8, .val = 1 },
- { .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(func_48m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
- 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
- OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_48m_fclk_rates,
- NULL);
-
-DEFINE_CLK_FIXED_FACTOR(func_48mc_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
- 0x0, 1, 4);
-
-static const struct clk_div_table func_64m_fclk_rates[] = {
- { .div = 2, .val = 0 },
- { .div = 4, .val = 1 },
- { .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(func_64m_fclk, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck,
- 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
- OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_64m_fclk_rates,
- NULL);
-
-static const struct clk_div_table func_96m_fclk_rates[] = {
- { .div = 2, .val = 0 },
- { .div = 4, .val = 1 },
- { .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(func_96m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
- 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
- OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_96m_fclk_rates,
- NULL);
-
-static const struct clk_div_table init_60m_fclk_rates[] = {
- { .div = 1, .val = 0 },
- { .div = 8, .val = 1 },
- { .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(init_60m_fclk, "dpll_usb_m2_ck", &dpll_usb_m2_ck,
- 0x0, OMAP4430_CM_CLKSEL_USB_60MHZ,
- OMAP4430_CLKSEL_0_0_SHIFT, OMAP4430_CLKSEL_0_0_WIDTH,
- 0x0, init_60m_fclk_rates, NULL);
-
-DEFINE_CLK_DIVIDER(l3_div_ck, "div_core_ck", &div_core_ck, 0x0,
- OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_L3_SHIFT,
- OMAP4430_CLKSEL_L3_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_DIVIDER(l4_div_ck, "l3_div_ck", &l3_div_ck, 0x0,
- OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_L4_SHIFT,
- OMAP4430_CLKSEL_L4_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_FIXED_FACTOR(lp_clk_div_ck, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck,
- 0x0, 1, 16);
-
-static const char *l4_wkup_clk_mux_ck_parents[] = {
- "sys_clkin_ck", "lp_clk_div_ck",
-};
-
-DEFINE_CLK_MUX(l4_wkup_clk_mux_ck, l4_wkup_clk_mux_ck_parents, NULL, 0x0,
- OMAP4430_CM_L4_WKUP_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
- OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
-
-static const struct clk_div_table ocp_abe_iclk_rates[] = {
- { .div = 2, .val = 0 },
- { .div = 1, .val = 1 },
- { .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(ocp_abe_iclk, "aess_fclk", &aess_fclk, 0x0,
- OMAP4430_CM1_ABE_AESS_CLKCTRL,
- OMAP4430_CLKSEL_AESS_FCLK_SHIFT,
- OMAP4430_CLKSEL_AESS_FCLK_WIDTH,
- 0x0, ocp_abe_iclk_rates, NULL);
-
-DEFINE_CLK_FIXED_FACTOR(per_abe_24m_fclk, "dpll_abe_m2_ck", &dpll_abe_m2_ck,
- 0x0, 1, 4);
-
-DEFINE_CLK_DIVIDER(per_abe_nc_fclk, "dpll_abe_m2_ck", &dpll_abe_m2_ck, 0x0,
- OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
- OMAP4430_SCALE_FCLK_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_DIVIDER(syc_clk_div_ck, "sys_clkin_ck", &sys_clkin_ck, 0x0,
- OMAP4430_CM_ABE_DSS_SYS_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
- OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
-
-static const char *dbgclk_mux_ck_parents[] = {
- "sys_clkin_ck"
-};
-
-static struct clk dbgclk_mux_ck;
-DEFINE_STRUCT_CLK_HW_OMAP(dbgclk_mux_ck, NULL);
-DEFINE_STRUCT_CLK(dbgclk_mux_ck, dbgclk_mux_ck_parents,
- dpll_usb_clkdcoldo_ck_ops);
-
-/* Leaf clocks controlled by modules */
-
-DEFINE_CLK_GATE(aes1_fck, "l3_div_ck", &l3_div_ck, 0x0,
- OMAP4430_CM_L4SEC_AES1_CLKCTRL,
- OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(aes2_fck, "l3_div_ck", &l3_div_ck, 0x0,
- OMAP4430_CM_L4SEC_AES2_CLKCTRL,
- OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(bandgap_fclk, "sys_32k_ck", &sys_32k_ck, 0x0,
- OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
- OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT, 0x0, NULL);
-
-static const struct clk_div_table div_ts_ck_rates[] = {
- { .div = 8, .val = 0 },
- { .div = 16, .val = 1 },
- { .div = 32, .val = 2 },
- { .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(div_ts_ck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
- 0x0, OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
- OMAP4430_CLKSEL_24_25_SHIFT,
- OMAP4430_CLKSEL_24_25_WIDTH, 0x0, div_ts_ck_rates,
- NULL);
-
-DEFINE_CLK_GATE(bandgap_ts_fclk, "div_ts_ck", &div_ts_ck, 0x0,
- OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
- OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT,
- 0x0, NULL);
-
-static const char *dmic_sync_mux_ck_parents[] = {
- "abe_24m_fclk", "syc_clk_div_ck", "func_24m_clk",
-};
-
-DEFINE_CLK_MUX(dmic_sync_mux_ck, dmic_sync_mux_ck_parents, NULL,
- 0x0, OMAP4430_CM1_ABE_DMIC_CLKCTRL,
- OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
- OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel func_dmic_abe_gfclk_sel[] = {
- { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates },
- { .parent = &pad_clks_ck, .rates = div_1_1_rates },
- { .parent = &slimbus_clk, .rates = div_1_2_rates },
- { .parent = NULL },
-};
-
-static const char *func_dmic_abe_gfclk_parents[] = {
- "dmic_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
-};
-
-DEFINE_CLK_OMAP_MUX(func_dmic_abe_gfclk, "abe_clkdm", func_dmic_abe_gfclk_sel,
- OMAP4430_CM1_ABE_DMIC_CLKCTRL, OMAP4430_CLKSEL_SOURCE_MASK,
- func_dmic_abe_gfclk_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_GATE(dss_sys_clk, "syc_clk_div_ck", &syc_clk_div_ck, 0x0,
- OMAP4430_CM_DSS_DSS_CLKCTRL,
- OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(dss_tv_clk, "extalt_clkin_ck", &extalt_clkin_ck, 0x0,
- OMAP4430_CM_DSS_DSS_CLKCTRL,
- OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, 0x0,
- OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
- 0x0, NULL);
-
-DEFINE_CLK_GATE(dss_48mhz_clk, "func_48mc_fclk", &func_48mc_fclk, 0x0,
- OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT,
- 0x0, NULL);
-
-DEFINE_CLK_GATE(dss_fck, "l3_div_ck", &l3_div_ck, 0x0,
- OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
- 0x0, NULL);
-
-DEFINE_CLK_DIVIDER(fdif_fck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0,
- OMAP4430_CM_CAM_FDIF_CLKCTRL, OMAP4430_CLKSEL_FCLK_SHIFT,
- OMAP4430_CLKSEL_FCLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
-
-DEFINE_CLK_GATE(gpio1_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
- OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
- OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(gpio2_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
- OMAP4430_CM_L4PER_GPIO2_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
- 0x0, NULL);
-
-DEFINE_CLK_GATE(gpio3_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
- OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
- OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(gpio4_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
- OMAP4430_CM_L4PER_GPIO4_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
- 0x0, NULL);
-
-DEFINE_CLK_GATE(gpio5_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
- OMAP4430_CM_L4PER_GPIO5_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
- 0x0, NULL);
-
-DEFINE_CLK_GATE(gpio6_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
- OMAP4430_CM_L4PER_GPIO6_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
- 0x0, NULL);
-
-static const struct clksel sgx_clk_mux_sel[] = {
- { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates },
- { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates },
- { .parent = NULL },
-};
-
-static const char *sgx_clk_mux_parents[] = {
- "dpll_core_m7x2_ck", "dpll_per_m7x2_ck",
-};
-
-DEFINE_CLK_OMAP_MUX(sgx_clk_mux, "l3_gfx_clkdm", sgx_clk_mux_sel,
- OMAP4430_CM_GFX_GFX_CLKCTRL, OMAP4430_CLKSEL_SGX_FCLK_MASK,
- sgx_clk_mux_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_DIVIDER(hsi_fck, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, 0x0,
- OMAP4430_CM_L3INIT_HSI_CLKCTRL, OMAP4430_CLKSEL_24_25_SHIFT,
- OMAP4430_CLKSEL_24_25_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
- NULL);
-
-DEFINE_CLK_GATE(iss_ctrlclk, "func_96m_fclk", &func_96m_fclk, 0x0,
- OMAP4430_CM_CAM_ISS_CLKCTRL, OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
- 0x0, NULL);
-
-DEFINE_CLK_MUX(mcasp_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
- OMAP4430_CM1_ABE_MCASP_CLKCTRL,
- OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
- OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel func_mcasp_abe_gfclk_sel[] = {
- { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates },
- { .parent = &pad_clks_ck, .rates = div_1_1_rates },
- { .parent = &slimbus_clk, .rates = div_1_2_rates },
- { .parent = NULL },
-};
-
-static const char *func_mcasp_abe_gfclk_parents[] = {
- "mcasp_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
-};
-
-DEFINE_CLK_OMAP_MUX(func_mcasp_abe_gfclk, "abe_clkdm", func_mcasp_abe_gfclk_sel,
- OMAP4430_CM1_ABE_MCASP_CLKCTRL, OMAP4430_CLKSEL_SOURCE_MASK,
- func_mcasp_abe_gfclk_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_MUX(mcbsp1_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
- OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
- OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
- OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel func_mcbsp1_gfclk_sel[] = {
- { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates },
- { .parent = &pad_clks_ck, .rates = div_1_1_rates },
- { .parent = &slimbus_clk, .rates = div_1_2_rates },
- { .parent = NULL },
-};
-
-static const char *func_mcbsp1_gfclk_parents[] = {
- "mcbsp1_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
-};
-
-DEFINE_CLK_OMAP_MUX(func_mcbsp1_gfclk, "abe_clkdm", func_mcbsp1_gfclk_sel,
- OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
- OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp1_gfclk_parents,
- func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_MUX(mcbsp2_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
- OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
- OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
- OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel func_mcbsp2_gfclk_sel[] = {
- { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates },
- { .parent = &pad_clks_ck, .rates = div_1_1_rates },
- { .parent = &slimbus_clk, .rates = div_1_2_rates },
- { .parent = NULL },
-};
-
-static const char *func_mcbsp2_gfclk_parents[] = {
- "mcbsp2_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
-};
-
-DEFINE_CLK_OMAP_MUX(func_mcbsp2_gfclk, "abe_clkdm", func_mcbsp2_gfclk_sel,
- OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
- OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp2_gfclk_parents,
- func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_MUX(mcbsp3_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
- OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
- OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
- OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel func_mcbsp3_gfclk_sel[] = {
- { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates },
- { .parent = &pad_clks_ck, .rates = div_1_1_rates },
- { .parent = &slimbus_clk, .rates = div_1_2_rates },
- { .parent = NULL },
-};
-
-static const char *func_mcbsp3_gfclk_parents[] = {
- "mcbsp3_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
-};
-
-DEFINE_CLK_OMAP_MUX(func_mcbsp3_gfclk, "abe_clkdm", func_mcbsp3_gfclk_sel,
- OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
- OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp3_gfclk_parents,
- func_dmic_abe_gfclk_ops);
-
-static const char *mcbsp4_sync_mux_ck_parents[] = {
- "func_96m_fclk", "per_abe_nc_fclk",
-};
-
-DEFINE_CLK_MUX(mcbsp4_sync_mux_ck, mcbsp4_sync_mux_ck_parents, NULL, 0x0,
- OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
- OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
- OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel per_mcbsp4_gfclk_sel[] = {
- { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates },
- { .parent = &pad_clks_ck, .rates = div_1_1_rates },
- { .parent = NULL },
-};
-
-static const char *per_mcbsp4_gfclk_parents[] = {
- "mcbsp4_sync_mux_ck", "pad_clks_ck",
-};
-
-DEFINE_CLK_OMAP_MUX(per_mcbsp4_gfclk, "l4_per_clkdm", per_mcbsp4_gfclk_sel,
- OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
- OMAP4430_CLKSEL_SOURCE_24_24_MASK, per_mcbsp4_gfclk_parents,
- func_dmic_abe_gfclk_ops);
-
-static const struct clksel hsmmc1_fclk_sel[] = {
- { .parent = &func_64m_fclk, .rates = div_1_0_rates },
- { .parent = &func_96m_fclk, .rates = div_1_1_rates },
- { .parent = NULL },
-};
-
-static const char *hsmmc1_fclk_parents[] = {
- "func_64m_fclk", "func_96m_fclk",
-};
-
-DEFINE_CLK_OMAP_MUX(hsmmc1_fclk, "l3_init_clkdm", hsmmc1_fclk_sel,
- OMAP4430_CM_L3INIT_MMC1_CLKCTRL, OMAP4430_CLKSEL_MASK,
- hsmmc1_fclk_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(hsmmc2_fclk, "l3_init_clkdm", hsmmc1_fclk_sel,
- OMAP4430_CM_L3INIT_MMC2_CLKCTRL, OMAP4430_CLKSEL_MASK,
- hsmmc1_fclk_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_GATE(ocp2scp_usb_phy_phy_48m, "func_48m_fclk", &func_48m_fclk, 0x0,
- OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
- OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(sha2md5_fck, "l3_div_ck", &l3_div_ck, 0x0,
- OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
- OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus1_fclk_1, "func_24m_clk", &func_24m_clk, 0x0,
- OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
- OMAP4430_OPTFCLKEN_FCLK1_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus1_fclk_0, "abe_24m_fclk", &abe_24m_fclk, 0x0,
- OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
- OMAP4430_OPTFCLKEN_FCLK0_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus1_fclk_2, "pad_clks_ck", &pad_clks_ck, 0x0,
- OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
- OMAP4430_OPTFCLKEN_FCLK2_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus1_slimbus_clk, "slimbus_clk", &slimbus_clk, 0x0,
- OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
- OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus2_fclk_1, "per_abe_24m_fclk", &per_abe_24m_fclk, 0x0,
- OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
- OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus2_fclk_0, "func_24mc_fclk", &func_24mc_fclk, 0x0,
- OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
- OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus2_slimbus_clk, "pad_slimbus_core_clks_ck",
- &pad_slimbus_core_clks_ck, 0x0,
- OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
- OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(smartreflex_core_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
- 0x0, OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
- OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(smartreflex_iva_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
- 0x0, OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
- OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(smartreflex_mpu_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
- 0x0, OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
- OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-static const struct clksel dmt1_clk_mux_sel[] = {
- { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
- { .parent = &sys_32k_ck, .rates = div_1_1_rates },
- { .parent = NULL },
-};
-
-DEFINE_CLK_OMAP_MUX(dmt1_clk_mux, "l4_wkup_clkdm", dmt1_clk_mux_sel,
- OMAP4430_CM_WKUP_TIMER1_CLKCTRL, OMAP4430_CLKSEL_MASK,
- abe_dpll_bypass_clk_mux_ck_parents,
- func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm10_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
- OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, OMAP4430_CLKSEL_MASK,
- abe_dpll_bypass_clk_mux_ck_parents,
- func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm11_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
- OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, OMAP4430_CLKSEL_MASK,
- abe_dpll_bypass_clk_mux_ck_parents,
- func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm2_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
- OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, OMAP4430_CLKSEL_MASK,
- abe_dpll_bypass_clk_mux_ck_parents,
- func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm3_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
- OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, OMAP4430_CLKSEL_MASK,
- abe_dpll_bypass_clk_mux_ck_parents,
- func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm4_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
- OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, OMAP4430_CLKSEL_MASK,
- abe_dpll_bypass_clk_mux_ck_parents,
- func_dmic_abe_gfclk_ops);
-
-static const struct clksel timer5_sync_mux_sel[] = {
- { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
- { .parent = &sys_32k_ck, .rates = div_1_1_rates },
- { .parent = NULL },
-};
-
-static const char *timer5_sync_mux_parents[] = {
- "syc_clk_div_ck", "sys_32k_ck",
-};
-
-DEFINE_CLK_OMAP_MUX(timer5_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
- OMAP4430_CM1_ABE_TIMER5_CLKCTRL, OMAP4430_CLKSEL_MASK,
- timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(timer6_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
- OMAP4430_CM1_ABE_TIMER6_CLKCTRL, OMAP4430_CLKSEL_MASK,
- timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(timer7_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
- OMAP4430_CM1_ABE_TIMER7_CLKCTRL, OMAP4430_CLKSEL_MASK,
- timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(timer8_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
- OMAP4430_CM1_ABE_TIMER8_CLKCTRL, OMAP4430_CLKSEL_MASK,
- timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm9_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
- OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, OMAP4430_CLKSEL_MASK,
- abe_dpll_bypass_clk_mux_ck_parents,
- func_dmic_abe_gfclk_ops);
-
-static struct clk usb_host_fs_fck;
-
-static const char *usb_host_fs_fck_parent_names[] = {
- "func_48mc_fclk",
-};
-
-static const struct clk_ops usb_host_fs_fck_ops = {
- .enable = &omap2_dflt_clk_enable,
- .disable = &omap2_dflt_clk_disable,
- .is_enabled = &omap2_dflt_clk_is_enabled,
-};
-
-static struct clk_hw_omap usb_host_fs_fck_hw = {
- .hw = {
- .clk = &usb_host_fs_fck,
- },
- .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
- .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT,
- .clkdm_name = "l3_init_clkdm",
-};
-
-DEFINE_STRUCT_CLK(usb_host_fs_fck, usb_host_fs_fck_parent_names,
- usb_host_fs_fck_ops);
-
-static const char *utmi_p1_gfclk_parents[] = {
- "init_60m_fclk", "xclk60mhsp1_ck",
-};
-
-DEFINE_CLK_MUX(utmi_p1_gfclk, utmi_p1_gfclk_parents, NULL, 0x0,
- OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
- OMAP4430_CLKSEL_UTMI_P1_SHIFT, OMAP4430_CLKSEL_UTMI_P1_WIDTH,
- 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_utmi_p1_clk, "utmi_p1_gfclk", &utmi_p1_gfclk, 0x0,
- OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
- OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT, 0x0, NULL);
-
-static const char *utmi_p2_gfclk_parents[] = {
- "init_60m_fclk", "xclk60mhsp2_ck",
-};
-
-DEFINE_CLK_MUX(utmi_p2_gfclk, utmi_p2_gfclk_parents, NULL, 0x0,
- OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
- OMAP4430_CLKSEL_UTMI_P2_SHIFT, OMAP4430_CLKSEL_UTMI_P2_WIDTH,
- 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_utmi_p2_clk, "utmi_p2_gfclk", &utmi_p2_gfclk, 0x0,
- OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
- OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_utmi_p3_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
- OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
- OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_hsic480m_p1_clk, "dpll_usb_m2_ck",
- &dpll_usb_m2_ck, 0x0,
- OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
- OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_hsic60m_p1_clk, "init_60m_fclk",
- &init_60m_fclk, 0x0,
- OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
- OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_hsic60m_p2_clk, "init_60m_fclk",
- &init_60m_fclk, 0x0,
- OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
- OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_hsic480m_p2_clk, "dpll_usb_m2_ck",
- &dpll_usb_m2_ck, 0x0,
- OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
- OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_func48mclk, "func_48mc_fclk", &func_48mc_fclk, 0x0,
- OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
- OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_fck, "init_60m_fclk", &init_60m_fclk, 0x0,
- OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
- OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-static const char *otg_60m_gfclk_parents[] = {
- "utmi_phy_clkout_ck", "xclk60motg_ck",
-};
-
-DEFINE_CLK_MUX(otg_60m_gfclk, otg_60m_gfclk_parents, NULL, 0x0,
- OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, OMAP4430_CLKSEL_60M_SHIFT,
- OMAP4430_CLKSEL_60M_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_otg_hs_xclk, "otg_60m_gfclk", &otg_60m_gfclk, 0x0,
- OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
- OMAP4430_OPTFCLKEN_XCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_otg_hs_ick, "l3_div_ck", &l3_div_ck, 0x0,
- OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
- OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_phy_cm_clk32k, "sys_32k_ck", &sys_32k_ck, 0x0,
- OMAP4430_CM_ALWON_USBPHY_CLKCTRL,
- OMAP4430_OPTFCLKEN_CLK32K_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_tll_hs_usb_ch2_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
- OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
- OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_tll_hs_usb_ch0_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
- OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
- OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_tll_hs_usb_ch1_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
- OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
- OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_tll_hs_ick, "l4_div_ck", &l4_div_ck, 0x0,
- OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
- OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
-
-static const struct clk_div_table usim_ck_rates[] = {
- { .div = 14, .val = 0 },
- { .div = 18, .val = 1 },
- { .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(usim_ck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0,
- OMAP4430_CM_WKUP_USIM_CLKCTRL,
- OMAP4430_CLKSEL_DIV_SHIFT, OMAP4430_CLKSEL_DIV_WIDTH,
- 0x0, usim_ck_rates, NULL);
-
-DEFINE_CLK_GATE(usim_fclk, "usim_ck", &usim_ck, 0x0,
- OMAP4430_CM_WKUP_USIM_CLKCTRL, OMAP4430_OPTFCLKEN_FCLK_SHIFT,
- 0x0, NULL);
-
-/* Remaining optional clocks */
-static const char *pmd_stm_clock_mux_ck_parents[] = {
- "sys_clkin_ck", "dpll_core_m6x2_ck", "tie_low_clock_ck",
-};
-
-DEFINE_CLK_MUX(pmd_stm_clock_mux_ck, pmd_stm_clock_mux_ck_parents, NULL, 0x0,
- OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, OMAP4430_PMD_STM_MUX_CTRL_SHIFT,
- OMAP4430_PMD_STM_MUX_CTRL_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_MUX(pmd_trace_clk_mux_ck, pmd_stm_clock_mux_ck_parents, NULL, 0x0,
- OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
- OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT,
- OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_DIVIDER(stm_clk_div_ck, "pmd_stm_clock_mux_ck",
- &pmd_stm_clock_mux_ck, 0x0, OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
- OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT,
- OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
- NULL);
-
-static const char *trace_clk_div_ck_parents[] = {
- "pmd_trace_clk_mux_ck",
-};
-
-static const struct clksel trace_clk_div_div[] = {
- { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates },
- { .parent = NULL },
-};
-
-static struct clk trace_clk_div_ck;
-
-static const struct clk_ops trace_clk_div_ck_ops = {
- .recalc_rate = &omap2_clksel_recalc,
- .set_rate = &omap2_clksel_set_rate,
- .round_rate = &omap2_clksel_round_rate,
- .init = &omap2_init_clk_clkdm,
- .enable = &omap2_clkops_enable_clkdm,
- .disable = &omap2_clkops_disable_clkdm,
-};
-
-static struct clk_hw_omap trace_clk_div_ck_hw = {
- .hw = {
- .clk = &trace_clk_div_ck,
- },
- .clkdm_name = "emu_sys_clkdm",
- .clksel = trace_clk_div_div,
- .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
- .clksel_mask = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
-};
-
-DEFINE_STRUCT_CLK(trace_clk_div_ck, trace_clk_div_ck_parents,
- trace_clk_div_ck_ops);
-
-/* SCRM aux clk nodes */
-
-static const struct clksel auxclk_src_sel[] = {
- { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
- { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates },
- { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates },
- { .parent = NULL },
-};
-
-static const char *auxclk_src_ck_parents[] = {
- "sys_clkin_ck", "dpll_core_m3x2_ck", "dpll_per_m3x2_ck",
-};
-
-static const struct clk_ops auxclk_src_ck_ops = {
- .enable = &omap2_dflt_clk_enable,
- .disable = &omap2_dflt_clk_disable,
- .is_enabled = &omap2_dflt_clk_is_enabled,
- .recalc_rate = &omap2_clksel_recalc,
- .get_parent = &omap2_clksel_find_parent_index,
-};
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk0_src_ck, NULL, auxclk_src_sel,
- OMAP4_SCRM_AUXCLK0, OMAP4_SRCSELECT_MASK,
- OMAP4_SCRM_AUXCLK0, OMAP4_ENABLE_SHIFT, NULL,
- auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk0_ck, "auxclk0_src_ck", &auxclk0_src_ck, 0x0,
- OMAP4_SCRM_AUXCLK0, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
- 0x0, NULL);
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk1_src_ck, NULL, auxclk_src_sel,
- OMAP4_SCRM_AUXCLK1, OMAP4_SRCSELECT_MASK,
- OMAP4_SCRM_AUXCLK1, OMAP4_ENABLE_SHIFT, NULL,
- auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk1_ck, "auxclk1_src_ck", &auxclk1_src_ck, 0x0,
- OMAP4_SCRM_AUXCLK1, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
- 0x0, NULL);
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk2_src_ck, NULL, auxclk_src_sel,
- OMAP4_SCRM_AUXCLK2, OMAP4_SRCSELECT_MASK,
- OMAP4_SCRM_AUXCLK2, OMAP4_ENABLE_SHIFT, NULL,
- auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk2_ck, "auxclk2_src_ck", &auxclk2_src_ck, 0x0,
- OMAP4_SCRM_AUXCLK2, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
- 0x0, NULL);
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk3_src_ck, NULL, auxclk_src_sel,
- OMAP4_SCRM_AUXCLK3, OMAP4_SRCSELECT_MASK,
- OMAP4_SCRM_AUXCLK3, OMAP4_ENABLE_SHIFT, NULL,
- auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk3_ck, "auxclk3_src_ck", &auxclk3_src_ck, 0x0,
- OMAP4_SCRM_AUXCLK3, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
- 0x0, NULL);
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk4_src_ck, NULL, auxclk_src_sel,
- OMAP4_SCRM_AUXCLK4, OMAP4_SRCSELECT_MASK,
- OMAP4_SCRM_AUXCLK4, OMAP4_ENABLE_SHIFT, NULL,
- auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk4_ck, "auxclk4_src_ck", &auxclk4_src_ck, 0x0,
- OMAP4_SCRM_AUXCLK4, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
- 0x0, NULL);
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk5_src_ck, NULL, auxclk_src_sel,
- OMAP4_SCRM_AUXCLK5, OMAP4_SRCSELECT_MASK,
- OMAP4_SCRM_AUXCLK5, OMAP4_ENABLE_SHIFT, NULL,
- auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk5_ck, "auxclk5_src_ck", &auxclk5_src_ck, 0x0,
- OMAP4_SCRM_AUXCLK5, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
- 0x0, NULL);
-
-static const char *auxclkreq_ck_parents[] = {
- "auxclk0_ck", "auxclk1_ck", "auxclk2_ck", "auxclk3_ck", "auxclk4_ck",
- "auxclk5_ck",
-};
-
-DEFINE_CLK_MUX(auxclkreq0_ck, auxclkreq_ck_parents, NULL, 0x0,
- OMAP4_SCRM_AUXCLKREQ0, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
- 0x0, NULL);
-
-DEFINE_CLK_MUX(auxclkreq1_ck, auxclkreq_ck_parents, NULL, 0x0,
- OMAP4_SCRM_AUXCLKREQ1, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
- 0x0, NULL);
-
-DEFINE_CLK_MUX(auxclkreq2_ck, auxclkreq_ck_parents, NULL, 0x0,
- OMAP4_SCRM_AUXCLKREQ2, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
- 0x0, NULL);
-
-DEFINE_CLK_MUX(auxclkreq3_ck, auxclkreq_ck_parents, NULL, 0x0,
- OMAP4_SCRM_AUXCLKREQ3, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
- 0x0, NULL);
-
-DEFINE_CLK_MUX(auxclkreq4_ck, auxclkreq_ck_parents, NULL, 0x0,
- OMAP4_SCRM_AUXCLKREQ4, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
- 0x0, NULL);
-
-DEFINE_CLK_MUX(auxclkreq5_ck, auxclkreq_ck_parents, NULL, 0x0,
- OMAP4_SCRM_AUXCLKREQ5, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
- 0x0, NULL);
-
-/*
- * clocks specific to omap4460
- */
-static struct omap_clk omap446x_clks[] = {
- CLK(NULL, "div_ts_ck", &div_ts_ck),
- CLK(NULL, "bandgap_ts_fclk", &bandgap_ts_fclk),
-};
-
-/*
- * clocks specific to omap4430
- */
-static struct omap_clk omap443x_clks[] = {
- CLK(NULL, "bandgap_fclk", &bandgap_fclk),
-};
-
-/*
- * clocks common to omap44xx
- */
-static struct omap_clk omap44xx_clks[] = {
- CLK(NULL, "extalt_clkin_ck", &extalt_clkin_ck),
- CLK(NULL, "pad_clks_src_ck", &pad_clks_src_ck),
- CLK(NULL, "pad_clks_ck", &pad_clks_ck),
- CLK(NULL, "pad_slimbus_core_clks_ck", &pad_slimbus_core_clks_ck),
- CLK(NULL, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck),
- CLK(NULL, "slimbus_src_clk", &slimbus_src_clk),
- CLK(NULL, "slimbus_clk", &slimbus_clk),
- CLK(NULL, "sys_32k_ck", &sys_32k_ck),
- CLK(NULL, "virt_12000000_ck", &virt_12000000_ck),
- CLK(NULL, "virt_13000000_ck", &virt_13000000_ck),
- CLK(NULL, "virt_16800000_ck", &virt_16800000_ck),
- CLK(NULL, "virt_19200000_ck", &virt_19200000_ck),
- CLK(NULL, "virt_26000000_ck", &virt_26000000_ck),
- CLK(NULL, "virt_27000000_ck", &virt_27000000_ck),
- CLK(NULL, "virt_38400000_ck", &virt_38400000_ck),
- CLK(NULL, "sys_clkin_ck", &sys_clkin_ck),
- CLK(NULL, "tie_low_clock_ck", &tie_low_clock_ck),
- CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck),
- CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck),
- CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck),
- CLK(NULL, "xclk60motg_ck", &xclk60motg_ck),
- CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck),
- CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck),
- CLK(NULL, "dpll_abe_ck", &dpll_abe_ck),
- CLK(NULL, "dpll_abe_x2_ck", &dpll_abe_x2_ck),
- CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck),
- CLK(NULL, "abe_24m_fclk", &abe_24m_fclk),
- CLK(NULL, "abe_clk", &abe_clk),
- CLK(NULL, "aess_fclk", &aess_fclk),
- CLK(NULL, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck),
- CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck),
- CLK(NULL, "dpll_core_ck", &dpll_core_ck),
- CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck),
- CLK(NULL, "dpll_core_m6x2_ck", &dpll_core_m6x2_ck),
- CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck),
- CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck),
- CLK(NULL, "ddrphy_ck", &ddrphy_ck),
- CLK(NULL, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck),
- CLK(NULL, "div_core_ck", &div_core_ck),
- CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk),
- CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk),
- CLK(NULL, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck),
- CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck),
- CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck),
- CLK(NULL, "dpll_core_m3x2_ck", &dpll_core_m3x2_ck),
- CLK(NULL, "dpll_core_m7x2_ck", &dpll_core_m7x2_ck),
- CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck),
- CLK(NULL, "dpll_iva_ck", &dpll_iva_ck),
- CLK(NULL, "dpll_iva_x2_ck", &dpll_iva_x2_ck),
- CLK(NULL, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck),
- CLK(NULL, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck),
- CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck),
- CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck),
- CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck),
- CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck),
- CLK(NULL, "dpll_per_ck", &dpll_per_ck),
- CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck),
- CLK(NULL, "dpll_per_x2_ck", &dpll_per_x2_ck),
- CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck),
- CLK(NULL, "dpll_per_m3x2_ck", &dpll_per_m3x2_ck),
- CLK(NULL, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck),
- CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck),
- CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck),
- CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck),
- CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck),
- CLK(NULL, "dpll_usb_ck", &dpll_usb_ck),
- CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck),
- CLK(NULL, "dpll_usb_m2_ck", &dpll_usb_m2_ck),
- CLK(NULL, "ducati_clk_mux_ck", &ducati_clk_mux_ck),
- CLK(NULL, "func_12m_fclk", &func_12m_fclk),
- CLK(NULL, "func_24m_clk", &func_24m_clk),
- CLK(NULL, "func_24mc_fclk", &func_24mc_fclk),
- CLK(NULL, "func_48m_fclk", &func_48m_fclk),
- CLK(NULL, "func_48mc_fclk", &func_48mc_fclk),
- CLK(NULL, "func_64m_fclk", &func_64m_fclk),
- CLK(NULL, "func_96m_fclk", &func_96m_fclk),
- CLK(NULL, "init_60m_fclk", &init_60m_fclk),
- CLK(NULL, "l3_div_ck", &l3_div_ck),
- CLK(NULL, "l4_div_ck", &l4_div_ck),
- CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck),
- CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck),
- CLK("smp_twd", NULL, &mpu_periphclk),
- CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk),
- CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk),
- CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk),
- CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck),
- CLK(NULL, "aes1_fck", &aes1_fck),
- CLK(NULL, "aes2_fck", &aes2_fck),
- CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck),
- CLK(NULL, "func_dmic_abe_gfclk", &func_dmic_abe_gfclk),
- CLK(NULL, "dss_sys_clk", &dss_sys_clk),
- CLK(NULL, "dss_tv_clk", &dss_tv_clk),
- CLK(NULL, "dss_dss_clk", &dss_dss_clk),
- CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk),
- CLK(NULL, "dss_fck", &dss_fck),
- CLK("omapdss_dss", "ick", &dss_fck),
- CLK(NULL, "fdif_fck", &fdif_fck),
- CLK(NULL, "gpio1_dbclk", &gpio1_dbclk),
- CLK(NULL, "gpio2_dbclk", &gpio2_dbclk),
- CLK(NULL, "gpio3_dbclk", &gpio3_dbclk),
- CLK(NULL, "gpio4_dbclk", &gpio4_dbclk),
- CLK(NULL, "gpio5_dbclk", &gpio5_dbclk),
- CLK(NULL, "gpio6_dbclk", &gpio6_dbclk),
- CLK(NULL, "sgx_clk_mux", &sgx_clk_mux),
- CLK(NULL, "hsi_fck", &hsi_fck),
- CLK(NULL, "iss_ctrlclk", &iss_ctrlclk),
- CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck),
- CLK(NULL, "func_mcasp_abe_gfclk", &func_mcasp_abe_gfclk),
- CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck),
- CLK(NULL, "func_mcbsp1_gfclk", &func_mcbsp1_gfclk),
- CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck),
- CLK(NULL, "func_mcbsp2_gfclk", &func_mcbsp2_gfclk),
- CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck),
- CLK(NULL, "func_mcbsp3_gfclk", &func_mcbsp3_gfclk),
- CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck),
- CLK(NULL, "per_mcbsp4_gfclk", &per_mcbsp4_gfclk),
- CLK(NULL, "hsmmc1_fclk", &hsmmc1_fclk),
- CLK(NULL, "hsmmc2_fclk", &hsmmc2_fclk),
- CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m),
- CLK(NULL, "sha2md5_fck", &sha2md5_fck),
- CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1),
- CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0),
- CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2),
- CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk),
- CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1),
- CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0),
- CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk),
- CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck),
- CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck),
- CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck),
- CLK(NULL, "dmt1_clk_mux", &dmt1_clk_mux),
- CLK(NULL, "cm2_dm10_mux", &cm2_dm10_mux),
- CLK(NULL, "cm2_dm11_mux", &cm2_dm11_mux),
- CLK(NULL, "cm2_dm2_mux", &cm2_dm2_mux),
- CLK(NULL, "cm2_dm3_mux", &cm2_dm3_mux),
- CLK(NULL, "cm2_dm4_mux", &cm2_dm4_mux),
- CLK(NULL, "timer5_sync_mux", &timer5_sync_mux),
- CLK(NULL, "timer6_sync_mux", &timer6_sync_mux),
- CLK(NULL, "timer7_sync_mux", &timer7_sync_mux),
- CLK(NULL, "timer8_sync_mux", &timer8_sync_mux),
- CLK(NULL, "cm2_dm9_mux", &cm2_dm9_mux),
- CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck),
- CLK("usbhs_omap", "fs_fck", &usb_host_fs_fck),
- CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk),
- CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk),
- CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk),
- CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk),
- CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk),
- CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk),
- CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk),
- CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk),
- CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk),
- CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk),
- CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck),
- CLK("usbhs_omap", "hs_fck", &usb_host_hs_fck),
- CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk),
- CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk),
- CLK(NULL, "usb_otg_hs_ick", &usb_otg_hs_ick),
- CLK("musb-omap2430", "ick", &usb_otg_hs_ick),
- CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k),
- CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk),
- CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk),
- CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk),
- CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick),
- CLK("usbhs_omap", "usbtll_ick", &usb_tll_hs_ick),
- CLK("usbhs_tll", "usbtll_ick", &usb_tll_hs_ick),
- CLK(NULL, "usim_ck", &usim_ck),
- CLK(NULL, "usim_fclk", &usim_fclk),
- CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck),
- CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck),
- CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck),
- CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck),
- CLK(NULL, "auxclk0_src_ck", &auxclk0_src_ck),
- CLK(NULL, "auxclk0_ck", &auxclk0_ck),
- CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck),
- CLK(NULL, "auxclk1_src_ck", &auxclk1_src_ck),
- CLK(NULL, "auxclk1_ck", &auxclk1_ck),
- CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck),
- CLK(NULL, "auxclk2_src_ck", &auxclk2_src_ck),
- CLK(NULL, "auxclk2_ck", &auxclk2_ck),
- CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck),
- CLK(NULL, "auxclk3_src_ck", &auxclk3_src_ck),
- CLK(NULL, "auxclk3_ck", &auxclk3_ck),
- CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck),
- CLK(NULL, "auxclk4_src_ck", &auxclk4_src_ck),
- CLK(NULL, "auxclk4_ck", &auxclk4_ck),
- CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck),
- CLK(NULL, "auxclk5_src_ck", &auxclk5_src_ck),
- CLK(NULL, "auxclk5_ck", &auxclk5_ck),
- CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck),
- CLK("50000000.gpmc", "fck", &dummy_ck),
- CLK("omap_i2c.1", "ick", &dummy_ck),
- CLK("omap_i2c.2", "ick", &dummy_ck),
- CLK("omap_i2c.3", "ick", &dummy_ck),
- CLK("omap_i2c.4", "ick", &dummy_ck),
- CLK(NULL, "mailboxes_ick", &dummy_ck),
- CLK("omap_hsmmc.0", "ick", &dummy_ck),
- CLK("omap_hsmmc.1", "ick", &dummy_ck),
- CLK("omap_hsmmc.2", "ick", &dummy_ck),
- CLK("omap_hsmmc.3", "ick", &dummy_ck),
- CLK("omap_hsmmc.4", "ick", &dummy_ck),
- CLK("omap-mcbsp.1", "ick", &dummy_ck),
- CLK("omap-mcbsp.2", "ick", &dummy_ck),
- CLK("omap-mcbsp.3", "ick", &dummy_ck),
- CLK("omap-mcbsp.4", "ick", &dummy_ck),
- CLK("omap2_mcspi.1", "ick", &dummy_ck),
- CLK("omap2_mcspi.2", "ick", &dummy_ck),
- CLK("omap2_mcspi.3", "ick", &dummy_ck),
- CLK("omap2_mcspi.4", "ick", &dummy_ck),
- CLK(NULL, "uart1_ick", &dummy_ck),
- CLK(NULL, "uart2_ick", &dummy_ck),
- CLK(NULL, "uart3_ick", &dummy_ck),
- CLK(NULL, "uart4_ick", &dummy_ck),
- CLK("usbhs_omap", "usbhost_ick", &dummy_ck),
- CLK("usbhs_omap", "usbtll_fck", &dummy_ck),
- CLK("usbhs_tll", "usbtll_fck", &dummy_ck),
- CLK("omap_wdt", "ick", &dummy_ck),
- CLK(NULL, "timer_32k_ck", &sys_32k_ck),
- /* TODO: Remove "omap_timer.X" aliases once DT migration is complete */
- CLK("omap_timer.1", "timer_sys_ck", &sys_clkin_ck),
- CLK("omap_timer.2", "timer_sys_ck", &sys_clkin_ck),
- CLK("omap_timer.3", "timer_sys_ck", &sys_clkin_ck),
- CLK("omap_timer.4", "timer_sys_ck", &sys_clkin_ck),
- CLK("omap_timer.9", "timer_sys_ck", &sys_clkin_ck),
- CLK("omap_timer.10", "timer_sys_ck", &sys_clkin_ck),
- CLK("omap_timer.11", "timer_sys_ck", &sys_clkin_ck),
- CLK("omap_timer.5", "timer_sys_ck", &syc_clk_div_ck),
- CLK("omap_timer.6", "timer_sys_ck", &syc_clk_div_ck),
- CLK("omap_timer.7", "timer_sys_ck", &syc_clk_div_ck),
- CLK("omap_timer.8", "timer_sys_ck", &syc_clk_div_ck),
- CLK("4a318000.timer", "timer_sys_ck", &sys_clkin_ck),
- CLK("48032000.timer", "timer_sys_ck", &sys_clkin_ck),
- CLK("48034000.timer", "timer_sys_ck", &sys_clkin_ck),
- CLK("48036000.timer", "timer_sys_ck", &sys_clkin_ck),
- CLK("4803e000.timer", "timer_sys_ck", &sys_clkin_ck),
- CLK("48086000.timer", "timer_sys_ck", &sys_clkin_ck),
- CLK("48088000.timer", "timer_sys_ck", &sys_clkin_ck),
- CLK("40138000.timer", "timer_sys_ck", &syc_clk_div_ck),
- CLK("4013a000.timer", "timer_sys_ck", &syc_clk_div_ck),
- CLK("4013c000.timer", "timer_sys_ck", &syc_clk_div_ck),
- CLK("4013e000.timer", "timer_sys_ck", &syc_clk_div_ck),
- CLK(NULL, "cpufreq_ck", &dpll_mpu_ck),
-};
-
-int __init omap4xxx_clk_init(void)
-{
- int rc;
-
- if (cpu_is_omap443x()) {
- cpu_mask = RATE_IN_4430;
- omap_clocks_register(omap443x_clks, ARRAY_SIZE(omap443x_clks));
- } else if (cpu_is_omap446x() || cpu_is_omap447x()) {
- cpu_mask = RATE_IN_4460 | RATE_IN_4430;
- omap_clocks_register(omap446x_clks, ARRAY_SIZE(omap446x_clks));
- if (cpu_is_omap447x())
- pr_warn("WARNING: OMAP4470 clock data incomplete!\n");
- } else {
- return 0;
- }
-
- omap_clocks_register(omap44xx_clks, ARRAY_SIZE(omap44xx_clks));
-
- omap2_clk_disable_autoidle_all();
-
- /*
- * A set rate of ABE DPLL inturn triggers a set rate of USB DPLL
- * when its in bypass. So always lock USB before ABE DPLL.
- */
- /*
- * Lock USB DPLL on OMAP4 devices so that the L3INIT power
- * domain can transition to retention state when not in use.
- */
- rc = clk_set_rate(&dpll_usb_ck, OMAP4_DPLL_USB_DEFFREQ);
- if (rc)
- pr_err("%s: failed to configure USB DPLL!\n", __func__);
-
- /*
- * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power
- * state when turning the ABE clock domain. Workaround this by
- * locking the ABE DPLL on boot.
- * Lock the ABE DPLL in any case to avoid issues with audio.
- */
- rc = clk_set_parent(&abe_dpll_refclk_mux_ck, &sys_32k_ck);
- if (!rc)
- rc = clk_set_rate(&dpll_abe_ck, OMAP4_DPLL_ABE_DEFFREQ);
- if (rc)
- pr_err("%s: failed to configure ABE DPLL!\n", __func__);
-
- return 0;
-}
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index f0986a5..1ed6dd7 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -2,4 +2,5 @@ ifneq ($(CONFIG_OF),)
obj-y += clk.o dpll.o autoidle.o divider.o \
fixed-factor.o gate.o clockdomain.o \
mux-gate.o mux.o
+obj-$(CONFIG_ARCH_OMAP4) += clk-44xx.o
endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 12/36] ARM: OMAP4: remove old clock data and link in new clock init code
@ 2013-09-25 8:48 ` Tero Kristo
0 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-arm-kernel
OMAP4 clocks have now been moved to DT, thus remove the old data file
and use the new init code under drivers/clk/omap/clk-44xx.c.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/mach-omap2/Makefile | 2 +-
arch/arm/mach-omap2/cclock44xx_data.c | 1734 ---------------------------------
drivers/clk/ti/Makefile | 1 +
3 files changed, 2 insertions(+), 1735 deletions(-)
delete mode 100644 arch/arm/mach-omap2/cclock44xx_data.c
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index afb457c..f518360 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -184,7 +184,7 @@ obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o
obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o
obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o cclock3xxx_data.o
obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o
-obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) cclock44xx_data.o
+obj-$(CONFIG_ARCH_OMAP4) += $(clock-common)
obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o
obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o
obj-$(CONFIG_SOC_AM33XX) += cclock33xx_data.o
diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c
deleted file mode 100644
index b237950..0000000
--- a/arch/arm/mach-omap2/cclock44xx_data.c
+++ /dev/null
@@ -1,1734 +0,0 @@
-/*
- * OMAP4 Clock data
- *
- * Copyright (C) 2009-2012 Texas Instruments, Inc.
- * Copyright (C) 2009-2010 Nokia Corporation
- *
- * Paul Walmsley (paul at pwsan.com)
- * Rajendra Nayak (rnayak at ti.com)
- * Benoit Cousson (b-cousson at ti.com)
- * Mike Turquette (mturquette at ti.com)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * XXX Some of the ES1 clocks have been removed/changed; once support
- * is added for discriminating clocks by ES level, these should be added back
- * in.
- *
- * XXX All of the remaining MODULEMODE clock nodes should be removed
- * once the drivers are updated to use pm_runtime or to use the appropriate
- * upstream clock node for rate/parent selection.
- */
-
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/clk-private.h>
-#include <linux/clkdev.h>
-#include <linux/io.h>
-
-#include "soc.h"
-#include "iomap.h"
-#include "clock.h"
-#include "clock44xx.h"
-#include "cm1_44xx.h"
-#include "cm2_44xx.h"
-#include "cm-regbits-44xx.h"
-#include "prm44xx.h"
-#include "prm-regbits-44xx.h"
-#include "control.h"
-#include "scrm44xx.h"
-
-/* OMAP4 modulemode control */
-#define OMAP4430_MODULEMODE_HWCTRL_SHIFT 0
-#define OMAP4430_MODULEMODE_SWCTRL_SHIFT 1
-
-/*
- * OMAP4 ABE DPLL default frequency. In OMAP4460 TRM version V, section
- * "3.6.3.2.3 CM1_ABE Clock Generator" states that the "DPLL_ABE_X2_CLK
- * must be set to 196.608 MHz" and hence, the DPLL locked frequency is
- * half of this value.
- */
-#define OMAP4_DPLL_ABE_DEFFREQ 98304000
-
-/*
- * OMAP4 USB DPLL default frequency. In OMAP4430 TRM version V, section
- * "3.6.3.9.5 DPLL_USB Preferred Settings" shows that the preferred
- * locked frequency for the USB DPLL is 960MHz.
- */
-#define OMAP4_DPLL_USB_DEFFREQ 960000000
-
-/* Root clocks */
-
-DEFINE_CLK_FIXED_RATE(extalt_clkin_ck, CLK_IS_ROOT, 59000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(pad_clks_src_ck, CLK_IS_ROOT, 12000000, 0x0);
-
-DEFINE_CLK_GATE(pad_clks_ck, "pad_clks_src_ck", &pad_clks_src_ck, 0x0,
- OMAP4430_CM_CLKSEL_ABE, OMAP4430_PAD_CLKS_GATE_SHIFT,
- 0x0, NULL);
-
-DEFINE_CLK_FIXED_RATE(pad_slimbus_core_clks_ck, CLK_IS_ROOT, 12000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(secure_32k_clk_src_ck, CLK_IS_ROOT, 32768, 0x0);
-
-DEFINE_CLK_FIXED_RATE(slimbus_src_clk, CLK_IS_ROOT, 12000000, 0x0);
-
-DEFINE_CLK_GATE(slimbus_clk, "slimbus_src_clk", &slimbus_src_clk, 0x0,
- OMAP4430_CM_CLKSEL_ABE, OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
- 0x0, NULL);
-
-DEFINE_CLK_FIXED_RATE(sys_32k_ck, CLK_IS_ROOT, 32768, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_12000000_ck, CLK_IS_ROOT, 12000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_13000000_ck, CLK_IS_ROOT, 13000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_16800000_ck, CLK_IS_ROOT, 16800000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_27000000_ck, CLK_IS_ROOT, 27000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_38400000_ck, CLK_IS_ROOT, 38400000, 0x0);
-
-static const char *sys_clkin_ck_parents[] = {
- "virt_12000000_ck", "virt_13000000_ck", "virt_16800000_ck",
- "virt_19200000_ck", "virt_26000000_ck", "virt_27000000_ck",
- "virt_38400000_ck",
-};
-
-DEFINE_CLK_MUX(sys_clkin_ck, sys_clkin_ck_parents, NULL, 0x0,
- OMAP4430_CM_SYS_CLKSEL, OMAP4430_SYS_CLKSEL_SHIFT,
- OMAP4430_SYS_CLKSEL_WIDTH, CLK_MUX_INDEX_ONE, NULL);
-
-DEFINE_CLK_FIXED_RATE(tie_low_clock_ck, CLK_IS_ROOT, 0, 0x0);
-
-DEFINE_CLK_FIXED_RATE(utmi_phy_clkout_ck, CLK_IS_ROOT, 60000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(xclk60mhsp1_ck, CLK_IS_ROOT, 60000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(xclk60mhsp2_ck, CLK_IS_ROOT, 60000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(xclk60motg_ck, CLK_IS_ROOT, 60000000, 0x0);
-
-/* Module clocks and DPLL outputs */
-
-static const char *abe_dpll_bypass_clk_mux_ck_parents[] = {
- "sys_clkin_ck", "sys_32k_ck",
-};
-
-DEFINE_CLK_MUX(abe_dpll_bypass_clk_mux_ck, abe_dpll_bypass_clk_mux_ck_parents,
- NULL, 0x0, OMAP4430_CM_L4_WKUP_CLKSEL, OMAP4430_CLKSEL_SHIFT,
- OMAP4430_CLKSEL_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_MUX(abe_dpll_refclk_mux_ck, abe_dpll_bypass_clk_mux_ck_parents, NULL,
- 0x0, OMAP4430_CM_ABE_PLL_REF_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
- OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
-
-/* DPLL_ABE */
-static struct dpll_data dpll_abe_dd = {
- .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_ABE,
- .clk_bypass = &abe_dpll_bypass_clk_mux_ck,
- .clk_ref = &abe_dpll_refclk_mux_ck,
- .control_reg = OMAP4430_CM_CLKMODE_DPLL_ABE,
- .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
- .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_ABE,
- .idlest_reg = OMAP4430_CM_IDLEST_DPLL_ABE,
- .mult_mask = OMAP4430_DPLL_MULT_MASK,
- .div1_mask = OMAP4430_DPLL_DIV_MASK,
- .enable_mask = OMAP4430_DPLL_EN_MASK,
- .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
- .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
- .m4xen_mask = OMAP4430_DPLL_REGM4XEN_MASK,
- .lpmode_mask = OMAP4430_DPLL_LPMODE_EN_MASK,
- .max_multiplier = 2047,
- .max_divider = 128,
- .min_divider = 1,
-};
-
-
-static const char *dpll_abe_ck_parents[] = {
- "abe_dpll_refclk_mux_ck",
-};
-
-static struct clk dpll_abe_ck;
-
-static const struct clk_ops dpll_abe_ck_ops = {
- .enable = &omap3_noncore_dpll_enable,
- .disable = &omap3_noncore_dpll_disable,
- .recalc_rate = &omap4_dpll_regm4xen_recalc,
- .round_rate = &omap4_dpll_regm4xen_round_rate,
- .set_rate = &omap3_noncore_dpll_set_rate,
- .get_parent = &omap2_init_dpll_parent,
-};
-
-static struct clk_hw_omap dpll_abe_ck_hw = {
- .hw = {
- .clk = &dpll_abe_ck,
- },
- .dpll_data = &dpll_abe_dd,
- .ops = &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_abe_ck, dpll_abe_ck_parents, dpll_abe_ck_ops);
-
-static const char *dpll_abe_x2_ck_parents[] = {
- "dpll_abe_ck",
-};
-
-static struct clk dpll_abe_x2_ck;
-
-static const struct clk_ops dpll_abe_x2_ck_ops = {
- .recalc_rate = &omap3_clkoutx2_recalc,
-};
-
-static struct clk_hw_omap dpll_abe_x2_ck_hw = {
- .hw = {
- .clk = &dpll_abe_x2_ck,
- },
- .flags = CLOCK_CLKOUTX2,
- .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
- .ops = &clkhwops_omap4_dpllmx,
-};
-
-DEFINE_STRUCT_CLK(dpll_abe_x2_ck, dpll_abe_x2_ck_parents, dpll_abe_x2_ck_ops);
-
-static const struct clk_ops omap_hsdivider_ops = {
- .set_rate = &omap2_clksel_set_rate,
- .recalc_rate = &omap2_clksel_recalc,
- .round_rate = &omap2_clksel_round_rate,
-};
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_abe_m2x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck,
- 0x0, OMAP4430_CM_DIV_M2_DPLL_ABE,
- OMAP4430_DPLL_CLKOUT_DIV_MASK);
-
-DEFINE_CLK_FIXED_FACTOR(abe_24m_fclk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck,
- 0x0, 1, 8);
-
-DEFINE_CLK_DIVIDER(abe_clk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, 0x0,
- OMAP4430_CM_CLKSEL_ABE, OMAP4430_CLKSEL_OPP_SHIFT,
- OMAP4430_CLKSEL_OPP_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
-
-DEFINE_CLK_DIVIDER(aess_fclk, "abe_clk", &abe_clk, 0x0,
- OMAP4430_CM1_ABE_AESS_CLKCTRL,
- OMAP4430_CLKSEL_AESS_FCLK_SHIFT,
- OMAP4430_CLKSEL_AESS_FCLK_WIDTH,
- 0x0, NULL);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_abe_m3x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck,
- 0x0, OMAP4430_CM_DIV_M3_DPLL_ABE,
- OMAP4430_DPLL_CLKOUTHIF_DIV_MASK);
-
-static const char *core_hsd_byp_clk_mux_ck_parents[] = {
- "sys_clkin_ck", "dpll_abe_m3x2_ck",
-};
-
-DEFINE_CLK_MUX(core_hsd_byp_clk_mux_ck, core_hsd_byp_clk_mux_ck_parents, NULL,
- 0x0, OMAP4430_CM_CLKSEL_DPLL_CORE,
- OMAP4430_DPLL_BYP_CLKSEL_SHIFT, OMAP4430_DPLL_BYP_CLKSEL_WIDTH,
- 0x0, NULL);
-
-/* DPLL_CORE */
-static struct dpll_data dpll_core_dd = {
- .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_CORE,
- .clk_bypass = &core_hsd_byp_clk_mux_ck,
- .clk_ref = &sys_clkin_ck,
- .control_reg = OMAP4430_CM_CLKMODE_DPLL_CORE,
- .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
- .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_CORE,
- .idlest_reg = OMAP4430_CM_IDLEST_DPLL_CORE,
- .mult_mask = OMAP4430_DPLL_MULT_MASK,
- .div1_mask = OMAP4430_DPLL_DIV_MASK,
- .enable_mask = OMAP4430_DPLL_EN_MASK,
- .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
- .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
- .max_multiplier = 2047,
- .max_divider = 128,
- .min_divider = 1,
-};
-
-
-static const char *dpll_core_ck_parents[] = {
- "sys_clkin_ck", "core_hsd_byp_clk_mux_ck"
-};
-
-static struct clk dpll_core_ck;
-
-static const struct clk_ops dpll_core_ck_ops = {
- .recalc_rate = &omap3_dpll_recalc,
- .get_parent = &omap2_init_dpll_parent,
-};
-
-static struct clk_hw_omap dpll_core_ck_hw = {
- .hw = {
- .clk = &dpll_core_ck,
- },
- .dpll_data = &dpll_core_dd,
- .ops = &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops);
-
-static const char *dpll_core_x2_ck_parents[] = {
- "dpll_core_ck",
-};
-
-static struct clk dpll_core_x2_ck;
-
-static struct clk_hw_omap dpll_core_x2_ck_hw = {
- .hw = {
- .clk = &dpll_core_x2_ck,
- },
-};
-
-DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_abe_x2_ck_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m6x2_ck, "dpll_core_x2_ck",
- &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M6_DPLL_CORE,
- OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m2_ck, "dpll_core_ck", &dpll_core_ck, 0x0,
- OMAP4430_CM_DIV_M2_DPLL_CORE,
- OMAP4430_DPLL_CLKOUT_DIV_MASK);
-
-DEFINE_CLK_FIXED_FACTOR(ddrphy_ck, "dpll_core_m2_ck", &dpll_core_m2_ck, 0x0, 1,
- 2);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m5x2_ck, "dpll_core_x2_ck",
- &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M5_DPLL_CORE,
- OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK);
-
-DEFINE_CLK_DIVIDER(div_core_ck, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, 0x0,
- OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_CORE_SHIFT,
- OMAP4430_CLKSEL_CORE_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_DIVIDER(div_iva_hs_clk, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck,
- 0x0, OMAP4430_CM_BYPCLK_DPLL_IVA, OMAP4430_CLKSEL_0_1_SHIFT,
- OMAP4430_CLKSEL_0_1_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
-
-DEFINE_CLK_DIVIDER(div_mpu_hs_clk, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck,
- 0x0, OMAP4430_CM_BYPCLK_DPLL_MPU, OMAP4430_CLKSEL_0_1_SHIFT,
- OMAP4430_CLKSEL_0_1_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m4x2_ck, "dpll_core_x2_ck",
- &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M4_DPLL_CORE,
- OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK);
-
-DEFINE_CLK_FIXED_FACTOR(dll_clk_div_ck, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck,
- 0x0, 1, 2);
-
-DEFINE_CLK_DIVIDER(dpll_abe_m2_ck, "dpll_abe_ck", &dpll_abe_ck, 0x0,
- OMAP4430_CM_DIV_M2_DPLL_ABE, OMAP4430_DPLL_CLKOUT_DIV_SHIFT,
- OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
-
-static const struct clk_ops dpll_hsd_ops = {
- .enable = &omap2_dflt_clk_enable,
- .disable = &omap2_dflt_clk_disable,
- .is_enabled = &omap2_dflt_clk_is_enabled,
- .recalc_rate = &omap2_clksel_recalc,
- .get_parent = &omap2_clksel_find_parent_index,
- .set_parent = &omap2_clksel_set_parent,
- .init = &omap2_init_clk_clkdm,
-};
-
-static const struct clk_ops func_dmic_abe_gfclk_ops = {
- .recalc_rate = &omap2_clksel_recalc,
- .get_parent = &omap2_clksel_find_parent_index,
- .set_parent = &omap2_clksel_set_parent,
-};
-
-static const char *dpll_core_m3x2_ck_parents[] = {
- "dpll_core_x2_ck",
-};
-
-static const struct clksel dpll_core_m3x2_div[] = {
- { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
- { .parent = NULL },
-};
-
-/* XXX Missing round_rate, set_rate in ops */
-DEFINE_CLK_OMAP_MUX_GATE(dpll_core_m3x2_ck, NULL, dpll_core_m3x2_div,
- OMAP4430_CM_DIV_M3_DPLL_CORE,
- OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
- OMAP4430_CM_DIV_M3_DPLL_CORE,
- OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL,
- dpll_core_m3x2_ck_parents, dpll_hsd_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m7x2_ck, "dpll_core_x2_ck",
- &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M7_DPLL_CORE,
- OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK);
-
-static const char *iva_hsd_byp_clk_mux_ck_parents[] = {
- "sys_clkin_ck", "div_iva_hs_clk",
-};
-
-DEFINE_CLK_MUX(iva_hsd_byp_clk_mux_ck, iva_hsd_byp_clk_mux_ck_parents, NULL,
- 0x0, OMAP4430_CM_CLKSEL_DPLL_IVA, OMAP4430_DPLL_BYP_CLKSEL_SHIFT,
- OMAP4430_DPLL_BYP_CLKSEL_WIDTH, 0x0, NULL);
-
-/* DPLL_IVA */
-static struct dpll_data dpll_iva_dd = {
- .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_IVA,
- .clk_bypass = &iva_hsd_byp_clk_mux_ck,
- .clk_ref = &sys_clkin_ck,
- .control_reg = OMAP4430_CM_CLKMODE_DPLL_IVA,
- .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
- .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_IVA,
- .idlest_reg = OMAP4430_CM_IDLEST_DPLL_IVA,
- .mult_mask = OMAP4430_DPLL_MULT_MASK,
- .div1_mask = OMAP4430_DPLL_DIV_MASK,
- .enable_mask = OMAP4430_DPLL_EN_MASK,
- .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
- .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
- .max_multiplier = 2047,
- .max_divider = 128,
- .min_divider = 1,
-};
-
-static const char *dpll_iva_ck_parents[] = {
- "sys_clkin_ck", "iva_hsd_byp_clk_mux_ck"
-};
-
-static struct clk dpll_iva_ck;
-
-static const struct clk_ops dpll_ck_ops = {
- .enable = &omap3_noncore_dpll_enable,
- .disable = &omap3_noncore_dpll_disable,
- .recalc_rate = &omap3_dpll_recalc,
- .round_rate = &omap2_dpll_round_rate,
- .set_rate = &omap3_noncore_dpll_set_rate,
- .get_parent = &omap2_init_dpll_parent,
-};
-
-static struct clk_hw_omap dpll_iva_ck_hw = {
- .hw = {
- .clk = &dpll_iva_ck,
- },
- .dpll_data = &dpll_iva_dd,
- .ops = &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_iva_ck, dpll_iva_ck_parents, dpll_ck_ops);
-
-static const char *dpll_iva_x2_ck_parents[] = {
- "dpll_iva_ck",
-};
-
-static struct clk dpll_iva_x2_ck;
-
-static struct clk_hw_omap dpll_iva_x2_ck_hw = {
- .hw = {
- .clk = &dpll_iva_x2_ck,
- },
-};
-
-DEFINE_STRUCT_CLK(dpll_iva_x2_ck, dpll_iva_x2_ck_parents, dpll_abe_x2_ck_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_iva_m4x2_ck, "dpll_iva_x2_ck", &dpll_iva_x2_ck,
- 0x0, OMAP4430_CM_DIV_M4_DPLL_IVA,
- OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_iva_m5x2_ck, "dpll_iva_x2_ck", &dpll_iva_x2_ck,
- 0x0, OMAP4430_CM_DIV_M5_DPLL_IVA,
- OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK);
-
-/* DPLL_MPU */
-static struct dpll_data dpll_mpu_dd = {
- .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_MPU,
- .clk_bypass = &div_mpu_hs_clk,
- .clk_ref = &sys_clkin_ck,
- .control_reg = OMAP4430_CM_CLKMODE_DPLL_MPU,
- .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
- .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_MPU,
- .idlest_reg = OMAP4430_CM_IDLEST_DPLL_MPU,
- .mult_mask = OMAP4430_DPLL_MULT_MASK,
- .div1_mask = OMAP4430_DPLL_DIV_MASK,
- .enable_mask = OMAP4430_DPLL_EN_MASK,
- .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
- .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
- .max_multiplier = 2047,
- .max_divider = 128,
- .min_divider = 1,
-};
-
-static const char *dpll_mpu_ck_parents[] = {
- "sys_clkin_ck", "div_mpu_hs_clk"
-};
-
-static struct clk dpll_mpu_ck;
-
-static struct clk_hw_omap dpll_mpu_ck_hw = {
- .hw = {
- .clk = &dpll_mpu_ck,
- },
- .dpll_data = &dpll_mpu_dd,
- .ops = &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_mpu_ck_parents, dpll_ck_ops);
-
-DEFINE_CLK_FIXED_FACTOR(mpu_periphclk, "dpll_mpu_ck", &dpll_mpu_ck, 0x0, 1, 2);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck, 0x0,
- OMAP4430_CM_DIV_M2_DPLL_MPU,
- OMAP4430_DPLL_CLKOUT_DIV_MASK);
-
-DEFINE_CLK_FIXED_FACTOR(per_hs_clk_div_ck, "dpll_abe_m3x2_ck",
- &dpll_abe_m3x2_ck, 0x0, 1, 2);
-
-static const char *per_hsd_byp_clk_mux_ck_parents[] = {
- "sys_clkin_ck", "per_hs_clk_div_ck",
-};
-
-DEFINE_CLK_MUX(per_hsd_byp_clk_mux_ck, per_hsd_byp_clk_mux_ck_parents, NULL,
- 0x0, OMAP4430_CM_CLKSEL_DPLL_PER, OMAP4430_DPLL_BYP_CLKSEL_SHIFT,
- OMAP4430_DPLL_BYP_CLKSEL_WIDTH, 0x0, NULL);
-
-/* DPLL_PER */
-static struct dpll_data dpll_per_dd = {
- .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_PER,
- .clk_bypass = &per_hsd_byp_clk_mux_ck,
- .clk_ref = &sys_clkin_ck,
- .control_reg = OMAP4430_CM_CLKMODE_DPLL_PER,
- .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
- .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_PER,
- .idlest_reg = OMAP4430_CM_IDLEST_DPLL_PER,
- .mult_mask = OMAP4430_DPLL_MULT_MASK,
- .div1_mask = OMAP4430_DPLL_DIV_MASK,
- .enable_mask = OMAP4430_DPLL_EN_MASK,
- .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
- .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
- .max_multiplier = 2047,
- .max_divider = 128,
- .min_divider = 1,
-};
-
-static const char *dpll_per_ck_parents[] = {
- "sys_clkin_ck", "per_hsd_byp_clk_mux_ck"
-};
-
-static struct clk dpll_per_ck;
-
-static struct clk_hw_omap dpll_per_ck_hw = {
- .hw = {
- .clk = &dpll_per_ck,
- },
- .dpll_data = &dpll_per_dd,
- .ops = &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_per_ck, dpll_per_ck_parents, dpll_ck_ops);
-
-DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0,
- OMAP4430_CM_DIV_M2_DPLL_PER, OMAP4430_DPLL_CLKOUT_DIV_SHIFT,
- OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
-
-static const char *dpll_per_x2_ck_parents[] = {
- "dpll_per_ck",
-};
-
-static struct clk dpll_per_x2_ck;
-
-static struct clk_hw_omap dpll_per_x2_ck_hw = {
- .hw = {
- .clk = &dpll_per_x2_ck,
- },
- .flags = CLOCK_CLKOUTX2,
- .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
- .ops = &clkhwops_omap4_dpllmx,
-};
-
-DEFINE_STRUCT_CLK(dpll_per_x2_ck, dpll_per_x2_ck_parents, dpll_abe_x2_ck_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m2x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
- 0x0, OMAP4430_CM_DIV_M2_DPLL_PER,
- OMAP4430_DPLL_CLKOUT_DIV_MASK);
-
-static const char *dpll_per_m3x2_ck_parents[] = {
- "dpll_per_x2_ck",
-};
-
-static const struct clksel dpll_per_m3x2_div[] = {
- { .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates },
- { .parent = NULL },
-};
-
-/* XXX Missing round_rate, set_rate in ops */
-DEFINE_CLK_OMAP_MUX_GATE(dpll_per_m3x2_ck, NULL, dpll_per_m3x2_div,
- OMAP4430_CM_DIV_M3_DPLL_PER,
- OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
- OMAP4430_CM_DIV_M3_DPLL_PER,
- OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL,
- dpll_per_m3x2_ck_parents, dpll_hsd_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m4x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
- 0x0, OMAP4430_CM_DIV_M4_DPLL_PER,
- OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m5x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
- 0x0, OMAP4430_CM_DIV_M5_DPLL_PER,
- OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m6x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
- 0x0, OMAP4430_CM_DIV_M6_DPLL_PER,
- OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m7x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
- 0x0, OMAP4430_CM_DIV_M7_DPLL_PER,
- OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK);
-
-DEFINE_CLK_FIXED_FACTOR(usb_hs_clk_div_ck, "dpll_abe_m3x2_ck",
- &dpll_abe_m3x2_ck, 0x0, 1, 3);
-
-/* DPLL_USB */
-static struct dpll_data dpll_usb_dd = {
- .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB,
- .clk_bypass = &usb_hs_clk_div_ck,
- .flags = DPLL_J_TYPE,
- .clk_ref = &sys_clkin_ck,
- .control_reg = OMAP4430_CM_CLKMODE_DPLL_USB,
- .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
- .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_USB,
- .idlest_reg = OMAP4430_CM_IDLEST_DPLL_USB,
- .mult_mask = OMAP4430_DPLL_MULT_USB_MASK,
- .div1_mask = OMAP4430_DPLL_DIV_0_7_MASK,
- .enable_mask = OMAP4430_DPLL_EN_MASK,
- .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
- .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
- .sddiv_mask = OMAP4430_DPLL_SD_DIV_MASK,
- .max_multiplier = 4095,
- .max_divider = 256,
- .min_divider = 1,
-};
-
-static const char *dpll_usb_ck_parents[] = {
- "sys_clkin_ck", "usb_hs_clk_div_ck"
-};
-
-static struct clk dpll_usb_ck;
-
-static const struct clk_ops dpll_usb_ck_ops = {
- .enable = &omap3_noncore_dpll_enable,
- .disable = &omap3_noncore_dpll_disable,
- .recalc_rate = &omap3_dpll_recalc,
- .round_rate = &omap2_dpll_round_rate,
- .set_rate = &omap3_noncore_dpll_set_rate,
- .get_parent = &omap2_init_dpll_parent,
- .init = &omap2_init_clk_clkdm,
-};
-
-static struct clk_hw_omap dpll_usb_ck_hw = {
- .hw = {
- .clk = &dpll_usb_ck,
- },
- .dpll_data = &dpll_usb_dd,
- .clkdm_name = "l3_init_clkdm",
- .ops = &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_usb_ck, dpll_usb_ck_parents, dpll_usb_ck_ops);
-
-static const char *dpll_usb_clkdcoldo_ck_parents[] = {
- "dpll_usb_ck",
-};
-
-static struct clk dpll_usb_clkdcoldo_ck;
-
-static const struct clk_ops dpll_usb_clkdcoldo_ck_ops = {
-};
-
-static struct clk_hw_omap dpll_usb_clkdcoldo_ck_hw = {
- .hw = {
- .clk = &dpll_usb_clkdcoldo_ck,
- },
- .clksel_reg = OMAP4430_CM_CLKDCOLDO_DPLL_USB,
- .ops = &clkhwops_omap4_dpllmx,
-};
-
-DEFINE_STRUCT_CLK(dpll_usb_clkdcoldo_ck, dpll_usb_clkdcoldo_ck_parents,
- dpll_usb_clkdcoldo_ck_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_usb_m2_ck, "dpll_usb_ck", &dpll_usb_ck, 0x0,
- OMAP4430_CM_DIV_M2_DPLL_USB,
- OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK);
-
-static const char *ducati_clk_mux_ck_parents[] = {
- "div_core_ck", "dpll_per_m6x2_ck",
-};
-
-DEFINE_CLK_MUX(ducati_clk_mux_ck, ducati_clk_mux_ck_parents, NULL, 0x0,
- OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT, OMAP4430_CLKSEL_0_0_SHIFT,
- OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_FIXED_FACTOR(func_12m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
- 0x0, 1, 16);
-
-DEFINE_CLK_FIXED_FACTOR(func_24m_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0,
- 1, 4);
-
-DEFINE_CLK_FIXED_FACTOR(func_24mc_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
- 0x0, 1, 8);
-
-static const struct clk_div_table func_48m_fclk_rates[] = {
- { .div = 4, .val = 0 },
- { .div = 8, .val = 1 },
- { .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(func_48m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
- 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
- OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_48m_fclk_rates,
- NULL);
-
-DEFINE_CLK_FIXED_FACTOR(func_48mc_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
- 0x0, 1, 4);
-
-static const struct clk_div_table func_64m_fclk_rates[] = {
- { .div = 2, .val = 0 },
- { .div = 4, .val = 1 },
- { .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(func_64m_fclk, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck,
- 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
- OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_64m_fclk_rates,
- NULL);
-
-static const struct clk_div_table func_96m_fclk_rates[] = {
- { .div = 2, .val = 0 },
- { .div = 4, .val = 1 },
- { .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(func_96m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
- 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
- OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_96m_fclk_rates,
- NULL);
-
-static const struct clk_div_table init_60m_fclk_rates[] = {
- { .div = 1, .val = 0 },
- { .div = 8, .val = 1 },
- { .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(init_60m_fclk, "dpll_usb_m2_ck", &dpll_usb_m2_ck,
- 0x0, OMAP4430_CM_CLKSEL_USB_60MHZ,
- OMAP4430_CLKSEL_0_0_SHIFT, OMAP4430_CLKSEL_0_0_WIDTH,
- 0x0, init_60m_fclk_rates, NULL);
-
-DEFINE_CLK_DIVIDER(l3_div_ck, "div_core_ck", &div_core_ck, 0x0,
- OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_L3_SHIFT,
- OMAP4430_CLKSEL_L3_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_DIVIDER(l4_div_ck, "l3_div_ck", &l3_div_ck, 0x0,
- OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_L4_SHIFT,
- OMAP4430_CLKSEL_L4_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_FIXED_FACTOR(lp_clk_div_ck, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck,
- 0x0, 1, 16);
-
-static const char *l4_wkup_clk_mux_ck_parents[] = {
- "sys_clkin_ck", "lp_clk_div_ck",
-};
-
-DEFINE_CLK_MUX(l4_wkup_clk_mux_ck, l4_wkup_clk_mux_ck_parents, NULL, 0x0,
- OMAP4430_CM_L4_WKUP_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
- OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
-
-static const struct clk_div_table ocp_abe_iclk_rates[] = {
- { .div = 2, .val = 0 },
- { .div = 1, .val = 1 },
- { .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(ocp_abe_iclk, "aess_fclk", &aess_fclk, 0x0,
- OMAP4430_CM1_ABE_AESS_CLKCTRL,
- OMAP4430_CLKSEL_AESS_FCLK_SHIFT,
- OMAP4430_CLKSEL_AESS_FCLK_WIDTH,
- 0x0, ocp_abe_iclk_rates, NULL);
-
-DEFINE_CLK_FIXED_FACTOR(per_abe_24m_fclk, "dpll_abe_m2_ck", &dpll_abe_m2_ck,
- 0x0, 1, 4);
-
-DEFINE_CLK_DIVIDER(per_abe_nc_fclk, "dpll_abe_m2_ck", &dpll_abe_m2_ck, 0x0,
- OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
- OMAP4430_SCALE_FCLK_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_DIVIDER(syc_clk_div_ck, "sys_clkin_ck", &sys_clkin_ck, 0x0,
- OMAP4430_CM_ABE_DSS_SYS_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
- OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
-
-static const char *dbgclk_mux_ck_parents[] = {
- "sys_clkin_ck"
-};
-
-static struct clk dbgclk_mux_ck;
-DEFINE_STRUCT_CLK_HW_OMAP(dbgclk_mux_ck, NULL);
-DEFINE_STRUCT_CLK(dbgclk_mux_ck, dbgclk_mux_ck_parents,
- dpll_usb_clkdcoldo_ck_ops);
-
-/* Leaf clocks controlled by modules */
-
-DEFINE_CLK_GATE(aes1_fck, "l3_div_ck", &l3_div_ck, 0x0,
- OMAP4430_CM_L4SEC_AES1_CLKCTRL,
- OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(aes2_fck, "l3_div_ck", &l3_div_ck, 0x0,
- OMAP4430_CM_L4SEC_AES2_CLKCTRL,
- OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(bandgap_fclk, "sys_32k_ck", &sys_32k_ck, 0x0,
- OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
- OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT, 0x0, NULL);
-
-static const struct clk_div_table div_ts_ck_rates[] = {
- { .div = 8, .val = 0 },
- { .div = 16, .val = 1 },
- { .div = 32, .val = 2 },
- { .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(div_ts_ck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
- 0x0, OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
- OMAP4430_CLKSEL_24_25_SHIFT,
- OMAP4430_CLKSEL_24_25_WIDTH, 0x0, div_ts_ck_rates,
- NULL);
-
-DEFINE_CLK_GATE(bandgap_ts_fclk, "div_ts_ck", &div_ts_ck, 0x0,
- OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
- OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT,
- 0x0, NULL);
-
-static const char *dmic_sync_mux_ck_parents[] = {
- "abe_24m_fclk", "syc_clk_div_ck", "func_24m_clk",
-};
-
-DEFINE_CLK_MUX(dmic_sync_mux_ck, dmic_sync_mux_ck_parents, NULL,
- 0x0, OMAP4430_CM1_ABE_DMIC_CLKCTRL,
- OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
- OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel func_dmic_abe_gfclk_sel[] = {
- { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates },
- { .parent = &pad_clks_ck, .rates = div_1_1_rates },
- { .parent = &slimbus_clk, .rates = div_1_2_rates },
- { .parent = NULL },
-};
-
-static const char *func_dmic_abe_gfclk_parents[] = {
- "dmic_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
-};
-
-DEFINE_CLK_OMAP_MUX(func_dmic_abe_gfclk, "abe_clkdm", func_dmic_abe_gfclk_sel,
- OMAP4430_CM1_ABE_DMIC_CLKCTRL, OMAP4430_CLKSEL_SOURCE_MASK,
- func_dmic_abe_gfclk_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_GATE(dss_sys_clk, "syc_clk_div_ck", &syc_clk_div_ck, 0x0,
- OMAP4430_CM_DSS_DSS_CLKCTRL,
- OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(dss_tv_clk, "extalt_clkin_ck", &extalt_clkin_ck, 0x0,
- OMAP4430_CM_DSS_DSS_CLKCTRL,
- OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, 0x0,
- OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
- 0x0, NULL);
-
-DEFINE_CLK_GATE(dss_48mhz_clk, "func_48mc_fclk", &func_48mc_fclk, 0x0,
- OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT,
- 0x0, NULL);
-
-DEFINE_CLK_GATE(dss_fck, "l3_div_ck", &l3_div_ck, 0x0,
- OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
- 0x0, NULL);
-
-DEFINE_CLK_DIVIDER(fdif_fck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0,
- OMAP4430_CM_CAM_FDIF_CLKCTRL, OMAP4430_CLKSEL_FCLK_SHIFT,
- OMAP4430_CLKSEL_FCLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
-
-DEFINE_CLK_GATE(gpio1_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
- OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
- OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(gpio2_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
- OMAP4430_CM_L4PER_GPIO2_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
- 0x0, NULL);
-
-DEFINE_CLK_GATE(gpio3_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
- OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
- OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(gpio4_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
- OMAP4430_CM_L4PER_GPIO4_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
- 0x0, NULL);
-
-DEFINE_CLK_GATE(gpio5_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
- OMAP4430_CM_L4PER_GPIO5_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
- 0x0, NULL);
-
-DEFINE_CLK_GATE(gpio6_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
- OMAP4430_CM_L4PER_GPIO6_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
- 0x0, NULL);
-
-static const struct clksel sgx_clk_mux_sel[] = {
- { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates },
- { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates },
- { .parent = NULL },
-};
-
-static const char *sgx_clk_mux_parents[] = {
- "dpll_core_m7x2_ck", "dpll_per_m7x2_ck",
-};
-
-DEFINE_CLK_OMAP_MUX(sgx_clk_mux, "l3_gfx_clkdm", sgx_clk_mux_sel,
- OMAP4430_CM_GFX_GFX_CLKCTRL, OMAP4430_CLKSEL_SGX_FCLK_MASK,
- sgx_clk_mux_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_DIVIDER(hsi_fck, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, 0x0,
- OMAP4430_CM_L3INIT_HSI_CLKCTRL, OMAP4430_CLKSEL_24_25_SHIFT,
- OMAP4430_CLKSEL_24_25_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
- NULL);
-
-DEFINE_CLK_GATE(iss_ctrlclk, "func_96m_fclk", &func_96m_fclk, 0x0,
- OMAP4430_CM_CAM_ISS_CLKCTRL, OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
- 0x0, NULL);
-
-DEFINE_CLK_MUX(mcasp_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
- OMAP4430_CM1_ABE_MCASP_CLKCTRL,
- OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
- OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel func_mcasp_abe_gfclk_sel[] = {
- { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates },
- { .parent = &pad_clks_ck, .rates = div_1_1_rates },
- { .parent = &slimbus_clk, .rates = div_1_2_rates },
- { .parent = NULL },
-};
-
-static const char *func_mcasp_abe_gfclk_parents[] = {
- "mcasp_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
-};
-
-DEFINE_CLK_OMAP_MUX(func_mcasp_abe_gfclk, "abe_clkdm", func_mcasp_abe_gfclk_sel,
- OMAP4430_CM1_ABE_MCASP_CLKCTRL, OMAP4430_CLKSEL_SOURCE_MASK,
- func_mcasp_abe_gfclk_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_MUX(mcbsp1_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
- OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
- OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
- OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel func_mcbsp1_gfclk_sel[] = {
- { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates },
- { .parent = &pad_clks_ck, .rates = div_1_1_rates },
- { .parent = &slimbus_clk, .rates = div_1_2_rates },
- { .parent = NULL },
-};
-
-static const char *func_mcbsp1_gfclk_parents[] = {
- "mcbsp1_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
-};
-
-DEFINE_CLK_OMAP_MUX(func_mcbsp1_gfclk, "abe_clkdm", func_mcbsp1_gfclk_sel,
- OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
- OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp1_gfclk_parents,
- func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_MUX(mcbsp2_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
- OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
- OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
- OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel func_mcbsp2_gfclk_sel[] = {
- { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates },
- { .parent = &pad_clks_ck, .rates = div_1_1_rates },
- { .parent = &slimbus_clk, .rates = div_1_2_rates },
- { .parent = NULL },
-};
-
-static const char *func_mcbsp2_gfclk_parents[] = {
- "mcbsp2_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
-};
-
-DEFINE_CLK_OMAP_MUX(func_mcbsp2_gfclk, "abe_clkdm", func_mcbsp2_gfclk_sel,
- OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
- OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp2_gfclk_parents,
- func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_MUX(mcbsp3_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
- OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
- OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
- OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel func_mcbsp3_gfclk_sel[] = {
- { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates },
- { .parent = &pad_clks_ck, .rates = div_1_1_rates },
- { .parent = &slimbus_clk, .rates = div_1_2_rates },
- { .parent = NULL },
-};
-
-static const char *func_mcbsp3_gfclk_parents[] = {
- "mcbsp3_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
-};
-
-DEFINE_CLK_OMAP_MUX(func_mcbsp3_gfclk, "abe_clkdm", func_mcbsp3_gfclk_sel,
- OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
- OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp3_gfclk_parents,
- func_dmic_abe_gfclk_ops);
-
-static const char *mcbsp4_sync_mux_ck_parents[] = {
- "func_96m_fclk", "per_abe_nc_fclk",
-};
-
-DEFINE_CLK_MUX(mcbsp4_sync_mux_ck, mcbsp4_sync_mux_ck_parents, NULL, 0x0,
- OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
- OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
- OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel per_mcbsp4_gfclk_sel[] = {
- { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates },
- { .parent = &pad_clks_ck, .rates = div_1_1_rates },
- { .parent = NULL },
-};
-
-static const char *per_mcbsp4_gfclk_parents[] = {
- "mcbsp4_sync_mux_ck", "pad_clks_ck",
-};
-
-DEFINE_CLK_OMAP_MUX(per_mcbsp4_gfclk, "l4_per_clkdm", per_mcbsp4_gfclk_sel,
- OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
- OMAP4430_CLKSEL_SOURCE_24_24_MASK, per_mcbsp4_gfclk_parents,
- func_dmic_abe_gfclk_ops);
-
-static const struct clksel hsmmc1_fclk_sel[] = {
- { .parent = &func_64m_fclk, .rates = div_1_0_rates },
- { .parent = &func_96m_fclk, .rates = div_1_1_rates },
- { .parent = NULL },
-};
-
-static const char *hsmmc1_fclk_parents[] = {
- "func_64m_fclk", "func_96m_fclk",
-};
-
-DEFINE_CLK_OMAP_MUX(hsmmc1_fclk, "l3_init_clkdm", hsmmc1_fclk_sel,
- OMAP4430_CM_L3INIT_MMC1_CLKCTRL, OMAP4430_CLKSEL_MASK,
- hsmmc1_fclk_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(hsmmc2_fclk, "l3_init_clkdm", hsmmc1_fclk_sel,
- OMAP4430_CM_L3INIT_MMC2_CLKCTRL, OMAP4430_CLKSEL_MASK,
- hsmmc1_fclk_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_GATE(ocp2scp_usb_phy_phy_48m, "func_48m_fclk", &func_48m_fclk, 0x0,
- OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
- OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(sha2md5_fck, "l3_div_ck", &l3_div_ck, 0x0,
- OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
- OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus1_fclk_1, "func_24m_clk", &func_24m_clk, 0x0,
- OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
- OMAP4430_OPTFCLKEN_FCLK1_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus1_fclk_0, "abe_24m_fclk", &abe_24m_fclk, 0x0,
- OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
- OMAP4430_OPTFCLKEN_FCLK0_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus1_fclk_2, "pad_clks_ck", &pad_clks_ck, 0x0,
- OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
- OMAP4430_OPTFCLKEN_FCLK2_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus1_slimbus_clk, "slimbus_clk", &slimbus_clk, 0x0,
- OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
- OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus2_fclk_1, "per_abe_24m_fclk", &per_abe_24m_fclk, 0x0,
- OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
- OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus2_fclk_0, "func_24mc_fclk", &func_24mc_fclk, 0x0,
- OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
- OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus2_slimbus_clk, "pad_slimbus_core_clks_ck",
- &pad_slimbus_core_clks_ck, 0x0,
- OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
- OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(smartreflex_core_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
- 0x0, OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
- OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(smartreflex_iva_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
- 0x0, OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
- OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(smartreflex_mpu_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
- 0x0, OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
- OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-static const struct clksel dmt1_clk_mux_sel[] = {
- { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
- { .parent = &sys_32k_ck, .rates = div_1_1_rates },
- { .parent = NULL },
-};
-
-DEFINE_CLK_OMAP_MUX(dmt1_clk_mux, "l4_wkup_clkdm", dmt1_clk_mux_sel,
- OMAP4430_CM_WKUP_TIMER1_CLKCTRL, OMAP4430_CLKSEL_MASK,
- abe_dpll_bypass_clk_mux_ck_parents,
- func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm10_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
- OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, OMAP4430_CLKSEL_MASK,
- abe_dpll_bypass_clk_mux_ck_parents,
- func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm11_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
- OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, OMAP4430_CLKSEL_MASK,
- abe_dpll_bypass_clk_mux_ck_parents,
- func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm2_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
- OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, OMAP4430_CLKSEL_MASK,
- abe_dpll_bypass_clk_mux_ck_parents,
- func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm3_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
- OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, OMAP4430_CLKSEL_MASK,
- abe_dpll_bypass_clk_mux_ck_parents,
- func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm4_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
- OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, OMAP4430_CLKSEL_MASK,
- abe_dpll_bypass_clk_mux_ck_parents,
- func_dmic_abe_gfclk_ops);
-
-static const struct clksel timer5_sync_mux_sel[] = {
- { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
- { .parent = &sys_32k_ck, .rates = div_1_1_rates },
- { .parent = NULL },
-};
-
-static const char *timer5_sync_mux_parents[] = {
- "syc_clk_div_ck", "sys_32k_ck",
-};
-
-DEFINE_CLK_OMAP_MUX(timer5_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
- OMAP4430_CM1_ABE_TIMER5_CLKCTRL, OMAP4430_CLKSEL_MASK,
- timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(timer6_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
- OMAP4430_CM1_ABE_TIMER6_CLKCTRL, OMAP4430_CLKSEL_MASK,
- timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(timer7_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
- OMAP4430_CM1_ABE_TIMER7_CLKCTRL, OMAP4430_CLKSEL_MASK,
- timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(timer8_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
- OMAP4430_CM1_ABE_TIMER8_CLKCTRL, OMAP4430_CLKSEL_MASK,
- timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm9_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
- OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, OMAP4430_CLKSEL_MASK,
- abe_dpll_bypass_clk_mux_ck_parents,
- func_dmic_abe_gfclk_ops);
-
-static struct clk usb_host_fs_fck;
-
-static const char *usb_host_fs_fck_parent_names[] = {
- "func_48mc_fclk",
-};
-
-static const struct clk_ops usb_host_fs_fck_ops = {
- .enable = &omap2_dflt_clk_enable,
- .disable = &omap2_dflt_clk_disable,
- .is_enabled = &omap2_dflt_clk_is_enabled,
-};
-
-static struct clk_hw_omap usb_host_fs_fck_hw = {
- .hw = {
- .clk = &usb_host_fs_fck,
- },
- .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
- .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT,
- .clkdm_name = "l3_init_clkdm",
-};
-
-DEFINE_STRUCT_CLK(usb_host_fs_fck, usb_host_fs_fck_parent_names,
- usb_host_fs_fck_ops);
-
-static const char *utmi_p1_gfclk_parents[] = {
- "init_60m_fclk", "xclk60mhsp1_ck",
-};
-
-DEFINE_CLK_MUX(utmi_p1_gfclk, utmi_p1_gfclk_parents, NULL, 0x0,
- OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
- OMAP4430_CLKSEL_UTMI_P1_SHIFT, OMAP4430_CLKSEL_UTMI_P1_WIDTH,
- 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_utmi_p1_clk, "utmi_p1_gfclk", &utmi_p1_gfclk, 0x0,
- OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
- OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT, 0x0, NULL);
-
-static const char *utmi_p2_gfclk_parents[] = {
- "init_60m_fclk", "xclk60mhsp2_ck",
-};
-
-DEFINE_CLK_MUX(utmi_p2_gfclk, utmi_p2_gfclk_parents, NULL, 0x0,
- OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
- OMAP4430_CLKSEL_UTMI_P2_SHIFT, OMAP4430_CLKSEL_UTMI_P2_WIDTH,
- 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_utmi_p2_clk, "utmi_p2_gfclk", &utmi_p2_gfclk, 0x0,
- OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
- OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_utmi_p3_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
- OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
- OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_hsic480m_p1_clk, "dpll_usb_m2_ck",
- &dpll_usb_m2_ck, 0x0,
- OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
- OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_hsic60m_p1_clk, "init_60m_fclk",
- &init_60m_fclk, 0x0,
- OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
- OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_hsic60m_p2_clk, "init_60m_fclk",
- &init_60m_fclk, 0x0,
- OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
- OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_hsic480m_p2_clk, "dpll_usb_m2_ck",
- &dpll_usb_m2_ck, 0x0,
- OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
- OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_func48mclk, "func_48mc_fclk", &func_48mc_fclk, 0x0,
- OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
- OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_fck, "init_60m_fclk", &init_60m_fclk, 0x0,
- OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
- OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-static const char *otg_60m_gfclk_parents[] = {
- "utmi_phy_clkout_ck", "xclk60motg_ck",
-};
-
-DEFINE_CLK_MUX(otg_60m_gfclk, otg_60m_gfclk_parents, NULL, 0x0,
- OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, OMAP4430_CLKSEL_60M_SHIFT,
- OMAP4430_CLKSEL_60M_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_otg_hs_xclk, "otg_60m_gfclk", &otg_60m_gfclk, 0x0,
- OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
- OMAP4430_OPTFCLKEN_XCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_otg_hs_ick, "l3_div_ck", &l3_div_ck, 0x0,
- OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
- OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_phy_cm_clk32k, "sys_32k_ck", &sys_32k_ck, 0x0,
- OMAP4430_CM_ALWON_USBPHY_CLKCTRL,
- OMAP4430_OPTFCLKEN_CLK32K_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_tll_hs_usb_ch2_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
- OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
- OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_tll_hs_usb_ch0_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
- OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
- OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_tll_hs_usb_ch1_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
- OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
- OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_tll_hs_ick, "l4_div_ck", &l4_div_ck, 0x0,
- OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
- OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
-
-static const struct clk_div_table usim_ck_rates[] = {
- { .div = 14, .val = 0 },
- { .div = 18, .val = 1 },
- { .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(usim_ck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0,
- OMAP4430_CM_WKUP_USIM_CLKCTRL,
- OMAP4430_CLKSEL_DIV_SHIFT, OMAP4430_CLKSEL_DIV_WIDTH,
- 0x0, usim_ck_rates, NULL);
-
-DEFINE_CLK_GATE(usim_fclk, "usim_ck", &usim_ck, 0x0,
- OMAP4430_CM_WKUP_USIM_CLKCTRL, OMAP4430_OPTFCLKEN_FCLK_SHIFT,
- 0x0, NULL);
-
-/* Remaining optional clocks */
-static const char *pmd_stm_clock_mux_ck_parents[] = {
- "sys_clkin_ck", "dpll_core_m6x2_ck", "tie_low_clock_ck",
-};
-
-DEFINE_CLK_MUX(pmd_stm_clock_mux_ck, pmd_stm_clock_mux_ck_parents, NULL, 0x0,
- OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, OMAP4430_PMD_STM_MUX_CTRL_SHIFT,
- OMAP4430_PMD_STM_MUX_CTRL_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_MUX(pmd_trace_clk_mux_ck, pmd_stm_clock_mux_ck_parents, NULL, 0x0,
- OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
- OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT,
- OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_DIVIDER(stm_clk_div_ck, "pmd_stm_clock_mux_ck",
- &pmd_stm_clock_mux_ck, 0x0, OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
- OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT,
- OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
- NULL);
-
-static const char *trace_clk_div_ck_parents[] = {
- "pmd_trace_clk_mux_ck",
-};
-
-static const struct clksel trace_clk_div_div[] = {
- { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates },
- { .parent = NULL },
-};
-
-static struct clk trace_clk_div_ck;
-
-static const struct clk_ops trace_clk_div_ck_ops = {
- .recalc_rate = &omap2_clksel_recalc,
- .set_rate = &omap2_clksel_set_rate,
- .round_rate = &omap2_clksel_round_rate,
- .init = &omap2_init_clk_clkdm,
- .enable = &omap2_clkops_enable_clkdm,
- .disable = &omap2_clkops_disable_clkdm,
-};
-
-static struct clk_hw_omap trace_clk_div_ck_hw = {
- .hw = {
- .clk = &trace_clk_div_ck,
- },
- .clkdm_name = "emu_sys_clkdm",
- .clksel = trace_clk_div_div,
- .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
- .clksel_mask = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
-};
-
-DEFINE_STRUCT_CLK(trace_clk_div_ck, trace_clk_div_ck_parents,
- trace_clk_div_ck_ops);
-
-/* SCRM aux clk nodes */
-
-static const struct clksel auxclk_src_sel[] = {
- { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
- { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates },
- { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates },
- { .parent = NULL },
-};
-
-static const char *auxclk_src_ck_parents[] = {
- "sys_clkin_ck", "dpll_core_m3x2_ck", "dpll_per_m3x2_ck",
-};
-
-static const struct clk_ops auxclk_src_ck_ops = {
- .enable = &omap2_dflt_clk_enable,
- .disable = &omap2_dflt_clk_disable,
- .is_enabled = &omap2_dflt_clk_is_enabled,
- .recalc_rate = &omap2_clksel_recalc,
- .get_parent = &omap2_clksel_find_parent_index,
-};
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk0_src_ck, NULL, auxclk_src_sel,
- OMAP4_SCRM_AUXCLK0, OMAP4_SRCSELECT_MASK,
- OMAP4_SCRM_AUXCLK0, OMAP4_ENABLE_SHIFT, NULL,
- auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk0_ck, "auxclk0_src_ck", &auxclk0_src_ck, 0x0,
- OMAP4_SCRM_AUXCLK0, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
- 0x0, NULL);
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk1_src_ck, NULL, auxclk_src_sel,
- OMAP4_SCRM_AUXCLK1, OMAP4_SRCSELECT_MASK,
- OMAP4_SCRM_AUXCLK1, OMAP4_ENABLE_SHIFT, NULL,
- auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk1_ck, "auxclk1_src_ck", &auxclk1_src_ck, 0x0,
- OMAP4_SCRM_AUXCLK1, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
- 0x0, NULL);
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk2_src_ck, NULL, auxclk_src_sel,
- OMAP4_SCRM_AUXCLK2, OMAP4_SRCSELECT_MASK,
- OMAP4_SCRM_AUXCLK2, OMAP4_ENABLE_SHIFT, NULL,
- auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk2_ck, "auxclk2_src_ck", &auxclk2_src_ck, 0x0,
- OMAP4_SCRM_AUXCLK2, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
- 0x0, NULL);
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk3_src_ck, NULL, auxclk_src_sel,
- OMAP4_SCRM_AUXCLK3, OMAP4_SRCSELECT_MASK,
- OMAP4_SCRM_AUXCLK3, OMAP4_ENABLE_SHIFT, NULL,
- auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk3_ck, "auxclk3_src_ck", &auxclk3_src_ck, 0x0,
- OMAP4_SCRM_AUXCLK3, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
- 0x0, NULL);
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk4_src_ck, NULL, auxclk_src_sel,
- OMAP4_SCRM_AUXCLK4, OMAP4_SRCSELECT_MASK,
- OMAP4_SCRM_AUXCLK4, OMAP4_ENABLE_SHIFT, NULL,
- auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk4_ck, "auxclk4_src_ck", &auxclk4_src_ck, 0x0,
- OMAP4_SCRM_AUXCLK4, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
- 0x0, NULL);
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk5_src_ck, NULL, auxclk_src_sel,
- OMAP4_SCRM_AUXCLK5, OMAP4_SRCSELECT_MASK,
- OMAP4_SCRM_AUXCLK5, OMAP4_ENABLE_SHIFT, NULL,
- auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk5_ck, "auxclk5_src_ck", &auxclk5_src_ck, 0x0,
- OMAP4_SCRM_AUXCLK5, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
- 0x0, NULL);
-
-static const char *auxclkreq_ck_parents[] = {
- "auxclk0_ck", "auxclk1_ck", "auxclk2_ck", "auxclk3_ck", "auxclk4_ck",
- "auxclk5_ck",
-};
-
-DEFINE_CLK_MUX(auxclkreq0_ck, auxclkreq_ck_parents, NULL, 0x0,
- OMAP4_SCRM_AUXCLKREQ0, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
- 0x0, NULL);
-
-DEFINE_CLK_MUX(auxclkreq1_ck, auxclkreq_ck_parents, NULL, 0x0,
- OMAP4_SCRM_AUXCLKREQ1, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
- 0x0, NULL);
-
-DEFINE_CLK_MUX(auxclkreq2_ck, auxclkreq_ck_parents, NULL, 0x0,
- OMAP4_SCRM_AUXCLKREQ2, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
- 0x0, NULL);
-
-DEFINE_CLK_MUX(auxclkreq3_ck, auxclkreq_ck_parents, NULL, 0x0,
- OMAP4_SCRM_AUXCLKREQ3, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
- 0x0, NULL);
-
-DEFINE_CLK_MUX(auxclkreq4_ck, auxclkreq_ck_parents, NULL, 0x0,
- OMAP4_SCRM_AUXCLKREQ4, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
- 0x0, NULL);
-
-DEFINE_CLK_MUX(auxclkreq5_ck, auxclkreq_ck_parents, NULL, 0x0,
- OMAP4_SCRM_AUXCLKREQ5, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
- 0x0, NULL);
-
-/*
- * clocks specific to omap4460
- */
-static struct omap_clk omap446x_clks[] = {
- CLK(NULL, "div_ts_ck", &div_ts_ck),
- CLK(NULL, "bandgap_ts_fclk", &bandgap_ts_fclk),
-};
-
-/*
- * clocks specific to omap4430
- */
-static struct omap_clk omap443x_clks[] = {
- CLK(NULL, "bandgap_fclk", &bandgap_fclk),
-};
-
-/*
- * clocks common to omap44xx
- */
-static struct omap_clk omap44xx_clks[] = {
- CLK(NULL, "extalt_clkin_ck", &extalt_clkin_ck),
- CLK(NULL, "pad_clks_src_ck", &pad_clks_src_ck),
- CLK(NULL, "pad_clks_ck", &pad_clks_ck),
- CLK(NULL, "pad_slimbus_core_clks_ck", &pad_slimbus_core_clks_ck),
- CLK(NULL, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck),
- CLK(NULL, "slimbus_src_clk", &slimbus_src_clk),
- CLK(NULL, "slimbus_clk", &slimbus_clk),
- CLK(NULL, "sys_32k_ck", &sys_32k_ck),
- CLK(NULL, "virt_12000000_ck", &virt_12000000_ck),
- CLK(NULL, "virt_13000000_ck", &virt_13000000_ck),
- CLK(NULL, "virt_16800000_ck", &virt_16800000_ck),
- CLK(NULL, "virt_19200000_ck", &virt_19200000_ck),
- CLK(NULL, "virt_26000000_ck", &virt_26000000_ck),
- CLK(NULL, "virt_27000000_ck", &virt_27000000_ck),
- CLK(NULL, "virt_38400000_ck", &virt_38400000_ck),
- CLK(NULL, "sys_clkin_ck", &sys_clkin_ck),
- CLK(NULL, "tie_low_clock_ck", &tie_low_clock_ck),
- CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck),
- CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck),
- CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck),
- CLK(NULL, "xclk60motg_ck", &xclk60motg_ck),
- CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck),
- CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck),
- CLK(NULL, "dpll_abe_ck", &dpll_abe_ck),
- CLK(NULL, "dpll_abe_x2_ck", &dpll_abe_x2_ck),
- CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck),
- CLK(NULL, "abe_24m_fclk", &abe_24m_fclk),
- CLK(NULL, "abe_clk", &abe_clk),
- CLK(NULL, "aess_fclk", &aess_fclk),
- CLK(NULL, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck),
- CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck),
- CLK(NULL, "dpll_core_ck", &dpll_core_ck),
- CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck),
- CLK(NULL, "dpll_core_m6x2_ck", &dpll_core_m6x2_ck),
- CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck),
- CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck),
- CLK(NULL, "ddrphy_ck", &ddrphy_ck),
- CLK(NULL, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck),
- CLK(NULL, "div_core_ck", &div_core_ck),
- CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk),
- CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk),
- CLK(NULL, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck),
- CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck),
- CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck),
- CLK(NULL, "dpll_core_m3x2_ck", &dpll_core_m3x2_ck),
- CLK(NULL, "dpll_core_m7x2_ck", &dpll_core_m7x2_ck),
- CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck),
- CLK(NULL, "dpll_iva_ck", &dpll_iva_ck),
- CLK(NULL, "dpll_iva_x2_ck", &dpll_iva_x2_ck),
- CLK(NULL, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck),
- CLK(NULL, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck),
- CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck),
- CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck),
- CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck),
- CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck),
- CLK(NULL, "dpll_per_ck", &dpll_per_ck),
- CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck),
- CLK(NULL, "dpll_per_x2_ck", &dpll_per_x2_ck),
- CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck),
- CLK(NULL, "dpll_per_m3x2_ck", &dpll_per_m3x2_ck),
- CLK(NULL, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck),
- CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck),
- CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck),
- CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck),
- CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck),
- CLK(NULL, "dpll_usb_ck", &dpll_usb_ck),
- CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck),
- CLK(NULL, "dpll_usb_m2_ck", &dpll_usb_m2_ck),
- CLK(NULL, "ducati_clk_mux_ck", &ducati_clk_mux_ck),
- CLK(NULL, "func_12m_fclk", &func_12m_fclk),
- CLK(NULL, "func_24m_clk", &func_24m_clk),
- CLK(NULL, "func_24mc_fclk", &func_24mc_fclk),
- CLK(NULL, "func_48m_fclk", &func_48m_fclk),
- CLK(NULL, "func_48mc_fclk", &func_48mc_fclk),
- CLK(NULL, "func_64m_fclk", &func_64m_fclk),
- CLK(NULL, "func_96m_fclk", &func_96m_fclk),
- CLK(NULL, "init_60m_fclk", &init_60m_fclk),
- CLK(NULL, "l3_div_ck", &l3_div_ck),
- CLK(NULL, "l4_div_ck", &l4_div_ck),
- CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck),
- CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck),
- CLK("smp_twd", NULL, &mpu_periphclk),
- CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk),
- CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk),
- CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk),
- CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck),
- CLK(NULL, "aes1_fck", &aes1_fck),
- CLK(NULL, "aes2_fck", &aes2_fck),
- CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck),
- CLK(NULL, "func_dmic_abe_gfclk", &func_dmic_abe_gfclk),
- CLK(NULL, "dss_sys_clk", &dss_sys_clk),
- CLK(NULL, "dss_tv_clk", &dss_tv_clk),
- CLK(NULL, "dss_dss_clk", &dss_dss_clk),
- CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk),
- CLK(NULL, "dss_fck", &dss_fck),
- CLK("omapdss_dss", "ick", &dss_fck),
- CLK(NULL, "fdif_fck", &fdif_fck),
- CLK(NULL, "gpio1_dbclk", &gpio1_dbclk),
- CLK(NULL, "gpio2_dbclk", &gpio2_dbclk),
- CLK(NULL, "gpio3_dbclk", &gpio3_dbclk),
- CLK(NULL, "gpio4_dbclk", &gpio4_dbclk),
- CLK(NULL, "gpio5_dbclk", &gpio5_dbclk),
- CLK(NULL, "gpio6_dbclk", &gpio6_dbclk),
- CLK(NULL, "sgx_clk_mux", &sgx_clk_mux),
- CLK(NULL, "hsi_fck", &hsi_fck),
- CLK(NULL, "iss_ctrlclk", &iss_ctrlclk),
- CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck),
- CLK(NULL, "func_mcasp_abe_gfclk", &func_mcasp_abe_gfclk),
- CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck),
- CLK(NULL, "func_mcbsp1_gfclk", &func_mcbsp1_gfclk),
- CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck),
- CLK(NULL, "func_mcbsp2_gfclk", &func_mcbsp2_gfclk),
- CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck),
- CLK(NULL, "func_mcbsp3_gfclk", &func_mcbsp3_gfclk),
- CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck),
- CLK(NULL, "per_mcbsp4_gfclk", &per_mcbsp4_gfclk),
- CLK(NULL, "hsmmc1_fclk", &hsmmc1_fclk),
- CLK(NULL, "hsmmc2_fclk", &hsmmc2_fclk),
- CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m),
- CLK(NULL, "sha2md5_fck", &sha2md5_fck),
- CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1),
- CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0),
- CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2),
- CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk),
- CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1),
- CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0),
- CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk),
- CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck),
- CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck),
- CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck),
- CLK(NULL, "dmt1_clk_mux", &dmt1_clk_mux),
- CLK(NULL, "cm2_dm10_mux", &cm2_dm10_mux),
- CLK(NULL, "cm2_dm11_mux", &cm2_dm11_mux),
- CLK(NULL, "cm2_dm2_mux", &cm2_dm2_mux),
- CLK(NULL, "cm2_dm3_mux", &cm2_dm3_mux),
- CLK(NULL, "cm2_dm4_mux", &cm2_dm4_mux),
- CLK(NULL, "timer5_sync_mux", &timer5_sync_mux),
- CLK(NULL, "timer6_sync_mux", &timer6_sync_mux),
- CLK(NULL, "timer7_sync_mux", &timer7_sync_mux),
- CLK(NULL, "timer8_sync_mux", &timer8_sync_mux),
- CLK(NULL, "cm2_dm9_mux", &cm2_dm9_mux),
- CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck),
- CLK("usbhs_omap", "fs_fck", &usb_host_fs_fck),
- CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk),
- CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk),
- CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk),
- CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk),
- CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk),
- CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk),
- CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk),
- CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk),
- CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk),
- CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk),
- CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck),
- CLK("usbhs_omap", "hs_fck", &usb_host_hs_fck),
- CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk),
- CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk),
- CLK(NULL, "usb_otg_hs_ick", &usb_otg_hs_ick),
- CLK("musb-omap2430", "ick", &usb_otg_hs_ick),
- CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k),
- CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk),
- CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk),
- CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk),
- CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick),
- CLK("usbhs_omap", "usbtll_ick", &usb_tll_hs_ick),
- CLK("usbhs_tll", "usbtll_ick", &usb_tll_hs_ick),
- CLK(NULL, "usim_ck", &usim_ck),
- CLK(NULL, "usim_fclk", &usim_fclk),
- CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck),
- CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck),
- CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck),
- CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck),
- CLK(NULL, "auxclk0_src_ck", &auxclk0_src_ck),
- CLK(NULL, "auxclk0_ck", &auxclk0_ck),
- CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck),
- CLK(NULL, "auxclk1_src_ck", &auxclk1_src_ck),
- CLK(NULL, "auxclk1_ck", &auxclk1_ck),
- CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck),
- CLK(NULL, "auxclk2_src_ck", &auxclk2_src_ck),
- CLK(NULL, "auxclk2_ck", &auxclk2_ck),
- CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck),
- CLK(NULL, "auxclk3_src_ck", &auxclk3_src_ck),
- CLK(NULL, "auxclk3_ck", &auxclk3_ck),
- CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck),
- CLK(NULL, "auxclk4_src_ck", &auxclk4_src_ck),
- CLK(NULL, "auxclk4_ck", &auxclk4_ck),
- CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck),
- CLK(NULL, "auxclk5_src_ck", &auxclk5_src_ck),
- CLK(NULL, "auxclk5_ck", &auxclk5_ck),
- CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck),
- CLK("50000000.gpmc", "fck", &dummy_ck),
- CLK("omap_i2c.1", "ick", &dummy_ck),
- CLK("omap_i2c.2", "ick", &dummy_ck),
- CLK("omap_i2c.3", "ick", &dummy_ck),
- CLK("omap_i2c.4", "ick", &dummy_ck),
- CLK(NULL, "mailboxes_ick", &dummy_ck),
- CLK("omap_hsmmc.0", "ick", &dummy_ck),
- CLK("omap_hsmmc.1", "ick", &dummy_ck),
- CLK("omap_hsmmc.2", "ick", &dummy_ck),
- CLK("omap_hsmmc.3", "ick", &dummy_ck),
- CLK("omap_hsmmc.4", "ick", &dummy_ck),
- CLK("omap-mcbsp.1", "ick", &dummy_ck),
- CLK("omap-mcbsp.2", "ick", &dummy_ck),
- CLK("omap-mcbsp.3", "ick", &dummy_ck),
- CLK("omap-mcbsp.4", "ick", &dummy_ck),
- CLK("omap2_mcspi.1", "ick", &dummy_ck),
- CLK("omap2_mcspi.2", "ick", &dummy_ck),
- CLK("omap2_mcspi.3", "ick", &dummy_ck),
- CLK("omap2_mcspi.4", "ick", &dummy_ck),
- CLK(NULL, "uart1_ick", &dummy_ck),
- CLK(NULL, "uart2_ick", &dummy_ck),
- CLK(NULL, "uart3_ick", &dummy_ck),
- CLK(NULL, "uart4_ick", &dummy_ck),
- CLK("usbhs_omap", "usbhost_ick", &dummy_ck),
- CLK("usbhs_omap", "usbtll_fck", &dummy_ck),
- CLK("usbhs_tll", "usbtll_fck", &dummy_ck),
- CLK("omap_wdt", "ick", &dummy_ck),
- CLK(NULL, "timer_32k_ck", &sys_32k_ck),
- /* TODO: Remove "omap_timer.X" aliases once DT migration is complete */
- CLK("omap_timer.1", "timer_sys_ck", &sys_clkin_ck),
- CLK("omap_timer.2", "timer_sys_ck", &sys_clkin_ck),
- CLK("omap_timer.3", "timer_sys_ck", &sys_clkin_ck),
- CLK("omap_timer.4", "timer_sys_ck", &sys_clkin_ck),
- CLK("omap_timer.9", "timer_sys_ck", &sys_clkin_ck),
- CLK("omap_timer.10", "timer_sys_ck", &sys_clkin_ck),
- CLK("omap_timer.11", "timer_sys_ck", &sys_clkin_ck),
- CLK("omap_timer.5", "timer_sys_ck", &syc_clk_div_ck),
- CLK("omap_timer.6", "timer_sys_ck", &syc_clk_div_ck),
- CLK("omap_timer.7", "timer_sys_ck", &syc_clk_div_ck),
- CLK("omap_timer.8", "timer_sys_ck", &syc_clk_div_ck),
- CLK("4a318000.timer", "timer_sys_ck", &sys_clkin_ck),
- CLK("48032000.timer", "timer_sys_ck", &sys_clkin_ck),
- CLK("48034000.timer", "timer_sys_ck", &sys_clkin_ck),
- CLK("48036000.timer", "timer_sys_ck", &sys_clkin_ck),
- CLK("4803e000.timer", "timer_sys_ck", &sys_clkin_ck),
- CLK("48086000.timer", "timer_sys_ck", &sys_clkin_ck),
- CLK("48088000.timer", "timer_sys_ck", &sys_clkin_ck),
- CLK("40138000.timer", "timer_sys_ck", &syc_clk_div_ck),
- CLK("4013a000.timer", "timer_sys_ck", &syc_clk_div_ck),
- CLK("4013c000.timer", "timer_sys_ck", &syc_clk_div_ck),
- CLK("4013e000.timer", "timer_sys_ck", &syc_clk_div_ck),
- CLK(NULL, "cpufreq_ck", &dpll_mpu_ck),
-};
-
-int __init omap4xxx_clk_init(void)
-{
- int rc;
-
- if (cpu_is_omap443x()) {
- cpu_mask = RATE_IN_4430;
- omap_clocks_register(omap443x_clks, ARRAY_SIZE(omap443x_clks));
- } else if (cpu_is_omap446x() || cpu_is_omap447x()) {
- cpu_mask = RATE_IN_4460 | RATE_IN_4430;
- omap_clocks_register(omap446x_clks, ARRAY_SIZE(omap446x_clks));
- if (cpu_is_omap447x())
- pr_warn("WARNING: OMAP4470 clock data incomplete!\n");
- } else {
- return 0;
- }
-
- omap_clocks_register(omap44xx_clks, ARRAY_SIZE(omap44xx_clks));
-
- omap2_clk_disable_autoidle_all();
-
- /*
- * A set rate of ABE DPLL inturn triggers a set rate of USB DPLL
- * when its in bypass. So always lock USB before ABE DPLL.
- */
- /*
- * Lock USB DPLL on OMAP4 devices so that the L3INIT power
- * domain can transition to retention state when not in use.
- */
- rc = clk_set_rate(&dpll_usb_ck, OMAP4_DPLL_USB_DEFFREQ);
- if (rc)
- pr_err("%s: failed to configure USB DPLL!\n", __func__);
-
- /*
- * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power
- * state when turning the ABE clock domain. Workaround this by
- * locking the ABE DPLL on boot.
- * Lock the ABE DPLL in any case to avoid issues with audio.
- */
- rc = clk_set_parent(&abe_dpll_refclk_mux_ck, &sys_32k_ck);
- if (!rc)
- rc = clk_set_rate(&dpll_abe_ck, OMAP4_DPLL_ABE_DEFFREQ);
- if (rc)
- pr_err("%s: failed to configure ABE DPLL!\n", __func__);
-
- return 0;
-}
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index f0986a5..1ed6dd7 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -2,4 +2,5 @@ ifneq ($(CONFIG_OF),)
obj-y += clk.o dpll.o autoidle.o divider.o \
fixed-factor.o gate.o clockdomain.o \
mux-gate.o mux.o
+obj-$(CONFIG_ARCH_OMAP4) += clk-44xx.o
endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 13/36] ARM: dts: omap5 clock data
2013-09-25 8:48 ` Tero Kristo
@ 2013-09-25 8:48 ` Tero Kristo
-1 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-omap, paul, tony, nm, rnayak, bcousson, mturquette
Cc: linux-arm-kernel, devicetree
This patch creates a unique node for each clock in the OMAP5 power,
reset and clock manager (PRCM).
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/boot/dts/omap5.dtsi | 14 +
arch/arm/boot/dts/omap54xx-clocks.dtsi | 1327 ++++++++++++++++++++++++++++++++
2 files changed, 1341 insertions(+)
create mode 100644 arch/arm/boot/dts/omap54xx-clocks.dtsi
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 156b587..f25adc5 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -724,4 +724,18 @@
compatible = "ti,omap5430-bandgap";
};
};
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ /include/ "omap54xx-clocks.dtsi"
+ };
+
+ clockdomains {
+ l3init_clkdm: l3init_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll_usb_ck>;
+ };
+ };
};
diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/omap54xx-clocks.dtsi
new file mode 100644
index 0000000..6e9e293
--- /dev/null
+++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi
@@ -0,0 +1,1327 @@
+/*
+ * Device Tree Source for OMAP5 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+pad_clks_src_ck: pad_clks_src_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+};
+
+pad_clks_ck: pad_clks_ck@4a004108 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&pad_clks_src_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a004108 0x4>;
+};
+
+secure_32k_clk_src_ck: secure_32k_clk_src_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+};
+
+slimbus_src_clk: slimbus_src_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+};
+
+slimbus_clk: slimbus_clk@4a004108 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&slimbus_src_clk>;
+ ti,bit-shift = <10>;
+ reg = <0x4a004108 0x4>;
+};
+
+sys_32k_ck: sys_32k_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+};
+
+virt_12000000_ck: virt_12000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+};
+
+virt_13000000_ck: virt_13000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <13000000>;
+};
+
+virt_16800000_ck: virt_16800000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <16800000>;
+};
+
+virt_19200000_ck: virt_19200000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <19200000>;
+};
+
+virt_26000000_ck: virt_26000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <26000000>;
+};
+
+virt_27000000_ck: virt_27000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <27000000>;
+};
+
+virt_38400000_ck: virt_38400000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <38400000>;
+};
+
+sys_clkin: sys_clkin@4ae06110 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
+ reg = <0x4ae06110 0x4>;
+ ti,index-starts-at-one;
+};
+
+xclk60mhsp1_ck: xclk60mhsp1_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <60000000>;
+};
+
+xclk60mhsp2_ck: xclk60mhsp2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <60000000>;
+};
+
+abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@4ae06108 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
+ reg = <0x4ae06108 0x4>;
+};
+
+abe_dpll_clk_mux: abe_dpll_clk_mux@4ae0610c {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
+ reg = <0x4ae0610c 0x4>;
+};
+
+dpll_abe_ck: dpll_abe_ck@4a0041e0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-m4xen-clock";
+ clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
+ reg = <0x4a0041e0 0x4>, <0x4a0041e4 0x4>, <0x4a0041e8 0x4>, <0x4a0041ec 0x4>;
+};
+
+dpll_abe_x2_ck: dpll_abe_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_abe_ck>;
+};
+
+dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@4a0041f0 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0041f0 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+abe_24m_fclk: abe_24m_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_abe_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <8>;
+};
+
+abe_clk: abe_clk@4a004108 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_m2x2_ck>;
+ reg = <0x4a004108 0x4>;
+ ti,max-div = <4>;
+ ti,index-power-of-two;
+};
+
+abe_iclk: abe_iclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&abe_clk>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+abe_lp_clk_div: abe_lp_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_abe_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <16>;
+};
+
+dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@4a0041f4 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0041f4 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_core_ck: dpll_core_ck@4a004120 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-core-clock";
+ clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>;
+ reg = <0x4a004120 0x4>, <0x4a004124 0x4>, <0x4a004128 0x4>, <0x4a00412c 0x4>;
+};
+
+dpll_core_x2_ck: dpll_core_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_core_ck>;
+};
+
+dpll_core_h21x2_ck: dpll_core_h21x2_ck@4a004150 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a004150 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+c2c_fclk: c2c_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_h21x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+c2c_iclk: c2c_iclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&c2c_fclk>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+dpll_core_h11x2_ck: dpll_core_h11x2_ck@4a004138 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a004138 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_core_h12x2_ck: dpll_core_h12x2_ck@4a00413c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a00413c 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_core_h13x2_ck: dpll_core_h13x2_ck@4a004140 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a004140 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_core_h14x2_ck: dpll_core_h14x2_ck@4a004144 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a004144 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_core_h22x2_ck: dpll_core_h22x2_ck@4a004154 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a004154 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_core_h23x2_ck: dpll_core_h23x2_ck@4a004158 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a004158 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_core_h24x2_ck: dpll_core_h24x2_ck@4a00415c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a00415c 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_core_m2_ck: dpll_core_m2_ck@4a004130 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a004130 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_core_m3x2_ck: dpll_core_m3x2_ck@4a004134 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a004134 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_h12x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dpll_iva_ck: dpll_iva_ck@4a0041a0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>;
+ reg = <0x4a0041a0 0x4>, <0x4a0041a4 0x4>, <0x4a0041a8 0x4>, <0x4a0041ac 0x4>;
+};
+
+dpll_iva_x2_ck: dpll_iva_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_iva_ck>;
+};
+
+dpll_iva_h11x2_ck: dpll_iva_h11x2_ck@4a0041b8 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_iva_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0041b8 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_iva_h12x2_ck: dpll_iva_h12x2_ck@4a0041bc {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_iva_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0041bc 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_h12x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dpll_mpu_ck: dpll_mpu_ck@4a004160 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>;
+ reg = <0x4a004160 0x4>, <0x4a004164 0x4>, <0x4a004168 0x4>, <0x4a00416c 0x4>;
+};
+
+dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a004170 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_mpu_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a004170 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+per_dpll_hs_clk_div: per_dpll_hs_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_abe_m3x2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+dpll_per_ck: dpll_per_ck@4a008140 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>;
+ reg = <0x4a008140 0x4>, <0x4a008144 0x4>, <0x4a008148 0x4>, <0x4a00814c 0x4>;
+};
+
+dpll_per_x2_ck: dpll_per_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_per_ck>;
+};
+
+dpll_per_h11x2_ck: dpll_per_h11x2_ck@4a008158 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008158 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_per_h12x2_ck: dpll_per_h12x2_ck@4a00815c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a00815c 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_per_h14x2_ck: dpll_per_h14x2_ck@4a008164 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008164 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_per_m2_ck: dpll_per_m2_ck@4a008150 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008150 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_per_m2x2_ck: dpll_per_m2x2_ck@4a008150 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008150 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_per_m3x2_ck: dpll_per_m3x2_ck@4a008154 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008154 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_unipro1_ck: dpll_unipro1_ck@4a008200 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin>, <&sys_clkin>;
+ reg = <0x4a008200 0x4>, <0x4a008204 0x4>, <0x4a008208 0x4>, <0x4a00820c 0x4>;
+};
+
+dpll_unipro1_clkdcoldo: dpll_unipro1_clkdcoldo {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_unipro1_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dpll_unipro1_m2_ck: dpll_unipro1_m2_ck@4a008210 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_unipro1_ck>;
+ ti,max-div = <127>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008210 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_unipro2_ck: dpll_unipro2_ck@4a0081c0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin>, <&sys_clkin>;
+ reg = <0x4a0081c0 0x4>, <0x4a0081c4 0x4>, <0x4a0081c8 0x4>, <0x4a0081cc 0x4>;
+};
+
+dpll_unipro2_clkdcoldo: dpll_unipro2_clkdcoldo {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_unipro2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dpll_unipro2_m2_ck: dpll_unipro2_m2_ck@4a0081d0 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_unipro2_ck>;
+ ti,max-div = <127>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0081d0 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_abe_m3x2_ck>;
+ clock-mult = <1>;
+ clock-div = <3>;
+};
+
+dpll_usb_ck: dpll_usb_ck@4a008180 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-j-type-clock";
+ clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>;
+ reg = <0x4a008180 0x4>, <0x4a008184 0x4>, <0x4a008188 0x4>, <0x4a00818c 0x4>;
+};
+
+dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_usb_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dpll_usb_m2_ck: dpll_usb_m2_ck@4a008190 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_usb_ck>;
+ ti,max-div = <127>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008190 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dss_syc_gfclk_div: dss_syc_gfclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+func_128m_clk: func_128m_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_h11x2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+func_12m_fclk: func_12m_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <16>;
+};
+
+func_24m_clk: func_24m_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+};
+
+func_48m_fclk: func_48m_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+};
+
+func_96m_fclk: func_96m_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+l3_iclk_div: l3_iclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_h12x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+gpu_l3_iclk: gpu_l3_iclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l3_iclk_div>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+l3init_60m_fclk: l3init_60m_fclk@4a008104 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_usb_m2_ck>;
+ reg = <0x4a008104 0x4>;
+ ti,dividers = <1>, <8>;
+};
+
+wkupaon_iclk_mux: wkupaon_iclk_mux@4ae06108 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin>, <&abe_lp_clk_div>;
+ reg = <0x4ae06108 0x4>;
+};
+
+l3instr_ts_gclk_div: l3instr_ts_gclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&wkupaon_iclk_mux>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+l4_root_clk_div: l4_root_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l3_iclk_div>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dss_32khz_clk: dss_32khz_clk@4a009420 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <11>;
+ reg = <0x4a009420 0x4>;
+};
+
+dss_48mhz_clk: dss_48mhz_clk@4a009420 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&func_48m_fclk>;
+ ti,bit-shift = <9>;
+ reg = <0x4a009420 0x4>;
+};
+
+dss_dss_clk: dss_dss_clk@4a009420 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll_per_h12x2_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009420 0x4>;
+};
+
+dss_sys_clk: dss_sys_clk@4a009420 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dss_syc_gfclk_div>;
+ ti,bit-shift = <10>;
+ reg = <0x4a009420 0x4>;
+};
+
+gpio1_dbclk: gpio1_dbclk@4ae07938 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4ae07938 0x4>;
+};
+
+gpio2_dbclk: gpio2_dbclk@4a009060 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009060 0x4>;
+};
+
+gpio3_dbclk: gpio3_dbclk@4a009068 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009068 0x4>;
+};
+
+gpio4_dbclk: gpio4_dbclk@4a009070 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009070 0x4>;
+};
+
+gpio5_dbclk: gpio5_dbclk@4a009078 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009078 0x4>;
+};
+
+gpio6_dbclk: gpio6_dbclk@4a009080 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009080 0x4>;
+};
+
+gpio7_dbclk: gpio7_dbclk@4a009110 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009110 0x4>;
+};
+
+gpio8_dbclk: gpio8_dbclk@4a009118 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009118 0x4>;
+};
+
+iss_ctrlclk: iss_ctrlclk@4a009320 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&func_96m_fclk>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009320 0x4>;
+};
+
+lli_txphy_clk: lli_txphy_clk@4a008f20 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll_unipro1_clkdcoldo>;
+ ti,bit-shift = <8>;
+ reg = <0x4a008f20 0x4>;
+};
+
+lli_txphy_ls_clk: lli_txphy_ls_clk@4a008f20 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll_unipro1_m2_ck>;
+ ti,bit-shift = <9>;
+ reg = <0x4a008f20 0x4>;
+};
+
+mmc1_32khz_clk: mmc1_32khz_clk@4a009628 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009628 0x4>;
+};
+
+sata_ref_clk: sata_ref_clk@4a009688 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_clkin>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009688 0x4>;
+};
+
+slimbus1_slimbus_clk: slimbus1_slimbus_clk@4a004560 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&slimbus_clk>;
+ ti,bit-shift = <11>;
+ reg = <0x4a004560 0x4>;
+};
+
+usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk@4a009658 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll_usb_m2_ck>;
+ ti,bit-shift = <13>;
+ reg = <0x4a009658 0x4>;
+};
+
+usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk@4a009658 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll_usb_m2_ck>;
+ ti,bit-shift = <14>;
+ reg = <0x4a009658 0x4>;
+};
+
+usb_host_hs_hsic480m_p3_clk: usb_host_hs_hsic480m_p3_clk@4a009658 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll_usb_m2_ck>;
+ ti,bit-shift = <7>;
+ reg = <0x4a009658 0x4>;
+};
+
+usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk@4a009658 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l3init_60m_fclk>;
+ ti,bit-shift = <11>;
+ reg = <0x4a009658 0x4>;
+};
+
+usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk@4a009658 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l3init_60m_fclk>;
+ ti,bit-shift = <12>;
+ reg = <0x4a009658 0x4>;
+};
+
+usb_host_hs_hsic60m_p3_clk: usb_host_hs_hsic60m_p3_clk@4a009658 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l3init_60m_fclk>;
+ ti,bit-shift = <6>;
+ reg = <0x4a009658 0x4>;
+};
+
+utmi_p1_gfclk: utmi_p1_gfclk@4a009658 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&l3init_60m_fclk>, <&xclk60mhsp1_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009658 0x4>;
+};
+
+usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk@4a009658 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&utmi_p1_gfclk>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009658 0x4>;
+};
+
+utmi_p2_gfclk: utmi_p2_gfclk@4a009658 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&l3init_60m_fclk>, <&xclk60mhsp2_ck>;
+ ti,bit-shift = <25>;
+ reg = <0x4a009658 0x4>;
+};
+
+usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk@4a009658 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&utmi_p2_gfclk>;
+ ti,bit-shift = <9>;
+ reg = <0x4a009658 0x4>;
+};
+
+usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk@4a009658 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l3init_60m_fclk>;
+ ti,bit-shift = <10>;
+ reg = <0x4a009658 0x4>;
+};
+
+usb_otg_ss_refclk960m: usb_otg_ss_refclk960m@4a0096f0 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll_usb_clkdcoldo>;
+ ti,bit-shift = <8>;
+ reg = <0x4a0096f0 0x4>;
+};
+
+usb_phy_cm_clk32k: usb_phy_cm_clk32k@4a008640 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a008640 0x4>;
+};
+
+usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk@4a009668 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l3init_60m_fclk>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009668 0x4>;
+};
+
+usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk@4a009668 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l3init_60m_fclk>;
+ ti,bit-shift = <9>;
+ reg = <0x4a009668 0x4>;
+};
+
+usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk@4a009668 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l3init_60m_fclk>;
+ ti,bit-shift = <10>;
+ reg = <0x4a009668 0x4>;
+};
+
+aess_fclk: aess_fclk@4a004528 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&abe_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a004528 0x4>;
+ ti,max-div = <2>;
+};
+
+dmic_sync_mux_ck: dmic_sync_mux_ck@4a004538 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
+ ti,bit-shift = <26>;
+ reg = <0x4a004538 0x4>;
+};
+
+dmic_gfclk: dmic_gfclk@4a004538 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a004538 0x4>;
+};
+
+fdif_fclk: fdif_fclk@4a009328 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_h11x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009328 0x4>;
+ ti,max-div = <2>;
+};
+
+gpu_core_gclk_mux: gpu_core_gclk_mux@4a009520 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009520 0x4>;
+};
+
+gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@4a009520 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
+ ti,bit-shift = <25>;
+ reg = <0x4a009520 0x4>;
+};
+
+hsi_fclk: hsi_fclk@4a009638 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009638 0x4>;
+ ti,max-div = <2>;
+};
+
+mcasp_sync_mux_ck: mcasp_sync_mux_ck@4a004540 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
+ ti,bit-shift = <26>;
+ reg = <0x4a004540 0x4>;
+};
+
+mcasp_gfclk: mcasp_gfclk@4a004540 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a004540 0x4>;
+};
+
+mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck@4a004548 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
+ ti,bit-shift = <26>;
+ reg = <0x4a004548 0x4>;
+};
+
+mcbsp1_gfclk: mcbsp1_gfclk@4a004548 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a004548 0x4>;
+};
+
+mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck@4a004550 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
+ ti,bit-shift = <26>;
+ reg = <0x4a004550 0x4>;
+};
+
+mcbsp2_gfclk: mcbsp2_gfclk@4a004550 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a004550 0x4>;
+};
+
+mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck@4a004558 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
+ ti,bit-shift = <26>;
+ reg = <0x4a004558 0x4>;
+};
+
+mcbsp3_gfclk: mcbsp3_gfclk@4a004558 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a004558 0x4>;
+};
+
+mmc1_fclk_mux: mmc1_fclk_mux@4a009628 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009628 0x4>;
+};
+
+mmc1_fclk: mmc1_fclk@4a009628 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&mmc1_fclk_mux>;
+ ti,bit-shift = <25>;
+ reg = <0x4a009628 0x4>;
+ ti,max-div = <2>;
+};
+
+mmc2_fclk_mux: mmc2_fclk_mux@4a009630 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009630 0x4>;
+};
+
+mmc2_fclk: mmc2_fclk@4a009630 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&mmc2_fclk_mux>;
+ ti,bit-shift = <25>;
+ reg = <0x4a009630 0x4>;
+ ti,max-div = <2>;
+};
+
+timer10_gfclk_mux: timer10_gfclk_mux@4a009028 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009028 0x4>;
+};
+
+timer11_gfclk_mux: timer11_gfclk_mux@4a009030 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009030 0x4>;
+};
+
+timer1_gfclk_mux: timer1_gfclk_mux@4ae07940 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4ae07940 0x4>;
+};
+
+timer2_gfclk_mux: timer2_gfclk_mux@4a009038 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009038 0x4>;
+};
+
+timer3_gfclk_mux: timer3_gfclk_mux@4a009040 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009040 0x4>;
+};
+
+timer4_gfclk_mux: timer4_gfclk_mux@4a009048 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009048 0x4>;
+};
+
+timer5_gfclk_mux: timer5_gfclk_mux@4a004568 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a004568 0x4>;
+};
+
+timer6_gfclk_mux: timer6_gfclk_mux@4a004570 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a004570 0x4>;
+};
+
+timer7_gfclk_mux: timer7_gfclk_mux@4a004578 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a004578 0x4>;
+};
+
+timer8_gfclk_mux: timer8_gfclk_mux@4a004580 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a004580 0x4>;
+};
+
+timer9_gfclk_mux: timer9_gfclk_mux@4a009050 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009050 0x4>;
+};
+
+auxclk0_src_ck: auxclk0_src_ck@4ae0a310 {
+ #clock-cells = <0>;
+ compatible = "ti,no-wait-mux-gate-clock";
+ clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ ti,gate-bit-shift = <8>;
+ reg = <0x4ae0a310 0x4>, <0x4ae0a310 0x4>;
+ ti,mux-bit-shift = <1>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+auxclk0_ck: auxclk0_ck@4ae0a310 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&auxclk0_src_ck>;
+ ti,bit-shift = <16>;
+ reg = <0x4ae0a310 0x4>;
+ ti,max-div = <16>;
+};
+
+auxclk1_src_ck: auxclk1_src_ck@4ae0a314 {
+ #clock-cells = <0>;
+ compatible = "ti,no-wait-mux-gate-clock";
+ clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ ti,gate-bit-shift = <8>;
+ reg = <0x4ae0a314 0x4>, <0x4ae0a314 0x4>;
+ ti,mux-bit-shift = <1>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+auxclk1_ck: auxclk1_ck@4ae0a314 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&auxclk1_src_ck>;
+ ti,bit-shift = <16>;
+ reg = <0x4ae0a314 0x4>;
+ ti,max-div = <16>;
+};
+
+auxclk2_src_ck: auxclk2_src_ck@4ae0a318 {
+ #clock-cells = <0>;
+ compatible = "ti,no-wait-mux-gate-clock";
+ clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ ti,gate-bit-shift = <8>;
+ reg = <0x4ae0a318 0x4>, <0x4ae0a318 0x4>;
+ ti,mux-bit-shift = <1>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+auxclk2_ck: auxclk2_ck@4ae0a318 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&auxclk2_src_ck>;
+ ti,bit-shift = <16>;
+ reg = <0x4ae0a318 0x4>;
+ ti,max-div = <16>;
+};
+
+auxclk3_src_ck: auxclk3_src_ck@4ae0a31c {
+ #clock-cells = <0>;
+ compatible = "ti,no-wait-mux-gate-clock";
+ clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ ti,gate-bit-shift = <8>;
+ reg = <0x4ae0a31c 0x4>, <0x4ae0a31c 0x4>;
+ ti,mux-bit-shift = <1>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+auxclk3_ck: auxclk3_ck@4ae0a31c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&auxclk3_src_ck>;
+ ti,bit-shift = <16>;
+ reg = <0x4ae0a31c 0x4>;
+ ti,max-div = <16>;
+};
+
+auxclk4_src_ck: auxclk4_src_ck@4ae0a320 {
+ #clock-cells = <0>;
+ compatible = "ti,no-wait-mux-gate-clock";
+ clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ ti,gate-bit-shift = <8>;
+ reg = <0x4ae0a320 0x4>, <0x4ae0a320 0x4>;
+ ti,mux-bit-shift = <1>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+auxclk4_ck: auxclk4_ck@4ae0a320 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&auxclk4_src_ck>;
+ ti,bit-shift = <16>;
+ reg = <0x4ae0a320 0x4>;
+ ti,max-div = <16>;
+};
+
+auxclkreq0_ck: auxclkreq0_ck@4ae0a210 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x4ae0a210 0x4>;
+};
+
+auxclkreq1_ck: auxclkreq1_ck@4ae0a214 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x4ae0a214 0x4>;
+};
+
+auxclkreq2_ck: auxclkreq2_ck@4ae0a218 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x4ae0a218 0x4>;
+};
+
+auxclkreq3_ck: auxclkreq3_ck@4ae0a21c {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x4ae0a21c 0x4>;
+};
+
+dummy_ck: dummy_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
\ No newline at end of file
--
1.7.9.5
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 13/36] ARM: dts: omap5 clock data
@ 2013-09-25 8:48 ` Tero Kristo
0 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-arm-kernel
This patch creates a unique node for each clock in the OMAP5 power,
reset and clock manager (PRCM).
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/boot/dts/omap5.dtsi | 14 +
arch/arm/boot/dts/omap54xx-clocks.dtsi | 1327 ++++++++++++++++++++++++++++++++
2 files changed, 1341 insertions(+)
create mode 100644 arch/arm/boot/dts/omap54xx-clocks.dtsi
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 156b587..f25adc5 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -724,4 +724,18 @@
compatible = "ti,omap5430-bandgap";
};
};
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ /include/ "omap54xx-clocks.dtsi"
+ };
+
+ clockdomains {
+ l3init_clkdm: l3init_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll_usb_ck>;
+ };
+ };
};
diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/omap54xx-clocks.dtsi
new file mode 100644
index 0000000..6e9e293
--- /dev/null
+++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi
@@ -0,0 +1,1327 @@
+/*
+ * Device Tree Source for OMAP5 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+pad_clks_src_ck: pad_clks_src_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+};
+
+pad_clks_ck: pad_clks_ck at 4a004108 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&pad_clks_src_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a004108 0x4>;
+};
+
+secure_32k_clk_src_ck: secure_32k_clk_src_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+};
+
+slimbus_src_clk: slimbus_src_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+};
+
+slimbus_clk: slimbus_clk at 4a004108 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&slimbus_src_clk>;
+ ti,bit-shift = <10>;
+ reg = <0x4a004108 0x4>;
+};
+
+sys_32k_ck: sys_32k_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+};
+
+virt_12000000_ck: virt_12000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+};
+
+virt_13000000_ck: virt_13000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <13000000>;
+};
+
+virt_16800000_ck: virt_16800000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <16800000>;
+};
+
+virt_19200000_ck: virt_19200000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <19200000>;
+};
+
+virt_26000000_ck: virt_26000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <26000000>;
+};
+
+virt_27000000_ck: virt_27000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <27000000>;
+};
+
+virt_38400000_ck: virt_38400000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <38400000>;
+};
+
+sys_clkin: sys_clkin at 4ae06110 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
+ reg = <0x4ae06110 0x4>;
+ ti,index-starts-at-one;
+};
+
+xclk60mhsp1_ck: xclk60mhsp1_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <60000000>;
+};
+
+xclk60mhsp2_ck: xclk60mhsp2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <60000000>;
+};
+
+abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux at 4ae06108 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
+ reg = <0x4ae06108 0x4>;
+};
+
+abe_dpll_clk_mux: abe_dpll_clk_mux at 4ae0610c {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
+ reg = <0x4ae0610c 0x4>;
+};
+
+dpll_abe_ck: dpll_abe_ck at 4a0041e0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-m4xen-clock";
+ clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
+ reg = <0x4a0041e0 0x4>, <0x4a0041e4 0x4>, <0x4a0041e8 0x4>, <0x4a0041ec 0x4>;
+};
+
+dpll_abe_x2_ck: dpll_abe_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_abe_ck>;
+};
+
+dpll_abe_m2x2_ck: dpll_abe_m2x2_ck at 4a0041f0 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0041f0 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+abe_24m_fclk: abe_24m_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_abe_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <8>;
+};
+
+abe_clk: abe_clk at 4a004108 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_m2x2_ck>;
+ reg = <0x4a004108 0x4>;
+ ti,max-div = <4>;
+ ti,index-power-of-two;
+};
+
+abe_iclk: abe_iclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&abe_clk>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+abe_lp_clk_div: abe_lp_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_abe_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <16>;
+};
+
+dpll_abe_m3x2_ck: dpll_abe_m3x2_ck at 4a0041f4 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0041f4 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_core_ck: dpll_core_ck at 4a004120 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-core-clock";
+ clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>;
+ reg = <0x4a004120 0x4>, <0x4a004124 0x4>, <0x4a004128 0x4>, <0x4a00412c 0x4>;
+};
+
+dpll_core_x2_ck: dpll_core_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_core_ck>;
+};
+
+dpll_core_h21x2_ck: dpll_core_h21x2_ck at 4a004150 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a004150 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+c2c_fclk: c2c_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_h21x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+c2c_iclk: c2c_iclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&c2c_fclk>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+dpll_core_h11x2_ck: dpll_core_h11x2_ck at 4a004138 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a004138 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_core_h12x2_ck: dpll_core_h12x2_ck at 4a00413c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a00413c 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_core_h13x2_ck: dpll_core_h13x2_ck at 4a004140 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a004140 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_core_h14x2_ck: dpll_core_h14x2_ck at 4a004144 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a004144 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_core_h22x2_ck: dpll_core_h22x2_ck at 4a004154 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a004154 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_core_h23x2_ck: dpll_core_h23x2_ck at 4a004158 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a004158 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_core_h24x2_ck: dpll_core_h24x2_ck at 4a00415c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a00415c 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_core_m2_ck: dpll_core_m2_ck at 4a004130 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a004130 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_core_m3x2_ck: dpll_core_m3x2_ck at 4a004134 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a004134 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_h12x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dpll_iva_ck: dpll_iva_ck at 4a0041a0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>;
+ reg = <0x4a0041a0 0x4>, <0x4a0041a4 0x4>, <0x4a0041a8 0x4>, <0x4a0041ac 0x4>;
+};
+
+dpll_iva_x2_ck: dpll_iva_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_iva_ck>;
+};
+
+dpll_iva_h11x2_ck: dpll_iva_h11x2_ck at 4a0041b8 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_iva_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0041b8 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_iva_h12x2_ck: dpll_iva_h12x2_ck at 4a0041bc {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_iva_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0041bc 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_h12x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dpll_mpu_ck: dpll_mpu_ck at 4a004160 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>;
+ reg = <0x4a004160 0x4>, <0x4a004164 0x4>, <0x4a004168 0x4>, <0x4a00416c 0x4>;
+};
+
+dpll_mpu_m2_ck: dpll_mpu_m2_ck at 4a004170 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_mpu_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a004170 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+per_dpll_hs_clk_div: per_dpll_hs_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_abe_m3x2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+dpll_per_ck: dpll_per_ck at 4a008140 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>;
+ reg = <0x4a008140 0x4>, <0x4a008144 0x4>, <0x4a008148 0x4>, <0x4a00814c 0x4>;
+};
+
+dpll_per_x2_ck: dpll_per_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_per_ck>;
+};
+
+dpll_per_h11x2_ck: dpll_per_h11x2_ck at 4a008158 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008158 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_per_h12x2_ck: dpll_per_h12x2_ck at 4a00815c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a00815c 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_per_h14x2_ck: dpll_per_h14x2_ck at 4a008164 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008164 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_per_m2_ck: dpll_per_m2_ck at 4a008150 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008150 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_per_m2x2_ck: dpll_per_m2x2_ck at 4a008150 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008150 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_per_m3x2_ck: dpll_per_m3x2_ck at 4a008154 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008154 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_unipro1_ck: dpll_unipro1_ck at 4a008200 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin>, <&sys_clkin>;
+ reg = <0x4a008200 0x4>, <0x4a008204 0x4>, <0x4a008208 0x4>, <0x4a00820c 0x4>;
+};
+
+dpll_unipro1_clkdcoldo: dpll_unipro1_clkdcoldo {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_unipro1_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dpll_unipro1_m2_ck: dpll_unipro1_m2_ck at 4a008210 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_unipro1_ck>;
+ ti,max-div = <127>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008210 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_unipro2_ck: dpll_unipro2_ck at 4a0081c0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin>, <&sys_clkin>;
+ reg = <0x4a0081c0 0x4>, <0x4a0081c4 0x4>, <0x4a0081c8 0x4>, <0x4a0081cc 0x4>;
+};
+
+dpll_unipro2_clkdcoldo: dpll_unipro2_clkdcoldo {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_unipro2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dpll_unipro2_m2_ck: dpll_unipro2_m2_ck at 4a0081d0 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_unipro2_ck>;
+ ti,max-div = <127>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0081d0 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_abe_m3x2_ck>;
+ clock-mult = <1>;
+ clock-div = <3>;
+};
+
+dpll_usb_ck: dpll_usb_ck at 4a008180 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-j-type-clock";
+ clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>;
+ reg = <0x4a008180 0x4>, <0x4a008184 0x4>, <0x4a008188 0x4>, <0x4a00818c 0x4>;
+};
+
+dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_usb_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dpll_usb_m2_ck: dpll_usb_m2_ck at 4a008190 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_usb_ck>;
+ ti,max-div = <127>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008190 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dss_syc_gfclk_div: dss_syc_gfclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+func_128m_clk: func_128m_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_h11x2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+func_12m_fclk: func_12m_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <16>;
+};
+
+func_24m_clk: func_24m_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+};
+
+func_48m_fclk: func_48m_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+};
+
+func_96m_fclk: func_96m_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+l3_iclk_div: l3_iclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_h12x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+gpu_l3_iclk: gpu_l3_iclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l3_iclk_div>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+l3init_60m_fclk: l3init_60m_fclk at 4a008104 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_usb_m2_ck>;
+ reg = <0x4a008104 0x4>;
+ ti,dividers = <1>, <8>;
+};
+
+wkupaon_iclk_mux: wkupaon_iclk_mux at 4ae06108 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin>, <&abe_lp_clk_div>;
+ reg = <0x4ae06108 0x4>;
+};
+
+l3instr_ts_gclk_div: l3instr_ts_gclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&wkupaon_iclk_mux>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+l4_root_clk_div: l4_root_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l3_iclk_div>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dss_32khz_clk: dss_32khz_clk at 4a009420 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <11>;
+ reg = <0x4a009420 0x4>;
+};
+
+dss_48mhz_clk: dss_48mhz_clk at 4a009420 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&func_48m_fclk>;
+ ti,bit-shift = <9>;
+ reg = <0x4a009420 0x4>;
+};
+
+dss_dss_clk: dss_dss_clk at 4a009420 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll_per_h12x2_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009420 0x4>;
+};
+
+dss_sys_clk: dss_sys_clk at 4a009420 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dss_syc_gfclk_div>;
+ ti,bit-shift = <10>;
+ reg = <0x4a009420 0x4>;
+};
+
+gpio1_dbclk: gpio1_dbclk at 4ae07938 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4ae07938 0x4>;
+};
+
+gpio2_dbclk: gpio2_dbclk at 4a009060 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009060 0x4>;
+};
+
+gpio3_dbclk: gpio3_dbclk at 4a009068 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009068 0x4>;
+};
+
+gpio4_dbclk: gpio4_dbclk at 4a009070 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009070 0x4>;
+};
+
+gpio5_dbclk: gpio5_dbclk at 4a009078 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009078 0x4>;
+};
+
+gpio6_dbclk: gpio6_dbclk at 4a009080 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009080 0x4>;
+};
+
+gpio7_dbclk: gpio7_dbclk at 4a009110 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009110 0x4>;
+};
+
+gpio8_dbclk: gpio8_dbclk at 4a009118 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009118 0x4>;
+};
+
+iss_ctrlclk: iss_ctrlclk at 4a009320 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&func_96m_fclk>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009320 0x4>;
+};
+
+lli_txphy_clk: lli_txphy_clk at 4a008f20 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll_unipro1_clkdcoldo>;
+ ti,bit-shift = <8>;
+ reg = <0x4a008f20 0x4>;
+};
+
+lli_txphy_ls_clk: lli_txphy_ls_clk at 4a008f20 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll_unipro1_m2_ck>;
+ ti,bit-shift = <9>;
+ reg = <0x4a008f20 0x4>;
+};
+
+mmc1_32khz_clk: mmc1_32khz_clk at 4a009628 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009628 0x4>;
+};
+
+sata_ref_clk: sata_ref_clk at 4a009688 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_clkin>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009688 0x4>;
+};
+
+slimbus1_slimbus_clk: slimbus1_slimbus_clk at 4a004560 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&slimbus_clk>;
+ ti,bit-shift = <11>;
+ reg = <0x4a004560 0x4>;
+};
+
+usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk at 4a009658 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll_usb_m2_ck>;
+ ti,bit-shift = <13>;
+ reg = <0x4a009658 0x4>;
+};
+
+usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk at 4a009658 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll_usb_m2_ck>;
+ ti,bit-shift = <14>;
+ reg = <0x4a009658 0x4>;
+};
+
+usb_host_hs_hsic480m_p3_clk: usb_host_hs_hsic480m_p3_clk at 4a009658 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll_usb_m2_ck>;
+ ti,bit-shift = <7>;
+ reg = <0x4a009658 0x4>;
+};
+
+usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk at 4a009658 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l3init_60m_fclk>;
+ ti,bit-shift = <11>;
+ reg = <0x4a009658 0x4>;
+};
+
+usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk at 4a009658 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l3init_60m_fclk>;
+ ti,bit-shift = <12>;
+ reg = <0x4a009658 0x4>;
+};
+
+usb_host_hs_hsic60m_p3_clk: usb_host_hs_hsic60m_p3_clk at 4a009658 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l3init_60m_fclk>;
+ ti,bit-shift = <6>;
+ reg = <0x4a009658 0x4>;
+};
+
+utmi_p1_gfclk: utmi_p1_gfclk at 4a009658 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&l3init_60m_fclk>, <&xclk60mhsp1_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009658 0x4>;
+};
+
+usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk at 4a009658 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&utmi_p1_gfclk>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009658 0x4>;
+};
+
+utmi_p2_gfclk: utmi_p2_gfclk at 4a009658 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&l3init_60m_fclk>, <&xclk60mhsp2_ck>;
+ ti,bit-shift = <25>;
+ reg = <0x4a009658 0x4>;
+};
+
+usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk at 4a009658 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&utmi_p2_gfclk>;
+ ti,bit-shift = <9>;
+ reg = <0x4a009658 0x4>;
+};
+
+usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk at 4a009658 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l3init_60m_fclk>;
+ ti,bit-shift = <10>;
+ reg = <0x4a009658 0x4>;
+};
+
+usb_otg_ss_refclk960m: usb_otg_ss_refclk960m at 4a0096f0 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll_usb_clkdcoldo>;
+ ti,bit-shift = <8>;
+ reg = <0x4a0096f0 0x4>;
+};
+
+usb_phy_cm_clk32k: usb_phy_cm_clk32k at 4a008640 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a008640 0x4>;
+};
+
+usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk at 4a009668 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l3init_60m_fclk>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009668 0x4>;
+};
+
+usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk at 4a009668 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l3init_60m_fclk>;
+ ti,bit-shift = <9>;
+ reg = <0x4a009668 0x4>;
+};
+
+usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk at 4a009668 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l3init_60m_fclk>;
+ ti,bit-shift = <10>;
+ reg = <0x4a009668 0x4>;
+};
+
+aess_fclk: aess_fclk at 4a004528 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&abe_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a004528 0x4>;
+ ti,max-div = <2>;
+};
+
+dmic_sync_mux_ck: dmic_sync_mux_ck at 4a004538 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
+ ti,bit-shift = <26>;
+ reg = <0x4a004538 0x4>;
+};
+
+dmic_gfclk: dmic_gfclk at 4a004538 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a004538 0x4>;
+};
+
+fdif_fclk: fdif_fclk at 4a009328 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_h11x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009328 0x4>;
+ ti,max-div = <2>;
+};
+
+gpu_core_gclk_mux: gpu_core_gclk_mux at 4a009520 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009520 0x4>;
+};
+
+gpu_hyd_gclk_mux: gpu_hyd_gclk_mux at 4a009520 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
+ ti,bit-shift = <25>;
+ reg = <0x4a009520 0x4>;
+};
+
+hsi_fclk: hsi_fclk at 4a009638 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009638 0x4>;
+ ti,max-div = <2>;
+};
+
+mcasp_sync_mux_ck: mcasp_sync_mux_ck at 4a004540 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
+ ti,bit-shift = <26>;
+ reg = <0x4a004540 0x4>;
+};
+
+mcasp_gfclk: mcasp_gfclk at 4a004540 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a004540 0x4>;
+};
+
+mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck at 4a004548 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
+ ti,bit-shift = <26>;
+ reg = <0x4a004548 0x4>;
+};
+
+mcbsp1_gfclk: mcbsp1_gfclk at 4a004548 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a004548 0x4>;
+};
+
+mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck at 4a004550 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
+ ti,bit-shift = <26>;
+ reg = <0x4a004550 0x4>;
+};
+
+mcbsp2_gfclk: mcbsp2_gfclk at 4a004550 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a004550 0x4>;
+};
+
+mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck at 4a004558 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
+ ti,bit-shift = <26>;
+ reg = <0x4a004558 0x4>;
+};
+
+mcbsp3_gfclk: mcbsp3_gfclk at 4a004558 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a004558 0x4>;
+};
+
+mmc1_fclk_mux: mmc1_fclk_mux at 4a009628 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009628 0x4>;
+};
+
+mmc1_fclk: mmc1_fclk at 4a009628 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&mmc1_fclk_mux>;
+ ti,bit-shift = <25>;
+ reg = <0x4a009628 0x4>;
+ ti,max-div = <2>;
+};
+
+mmc2_fclk_mux: mmc2_fclk_mux at 4a009630 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009630 0x4>;
+};
+
+mmc2_fclk: mmc2_fclk at 4a009630 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&mmc2_fclk_mux>;
+ ti,bit-shift = <25>;
+ reg = <0x4a009630 0x4>;
+ ti,max-div = <2>;
+};
+
+timer10_gfclk_mux: timer10_gfclk_mux at 4a009028 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009028 0x4>;
+};
+
+timer11_gfclk_mux: timer11_gfclk_mux at 4a009030 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009030 0x4>;
+};
+
+timer1_gfclk_mux: timer1_gfclk_mux at 4ae07940 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4ae07940 0x4>;
+};
+
+timer2_gfclk_mux: timer2_gfclk_mux at 4a009038 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009038 0x4>;
+};
+
+timer3_gfclk_mux: timer3_gfclk_mux at 4a009040 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009040 0x4>;
+};
+
+timer4_gfclk_mux: timer4_gfclk_mux at 4a009048 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009048 0x4>;
+};
+
+timer5_gfclk_mux: timer5_gfclk_mux at 4a004568 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a004568 0x4>;
+};
+
+timer6_gfclk_mux: timer6_gfclk_mux at 4a004570 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a004570 0x4>;
+};
+
+timer7_gfclk_mux: timer7_gfclk_mux at 4a004578 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a004578 0x4>;
+};
+
+timer8_gfclk_mux: timer8_gfclk_mux at 4a004580 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a004580 0x4>;
+};
+
+timer9_gfclk_mux: timer9_gfclk_mux at 4a009050 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009050 0x4>;
+};
+
+auxclk0_src_ck: auxclk0_src_ck at 4ae0a310 {
+ #clock-cells = <0>;
+ compatible = "ti,no-wait-mux-gate-clock";
+ clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ ti,gate-bit-shift = <8>;
+ reg = <0x4ae0a310 0x4>, <0x4ae0a310 0x4>;
+ ti,mux-bit-shift = <1>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+auxclk0_ck: auxclk0_ck at 4ae0a310 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&auxclk0_src_ck>;
+ ti,bit-shift = <16>;
+ reg = <0x4ae0a310 0x4>;
+ ti,max-div = <16>;
+};
+
+auxclk1_src_ck: auxclk1_src_ck at 4ae0a314 {
+ #clock-cells = <0>;
+ compatible = "ti,no-wait-mux-gate-clock";
+ clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ ti,gate-bit-shift = <8>;
+ reg = <0x4ae0a314 0x4>, <0x4ae0a314 0x4>;
+ ti,mux-bit-shift = <1>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+auxclk1_ck: auxclk1_ck at 4ae0a314 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&auxclk1_src_ck>;
+ ti,bit-shift = <16>;
+ reg = <0x4ae0a314 0x4>;
+ ti,max-div = <16>;
+};
+
+auxclk2_src_ck: auxclk2_src_ck at 4ae0a318 {
+ #clock-cells = <0>;
+ compatible = "ti,no-wait-mux-gate-clock";
+ clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ ti,gate-bit-shift = <8>;
+ reg = <0x4ae0a318 0x4>, <0x4ae0a318 0x4>;
+ ti,mux-bit-shift = <1>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+auxclk2_ck: auxclk2_ck at 4ae0a318 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&auxclk2_src_ck>;
+ ti,bit-shift = <16>;
+ reg = <0x4ae0a318 0x4>;
+ ti,max-div = <16>;
+};
+
+auxclk3_src_ck: auxclk3_src_ck at 4ae0a31c {
+ #clock-cells = <0>;
+ compatible = "ti,no-wait-mux-gate-clock";
+ clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ ti,gate-bit-shift = <8>;
+ reg = <0x4ae0a31c 0x4>, <0x4ae0a31c 0x4>;
+ ti,mux-bit-shift = <1>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+auxclk3_ck: auxclk3_ck at 4ae0a31c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&auxclk3_src_ck>;
+ ti,bit-shift = <16>;
+ reg = <0x4ae0a31c 0x4>;
+ ti,max-div = <16>;
+};
+
+auxclk4_src_ck: auxclk4_src_ck at 4ae0a320 {
+ #clock-cells = <0>;
+ compatible = "ti,no-wait-mux-gate-clock";
+ clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ ti,gate-bit-shift = <8>;
+ reg = <0x4ae0a320 0x4>, <0x4ae0a320 0x4>;
+ ti,mux-bit-shift = <1>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+auxclk4_ck: auxclk4_ck at 4ae0a320 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&auxclk4_src_ck>;
+ ti,bit-shift = <16>;
+ reg = <0x4ae0a320 0x4>;
+ ti,max-div = <16>;
+};
+
+auxclkreq0_ck: auxclkreq0_ck at 4ae0a210 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x4ae0a210 0x4>;
+};
+
+auxclkreq1_ck: auxclkreq1_ck at 4ae0a214 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x4ae0a214 0x4>;
+};
+
+auxclkreq2_ck: auxclkreq2_ck at 4ae0a218 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x4ae0a218 0x4>;
+};
+
+auxclkreq3_ck: auxclkreq3_ck at 4ae0a21c {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x4ae0a21c 0x4>;
+};
+
+dummy_ck: dummy_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
\ No newline at end of file
--
1.7.9.5
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 14/36] CLK: TI: add omap5 clock init file
2013-09-25 8:48 ` Tero Kristo
@ 2013-09-25 8:48 ` Tero Kristo
-1 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-omap-u79uwXL29TY76Z2rM5mHXA, paul-DWxLp4Yu+b8AvxtiuMwx3w,
tony-4v6yS6AI5VpBDgjK7y7TUQ, nm-l0cyMroinI0, rnayak-l0cyMroinI0,
bcousson-rdvid1DuHRBWk0Htik3J/w,
mturquette-QSEj5FYQhm4dnm+yROfE0A
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
clk-54xx.c now contains the clock init functionality for omap5, including
DT clock registration and adding of static clkdev entries.
Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
arch/arm/mach-omap2/io.c | 1 +
drivers/clk/ti/Makefile | 1 +
drivers/clk/ti/clk-54xx.c | 241 +++++++++++++++++++++++++++++++++++++++++++++
include/linux/clk/ti.h | 1 +
4 files changed, 244 insertions(+)
create mode 100644 drivers/clk/ti/clk-54xx.c
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index ff2113c..205bb1d 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -650,6 +650,7 @@ void __init omap5_init_early(void)
omap54xx_clockdomains_init();
omap54xx_hwmod_init();
omap_hwmod_init_postsetup();
+ omap_clk_init = omap5xxx_clk_init;
}
#endif
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 1ed6dd7..9d785e5 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -3,4 +3,5 @@ obj-y += clk.o dpll.o autoidle.o divider.o \
fixed-factor.o gate.o clockdomain.o \
mux-gate.o mux.o
obj-$(CONFIG_ARCH_OMAP4) += clk-44xx.o
+obj-$(CONFIG_SOC_OMAP5) += clk-54xx.o
endif
diff --git a/drivers/clk/ti/clk-54xx.c b/drivers/clk/ti/clk-54xx.c
new file mode 100644
index 0000000..efa81ab
--- /dev/null
+++ b/drivers/clk/ti/clk-54xx.c
@@ -0,0 +1,241 @@
+/*
+ * OMAP5 Clock init
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo (t-kristo-l0cyMroinI0@public.gmane.org)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/clk-private.h>
+#include <linux/clkdev.h>
+#include <linux/io.h>
+#include <linux/clk/ti.h>
+
+#define OMAP5_DPLL_ABE_DEFFREQ 98304000
+
+static struct ti_dt_clk omap54xx_clks[] = {
+ DT_CLK(NULL, "pad_clks_src_ck", "pad_clks_src_ck"),
+ DT_CLK(NULL, "pad_clks_ck", "pad_clks_ck"),
+ DT_CLK(NULL, "secure_32k_clk_src_ck", "secure_32k_clk_src_ck"),
+ DT_CLK(NULL, "slimbus_src_clk", "slimbus_src_clk"),
+ DT_CLK(NULL, "slimbus_clk", "slimbus_clk"),
+ DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"),
+ DT_CLK(NULL, "virt_12000000_ck", "virt_12000000_ck"),
+ DT_CLK(NULL, "virt_13000000_ck", "virt_13000000_ck"),
+ DT_CLK(NULL, "virt_16800000_ck", "virt_16800000_ck"),
+ DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
+ DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
+ DT_CLK(NULL, "virt_27000000_ck", "virt_27000000_ck"),
+ DT_CLK(NULL, "virt_38400000_ck", "virt_38400000_ck"),
+ DT_CLK(NULL, "sys_clkin", "sys_clkin"),
+ DT_CLK(NULL, "xclk60mhsp1_ck", "xclk60mhsp1_ck"),
+ DT_CLK(NULL, "xclk60mhsp2_ck", "xclk60mhsp2_ck"),
+ DT_CLK(NULL, "abe_dpll_bypass_clk_mux", "abe_dpll_bypass_clk_mux"),
+ DT_CLK(NULL, "abe_dpll_clk_mux", "abe_dpll_clk_mux"),
+ DT_CLK(NULL, "dpll_abe_ck", "dpll_abe_ck"),
+ DT_CLK(NULL, "dpll_abe_x2_ck", "dpll_abe_x2_ck"),
+ DT_CLK(NULL, "dpll_abe_m2x2_ck", "dpll_abe_m2x2_ck"),
+ DT_CLK(NULL, "abe_24m_fclk", "abe_24m_fclk"),
+ DT_CLK(NULL, "abe_clk", "abe_clk"),
+ DT_CLK(NULL, "abe_iclk", "abe_iclk"),
+ DT_CLK(NULL, "abe_lp_clk_div", "abe_lp_clk_div"),
+ DT_CLK(NULL, "dpll_abe_m3x2_ck", "dpll_abe_m3x2_ck"),
+ DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
+ DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
+ DT_CLK(NULL, "dpll_core_h21x2_ck", "dpll_core_h21x2_ck"),
+ DT_CLK(NULL, "c2c_fclk", "c2c_fclk"),
+ DT_CLK(NULL, "c2c_iclk", "c2c_iclk"),
+ DT_CLK(NULL, "custefuse_sys_gfclk_div", "custefuse_sys_gfclk_div"),
+ DT_CLK(NULL, "dpll_core_h11x2_ck", "dpll_core_h11x2_ck"),
+ DT_CLK(NULL, "dpll_core_h12x2_ck", "dpll_core_h12x2_ck"),
+ DT_CLK(NULL, "dpll_core_h13x2_ck", "dpll_core_h13x2_ck"),
+ DT_CLK(NULL, "dpll_core_h14x2_ck", "dpll_core_h14x2_ck"),
+ DT_CLK(NULL, "dpll_core_h22x2_ck", "dpll_core_h22x2_ck"),
+ DT_CLK(NULL, "dpll_core_h23x2_ck", "dpll_core_h23x2_ck"),
+ DT_CLK(NULL, "dpll_core_h24x2_ck", "dpll_core_h24x2_ck"),
+ DT_CLK(NULL, "dpll_core_m2_ck", "dpll_core_m2_ck"),
+ DT_CLK(NULL, "dpll_core_m3x2_ck", "dpll_core_m3x2_ck"),
+ DT_CLK(NULL, "iva_dpll_hs_clk_div", "iva_dpll_hs_clk_div"),
+ DT_CLK(NULL, "dpll_iva_ck", "dpll_iva_ck"),
+ DT_CLK(NULL, "dpll_iva_x2_ck", "dpll_iva_x2_ck"),
+ DT_CLK(NULL, "dpll_iva_h11x2_ck", "dpll_iva_h11x2_ck"),
+ DT_CLK(NULL, "dpll_iva_h12x2_ck", "dpll_iva_h12x2_ck"),
+ DT_CLK(NULL, "mpu_dpll_hs_clk_div", "mpu_dpll_hs_clk_div"),
+ DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"),
+ DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"),
+ DT_CLK(NULL, "per_dpll_hs_clk_div", "per_dpll_hs_clk_div"),
+ DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"),
+ DT_CLK(NULL, "dpll_per_x2_ck", "dpll_per_x2_ck"),
+ DT_CLK(NULL, "dpll_per_h11x2_ck", "dpll_per_h11x2_ck"),
+ DT_CLK(NULL, "dpll_per_h12x2_ck", "dpll_per_h12x2_ck"),
+ DT_CLK(NULL, "dpll_per_h14x2_ck", "dpll_per_h14x2_ck"),
+ DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"),
+ DT_CLK(NULL, "dpll_per_m2x2_ck", "dpll_per_m2x2_ck"),
+ DT_CLK(NULL, "dpll_per_m3x2_ck", "dpll_per_m3x2_ck"),
+ DT_CLK(NULL, "dpll_unipro1_ck", "dpll_unipro1_ck"),
+ DT_CLK(NULL, "dpll_unipro1_clkdcoldo", "dpll_unipro1_clkdcoldo"),
+ DT_CLK(NULL, "dpll_unipro1_m2_ck", "dpll_unipro1_m2_ck"),
+ DT_CLK(NULL, "dpll_unipro2_ck", "dpll_unipro2_ck"),
+ DT_CLK(NULL, "dpll_unipro2_clkdcoldo", "dpll_unipro2_clkdcoldo"),
+ DT_CLK(NULL, "dpll_unipro2_m2_ck", "dpll_unipro2_m2_ck"),
+ DT_CLK(NULL, "usb_dpll_hs_clk_div", "usb_dpll_hs_clk_div"),
+ DT_CLK(NULL, "dpll_usb_ck", "dpll_usb_ck"),
+ DT_CLK(NULL, "dpll_usb_clkdcoldo", "dpll_usb_clkdcoldo"),
+ DT_CLK(NULL, "dpll_usb_m2_ck", "dpll_usb_m2_ck"),
+ DT_CLK(NULL, "dss_syc_gfclk_div", "dss_syc_gfclk_div"),
+ DT_CLK(NULL, "func_128m_clk", "func_128m_clk"),
+ DT_CLK(NULL, "func_12m_fclk", "func_12m_fclk"),
+ DT_CLK(NULL, "func_24m_clk", "func_24m_clk"),
+ DT_CLK(NULL, "func_48m_fclk", "func_48m_fclk"),
+ DT_CLK(NULL, "func_96m_fclk", "func_96m_fclk"),
+ DT_CLK(NULL, "l3_iclk_div", "l3_iclk_div"),
+ DT_CLK(NULL, "gpu_l3_iclk", "gpu_l3_iclk"),
+ DT_CLK(NULL, "l3init_60m_fclk", "l3init_60m_fclk"),
+ DT_CLK(NULL, "wkupaon_iclk_mux", "wkupaon_iclk_mux"),
+ DT_CLK(NULL, "l3instr_ts_gclk_div", "l3instr_ts_gclk_div"),
+ DT_CLK(NULL, "l4_root_clk_div", "l4_root_clk_div"),
+ DT_CLK(NULL, "dss_32khz_clk", "dss_32khz_clk"),
+ DT_CLK(NULL, "dss_48mhz_clk", "dss_48mhz_clk"),
+ DT_CLK(NULL, "dss_dss_clk", "dss_dss_clk"),
+ DT_CLK(NULL, "dss_sys_clk", "dss_sys_clk"),
+ DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
+ DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"),
+ DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"),
+ DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"),
+ DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"),
+ DT_CLK(NULL, "gpio6_dbclk", "gpio6_dbclk"),
+ DT_CLK(NULL, "gpio7_dbclk", "gpio7_dbclk"),
+ DT_CLK(NULL, "gpio8_dbclk", "gpio8_dbclk"),
+ DT_CLK(NULL, "iss_ctrlclk", "iss_ctrlclk"),
+ DT_CLK(NULL, "lli_txphy_clk", "lli_txphy_clk"),
+ DT_CLK(NULL, "lli_txphy_ls_clk", "lli_txphy_ls_clk"),
+ DT_CLK(NULL, "mmc1_32khz_clk", "mmc1_32khz_clk"),
+ DT_CLK(NULL, "sata_ref_clk", "sata_ref_clk"),
+ DT_CLK(NULL, "slimbus1_slimbus_clk", "slimbus1_slimbus_clk"),
+ DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "usb_host_hs_hsic480m_p1_clk"),
+ DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "usb_host_hs_hsic480m_p2_clk"),
+ DT_CLK(NULL, "usb_host_hs_hsic480m_p3_clk", "usb_host_hs_hsic480m_p3_clk"),
+ DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "usb_host_hs_hsic60m_p1_clk"),
+ DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "usb_host_hs_hsic60m_p2_clk"),
+ DT_CLK(NULL, "usb_host_hs_hsic60m_p3_clk", "usb_host_hs_hsic60m_p3_clk"),
+ DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "usb_host_hs_utmi_p1_clk"),
+ DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "usb_host_hs_utmi_p2_clk"),
+ DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "usb_host_hs_utmi_p3_clk"),
+ DT_CLK(NULL, "usb_otg_ss_refclk960m", "usb_otg_ss_refclk960m"),
+ DT_CLK(NULL, "usb_phy_cm_clk32k", "usb_phy_cm_clk32k"),
+ DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "usb_tll_hs_usb_ch0_clk"),
+ DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "usb_tll_hs_usb_ch1_clk"),
+ DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "usb_tll_hs_usb_ch2_clk"),
+ DT_CLK(NULL, "aess_fclk", "aess_fclk"),
+ DT_CLK(NULL, "dmic_sync_mux_ck", "dmic_sync_mux_ck"),
+ DT_CLK(NULL, "dmic_gfclk", "dmic_gfclk"),
+ DT_CLK(NULL, "fdif_fclk", "fdif_fclk"),
+ DT_CLK(NULL, "gpu_core_gclk_mux", "gpu_core_gclk_mux"),
+ DT_CLK(NULL, "gpu_hyd_gclk_mux", "gpu_hyd_gclk_mux"),
+ DT_CLK(NULL, "hsi_fclk", "hsi_fclk"),
+ DT_CLK(NULL, "mcasp_sync_mux_ck", "mcasp_sync_mux_ck"),
+ DT_CLK(NULL, "mcasp_gfclk", "mcasp_gfclk"),
+ DT_CLK(NULL, "mcbsp1_sync_mux_ck", "mcbsp1_sync_mux_ck"),
+ DT_CLK(NULL, "mcbsp1_gfclk", "mcbsp1_gfclk"),
+ DT_CLK(NULL, "mcbsp2_sync_mux_ck", "mcbsp2_sync_mux_ck"),
+ DT_CLK(NULL, "mcbsp2_gfclk", "mcbsp2_gfclk"),
+ DT_CLK(NULL, "mcbsp3_sync_mux_ck", "mcbsp3_sync_mux_ck"),
+ DT_CLK(NULL, "mcbsp3_gfclk", "mcbsp3_gfclk"),
+ DT_CLK(NULL, "mmc1_fclk_mux", "mmc1_fclk_mux"),
+ DT_CLK(NULL, "mmc1_fclk", "mmc1_fclk"),
+ DT_CLK(NULL, "mmc2_fclk_mux", "mmc2_fclk_mux"),
+ DT_CLK(NULL, "mmc2_fclk", "mmc2_fclk"),
+ DT_CLK(NULL, "timer10_gfclk_mux", "timer10_gfclk_mux"),
+ DT_CLK(NULL, "timer11_gfclk_mux", "timer11_gfclk_mux"),
+ DT_CLK(NULL, "timer1_gfclk_mux", "timer1_gfclk_mux"),
+ DT_CLK(NULL, "timer2_gfclk_mux", "timer2_gfclk_mux"),
+ DT_CLK(NULL, "timer3_gfclk_mux", "timer3_gfclk_mux"),
+ DT_CLK(NULL, "timer4_gfclk_mux", "timer4_gfclk_mux"),
+ DT_CLK(NULL, "timer5_gfclk_mux", "timer5_gfclk_mux"),
+ DT_CLK(NULL, "timer6_gfclk_mux", "timer6_gfclk_mux"),
+ DT_CLK(NULL, "timer7_gfclk_mux", "timer7_gfclk_mux"),
+ DT_CLK(NULL, "timer8_gfclk_mux", "timer8_gfclk_mux"),
+ DT_CLK(NULL, "timer9_gfclk_mux", "timer9_gfclk_mux"),
+ DT_CLK(NULL, "utmi_p1_gfclk", "utmi_p1_gfclk"),
+ DT_CLK(NULL, "utmi_p2_gfclk", "utmi_p2_gfclk"),
+ DT_CLK(NULL, "auxclk0_src_ck", "auxclk0_src_ck"),
+ DT_CLK(NULL, "auxclk0_ck", "auxclk0_ck"),
+ DT_CLK(NULL, "auxclkreq0_ck", "auxclkreq0_ck"),
+ DT_CLK(NULL, "auxclk1_src_ck", "auxclk1_src_ck"),
+ DT_CLK(NULL, "auxclk1_ck", "auxclk1_ck"),
+ DT_CLK(NULL, "auxclkreq1_ck", "auxclkreq1_ck"),
+ DT_CLK(NULL, "auxclk2_src_ck", "auxclk2_src_ck"),
+ DT_CLK(NULL, "auxclk2_ck", "auxclk2_ck"),
+ DT_CLK(NULL, "auxclkreq2_ck", "auxclkreq2_ck"),
+ DT_CLK(NULL, "auxclk3_src_ck", "auxclk3_src_ck"),
+ DT_CLK(NULL, "auxclk3_ck", "auxclk3_ck"),
+ DT_CLK(NULL, "auxclkreq3_ck", "auxclkreq3_ck"),
+ DT_CLK(NULL, "gpmc_ck", "dummy_ck"),
+ DT_CLK("omap_i2c.1", "ick", "dummy_ck"),
+ DT_CLK("omap_i2c.2", "ick", "dummy_ck"),
+ DT_CLK("omap_i2c.3", "ick", "dummy_ck"),
+ DT_CLK("omap_i2c.4", "ick", "dummy_ck"),
+ DT_CLK(NULL, "mailboxes_ick", "dummy_ck"),
+ DT_CLK("omap_hsmmc.0", "ick", "dummy_ck"),
+ DT_CLK("omap_hsmmc.1", "ick", "dummy_ck"),
+ DT_CLK("omap_hsmmc.2", "ick", "dummy_ck"),
+ DT_CLK("omap_hsmmc.3", "ick", "dummy_ck"),
+ DT_CLK("omap_hsmmc.4", "ick", "dummy_ck"),
+ DT_CLK("omap-mcbsp.1", "ick", "dummy_ck"),
+ DT_CLK("omap-mcbsp.2", "ick", "dummy_ck"),
+ DT_CLK("omap-mcbsp.3", "ick", "dummy_ck"),
+ DT_CLK("omap-mcbsp.4", "ick", "dummy_ck"),
+ DT_CLK("omap2_mcspi.1", "ick", "dummy_ck"),
+ DT_CLK("omap2_mcspi.2", "ick", "dummy_ck"),
+ DT_CLK("omap2_mcspi.3", "ick", "dummy_ck"),
+ DT_CLK("omap2_mcspi.4", "ick", "dummy_ck"),
+ DT_CLK(NULL, "uart1_ick", "dummy_ck"),
+ DT_CLK(NULL, "uart2_ick", "dummy_ck"),
+ DT_CLK(NULL, "uart3_ick", "dummy_ck"),
+ DT_CLK(NULL, "uart4_ick", "dummy_ck"),
+ DT_CLK("usbhs_omap", "usbhost_ick", "dummy_ck"),
+ DT_CLK("usbhs_omap", "usbtll_fck", "dummy_ck"),
+ DT_CLK("omap_wdt", "ick", "dummy_ck"),
+ DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
+ DT_CLK("omap_timer.1", "sys_ck", "sys_clkin"),
+ DT_CLK("omap_timer.2", "sys_ck", "sys_clkin"),
+ DT_CLK("omap_timer.3", "sys_ck", "sys_clkin"),
+ DT_CLK("omap_timer.4", "sys_ck", "sys_clkin"),
+ DT_CLK("omap_timer.9", "sys_ck", "sys_clkin"),
+ DT_CLK("omap_timer.10", "sys_ck", "sys_clkin"),
+ DT_CLK("omap_timer.11", "sys_ck", "sys_clkin"),
+ DT_CLK("omap_timer.5", "sys_ck", "dss_syc_gfclk_div"),
+ DT_CLK("omap_timer.6", "sys_ck", "dss_syc_gfclk_div"),
+ DT_CLK("omap_timer.7", "sys_ck", "dss_syc_gfclk_div"),
+ DT_CLK("omap_timer.8", "sys_ck", "dss_syc_gfclk_div"),
+ { .node_name = NULL },
+};
+
+int __init omap5xxx_clk_init(void)
+{
+ int rc;
+ struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck;
+
+ of_clk_init(NULL);
+
+ ti_dt_clocks_register(omap54xx_clks);
+
+ omap2_clk_disable_autoidle_all();
+
+ abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_clk_mux");
+ sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
+ rc = clk_set_parent(abe_dpll_ref, sys_32k_ck);
+ abe_dpll = clk_get_sys(NULL, "dpll_abe_ck");
+ if (!rc)
+ rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ);
+ if (rc)
+ pr_err("%s: failed to configure ABE DPLL!\n", __func__);
+
+ return 0;
+}
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index c9a18b9..9a29e17 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -220,6 +220,7 @@ void of_ti_autoidle_setup(struct device_node *node);
struct clk_div_table *ti_clk_get_div_table(struct device_node *node);
int omap4xxx_clk_init(void);
+int omap5xxx_clk_init(void);
#ifdef CONFIG_OF
void of_ti_clk_allow_autoidle_all(void);
--
1.7.9.5
--
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^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 14/36] CLK: TI: add omap5 clock init file
@ 2013-09-25 8:48 ` Tero Kristo
0 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-arm-kernel
clk-54xx.c now contains the clock init functionality for omap5, including
DT clock registration and adding of static clkdev entries.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/mach-omap2/io.c | 1 +
drivers/clk/ti/Makefile | 1 +
drivers/clk/ti/clk-54xx.c | 241 +++++++++++++++++++++++++++++++++++++++++++++
include/linux/clk/ti.h | 1 +
4 files changed, 244 insertions(+)
create mode 100644 drivers/clk/ti/clk-54xx.c
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index ff2113c..205bb1d 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -650,6 +650,7 @@ void __init omap5_init_early(void)
omap54xx_clockdomains_init();
omap54xx_hwmod_init();
omap_hwmod_init_postsetup();
+ omap_clk_init = omap5xxx_clk_init;
}
#endif
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 1ed6dd7..9d785e5 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -3,4 +3,5 @@ obj-y += clk.o dpll.o autoidle.o divider.o \
fixed-factor.o gate.o clockdomain.o \
mux-gate.o mux.o
obj-$(CONFIG_ARCH_OMAP4) += clk-44xx.o
+obj-$(CONFIG_SOC_OMAP5) += clk-54xx.o
endif
diff --git a/drivers/clk/ti/clk-54xx.c b/drivers/clk/ti/clk-54xx.c
new file mode 100644
index 0000000..efa81ab
--- /dev/null
+++ b/drivers/clk/ti/clk-54xx.c
@@ -0,0 +1,241 @@
+/*
+ * OMAP5 Clock init
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo (t-kristo at ti.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/clk-private.h>
+#include <linux/clkdev.h>
+#include <linux/io.h>
+#include <linux/clk/ti.h>
+
+#define OMAP5_DPLL_ABE_DEFFREQ 98304000
+
+static struct ti_dt_clk omap54xx_clks[] = {
+ DT_CLK(NULL, "pad_clks_src_ck", "pad_clks_src_ck"),
+ DT_CLK(NULL, "pad_clks_ck", "pad_clks_ck"),
+ DT_CLK(NULL, "secure_32k_clk_src_ck", "secure_32k_clk_src_ck"),
+ DT_CLK(NULL, "slimbus_src_clk", "slimbus_src_clk"),
+ DT_CLK(NULL, "slimbus_clk", "slimbus_clk"),
+ DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"),
+ DT_CLK(NULL, "virt_12000000_ck", "virt_12000000_ck"),
+ DT_CLK(NULL, "virt_13000000_ck", "virt_13000000_ck"),
+ DT_CLK(NULL, "virt_16800000_ck", "virt_16800000_ck"),
+ DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
+ DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
+ DT_CLK(NULL, "virt_27000000_ck", "virt_27000000_ck"),
+ DT_CLK(NULL, "virt_38400000_ck", "virt_38400000_ck"),
+ DT_CLK(NULL, "sys_clkin", "sys_clkin"),
+ DT_CLK(NULL, "xclk60mhsp1_ck", "xclk60mhsp1_ck"),
+ DT_CLK(NULL, "xclk60mhsp2_ck", "xclk60mhsp2_ck"),
+ DT_CLK(NULL, "abe_dpll_bypass_clk_mux", "abe_dpll_bypass_clk_mux"),
+ DT_CLK(NULL, "abe_dpll_clk_mux", "abe_dpll_clk_mux"),
+ DT_CLK(NULL, "dpll_abe_ck", "dpll_abe_ck"),
+ DT_CLK(NULL, "dpll_abe_x2_ck", "dpll_abe_x2_ck"),
+ DT_CLK(NULL, "dpll_abe_m2x2_ck", "dpll_abe_m2x2_ck"),
+ DT_CLK(NULL, "abe_24m_fclk", "abe_24m_fclk"),
+ DT_CLK(NULL, "abe_clk", "abe_clk"),
+ DT_CLK(NULL, "abe_iclk", "abe_iclk"),
+ DT_CLK(NULL, "abe_lp_clk_div", "abe_lp_clk_div"),
+ DT_CLK(NULL, "dpll_abe_m3x2_ck", "dpll_abe_m3x2_ck"),
+ DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
+ DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
+ DT_CLK(NULL, "dpll_core_h21x2_ck", "dpll_core_h21x2_ck"),
+ DT_CLK(NULL, "c2c_fclk", "c2c_fclk"),
+ DT_CLK(NULL, "c2c_iclk", "c2c_iclk"),
+ DT_CLK(NULL, "custefuse_sys_gfclk_div", "custefuse_sys_gfclk_div"),
+ DT_CLK(NULL, "dpll_core_h11x2_ck", "dpll_core_h11x2_ck"),
+ DT_CLK(NULL, "dpll_core_h12x2_ck", "dpll_core_h12x2_ck"),
+ DT_CLK(NULL, "dpll_core_h13x2_ck", "dpll_core_h13x2_ck"),
+ DT_CLK(NULL, "dpll_core_h14x2_ck", "dpll_core_h14x2_ck"),
+ DT_CLK(NULL, "dpll_core_h22x2_ck", "dpll_core_h22x2_ck"),
+ DT_CLK(NULL, "dpll_core_h23x2_ck", "dpll_core_h23x2_ck"),
+ DT_CLK(NULL, "dpll_core_h24x2_ck", "dpll_core_h24x2_ck"),
+ DT_CLK(NULL, "dpll_core_m2_ck", "dpll_core_m2_ck"),
+ DT_CLK(NULL, "dpll_core_m3x2_ck", "dpll_core_m3x2_ck"),
+ DT_CLK(NULL, "iva_dpll_hs_clk_div", "iva_dpll_hs_clk_div"),
+ DT_CLK(NULL, "dpll_iva_ck", "dpll_iva_ck"),
+ DT_CLK(NULL, "dpll_iva_x2_ck", "dpll_iva_x2_ck"),
+ DT_CLK(NULL, "dpll_iva_h11x2_ck", "dpll_iva_h11x2_ck"),
+ DT_CLK(NULL, "dpll_iva_h12x2_ck", "dpll_iva_h12x2_ck"),
+ DT_CLK(NULL, "mpu_dpll_hs_clk_div", "mpu_dpll_hs_clk_div"),
+ DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"),
+ DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"),
+ DT_CLK(NULL, "per_dpll_hs_clk_div", "per_dpll_hs_clk_div"),
+ DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"),
+ DT_CLK(NULL, "dpll_per_x2_ck", "dpll_per_x2_ck"),
+ DT_CLK(NULL, "dpll_per_h11x2_ck", "dpll_per_h11x2_ck"),
+ DT_CLK(NULL, "dpll_per_h12x2_ck", "dpll_per_h12x2_ck"),
+ DT_CLK(NULL, "dpll_per_h14x2_ck", "dpll_per_h14x2_ck"),
+ DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"),
+ DT_CLK(NULL, "dpll_per_m2x2_ck", "dpll_per_m2x2_ck"),
+ DT_CLK(NULL, "dpll_per_m3x2_ck", "dpll_per_m3x2_ck"),
+ DT_CLK(NULL, "dpll_unipro1_ck", "dpll_unipro1_ck"),
+ DT_CLK(NULL, "dpll_unipro1_clkdcoldo", "dpll_unipro1_clkdcoldo"),
+ DT_CLK(NULL, "dpll_unipro1_m2_ck", "dpll_unipro1_m2_ck"),
+ DT_CLK(NULL, "dpll_unipro2_ck", "dpll_unipro2_ck"),
+ DT_CLK(NULL, "dpll_unipro2_clkdcoldo", "dpll_unipro2_clkdcoldo"),
+ DT_CLK(NULL, "dpll_unipro2_m2_ck", "dpll_unipro2_m2_ck"),
+ DT_CLK(NULL, "usb_dpll_hs_clk_div", "usb_dpll_hs_clk_div"),
+ DT_CLK(NULL, "dpll_usb_ck", "dpll_usb_ck"),
+ DT_CLK(NULL, "dpll_usb_clkdcoldo", "dpll_usb_clkdcoldo"),
+ DT_CLK(NULL, "dpll_usb_m2_ck", "dpll_usb_m2_ck"),
+ DT_CLK(NULL, "dss_syc_gfclk_div", "dss_syc_gfclk_div"),
+ DT_CLK(NULL, "func_128m_clk", "func_128m_clk"),
+ DT_CLK(NULL, "func_12m_fclk", "func_12m_fclk"),
+ DT_CLK(NULL, "func_24m_clk", "func_24m_clk"),
+ DT_CLK(NULL, "func_48m_fclk", "func_48m_fclk"),
+ DT_CLK(NULL, "func_96m_fclk", "func_96m_fclk"),
+ DT_CLK(NULL, "l3_iclk_div", "l3_iclk_div"),
+ DT_CLK(NULL, "gpu_l3_iclk", "gpu_l3_iclk"),
+ DT_CLK(NULL, "l3init_60m_fclk", "l3init_60m_fclk"),
+ DT_CLK(NULL, "wkupaon_iclk_mux", "wkupaon_iclk_mux"),
+ DT_CLK(NULL, "l3instr_ts_gclk_div", "l3instr_ts_gclk_div"),
+ DT_CLK(NULL, "l4_root_clk_div", "l4_root_clk_div"),
+ DT_CLK(NULL, "dss_32khz_clk", "dss_32khz_clk"),
+ DT_CLK(NULL, "dss_48mhz_clk", "dss_48mhz_clk"),
+ DT_CLK(NULL, "dss_dss_clk", "dss_dss_clk"),
+ DT_CLK(NULL, "dss_sys_clk", "dss_sys_clk"),
+ DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
+ DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"),
+ DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"),
+ DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"),
+ DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"),
+ DT_CLK(NULL, "gpio6_dbclk", "gpio6_dbclk"),
+ DT_CLK(NULL, "gpio7_dbclk", "gpio7_dbclk"),
+ DT_CLK(NULL, "gpio8_dbclk", "gpio8_dbclk"),
+ DT_CLK(NULL, "iss_ctrlclk", "iss_ctrlclk"),
+ DT_CLK(NULL, "lli_txphy_clk", "lli_txphy_clk"),
+ DT_CLK(NULL, "lli_txphy_ls_clk", "lli_txphy_ls_clk"),
+ DT_CLK(NULL, "mmc1_32khz_clk", "mmc1_32khz_clk"),
+ DT_CLK(NULL, "sata_ref_clk", "sata_ref_clk"),
+ DT_CLK(NULL, "slimbus1_slimbus_clk", "slimbus1_slimbus_clk"),
+ DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "usb_host_hs_hsic480m_p1_clk"),
+ DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "usb_host_hs_hsic480m_p2_clk"),
+ DT_CLK(NULL, "usb_host_hs_hsic480m_p3_clk", "usb_host_hs_hsic480m_p3_clk"),
+ DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "usb_host_hs_hsic60m_p1_clk"),
+ DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "usb_host_hs_hsic60m_p2_clk"),
+ DT_CLK(NULL, "usb_host_hs_hsic60m_p3_clk", "usb_host_hs_hsic60m_p3_clk"),
+ DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "usb_host_hs_utmi_p1_clk"),
+ DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "usb_host_hs_utmi_p2_clk"),
+ DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "usb_host_hs_utmi_p3_clk"),
+ DT_CLK(NULL, "usb_otg_ss_refclk960m", "usb_otg_ss_refclk960m"),
+ DT_CLK(NULL, "usb_phy_cm_clk32k", "usb_phy_cm_clk32k"),
+ DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "usb_tll_hs_usb_ch0_clk"),
+ DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "usb_tll_hs_usb_ch1_clk"),
+ DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "usb_tll_hs_usb_ch2_clk"),
+ DT_CLK(NULL, "aess_fclk", "aess_fclk"),
+ DT_CLK(NULL, "dmic_sync_mux_ck", "dmic_sync_mux_ck"),
+ DT_CLK(NULL, "dmic_gfclk", "dmic_gfclk"),
+ DT_CLK(NULL, "fdif_fclk", "fdif_fclk"),
+ DT_CLK(NULL, "gpu_core_gclk_mux", "gpu_core_gclk_mux"),
+ DT_CLK(NULL, "gpu_hyd_gclk_mux", "gpu_hyd_gclk_mux"),
+ DT_CLK(NULL, "hsi_fclk", "hsi_fclk"),
+ DT_CLK(NULL, "mcasp_sync_mux_ck", "mcasp_sync_mux_ck"),
+ DT_CLK(NULL, "mcasp_gfclk", "mcasp_gfclk"),
+ DT_CLK(NULL, "mcbsp1_sync_mux_ck", "mcbsp1_sync_mux_ck"),
+ DT_CLK(NULL, "mcbsp1_gfclk", "mcbsp1_gfclk"),
+ DT_CLK(NULL, "mcbsp2_sync_mux_ck", "mcbsp2_sync_mux_ck"),
+ DT_CLK(NULL, "mcbsp2_gfclk", "mcbsp2_gfclk"),
+ DT_CLK(NULL, "mcbsp3_sync_mux_ck", "mcbsp3_sync_mux_ck"),
+ DT_CLK(NULL, "mcbsp3_gfclk", "mcbsp3_gfclk"),
+ DT_CLK(NULL, "mmc1_fclk_mux", "mmc1_fclk_mux"),
+ DT_CLK(NULL, "mmc1_fclk", "mmc1_fclk"),
+ DT_CLK(NULL, "mmc2_fclk_mux", "mmc2_fclk_mux"),
+ DT_CLK(NULL, "mmc2_fclk", "mmc2_fclk"),
+ DT_CLK(NULL, "timer10_gfclk_mux", "timer10_gfclk_mux"),
+ DT_CLK(NULL, "timer11_gfclk_mux", "timer11_gfclk_mux"),
+ DT_CLK(NULL, "timer1_gfclk_mux", "timer1_gfclk_mux"),
+ DT_CLK(NULL, "timer2_gfclk_mux", "timer2_gfclk_mux"),
+ DT_CLK(NULL, "timer3_gfclk_mux", "timer3_gfclk_mux"),
+ DT_CLK(NULL, "timer4_gfclk_mux", "timer4_gfclk_mux"),
+ DT_CLK(NULL, "timer5_gfclk_mux", "timer5_gfclk_mux"),
+ DT_CLK(NULL, "timer6_gfclk_mux", "timer6_gfclk_mux"),
+ DT_CLK(NULL, "timer7_gfclk_mux", "timer7_gfclk_mux"),
+ DT_CLK(NULL, "timer8_gfclk_mux", "timer8_gfclk_mux"),
+ DT_CLK(NULL, "timer9_gfclk_mux", "timer9_gfclk_mux"),
+ DT_CLK(NULL, "utmi_p1_gfclk", "utmi_p1_gfclk"),
+ DT_CLK(NULL, "utmi_p2_gfclk", "utmi_p2_gfclk"),
+ DT_CLK(NULL, "auxclk0_src_ck", "auxclk0_src_ck"),
+ DT_CLK(NULL, "auxclk0_ck", "auxclk0_ck"),
+ DT_CLK(NULL, "auxclkreq0_ck", "auxclkreq0_ck"),
+ DT_CLK(NULL, "auxclk1_src_ck", "auxclk1_src_ck"),
+ DT_CLK(NULL, "auxclk1_ck", "auxclk1_ck"),
+ DT_CLK(NULL, "auxclkreq1_ck", "auxclkreq1_ck"),
+ DT_CLK(NULL, "auxclk2_src_ck", "auxclk2_src_ck"),
+ DT_CLK(NULL, "auxclk2_ck", "auxclk2_ck"),
+ DT_CLK(NULL, "auxclkreq2_ck", "auxclkreq2_ck"),
+ DT_CLK(NULL, "auxclk3_src_ck", "auxclk3_src_ck"),
+ DT_CLK(NULL, "auxclk3_ck", "auxclk3_ck"),
+ DT_CLK(NULL, "auxclkreq3_ck", "auxclkreq3_ck"),
+ DT_CLK(NULL, "gpmc_ck", "dummy_ck"),
+ DT_CLK("omap_i2c.1", "ick", "dummy_ck"),
+ DT_CLK("omap_i2c.2", "ick", "dummy_ck"),
+ DT_CLK("omap_i2c.3", "ick", "dummy_ck"),
+ DT_CLK("omap_i2c.4", "ick", "dummy_ck"),
+ DT_CLK(NULL, "mailboxes_ick", "dummy_ck"),
+ DT_CLK("omap_hsmmc.0", "ick", "dummy_ck"),
+ DT_CLK("omap_hsmmc.1", "ick", "dummy_ck"),
+ DT_CLK("omap_hsmmc.2", "ick", "dummy_ck"),
+ DT_CLK("omap_hsmmc.3", "ick", "dummy_ck"),
+ DT_CLK("omap_hsmmc.4", "ick", "dummy_ck"),
+ DT_CLK("omap-mcbsp.1", "ick", "dummy_ck"),
+ DT_CLK("omap-mcbsp.2", "ick", "dummy_ck"),
+ DT_CLK("omap-mcbsp.3", "ick", "dummy_ck"),
+ DT_CLK("omap-mcbsp.4", "ick", "dummy_ck"),
+ DT_CLK("omap2_mcspi.1", "ick", "dummy_ck"),
+ DT_CLK("omap2_mcspi.2", "ick", "dummy_ck"),
+ DT_CLK("omap2_mcspi.3", "ick", "dummy_ck"),
+ DT_CLK("omap2_mcspi.4", "ick", "dummy_ck"),
+ DT_CLK(NULL, "uart1_ick", "dummy_ck"),
+ DT_CLK(NULL, "uart2_ick", "dummy_ck"),
+ DT_CLK(NULL, "uart3_ick", "dummy_ck"),
+ DT_CLK(NULL, "uart4_ick", "dummy_ck"),
+ DT_CLK("usbhs_omap", "usbhost_ick", "dummy_ck"),
+ DT_CLK("usbhs_omap", "usbtll_fck", "dummy_ck"),
+ DT_CLK("omap_wdt", "ick", "dummy_ck"),
+ DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
+ DT_CLK("omap_timer.1", "sys_ck", "sys_clkin"),
+ DT_CLK("omap_timer.2", "sys_ck", "sys_clkin"),
+ DT_CLK("omap_timer.3", "sys_ck", "sys_clkin"),
+ DT_CLK("omap_timer.4", "sys_ck", "sys_clkin"),
+ DT_CLK("omap_timer.9", "sys_ck", "sys_clkin"),
+ DT_CLK("omap_timer.10", "sys_ck", "sys_clkin"),
+ DT_CLK("omap_timer.11", "sys_ck", "sys_clkin"),
+ DT_CLK("omap_timer.5", "sys_ck", "dss_syc_gfclk_div"),
+ DT_CLK("omap_timer.6", "sys_ck", "dss_syc_gfclk_div"),
+ DT_CLK("omap_timer.7", "sys_ck", "dss_syc_gfclk_div"),
+ DT_CLK("omap_timer.8", "sys_ck", "dss_syc_gfclk_div"),
+ { .node_name = NULL },
+};
+
+int __init omap5xxx_clk_init(void)
+{
+ int rc;
+ struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck;
+
+ of_clk_init(NULL);
+
+ ti_dt_clocks_register(omap54xx_clks);
+
+ omap2_clk_disable_autoidle_all();
+
+ abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_clk_mux");
+ sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
+ rc = clk_set_parent(abe_dpll_ref, sys_32k_ck);
+ abe_dpll = clk_get_sys(NULL, "dpll_abe_ck");
+ if (!rc)
+ rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ);
+ if (rc)
+ pr_err("%s: failed to configure ABE DPLL!\n", __func__);
+
+ return 0;
+}
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index c9a18b9..9a29e17 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -220,6 +220,7 @@ void of_ti_autoidle_setup(struct device_node *node);
struct clk_div_table *ti_clk_get_div_table(struct device_node *node);
int omap4xxx_clk_init(void);
+int omap5xxx_clk_init(void);
#ifdef CONFIG_OF
void of_ti_clk_allow_autoidle_all(void);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 15/36] CLK: TI: omap5: Initialize USB_DPLL at boot
2013-09-25 8:48 ` Tero Kristo
@ 2013-09-25 8:48 ` Tero Kristo
-1 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-omap, paul, tony, nm, rnayak, bcousson, mturquette
Cc: linux-arm-kernel, devicetree, Roger Quadros
From: Roger Quadros <rogerq@ti.com>
USB_DPLL must be initialized and locked at boot so that
USB modules can work.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
drivers/clk/ti/clk-54xx.c | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/ti/clk-54xx.c b/drivers/clk/ti/clk-54xx.c
index efa81ab..e39e03d 100644
--- a/drivers/clk/ti/clk-54xx.c
+++ b/drivers/clk/ti/clk-54xx.c
@@ -19,6 +19,12 @@
#define OMAP5_DPLL_ABE_DEFFREQ 98304000
+/*
+ * OMAP543x TRM, section "3.6.3.9.5 DPLL_USB Preferred Settings"
+ * states it must be at 960MHz
+ */
+#define OMAP5_DPLL_USB_DEFFREQ 960000000
+
static struct ti_dt_clk omap54xx_clks[] = {
DT_CLK(NULL, "pad_clks_src_ck", "pad_clks_src_ck"),
DT_CLK(NULL, "pad_clks_ck", "pad_clks_ck"),
@@ -220,7 +226,7 @@ static struct ti_dt_clk omap54xx_clks[] = {
int __init omap5xxx_clk_init(void)
{
int rc;
- struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck;
+ struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll;
of_clk_init(NULL);
@@ -237,5 +243,15 @@ int __init omap5xxx_clk_init(void)
if (rc)
pr_err("%s: failed to configure ABE DPLL!\n", __func__);
+ usb_dpll = clk_get_sys(NULL, "dpll_usb_ck");
+ rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ);
+ if (rc)
+ pr_err("%s: failed to configure USB DPLL!\n", __func__);
+
+ usb_dpll = clk_get_sys(NULL, "dpll_usb_m2_ck");
+ rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ/2);
+ if (rc)
+ pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__);
+
return 0;
}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 15/36] CLK: TI: omap5: Initialize USB_DPLL at boot
@ 2013-09-25 8:48 ` Tero Kristo
0 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-arm-kernel
From: Roger Quadros <rogerq@ti.com>
USB_DPLL must be initialized and locked at boot so that
USB modules can work.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
drivers/clk/ti/clk-54xx.c | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/ti/clk-54xx.c b/drivers/clk/ti/clk-54xx.c
index efa81ab..e39e03d 100644
--- a/drivers/clk/ti/clk-54xx.c
+++ b/drivers/clk/ti/clk-54xx.c
@@ -19,6 +19,12 @@
#define OMAP5_DPLL_ABE_DEFFREQ 98304000
+/*
+ * OMAP543x TRM, section "3.6.3.9.5 DPLL_USB Preferred Settings"
+ * states it must be at 960MHz
+ */
+#define OMAP5_DPLL_USB_DEFFREQ 960000000
+
static struct ti_dt_clk omap54xx_clks[] = {
DT_CLK(NULL, "pad_clks_src_ck", "pad_clks_src_ck"),
DT_CLK(NULL, "pad_clks_ck", "pad_clks_ck"),
@@ -220,7 +226,7 @@ static struct ti_dt_clk omap54xx_clks[] = {
int __init omap5xxx_clk_init(void)
{
int rc;
- struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck;
+ struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll;
of_clk_init(NULL);
@@ -237,5 +243,15 @@ int __init omap5xxx_clk_init(void)
if (rc)
pr_err("%s: failed to configure ABE DPLL!\n", __func__);
+ usb_dpll = clk_get_sys(NULL, "dpll_usb_ck");
+ rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ);
+ if (rc)
+ pr_err("%s: failed to configure USB DPLL!\n", __func__);
+
+ usb_dpll = clk_get_sys(NULL, "dpll_usb_m2_ck");
+ rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ/2);
+ if (rc)
+ pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__);
+
return 0;
}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 16/36] ARM: dts: dra7 clock data
2013-09-25 8:48 ` Tero Kristo
@ 2013-09-25 8:48 ` Tero Kristo
-1 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-omap-u79uwXL29TY76Z2rM5mHXA, paul-DWxLp4Yu+b8AvxtiuMwx3w,
tony-4v6yS6AI5VpBDgjK7y7TUQ, nm-l0cyMroinI0, rnayak-l0cyMroinI0,
bcousson-rdvid1DuHRBWk0Htik3J/w,
mturquette-QSEj5FYQhm4dnm+yROfE0A
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
This patch creates a unique node for each clock in the DRA7 power,
reset and clock manager (PRCM).
TODO: apll_pcie clock node is still a dummy in this version, and
proper support for the APLL should be added.
Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
arch/arm/boot/dts/dra7xx-clocks.dtsi | 1975 ++++++++++++++++++++++++++++++++++
1 file changed, 1975 insertions(+)
create mode 100644 arch/arm/boot/dts/dra7xx-clocks.dtsi
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
new file mode 100644
index 0000000..0d83f95
--- /dev/null
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -0,0 +1,1975 @@
+/*
+ * Device Tree Source for DRA7xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+atl_clkin0_ck: atl_clkin0_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+atl_clkin1_ck: atl_clkin1_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+atl_clkin2_ck: atl_clkin2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+atlclkin3_ck: atlclkin3_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+hdmi_clkin_ck: hdmi_clkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+mlb_clkin_ck: mlb_clkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+mlbp_clkin_ck: mlbp_clkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+pciesref_acs_clk_ck: pciesref_acs_clk_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+};
+
+ref_clkin0_ck: ref_clkin0_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+ref_clkin1_ck: ref_clkin1_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+ref_clkin2_ck: ref_clkin2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+ref_clkin3_ck: ref_clkin3_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+rmii_clk_ck: rmii_clk_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+sdvenc_clkin_ck: sdvenc_clkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+secure_32k_clk_src_ck: secure_32k_clk_src_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+};
+
+sys_32k_ck: sys_32k_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+};
+
+virt_12000000_ck: virt_12000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+};
+
+virt_13000000_ck: virt_13000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <13000000>;
+};
+
+virt_16800000_ck: virt_16800000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <16800000>;
+};
+
+virt_19200000_ck: virt_19200000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <19200000>;
+};
+
+virt_20000000_ck: virt_20000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <20000000>;
+};
+
+virt_26000000_ck: virt_26000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <26000000>;
+};
+
+virt_27000000_ck: virt_27000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <27000000>;
+};
+
+virt_38400000_ck: virt_38400000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <38400000>;
+};
+
+sys_clkin1: sys_clkin1@4ae06110 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
+ reg = <0x4ae06110 0x4>;
+ ti,index-starts-at-one;
+};
+
+sys_clkin2: sys_clkin2 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <22579200>;
+};
+
+usb_otg_clkin_ck: usb_otg_clkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+video1_clkin_ck: video1_clkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+video1_m2_clkin_ck: video1_m2_clkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+video2_clkin_ck: video2_clkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+video2_m2_clkin_ck: video2_m2_clkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux@4ae06118 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin1>, <&sys_clkin2>;
+ reg = <0x4ae06118 0x4>;
+};
+
+abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@4ae06114 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
+ reg = <0x4ae06114 0x4>;
+};
+
+abe_dpll_clk_mux: abe_dpll_clk_mux@4ae0610c {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
+ reg = <0x4ae0610c 0x4>;
+};
+
+dpll_abe_ck: dpll_abe_ck@4a0051e0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-m4xen-clock";
+ clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
+ reg = <0x4a0051e0 0x4>, <0x4a0051e4 0x4>, <0x4a0051e8 0x4>, <0x4a0051ec 0x4>;
+};
+
+dpll_abe_x2_ck: dpll_abe_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_abe_ck>;
+};
+
+dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@4a0051f0 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0051f0 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+abe_24m_fclk: abe_24m_fclk@4ae0611c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_m2x2_ck>;
+ reg = <0x4ae0611c 0x4>;
+ ti,dividers = <8>, <16>;
+};
+
+abe_clk: abe_clk@4a005108 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_m2x2_ck>;
+ reg = <0x4a005108 0x4>;
+ ti,max-div = <4>;
+ ti,index-power-of-two;
+};
+
+aess_fclk: aess_fclk@4ae06178 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&abe_clk>;
+ reg = <0x4ae06178 0x4>;
+ ti,max-div = <2>;
+};
+
+abe_giclk_div: abe_giclk_div@4ae06174 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&aess_fclk>;
+ reg = <0x4ae06174 0x4>;
+ ti,max-div = <2>;
+};
+
+abe_lp_clk_div: abe_lp_clk_div@4ae061d8 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_m2x2_ck>;
+ reg = <0x4ae061d8 0x4>;
+ ti,dividers = <16>, <32>;
+};
+
+abe_sys_clk_div: abe_sys_clk_div@4ae06120 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&sys_clkin1>;
+ reg = <0x4ae06120 0x4>;
+ ti,max-div = <2>;
+};
+
+adc_gfclk_mux: adc_gfclk_mux@4ae061dc {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>;
+ reg = <0x4ae061dc 0x4>;
+};
+
+dpll_pcie_ref_ck: dpll_pcie_ref_ck@4a008200 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin1>, <&sys_clkin1>;
+ reg = <0x4a008200 0x4>, <0x4a008204 0x4>, <0x4a008208 0x4>, <0x4a00820c 0x4>;
+};
+
+dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck@4a008210 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_pcie_ref_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008210 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+apll_pcie_ck: apll_pcie_ck@4a008200 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&dpll_pcie_ref_ck>, <&dpll_pcie_ref_ck>;
+ reg = <0x4a008200 0x4>, <0x4a008204 0x4>, <0x4a008208 0x4>, <0x4a00820c 0x4>;
+};
+
+apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&apll_pcie_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&apll_pcie_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+apll_pcie_m2_ck: apll_pcie_m2_ck@4a008224 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&apll_pcie_ck>;
+ ti,max-div = <127>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008224 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+sys_clk1_dclk_div: sys_clk1_dclk_div@4ae061c8 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&sys_clkin1>;
+ reg = <0x4ae061c8 0x4>;
+ ti,max-div = <64>;
+ ti,index-power-of-two;
+};
+
+sys_clk2_dclk_div: sys_clk2_dclk_div@4ae061cc {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&sys_clkin2>;
+ reg = <0x4ae061cc 0x4>;
+ ti,max-div = <64>;
+ ti,index-power-of-two;
+};
+
+dpll_abe_m2_ck: dpll_abe_m2_ck@4a0051f0 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0051f0 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+per_abe_x1_dclk_div: per_abe_x1_dclk_div@4ae061bc {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_m2_ck>;
+ reg = <0x4ae061bc 0x4>;
+ ti,max-div = <64>;
+ ti,index-power-of-two;
+};
+
+dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@4a0051f4 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0051f4 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_core_ck: dpll_core_ck@4a005120 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-core-clock";
+ clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+ reg = <0x4a005120 0x4>, <0x4a005124 0x4>, <0x4a005128 0x4>, <0x4a00512c 0x4>;
+};
+
+dpll_core_x2_ck: dpll_core_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_core_ck>;
+};
+
+dpll_core_h12x2_ck: dpll_core_h12x2_ck@4a00513c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a00513c 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_h12x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dpll_mpu_ck: dpll_mpu_ck@4a005160 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>;
+ reg = <0x4a005160 0x4>, <0x4a005164 0x4>, <0x4a005168 0x4>, <0x4a00516c 0x4>;
+};
+
+dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a005170 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_mpu_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a005170 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+mpu_dclk_div: mpu_dclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_mpu_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dsp_dpll_hs_clk_div: dsp_dpll_hs_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_h12x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dpll_dsp_ck: dpll_dsp_ck@4a005234 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
+ reg = <0x4a005234 0x4>, <0x4a005238 0x4>, <0x4a00523c 0x4>, <0x4a005240 0x4>;
+};
+
+dpll_dsp_m2_ck: dpll_dsp_m2_ck@4a005244 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_dsp_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a005244 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dsp_gclk_div: dsp_gclk_div@4ae0618c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_dsp_m2_ck>;
+ reg = <0x4ae0618c 0x4>;
+ ti,max-div = <64>;
+ ti,index-power-of-two;
+};
+
+iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_h12x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dpll_iva_ck: dpll_iva_ck@4a0051a0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
+ reg = <0x4a0051a0 0x4>, <0x4a0051a4 0x4>, <0x4a0051a8 0x4>, <0x4a0051ac 0x4>;
+};
+
+dpll_iva_m2_ck: dpll_iva_m2_ck@4a0051b0 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_iva_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0051b0 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+iva_dclk: iva_dclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_iva_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dpll_gpu_ck: dpll_gpu_ck@4a0052d8 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+ reg = <0x4a0052d8 0x4>, <0x4a0052dc 0x4>, <0x4a0052e0 0x4>, <0x4a0052e4 0x4>;
+};
+
+dpll_gpu_m2_ck: dpll_gpu_m2_ck@4a0052e8 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_gpu_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0052e8 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+gpu_dclk: gpu_dclk@4ae061a0 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_gpu_m2_ck>;
+ reg = <0x4ae061a0 0x4>;
+ ti,max-div = <64>;
+ ti,index-power-of-two;
+};
+
+dpll_core_m2_ck: dpll_core_m2_ck@4a005130 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a005130 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+core_dpll_out_dclk_div: core_dpll_out_dclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dpll_ddr_ck: dpll_ddr_ck@4a005210 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+ reg = <0x4a005210 0x4>, <0x4a005214 0x4>, <0x4a005218 0x4>, <0x4a00521c 0x4>;
+};
+
+dpll_ddr_m2_ck: dpll_ddr_m2_ck@4a005220 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_ddr_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a005220 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+emif_phy_dclk_div: emif_phy_dclk_div@4ae06190 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_ddr_m2_ck>;
+ reg = <0x4ae06190 0x4>;
+ ti,max-div = <64>;
+ ti,index-power-of-two;
+};
+
+dpll_gmac_ck: dpll_gmac_ck@4a0052a8 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+ reg = <0x4a0052a8 0x4>, <0x4a0052ac 0x4>, <0x4a0052b0 0x4>, <0x4a0052b4 0x4>;
+};
+
+dpll_gmac_m2_ck: dpll_gmac_m2_ck@4a0052b8 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_gmac_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0052b8 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+gmac_250m_dclk_div: gmac_250m_dclk_div@4ae0619c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_gmac_m2_ck>;
+ reg = <0x4ae0619c 0x4>;
+ ti,max-div = <64>;
+ ti,index-power-of-two;
+};
+
+video2_dclk_div: video2_dclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&video2_m2_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+video1_dclk_div: video1_dclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&video1_m2_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+hdmi_dclk_div: hdmi_dclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&hdmi_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+per_dpll_hs_clk_div: per_dpll_hs_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_abe_m3x2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+dpll_per_ck: dpll_per_ck@4a008140 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
+ reg = <0x4a008140 0x4>, <0x4a008144 0x4>, <0x4a008148 0x4>, <0x4a00814c 0x4>;
+};
+
+dpll_per_m2_ck: dpll_per_m2_ck@4a008150 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008150 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+func_96m_aon_dclk_div: func_96m_aon_dclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_abe_m3x2_ck>;
+ clock-mult = <1>;
+ clock-div = <3>;
+};
+
+dpll_usb_ck: dpll_usb_ck@4a008180 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-j-type-clock";
+ clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
+ reg = <0x4a008180 0x4>, <0x4a008184 0x4>, <0x4a008188 0x4>, <0x4a00818c 0x4>;
+};
+
+dpll_usb_m2_ck: dpll_usb_m2_ck@4a008190 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_usb_ck>;
+ ti,max-div = <127>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008190 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+l3init_480m_dclk_div: l3init_480m_dclk_div@4ae061ac {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_usb_m2_ck>;
+ reg = <0x4ae061ac 0x4>;
+ ti,max-div = <64>;
+ ti,index-power-of-two;
+};
+
+usb_otg_dclk_div: usb_otg_dclk_div@4ae06184 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&usb_otg_clkin_ck>;
+ reg = <0x4ae06184 0x4>;
+ ti,max-div = <64>;
+ ti,index-power-of-two;
+};
+
+sata_dclk_div: sata_dclk_div@4ae061c0 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&sys_clkin1>;
+ reg = <0x4ae061c0 0x4>;
+ ti,max-div = <64>;
+ ti,index-power-of-two;
+};
+
+dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck@4a008210 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_pcie_ref_ck>;
+ ti,max-div = <127>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008210 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+pcie2_dclk_div: pcie2_dclk_div@4ae061b8 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_pcie_ref_m2_ck>;
+ reg = <0x4ae061b8 0x4>;
+ ti,max-div = <64>;
+ ti,index-power-of-two;
+};
+
+pcie_dclk_div: pcie_dclk_div@4ae061b4 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&apll_pcie_m2_ck>;
+ reg = <0x4ae061b4 0x4>;
+ ti,max-div = <64>;
+ ti,index-power-of-two;
+};
+
+emu_dclk_div: emu_dclk_div@4ae06194 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&sys_clkin1>;
+ reg = <0x4ae06194 0x4>;
+ ti,max-div = <64>;
+ ti,index-power-of-two;
+};
+
+secure_32k_dclk_div: secure_32k_dclk_div@4ae061c4 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&secure_32k_clk_src_ck>;
+ reg = <0x4ae061c4 0x4>;
+ ti,max-div = <64>;
+ ti,index-power-of-two;
+};
+
+eve_dpll_hs_clk_div: eve_dpll_hs_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_h12x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dpll_eve_ck: dpll_eve_ck@4a005284 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
+ reg = <0x4a005284 0x4>, <0x4a005288 0x4>, <0x4a00528c 0x4>, <0x4a005290 0x4>;
+};
+
+dpll_eve_m2_ck: dpll_eve_m2_ck@4a005294 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_eve_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a005294 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+eve_dclk_div: eve_dclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_eve_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+clkoutmux0_clk_mux: clkoutmux0_clk_mux@4ae06158 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
+ reg = <0x4ae06158 0x4>;
+};
+
+clkoutmux1_clk_mux: clkoutmux1_clk_mux@4ae0615c {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
+ reg = <0x4ae0615c 0x4>;
+};
+
+clkoutmux2_clk_mux: clkoutmux2_clk_mux@4ae06160 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
+ reg = <0x4ae06160 0x4>;
+};
+
+custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin1>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+dpll_core_h13x2_ck: dpll_core_h13x2_ck@4a005140 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a005140 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_core_h14x2_ck: dpll_core_h14x2_ck@4a005144 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a005144 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_core_h22x2_ck: dpll_core_h22x2_ck@4a005154 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a005154 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_core_h23x2_ck: dpll_core_h23x2_ck@4a005158 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a005158 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_core_h24x2_ck: dpll_core_h24x2_ck@4a00515c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a00515c 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_ddr_x2_ck: dpll_ddr_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_ddr_ck>;
+};
+
+dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck@4a005228 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_ddr_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a005228 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_dsp_x2_ck: dpll_dsp_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_dsp_ck>;
+};
+
+dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck@4a005248 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_dsp_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a005248 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_gmac_x2_ck: dpll_gmac_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_gmac_ck>;
+};
+
+dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck@4a0052c0 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_gmac_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0052c0 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck@4a0052c4 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_gmac_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0052c4 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck@4a0052c8 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_gmac_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0052c8 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck@4a0052bc {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_gmac_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0052bc 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_per_x2_ck: dpll_per_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_per_ck>;
+};
+
+dpll_per_h11x2_ck: dpll_per_h11x2_ck@4a008158 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008158 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_per_h12x2_ck: dpll_per_h12x2_ck@4a00815c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a00815c 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_per_h13x2_ck: dpll_per_h13x2_ck@4a008160 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008160 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_per_h14x2_ck: dpll_per_h14x2_ck@4a008164 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008164 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_per_m2x2_ck: dpll_per_m2x2_ck@4a008150 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008150 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_usb_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+eve_clk: eve_clk@4ae06180 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>;
+ reg = <0x4ae06180 0x4>;
+};
+
+func_128m_clk: func_128m_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_h11x2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+func_12m_fclk: func_12m_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <16>;
+};
+
+func_24m_clk: func_24m_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+};
+
+func_48m_fclk: func_48m_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+};
+
+func_96m_fclk: func_96m_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+gmii_m_clk_div: gmii_m_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_gmac_h11x2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+hdmi_clk2_div: hdmi_clk2_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&hdmi_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+hdmi_div_clk: hdmi_div_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&hdmi_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+hdmi_dpll_clk_mux: hdmi_dpll_clk_mux@4ae061a4 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin1>, <&sys_clkin2>;
+ reg = <0x4ae061a4 0x4>;
+};
+
+l3_iclk_div: l3_iclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_h12x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+l3init_60m_fclk: l3init_60m_fclk@4a008104 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_usb_m2_ck>;
+ reg = <0x4a008104 0x4>;
+ ti,dividers = <1>, <8>;
+};
+
+l4_root_clk_div: l4_root_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l3_iclk_div>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+mlb_clk: mlb_clk@4ae06134 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&mlb_clkin_ck>;
+ reg = <0x4ae06134 0x4>;
+ ti,max-div = <64>;
+ ti,index-power-of-two;
+};
+
+mlbp_clk: mlbp_clk@4ae06130 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&mlbp_clkin_ck>;
+ reg = <0x4ae06130 0x4>;
+ ti,max-div = <64>;
+ ti,index-power-of-two;
+};
+
+per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div@4ae06138 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_m2_ck>;
+ reg = <0x4ae06138 0x4>;
+ ti,max-div = <64>;
+ ti,index-power-of-two;
+};
+
+timer_sys_clk_div: timer_sys_clk_div@4ae06144 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&sys_clkin1>;
+ reg = <0x4ae06144 0x4>;
+ ti,max-div = <2>;
+};
+
+video1_clk2_div: video1_clk2_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&video1_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+video1_div_clk: video1_div_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&video1_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+video1_dpll_clk_mux: video1_dpll_clk_mux@4ae061d0 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin1>, <&sys_clkin2>;
+ reg = <0x4ae061d0 0x4>;
+};
+
+video2_clk2_div: video2_clk2_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&video2_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+video2_div_clk: video2_div_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&video2_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+video2_dpll_clk_mux: video2_dpll_clk_mux@4ae061d4 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin1>, <&sys_clkin2>;
+ reg = <0x4ae061d4 0x4>;
+};
+
+wkupaon_iclk_mux: wkupaon_iclk_mux@4ae06108 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin1>, <&abe_lp_clk_div>;
+ reg = <0x4ae06108 0x4>;
+};
+
+dss_32khz_clk: dss_32khz_clk@4a009120 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <11>;
+ reg = <0x4a009120 0x4>;
+};
+
+dss_48mhz_clk: dss_48mhz_clk@4a009120 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&func_48m_fclk>;
+ ti,bit-shift = <9>;
+ reg = <0x4a009120 0x4>;
+};
+
+dss_dss_clk: dss_dss_clk@4a009120 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll_per_h12x2_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009120 0x4>;
+};
+
+dss_hdmi_clk: dss_hdmi_clk@4a009120 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&hdmi_dpll_clk_mux>;
+ ti,bit-shift = <10>;
+ reg = <0x4a009120 0x4>;
+};
+
+dss_video1_clk: dss_video1_clk@4a009120 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&video1_dpll_clk_mux>;
+ ti,bit-shift = <12>;
+ reg = <0x4a009120 0x4>;
+};
+
+dss_video2_clk: dss_video2_clk@4a009120 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&video2_dpll_clk_mux>;
+ ti,bit-shift = <13>;
+ reg = <0x4a009120 0x4>;
+};
+
+gpio1_dbclk: gpio1_dbclk@4ae07838 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4ae07838 0x4>;
+};
+
+gpio2_dbclk: gpio2_dbclk@4a009760 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009760 0x4>;
+};
+
+gpio3_dbclk: gpio3_dbclk@4a009768 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009768 0x4>;
+};
+
+gpio4_dbclk: gpio4_dbclk@4a009770 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009770 0x4>;
+};
+
+gpio5_dbclk: gpio5_dbclk@4a009778 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009778 0x4>;
+};
+
+gpio6_dbclk: gpio6_dbclk@4a009780 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009780 0x4>;
+};
+
+gpio7_dbclk: gpio7_dbclk@4a009810 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009810 0x4>;
+};
+
+gpio8_dbclk: gpio8_dbclk@4a009818 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009818 0x4>;
+};
+
+mmc1_clk32k: mmc1_clk32k@4a009328 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009328 0x4>;
+};
+
+mmc2_clk32k: mmc2_clk32k@4a009330 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009330 0x4>;
+};
+
+mmc3_clk32k: mmc3_clk32k@4a009820 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009820 0x4>;
+};
+
+mmc4_clk32k: mmc4_clk32k@4a009828 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009828 0x4>;
+};
+
+sata_ref_clk: sata_ref_clk@4a009388 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_clkin1>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009388 0x4>;
+};
+
+usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m@4a0093f0 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll_usb_clkdcoldo>;
+ ti,bit-shift = <8>;
+ reg = <0x4a0093f0 0x4>;
+};
+
+usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m@4a009340 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll_usb_clkdcoldo>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009340 0x4>;
+};
+
+usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@4a008640 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a008640 0x4>;
+};
+
+usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k@4a008688 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a008688 0x4>;
+};
+
+usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k@4a008698 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a008698 0x4>;
+};
+
+atl_dpll_clk_mux: atl_dpll_clk_mux@4a008c00 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_32k_ck>, <&video1_clkin_ck>, <&video2_clkin_ck>, <&hdmi_clkin_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a008c00 0x4>;
+};
+
+atl_gfclk_mux: atl_gfclk_mux@4a008c00 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&l3_iclk_div>, <&dpll_abe_m2_ck>, <&atl_dpll_clk_mux>;
+ ti,bit-shift = <26>;
+ reg = <0x4a008c00 0x4>;
+};
+
+dcan1_sys_clk_mux: dcan1_sys_clk_mux@4ae07888 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin1>, <&sys_clkin2>;
+ ti,bit-shift = <24>;
+ reg = <0x4ae07888 0x4>;
+};
+
+gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div@4a0093d0 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_gmac_m2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a0093d0 0x4>;
+ ti,dividers = <2>;
+};
+
+gmac_rft_clk_mux: gmac_rft_clk_mux@4a0093d0 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&video1_clkin_ck>, <&video2_clkin_ck>, <&dpll_abe_m2_ck>, <&hdmi_clkin_ck>, <&l3_iclk_div>;
+ ti,bit-shift = <25>;
+ reg = <0x4a0093d0 0x4>;
+};
+
+gpu_core_gclk_mux: gpu_core_gclk_mux@4a009220 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009220 0x4>;
+};
+
+gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@4a009220 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
+ ti,bit-shift = <26>;
+ reg = <0x4a009220 0x4>;
+};
+
+ipu1_gfclk_mux: ipu1_gfclk_mux@4a005520 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a005520 0x4>;
+};
+
+l3instr_ts_gclk_div: l3instr_ts_gclk_div@4a008e50 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&wkupaon_iclk_mux>;
+ ti,bit-shift = <24>;
+ reg = <0x4a008e50 0x4>;
+ ti,dividers = <8>, <16>, <32>;
+};
+
+mcasp1_ahclkr_mux: mcasp1_ahclkr_mux@4a005550 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+ ti,bit-shift = <28>;
+ reg = <0x4a005550 0x4>;
+};
+
+mcasp1_ahclkx_mux: mcasp1_ahclkx_mux@4a005550 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a005550 0x4>;
+};
+
+mcasp1_aux_gfclk_mux: mcasp1_aux_gfclk_mux@4a005550 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+ ti,bit-shift = <22>;
+ reg = <0x4a005550 0x4>;
+};
+
+mcasp2_ahclkr_mux: mcasp2_ahclkr_mux@4a009860 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+ ti,bit-shift = <28>;
+ reg = <0x4a009860 0x4>;
+};
+
+mcasp2_ahclkx_mux: mcasp2_ahclkx_mux@4a009860 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+ ti,bit-shift = <28>;
+ reg = <0x4a009860 0x4>;
+};
+
+mcasp2_aux_gfclk_mux: mcasp2_aux_gfclk_mux@4a009860 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+ ti,bit-shift = <22>;
+ reg = <0x4a009860 0x4>;
+};
+
+mcasp3_ahclkx_mux: mcasp3_ahclkx_mux@4a009868 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009868 0x4>;
+};
+
+mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux@4a009868 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+ ti,bit-shift = <22>;
+ reg = <0x4a009868 0x4>;
+};
+
+mcasp4_ahclkx_mux: mcasp4_ahclkx_mux@4a009898 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009898 0x4>;
+};
+
+mcasp4_aux_gfclk_mux: mcasp4_aux_gfclk_mux@4a009898 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+ ti,bit-shift = <22>;
+ reg = <0x4a009898 0x4>;
+};
+
+mcasp5_ahclkx_mux: mcasp5_ahclkx_mux@4a009878 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009878 0x4>;
+};
+
+mcasp5_aux_gfclk_mux: mcasp5_aux_gfclk_mux@4a009878 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+ ti,bit-shift = <22>;
+ reg = <0x4a009878 0x4>;
+};
+
+mcasp6_ahclkx_mux: mcasp6_ahclkx_mux@4a009904 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009904 0x4>;
+};
+
+mcasp6_aux_gfclk_mux: mcasp6_aux_gfclk_mux@4a009904 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+ ti,bit-shift = <22>;
+ reg = <0x4a009904 0x4>;
+};
+
+mcasp7_ahclkx_mux: mcasp7_ahclkx_mux@4a009908 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009908 0x4>;
+};
+
+mcasp7_aux_gfclk_mux: mcasp7_aux_gfclk_mux@4a009908 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+ ti,bit-shift = <22>;
+ reg = <0x4a009908 0x4>;
+};
+
+mcasp8_ahclk_mux: mcasp8_ahclk_mux@4a009890 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+ ti,bit-shift = <22>;
+ reg = <0x4a009890 0x4>;
+};
+
+mcasp8_aux_gfclk_mux: mcasp8_aux_gfclk_mux@4a009890 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009890 0x4>;
+};
+
+mmc1_fclk_mux: mmc1_fclk_mux@4a009328 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009328 0x4>;
+};
+
+mmc1_fclk_div: mmc1_fclk_div@4a009328 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&mmc1_fclk_mux>;
+ ti,bit-shift = <25>;
+ ti,max-div = <4>;
+ reg = <0x4a009328 0x4>;
+ ti,index-power-of-two;
+};
+
+mmc2_fclk_mux: mmc2_fclk_mux@4a009330 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009330 0x4>;
+};
+
+mmc2_fclk_div: mmc2_fclk_div@4a009330 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&mmc2_fclk_mux>;
+ ti,bit-shift = <25>;
+ ti,max-div = <4>;
+ reg = <0x4a009330 0x4>;
+ ti,index-power-of-two;
+};
+
+mmc3_gfclk_mux: mmc3_gfclk_mux@4a009820 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009820 0x4>;
+};
+
+mmc3_gfclk_div: mmc3_gfclk_div@4a009820 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&mmc3_gfclk_mux>;
+ ti,bit-shift = <25>;
+ ti,max-div = <4>;
+ reg = <0x4a009820 0x4>;
+ ti,index-power-of-two;
+};
+
+mmc4_gfclk_mux: mmc4_gfclk_mux@4a009828 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009828 0x4>;
+};
+
+mmc4_gfclk_div: mmc4_gfclk_div@4a009828 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&mmc4_gfclk_mux>;
+ ti,bit-shift = <25>;
+ ti,max-div = <4>;
+ reg = <0x4a009828 0x4>;
+ ti,index-power-of-two;
+};
+
+qspi_gfclk_mux: qspi_gfclk_mux@4a009838 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_128m_clk>, <&dpll_per_h13x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009838 0x4>;
+};
+
+qspi_gfclk_div: qspi_gfclk_div@4a009838 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&qspi_gfclk_mux>;
+ ti,bit-shift = <25>;
+ ti,max-div = <4>;
+ reg = <0x4a009838 0x4>;
+ ti,index-power-of-two;
+};
+
+timer10_gfclk_mux: timer10_gfclk_mux@4a009728 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009728 0x4>;
+};
+
+timer11_gfclk_mux: timer11_gfclk_mux@4a009730 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009730 0x4>;
+};
+
+timer13_gfclk_mux: timer13_gfclk_mux@4a0097c8 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a0097c8 0x4>;
+};
+
+timer14_gfclk_mux: timer14_gfclk_mux@4a0097d0 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a0097d0 0x4>;
+};
+
+timer15_gfclk_mux: timer15_gfclk_mux@4a0097d8 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a0097d8 0x4>;
+};
+
+timer16_gfclk_mux: timer16_gfclk_mux@4a009830 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009830 0x4>;
+};
+
+timer1_gfclk_mux: timer1_gfclk_mux@4ae07840 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4ae07840 0x4>;
+};
+
+timer2_gfclk_mux: timer2_gfclk_mux@4a009738 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009738 0x4>;
+};
+
+timer3_gfclk_mux: timer3_gfclk_mux@4a009740 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009740 0x4>;
+};
+
+timer4_gfclk_mux: timer4_gfclk_mux@4a009748 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009748 0x4>;
+};
+
+timer5_gfclk_mux: timer5_gfclk_mux@4a005558 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
+ ti,bit-shift = <24>;
+ reg = <0x4a005558 0x4>;
+};
+
+timer6_gfclk_mux: timer6_gfclk_mux@4a005560 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
+ ti,bit-shift = <24>;
+ reg = <0x4a005560 0x4>;
+};
+
+timer7_gfclk_mux: timer7_gfclk_mux@4a005568 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
+ ti,bit-shift = <24>;
+ reg = <0x4a005568 0x4>;
+};
+
+timer8_gfclk_mux: timer8_gfclk_mux@4a005570 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
+ ti,bit-shift = <24>;
+ reg = <0x4a005570 0x4>;
+};
+
+timer9_gfclk_mux: timer9_gfclk_mux@4a009750 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009750 0x4>;
+};
+
+uart10_gfclk_mux: uart10_gfclk_mux@4ae07880 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4ae07880 0x4>;
+};
+
+uart1_gfclk_mux: uart1_gfclk_mux@4a009840 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009840 0x4>;
+};
+
+uart2_gfclk_mux: uart2_gfclk_mux@4a009848 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009848 0x4>;
+};
+
+uart3_gfclk_mux: uart3_gfclk_mux@4a009850 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009850 0x4>;
+};
+
+uart4_gfclk_mux: uart4_gfclk_mux@4a009858 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009858 0x4>;
+};
+
+uart5_gfclk_mux: uart5_gfclk_mux@4a009870 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009870 0x4>;
+};
+
+uart6_gfclk_mux: uart6_gfclk_mux@4a005580 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a005580 0x4>;
+};
+
+uart7_gfclk_mux: uart7_gfclk_mux@4a0098d0 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a0098d0 0x4>;
+};
+
+uart8_gfclk_mux: uart8_gfclk_mux@4a0098e0 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a0098e0 0x4>;
+};
+
+uart9_gfclk_mux: uart9_gfclk_mux@4a0098e8 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a0098e8 0x4>;
+};
+
+vip1_gclk_mux: vip1_gclk_mux@4a009020 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009020 0x4>;
+};
+
+vip2_gclk_mux: vip2_gclk_mux@4a009028 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009028 0x4>;
+};
+
+vip3_gclk_mux: vip3_gclk_mux@4a009030 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009030 0x4>;
+};
+
+dummy_ck: dummy_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
\ No newline at end of file
--
1.7.9.5
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^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 16/36] ARM: dts: dra7 clock data
@ 2013-09-25 8:48 ` Tero Kristo
0 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-arm-kernel
This patch creates a unique node for each clock in the DRA7 power,
reset and clock manager (PRCM).
TODO: apll_pcie clock node is still a dummy in this version, and
proper support for the APLL should be added.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/boot/dts/dra7xx-clocks.dtsi | 1975 ++++++++++++++++++++++++++++++++++
1 file changed, 1975 insertions(+)
create mode 100644 arch/arm/boot/dts/dra7xx-clocks.dtsi
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
new file mode 100644
index 0000000..0d83f95
--- /dev/null
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -0,0 +1,1975 @@
+/*
+ * Device Tree Source for DRA7xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+atl_clkin0_ck: atl_clkin0_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+atl_clkin1_ck: atl_clkin1_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+atl_clkin2_ck: atl_clkin2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+atlclkin3_ck: atlclkin3_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+hdmi_clkin_ck: hdmi_clkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+mlb_clkin_ck: mlb_clkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+mlbp_clkin_ck: mlbp_clkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+pciesref_acs_clk_ck: pciesref_acs_clk_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+};
+
+ref_clkin0_ck: ref_clkin0_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+ref_clkin1_ck: ref_clkin1_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+ref_clkin2_ck: ref_clkin2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+ref_clkin3_ck: ref_clkin3_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+rmii_clk_ck: rmii_clk_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+sdvenc_clkin_ck: sdvenc_clkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+secure_32k_clk_src_ck: secure_32k_clk_src_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+};
+
+sys_32k_ck: sys_32k_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+};
+
+virt_12000000_ck: virt_12000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+};
+
+virt_13000000_ck: virt_13000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <13000000>;
+};
+
+virt_16800000_ck: virt_16800000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <16800000>;
+};
+
+virt_19200000_ck: virt_19200000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <19200000>;
+};
+
+virt_20000000_ck: virt_20000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <20000000>;
+};
+
+virt_26000000_ck: virt_26000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <26000000>;
+};
+
+virt_27000000_ck: virt_27000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <27000000>;
+};
+
+virt_38400000_ck: virt_38400000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <38400000>;
+};
+
+sys_clkin1: sys_clkin1 at 4ae06110 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
+ reg = <0x4ae06110 0x4>;
+ ti,index-starts-at-one;
+};
+
+sys_clkin2: sys_clkin2 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <22579200>;
+};
+
+usb_otg_clkin_ck: usb_otg_clkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+video1_clkin_ck: video1_clkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+video1_m2_clkin_ck: video1_m2_clkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+video2_clkin_ck: video2_clkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+video2_m2_clkin_ck: video2_m2_clkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux at 4ae06118 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin1>, <&sys_clkin2>;
+ reg = <0x4ae06118 0x4>;
+};
+
+abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux at 4ae06114 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
+ reg = <0x4ae06114 0x4>;
+};
+
+abe_dpll_clk_mux: abe_dpll_clk_mux at 4ae0610c {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
+ reg = <0x4ae0610c 0x4>;
+};
+
+dpll_abe_ck: dpll_abe_ck at 4a0051e0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-m4xen-clock";
+ clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
+ reg = <0x4a0051e0 0x4>, <0x4a0051e4 0x4>, <0x4a0051e8 0x4>, <0x4a0051ec 0x4>;
+};
+
+dpll_abe_x2_ck: dpll_abe_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_abe_ck>;
+};
+
+dpll_abe_m2x2_ck: dpll_abe_m2x2_ck at 4a0051f0 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0051f0 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+abe_24m_fclk: abe_24m_fclk at 4ae0611c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_m2x2_ck>;
+ reg = <0x4ae0611c 0x4>;
+ ti,dividers = <8>, <16>;
+};
+
+abe_clk: abe_clk at 4a005108 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_m2x2_ck>;
+ reg = <0x4a005108 0x4>;
+ ti,max-div = <4>;
+ ti,index-power-of-two;
+};
+
+aess_fclk: aess_fclk at 4ae06178 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&abe_clk>;
+ reg = <0x4ae06178 0x4>;
+ ti,max-div = <2>;
+};
+
+abe_giclk_div: abe_giclk_div at 4ae06174 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&aess_fclk>;
+ reg = <0x4ae06174 0x4>;
+ ti,max-div = <2>;
+};
+
+abe_lp_clk_div: abe_lp_clk_div at 4ae061d8 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_m2x2_ck>;
+ reg = <0x4ae061d8 0x4>;
+ ti,dividers = <16>, <32>;
+};
+
+abe_sys_clk_div: abe_sys_clk_div at 4ae06120 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&sys_clkin1>;
+ reg = <0x4ae06120 0x4>;
+ ti,max-div = <2>;
+};
+
+adc_gfclk_mux: adc_gfclk_mux at 4ae061dc {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>;
+ reg = <0x4ae061dc 0x4>;
+};
+
+dpll_pcie_ref_ck: dpll_pcie_ref_ck at 4a008200 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin1>, <&sys_clkin1>;
+ reg = <0x4a008200 0x4>, <0x4a008204 0x4>, <0x4a008208 0x4>, <0x4a00820c 0x4>;
+};
+
+dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck at 4a008210 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_pcie_ref_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008210 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+apll_pcie_ck: apll_pcie_ck at 4a008200 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&dpll_pcie_ref_ck>, <&dpll_pcie_ref_ck>;
+ reg = <0x4a008200 0x4>, <0x4a008204 0x4>, <0x4a008208 0x4>, <0x4a00820c 0x4>;
+};
+
+apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&apll_pcie_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&apll_pcie_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+apll_pcie_m2_ck: apll_pcie_m2_ck at 4a008224 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&apll_pcie_ck>;
+ ti,max-div = <127>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008224 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+sys_clk1_dclk_div: sys_clk1_dclk_div at 4ae061c8 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&sys_clkin1>;
+ reg = <0x4ae061c8 0x4>;
+ ti,max-div = <64>;
+ ti,index-power-of-two;
+};
+
+sys_clk2_dclk_div: sys_clk2_dclk_div at 4ae061cc {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&sys_clkin2>;
+ reg = <0x4ae061cc 0x4>;
+ ti,max-div = <64>;
+ ti,index-power-of-two;
+};
+
+dpll_abe_m2_ck: dpll_abe_m2_ck at 4a0051f0 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0051f0 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+per_abe_x1_dclk_div: per_abe_x1_dclk_div at 4ae061bc {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_m2_ck>;
+ reg = <0x4ae061bc 0x4>;
+ ti,max-div = <64>;
+ ti,index-power-of-two;
+};
+
+dpll_abe_m3x2_ck: dpll_abe_m3x2_ck at 4a0051f4 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0051f4 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_core_ck: dpll_core_ck at 4a005120 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-core-clock";
+ clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+ reg = <0x4a005120 0x4>, <0x4a005124 0x4>, <0x4a005128 0x4>, <0x4a00512c 0x4>;
+};
+
+dpll_core_x2_ck: dpll_core_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_core_ck>;
+};
+
+dpll_core_h12x2_ck: dpll_core_h12x2_ck at 4a00513c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a00513c 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_h12x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dpll_mpu_ck: dpll_mpu_ck at 4a005160 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>;
+ reg = <0x4a005160 0x4>, <0x4a005164 0x4>, <0x4a005168 0x4>, <0x4a00516c 0x4>;
+};
+
+dpll_mpu_m2_ck: dpll_mpu_m2_ck at 4a005170 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_mpu_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a005170 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+mpu_dclk_div: mpu_dclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_mpu_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dsp_dpll_hs_clk_div: dsp_dpll_hs_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_h12x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dpll_dsp_ck: dpll_dsp_ck at 4a005234 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
+ reg = <0x4a005234 0x4>, <0x4a005238 0x4>, <0x4a00523c 0x4>, <0x4a005240 0x4>;
+};
+
+dpll_dsp_m2_ck: dpll_dsp_m2_ck at 4a005244 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_dsp_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a005244 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dsp_gclk_div: dsp_gclk_div at 4ae0618c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_dsp_m2_ck>;
+ reg = <0x4ae0618c 0x4>;
+ ti,max-div = <64>;
+ ti,index-power-of-two;
+};
+
+iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_h12x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dpll_iva_ck: dpll_iva_ck at 4a0051a0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
+ reg = <0x4a0051a0 0x4>, <0x4a0051a4 0x4>, <0x4a0051a8 0x4>, <0x4a0051ac 0x4>;
+};
+
+dpll_iva_m2_ck: dpll_iva_m2_ck at 4a0051b0 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_iva_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0051b0 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+iva_dclk: iva_dclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_iva_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dpll_gpu_ck: dpll_gpu_ck at 4a0052d8 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+ reg = <0x4a0052d8 0x4>, <0x4a0052dc 0x4>, <0x4a0052e0 0x4>, <0x4a0052e4 0x4>;
+};
+
+dpll_gpu_m2_ck: dpll_gpu_m2_ck at 4a0052e8 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_gpu_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0052e8 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+gpu_dclk: gpu_dclk at 4ae061a0 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_gpu_m2_ck>;
+ reg = <0x4ae061a0 0x4>;
+ ti,max-div = <64>;
+ ti,index-power-of-two;
+};
+
+dpll_core_m2_ck: dpll_core_m2_ck at 4a005130 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a005130 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+core_dpll_out_dclk_div: core_dpll_out_dclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dpll_ddr_ck: dpll_ddr_ck at 4a005210 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+ reg = <0x4a005210 0x4>, <0x4a005214 0x4>, <0x4a005218 0x4>, <0x4a00521c 0x4>;
+};
+
+dpll_ddr_m2_ck: dpll_ddr_m2_ck at 4a005220 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_ddr_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a005220 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+emif_phy_dclk_div: emif_phy_dclk_div at 4ae06190 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_ddr_m2_ck>;
+ reg = <0x4ae06190 0x4>;
+ ti,max-div = <64>;
+ ti,index-power-of-two;
+};
+
+dpll_gmac_ck: dpll_gmac_ck at 4a0052a8 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+ reg = <0x4a0052a8 0x4>, <0x4a0052ac 0x4>, <0x4a0052b0 0x4>, <0x4a0052b4 0x4>;
+};
+
+dpll_gmac_m2_ck: dpll_gmac_m2_ck at 4a0052b8 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_gmac_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0052b8 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+gmac_250m_dclk_div: gmac_250m_dclk_div at 4ae0619c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_gmac_m2_ck>;
+ reg = <0x4ae0619c 0x4>;
+ ti,max-div = <64>;
+ ti,index-power-of-two;
+};
+
+video2_dclk_div: video2_dclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&video2_m2_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+video1_dclk_div: video1_dclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&video1_m2_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+hdmi_dclk_div: hdmi_dclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&hdmi_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+per_dpll_hs_clk_div: per_dpll_hs_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_abe_m3x2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+dpll_per_ck: dpll_per_ck at 4a008140 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
+ reg = <0x4a008140 0x4>, <0x4a008144 0x4>, <0x4a008148 0x4>, <0x4a00814c 0x4>;
+};
+
+dpll_per_m2_ck: dpll_per_m2_ck at 4a008150 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008150 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+func_96m_aon_dclk_div: func_96m_aon_dclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_abe_m3x2_ck>;
+ clock-mult = <1>;
+ clock-div = <3>;
+};
+
+dpll_usb_ck: dpll_usb_ck at 4a008180 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-j-type-clock";
+ clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
+ reg = <0x4a008180 0x4>, <0x4a008184 0x4>, <0x4a008188 0x4>, <0x4a00818c 0x4>;
+};
+
+dpll_usb_m2_ck: dpll_usb_m2_ck at 4a008190 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_usb_ck>;
+ ti,max-div = <127>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008190 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+l3init_480m_dclk_div: l3init_480m_dclk_div at 4ae061ac {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_usb_m2_ck>;
+ reg = <0x4ae061ac 0x4>;
+ ti,max-div = <64>;
+ ti,index-power-of-two;
+};
+
+usb_otg_dclk_div: usb_otg_dclk_div at 4ae06184 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&usb_otg_clkin_ck>;
+ reg = <0x4ae06184 0x4>;
+ ti,max-div = <64>;
+ ti,index-power-of-two;
+};
+
+sata_dclk_div: sata_dclk_div at 4ae061c0 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&sys_clkin1>;
+ reg = <0x4ae061c0 0x4>;
+ ti,max-div = <64>;
+ ti,index-power-of-two;
+};
+
+dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck at 4a008210 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_pcie_ref_ck>;
+ ti,max-div = <127>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008210 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+pcie2_dclk_div: pcie2_dclk_div at 4ae061b8 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_pcie_ref_m2_ck>;
+ reg = <0x4ae061b8 0x4>;
+ ti,max-div = <64>;
+ ti,index-power-of-two;
+};
+
+pcie_dclk_div: pcie_dclk_div at 4ae061b4 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&apll_pcie_m2_ck>;
+ reg = <0x4ae061b4 0x4>;
+ ti,max-div = <64>;
+ ti,index-power-of-two;
+};
+
+emu_dclk_div: emu_dclk_div at 4ae06194 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&sys_clkin1>;
+ reg = <0x4ae06194 0x4>;
+ ti,max-div = <64>;
+ ti,index-power-of-two;
+};
+
+secure_32k_dclk_div: secure_32k_dclk_div at 4ae061c4 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&secure_32k_clk_src_ck>;
+ reg = <0x4ae061c4 0x4>;
+ ti,max-div = <64>;
+ ti,index-power-of-two;
+};
+
+eve_dpll_hs_clk_div: eve_dpll_hs_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_h12x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dpll_eve_ck: dpll_eve_ck at 4a005284 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
+ reg = <0x4a005284 0x4>, <0x4a005288 0x4>, <0x4a00528c 0x4>, <0x4a005290 0x4>;
+};
+
+dpll_eve_m2_ck: dpll_eve_m2_ck at 4a005294 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_eve_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a005294 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+eve_dclk_div: eve_dclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_eve_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+clkoutmux0_clk_mux: clkoutmux0_clk_mux at 4ae06158 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
+ reg = <0x4ae06158 0x4>;
+};
+
+clkoutmux1_clk_mux: clkoutmux1_clk_mux at 4ae0615c {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
+ reg = <0x4ae0615c 0x4>;
+};
+
+clkoutmux2_clk_mux: clkoutmux2_clk_mux at 4ae06160 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
+ reg = <0x4ae06160 0x4>;
+};
+
+custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin1>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+dpll_core_h13x2_ck: dpll_core_h13x2_ck at 4a005140 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a005140 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_core_h14x2_ck: dpll_core_h14x2_ck at 4a005144 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a005144 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_core_h22x2_ck: dpll_core_h22x2_ck at 4a005154 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a005154 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_core_h23x2_ck: dpll_core_h23x2_ck at 4a005158 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a005158 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_core_h24x2_ck: dpll_core_h24x2_ck at 4a00515c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a00515c 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_ddr_x2_ck: dpll_ddr_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_ddr_ck>;
+};
+
+dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck at 4a005228 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_ddr_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a005228 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_dsp_x2_ck: dpll_dsp_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_dsp_ck>;
+};
+
+dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck at 4a005248 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_dsp_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a005248 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_gmac_x2_ck: dpll_gmac_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_gmac_ck>;
+};
+
+dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck at 4a0052c0 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_gmac_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0052c0 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck at 4a0052c4 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_gmac_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0052c4 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck at 4a0052c8 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_gmac_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0052c8 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck at 4a0052bc {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_gmac_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0052bc 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_per_x2_ck: dpll_per_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_per_ck>;
+};
+
+dpll_per_h11x2_ck: dpll_per_h11x2_ck at 4a008158 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008158 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_per_h12x2_ck: dpll_per_h12x2_ck at 4a00815c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a00815c 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_per_h13x2_ck: dpll_per_h13x2_ck at 4a008160 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008160 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_per_h14x2_ck: dpll_per_h14x2_ck at 4a008164 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008164 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_per_m2x2_ck: dpll_per_m2x2_ck at 4a008150 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008150 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_usb_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+eve_clk: eve_clk at 4ae06180 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>;
+ reg = <0x4ae06180 0x4>;
+};
+
+func_128m_clk: func_128m_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_h11x2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+func_12m_fclk: func_12m_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <16>;
+};
+
+func_24m_clk: func_24m_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+};
+
+func_48m_fclk: func_48m_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+};
+
+func_96m_fclk: func_96m_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+gmii_m_clk_div: gmii_m_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_gmac_h11x2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+hdmi_clk2_div: hdmi_clk2_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&hdmi_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+hdmi_div_clk: hdmi_div_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&hdmi_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+hdmi_dpll_clk_mux: hdmi_dpll_clk_mux at 4ae061a4 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin1>, <&sys_clkin2>;
+ reg = <0x4ae061a4 0x4>;
+};
+
+l3_iclk_div: l3_iclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_h12x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+l3init_60m_fclk: l3init_60m_fclk at 4a008104 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_usb_m2_ck>;
+ reg = <0x4a008104 0x4>;
+ ti,dividers = <1>, <8>;
+};
+
+l4_root_clk_div: l4_root_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l3_iclk_div>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+mlb_clk: mlb_clk at 4ae06134 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&mlb_clkin_ck>;
+ reg = <0x4ae06134 0x4>;
+ ti,max-div = <64>;
+ ti,index-power-of-two;
+};
+
+mlbp_clk: mlbp_clk at 4ae06130 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&mlbp_clkin_ck>;
+ reg = <0x4ae06130 0x4>;
+ ti,max-div = <64>;
+ ti,index-power-of-two;
+};
+
+per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div at 4ae06138 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_m2_ck>;
+ reg = <0x4ae06138 0x4>;
+ ti,max-div = <64>;
+ ti,index-power-of-two;
+};
+
+timer_sys_clk_div: timer_sys_clk_div at 4ae06144 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&sys_clkin1>;
+ reg = <0x4ae06144 0x4>;
+ ti,max-div = <2>;
+};
+
+video1_clk2_div: video1_clk2_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&video1_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+video1_div_clk: video1_div_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&video1_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+video1_dpll_clk_mux: video1_dpll_clk_mux at 4ae061d0 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin1>, <&sys_clkin2>;
+ reg = <0x4ae061d0 0x4>;
+};
+
+video2_clk2_div: video2_clk2_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&video2_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+video2_div_clk: video2_div_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&video2_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+video2_dpll_clk_mux: video2_dpll_clk_mux at 4ae061d4 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin1>, <&sys_clkin2>;
+ reg = <0x4ae061d4 0x4>;
+};
+
+wkupaon_iclk_mux: wkupaon_iclk_mux at 4ae06108 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin1>, <&abe_lp_clk_div>;
+ reg = <0x4ae06108 0x4>;
+};
+
+dss_32khz_clk: dss_32khz_clk at 4a009120 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <11>;
+ reg = <0x4a009120 0x4>;
+};
+
+dss_48mhz_clk: dss_48mhz_clk at 4a009120 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&func_48m_fclk>;
+ ti,bit-shift = <9>;
+ reg = <0x4a009120 0x4>;
+};
+
+dss_dss_clk: dss_dss_clk at 4a009120 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll_per_h12x2_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009120 0x4>;
+};
+
+dss_hdmi_clk: dss_hdmi_clk at 4a009120 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&hdmi_dpll_clk_mux>;
+ ti,bit-shift = <10>;
+ reg = <0x4a009120 0x4>;
+};
+
+dss_video1_clk: dss_video1_clk at 4a009120 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&video1_dpll_clk_mux>;
+ ti,bit-shift = <12>;
+ reg = <0x4a009120 0x4>;
+};
+
+dss_video2_clk: dss_video2_clk at 4a009120 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&video2_dpll_clk_mux>;
+ ti,bit-shift = <13>;
+ reg = <0x4a009120 0x4>;
+};
+
+gpio1_dbclk: gpio1_dbclk at 4ae07838 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4ae07838 0x4>;
+};
+
+gpio2_dbclk: gpio2_dbclk at 4a009760 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009760 0x4>;
+};
+
+gpio3_dbclk: gpio3_dbclk at 4a009768 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009768 0x4>;
+};
+
+gpio4_dbclk: gpio4_dbclk at 4a009770 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009770 0x4>;
+};
+
+gpio5_dbclk: gpio5_dbclk at 4a009778 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009778 0x4>;
+};
+
+gpio6_dbclk: gpio6_dbclk at 4a009780 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009780 0x4>;
+};
+
+gpio7_dbclk: gpio7_dbclk at 4a009810 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009810 0x4>;
+};
+
+gpio8_dbclk: gpio8_dbclk at 4a009818 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009818 0x4>;
+};
+
+mmc1_clk32k: mmc1_clk32k at 4a009328 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009328 0x4>;
+};
+
+mmc2_clk32k: mmc2_clk32k at 4a009330 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009330 0x4>;
+};
+
+mmc3_clk32k: mmc3_clk32k at 4a009820 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009820 0x4>;
+};
+
+mmc4_clk32k: mmc4_clk32k at 4a009828 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009828 0x4>;
+};
+
+sata_ref_clk: sata_ref_clk at 4a009388 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_clkin1>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009388 0x4>;
+};
+
+usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m at 4a0093f0 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll_usb_clkdcoldo>;
+ ti,bit-shift = <8>;
+ reg = <0x4a0093f0 0x4>;
+};
+
+usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m at 4a009340 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll_usb_clkdcoldo>;
+ ti,bit-shift = <8>;
+ reg = <0x4a009340 0x4>;
+};
+
+usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k at 4a008640 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a008640 0x4>;
+};
+
+usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k at 4a008688 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a008688 0x4>;
+};
+
+usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k at 4a008698 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x4a008698 0x4>;
+};
+
+atl_dpll_clk_mux: atl_dpll_clk_mux at 4a008c00 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_32k_ck>, <&video1_clkin_ck>, <&video2_clkin_ck>, <&hdmi_clkin_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a008c00 0x4>;
+};
+
+atl_gfclk_mux: atl_gfclk_mux at 4a008c00 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&l3_iclk_div>, <&dpll_abe_m2_ck>, <&atl_dpll_clk_mux>;
+ ti,bit-shift = <26>;
+ reg = <0x4a008c00 0x4>;
+};
+
+dcan1_sys_clk_mux: dcan1_sys_clk_mux at 4ae07888 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin1>, <&sys_clkin2>;
+ ti,bit-shift = <24>;
+ reg = <0x4ae07888 0x4>;
+};
+
+gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div at 4a0093d0 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_gmac_m2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a0093d0 0x4>;
+ ti,dividers = <2>;
+};
+
+gmac_rft_clk_mux: gmac_rft_clk_mux at 4a0093d0 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&video1_clkin_ck>, <&video2_clkin_ck>, <&dpll_abe_m2_ck>, <&hdmi_clkin_ck>, <&l3_iclk_div>;
+ ti,bit-shift = <25>;
+ reg = <0x4a0093d0 0x4>;
+};
+
+gpu_core_gclk_mux: gpu_core_gclk_mux at 4a009220 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009220 0x4>;
+};
+
+gpu_hyd_gclk_mux: gpu_hyd_gclk_mux at 4a009220 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
+ ti,bit-shift = <26>;
+ reg = <0x4a009220 0x4>;
+};
+
+ipu1_gfclk_mux: ipu1_gfclk_mux at 4a005520 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a005520 0x4>;
+};
+
+l3instr_ts_gclk_div: l3instr_ts_gclk_div at 4a008e50 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&wkupaon_iclk_mux>;
+ ti,bit-shift = <24>;
+ reg = <0x4a008e50 0x4>;
+ ti,dividers = <8>, <16>, <32>;
+};
+
+mcasp1_ahclkr_mux: mcasp1_ahclkr_mux at 4a005550 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+ ti,bit-shift = <28>;
+ reg = <0x4a005550 0x4>;
+};
+
+mcasp1_ahclkx_mux: mcasp1_ahclkx_mux at 4a005550 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a005550 0x4>;
+};
+
+mcasp1_aux_gfclk_mux: mcasp1_aux_gfclk_mux at 4a005550 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+ ti,bit-shift = <22>;
+ reg = <0x4a005550 0x4>;
+};
+
+mcasp2_ahclkr_mux: mcasp2_ahclkr_mux at 4a009860 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+ ti,bit-shift = <28>;
+ reg = <0x4a009860 0x4>;
+};
+
+mcasp2_ahclkx_mux: mcasp2_ahclkx_mux at 4a009860 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+ ti,bit-shift = <28>;
+ reg = <0x4a009860 0x4>;
+};
+
+mcasp2_aux_gfclk_mux: mcasp2_aux_gfclk_mux at 4a009860 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+ ti,bit-shift = <22>;
+ reg = <0x4a009860 0x4>;
+};
+
+mcasp3_ahclkx_mux: mcasp3_ahclkx_mux at 4a009868 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009868 0x4>;
+};
+
+mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux at 4a009868 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+ ti,bit-shift = <22>;
+ reg = <0x4a009868 0x4>;
+};
+
+mcasp4_ahclkx_mux: mcasp4_ahclkx_mux at 4a009898 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009898 0x4>;
+};
+
+mcasp4_aux_gfclk_mux: mcasp4_aux_gfclk_mux at 4a009898 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+ ti,bit-shift = <22>;
+ reg = <0x4a009898 0x4>;
+};
+
+mcasp5_ahclkx_mux: mcasp5_ahclkx_mux at 4a009878 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009878 0x4>;
+};
+
+mcasp5_aux_gfclk_mux: mcasp5_aux_gfclk_mux at 4a009878 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+ ti,bit-shift = <22>;
+ reg = <0x4a009878 0x4>;
+};
+
+mcasp6_ahclkx_mux: mcasp6_ahclkx_mux at 4a009904 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009904 0x4>;
+};
+
+mcasp6_aux_gfclk_mux: mcasp6_aux_gfclk_mux at 4a009904 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+ ti,bit-shift = <22>;
+ reg = <0x4a009904 0x4>;
+};
+
+mcasp7_ahclkx_mux: mcasp7_ahclkx_mux at 4a009908 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009908 0x4>;
+};
+
+mcasp7_aux_gfclk_mux: mcasp7_aux_gfclk_mux at 4a009908 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+ ti,bit-shift = <22>;
+ reg = <0x4a009908 0x4>;
+};
+
+mcasp8_ahclk_mux: mcasp8_ahclk_mux at 4a009890 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+ ti,bit-shift = <22>;
+ reg = <0x4a009890 0x4>;
+};
+
+mcasp8_aux_gfclk_mux: mcasp8_aux_gfclk_mux at 4a009890 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009890 0x4>;
+};
+
+mmc1_fclk_mux: mmc1_fclk_mux at 4a009328 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009328 0x4>;
+};
+
+mmc1_fclk_div: mmc1_fclk_div at 4a009328 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&mmc1_fclk_mux>;
+ ti,bit-shift = <25>;
+ ti,max-div = <4>;
+ reg = <0x4a009328 0x4>;
+ ti,index-power-of-two;
+};
+
+mmc2_fclk_mux: mmc2_fclk_mux at 4a009330 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009330 0x4>;
+};
+
+mmc2_fclk_div: mmc2_fclk_div at 4a009330 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&mmc2_fclk_mux>;
+ ti,bit-shift = <25>;
+ ti,max-div = <4>;
+ reg = <0x4a009330 0x4>;
+ ti,index-power-of-two;
+};
+
+mmc3_gfclk_mux: mmc3_gfclk_mux at 4a009820 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009820 0x4>;
+};
+
+mmc3_gfclk_div: mmc3_gfclk_div at 4a009820 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&mmc3_gfclk_mux>;
+ ti,bit-shift = <25>;
+ ti,max-div = <4>;
+ reg = <0x4a009820 0x4>;
+ ti,index-power-of-two;
+};
+
+mmc4_gfclk_mux: mmc4_gfclk_mux at 4a009828 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009828 0x4>;
+};
+
+mmc4_gfclk_div: mmc4_gfclk_div at 4a009828 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&mmc4_gfclk_mux>;
+ ti,bit-shift = <25>;
+ ti,max-div = <4>;
+ reg = <0x4a009828 0x4>;
+ ti,index-power-of-two;
+};
+
+qspi_gfclk_mux: qspi_gfclk_mux at 4a009838 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_128m_clk>, <&dpll_per_h13x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009838 0x4>;
+};
+
+qspi_gfclk_div: qspi_gfclk_div at 4a009838 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&qspi_gfclk_mux>;
+ ti,bit-shift = <25>;
+ ti,max-div = <4>;
+ reg = <0x4a009838 0x4>;
+ ti,index-power-of-two;
+};
+
+timer10_gfclk_mux: timer10_gfclk_mux at 4a009728 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009728 0x4>;
+};
+
+timer11_gfclk_mux: timer11_gfclk_mux at 4a009730 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009730 0x4>;
+};
+
+timer13_gfclk_mux: timer13_gfclk_mux at 4a0097c8 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a0097c8 0x4>;
+};
+
+timer14_gfclk_mux: timer14_gfclk_mux at 4a0097d0 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a0097d0 0x4>;
+};
+
+timer15_gfclk_mux: timer15_gfclk_mux at 4a0097d8 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a0097d8 0x4>;
+};
+
+timer16_gfclk_mux: timer16_gfclk_mux at 4a009830 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009830 0x4>;
+};
+
+timer1_gfclk_mux: timer1_gfclk_mux at 4ae07840 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4ae07840 0x4>;
+};
+
+timer2_gfclk_mux: timer2_gfclk_mux at 4a009738 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009738 0x4>;
+};
+
+timer3_gfclk_mux: timer3_gfclk_mux at 4a009740 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009740 0x4>;
+};
+
+timer4_gfclk_mux: timer4_gfclk_mux at 4a009748 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009748 0x4>;
+};
+
+timer5_gfclk_mux: timer5_gfclk_mux at 4a005558 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
+ ti,bit-shift = <24>;
+ reg = <0x4a005558 0x4>;
+};
+
+timer6_gfclk_mux: timer6_gfclk_mux at 4a005560 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
+ ti,bit-shift = <24>;
+ reg = <0x4a005560 0x4>;
+};
+
+timer7_gfclk_mux: timer7_gfclk_mux at 4a005568 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
+ ti,bit-shift = <24>;
+ reg = <0x4a005568 0x4>;
+};
+
+timer8_gfclk_mux: timer8_gfclk_mux at 4a005570 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
+ ti,bit-shift = <24>;
+ reg = <0x4a005570 0x4>;
+};
+
+timer9_gfclk_mux: timer9_gfclk_mux at 4a009750 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009750 0x4>;
+};
+
+uart10_gfclk_mux: uart10_gfclk_mux at 4ae07880 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4ae07880 0x4>;
+};
+
+uart1_gfclk_mux: uart1_gfclk_mux at 4a009840 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009840 0x4>;
+};
+
+uart2_gfclk_mux: uart2_gfclk_mux at 4a009848 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009848 0x4>;
+};
+
+uart3_gfclk_mux: uart3_gfclk_mux at 4a009850 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009850 0x4>;
+};
+
+uart4_gfclk_mux: uart4_gfclk_mux at 4a009858 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009858 0x4>;
+};
+
+uart5_gfclk_mux: uart5_gfclk_mux at 4a009870 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009870 0x4>;
+};
+
+uart6_gfclk_mux: uart6_gfclk_mux at 4a005580 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a005580 0x4>;
+};
+
+uart7_gfclk_mux: uart7_gfclk_mux at 4a0098d0 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a0098d0 0x4>;
+};
+
+uart8_gfclk_mux: uart8_gfclk_mux at 4a0098e0 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a0098e0 0x4>;
+};
+
+uart9_gfclk_mux: uart9_gfclk_mux at 4a0098e8 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a0098e8 0x4>;
+};
+
+vip1_gclk_mux: vip1_gclk_mux at 4a009020 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009020 0x4>;
+};
+
+vip2_gclk_mux: vip2_gclk_mux at 4a009028 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009028 0x4>;
+};
+
+vip3_gclk_mux: vip3_gclk_mux at 4a009030 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x4a009030 0x4>;
+};
+
+dummy_ck: dummy_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
\ No newline at end of file
--
1.7.9.5
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 17/36] ARM: dts: clk: Add apll related clocks
2013-09-25 8:48 ` Tero Kristo
@ 2013-09-25 8:48 ` Tero Kristo
-1 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-omap-u79uwXL29TY76Z2rM5mHXA, paul-DWxLp4Yu+b8AvxtiuMwx3w,
tony-4v6yS6AI5VpBDgjK7y7TUQ, nm-l0cyMroinI0, rnayak-l0cyMroinI0,
bcousson-rdvid1DuHRBWk0Htik3J/w,
mturquette-QSEj5FYQhm4dnm+yROfE0A
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, Keerthy
From: Keerthy <j-keerthy-l0cyMroinI0@public.gmane.org>
The patch adds a mux node to choose the parent of apll_pcie_ck node.
Signed-off-by: Keerthy <j-keerthy-l0cyMroinI0@public.gmane.org>
Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
arch/arm/boot/dts/dra7xx-clocks.dtsi | 14 +++++++++++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 0d83f95..c830e15 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -315,11 +315,19 @@ dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck@4a008210 {
ti,autoidle-low;
};
+apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
+ compatible = "ti,mux-clock";
+ clocks = <&dpll_pcie_ref_ck>, <&pciesref_acs_clk_ck>;
+ #clock-cells = <0>;
+ reg = <0x4a00821c 0x4>;
+ ti,bit-shift = <7>;
+};
+
apll_pcie_ck: apll_pcie_ck@4a008200 {
#clock-cells = <0>;
- compatible = "ti,omap4-dpll-clock";
- clocks = <&dpll_pcie_ref_ck>, <&dpll_pcie_ref_ck>;
- reg = <0x4a008200 0x4>, <0x4a008204 0x4>, <0x4a008208 0x4>, <0x4a00820c 0x4>;
+ compatible = "ti,dra7-apll-clock";
+ clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
+ reg = <0x4a00821c 0x4>, <0x4a008220 0x4>;
};
apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
--
1.7.9.5
--
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^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 17/36] ARM: dts: clk: Add apll related clocks
@ 2013-09-25 8:48 ` Tero Kristo
0 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-arm-kernel
From: Keerthy <j-keerthy@ti.com>
The patch adds a mux node to choose the parent of apll_pcie_ck node.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/boot/dts/dra7xx-clocks.dtsi | 14 +++++++++++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 0d83f95..c830e15 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -315,11 +315,19 @@ dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck at 4a008210 {
ti,autoidle-low;
};
+apll_pcie_in_clk_mux: apll_pcie_in_clk_mux at 4ae06118 {
+ compatible = "ti,mux-clock";
+ clocks = <&dpll_pcie_ref_ck>, <&pciesref_acs_clk_ck>;
+ #clock-cells = <0>;
+ reg = <0x4a00821c 0x4>;
+ ti,bit-shift = <7>;
+};
+
apll_pcie_ck: apll_pcie_ck at 4a008200 {
#clock-cells = <0>;
- compatible = "ti,omap4-dpll-clock";
- clocks = <&dpll_pcie_ref_ck>, <&dpll_pcie_ref_ck>;
- reg = <0x4a008200 0x4>, <0x4a008204 0x4>, <0x4a008208 0x4>, <0x4a00820c 0x4>;
+ compatible = "ti,dra7-apll-clock";
+ clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
+ reg = <0x4a00821c 0x4>, <0x4a008220 0x4>;
};
apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
--
1.7.9.5
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 18/36] ARM: dts: DRA7: Change apll_pcie_m2_ck to fixed factor clock
2013-09-25 8:48 ` Tero Kristo
@ 2013-09-25 8:48 ` Tero Kristo
-1 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-omap, paul, tony, nm, rnayak, bcousson, mturquette
Cc: linux-arm-kernel, devicetree, Keerthy
From: Keerthy <j-keerthy@ti.com>
This patch changes apll_pcie_m2_ck to fixed factor
clock as there are no configurable divider associated to m2.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/boot/dts/dra7xx-clocks.dtsi | 9 +++------
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index c830e15..75d5e1b 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -348,13 +348,10 @@ apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div {
apll_pcie_m2_ck: apll_pcie_m2_ck@4a008224 {
#clock-cells = <0>;
- compatible = "ti,divider-clock";
+ compatible = "fixed-factor-clock";
clocks = <&apll_pcie_ck>;
- ti,max-div = <127>;
- ti,autoidle-shift = <8>;
- reg = <0x4a008224 0x4>;
- ti,index-starts-at-one;
- ti,autoidle-low;
+ clock-mult = <1>;
+ clock-div = <1>;
};
sys_clk1_dclk_div: sys_clk1_dclk_div@4ae061c8 {
--
1.7.9.5
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 18/36] ARM: dts: DRA7: Change apll_pcie_m2_ck to fixed factor clock
@ 2013-09-25 8:48 ` Tero Kristo
0 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-arm-kernel
From: Keerthy <j-keerthy@ti.com>
This patch changes apll_pcie_m2_ck to fixed factor
clock as there are no configurable divider associated to m2.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/boot/dts/dra7xx-clocks.dtsi | 9 +++------
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index c830e15..75d5e1b 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -348,13 +348,10 @@ apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div {
apll_pcie_m2_ck: apll_pcie_m2_ck at 4a008224 {
#clock-cells = <0>;
- compatible = "ti,divider-clock";
+ compatible = "fixed-factor-clock";
clocks = <&apll_pcie_ck>;
- ti,max-div = <127>;
- ti,autoidle-shift = <8>;
- reg = <0x4a008224 0x4>;
- ti,index-starts-at-one;
- ti,autoidle-low;
+ clock-mult = <1>;
+ clock-div = <1>;
};
sys_clk1_dclk_div: sys_clk1_dclk_div at 4ae061c8 {
--
1.7.9.5
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 19/36] ARM: dts: DRA7: Add PCIe related clock nodes
2013-09-25 8:48 ` Tero Kristo
@ 2013-09-25 8:48 ` Tero Kristo
-1 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-omap, paul, tony, nm, rnayak, bcousson, mturquette
Cc: linux-arm-kernel, devicetree, Keerthy
From: Keerthy <j-keerthy@ti.com>
This patch adds optfclk_pciephy_clk and optfclk_pciephy_div_clk
which are used by PCIe phy. It also adds a mux clock to choose
the source of optfclk_pciephy_div_clk clock.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/boot/dts/dra7xx-clocks.dtsi | 27 ++++++++++++++++++++++++++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 75d5e1b..d83afd3 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1973,8 +1973,33 @@ vip3_gclk_mux: vip3_gclk_mux@4a009030 {
reg = <0x4a009030 0x4>;
};
+optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
+ compatible = "ti,divider-clock";
+ clocks = <&apll_pcie_ck>;
+ #clock-cells = <0>;
+ reg = <0x4a00821c 0x4>;
+ ti,bit-shift = <8>;
+ ti,max-div = <2>;
+};
+
+optfclk_pciephy_clk: optfclk_pciephy_clk@4a0093b0 {
+ compatible = "ti,gate-clock";
+ clocks = <&apll_pcie_ck>;
+ #clock-cells = <0>;
+ reg = <0x4a0093b0 0x4>;
+ ti,bit-shift = <9>;
+};
+
+optfclk_pciephy_div_clk: optfclk_pciephy_div_clk@4a0093b0 {
+ compatible = "ti,gate-clock";
+ clocks = <&optfclk_pciephy_div>;
+ #clock-cells = <0>;
+ reg = <0x4a0093b0 0x4>;
+ ti,bit-shift = <10>;
+};
+
dummy_ck: dummy_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
-};
\ No newline at end of file
+};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 19/36] ARM: dts: DRA7: Add PCIe related clock nodes
@ 2013-09-25 8:48 ` Tero Kristo
0 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-arm-kernel
From: Keerthy <j-keerthy@ti.com>
This patch adds optfclk_pciephy_clk and optfclk_pciephy_div_clk
which are used by PCIe phy. It also adds a mux clock to choose
the source of optfclk_pciephy_div_clk clock.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/boot/dts/dra7xx-clocks.dtsi | 27 ++++++++++++++++++++++++++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 75d5e1b..d83afd3 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1973,8 +1973,33 @@ vip3_gclk_mux: vip3_gclk_mux at 4a009030 {
reg = <0x4a009030 0x4>;
};
+optfclk_pciephy_div: optfclk_pciephy_div at 4a00821c {
+ compatible = "ti,divider-clock";
+ clocks = <&apll_pcie_ck>;
+ #clock-cells = <0>;
+ reg = <0x4a00821c 0x4>;
+ ti,bit-shift = <8>;
+ ti,max-div = <2>;
+};
+
+optfclk_pciephy_clk: optfclk_pciephy_clk at 4a0093b0 {
+ compatible = "ti,gate-clock";
+ clocks = <&apll_pcie_ck>;
+ #clock-cells = <0>;
+ reg = <0x4a0093b0 0x4>;
+ ti,bit-shift = <9>;
+};
+
+optfclk_pciephy_div_clk: optfclk_pciephy_div_clk at 4a0093b0 {
+ compatible = "ti,gate-clock";
+ clocks = <&optfclk_pciephy_div>;
+ #clock-cells = <0>;
+ reg = <0x4a0093b0 0x4>;
+ ti,bit-shift = <10>;
+};
+
dummy_ck: dummy_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
-};
\ No newline at end of file
+};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 20/36] CLK: TI: DRA7: Add APLL support
2013-09-25 8:48 ` Tero Kristo
@ 2013-09-25 8:48 ` Tero Kristo
-1 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-omap-u79uwXL29TY76Z2rM5mHXA, paul-DWxLp4Yu+b8AvxtiuMwx3w,
tony-4v6yS6AI5VpBDgjK7y7TUQ, nm-l0cyMroinI0, rnayak-l0cyMroinI0,
bcousson-rdvid1DuHRBWk0Htik3J/w,
mturquette-QSEj5FYQhm4dnm+yROfE0A
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, Keerthy
From: Keerthy <j-keerthy-l0cyMroinI0@public.gmane.org>
The patch adds support for DRA7 PCIe APLL. The APLL
sources the optional functional clocks for PCIe module.
APLL stands for Analog PLL. This is different when comapred
with DPLL meaning Digital PLL, the phase detection is done
using an analog circuit.
Signed-off-by: Keerthy <j-keerthy-l0cyMroinI0@public.gmane.org>
Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
.../devicetree/bindings/clock/ti/apll.txt | 29 +++
drivers/clk/ti/Makefile | 2 +-
drivers/clk/ti/apll.c | 207 ++++++++++++++++++++
3 files changed, 237 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/clock/ti/apll.txt
create mode 100644 drivers/clk/ti/apll.c
diff --git a/Documentation/devicetree/bindings/clock/ti/apll.txt b/Documentation/devicetree/bindings/clock/ti/apll.txt
new file mode 100644
index 0000000..02649cd
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/apll.txt
@@ -0,0 +1,29 @@
+Binding for Texas Instruments APLL clock.
+
+This binding uses the common clock binding[1]. It assumes a
+register-mapped APLL with usually two selectable input clocks
+(reference clock and bypass clock), with analog phase locked
+loop logic for multiplying the input clock to a desired output
+clock. This clock also typically supports different operation
+modes (locked, low power stop etc.) APLL mostly behaves like
+a subtype of a DPLL [2], although a simplified one at that.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/clock/ti/dpll.txt
+
+Required properties:
+- compatible : shall be "ti,dra7-apll-clock"
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : link phandles of parent clocks (clk-ref and clk-bypass)
+- reg : address and length of the register set for controlling the APLL.
+ It contains the information of registers in the following order:
+ "control" - contains the control register base address
+ "idlest" - contains the idlest register base address
+
+Examples:
+ apll_pcie_ck: apll_pcie_ck@4a008200 {
+ #clock-cells = <0>;
+ clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
+ reg = <0x4a00821c 0x4>, <0x4a008220 0x4>;
+ compatible = "ti,dra7-apll-clock";
+ };
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 9d785e5..dba8b3e 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,7 +1,7 @@
ifneq ($(CONFIG_OF),)
obj-y += clk.o dpll.o autoidle.o divider.o \
fixed-factor.o gate.o clockdomain.o \
- mux-gate.o mux.o
+ mux-gate.o mux.o apll.o
obj-$(CONFIG_ARCH_OMAP4) += clk-44xx.o
obj-$(CONFIG_SOC_OMAP5) += clk-54xx.o
endif
diff --git a/drivers/clk/ti/apll.c b/drivers/clk/ti/apll.c
new file mode 100644
index 0000000..d9803b2
--- /dev/null
+++ b/drivers/clk/ti/apll.c
@@ -0,0 +1,207 @@
+/*
+ * OMAP APLL clock support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * J Keerthy <j-keerthy-l0cyMroinI0@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/string.h>
+#include <linux/log2.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk/ti.h>
+#include <linux/delay.h>
+
+#define APLL_FORCE_LOCK 0x1
+#define APLL_AUTO_IDLE 0x2
+#define MAX_APLL_WAIT_TRIES 1000000
+
+static int dra7_apll_enable(struct clk_hw *hw)
+{
+ struct clk_hw_omap *clk = to_clk_hw_omap(hw);
+ int r = 0, i = 0;
+ struct dpll_data *ad;
+ const char *clk_name;
+ u8 state = 1;
+ u32 v;
+
+ ad = clk->dpll_data;
+ if (!ad)
+ return -EINVAL;
+
+ clk_name = __clk_get_name(clk->hw.clk);
+
+ state <<= __ffs(ad->idlest_mask);
+
+ /* Check is already locked */
+ if ((readl(ad->idlest_reg) & ad->idlest_mask) == state)
+ return r;
+
+ v = readl(ad->control_reg);
+ v &= ~ad->enable_mask;
+ v |= APLL_FORCE_LOCK << __ffs(ad->enable_mask);
+ writel(v, ad->control_reg);
+
+ state <<= __ffs(ad->idlest_mask);
+
+ while (((readl(ad->idlest_reg) & ad->idlest_mask) != state) &&
+ i < MAX_APLL_WAIT_TRIES) {
+ i++;
+ udelay(1);
+ }
+
+ if (i == MAX_APLL_WAIT_TRIES) {
+ pr_warn("clock: %s failed transition to '%s'\n",
+ clk_name, (state) ? "locked" : "bypassed");
+ } else {
+ pr_debug("clock: %s transition to '%s' in %d loops\n",
+ clk_name, (state) ? "locked" : "bypassed", i);
+
+ r = 0;
+ }
+
+ return r;
+}
+
+static void dra7_apll_disable(struct clk_hw *hw)
+{
+ struct clk_hw_omap *clk = to_clk_hw_omap(hw);
+ struct dpll_data *ad;
+ u8 state = 1;
+ u32 v;
+
+ ad = clk->dpll_data;
+
+ state <<= __ffs(ad->idlest_mask);
+
+ v = readl(ad->control_reg);
+ v &= ~ad->enable_mask;
+ v |= APLL_AUTO_IDLE << __ffs(ad->enable_mask);
+ writel(v, ad->control_reg);
+}
+
+static u8 dra7_init_apll_parent(struct clk_hw *hw)
+{
+ return 0;
+}
+
+static const struct clk_ops apll_ck_ops = {
+ .enable = &dra7_apll_enable,
+ .disable = &dra7_apll_disable,
+ .get_parent = &dra7_init_apll_parent,
+};
+
+static struct clk *omap_clk_register_apll(struct device *dev, const char *name,
+ const char **parent_names, int num_parents, unsigned long flags,
+ struct dpll_data *dpll_data, const char *clkdm_name,
+ const struct clk_ops *ops)
+{
+ struct clk *clk;
+ struct clk_init_data init = { NULL };
+ struct clk_hw_omap *clk_hw;
+
+ clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
+ if (!clk_hw) {
+ pr_err("%s: could not allocate clk_hw_omap\n", __func__);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ clk_hw->dpll_data = dpll_data;
+ clk_hw->hw.init = &init;
+
+ init.name = name;
+ init.ops = ops;
+ init.flags = flags;
+ init.parent_names = parent_names;
+ init.num_parents = num_parents;
+
+ /* register the clock */
+ clk = clk_register(dev, &clk_hw->hw);
+
+ return clk;
+}
+
+static void __init of_dra7_apll_setup(struct device_node *node)
+{
+ const struct clk_ops *ops;
+ struct clk *clk;
+ const char *clk_name = node->name;
+ int num_parents;
+ const char **parent_names = NULL;
+ u8 apll_flags = 0;
+ struct dpll_data *ad;
+ u32 idlest_mask = 0x1;
+ u32 autoidle_mask = 0x3;
+ int i;
+
+ ops = &apll_ck_ops;
+ ad = kzalloc(sizeof(*ad), GFP_KERNEL);
+ if (!ad) {
+ pr_err("%s: could not allocate dpll_data\n", __func__);
+ return;
+ }
+
+ of_property_read_string(node, "clock-output-names", &clk_name);
+
+ num_parents = of_clk_get_parent_count(node);
+ if (num_parents < 1) {
+ pr_err("%s: omap dpll %s must have parent(s)\n",
+ __func__, node->name);
+ goto cleanup;
+ }
+
+ parent_names = kzalloc(sizeof(char *) * num_parents, GFP_KERNEL);
+
+ for (i = 0; i < num_parents; i++)
+ parent_names[i] = of_clk_get_parent_name(node, i);
+
+ ad->clk_ref = of_clk_get(node, 0);
+ ad->clk_bypass = of_clk_get(node, 1);
+
+ if (IS_ERR(ad->clk_ref)) {
+ pr_err("%s: ti,clk-ref for %s not found\n", __func__,
+ clk_name);
+ goto cleanup;
+ }
+
+ if (IS_ERR(ad->clk_bypass)) {
+ pr_err("%s: ti,clk-bypass for %s not found\n", __func__,
+ clk_name);
+ goto cleanup;
+ }
+
+ ad->control_reg = of_iomap(node, 0);
+ ad->idlest_reg = of_iomap(node, 1);
+
+ ad->idlest_mask = idlest_mask;
+ ad->enable_mask = autoidle_mask;
+
+ clk = omap_clk_register_apll(NULL, clk_name, parent_names,
+ num_parents, apll_flags, ad,
+ NULL, ops);
+
+ if (!IS_ERR(clk))
+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
+ return;
+
+cleanup:
+ kfree(parent_names);
+ kfree(ad);
+ return;
+}
+CLK_OF_DECLARE(dra7_apll_clock, "ti,dra7-apll-clock", of_dra7_apll_setup);
--
1.7.9.5
--
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^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 20/36] CLK: TI: DRA7: Add APLL support
@ 2013-09-25 8:48 ` Tero Kristo
0 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-arm-kernel
From: Keerthy <j-keerthy@ti.com>
The patch adds support for DRA7 PCIe APLL. The APLL
sources the optional functional clocks for PCIe module.
APLL stands for Analog PLL. This is different when comapred
with DPLL meaning Digital PLL, the phase detection is done
using an analog circuit.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
.../devicetree/bindings/clock/ti/apll.txt | 29 +++
drivers/clk/ti/Makefile | 2 +-
drivers/clk/ti/apll.c | 207 ++++++++++++++++++++
3 files changed, 237 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/clock/ti/apll.txt
create mode 100644 drivers/clk/ti/apll.c
diff --git a/Documentation/devicetree/bindings/clock/ti/apll.txt b/Documentation/devicetree/bindings/clock/ti/apll.txt
new file mode 100644
index 0000000..02649cd
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/apll.txt
@@ -0,0 +1,29 @@
+Binding for Texas Instruments APLL clock.
+
+This binding uses the common clock binding[1]. It assumes a
+register-mapped APLL with usually two selectable input clocks
+(reference clock and bypass clock), with analog phase locked
+loop logic for multiplying the input clock to a desired output
+clock. This clock also typically supports different operation
+modes (locked, low power stop etc.) APLL mostly behaves like
+a subtype of a DPLL [2], although a simplified one at that.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/clock/ti/dpll.txt
+
+Required properties:
+- compatible : shall be "ti,dra7-apll-clock"
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : link phandles of parent clocks (clk-ref and clk-bypass)
+- reg : address and length of the register set for controlling the APLL.
+ It contains the information of registers in the following order:
+ "control" - contains the control register base address
+ "idlest" - contains the idlest register base address
+
+Examples:
+ apll_pcie_ck: apll_pcie_ck at 4a008200 {
+ #clock-cells = <0>;
+ clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
+ reg = <0x4a00821c 0x4>, <0x4a008220 0x4>;
+ compatible = "ti,dra7-apll-clock";
+ };
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 9d785e5..dba8b3e 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,7 +1,7 @@
ifneq ($(CONFIG_OF),)
obj-y += clk.o dpll.o autoidle.o divider.o \
fixed-factor.o gate.o clockdomain.o \
- mux-gate.o mux.o
+ mux-gate.o mux.o apll.o
obj-$(CONFIG_ARCH_OMAP4) += clk-44xx.o
obj-$(CONFIG_SOC_OMAP5) += clk-54xx.o
endif
diff --git a/drivers/clk/ti/apll.c b/drivers/clk/ti/apll.c
new file mode 100644
index 0000000..d9803b2
--- /dev/null
+++ b/drivers/clk/ti/apll.c
@@ -0,0 +1,207 @@
+/*
+ * OMAP APLL clock support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * J Keerthy <j-keerthy@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/string.h>
+#include <linux/log2.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk/ti.h>
+#include <linux/delay.h>
+
+#define APLL_FORCE_LOCK 0x1
+#define APLL_AUTO_IDLE 0x2
+#define MAX_APLL_WAIT_TRIES 1000000
+
+static int dra7_apll_enable(struct clk_hw *hw)
+{
+ struct clk_hw_omap *clk = to_clk_hw_omap(hw);
+ int r = 0, i = 0;
+ struct dpll_data *ad;
+ const char *clk_name;
+ u8 state = 1;
+ u32 v;
+
+ ad = clk->dpll_data;
+ if (!ad)
+ return -EINVAL;
+
+ clk_name = __clk_get_name(clk->hw.clk);
+
+ state <<= __ffs(ad->idlest_mask);
+
+ /* Check is already locked */
+ if ((readl(ad->idlest_reg) & ad->idlest_mask) == state)
+ return r;
+
+ v = readl(ad->control_reg);
+ v &= ~ad->enable_mask;
+ v |= APLL_FORCE_LOCK << __ffs(ad->enable_mask);
+ writel(v, ad->control_reg);
+
+ state <<= __ffs(ad->idlest_mask);
+
+ while (((readl(ad->idlest_reg) & ad->idlest_mask) != state) &&
+ i < MAX_APLL_WAIT_TRIES) {
+ i++;
+ udelay(1);
+ }
+
+ if (i == MAX_APLL_WAIT_TRIES) {
+ pr_warn("clock: %s failed transition to '%s'\n",
+ clk_name, (state) ? "locked" : "bypassed");
+ } else {
+ pr_debug("clock: %s transition to '%s' in %d loops\n",
+ clk_name, (state) ? "locked" : "bypassed", i);
+
+ r = 0;
+ }
+
+ return r;
+}
+
+static void dra7_apll_disable(struct clk_hw *hw)
+{
+ struct clk_hw_omap *clk = to_clk_hw_omap(hw);
+ struct dpll_data *ad;
+ u8 state = 1;
+ u32 v;
+
+ ad = clk->dpll_data;
+
+ state <<= __ffs(ad->idlest_mask);
+
+ v = readl(ad->control_reg);
+ v &= ~ad->enable_mask;
+ v |= APLL_AUTO_IDLE << __ffs(ad->enable_mask);
+ writel(v, ad->control_reg);
+}
+
+static u8 dra7_init_apll_parent(struct clk_hw *hw)
+{
+ return 0;
+}
+
+static const struct clk_ops apll_ck_ops = {
+ .enable = &dra7_apll_enable,
+ .disable = &dra7_apll_disable,
+ .get_parent = &dra7_init_apll_parent,
+};
+
+static struct clk *omap_clk_register_apll(struct device *dev, const char *name,
+ const char **parent_names, int num_parents, unsigned long flags,
+ struct dpll_data *dpll_data, const char *clkdm_name,
+ const struct clk_ops *ops)
+{
+ struct clk *clk;
+ struct clk_init_data init = { NULL };
+ struct clk_hw_omap *clk_hw;
+
+ clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
+ if (!clk_hw) {
+ pr_err("%s: could not allocate clk_hw_omap\n", __func__);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ clk_hw->dpll_data = dpll_data;
+ clk_hw->hw.init = &init;
+
+ init.name = name;
+ init.ops = ops;
+ init.flags = flags;
+ init.parent_names = parent_names;
+ init.num_parents = num_parents;
+
+ /* register the clock */
+ clk = clk_register(dev, &clk_hw->hw);
+
+ return clk;
+}
+
+static void __init of_dra7_apll_setup(struct device_node *node)
+{
+ const struct clk_ops *ops;
+ struct clk *clk;
+ const char *clk_name = node->name;
+ int num_parents;
+ const char **parent_names = NULL;
+ u8 apll_flags = 0;
+ struct dpll_data *ad;
+ u32 idlest_mask = 0x1;
+ u32 autoidle_mask = 0x3;
+ int i;
+
+ ops = &apll_ck_ops;
+ ad = kzalloc(sizeof(*ad), GFP_KERNEL);
+ if (!ad) {
+ pr_err("%s: could not allocate dpll_data\n", __func__);
+ return;
+ }
+
+ of_property_read_string(node, "clock-output-names", &clk_name);
+
+ num_parents = of_clk_get_parent_count(node);
+ if (num_parents < 1) {
+ pr_err("%s: omap dpll %s must have parent(s)\n",
+ __func__, node->name);
+ goto cleanup;
+ }
+
+ parent_names = kzalloc(sizeof(char *) * num_parents, GFP_KERNEL);
+
+ for (i = 0; i < num_parents; i++)
+ parent_names[i] = of_clk_get_parent_name(node, i);
+
+ ad->clk_ref = of_clk_get(node, 0);
+ ad->clk_bypass = of_clk_get(node, 1);
+
+ if (IS_ERR(ad->clk_ref)) {
+ pr_err("%s: ti,clk-ref for %s not found\n", __func__,
+ clk_name);
+ goto cleanup;
+ }
+
+ if (IS_ERR(ad->clk_bypass)) {
+ pr_err("%s: ti,clk-bypass for %s not found\n", __func__,
+ clk_name);
+ goto cleanup;
+ }
+
+ ad->control_reg = of_iomap(node, 0);
+ ad->idlest_reg = of_iomap(node, 1);
+
+ ad->idlest_mask = idlest_mask;
+ ad->enable_mask = autoidle_mask;
+
+ clk = omap_clk_register_apll(NULL, clk_name, parent_names,
+ num_parents, apll_flags, ad,
+ NULL, ops);
+
+ if (!IS_ERR(clk))
+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
+ return;
+
+cleanup:
+ kfree(parent_names);
+ kfree(ad);
+ return;
+}
+CLK_OF_DECLARE(dra7_apll_clock, "ti,dra7-apll-clock", of_dra7_apll_setup);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 21/36] CLK: TI: add dra7 clock init file
2013-09-25 8:48 ` Tero Kristo
@ 2013-09-25 8:48 ` Tero Kristo
-1 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-omap-u79uwXL29TY76Z2rM5mHXA, paul-DWxLp4Yu+b8AvxtiuMwx3w,
tony-4v6yS6AI5VpBDgjK7y7TUQ, nm-l0cyMroinI0, rnayak-l0cyMroinI0,
bcousson-rdvid1DuHRBWk0Htik3J/w,
mturquette-QSEj5FYQhm4dnm+yROfE0A
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
clk-7xx.c now contains the clock init functionality for dra7, including
DT clock registration and adding of static clkdev entries.
Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
drivers/clk/ti/Makefile | 1 +
drivers/clk/ti/clk-7xx.c | 334 ++++++++++++++++++++++++++++++++++++++++++++++
include/linux/clk/ti.h | 1 +
3 files changed, 336 insertions(+)
create mode 100644 drivers/clk/ti/clk-7xx.c
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index dba8b3e..1a83c3c 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -4,4 +4,5 @@ obj-y += clk.o dpll.o autoidle.o divider.o \
mux-gate.o mux.o apll.o
obj-$(CONFIG_ARCH_OMAP4) += clk-44xx.o
obj-$(CONFIG_SOC_OMAP5) += clk-54xx.o
+obj-$(CONFIG_SOC_DRA7XX) += clk-7xx.o
endif
diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c
new file mode 100644
index 0000000..e0e65f1
--- /dev/null
+++ b/drivers/clk/ti/clk-7xx.c
@@ -0,0 +1,334 @@
+/*
+ * DRA7 Clock init
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo (t-kristo-l0cyMroinI0@public.gmane.org)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/clk-private.h>
+#include <linux/clkdev.h>
+#include <linux/clk/ti.h>
+
+#define DRA7_DPLL_ABE_DEFFREQ 361267200
+#define DRA7_DPLL_GMAC_DEFFREQ 1000000000
+
+
+static struct ti_dt_clk dra7xx_clks[] = {
+ DT_CLK(NULL, "atl_clkin0_ck", "atl_clkin0_ck"),
+ DT_CLK(NULL, "atl_clkin1_ck", "atl_clkin1_ck"),
+ DT_CLK(NULL, "atl_clkin2_ck", "atl_clkin2_ck"),
+ DT_CLK(NULL, "atlclkin3_ck", "atlclkin3_ck"),
+ DT_CLK(NULL, "hdmi_clkin_ck", "hdmi_clkin_ck"),
+ DT_CLK(NULL, "mlb_clkin_ck", "mlb_clkin_ck"),
+ DT_CLK(NULL, "mlbp_clkin_ck", "mlbp_clkin_ck"),
+ DT_CLK(NULL, "pciesref_acs_clk_ck", "pciesref_acs_clk_ck"),
+ DT_CLK(NULL, "ref_clkin0_ck", "ref_clkin0_ck"),
+ DT_CLK(NULL, "ref_clkin1_ck", "ref_clkin1_ck"),
+ DT_CLK(NULL, "ref_clkin2_ck", "ref_clkin2_ck"),
+ DT_CLK(NULL, "ref_clkin3_ck", "ref_clkin3_ck"),
+ DT_CLK(NULL, "rmii_clk_ck", "rmii_clk_ck"),
+ DT_CLK(NULL, "sdvenc_clkin_ck", "sdvenc_clkin_ck"),
+ DT_CLK(NULL, "secure_32k_clk_src_ck", "secure_32k_clk_src_ck"),
+ DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"),
+ DT_CLK(NULL, "virt_12000000_ck", "virt_12000000_ck"),
+ DT_CLK(NULL, "virt_13000000_ck", "virt_13000000_ck"),
+ DT_CLK(NULL, "virt_16800000_ck", "virt_16800000_ck"),
+ DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
+ DT_CLK(NULL, "virt_20000000_ck", "virt_20000000_ck"),
+ DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
+ DT_CLK(NULL, "virt_27000000_ck", "virt_27000000_ck"),
+ DT_CLK(NULL, "virt_38400000_ck", "virt_38400000_ck"),
+ DT_CLK(NULL, "sys_clkin1", "sys_clkin1"),
+ DT_CLK(NULL, "sys_clkin2", "sys_clkin2"),
+ DT_CLK(NULL, "usb_otg_clkin_ck", "usb_otg_clkin_ck"),
+ DT_CLK(NULL, "video1_clkin_ck", "video1_clkin_ck"),
+ DT_CLK(NULL, "video1_m2_clkin_ck", "video1_m2_clkin_ck"),
+ DT_CLK(NULL, "video2_clkin_ck", "video2_clkin_ck"),
+ DT_CLK(NULL, "video2_m2_clkin_ck", "video2_m2_clkin_ck"),
+ DT_CLK(NULL, "abe_dpll_sys_clk_mux", "abe_dpll_sys_clk_mux"),
+ DT_CLK(NULL, "abe_dpll_bypass_clk_mux", "abe_dpll_bypass_clk_mux"),
+ DT_CLK(NULL, "abe_dpll_clk_mux", "abe_dpll_clk_mux"),
+ DT_CLK(NULL, "dpll_abe_ck", "dpll_abe_ck"),
+ DT_CLK(NULL, "dpll_abe_x2_ck", "dpll_abe_x2_ck"),
+ DT_CLK(NULL, "dpll_abe_m2x2_ck", "dpll_abe_m2x2_ck"),
+ DT_CLK(NULL, "abe_24m_fclk", "abe_24m_fclk"),
+ DT_CLK(NULL, "abe_clk", "abe_clk"),
+ DT_CLK(NULL, "aess_fclk", "aess_fclk"),
+ DT_CLK(NULL, "abe_giclk_div", "abe_giclk_div"),
+ DT_CLK(NULL, "abe_lp_clk_div", "abe_lp_clk_div"),
+ DT_CLK(NULL, "abe_sys_clk_div", "abe_sys_clk_div"),
+ DT_CLK(NULL, "adc_gfclk_mux", "adc_gfclk_mux"),
+ DT_CLK(NULL, "dpll_pcie_ref_ck", "dpll_pcie_ref_ck"),
+ DT_CLK(NULL, "dpll_pcie_ref_m2ldo_ck", "dpll_pcie_ref_m2ldo_ck"),
+ DT_CLK(NULL, "apll_pcie_ck", "apll_pcie_ck"),
+ DT_CLK(NULL, "apll_pcie_clkvcoldo", "apll_pcie_clkvcoldo"),
+ DT_CLK(NULL, "apll_pcie_clkvcoldo_div", "apll_pcie_clkvcoldo_div"),
+ DT_CLK(NULL, "apll_pcie_m2_ck", "apll_pcie_m2_ck"),
+ DT_CLK(NULL, "sys_clk1_dclk_div", "sys_clk1_dclk_div"),
+ DT_CLK(NULL, "sys_clk2_dclk_div", "sys_clk2_dclk_div"),
+ DT_CLK(NULL, "dpll_abe_m2_ck", "dpll_abe_m2_ck"),
+ DT_CLK(NULL, "per_abe_x1_dclk_div", "per_abe_x1_dclk_div"),
+ DT_CLK(NULL, "dpll_abe_m3x2_ck", "dpll_abe_m3x2_ck"),
+ DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
+ DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
+ DT_CLK(NULL, "dpll_core_h12x2_ck", "dpll_core_h12x2_ck"),
+ DT_CLK(NULL, "mpu_dpll_hs_clk_div", "mpu_dpll_hs_clk_div"),
+ DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"),
+ DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"),
+ DT_CLK(NULL, "mpu_dclk_div", "mpu_dclk_div"),
+ DT_CLK(NULL, "dsp_dpll_hs_clk_div", "dsp_dpll_hs_clk_div"),
+ DT_CLK(NULL, "dpll_dsp_ck", "dpll_dsp_ck"),
+ DT_CLK(NULL, "dpll_dsp_m2_ck", "dpll_dsp_m2_ck"),
+ DT_CLK(NULL, "dsp_gclk_div", "dsp_gclk_div"),
+ DT_CLK(NULL, "iva_dpll_hs_clk_div", "iva_dpll_hs_clk_div"),
+ DT_CLK(NULL, "dpll_iva_ck", "dpll_iva_ck"),
+ DT_CLK(NULL, "dpll_iva_m2_ck", "dpll_iva_m2_ck"),
+ DT_CLK(NULL, "iva_dclk", "iva_dclk"),
+ DT_CLK(NULL, "dpll_gpu_ck", "dpll_gpu_ck"),
+ DT_CLK(NULL, "dpll_gpu_m2_ck", "dpll_gpu_m2_ck"),
+ DT_CLK(NULL, "gpu_dclk", "gpu_dclk"),
+ DT_CLK(NULL, "dpll_core_m2_ck", "dpll_core_m2_ck"),
+ DT_CLK(NULL, "core_dpll_out_dclk_div", "core_dpll_out_dclk_div"),
+ DT_CLK(NULL, "dpll_ddr_ck", "dpll_ddr_ck"),
+ DT_CLK(NULL, "dpll_ddr_m2_ck", "dpll_ddr_m2_ck"),
+ DT_CLK(NULL, "emif_phy_dclk_div", "emif_phy_dclk_div"),
+ DT_CLK(NULL, "dpll_gmac_ck", "dpll_gmac_ck"),
+ DT_CLK(NULL, "dpll_gmac_m2_ck", "dpll_gmac_m2_ck"),
+ DT_CLK(NULL, "gmac_250m_dclk_div", "gmac_250m_dclk_div"),
+ DT_CLK(NULL, "video2_dclk_div", "video2_dclk_div"),
+ DT_CLK(NULL, "video1_dclk_div", "video1_dclk_div"),
+ DT_CLK(NULL, "hdmi_dclk_div", "hdmi_dclk_div"),
+ DT_CLK(NULL, "per_dpll_hs_clk_div", "per_dpll_hs_clk_div"),
+ DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"),
+ DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"),
+ DT_CLK(NULL, "func_96m_aon_dclk_div", "func_96m_aon_dclk_div"),
+ DT_CLK(NULL, "usb_dpll_hs_clk_div", "usb_dpll_hs_clk_div"),
+ DT_CLK(NULL, "dpll_usb_ck", "dpll_usb_ck"),
+ DT_CLK(NULL, "dpll_usb_m2_ck", "dpll_usb_m2_ck"),
+ DT_CLK(NULL, "l3init_480m_dclk_div", "l3init_480m_dclk_div"),
+ DT_CLK(NULL, "usb_otg_dclk_div", "usb_otg_dclk_div"),
+ DT_CLK(NULL, "sata_dclk_div", "sata_dclk_div"),
+ DT_CLK(NULL, "dpll_pcie_ref_m2_ck", "dpll_pcie_ref_m2_ck"),
+ DT_CLK(NULL, "pcie2_dclk_div", "pcie2_dclk_div"),
+ DT_CLK(NULL, "pcie_dclk_div", "pcie_dclk_div"),
+ DT_CLK(NULL, "emu_dclk_div", "emu_dclk_div"),
+ DT_CLK(NULL, "secure_32k_dclk_div", "secure_32k_dclk_div"),
+ DT_CLK(NULL, "eve_dpll_hs_clk_div", "eve_dpll_hs_clk_div"),
+ DT_CLK(NULL, "dpll_eve_ck", "dpll_eve_ck"),
+ DT_CLK(NULL, "dpll_eve_m2_ck", "dpll_eve_m2_ck"),
+ DT_CLK(NULL, "eve_dclk_div", "eve_dclk_div"),
+ DT_CLK(NULL, "clkoutmux0_clk_mux", "clkoutmux0_clk_mux"),
+ DT_CLK(NULL, "clkoutmux1_clk_mux", "clkoutmux1_clk_mux"),
+ DT_CLK(NULL, "clkoutmux2_clk_mux", "clkoutmux2_clk_mux"),
+ DT_CLK(NULL, "custefuse_sys_gfclk_div", "custefuse_sys_gfclk_div"),
+ DT_CLK(NULL, "dpll_core_h13x2_ck", "dpll_core_h13x2_ck"),
+ DT_CLK(NULL, "dpll_core_h14x2_ck", "dpll_core_h14x2_ck"),
+ DT_CLK(NULL, "dpll_core_h22x2_ck", "dpll_core_h22x2_ck"),
+ DT_CLK(NULL, "dpll_core_h23x2_ck", "dpll_core_h23x2_ck"),
+ DT_CLK(NULL, "dpll_core_h24x2_ck", "dpll_core_h24x2_ck"),
+ DT_CLK(NULL, "dpll_ddr_x2_ck", "dpll_ddr_x2_ck"),
+ DT_CLK(NULL, "dpll_ddr_h11x2_ck", "dpll_ddr_h11x2_ck"),
+ DT_CLK(NULL, "dpll_dsp_x2_ck", "dpll_dsp_x2_ck"),
+ DT_CLK(NULL, "dpll_dsp_m3x2_ck", "dpll_dsp_m3x2_ck"),
+ DT_CLK(NULL, "dpll_gmac_x2_ck", "dpll_gmac_x2_ck"),
+ DT_CLK(NULL, "dpll_gmac_h11x2_ck", "dpll_gmac_h11x2_ck"),
+ DT_CLK(NULL, "dpll_gmac_h12x2_ck", "dpll_gmac_h12x2_ck"),
+ DT_CLK(NULL, "dpll_gmac_h13x2_ck", "dpll_gmac_h13x2_ck"),
+ DT_CLK(NULL, "dpll_gmac_m3x2_ck", "dpll_gmac_m3x2_ck"),
+ DT_CLK(NULL, "dpll_per_x2_ck", "dpll_per_x2_ck"),
+ DT_CLK(NULL, "dpll_per_h11x2_ck", "dpll_per_h11x2_ck"),
+ DT_CLK(NULL, "dpll_per_h12x2_ck", "dpll_per_h12x2_ck"),
+ DT_CLK(NULL, "dpll_per_h13x2_ck", "dpll_per_h13x2_ck"),
+ DT_CLK(NULL, "dpll_per_h14x2_ck", "dpll_per_h14x2_ck"),
+ DT_CLK(NULL, "dpll_per_m2x2_ck", "dpll_per_m2x2_ck"),
+ DT_CLK(NULL, "dpll_usb_clkdcoldo", "dpll_usb_clkdcoldo"),
+ DT_CLK(NULL, "eve_clk", "eve_clk"),
+ DT_CLK(NULL, "func_128m_clk", "func_128m_clk"),
+ DT_CLK(NULL, "func_12m_fclk", "func_12m_fclk"),
+ DT_CLK(NULL, "func_24m_clk", "func_24m_clk"),
+ DT_CLK(NULL, "func_48m_fclk", "func_48m_fclk"),
+ DT_CLK(NULL, "func_96m_fclk", "func_96m_fclk"),
+ DT_CLK(NULL, "gmii_m_clk_div", "gmii_m_clk_div"),
+ DT_CLK(NULL, "hdmi_clk2_div", "hdmi_clk2_div"),
+ DT_CLK(NULL, "hdmi_div_clk", "hdmi_div_clk"),
+ DT_CLK(NULL, "hdmi_dpll_clk_mux", "hdmi_dpll_clk_mux"),
+ DT_CLK(NULL, "l3_iclk_div", "l3_iclk_div"),
+ DT_CLK(NULL, "l3init_60m_fclk", "l3init_60m_fclk"),
+ DT_CLK(NULL, "l4_root_clk_div", "l4_root_clk_div"),
+ DT_CLK(NULL, "mlb_clk", "mlb_clk"),
+ DT_CLK(NULL, "mlbp_clk", "mlbp_clk"),
+ DT_CLK(NULL, "per_abe_x1_gfclk2_div", "per_abe_x1_gfclk2_div"),
+ DT_CLK(NULL, "timer_sys_clk_div", "timer_sys_clk_div"),
+ DT_CLK(NULL, "video1_clk2_div", "video1_clk2_div"),
+ DT_CLK(NULL, "video1_div_clk", "video1_div_clk"),
+ DT_CLK(NULL, "video1_dpll_clk_mux", "video1_dpll_clk_mux"),
+ DT_CLK(NULL, "video2_clk2_div", "video2_clk2_div"),
+ DT_CLK(NULL, "video2_div_clk", "video2_div_clk"),
+ DT_CLK(NULL, "video2_dpll_clk_mux", "video2_dpll_clk_mux"),
+ DT_CLK(NULL, "wkupaon_iclk_mux", "wkupaon_iclk_mux"),
+ DT_CLK(NULL, "dss_32khz_clk", "dss_32khz_clk"),
+ DT_CLK(NULL, "dss_48mhz_clk", "dss_48mhz_clk"),
+ DT_CLK(NULL, "dss_dss_clk", "dss_dss_clk"),
+ DT_CLK(NULL, "dss_hdmi_clk", "dss_hdmi_clk"),
+ DT_CLK(NULL, "dss_video1_clk", "dss_video1_clk"),
+ DT_CLK(NULL, "dss_video2_clk", "dss_video2_clk"),
+ DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
+ DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"),
+ DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"),
+ DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"),
+ DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"),
+ DT_CLK(NULL, "gpio6_dbclk", "gpio6_dbclk"),
+ DT_CLK(NULL, "gpio7_dbclk", "gpio7_dbclk"),
+ DT_CLK(NULL, "gpio8_dbclk", "gpio8_dbclk"),
+ DT_CLK(NULL, "mmc1_clk32k", "mmc1_clk32k"),
+ DT_CLK(NULL, "mmc2_clk32k", "mmc2_clk32k"),
+ DT_CLK(NULL, "mmc3_clk32k", "mmc3_clk32k"),
+ DT_CLK(NULL, "mmc4_clk32k", "mmc4_clk32k"),
+ DT_CLK(NULL, "sata_ref_clk", "sata_ref_clk"),
+ DT_CLK(NULL, "usb_otg_ss1_refclk960m", "usb_otg_ss1_refclk960m"),
+ DT_CLK(NULL, "usb_otg_ss2_refclk960m", "usb_otg_ss2_refclk960m"),
+ DT_CLK(NULL, "usb_phy1_always_on_clk32k", "usb_phy1_always_on_clk32k"),
+ DT_CLK(NULL, "usb_phy2_always_on_clk32k", "usb_phy2_always_on_clk32k"),
+ DT_CLK(NULL, "usb_phy3_always_on_clk32k", "usb_phy3_always_on_clk32k"),
+ DT_CLK(NULL, "atl_dpll_clk_mux", "atl_dpll_clk_mux"),
+ DT_CLK(NULL, "atl_gfclk_mux", "atl_gfclk_mux"),
+ DT_CLK(NULL, "dcan1_sys_clk_mux", "dcan1_sys_clk_mux"),
+ DT_CLK(NULL, "gmac_gmii_ref_clk_div", "gmac_gmii_ref_clk_div"),
+ DT_CLK(NULL, "gmac_rft_clk_mux", "gmac_rft_clk_mux"),
+ DT_CLK(NULL, "gpu_core_gclk_mux", "gpu_core_gclk_mux"),
+ DT_CLK(NULL, "gpu_hyd_gclk_mux", "gpu_hyd_gclk_mux"),
+ DT_CLK(NULL, "ipu1_gfclk_mux", "ipu1_gfclk_mux"),
+ DT_CLK(NULL, "l3instr_ts_gclk_div", "l3instr_ts_gclk_div"),
+ DT_CLK(NULL, "mcasp1_ahclkr_mux", "mcasp1_ahclkr_mux"),
+ DT_CLK(NULL, "mcasp1_ahclkx_mux", "mcasp1_ahclkx_mux"),
+ DT_CLK(NULL, "mcasp1_aux_gfclk_mux", "mcasp1_aux_gfclk_mux"),
+ DT_CLK(NULL, "mcasp2_ahclkr_mux", "mcasp2_ahclkr_mux"),
+ DT_CLK(NULL, "mcasp2_ahclkx_mux", "mcasp2_ahclkx_mux"),
+ DT_CLK(NULL, "mcasp2_aux_gfclk_mux", "mcasp2_aux_gfclk_mux"),
+ DT_CLK(NULL, "mcasp3_ahclkx_mux", "mcasp3_ahclkx_mux"),
+ DT_CLK(NULL, "mcasp3_aux_gfclk_mux", "mcasp3_aux_gfclk_mux"),
+ DT_CLK(NULL, "mcasp4_ahclkx_mux", "mcasp4_ahclkx_mux"),
+ DT_CLK(NULL, "mcasp4_aux_gfclk_mux", "mcasp4_aux_gfclk_mux"),
+ DT_CLK(NULL, "mcasp5_ahclkx_mux", "mcasp5_ahclkx_mux"),
+ DT_CLK(NULL, "mcasp5_aux_gfclk_mux", "mcasp5_aux_gfclk_mux"),
+ DT_CLK(NULL, "mcasp6_ahclkx_mux", "mcasp6_ahclkx_mux"),
+ DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "mcasp6_aux_gfclk_mux"),
+ DT_CLK(NULL, "mcasp7_ahclkx_mux", "mcasp7_ahclkx_mux"),
+ DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "mcasp7_aux_gfclk_mux"),
+ DT_CLK(NULL, "mcasp8_ahclk_mux", "mcasp8_ahclk_mux"),
+ DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "mcasp8_aux_gfclk_mux"),
+ DT_CLK(NULL, "mmc1_fclk_mux", "mmc1_fclk_mux"),
+ DT_CLK(NULL, "mmc1_fclk_div", "mmc1_fclk_div"),
+ DT_CLK(NULL, "mmc2_fclk_mux", "mmc2_fclk_mux"),
+ DT_CLK(NULL, "mmc2_fclk_div", "mmc2_fclk_div"),
+ DT_CLK(NULL, "mmc3_gfclk_mux", "mmc3_gfclk_mux"),
+ DT_CLK(NULL, "mmc3_gfclk_div", "mmc3_gfclk_div"),
+ DT_CLK(NULL, "mmc4_gfclk_mux", "mmc4_gfclk_mux"),
+ DT_CLK(NULL, "mmc4_gfclk_div", "mmc4_gfclk_div"),
+ DT_CLK(NULL, "qspi_gfclk_mux", "qspi_gfclk_mux"),
+ DT_CLK(NULL, "qspi_gfclk_div", "qspi_gfclk_div"),
+ DT_CLK(NULL, "timer10_gfclk_mux", "timer10_gfclk_mux"),
+ DT_CLK(NULL, "timer11_gfclk_mux", "timer11_gfclk_mux"),
+ DT_CLK(NULL, "timer13_gfclk_mux", "timer13_gfclk_mux"),
+ DT_CLK(NULL, "timer14_gfclk_mux", "timer14_gfclk_mux"),
+ DT_CLK(NULL, "timer15_gfclk_mux", "timer15_gfclk_mux"),
+ DT_CLK(NULL, "timer16_gfclk_mux", "timer16_gfclk_mux"),
+ DT_CLK(NULL, "timer1_gfclk_mux", "timer1_gfclk_mux"),
+ DT_CLK(NULL, "timer2_gfclk_mux", "timer2_gfclk_mux"),
+ DT_CLK(NULL, "timer3_gfclk_mux", "timer3_gfclk_mux"),
+ DT_CLK(NULL, "timer4_gfclk_mux", "timer4_gfclk_mux"),
+ DT_CLK(NULL, "timer5_gfclk_mux", "timer5_gfclk_mux"),
+ DT_CLK(NULL, "timer6_gfclk_mux", "timer6_gfclk_mux"),
+ DT_CLK(NULL, "timer7_gfclk_mux", "timer7_gfclk_mux"),
+ DT_CLK(NULL, "timer8_gfclk_mux", "timer8_gfclk_mux"),
+ DT_CLK(NULL, "timer9_gfclk_mux", "timer9_gfclk_mux"),
+ DT_CLK(NULL, "uart10_gfclk_mux", "uart10_gfclk_mux"),
+ DT_CLK(NULL, "uart1_gfclk_mux", "uart1_gfclk_mux"),
+ DT_CLK(NULL, "uart2_gfclk_mux", "uart2_gfclk_mux"),
+ DT_CLK(NULL, "uart3_gfclk_mux", "uart3_gfclk_mux"),
+ DT_CLK(NULL, "uart4_gfclk_mux", "uart4_gfclk_mux"),
+ DT_CLK(NULL, "uart5_gfclk_mux", "uart5_gfclk_mux"),
+ DT_CLK(NULL, "uart6_gfclk_mux", "uart6_gfclk_mux"),
+ DT_CLK(NULL, "uart7_gfclk_mux", "uart7_gfclk_mux"),
+ DT_CLK(NULL, "uart8_gfclk_mux", "uart8_gfclk_mux"),
+ DT_CLK(NULL, "uart9_gfclk_mux", "uart9_gfclk_mux"),
+ DT_CLK(NULL, "vip1_gclk_mux", "vip1_gclk_mux"),
+ DT_CLK(NULL, "vip2_gclk_mux", "vip2_gclk_mux"),
+ DT_CLK(NULL, "vip3_gclk_mux", "vip3_gclk_mux"),
+ DT_CLK(NULL, "gpmc_ck", "dummy_ck"),
+ DT_CLK("omap_i2c.1", "ick", "dummy_ck"),
+ DT_CLK("omap_i2c.2", "ick", "dummy_ck"),
+ DT_CLK("omap_i2c.3", "ick", "dummy_ck"),
+ DT_CLK("omap_i2c.4", "ick", "dummy_ck"),
+ DT_CLK(NULL, "mailboxes_ick", "dummy_ck"),
+ DT_CLK("omap_hsmmc.0", "ick", "dummy_ck"),
+ DT_CLK("omap_hsmmc.1", "ick", "dummy_ck"),
+ DT_CLK("omap_hsmmc.2", "ick", "dummy_ck"),
+ DT_CLK("omap_hsmmc.3", "ick", "dummy_ck"),
+ DT_CLK("omap_hsmmc.4", "ick", "dummy_ck"),
+ DT_CLK("omap-mcbsp.1", "ick", "dummy_ck"),
+ DT_CLK("omap-mcbsp.2", "ick", "dummy_ck"),
+ DT_CLK("omap-mcbsp.3", "ick", "dummy_ck"),
+ DT_CLK("omap-mcbsp.4", "ick", "dummy_ck"),
+ DT_CLK("omap2_mcspi.1", "ick", "dummy_ck"),
+ DT_CLK("omap2_mcspi.2", "ick", "dummy_ck"),
+ DT_CLK("omap2_mcspi.3", "ick", "dummy_ck"),
+ DT_CLK("omap2_mcspi.4", "ick", "dummy_ck"),
+ DT_CLK(NULL, "uart1_ick", "dummy_ck"),
+ DT_CLK(NULL, "uart2_ick", "dummy_ck"),
+ DT_CLK(NULL, "uart3_ick", "dummy_ck"),
+ DT_CLK(NULL, "uart4_ick", "dummy_ck"),
+ DT_CLK("usbhs_omap", "usbhost_ick", "dummy_ck"),
+ DT_CLK("usbhs_omap", "usbtll_fck", "dummy_ck"),
+ DT_CLK("omap_wdt", "ick", "dummy_ck"),
+ DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
+ DT_CLK("4ae18000.timer", "timer_sys_ck", "sys_clkin2"),
+ DT_CLK("48032000.timer", "timer_sys_ck", "sys_clkin2"),
+ DT_CLK("48034000.timer", "timer_sys_ck", "sys_clkin2"),
+ DT_CLK("48036000.timer", "timer_sys_ck", "sys_clkin2"),
+ DT_CLK("4803e000.timer", "timer_sys_ck", "sys_clkin2"),
+ DT_CLK("48086000.timer", "timer_sys_ck", "sys_clkin2"),
+ DT_CLK("48088000.timer", "timer_sys_ck", "sys_clkin2"),
+ DT_CLK("48820000.timer", "timer_sys_ck", "timer_sys_clk_div"),
+ DT_CLK("48822000.timer", "timer_sys_ck", "timer_sys_clk_div"),
+ DT_CLK("48824000.timer", "timer_sys_ck", "timer_sys_clk_div"),
+ DT_CLK("48826000.timer", "timer_sys_ck", "timer_sys_clk_div"),
+ DT_CLK(NULL, "sys_clkin", "sys_clkin1"),
+ { .node_name = NULL },
+};
+
+int __init dra7xx_clk_init(void)
+{
+ int rc;
+ struct clk *abe_dpll_mux, *sys_clkin2, *dpll_ck;
+
+ of_clk_init(NULL);
+
+ ti_dt_clocks_register(dra7xx_clks);
+
+ omap2_clk_disable_autoidle_all();
+
+ abe_dpll_mux = clk_get_sys(NULL, "abe_dpll_sys_clk_mux");
+ sys_clkin2 = clk_get_sys(NULL, "sys_clkin2");
+ dpll_ck = clk_get_sys(NULL, "dpll_abe_ck");
+
+ rc = clk_set_parent(abe_dpll_mux, sys_clkin2);
+ if (!rc)
+ rc = clk_set_rate(dpll_ck, DRA7_DPLL_ABE_DEFFREQ);
+ if (rc)
+ pr_err("%s: failed to configure ABE DPLL!\n", __func__);
+
+ dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck");
+ rc = clk_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ);
+ if (rc)
+ pr_err("%s: failed to configure GMAC DPLL!\n", __func__);
+
+ return rc;
+}
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 9a29e17..1b2dc51 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -221,6 +221,7 @@ struct clk_div_table *ti_clk_get_div_table(struct device_node *node);
int omap4xxx_clk_init(void);
int omap5xxx_clk_init(void);
+int dra7xx_clk_init(void);
#ifdef CONFIG_OF
void of_ti_clk_allow_autoidle_all(void);
--
1.7.9.5
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^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 21/36] CLK: TI: add dra7 clock init file
@ 2013-09-25 8:48 ` Tero Kristo
0 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-arm-kernel
clk-7xx.c now contains the clock init functionality for dra7, including
DT clock registration and adding of static clkdev entries.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
drivers/clk/ti/Makefile | 1 +
drivers/clk/ti/clk-7xx.c | 334 ++++++++++++++++++++++++++++++++++++++++++++++
include/linux/clk/ti.h | 1 +
3 files changed, 336 insertions(+)
create mode 100644 drivers/clk/ti/clk-7xx.c
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index dba8b3e..1a83c3c 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -4,4 +4,5 @@ obj-y += clk.o dpll.o autoidle.o divider.o \
mux-gate.o mux.o apll.o
obj-$(CONFIG_ARCH_OMAP4) += clk-44xx.o
obj-$(CONFIG_SOC_OMAP5) += clk-54xx.o
+obj-$(CONFIG_SOC_DRA7XX) += clk-7xx.o
endif
diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c
new file mode 100644
index 0000000..e0e65f1
--- /dev/null
+++ b/drivers/clk/ti/clk-7xx.c
@@ -0,0 +1,334 @@
+/*
+ * DRA7 Clock init
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo (t-kristo at ti.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/clk-private.h>
+#include <linux/clkdev.h>
+#include <linux/clk/ti.h>
+
+#define DRA7_DPLL_ABE_DEFFREQ 361267200
+#define DRA7_DPLL_GMAC_DEFFREQ 1000000000
+
+
+static struct ti_dt_clk dra7xx_clks[] = {
+ DT_CLK(NULL, "atl_clkin0_ck", "atl_clkin0_ck"),
+ DT_CLK(NULL, "atl_clkin1_ck", "atl_clkin1_ck"),
+ DT_CLK(NULL, "atl_clkin2_ck", "atl_clkin2_ck"),
+ DT_CLK(NULL, "atlclkin3_ck", "atlclkin3_ck"),
+ DT_CLK(NULL, "hdmi_clkin_ck", "hdmi_clkin_ck"),
+ DT_CLK(NULL, "mlb_clkin_ck", "mlb_clkin_ck"),
+ DT_CLK(NULL, "mlbp_clkin_ck", "mlbp_clkin_ck"),
+ DT_CLK(NULL, "pciesref_acs_clk_ck", "pciesref_acs_clk_ck"),
+ DT_CLK(NULL, "ref_clkin0_ck", "ref_clkin0_ck"),
+ DT_CLK(NULL, "ref_clkin1_ck", "ref_clkin1_ck"),
+ DT_CLK(NULL, "ref_clkin2_ck", "ref_clkin2_ck"),
+ DT_CLK(NULL, "ref_clkin3_ck", "ref_clkin3_ck"),
+ DT_CLK(NULL, "rmii_clk_ck", "rmii_clk_ck"),
+ DT_CLK(NULL, "sdvenc_clkin_ck", "sdvenc_clkin_ck"),
+ DT_CLK(NULL, "secure_32k_clk_src_ck", "secure_32k_clk_src_ck"),
+ DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"),
+ DT_CLK(NULL, "virt_12000000_ck", "virt_12000000_ck"),
+ DT_CLK(NULL, "virt_13000000_ck", "virt_13000000_ck"),
+ DT_CLK(NULL, "virt_16800000_ck", "virt_16800000_ck"),
+ DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
+ DT_CLK(NULL, "virt_20000000_ck", "virt_20000000_ck"),
+ DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
+ DT_CLK(NULL, "virt_27000000_ck", "virt_27000000_ck"),
+ DT_CLK(NULL, "virt_38400000_ck", "virt_38400000_ck"),
+ DT_CLK(NULL, "sys_clkin1", "sys_clkin1"),
+ DT_CLK(NULL, "sys_clkin2", "sys_clkin2"),
+ DT_CLK(NULL, "usb_otg_clkin_ck", "usb_otg_clkin_ck"),
+ DT_CLK(NULL, "video1_clkin_ck", "video1_clkin_ck"),
+ DT_CLK(NULL, "video1_m2_clkin_ck", "video1_m2_clkin_ck"),
+ DT_CLK(NULL, "video2_clkin_ck", "video2_clkin_ck"),
+ DT_CLK(NULL, "video2_m2_clkin_ck", "video2_m2_clkin_ck"),
+ DT_CLK(NULL, "abe_dpll_sys_clk_mux", "abe_dpll_sys_clk_mux"),
+ DT_CLK(NULL, "abe_dpll_bypass_clk_mux", "abe_dpll_bypass_clk_mux"),
+ DT_CLK(NULL, "abe_dpll_clk_mux", "abe_dpll_clk_mux"),
+ DT_CLK(NULL, "dpll_abe_ck", "dpll_abe_ck"),
+ DT_CLK(NULL, "dpll_abe_x2_ck", "dpll_abe_x2_ck"),
+ DT_CLK(NULL, "dpll_abe_m2x2_ck", "dpll_abe_m2x2_ck"),
+ DT_CLK(NULL, "abe_24m_fclk", "abe_24m_fclk"),
+ DT_CLK(NULL, "abe_clk", "abe_clk"),
+ DT_CLK(NULL, "aess_fclk", "aess_fclk"),
+ DT_CLK(NULL, "abe_giclk_div", "abe_giclk_div"),
+ DT_CLK(NULL, "abe_lp_clk_div", "abe_lp_clk_div"),
+ DT_CLK(NULL, "abe_sys_clk_div", "abe_sys_clk_div"),
+ DT_CLK(NULL, "adc_gfclk_mux", "adc_gfclk_mux"),
+ DT_CLK(NULL, "dpll_pcie_ref_ck", "dpll_pcie_ref_ck"),
+ DT_CLK(NULL, "dpll_pcie_ref_m2ldo_ck", "dpll_pcie_ref_m2ldo_ck"),
+ DT_CLK(NULL, "apll_pcie_ck", "apll_pcie_ck"),
+ DT_CLK(NULL, "apll_pcie_clkvcoldo", "apll_pcie_clkvcoldo"),
+ DT_CLK(NULL, "apll_pcie_clkvcoldo_div", "apll_pcie_clkvcoldo_div"),
+ DT_CLK(NULL, "apll_pcie_m2_ck", "apll_pcie_m2_ck"),
+ DT_CLK(NULL, "sys_clk1_dclk_div", "sys_clk1_dclk_div"),
+ DT_CLK(NULL, "sys_clk2_dclk_div", "sys_clk2_dclk_div"),
+ DT_CLK(NULL, "dpll_abe_m2_ck", "dpll_abe_m2_ck"),
+ DT_CLK(NULL, "per_abe_x1_dclk_div", "per_abe_x1_dclk_div"),
+ DT_CLK(NULL, "dpll_abe_m3x2_ck", "dpll_abe_m3x2_ck"),
+ DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
+ DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
+ DT_CLK(NULL, "dpll_core_h12x2_ck", "dpll_core_h12x2_ck"),
+ DT_CLK(NULL, "mpu_dpll_hs_clk_div", "mpu_dpll_hs_clk_div"),
+ DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"),
+ DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"),
+ DT_CLK(NULL, "mpu_dclk_div", "mpu_dclk_div"),
+ DT_CLK(NULL, "dsp_dpll_hs_clk_div", "dsp_dpll_hs_clk_div"),
+ DT_CLK(NULL, "dpll_dsp_ck", "dpll_dsp_ck"),
+ DT_CLK(NULL, "dpll_dsp_m2_ck", "dpll_dsp_m2_ck"),
+ DT_CLK(NULL, "dsp_gclk_div", "dsp_gclk_div"),
+ DT_CLK(NULL, "iva_dpll_hs_clk_div", "iva_dpll_hs_clk_div"),
+ DT_CLK(NULL, "dpll_iva_ck", "dpll_iva_ck"),
+ DT_CLK(NULL, "dpll_iva_m2_ck", "dpll_iva_m2_ck"),
+ DT_CLK(NULL, "iva_dclk", "iva_dclk"),
+ DT_CLK(NULL, "dpll_gpu_ck", "dpll_gpu_ck"),
+ DT_CLK(NULL, "dpll_gpu_m2_ck", "dpll_gpu_m2_ck"),
+ DT_CLK(NULL, "gpu_dclk", "gpu_dclk"),
+ DT_CLK(NULL, "dpll_core_m2_ck", "dpll_core_m2_ck"),
+ DT_CLK(NULL, "core_dpll_out_dclk_div", "core_dpll_out_dclk_div"),
+ DT_CLK(NULL, "dpll_ddr_ck", "dpll_ddr_ck"),
+ DT_CLK(NULL, "dpll_ddr_m2_ck", "dpll_ddr_m2_ck"),
+ DT_CLK(NULL, "emif_phy_dclk_div", "emif_phy_dclk_div"),
+ DT_CLK(NULL, "dpll_gmac_ck", "dpll_gmac_ck"),
+ DT_CLK(NULL, "dpll_gmac_m2_ck", "dpll_gmac_m2_ck"),
+ DT_CLK(NULL, "gmac_250m_dclk_div", "gmac_250m_dclk_div"),
+ DT_CLK(NULL, "video2_dclk_div", "video2_dclk_div"),
+ DT_CLK(NULL, "video1_dclk_div", "video1_dclk_div"),
+ DT_CLK(NULL, "hdmi_dclk_div", "hdmi_dclk_div"),
+ DT_CLK(NULL, "per_dpll_hs_clk_div", "per_dpll_hs_clk_div"),
+ DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"),
+ DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"),
+ DT_CLK(NULL, "func_96m_aon_dclk_div", "func_96m_aon_dclk_div"),
+ DT_CLK(NULL, "usb_dpll_hs_clk_div", "usb_dpll_hs_clk_div"),
+ DT_CLK(NULL, "dpll_usb_ck", "dpll_usb_ck"),
+ DT_CLK(NULL, "dpll_usb_m2_ck", "dpll_usb_m2_ck"),
+ DT_CLK(NULL, "l3init_480m_dclk_div", "l3init_480m_dclk_div"),
+ DT_CLK(NULL, "usb_otg_dclk_div", "usb_otg_dclk_div"),
+ DT_CLK(NULL, "sata_dclk_div", "sata_dclk_div"),
+ DT_CLK(NULL, "dpll_pcie_ref_m2_ck", "dpll_pcie_ref_m2_ck"),
+ DT_CLK(NULL, "pcie2_dclk_div", "pcie2_dclk_div"),
+ DT_CLK(NULL, "pcie_dclk_div", "pcie_dclk_div"),
+ DT_CLK(NULL, "emu_dclk_div", "emu_dclk_div"),
+ DT_CLK(NULL, "secure_32k_dclk_div", "secure_32k_dclk_div"),
+ DT_CLK(NULL, "eve_dpll_hs_clk_div", "eve_dpll_hs_clk_div"),
+ DT_CLK(NULL, "dpll_eve_ck", "dpll_eve_ck"),
+ DT_CLK(NULL, "dpll_eve_m2_ck", "dpll_eve_m2_ck"),
+ DT_CLK(NULL, "eve_dclk_div", "eve_dclk_div"),
+ DT_CLK(NULL, "clkoutmux0_clk_mux", "clkoutmux0_clk_mux"),
+ DT_CLK(NULL, "clkoutmux1_clk_mux", "clkoutmux1_clk_mux"),
+ DT_CLK(NULL, "clkoutmux2_clk_mux", "clkoutmux2_clk_mux"),
+ DT_CLK(NULL, "custefuse_sys_gfclk_div", "custefuse_sys_gfclk_div"),
+ DT_CLK(NULL, "dpll_core_h13x2_ck", "dpll_core_h13x2_ck"),
+ DT_CLK(NULL, "dpll_core_h14x2_ck", "dpll_core_h14x2_ck"),
+ DT_CLK(NULL, "dpll_core_h22x2_ck", "dpll_core_h22x2_ck"),
+ DT_CLK(NULL, "dpll_core_h23x2_ck", "dpll_core_h23x2_ck"),
+ DT_CLK(NULL, "dpll_core_h24x2_ck", "dpll_core_h24x2_ck"),
+ DT_CLK(NULL, "dpll_ddr_x2_ck", "dpll_ddr_x2_ck"),
+ DT_CLK(NULL, "dpll_ddr_h11x2_ck", "dpll_ddr_h11x2_ck"),
+ DT_CLK(NULL, "dpll_dsp_x2_ck", "dpll_dsp_x2_ck"),
+ DT_CLK(NULL, "dpll_dsp_m3x2_ck", "dpll_dsp_m3x2_ck"),
+ DT_CLK(NULL, "dpll_gmac_x2_ck", "dpll_gmac_x2_ck"),
+ DT_CLK(NULL, "dpll_gmac_h11x2_ck", "dpll_gmac_h11x2_ck"),
+ DT_CLK(NULL, "dpll_gmac_h12x2_ck", "dpll_gmac_h12x2_ck"),
+ DT_CLK(NULL, "dpll_gmac_h13x2_ck", "dpll_gmac_h13x2_ck"),
+ DT_CLK(NULL, "dpll_gmac_m3x2_ck", "dpll_gmac_m3x2_ck"),
+ DT_CLK(NULL, "dpll_per_x2_ck", "dpll_per_x2_ck"),
+ DT_CLK(NULL, "dpll_per_h11x2_ck", "dpll_per_h11x2_ck"),
+ DT_CLK(NULL, "dpll_per_h12x2_ck", "dpll_per_h12x2_ck"),
+ DT_CLK(NULL, "dpll_per_h13x2_ck", "dpll_per_h13x2_ck"),
+ DT_CLK(NULL, "dpll_per_h14x2_ck", "dpll_per_h14x2_ck"),
+ DT_CLK(NULL, "dpll_per_m2x2_ck", "dpll_per_m2x2_ck"),
+ DT_CLK(NULL, "dpll_usb_clkdcoldo", "dpll_usb_clkdcoldo"),
+ DT_CLK(NULL, "eve_clk", "eve_clk"),
+ DT_CLK(NULL, "func_128m_clk", "func_128m_clk"),
+ DT_CLK(NULL, "func_12m_fclk", "func_12m_fclk"),
+ DT_CLK(NULL, "func_24m_clk", "func_24m_clk"),
+ DT_CLK(NULL, "func_48m_fclk", "func_48m_fclk"),
+ DT_CLK(NULL, "func_96m_fclk", "func_96m_fclk"),
+ DT_CLK(NULL, "gmii_m_clk_div", "gmii_m_clk_div"),
+ DT_CLK(NULL, "hdmi_clk2_div", "hdmi_clk2_div"),
+ DT_CLK(NULL, "hdmi_div_clk", "hdmi_div_clk"),
+ DT_CLK(NULL, "hdmi_dpll_clk_mux", "hdmi_dpll_clk_mux"),
+ DT_CLK(NULL, "l3_iclk_div", "l3_iclk_div"),
+ DT_CLK(NULL, "l3init_60m_fclk", "l3init_60m_fclk"),
+ DT_CLK(NULL, "l4_root_clk_div", "l4_root_clk_div"),
+ DT_CLK(NULL, "mlb_clk", "mlb_clk"),
+ DT_CLK(NULL, "mlbp_clk", "mlbp_clk"),
+ DT_CLK(NULL, "per_abe_x1_gfclk2_div", "per_abe_x1_gfclk2_div"),
+ DT_CLK(NULL, "timer_sys_clk_div", "timer_sys_clk_div"),
+ DT_CLK(NULL, "video1_clk2_div", "video1_clk2_div"),
+ DT_CLK(NULL, "video1_div_clk", "video1_div_clk"),
+ DT_CLK(NULL, "video1_dpll_clk_mux", "video1_dpll_clk_mux"),
+ DT_CLK(NULL, "video2_clk2_div", "video2_clk2_div"),
+ DT_CLK(NULL, "video2_div_clk", "video2_div_clk"),
+ DT_CLK(NULL, "video2_dpll_clk_mux", "video2_dpll_clk_mux"),
+ DT_CLK(NULL, "wkupaon_iclk_mux", "wkupaon_iclk_mux"),
+ DT_CLK(NULL, "dss_32khz_clk", "dss_32khz_clk"),
+ DT_CLK(NULL, "dss_48mhz_clk", "dss_48mhz_clk"),
+ DT_CLK(NULL, "dss_dss_clk", "dss_dss_clk"),
+ DT_CLK(NULL, "dss_hdmi_clk", "dss_hdmi_clk"),
+ DT_CLK(NULL, "dss_video1_clk", "dss_video1_clk"),
+ DT_CLK(NULL, "dss_video2_clk", "dss_video2_clk"),
+ DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
+ DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"),
+ DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"),
+ DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"),
+ DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"),
+ DT_CLK(NULL, "gpio6_dbclk", "gpio6_dbclk"),
+ DT_CLK(NULL, "gpio7_dbclk", "gpio7_dbclk"),
+ DT_CLK(NULL, "gpio8_dbclk", "gpio8_dbclk"),
+ DT_CLK(NULL, "mmc1_clk32k", "mmc1_clk32k"),
+ DT_CLK(NULL, "mmc2_clk32k", "mmc2_clk32k"),
+ DT_CLK(NULL, "mmc3_clk32k", "mmc3_clk32k"),
+ DT_CLK(NULL, "mmc4_clk32k", "mmc4_clk32k"),
+ DT_CLK(NULL, "sata_ref_clk", "sata_ref_clk"),
+ DT_CLK(NULL, "usb_otg_ss1_refclk960m", "usb_otg_ss1_refclk960m"),
+ DT_CLK(NULL, "usb_otg_ss2_refclk960m", "usb_otg_ss2_refclk960m"),
+ DT_CLK(NULL, "usb_phy1_always_on_clk32k", "usb_phy1_always_on_clk32k"),
+ DT_CLK(NULL, "usb_phy2_always_on_clk32k", "usb_phy2_always_on_clk32k"),
+ DT_CLK(NULL, "usb_phy3_always_on_clk32k", "usb_phy3_always_on_clk32k"),
+ DT_CLK(NULL, "atl_dpll_clk_mux", "atl_dpll_clk_mux"),
+ DT_CLK(NULL, "atl_gfclk_mux", "atl_gfclk_mux"),
+ DT_CLK(NULL, "dcan1_sys_clk_mux", "dcan1_sys_clk_mux"),
+ DT_CLK(NULL, "gmac_gmii_ref_clk_div", "gmac_gmii_ref_clk_div"),
+ DT_CLK(NULL, "gmac_rft_clk_mux", "gmac_rft_clk_mux"),
+ DT_CLK(NULL, "gpu_core_gclk_mux", "gpu_core_gclk_mux"),
+ DT_CLK(NULL, "gpu_hyd_gclk_mux", "gpu_hyd_gclk_mux"),
+ DT_CLK(NULL, "ipu1_gfclk_mux", "ipu1_gfclk_mux"),
+ DT_CLK(NULL, "l3instr_ts_gclk_div", "l3instr_ts_gclk_div"),
+ DT_CLK(NULL, "mcasp1_ahclkr_mux", "mcasp1_ahclkr_mux"),
+ DT_CLK(NULL, "mcasp1_ahclkx_mux", "mcasp1_ahclkx_mux"),
+ DT_CLK(NULL, "mcasp1_aux_gfclk_mux", "mcasp1_aux_gfclk_mux"),
+ DT_CLK(NULL, "mcasp2_ahclkr_mux", "mcasp2_ahclkr_mux"),
+ DT_CLK(NULL, "mcasp2_ahclkx_mux", "mcasp2_ahclkx_mux"),
+ DT_CLK(NULL, "mcasp2_aux_gfclk_mux", "mcasp2_aux_gfclk_mux"),
+ DT_CLK(NULL, "mcasp3_ahclkx_mux", "mcasp3_ahclkx_mux"),
+ DT_CLK(NULL, "mcasp3_aux_gfclk_mux", "mcasp3_aux_gfclk_mux"),
+ DT_CLK(NULL, "mcasp4_ahclkx_mux", "mcasp4_ahclkx_mux"),
+ DT_CLK(NULL, "mcasp4_aux_gfclk_mux", "mcasp4_aux_gfclk_mux"),
+ DT_CLK(NULL, "mcasp5_ahclkx_mux", "mcasp5_ahclkx_mux"),
+ DT_CLK(NULL, "mcasp5_aux_gfclk_mux", "mcasp5_aux_gfclk_mux"),
+ DT_CLK(NULL, "mcasp6_ahclkx_mux", "mcasp6_ahclkx_mux"),
+ DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "mcasp6_aux_gfclk_mux"),
+ DT_CLK(NULL, "mcasp7_ahclkx_mux", "mcasp7_ahclkx_mux"),
+ DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "mcasp7_aux_gfclk_mux"),
+ DT_CLK(NULL, "mcasp8_ahclk_mux", "mcasp8_ahclk_mux"),
+ DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "mcasp8_aux_gfclk_mux"),
+ DT_CLK(NULL, "mmc1_fclk_mux", "mmc1_fclk_mux"),
+ DT_CLK(NULL, "mmc1_fclk_div", "mmc1_fclk_div"),
+ DT_CLK(NULL, "mmc2_fclk_mux", "mmc2_fclk_mux"),
+ DT_CLK(NULL, "mmc2_fclk_div", "mmc2_fclk_div"),
+ DT_CLK(NULL, "mmc3_gfclk_mux", "mmc3_gfclk_mux"),
+ DT_CLK(NULL, "mmc3_gfclk_div", "mmc3_gfclk_div"),
+ DT_CLK(NULL, "mmc4_gfclk_mux", "mmc4_gfclk_mux"),
+ DT_CLK(NULL, "mmc4_gfclk_div", "mmc4_gfclk_div"),
+ DT_CLK(NULL, "qspi_gfclk_mux", "qspi_gfclk_mux"),
+ DT_CLK(NULL, "qspi_gfclk_div", "qspi_gfclk_div"),
+ DT_CLK(NULL, "timer10_gfclk_mux", "timer10_gfclk_mux"),
+ DT_CLK(NULL, "timer11_gfclk_mux", "timer11_gfclk_mux"),
+ DT_CLK(NULL, "timer13_gfclk_mux", "timer13_gfclk_mux"),
+ DT_CLK(NULL, "timer14_gfclk_mux", "timer14_gfclk_mux"),
+ DT_CLK(NULL, "timer15_gfclk_mux", "timer15_gfclk_mux"),
+ DT_CLK(NULL, "timer16_gfclk_mux", "timer16_gfclk_mux"),
+ DT_CLK(NULL, "timer1_gfclk_mux", "timer1_gfclk_mux"),
+ DT_CLK(NULL, "timer2_gfclk_mux", "timer2_gfclk_mux"),
+ DT_CLK(NULL, "timer3_gfclk_mux", "timer3_gfclk_mux"),
+ DT_CLK(NULL, "timer4_gfclk_mux", "timer4_gfclk_mux"),
+ DT_CLK(NULL, "timer5_gfclk_mux", "timer5_gfclk_mux"),
+ DT_CLK(NULL, "timer6_gfclk_mux", "timer6_gfclk_mux"),
+ DT_CLK(NULL, "timer7_gfclk_mux", "timer7_gfclk_mux"),
+ DT_CLK(NULL, "timer8_gfclk_mux", "timer8_gfclk_mux"),
+ DT_CLK(NULL, "timer9_gfclk_mux", "timer9_gfclk_mux"),
+ DT_CLK(NULL, "uart10_gfclk_mux", "uart10_gfclk_mux"),
+ DT_CLK(NULL, "uart1_gfclk_mux", "uart1_gfclk_mux"),
+ DT_CLK(NULL, "uart2_gfclk_mux", "uart2_gfclk_mux"),
+ DT_CLK(NULL, "uart3_gfclk_mux", "uart3_gfclk_mux"),
+ DT_CLK(NULL, "uart4_gfclk_mux", "uart4_gfclk_mux"),
+ DT_CLK(NULL, "uart5_gfclk_mux", "uart5_gfclk_mux"),
+ DT_CLK(NULL, "uart6_gfclk_mux", "uart6_gfclk_mux"),
+ DT_CLK(NULL, "uart7_gfclk_mux", "uart7_gfclk_mux"),
+ DT_CLK(NULL, "uart8_gfclk_mux", "uart8_gfclk_mux"),
+ DT_CLK(NULL, "uart9_gfclk_mux", "uart9_gfclk_mux"),
+ DT_CLK(NULL, "vip1_gclk_mux", "vip1_gclk_mux"),
+ DT_CLK(NULL, "vip2_gclk_mux", "vip2_gclk_mux"),
+ DT_CLK(NULL, "vip3_gclk_mux", "vip3_gclk_mux"),
+ DT_CLK(NULL, "gpmc_ck", "dummy_ck"),
+ DT_CLK("omap_i2c.1", "ick", "dummy_ck"),
+ DT_CLK("omap_i2c.2", "ick", "dummy_ck"),
+ DT_CLK("omap_i2c.3", "ick", "dummy_ck"),
+ DT_CLK("omap_i2c.4", "ick", "dummy_ck"),
+ DT_CLK(NULL, "mailboxes_ick", "dummy_ck"),
+ DT_CLK("omap_hsmmc.0", "ick", "dummy_ck"),
+ DT_CLK("omap_hsmmc.1", "ick", "dummy_ck"),
+ DT_CLK("omap_hsmmc.2", "ick", "dummy_ck"),
+ DT_CLK("omap_hsmmc.3", "ick", "dummy_ck"),
+ DT_CLK("omap_hsmmc.4", "ick", "dummy_ck"),
+ DT_CLK("omap-mcbsp.1", "ick", "dummy_ck"),
+ DT_CLK("omap-mcbsp.2", "ick", "dummy_ck"),
+ DT_CLK("omap-mcbsp.3", "ick", "dummy_ck"),
+ DT_CLK("omap-mcbsp.4", "ick", "dummy_ck"),
+ DT_CLK("omap2_mcspi.1", "ick", "dummy_ck"),
+ DT_CLK("omap2_mcspi.2", "ick", "dummy_ck"),
+ DT_CLK("omap2_mcspi.3", "ick", "dummy_ck"),
+ DT_CLK("omap2_mcspi.4", "ick", "dummy_ck"),
+ DT_CLK(NULL, "uart1_ick", "dummy_ck"),
+ DT_CLK(NULL, "uart2_ick", "dummy_ck"),
+ DT_CLK(NULL, "uart3_ick", "dummy_ck"),
+ DT_CLK(NULL, "uart4_ick", "dummy_ck"),
+ DT_CLK("usbhs_omap", "usbhost_ick", "dummy_ck"),
+ DT_CLK("usbhs_omap", "usbtll_fck", "dummy_ck"),
+ DT_CLK("omap_wdt", "ick", "dummy_ck"),
+ DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
+ DT_CLK("4ae18000.timer", "timer_sys_ck", "sys_clkin2"),
+ DT_CLK("48032000.timer", "timer_sys_ck", "sys_clkin2"),
+ DT_CLK("48034000.timer", "timer_sys_ck", "sys_clkin2"),
+ DT_CLK("48036000.timer", "timer_sys_ck", "sys_clkin2"),
+ DT_CLK("4803e000.timer", "timer_sys_ck", "sys_clkin2"),
+ DT_CLK("48086000.timer", "timer_sys_ck", "sys_clkin2"),
+ DT_CLK("48088000.timer", "timer_sys_ck", "sys_clkin2"),
+ DT_CLK("48820000.timer", "timer_sys_ck", "timer_sys_clk_div"),
+ DT_CLK("48822000.timer", "timer_sys_ck", "timer_sys_clk_div"),
+ DT_CLK("48824000.timer", "timer_sys_ck", "timer_sys_clk_div"),
+ DT_CLK("48826000.timer", "timer_sys_ck", "timer_sys_clk_div"),
+ DT_CLK(NULL, "sys_clkin", "sys_clkin1"),
+ { .node_name = NULL },
+};
+
+int __init dra7xx_clk_init(void)
+{
+ int rc;
+ struct clk *abe_dpll_mux, *sys_clkin2, *dpll_ck;
+
+ of_clk_init(NULL);
+
+ ti_dt_clocks_register(dra7xx_clks);
+
+ omap2_clk_disable_autoidle_all();
+
+ abe_dpll_mux = clk_get_sys(NULL, "abe_dpll_sys_clk_mux");
+ sys_clkin2 = clk_get_sys(NULL, "sys_clkin2");
+ dpll_ck = clk_get_sys(NULL, "dpll_abe_ck");
+
+ rc = clk_set_parent(abe_dpll_mux, sys_clkin2);
+ if (!rc)
+ rc = clk_set_rate(dpll_ck, DRA7_DPLL_ABE_DEFFREQ);
+ if (rc)
+ pr_err("%s: failed to configure ABE DPLL!\n", __func__);
+
+ dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck");
+ rc = clk_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ);
+ if (rc)
+ pr_err("%s: failed to configure GMAC DPLL!\n", __func__);
+
+ return rc;
+}
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 9a29e17..1b2dc51 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -221,6 +221,7 @@ struct clk_div_table *ti_clk_get_div_table(struct device_node *node);
int omap4xxx_clk_init(void);
int omap5xxx_clk_init(void);
+int dra7xx_clk_init(void);
#ifdef CONFIG_OF
void of_ti_clk_allow_autoidle_all(void);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 22/36] ARM: OMAP: DRA7: Enable clock init
2013-09-25 8:48 ` Tero Kristo
@ 2013-09-25 8:48 ` Tero Kristo
-1 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-omap-u79uwXL29TY76Z2rM5mHXA, paul-DWxLp4Yu+b8AvxtiuMwx3w,
tony-4v6yS6AI5VpBDgjK7y7TUQ, nm-l0cyMroinI0, rnayak-l0cyMroinI0,
bcousson-rdvid1DuHRBWk0Htik3J/w,
mturquette-QSEj5FYQhm4dnm+yROfE0A
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
Initializes clock data from device tree.
Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
arch/arm/mach-omap2/io.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 205bb1d..1f23182 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -671,6 +671,7 @@ void __init dra7xx_init_early(void)
dra7xx_clockdomains_init();
dra7xx_hwmod_init();
omap_hwmod_init_postsetup();
+ omap_clk_init = dra7xx_clk_init;
}
#endif
--
1.7.9.5
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 22/36] ARM: OMAP: DRA7: Enable clock init
@ 2013-09-25 8:48 ` Tero Kristo
0 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-arm-kernel
Initializes clock data from device tree.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/mach-omap2/io.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 205bb1d..1f23182 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -671,6 +671,7 @@ void __init dra7xx_init_early(void)
dra7xx_clockdomains_init();
dra7xx_hwmod_init();
omap_hwmod_init_postsetup();
+ omap_clk_init = dra7xx_clk_init;
}
#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 23/36] ARM: dts: DRA7: link in clock DT data
2013-09-25 8:48 ` Tero Kristo
@ 2013-09-25 8:48 ` Tero Kristo
-1 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-omap, paul, tony, nm, rnayak, bcousson, mturquette
Cc: linux-arm-kernel, devicetree
Clock tree DT data is now included from base dra7.dtsi file.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/boot/dts/dra7.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index c01ef76..c98997b 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -572,4 +572,18 @@
status = "disabled";
};
};
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ /include/ "dra7xx-clocks.dtsi"
+ };
+
+ clockdomains {
+ coreaon_clkdm: coreaon_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll_usb_ck>;
+ };
+ };
};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 23/36] ARM: dts: DRA7: link in clock DT data
@ 2013-09-25 8:48 ` Tero Kristo
0 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-arm-kernel
Clock tree DT data is now included from base dra7.dtsi file.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/boot/dts/dra7.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index c01ef76..c98997b 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -572,4 +572,18 @@
status = "disabled";
};
};
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ /include/ "dra7xx-clocks.dtsi"
+ };
+
+ clockdomains {
+ coreaon_clkdm: coreaon_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll_usb_ck>;
+ };
+ };
};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 24/36] ARM: dts: am33xx clock data
2013-09-25 8:48 ` Tero Kristo
@ 2013-09-25 8:48 ` Tero Kristo
-1 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-omap, paul, tony, nm, rnayak, bcousson, mturquette
Cc: linux-arm-kernel, devicetree
This patch creates a unique node for each clock in the AM33xx power,
reset and clock manager (PRCM).
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/boot/dts/am33xx-clocks.dtsi | 640 ++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/am33xx.dtsi | 16 +-
2 files changed, 655 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/am33xx-clocks.dtsi
diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/am33xx-clocks.dtsi
new file mode 100644
index 0000000..9a79e49
--- /dev/null
+++ b/arch/arm/boot/dts/am33xx-clocks.dtsi
@@ -0,0 +1,640 @@
+/*
+ * Device Tree Source for AM33xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+clk_32768_ck: clk_32768_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+};
+
+clk_rc32k_ck: clk_rc32k_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32000>;
+};
+
+virt_19200000_ck: virt_19200000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <19200000>;
+};
+
+virt_24000000_ck: virt_24000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+};
+
+virt_25000000_ck: virt_25000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <25000000>;
+};
+
+virt_26000000_ck: virt_26000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <26000000>;
+};
+
+sys_clkin_ck: sys_clkin_ck@44e10040 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
+ ti,bit-shift = <22>;
+ reg = <0x44e10040 0x4>;
+};
+
+tclkin_ck: tclkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+};
+
+dpll_core_ck: dpll_core_ck@44e00490 {
+ #clock-cells = <0>;
+ compatible = "ti,am3-dpll-core-clock";
+ clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+ reg = <0x44e00490 0x4>, <0x44e0045c 0x4>, <0x44e00468 0x4>;
+};
+
+dpll_core_x2_ck: dpll_core_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,am3-dpll-x2-clock";
+ clocks = <&dpll_core_ck>;
+};
+
+dpll_core_m4_ck: dpll_core_m4_ck@44e00480 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ reg = <0x44e00480 0x4>;
+ ti,max-div = <31>;
+ ti,index-starts-at-one;
+};
+
+dpll_core_m5_ck: dpll_core_m5_ck@44e00484 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ reg = <0x44e00484 0x4>;
+ ti,max-div = <31>;
+ ti,index-starts-at-one;
+};
+
+dpll_core_m6_ck: dpll_core_m6_ck@44e004d8 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ reg = <0x44e004d8 0x4>;
+ ti,max-div = <31>;
+ ti,index-starts-at-one;
+};
+
+dpll_mpu_ck: dpll_mpu_ck@44e00488 {
+ #clock-cells = <0>;
+ compatible = "ti,am3-dpll-clock";
+ clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+ reg = <0x44e00488 0x4>, <0x44e00420 0x4>, <0x44e0042c 0x4>;
+};
+
+dpll_mpu_m2_ck: dpll_mpu_m2_ck@44e004a8 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_mpu_ck>;
+ reg = <0x44e004a8 0x4>;
+ ti,max-div = <31>;
+ ti,index-starts-at-one;
+};
+
+dpll_ddr_ck: dpll_ddr_ck@44e00494 {
+ #clock-cells = <0>;
+ compatible = "ti,am3-dpll-no-gate-clock";
+ clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+ reg = <0x44e00494 0x4>, <0x44e00434 0x4>, <0x44e00440 0x4>;
+};
+
+dpll_ddr_m2_ck: dpll_ddr_m2_ck@44e004a0 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_ddr_ck>;
+ reg = <0x44e004a0 0x4>;
+ ti,max-div = <31>;
+ ti,index-starts-at-one;
+};
+
+dpll_ddr_m2_div2_ck: dpll_ddr_m2_div2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_ddr_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+dpll_disp_ck: dpll_disp_ck@44e00498 {
+ #clock-cells = <0>;
+ compatible = "ti,am3-dpll-no-gate-clock";
+ clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+ reg = <0x44e00498 0x4>, <0x44e00448 0x4>, <0x44e00454 0x4>;
+};
+
+dpll_disp_m2_ck: dpll_disp_m2_ck@44e004a4 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_disp_ck>;
+ ti,max-div = <31>;
+ reg = <0x44e004a4 0x4>;
+ ti,index-starts-at-one;
+ ti,set-rate-parent;
+};
+
+dpll_per_ck: dpll_per_ck@44e0048c {
+ #clock-cells = <0>;
+ compatible = "ti,am3-dpll-no-gate-j-type-clock";
+ clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+ reg = <0x44e0048c 0x4>, <0x44e00470 0x4>, <0x44e0049c 0x4>;
+};
+
+dpll_per_m2_ck: dpll_per_m2_ck@44e004ac {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_ck>;
+ reg = <0x44e004ac 0x4>;
+ ti,max-div = <31>;
+ ti,index-starts-at-one;
+};
+
+dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+};
+
+dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+};
+
+adc_tsc_fck: adc_tsc_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+cefuse_fck: cefuse_fck@44e00a20 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_clkin_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x44e00a20 0x4>;
+};
+
+clk_24mhz: clk_24mhz {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <8>;
+};
+
+clkdiv32k_ck: clkdiv32k_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&clk_24mhz>;
+ clock-mult = <1>;
+ clock-div = <732>;
+};
+
+clkdiv32k_ick: clkdiv32k_ick@44e0014c {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&clkdiv32k_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x44e0014c 0x4>;
+};
+
+dcan0_fck: dcan0_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dcan1_fck: dcan1_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+l3_gclk: l3_gclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m4_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+pruss_ocp_gclk: pruss_ocp_gclk@44e00530 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&l3_gclk>, <&dpll_disp_m2_ck>;
+ reg = <0x44e00530 0x4>;
+};
+
+mcasp0_fck: mcasp0_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+mcasp1_fck: mcasp1_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+mmu_fck: mmu_fck@44e00914 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll_core_m4_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x44e00914 0x4>;
+};
+
+smartreflex0_fck: smartreflex0_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+smartreflex1_fck: smartreflex1_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+sha0_fck: sha0_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+aes0_fck: aes0_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+rng_fck: rng_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+timer1_fck: timer1_fck@44e00528 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
+ reg = <0x44e00528 0x4>;
+};
+
+timer2_fck: timer2_fck@44e00508 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ reg = <0x44e00508 0x4>;
+};
+
+timer3_fck: timer3_fck@44e0050c {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ reg = <0x44e0050c 0x4>;
+};
+
+timer4_fck: timer4_fck@44e00510 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ reg = <0x44e00510 0x4>;
+};
+
+timer5_fck: timer5_fck@44e00518 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ reg = <0x44e00518 0x4>;
+};
+
+timer6_fck: timer6_fck@44e0051c {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ reg = <0x44e0051c 0x4>;
+};
+
+timer7_fck: timer7_fck@44e00504 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ reg = <0x44e00504 0x4>;
+};
+
+usbotg_fck: usbotg_fck@44e0047c {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll_per_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x44e0047c 0x4>;
+};
+
+dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m4_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+ieee5000_fck: ieee5000_fck@44e000e4 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll_core_m4_div2_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x44e000e4 0x4>;
+};
+
+wdt1_fck: wdt1_fck@44e00538 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
+ reg = <0x44e00538 0x4>;
+};
+
+l4_rtc_gclk: l4_rtc_gclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m4_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+l4hs_gclk: l4hs_gclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m4_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+l3s_gclk: l3s_gclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m4_div2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+l4fw_gclk: l4fw_gclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m4_div2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+l4ls_gclk: l4ls_gclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m4_div2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+sysclk_div_ck: sysclk_div_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m4_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+cpsw_125mhz_gclk: cpsw_125mhz_gclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m5_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@44e00520 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>;
+ reg = <0x44e00520 0x4>;
+};
+
+gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@44e0053c {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>;
+ reg = <0x44e0053c 0x4>;
+};
+
+gpio0_dbclk: gpio0_dbclk@44e00408 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&gpio0_dbclk_mux_ck>;
+ ti,bit-shift = <18>;
+ reg = <0x44e00408 0x4>;
+};
+
+gpio1_dbclk: gpio1_dbclk@44e000ac {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&clkdiv32k_ick>;
+ ti,bit-shift = <18>;
+ reg = <0x44e000ac 0x4>;
+};
+
+gpio2_dbclk: gpio2_dbclk@44e000b0 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&clkdiv32k_ick>;
+ ti,bit-shift = <18>;
+ reg = <0x44e000b0 0x4>;
+};
+
+gpio3_dbclk: gpio3_dbclk@44e000b4 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&clkdiv32k_ick>;
+ ti,bit-shift = <18>;
+ reg = <0x44e000b4 0x4>;
+};
+
+lcd_gclk: lcd_gclk@44e00534 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
+ reg = <0x44e00534 0x4>;
+ ti,set-rate-parent;
+};
+
+mmc_clk: mmc_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@44e0052c {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x44e0052c 0x4>;
+};
+
+gfx_fck_div_ck: gfx_fck_div_ck@44e0052c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&gfx_fclk_clksel_ck>;
+ reg = <0x44e0052c 0x4>;
+ ti,dividers = <1>, <2>;
+};
+
+sysclkout_pre_ck: sysclkout_pre_ck@44e00700 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>;
+ reg = <0x44e00700 0x4>;
+};
+
+clkout2_div_ck: clkout2_div_ck@44e00700 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&sysclkout_pre_ck>;
+ ti,bit-shift = <3>;
+ reg = <0x44e00700 0x4>;
+ ti,dividers = <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>;
+};
+
+dbg_sysclk_ck: dbg_sysclk_ck@44e00414 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_clkin_ck>;
+ ti,bit-shift = <19>;
+ reg = <0x44e00414 0x4>;
+};
+
+dbg_clka_ck: dbg_clka_ck@44e00414 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll_core_m4_ck>;
+ ti,bit-shift = <30>;
+ reg = <0x44e00414 0x4>;
+};
+
+stm_pmd_clock_mux_ck: stm_pmd_clock_mux_ck@44e00414 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
+ ti,bit-shift = <22>;
+ reg = <0x44e00414 0x4>;
+};
+
+trace_pmd_clk_mux_ck: trace_pmd_clk_mux_ck@44e00414 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
+ ti,bit-shift = <20>;
+ reg = <0x44e00414 0x4>;
+};
+
+stm_clk_div_ck: stm_clk_div_ck@44e00414 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&stm_pmd_clock_mux_ck>;
+ ti,bit-shift = <27>;
+ ti,max-div = <64>;
+ reg = <0x44e00414 0x4>;
+ ti,index-power-of-two;
+};
+
+trace_clk_div_ck: trace_clk_div_ck@44e00414 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&trace_pmd_clk_mux_ck>;
+ ti,bit-shift = <24>;
+ ti,max-div = <64>;
+ reg = <0x44e00414 0x4>;
+ ti,index-power-of-two;
+};
+
+clkout2_ck: clkout2_ck@44e00700 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&clkout2_div_ck>;
+ ti,bit-shift = <7>;
+ reg = <0x44e00700 0x4>;
+};
+
+ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 {
+ #clock-cells = <0>;
+ compatible = "ti,no-wait-mux-gate-clock";
+ clocks = <&dpll_per_m2_ck>;
+ ti,gate-bit-shift = <0>;
+ reg = <0x44e10664 0x4>;
+ reg-names = "gate-reg";
+};
+
+ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 {
+ #clock-cells = <0>;
+ compatible = "ti,no-wait-mux-gate-clock";
+ clocks = <&dpll_per_m2_ck>;
+ ti,gate-bit-shift = <1>;
+ reg = <0x44e10664 0x4>;
+ reg-names = "gate-reg";
+};
+
+ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 {
+ #clock-cells = <0>;
+ compatible = "ti,no-wait-mux-gate-clock";
+ clocks = <&dpll_per_m2_ck>;
+ ti,gate-bit-shift = <2>;
+ reg = <0x44e10664 0x4>;
+ reg-names = "gate-reg";
+};
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 553adc6..4fb2bf3 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -711,4 +711,18 @@
status = "disabled";
};
};
-};
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ /include/ "am33xx-clocks.dtsi"
+ };
+
+ clockdomains {
+ clk_24mhz_clkdm: clk_24mhz_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&clkdiv32k_ick>;
+ };
+ };
+};
\ No newline at end of file
--
1.7.9.5
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 24/36] ARM: dts: am33xx clock data
@ 2013-09-25 8:48 ` Tero Kristo
0 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-arm-kernel
This patch creates a unique node for each clock in the AM33xx power,
reset and clock manager (PRCM).
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/boot/dts/am33xx-clocks.dtsi | 640 ++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/am33xx.dtsi | 16 +-
2 files changed, 655 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/am33xx-clocks.dtsi
diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/am33xx-clocks.dtsi
new file mode 100644
index 0000000..9a79e49
--- /dev/null
+++ b/arch/arm/boot/dts/am33xx-clocks.dtsi
@@ -0,0 +1,640 @@
+/*
+ * Device Tree Source for AM33xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+clk_32768_ck: clk_32768_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+};
+
+clk_rc32k_ck: clk_rc32k_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32000>;
+};
+
+virt_19200000_ck: virt_19200000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <19200000>;
+};
+
+virt_24000000_ck: virt_24000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+};
+
+virt_25000000_ck: virt_25000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <25000000>;
+};
+
+virt_26000000_ck: virt_26000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <26000000>;
+};
+
+sys_clkin_ck: sys_clkin_ck at 44e10040 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
+ ti,bit-shift = <22>;
+ reg = <0x44e10040 0x4>;
+};
+
+tclkin_ck: tclkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+};
+
+dpll_core_ck: dpll_core_ck at 44e00490 {
+ #clock-cells = <0>;
+ compatible = "ti,am3-dpll-core-clock";
+ clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+ reg = <0x44e00490 0x4>, <0x44e0045c 0x4>, <0x44e00468 0x4>;
+};
+
+dpll_core_x2_ck: dpll_core_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,am3-dpll-x2-clock";
+ clocks = <&dpll_core_ck>;
+};
+
+dpll_core_m4_ck: dpll_core_m4_ck at 44e00480 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ reg = <0x44e00480 0x4>;
+ ti,max-div = <31>;
+ ti,index-starts-at-one;
+};
+
+dpll_core_m5_ck: dpll_core_m5_ck at 44e00484 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ reg = <0x44e00484 0x4>;
+ ti,max-div = <31>;
+ ti,index-starts-at-one;
+};
+
+dpll_core_m6_ck: dpll_core_m6_ck at 44e004d8 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ reg = <0x44e004d8 0x4>;
+ ti,max-div = <31>;
+ ti,index-starts-at-one;
+};
+
+dpll_mpu_ck: dpll_mpu_ck at 44e00488 {
+ #clock-cells = <0>;
+ compatible = "ti,am3-dpll-clock";
+ clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+ reg = <0x44e00488 0x4>, <0x44e00420 0x4>, <0x44e0042c 0x4>;
+};
+
+dpll_mpu_m2_ck: dpll_mpu_m2_ck at 44e004a8 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_mpu_ck>;
+ reg = <0x44e004a8 0x4>;
+ ti,max-div = <31>;
+ ti,index-starts-at-one;
+};
+
+dpll_ddr_ck: dpll_ddr_ck at 44e00494 {
+ #clock-cells = <0>;
+ compatible = "ti,am3-dpll-no-gate-clock";
+ clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+ reg = <0x44e00494 0x4>, <0x44e00434 0x4>, <0x44e00440 0x4>;
+};
+
+dpll_ddr_m2_ck: dpll_ddr_m2_ck at 44e004a0 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_ddr_ck>;
+ reg = <0x44e004a0 0x4>;
+ ti,max-div = <31>;
+ ti,index-starts-at-one;
+};
+
+dpll_ddr_m2_div2_ck: dpll_ddr_m2_div2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_ddr_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+dpll_disp_ck: dpll_disp_ck at 44e00498 {
+ #clock-cells = <0>;
+ compatible = "ti,am3-dpll-no-gate-clock";
+ clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+ reg = <0x44e00498 0x4>, <0x44e00448 0x4>, <0x44e00454 0x4>;
+};
+
+dpll_disp_m2_ck: dpll_disp_m2_ck at 44e004a4 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_disp_ck>;
+ ti,max-div = <31>;
+ reg = <0x44e004a4 0x4>;
+ ti,index-starts-at-one;
+ ti,set-rate-parent;
+};
+
+dpll_per_ck: dpll_per_ck at 44e0048c {
+ #clock-cells = <0>;
+ compatible = "ti,am3-dpll-no-gate-j-type-clock";
+ clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+ reg = <0x44e0048c 0x4>, <0x44e00470 0x4>, <0x44e0049c 0x4>;
+};
+
+dpll_per_m2_ck: dpll_per_m2_ck at 44e004ac {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_ck>;
+ reg = <0x44e004ac 0x4>;
+ ti,max-div = <31>;
+ ti,index-starts-at-one;
+};
+
+dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+};
+
+dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+};
+
+adc_tsc_fck: adc_tsc_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+cefuse_fck: cefuse_fck at 44e00a20 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_clkin_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x44e00a20 0x4>;
+};
+
+clk_24mhz: clk_24mhz {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <8>;
+};
+
+clkdiv32k_ck: clkdiv32k_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&clk_24mhz>;
+ clock-mult = <1>;
+ clock-div = <732>;
+};
+
+clkdiv32k_ick: clkdiv32k_ick at 44e0014c {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&clkdiv32k_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x44e0014c 0x4>;
+};
+
+dcan0_fck: dcan0_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dcan1_fck: dcan1_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+l3_gclk: l3_gclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m4_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+pruss_ocp_gclk: pruss_ocp_gclk at 44e00530 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&l3_gclk>, <&dpll_disp_m2_ck>;
+ reg = <0x44e00530 0x4>;
+};
+
+mcasp0_fck: mcasp0_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+mcasp1_fck: mcasp1_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+mmu_fck: mmu_fck at 44e00914 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll_core_m4_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x44e00914 0x4>;
+};
+
+smartreflex0_fck: smartreflex0_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+smartreflex1_fck: smartreflex1_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+sha0_fck: sha0_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+aes0_fck: aes0_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+rng_fck: rng_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+timer1_fck: timer1_fck at 44e00528 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
+ reg = <0x44e00528 0x4>;
+};
+
+timer2_fck: timer2_fck at 44e00508 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ reg = <0x44e00508 0x4>;
+};
+
+timer3_fck: timer3_fck at 44e0050c {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ reg = <0x44e0050c 0x4>;
+};
+
+timer4_fck: timer4_fck at 44e00510 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ reg = <0x44e00510 0x4>;
+};
+
+timer5_fck: timer5_fck at 44e00518 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ reg = <0x44e00518 0x4>;
+};
+
+timer6_fck: timer6_fck at 44e0051c {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ reg = <0x44e0051c 0x4>;
+};
+
+timer7_fck: timer7_fck at 44e00504 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ reg = <0x44e00504 0x4>;
+};
+
+usbotg_fck: usbotg_fck at 44e0047c {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll_per_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x44e0047c 0x4>;
+};
+
+dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m4_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+ieee5000_fck: ieee5000_fck at 44e000e4 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll_core_m4_div2_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x44e000e4 0x4>;
+};
+
+wdt1_fck: wdt1_fck at 44e00538 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
+ reg = <0x44e00538 0x4>;
+};
+
+l4_rtc_gclk: l4_rtc_gclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m4_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+l4hs_gclk: l4hs_gclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m4_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+l3s_gclk: l3s_gclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m4_div2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+l4fw_gclk: l4fw_gclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m4_div2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+l4ls_gclk: l4ls_gclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m4_div2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+sysclk_div_ck: sysclk_div_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m4_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+cpsw_125mhz_gclk: cpsw_125mhz_gclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m5_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+cpsw_cpts_rft_clk: cpsw_cpts_rft_clk at 44e00520 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>;
+ reg = <0x44e00520 0x4>;
+};
+
+gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck at 44e0053c {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>;
+ reg = <0x44e0053c 0x4>;
+};
+
+gpio0_dbclk: gpio0_dbclk at 44e00408 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&gpio0_dbclk_mux_ck>;
+ ti,bit-shift = <18>;
+ reg = <0x44e00408 0x4>;
+};
+
+gpio1_dbclk: gpio1_dbclk at 44e000ac {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&clkdiv32k_ick>;
+ ti,bit-shift = <18>;
+ reg = <0x44e000ac 0x4>;
+};
+
+gpio2_dbclk: gpio2_dbclk at 44e000b0 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&clkdiv32k_ick>;
+ ti,bit-shift = <18>;
+ reg = <0x44e000b0 0x4>;
+};
+
+gpio3_dbclk: gpio3_dbclk at 44e000b4 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&clkdiv32k_ick>;
+ ti,bit-shift = <18>;
+ reg = <0x44e000b4 0x4>;
+};
+
+lcd_gclk: lcd_gclk at 44e00534 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
+ reg = <0x44e00534 0x4>;
+ ti,set-rate-parent;
+};
+
+mmc_clk: mmc_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+gfx_fclk_clksel_ck: gfx_fclk_clksel_ck at 44e0052c {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x44e0052c 0x4>;
+};
+
+gfx_fck_div_ck: gfx_fck_div_ck at 44e0052c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&gfx_fclk_clksel_ck>;
+ reg = <0x44e0052c 0x4>;
+ ti,dividers = <1>, <2>;
+};
+
+sysclkout_pre_ck: sysclkout_pre_ck at 44e00700 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>;
+ reg = <0x44e00700 0x4>;
+};
+
+clkout2_div_ck: clkout2_div_ck at 44e00700 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&sysclkout_pre_ck>;
+ ti,bit-shift = <3>;
+ reg = <0x44e00700 0x4>;
+ ti,dividers = <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>;
+};
+
+dbg_sysclk_ck: dbg_sysclk_ck at 44e00414 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_clkin_ck>;
+ ti,bit-shift = <19>;
+ reg = <0x44e00414 0x4>;
+};
+
+dbg_clka_ck: dbg_clka_ck at 44e00414 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll_core_m4_ck>;
+ ti,bit-shift = <30>;
+ reg = <0x44e00414 0x4>;
+};
+
+stm_pmd_clock_mux_ck: stm_pmd_clock_mux_ck at 44e00414 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
+ ti,bit-shift = <22>;
+ reg = <0x44e00414 0x4>;
+};
+
+trace_pmd_clk_mux_ck: trace_pmd_clk_mux_ck at 44e00414 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
+ ti,bit-shift = <20>;
+ reg = <0x44e00414 0x4>;
+};
+
+stm_clk_div_ck: stm_clk_div_ck at 44e00414 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&stm_pmd_clock_mux_ck>;
+ ti,bit-shift = <27>;
+ ti,max-div = <64>;
+ reg = <0x44e00414 0x4>;
+ ti,index-power-of-two;
+};
+
+trace_clk_div_ck: trace_clk_div_ck at 44e00414 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&trace_pmd_clk_mux_ck>;
+ ti,bit-shift = <24>;
+ ti,max-div = <64>;
+ reg = <0x44e00414 0x4>;
+ ti,index-power-of-two;
+};
+
+clkout2_ck: clkout2_ck at 44e00700 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&clkout2_div_ck>;
+ ti,bit-shift = <7>;
+ reg = <0x44e00700 0x4>;
+};
+
+ehrpwm0_tbclk: ehrpwm0_tbclk at 44e10664 {
+ #clock-cells = <0>;
+ compatible = "ti,no-wait-mux-gate-clock";
+ clocks = <&dpll_per_m2_ck>;
+ ti,gate-bit-shift = <0>;
+ reg = <0x44e10664 0x4>;
+ reg-names = "gate-reg";
+};
+
+ehrpwm1_tbclk: ehrpwm1_tbclk at 44e10664 {
+ #clock-cells = <0>;
+ compatible = "ti,no-wait-mux-gate-clock";
+ clocks = <&dpll_per_m2_ck>;
+ ti,gate-bit-shift = <1>;
+ reg = <0x44e10664 0x4>;
+ reg-names = "gate-reg";
+};
+
+ehrpwm2_tbclk: ehrpwm2_tbclk at 44e10664 {
+ #clock-cells = <0>;
+ compatible = "ti,no-wait-mux-gate-clock";
+ clocks = <&dpll_per_m2_ck>;
+ ti,gate-bit-shift = <2>;
+ reg = <0x44e10664 0x4>;
+ reg-names = "gate-reg";
+};
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 553adc6..4fb2bf3 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -711,4 +711,18 @@
status = "disabled";
};
};
-};
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ /include/ "am33xx-clocks.dtsi"
+ };
+
+ clockdomains {
+ clk_24mhz_clkdm: clk_24mhz_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&clkdiv32k_ick>;
+ };
+ };
+};
\ No newline at end of file
--
1.7.9.5
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 25/36] CLK: TI: add am33xx clock init file
2013-09-25 8:48 ` Tero Kristo
@ 2013-09-25 8:48 ` Tero Kristo
-1 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-omap-u79uwXL29TY76Z2rM5mHXA, paul-DWxLp4Yu+b8AvxtiuMwx3w,
tony-4v6yS6AI5VpBDgjK7y7TUQ, nm-l0cyMroinI0, rnayak-l0cyMroinI0,
bcousson-rdvid1DuHRBWk0Htik3J/w,
mturquette-QSEj5FYQhm4dnm+yROfE0A
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
clk-33xx.c now contains the clock init functionality for am33xx, including
DT clock registration and adding of static clkdev entries.
This patch also moves the omap2_clk_enable_init_clocks declaration to
the driver include, as this is needed by the am33xx clock init code.
Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
arch/arm/mach-omap2/clock.h | 1 -
drivers/clk/ti/clk-33xx.c | 163 +++++++++++++++++++++++++++++++++++++++++++
include/linux/clk/ti.h | 2 +
3 files changed, 165 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/ti/clk-33xx.c
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 106c5c2..2e6cbeb 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -247,7 +247,6 @@ void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
void __iomem **idlest_reg,
u8 *idlest_bit, u8 *idlest_val);
int omap2_clk_enable_autoidle_all(void);
-void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
const char *core_ck_name,
diff --git a/drivers/clk/ti/clk-33xx.c b/drivers/clk/ti/clk-33xx.c
new file mode 100644
index 0000000..1c9ad1b
--- /dev/null
+++ b/drivers/clk/ti/clk-33xx.c
@@ -0,0 +1,163 @@
+/*
+ * AM33XX Clock init
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc
+ * Tero Kristo (t-kristo-l0cyMroinI0@public.gmane.org)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/clk-provider.h>
+#include <linux/clk/ti.h>
+
+static struct ti_dt_clk am33xx_clks[] = {
+ DT_CLK(NULL, "clk_32768_ck", "clk_32768_ck"),
+ DT_CLK(NULL, "clk_rc32k_ck", "clk_rc32k_ck"),
+ DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
+ DT_CLK(NULL, "virt_24000000_ck", "virt_24000000_ck"),
+ DT_CLK(NULL, "virt_25000000_ck", "virt_25000000_ck"),
+ DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
+ DT_CLK(NULL, "sys_clkin_ck", "sys_clkin_ck"),
+ DT_CLK(NULL, "tclkin_ck", "tclkin_ck"),
+ DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
+ DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
+ DT_CLK(NULL, "dpll_core_m4_ck", "dpll_core_m4_ck"),
+ DT_CLK(NULL, "dpll_core_m5_ck", "dpll_core_m5_ck"),
+ DT_CLK(NULL, "dpll_core_m6_ck", "dpll_core_m6_ck"),
+ DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"),
+ DT_CLK("cpu0", NULL, "dpll_mpu_ck"),
+ DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"),
+ DT_CLK(NULL, "dpll_ddr_ck", "dpll_ddr_ck"),
+ DT_CLK(NULL, "dpll_ddr_m2_ck", "dpll_ddr_m2_ck"),
+ DT_CLK(NULL, "dpll_ddr_m2_div2_ck", "dpll_ddr_m2_div2_ck"),
+ DT_CLK(NULL, "dpll_disp_ck", "dpll_disp_ck"),
+ DT_CLK(NULL, "dpll_disp_m2_ck", "dpll_disp_m2_ck"),
+ DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"),
+ DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"),
+ DT_CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", "dpll_per_m2_div4_wkupdm_ck"),
+ DT_CLK(NULL, "dpll_per_m2_div4_ck", "dpll_per_m2_div4_ck"),
+ DT_CLK(NULL, "adc_tsc_fck", "adc_tsc_fck"),
+ DT_CLK(NULL, "cefuse_fck", "cefuse_fck"),
+ DT_CLK(NULL, "clkdiv32k_ck", "clkdiv32k_ck"),
+ DT_CLK(NULL, "clkdiv32k_ick", "clkdiv32k_ick"),
+ DT_CLK(NULL, "dcan0_fck", "dcan0_fck"),
+ DT_CLK("481cc000.d_can", NULL, "dcan0_fck"),
+ DT_CLK(NULL, "dcan1_fck", "dcan1_fck"),
+ DT_CLK("481d0000.d_can", NULL, "dcan1_fck"),
+ DT_CLK(NULL, "pruss_ocp_gclk", "pruss_ocp_gclk"),
+ DT_CLK(NULL, "mcasp0_fck", "mcasp0_fck"),
+ DT_CLK(NULL, "mcasp1_fck", "mcasp1_fck"),
+ DT_CLK(NULL, "mmu_fck", "mmu_fck"),
+ DT_CLK(NULL, "smartreflex0_fck", "smartreflex0_fck"),
+ DT_CLK(NULL, "smartreflex1_fck", "smartreflex1_fck"),
+ DT_CLK(NULL, "sha0_fck", "sha0_fck"),
+ DT_CLK(NULL, "aes0_fck", "aes0_fck"),
+ DT_CLK(NULL, "rng_fck", "rng_fck"),
+ DT_CLK(NULL, "timer1_fck", "timer1_fck"),
+ DT_CLK(NULL, "timer2_fck", "timer2_fck"),
+ DT_CLK(NULL, "timer3_fck", "timer3_fck"),
+ DT_CLK(NULL, "timer4_fck", "timer4_fck"),
+ DT_CLK(NULL, "timer5_fck", "timer5_fck"),
+ DT_CLK(NULL, "timer6_fck", "timer6_fck"),
+ DT_CLK(NULL, "timer7_fck", "timer7_fck"),
+ DT_CLK(NULL, "usbotg_fck", "usbotg_fck"),
+ DT_CLK(NULL, "ieee5000_fck", "ieee5000_fck"),
+ DT_CLK(NULL, "wdt1_fck", "wdt1_fck"),
+ DT_CLK(NULL, "l4_rtc_gclk", "l4_rtc_gclk"),
+ DT_CLK(NULL, "l3_gclk", "l3_gclk"),
+ DT_CLK(NULL, "dpll_core_m4_div2_ck", "dpll_core_m4_div2_ck"),
+ DT_CLK(NULL, "l4hs_gclk", "l4hs_gclk"),
+ DT_CLK(NULL, "l3s_gclk", "l3s_gclk"),
+ DT_CLK(NULL, "l4fw_gclk", "l4fw_gclk"),
+ DT_CLK(NULL, "l4ls_gclk", "l4ls_gclk"),
+ DT_CLK(NULL, "clk_24mhz", "clk_24mhz"),
+ DT_CLK(NULL, "sysclk_div_ck", "sysclk_div_ck"),
+ DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"),
+ DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"),
+ DT_CLK(NULL, "gpio0_dbclk_mux_ck", "gpio0_dbclk_mux_ck"),
+ DT_CLK(NULL, "gpio0_dbclk", "gpio0_dbclk"),
+ DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
+ DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"),
+ DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"),
+ DT_CLK(NULL, "lcd_gclk", "lcd_gclk"),
+ DT_CLK(NULL, "mmc_clk", "mmc_clk"),
+ DT_CLK(NULL, "gfx_fclk_clksel_ck", "gfx_fclk_clksel_ck"),
+ DT_CLK(NULL, "gfx_fck_div_ck", "gfx_fck_div_ck"),
+ DT_CLK(NULL, "sysclkout_pre_ck", "sysclkout_pre_ck"),
+ DT_CLK(NULL, "clkout2_div_ck", "clkout2_div_ck"),
+ DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"),
+ DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
+ DT_CLK(NULL, "dbg_sysclk_ck", "dbg_sysclk_ck"),
+ DT_CLK(NULL, "dbg_clka_ck", "dbg_clka_ck"),
+ DT_CLK(NULL, "stm_pmd_clock_mux_ck", "stm_pmd_clock_mux_ck"),
+ DT_CLK(NULL, "trace_pmd_clk_mux_ck", "trace_pmd_clk_mux_ck"),
+ DT_CLK(NULL, "stm_clk_div_ck", "stm_clk_div_ck"),
+ DT_CLK(NULL, "trace_clk_div_ck", "trace_clk_div_ck"),
+ DT_CLK(NULL, "clkout2_ck", "clkout2_ck"),
+ DT_CLK("48300200.ehrpwm", "tbclk", "ehrpwm0_tbclk"),
+ DT_CLK("48302200.ehrpwm", "tbclk", "ehrpwm1_tbclk"),
+ DT_CLK("48304200.ehrpwm", "tbclk", "ehrpwm2_tbclk"),
+ { .node_name = NULL },
+};
+
+static const char *enable_init_clks[] = {
+ "dpll_ddr_m2_ck",
+ "dpll_mpu_m2_ck",
+ "l3_gclk",
+ "l4hs_gclk",
+ "l4fw_gclk",
+ "l4ls_gclk",
+ /* Required for external peripherals like, Audio codecs */
+ "clkout2_ck",
+};
+
+int __init am33xx_clk_init(void)
+{
+ struct clk *clk1, *clk2;
+
+ of_clk_init(NULL);
+
+ ti_dt_clocks_register(am33xx_clks);
+
+ omap2_clk_disable_autoidle_all();
+
+ omap2_clk_enable_init_clocks(enable_init_clks,
+ ARRAY_SIZE(enable_init_clks));
+
+ /* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always
+ * physically present, in such a case HWMOD enabling of
+ * clock would be failure with default parent. And timer
+ * probe thinks clock is already enabled, this leads to
+ * crash upon accessing timer 3 & 6 registers in probe.
+ * Fix by setting parent of both these timers to master
+ * oscillator clock.
+ */
+
+ clk1 = clk_get_sys(NULL, "sys_clkin_ck");
+ clk2 = clk_get_sys(NULL, "timer3_fck");
+ clk_set_parent(clk2, clk1);
+
+ clk2 = clk_get_sys(NULL, "timer6_fck");
+ clk_set_parent(clk2, clk1);
+ /*
+ * The On-Chip 32K RC Osc clock is not an accurate clock-source as per
+ * the design/spec, so as a result, for example, timer which supposed
+ * to get expired @60Sec, but will expire somewhere ~@40Sec, which is
+ * not expected by any use-case, so change WDT1 clock source to PRCM
+ * 32KHz clock.
+ */
+ clk1 = clk_get_sys(NULL, "wdt1_fck");
+ clk2 = clk_get_sys(NULL, "clkdiv32k_ick");
+ clk_set_parent(clk1, clk2);
+
+ return 0;
+}
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 1b2dc51..0748581 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -208,6 +208,7 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
int omap2_clkops_enable_clkdm(struct clk_hw *hw);
void omap2_clkops_disable_clkdm(struct clk_hw *hw);
int omap2_clk_disable_autoidle_all(void);
+void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
unsigned long parent_rate);
int omap2_dflt_clk_enable(struct clk_hw *hw);
@@ -222,6 +223,7 @@ struct clk_div_table *ti_clk_get_div_table(struct device_node *node);
int omap4xxx_clk_init(void);
int omap5xxx_clk_init(void);
int dra7xx_clk_init(void);
+int am33xx_clk_init(void);
#ifdef CONFIG_OF
void of_ti_clk_allow_autoidle_all(void);
--
1.7.9.5
--
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^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 25/36] CLK: TI: add am33xx clock init file
@ 2013-09-25 8:48 ` Tero Kristo
0 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-arm-kernel
clk-33xx.c now contains the clock init functionality for am33xx, including
DT clock registration and adding of static clkdev entries.
This patch also moves the omap2_clk_enable_init_clocks declaration to
the driver include, as this is needed by the am33xx clock init code.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/mach-omap2/clock.h | 1 -
drivers/clk/ti/clk-33xx.c | 163 +++++++++++++++++++++++++++++++++++++++++++
include/linux/clk/ti.h | 2 +
3 files changed, 165 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/ti/clk-33xx.c
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 106c5c2..2e6cbeb 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -247,7 +247,6 @@ void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
void __iomem **idlest_reg,
u8 *idlest_bit, u8 *idlest_val);
int omap2_clk_enable_autoidle_all(void);
-void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
const char *core_ck_name,
diff --git a/drivers/clk/ti/clk-33xx.c b/drivers/clk/ti/clk-33xx.c
new file mode 100644
index 0000000..1c9ad1b
--- /dev/null
+++ b/drivers/clk/ti/clk-33xx.c
@@ -0,0 +1,163 @@
+/*
+ * AM33XX Clock init
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc
+ * Tero Kristo (t-kristo at ti.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/clk-provider.h>
+#include <linux/clk/ti.h>
+
+static struct ti_dt_clk am33xx_clks[] = {
+ DT_CLK(NULL, "clk_32768_ck", "clk_32768_ck"),
+ DT_CLK(NULL, "clk_rc32k_ck", "clk_rc32k_ck"),
+ DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
+ DT_CLK(NULL, "virt_24000000_ck", "virt_24000000_ck"),
+ DT_CLK(NULL, "virt_25000000_ck", "virt_25000000_ck"),
+ DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
+ DT_CLK(NULL, "sys_clkin_ck", "sys_clkin_ck"),
+ DT_CLK(NULL, "tclkin_ck", "tclkin_ck"),
+ DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
+ DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
+ DT_CLK(NULL, "dpll_core_m4_ck", "dpll_core_m4_ck"),
+ DT_CLK(NULL, "dpll_core_m5_ck", "dpll_core_m5_ck"),
+ DT_CLK(NULL, "dpll_core_m6_ck", "dpll_core_m6_ck"),
+ DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"),
+ DT_CLK("cpu0", NULL, "dpll_mpu_ck"),
+ DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"),
+ DT_CLK(NULL, "dpll_ddr_ck", "dpll_ddr_ck"),
+ DT_CLK(NULL, "dpll_ddr_m2_ck", "dpll_ddr_m2_ck"),
+ DT_CLK(NULL, "dpll_ddr_m2_div2_ck", "dpll_ddr_m2_div2_ck"),
+ DT_CLK(NULL, "dpll_disp_ck", "dpll_disp_ck"),
+ DT_CLK(NULL, "dpll_disp_m2_ck", "dpll_disp_m2_ck"),
+ DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"),
+ DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"),
+ DT_CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", "dpll_per_m2_div4_wkupdm_ck"),
+ DT_CLK(NULL, "dpll_per_m2_div4_ck", "dpll_per_m2_div4_ck"),
+ DT_CLK(NULL, "adc_tsc_fck", "adc_tsc_fck"),
+ DT_CLK(NULL, "cefuse_fck", "cefuse_fck"),
+ DT_CLK(NULL, "clkdiv32k_ck", "clkdiv32k_ck"),
+ DT_CLK(NULL, "clkdiv32k_ick", "clkdiv32k_ick"),
+ DT_CLK(NULL, "dcan0_fck", "dcan0_fck"),
+ DT_CLK("481cc000.d_can", NULL, "dcan0_fck"),
+ DT_CLK(NULL, "dcan1_fck", "dcan1_fck"),
+ DT_CLK("481d0000.d_can", NULL, "dcan1_fck"),
+ DT_CLK(NULL, "pruss_ocp_gclk", "pruss_ocp_gclk"),
+ DT_CLK(NULL, "mcasp0_fck", "mcasp0_fck"),
+ DT_CLK(NULL, "mcasp1_fck", "mcasp1_fck"),
+ DT_CLK(NULL, "mmu_fck", "mmu_fck"),
+ DT_CLK(NULL, "smartreflex0_fck", "smartreflex0_fck"),
+ DT_CLK(NULL, "smartreflex1_fck", "smartreflex1_fck"),
+ DT_CLK(NULL, "sha0_fck", "sha0_fck"),
+ DT_CLK(NULL, "aes0_fck", "aes0_fck"),
+ DT_CLK(NULL, "rng_fck", "rng_fck"),
+ DT_CLK(NULL, "timer1_fck", "timer1_fck"),
+ DT_CLK(NULL, "timer2_fck", "timer2_fck"),
+ DT_CLK(NULL, "timer3_fck", "timer3_fck"),
+ DT_CLK(NULL, "timer4_fck", "timer4_fck"),
+ DT_CLK(NULL, "timer5_fck", "timer5_fck"),
+ DT_CLK(NULL, "timer6_fck", "timer6_fck"),
+ DT_CLK(NULL, "timer7_fck", "timer7_fck"),
+ DT_CLK(NULL, "usbotg_fck", "usbotg_fck"),
+ DT_CLK(NULL, "ieee5000_fck", "ieee5000_fck"),
+ DT_CLK(NULL, "wdt1_fck", "wdt1_fck"),
+ DT_CLK(NULL, "l4_rtc_gclk", "l4_rtc_gclk"),
+ DT_CLK(NULL, "l3_gclk", "l3_gclk"),
+ DT_CLK(NULL, "dpll_core_m4_div2_ck", "dpll_core_m4_div2_ck"),
+ DT_CLK(NULL, "l4hs_gclk", "l4hs_gclk"),
+ DT_CLK(NULL, "l3s_gclk", "l3s_gclk"),
+ DT_CLK(NULL, "l4fw_gclk", "l4fw_gclk"),
+ DT_CLK(NULL, "l4ls_gclk", "l4ls_gclk"),
+ DT_CLK(NULL, "clk_24mhz", "clk_24mhz"),
+ DT_CLK(NULL, "sysclk_div_ck", "sysclk_div_ck"),
+ DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"),
+ DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"),
+ DT_CLK(NULL, "gpio0_dbclk_mux_ck", "gpio0_dbclk_mux_ck"),
+ DT_CLK(NULL, "gpio0_dbclk", "gpio0_dbclk"),
+ DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
+ DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"),
+ DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"),
+ DT_CLK(NULL, "lcd_gclk", "lcd_gclk"),
+ DT_CLK(NULL, "mmc_clk", "mmc_clk"),
+ DT_CLK(NULL, "gfx_fclk_clksel_ck", "gfx_fclk_clksel_ck"),
+ DT_CLK(NULL, "gfx_fck_div_ck", "gfx_fck_div_ck"),
+ DT_CLK(NULL, "sysclkout_pre_ck", "sysclkout_pre_ck"),
+ DT_CLK(NULL, "clkout2_div_ck", "clkout2_div_ck"),
+ DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"),
+ DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
+ DT_CLK(NULL, "dbg_sysclk_ck", "dbg_sysclk_ck"),
+ DT_CLK(NULL, "dbg_clka_ck", "dbg_clka_ck"),
+ DT_CLK(NULL, "stm_pmd_clock_mux_ck", "stm_pmd_clock_mux_ck"),
+ DT_CLK(NULL, "trace_pmd_clk_mux_ck", "trace_pmd_clk_mux_ck"),
+ DT_CLK(NULL, "stm_clk_div_ck", "stm_clk_div_ck"),
+ DT_CLK(NULL, "trace_clk_div_ck", "trace_clk_div_ck"),
+ DT_CLK(NULL, "clkout2_ck", "clkout2_ck"),
+ DT_CLK("48300200.ehrpwm", "tbclk", "ehrpwm0_tbclk"),
+ DT_CLK("48302200.ehrpwm", "tbclk", "ehrpwm1_tbclk"),
+ DT_CLK("48304200.ehrpwm", "tbclk", "ehrpwm2_tbclk"),
+ { .node_name = NULL },
+};
+
+static const char *enable_init_clks[] = {
+ "dpll_ddr_m2_ck",
+ "dpll_mpu_m2_ck",
+ "l3_gclk",
+ "l4hs_gclk",
+ "l4fw_gclk",
+ "l4ls_gclk",
+ /* Required for external peripherals like, Audio codecs */
+ "clkout2_ck",
+};
+
+int __init am33xx_clk_init(void)
+{
+ struct clk *clk1, *clk2;
+
+ of_clk_init(NULL);
+
+ ti_dt_clocks_register(am33xx_clks);
+
+ omap2_clk_disable_autoidle_all();
+
+ omap2_clk_enable_init_clocks(enable_init_clks,
+ ARRAY_SIZE(enable_init_clks));
+
+ /* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always
+ * physically present, in such a case HWMOD enabling of
+ * clock would be failure with default parent. And timer
+ * probe thinks clock is already enabled, this leads to
+ * crash upon accessing timer 3 & 6 registers in probe.
+ * Fix by setting parent of both these timers to master
+ * oscillator clock.
+ */
+
+ clk1 = clk_get_sys(NULL, "sys_clkin_ck");
+ clk2 = clk_get_sys(NULL, "timer3_fck");
+ clk_set_parent(clk2, clk1);
+
+ clk2 = clk_get_sys(NULL, "timer6_fck");
+ clk_set_parent(clk2, clk1);
+ /*
+ * The On-Chip 32K RC Osc clock is not an accurate clock-source as per
+ * the design/spec, so as a result, for example, timer which supposed
+ * to get expired @60Sec, but will expire somewhere ~@40Sec, which is
+ * not expected by any use-case, so change WDT1 clock source to PRCM
+ * 32KHz clock.
+ */
+ clk1 = clk_get_sys(NULL, "wdt1_fck");
+ clk2 = clk_get_sys(NULL, "clkdiv32k_ick");
+ clk_set_parent(clk1, clk2);
+
+ return 0;
+}
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 1b2dc51..0748581 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -208,6 +208,7 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
int omap2_clkops_enable_clkdm(struct clk_hw *hw);
void omap2_clkops_disable_clkdm(struct clk_hw *hw);
int omap2_clk_disable_autoidle_all(void);
+void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
unsigned long parent_rate);
int omap2_dflt_clk_enable(struct clk_hw *hw);
@@ -222,6 +223,7 @@ struct clk_div_table *ti_clk_get_div_table(struct device_node *node);
int omap4xxx_clk_init(void);
int omap5xxx_clk_init(void);
int dra7xx_clk_init(void);
+int am33xx_clk_init(void);
#ifdef CONFIG_OF
void of_ti_clk_allow_autoidle_all(void);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 26/36] ARM: AM33xx: remove old clock data and link in new clock init code
2013-09-25 8:48 ` Tero Kristo
@ 2013-09-25 8:48 ` Tero Kristo
-1 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-omap-u79uwXL29TY76Z2rM5mHXA, paul-DWxLp4Yu+b8AvxtiuMwx3w,
tony-4v6yS6AI5VpBDgjK7y7TUQ, nm-l0cyMroinI0, rnayak-l0cyMroinI0,
bcousson-rdvid1DuHRBWk0Htik3J/w,
mturquette-QSEj5FYQhm4dnm+yROfE0A
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
AM33xx clocks have now been moved to DT, thus remove the old data file
and use the new init code under OMAP clock driver.
Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
arch/arm/mach-omap2/Makefile | 1 -
arch/arm/mach-omap2/cclock33xx_data.c | 1064 ---------------------------------
drivers/clk/ti/Makefile | 1 +
3 files changed, 1 insertion(+), 1065 deletions(-)
delete mode 100644 arch/arm/mach-omap2/cclock33xx_data.c
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index f518360..020079e 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -187,7 +187,6 @@ obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o
obj-$(CONFIG_ARCH_OMAP4) += $(clock-common)
obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o
obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o
-obj-$(CONFIG_SOC_AM33XX) += cclock33xx_data.o
obj-$(CONFIG_SOC_OMAP5) += $(clock-common)
obj-$(CONFIG_SOC_OMAP5) += dpll3xxx.o dpll44xx.o
diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c
deleted file mode 100644
index 865d30e..0000000
--- a/arch/arm/mach-omap2/cclock33xx_data.c
+++ /dev/null
@@ -1,1064 +0,0 @@
-/*
- * AM33XX Clock data
- *
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
- * Vaibhav Hiremath <hvaibhav-l0cyMroinI0@public.gmane.org>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/clk-private.h>
-#include <linux/clkdev.h>
-#include <linux/io.h>
-
-#include "am33xx.h"
-#include "soc.h"
-#include "iomap.h"
-#include "clock.h"
-#include "control.h"
-#include "cm.h"
-#include "cm33xx.h"
-#include "cm-regbits-33xx.h"
-#include "prm.h"
-
-/* Modulemode control */
-#define AM33XX_MODULEMODE_HWCTRL_SHIFT 0
-#define AM33XX_MODULEMODE_SWCTRL_SHIFT 1
-
-/*LIST_HEAD(clocks);*/
-
-/* Root clocks */
-
-/* RTC 32k */
-DEFINE_CLK_FIXED_RATE(clk_32768_ck, CLK_IS_ROOT, 32768, 0x0);
-
-/* On-Chip 32KHz RC OSC */
-DEFINE_CLK_FIXED_RATE(clk_rc32k_ck, CLK_IS_ROOT, 32000, 0x0);
-
-/* Crystal input clks */
-DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_24000000_ck, CLK_IS_ROOT, 24000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_25000000_ck, CLK_IS_ROOT, 25000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
-
-/* Oscillator clock */
-/* 19.2, 24, 25 or 26 MHz */
-static const char *sys_clkin_ck_parents[] = {
- "virt_19200000_ck", "virt_24000000_ck", "virt_25000000_ck",
- "virt_26000000_ck",
-};
-
-/*
- * sys_clk in: input to the dpll and also used as funtional clock for,
- * adc_tsc, smartreflex0-1, timer1-7, mcasp0-1, dcan0-1, cefuse
- *
- */
-DEFINE_CLK_MUX(sys_clkin_ck, sys_clkin_ck_parents, NULL, 0x0,
- AM33XX_CTRL_REGADDR(AM33XX_CONTROL_STATUS),
- AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT,
- AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH,
- 0, NULL);
-
-/* External clock - 12 MHz */
-DEFINE_CLK_FIXED_RATE(tclkin_ck, CLK_IS_ROOT, 12000000, 0x0);
-
-/* Module clocks and DPLL outputs */
-
-/* DPLL_CORE */
-static struct dpll_data dpll_core_dd = {
- .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_CORE,
- .clk_bypass = &sys_clkin_ck,
- .clk_ref = &sys_clkin_ck,
- .control_reg = AM33XX_CM_CLKMODE_DPLL_CORE,
- .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
- .idlest_reg = AM33XX_CM_IDLEST_DPLL_CORE,
- .mult_mask = AM33XX_DPLL_MULT_MASK,
- .div1_mask = AM33XX_DPLL_DIV_MASK,
- .enable_mask = AM33XX_DPLL_EN_MASK,
- .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
- .max_multiplier = 2047,
- .max_divider = 128,
- .min_divider = 1,
-};
-
-/* CLKDCOLDO output */
-static const char *dpll_core_ck_parents[] = {
- "sys_clkin_ck",
-};
-
-static struct clk dpll_core_ck;
-
-static const struct clk_ops dpll_core_ck_ops = {
- .recalc_rate = &omap3_dpll_recalc,
- .get_parent = &omap2_init_dpll_parent,
-};
-
-static struct clk_hw_omap dpll_core_ck_hw = {
- .hw = {
- .clk = &dpll_core_ck,
- },
- .dpll_data = &dpll_core_dd,
- .ops = &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops);
-
-static const char *dpll_core_x2_ck_parents[] = {
- "dpll_core_ck",
-};
-
-static struct clk dpll_core_x2_ck;
-
-static const struct clk_ops dpll_x2_ck_ops = {
- .recalc_rate = &omap3_clkoutx2_recalc,
-};
-
-static struct clk_hw_omap dpll_core_x2_ck_hw = {
- .hw = {
- .clk = &dpll_core_x2_ck,
- },
- .flags = CLOCK_CLKOUTX2,
-};
-
-DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_x2_ck_ops);
-
-DEFINE_CLK_DIVIDER(dpll_core_m4_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
- 0x0, AM33XX_CM_DIV_M4_DPLL_CORE,
- AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT,
- AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH, CLK_DIVIDER_ONE_BASED,
- NULL);
-
-DEFINE_CLK_DIVIDER(dpll_core_m5_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
- 0x0, AM33XX_CM_DIV_M5_DPLL_CORE,
- AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT,
- AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH,
- CLK_DIVIDER_ONE_BASED, NULL);
-
-DEFINE_CLK_DIVIDER(dpll_core_m6_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
- 0x0, AM33XX_CM_DIV_M6_DPLL_CORE,
- AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT,
- AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH,
- CLK_DIVIDER_ONE_BASED, NULL);
-
-
-/* DPLL_MPU */
-static struct dpll_data dpll_mpu_dd = {
- .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_MPU,
- .clk_bypass = &sys_clkin_ck,
- .clk_ref = &sys_clkin_ck,
- .control_reg = AM33XX_CM_CLKMODE_DPLL_MPU,
- .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
- .idlest_reg = AM33XX_CM_IDLEST_DPLL_MPU,
- .mult_mask = AM33XX_DPLL_MULT_MASK,
- .div1_mask = AM33XX_DPLL_DIV_MASK,
- .enable_mask = AM33XX_DPLL_EN_MASK,
- .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
- .max_multiplier = 2047,
- .max_divider = 128,
- .min_divider = 1,
-};
-
-/* CLKOUT: fdpll/M2 */
-static struct clk dpll_mpu_ck;
-
-static const struct clk_ops dpll_mpu_ck_ops = {
- .enable = &omap3_noncore_dpll_enable,
- .disable = &omap3_noncore_dpll_disable,
- .recalc_rate = &omap3_dpll_recalc,
- .round_rate = &omap2_dpll_round_rate,
- .set_rate = &omap3_noncore_dpll_set_rate,
- .get_parent = &omap2_init_dpll_parent,
-};
-
-static struct clk_hw_omap dpll_mpu_ck_hw = {
- .hw = {
- .clk = &dpll_mpu_ck,
- },
- .dpll_data = &dpll_mpu_dd,
- .ops = &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_core_ck_parents, dpll_mpu_ck_ops);
-
-/*
- * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
- * and ALT_CLK1/2)
- */
-DEFINE_CLK_DIVIDER(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck,
- 0x0, AM33XX_CM_DIV_M2_DPLL_MPU, AM33XX_DPLL_CLKOUT_DIV_SHIFT,
- AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
-
-/* DPLL_DDR */
-static struct dpll_data dpll_ddr_dd = {
- .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_DDR,
- .clk_bypass = &sys_clkin_ck,
- .clk_ref = &sys_clkin_ck,
- .control_reg = AM33XX_CM_CLKMODE_DPLL_DDR,
- .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
- .idlest_reg = AM33XX_CM_IDLEST_DPLL_DDR,
- .mult_mask = AM33XX_DPLL_MULT_MASK,
- .div1_mask = AM33XX_DPLL_DIV_MASK,
- .enable_mask = AM33XX_DPLL_EN_MASK,
- .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
- .max_multiplier = 2047,
- .max_divider = 128,
- .min_divider = 1,
-};
-
-/* CLKOUT: fdpll/M2 */
-static struct clk dpll_ddr_ck;
-
-static const struct clk_ops dpll_ddr_ck_ops = {
- .recalc_rate = &omap3_dpll_recalc,
- .get_parent = &omap2_init_dpll_parent,
- .round_rate = &omap2_dpll_round_rate,
- .set_rate = &omap3_noncore_dpll_set_rate,
-};
-
-static struct clk_hw_omap dpll_ddr_ck_hw = {
- .hw = {
- .clk = &dpll_ddr_ck,
- },
- .dpll_data = &dpll_ddr_dd,
- .ops = &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_ddr_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
-
-/*
- * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
- * and ALT_CLK1/2)
- */
-DEFINE_CLK_DIVIDER(dpll_ddr_m2_ck, "dpll_ddr_ck", &dpll_ddr_ck,
- 0x0, AM33XX_CM_DIV_M2_DPLL_DDR,
- AM33XX_DPLL_CLKOUT_DIV_SHIFT, AM33XX_DPLL_CLKOUT_DIV_WIDTH,
- CLK_DIVIDER_ONE_BASED, NULL);
-
-/* emif_fck functional clock */
-DEFINE_CLK_FIXED_FACTOR(dpll_ddr_m2_div2_ck, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck,
- 0x0, 1, 2);
-
-/* DPLL_DISP */
-static struct dpll_data dpll_disp_dd = {
- .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_DISP,
- .clk_bypass = &sys_clkin_ck,
- .clk_ref = &sys_clkin_ck,
- .control_reg = AM33XX_CM_CLKMODE_DPLL_DISP,
- .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
- .idlest_reg = AM33XX_CM_IDLEST_DPLL_DISP,
- .mult_mask = AM33XX_DPLL_MULT_MASK,
- .div1_mask = AM33XX_DPLL_DIV_MASK,
- .enable_mask = AM33XX_DPLL_EN_MASK,
- .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
- .max_multiplier = 2047,
- .max_divider = 128,
- .min_divider = 1,
-};
-
-/* CLKOUT: fdpll/M2 */
-static struct clk dpll_disp_ck;
-
-static struct clk_hw_omap dpll_disp_ck_hw = {
- .hw = {
- .clk = &dpll_disp_ck,
- },
- .dpll_data = &dpll_disp_dd,
- .ops = &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_disp_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
-
-/*
- * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
- * and ALT_CLK1/2)
- */
-DEFINE_CLK_DIVIDER(dpll_disp_m2_ck, "dpll_disp_ck", &dpll_disp_ck,
- CLK_SET_RATE_PARENT, AM33XX_CM_DIV_M2_DPLL_DISP,
- AM33XX_DPLL_CLKOUT_DIV_SHIFT, AM33XX_DPLL_CLKOUT_DIV_WIDTH,
- CLK_DIVIDER_ONE_BASED, NULL);
-
-/* DPLL_PER */
-static struct dpll_data dpll_per_dd = {
- .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_PERIPH,
- .clk_bypass = &sys_clkin_ck,
- .clk_ref = &sys_clkin_ck,
- .control_reg = AM33XX_CM_CLKMODE_DPLL_PER,
- .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
- .idlest_reg = AM33XX_CM_IDLEST_DPLL_PER,
- .mult_mask = AM33XX_DPLL_MULT_PERIPH_MASK,
- .div1_mask = AM33XX_DPLL_PER_DIV_MASK,
- .enable_mask = AM33XX_DPLL_EN_MASK,
- .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
- .max_multiplier = 2047,
- .max_divider = 128,
- .min_divider = 1,
- .flags = DPLL_J_TYPE,
-};
-
-/* CLKDCOLDO */
-static struct clk dpll_per_ck;
-
-static struct clk_hw_omap dpll_per_ck_hw = {
- .hw = {
- .clk = &dpll_per_ck,
- },
- .dpll_data = &dpll_per_dd,
- .ops = &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_per_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
-
-/* CLKOUT: fdpll/M2 */
-DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0,
- AM33XX_CM_DIV_M2_DPLL_PER, AM33XX_DPLL_CLKOUT_DIV_SHIFT,
- AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED,
- NULL);
-
-DEFINE_CLK_FIXED_FACTOR(dpll_per_m2_div4_wkupdm_ck, "dpll_per_m2_ck",
- &dpll_per_m2_ck, 0x0, 1, 4);
-
-DEFINE_CLK_FIXED_FACTOR(dpll_per_m2_div4_ck, "dpll_per_m2_ck",
- &dpll_per_m2_ck, 0x0, 1, 4);
-
-DEFINE_CLK_FIXED_FACTOR(dpll_core_m4_div2_ck, "dpll_core_m4_ck",
- &dpll_core_m4_ck, 0x0, 1, 2);
-
-DEFINE_CLK_FIXED_FACTOR(l4_rtc_gclk, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0,
- 1, 2);
-
-DEFINE_CLK_FIXED_FACTOR(clk_24mhz, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1,
- 8);
-
-/*
- * Below clock nodes describes clockdomains derived out
- * of core clock.
- */
-static const struct clk_ops clk_ops_null = {
-};
-
-static const char *l3_gclk_parents[] = {
- "dpll_core_m4_ck"
-};
-
-static struct clk l3_gclk;
-DEFINE_STRUCT_CLK_HW_OMAP(l3_gclk, NULL);
-DEFINE_STRUCT_CLK(l3_gclk, l3_gclk_parents, clk_ops_null);
-
-static struct clk l4hs_gclk;
-DEFINE_STRUCT_CLK_HW_OMAP(l4hs_gclk, NULL);
-DEFINE_STRUCT_CLK(l4hs_gclk, l3_gclk_parents, clk_ops_null);
-
-static const char *l3s_gclk_parents[] = {
- "dpll_core_m4_div2_ck"
-};
-
-static struct clk l3s_gclk;
-DEFINE_STRUCT_CLK_HW_OMAP(l3s_gclk, NULL);
-DEFINE_STRUCT_CLK(l3s_gclk, l3s_gclk_parents, clk_ops_null);
-
-static struct clk l4fw_gclk;
-DEFINE_STRUCT_CLK_HW_OMAP(l4fw_gclk, NULL);
-DEFINE_STRUCT_CLK(l4fw_gclk, l3s_gclk_parents, clk_ops_null);
-
-static struct clk l4ls_gclk;
-DEFINE_STRUCT_CLK_HW_OMAP(l4ls_gclk, NULL);
-DEFINE_STRUCT_CLK(l4ls_gclk, l3s_gclk_parents, clk_ops_null);
-
-static struct clk sysclk_div_ck;
-DEFINE_STRUCT_CLK_HW_OMAP(sysclk_div_ck, NULL);
-DEFINE_STRUCT_CLK(sysclk_div_ck, l3_gclk_parents, clk_ops_null);
-
-/*
- * In order to match the clock domain with hwmod clockdomain entry,
- * separate clock nodes is required for the modules which are
- * directly getting their funtioncal clock from sys_clkin.
- */
-static struct clk adc_tsc_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(adc_tsc_fck, NULL);
-DEFINE_STRUCT_CLK(adc_tsc_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk dcan0_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(dcan0_fck, NULL);
-DEFINE_STRUCT_CLK(dcan0_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk dcan1_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(dcan1_fck, NULL);
-DEFINE_STRUCT_CLK(dcan1_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk mcasp0_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(mcasp0_fck, NULL);
-DEFINE_STRUCT_CLK(mcasp0_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk mcasp1_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(mcasp1_fck, NULL);
-DEFINE_STRUCT_CLK(mcasp1_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk smartreflex0_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(smartreflex0_fck, NULL);
-DEFINE_STRUCT_CLK(smartreflex0_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk smartreflex1_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(smartreflex1_fck, NULL);
-DEFINE_STRUCT_CLK(smartreflex1_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk sha0_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(sha0_fck, NULL);
-DEFINE_STRUCT_CLK(sha0_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk aes0_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(aes0_fck, NULL);
-DEFINE_STRUCT_CLK(aes0_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk rng_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(rng_fck, NULL);
-DEFINE_STRUCT_CLK(rng_fck, dpll_core_ck_parents, clk_ops_null);
-
-/*
- * Modules clock nodes
- *
- * The following clock leaf nodes are added for the moment because:
- *
- * - hwmod data is not present for these modules, either hwmod
- * control is not required or its not populated.
- * - Driver code is not yet migrated to use hwmod/runtime pm
- * - Modules outside kernel access (to disable them by default)
- *
- * - mmu (gfx domain)
- * - cefuse
- * - usbotg_fck (its additional clock and not really a modulemode)
- * - ieee5000
- */
-
-DEFINE_CLK_GATE(mmu_fck, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0,
- AM33XX_CM_GFX_MMUDATA_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
- 0x0, NULL);
-
-DEFINE_CLK_GATE(cefuse_fck, "sys_clkin_ck", &sys_clkin_ck, 0x0,
- AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
- 0x0, NULL);
-
-/*
- * clkdiv32 is generated from fixed division of 732.4219
- */
-DEFINE_CLK_FIXED_FACTOR(clkdiv32k_ck, "clk_24mhz", &clk_24mhz, 0x0, 1, 732);
-
-static struct clk clkdiv32k_ick;
-
-static const char *clkdiv32k_ick_parent_names[] = {
- "clkdiv32k_ck",
-};
-
-static const struct clk_ops clkdiv32k_ick_ops = {
- .enable = &omap2_dflt_clk_enable,
- .disable = &omap2_dflt_clk_disable,
- .is_enabled = &omap2_dflt_clk_is_enabled,
- .init = &omap2_init_clk_clkdm,
-};
-
-static struct clk_hw_omap clkdiv32k_ick_hw = {
- .hw = {
- .clk = &clkdiv32k_ick,
- },
- .enable_reg = AM33XX_CM_PER_CLKDIV32K_CLKCTRL,
- .enable_bit = AM33XX_MODULEMODE_SWCTRL_SHIFT,
- .clkdm_name = "clk_24mhz_clkdm",
-};
-
-DEFINE_STRUCT_CLK(clkdiv32k_ick, clkdiv32k_ick_parent_names, clkdiv32k_ick_ops);
-
-/* "usbotg_fck" is an additional clock and not really a modulemode */
-DEFINE_CLK_GATE(usbotg_fck, "dpll_per_ck", &dpll_per_ck, 0x0,
- AM33XX_CM_CLKDCOLDO_DPLL_PER, AM33XX_ST_DPLL_CLKDCOLDO_SHIFT,
- 0x0, NULL);
-
-DEFINE_CLK_GATE(ieee5000_fck, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck,
- 0x0, AM33XX_CM_PER_IEEE5000_CLKCTRL,
- AM33XX_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-/* Timers */
-static const struct clksel timer1_clkmux_sel[] = {
- { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
- { .parent = &clkdiv32k_ick, .rates = div_1_1_rates },
- { .parent = &tclkin_ck, .rates = div_1_2_rates },
- { .parent = &clk_rc32k_ck, .rates = div_1_3_rates },
- { .parent = &clk_32768_ck, .rates = div_1_4_rates },
- { .parent = NULL },
-};
-
-static const char *timer1_ck_parents[] = {
- "sys_clkin_ck", "clkdiv32k_ick", "tclkin_ck", "clk_rc32k_ck",
- "clk_32768_ck",
-};
-
-static struct clk timer1_fck;
-
-static const struct clk_ops timer1_fck_ops = {
- .recalc_rate = &omap2_clksel_recalc,
- .get_parent = &omap2_clksel_find_parent_index,
- .set_parent = &omap2_clksel_set_parent,
- .init = &omap2_init_clk_clkdm,
-};
-
-static struct clk_hw_omap timer1_fck_hw = {
- .hw = {
- .clk = &timer1_fck,
- },
- .clkdm_name = "l4ls_clkdm",
- .clksel = timer1_clkmux_sel,
- .clksel_reg = AM33XX_CLKSEL_TIMER1MS_CLK,
- .clksel_mask = AM33XX_CLKSEL_0_2_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer1_fck, timer1_ck_parents, timer1_fck_ops);
-
-static const struct clksel timer2_to_7_clk_sel[] = {
- { .parent = &tclkin_ck, .rates = div_1_0_rates },
- { .parent = &sys_clkin_ck, .rates = div_1_1_rates },
- { .parent = &clkdiv32k_ick, .rates = div_1_2_rates },
- { .parent = NULL },
-};
-
-static const char *timer2_to_7_ck_parents[] = {
- "tclkin_ck", "sys_clkin_ck", "clkdiv32k_ick",
-};
-
-static struct clk timer2_fck;
-
-static struct clk_hw_omap timer2_fck_hw = {
- .hw = {
- .clk = &timer2_fck,
- },
- .clkdm_name = "l4ls_clkdm",
- .clksel = timer2_to_7_clk_sel,
- .clksel_reg = AM33XX_CLKSEL_TIMER2_CLK,
- .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer2_fck, timer2_to_7_ck_parents, timer1_fck_ops);
-
-static struct clk timer3_fck;
-
-static struct clk_hw_omap timer3_fck_hw = {
- .hw = {
- .clk = &timer3_fck,
- },
- .clkdm_name = "l4ls_clkdm",
- .clksel = timer2_to_7_clk_sel,
- .clksel_reg = AM33XX_CLKSEL_TIMER3_CLK,
- .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer3_fck, timer2_to_7_ck_parents, timer1_fck_ops);
-
-static struct clk timer4_fck;
-
-static struct clk_hw_omap timer4_fck_hw = {
- .hw = {
- .clk = &timer4_fck,
- },
- .clkdm_name = "l4ls_clkdm",
- .clksel = timer2_to_7_clk_sel,
- .clksel_reg = AM33XX_CLKSEL_TIMER4_CLK,
- .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer4_fck, timer2_to_7_ck_parents, timer1_fck_ops);
-
-static struct clk timer5_fck;
-
-static struct clk_hw_omap timer5_fck_hw = {
- .hw = {
- .clk = &timer5_fck,
- },
- .clkdm_name = "l4ls_clkdm",
- .clksel = timer2_to_7_clk_sel,
- .clksel_reg = AM33XX_CLKSEL_TIMER5_CLK,
- .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer5_fck, timer2_to_7_ck_parents, timer1_fck_ops);
-
-static struct clk timer6_fck;
-
-static struct clk_hw_omap timer6_fck_hw = {
- .hw = {
- .clk = &timer6_fck,
- },
- .clkdm_name = "l4ls_clkdm",
- .clksel = timer2_to_7_clk_sel,
- .clksel_reg = AM33XX_CLKSEL_TIMER6_CLK,
- .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer6_fck, timer2_to_7_ck_parents, timer1_fck_ops);
-
-static struct clk timer7_fck;
-
-static struct clk_hw_omap timer7_fck_hw = {
- .hw = {
- .clk = &timer7_fck,
- },
- .clkdm_name = "l4ls_clkdm",
- .clksel = timer2_to_7_clk_sel,
- .clksel_reg = AM33XX_CLKSEL_TIMER7_CLK,
- .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer7_fck, timer2_to_7_ck_parents, timer1_fck_ops);
-
-DEFINE_CLK_FIXED_FACTOR(cpsw_125mhz_gclk,
- "dpll_core_m5_ck",
- &dpll_core_m5_ck,
- 0x0,
- 1, 2);
-
-static const struct clk_ops cpsw_fck_ops = {
- .recalc_rate = &omap2_clksel_recalc,
- .get_parent = &omap2_clksel_find_parent_index,
- .set_parent = &omap2_clksel_set_parent,
-};
-
-static const struct clksel cpsw_cpts_rft_clkmux_sel[] = {
- { .parent = &dpll_core_m5_ck, .rates = div_1_0_rates },
- { .parent = &dpll_core_m4_ck, .rates = div_1_1_rates },
- { .parent = NULL },
-};
-
-static const char *cpsw_cpts_rft_ck_parents[] = {
- "dpll_core_m5_ck", "dpll_core_m4_ck",
-};
-
-static struct clk cpsw_cpts_rft_clk;
-
-static struct clk_hw_omap cpsw_cpts_rft_clk_hw = {
- .hw = {
- .clk = &cpsw_cpts_rft_clk,
- },
- .clkdm_name = "cpsw_125mhz_clkdm",
- .clksel = cpsw_cpts_rft_clkmux_sel,
- .clksel_reg = AM33XX_CM_CPTS_RFT_CLKSEL,
- .clksel_mask = AM33XX_CLKSEL_0_0_MASK,
-};
-
-DEFINE_STRUCT_CLK(cpsw_cpts_rft_clk, cpsw_cpts_rft_ck_parents, cpsw_fck_ops);
-
-
-/* gpio */
-static const char *gpio0_ck_parents[] = {
- "clk_rc32k_ck", "clk_32768_ck", "clkdiv32k_ick",
-};
-
-static const struct clksel gpio0_dbclk_mux_sel[] = {
- { .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
- { .parent = &clk_32768_ck, .rates = div_1_1_rates },
- { .parent = &clkdiv32k_ick, .rates = div_1_2_rates },
- { .parent = NULL },
-};
-
-static const struct clk_ops gpio_fck_ops = {
- .recalc_rate = &omap2_clksel_recalc,
- .get_parent = &omap2_clksel_find_parent_index,
- .set_parent = &omap2_clksel_set_parent,
- .init = &omap2_init_clk_clkdm,
-};
-
-static struct clk gpio0_dbclk_mux_ck;
-
-static struct clk_hw_omap gpio0_dbclk_mux_ck_hw = {
- .hw = {
- .clk = &gpio0_dbclk_mux_ck,
- },
- .clkdm_name = "l4_wkup_clkdm",
- .clksel = gpio0_dbclk_mux_sel,
- .clksel_reg = AM33XX_CLKSEL_GPIO0_DBCLK,
- .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(gpio0_dbclk_mux_ck, gpio0_ck_parents, gpio_fck_ops);
-
-DEFINE_CLK_GATE(gpio0_dbclk, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck, 0x0,
- AM33XX_CM_WKUP_GPIO0_CLKCTRL,
- AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(gpio1_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
- AM33XX_CM_PER_GPIO1_CLKCTRL,
- AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(gpio2_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
- AM33XX_CM_PER_GPIO2_CLKCTRL,
- AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(gpio3_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
- AM33XX_CM_PER_GPIO3_CLKCTRL,
- AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT, 0x0, NULL);
-
-
-static const char *pruss_ck_parents[] = {
- "l3_gclk", "dpll_disp_m2_ck",
-};
-
-static const struct clksel pruss_ocp_clk_mux_sel[] = {
- { .parent = &l3_gclk, .rates = div_1_0_rates },
- { .parent = &dpll_disp_m2_ck, .rates = div_1_1_rates },
- { .parent = NULL },
-};
-
-static struct clk pruss_ocp_gclk;
-
-static struct clk_hw_omap pruss_ocp_gclk_hw = {
- .hw = {
- .clk = &pruss_ocp_gclk,
- },
- .clkdm_name = "pruss_ocp_clkdm",
- .clksel = pruss_ocp_clk_mux_sel,
- .clksel_reg = AM33XX_CLKSEL_PRUSS_OCP_CLK,
- .clksel_mask = AM33XX_CLKSEL_0_0_MASK,
-};
-
-DEFINE_STRUCT_CLK(pruss_ocp_gclk, pruss_ck_parents, gpio_fck_ops);
-
-static const char *lcd_ck_parents[] = {
- "dpll_disp_m2_ck", "dpll_core_m5_ck", "dpll_per_m2_ck",
-};
-
-static const struct clksel lcd_clk_mux_sel[] = {
- { .parent = &dpll_disp_m2_ck, .rates = div_1_0_rates },
- { .parent = &dpll_core_m5_ck, .rates = div_1_1_rates },
- { .parent = &dpll_per_m2_ck, .rates = div_1_2_rates },
- { .parent = NULL },
-};
-
-static struct clk lcd_gclk;
-
-static struct clk_hw_omap lcd_gclk_hw = {
- .hw = {
- .clk = &lcd_gclk,
- },
- .clkdm_name = "lcdc_clkdm",
- .clksel = lcd_clk_mux_sel,
- .clksel_reg = AM33XX_CLKSEL_LCDC_PIXEL_CLK,
- .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK_FLAGS(lcd_gclk, lcd_ck_parents,
- gpio_fck_ops, CLK_SET_RATE_PARENT);
-
-DEFINE_CLK_FIXED_FACTOR(mmc_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1, 2);
-
-static const char *gfx_ck_parents[] = {
- "dpll_core_m4_ck", "dpll_per_m2_ck",
-};
-
-static const struct clksel gfx_clksel_sel[] = {
- { .parent = &dpll_core_m4_ck, .rates = div_1_0_rates },
- { .parent = &dpll_per_m2_ck, .rates = div_1_1_rates },
- { .parent = NULL },
-};
-
-static struct clk gfx_fclk_clksel_ck;
-
-static struct clk_hw_omap gfx_fclk_clksel_ck_hw = {
- .hw = {
- .clk = &gfx_fclk_clksel_ck,
- },
- .clksel = gfx_clksel_sel,
- .clksel_reg = AM33XX_CLKSEL_GFX_FCLK,
- .clksel_mask = AM33XX_CLKSEL_GFX_FCLK_MASK,
-};
-
-DEFINE_STRUCT_CLK(gfx_fclk_clksel_ck, gfx_ck_parents, gpio_fck_ops);
-
-static const struct clk_div_table div_1_0_2_1_rates[] = {
- { .div = 1, .val = 0, },
- { .div = 2, .val = 1, },
- { .div = 0 },
-};
-
-DEFINE_CLK_DIVIDER_TABLE(gfx_fck_div_ck, "gfx_fclk_clksel_ck",
- &gfx_fclk_clksel_ck, 0x0, AM33XX_CLKSEL_GFX_FCLK,
- AM33XX_CLKSEL_0_0_SHIFT, AM33XX_CLKSEL_0_0_WIDTH,
- 0x0, div_1_0_2_1_rates, NULL);
-
-static const char *sysclkout_ck_parents[] = {
- "clk_32768_ck", "l3_gclk", "dpll_ddr_m2_ck", "dpll_per_m2_ck",
- "lcd_gclk",
-};
-
-static const struct clksel sysclkout_pre_sel[] = {
- { .parent = &clk_32768_ck, .rates = div_1_0_rates },
- { .parent = &l3_gclk, .rates = div_1_1_rates },
- { .parent = &dpll_ddr_m2_ck, .rates = div_1_2_rates },
- { .parent = &dpll_per_m2_ck, .rates = div_1_3_rates },
- { .parent = &lcd_gclk, .rates = div_1_4_rates },
- { .parent = NULL },
-};
-
-static struct clk sysclkout_pre_ck;
-
-static struct clk_hw_omap sysclkout_pre_ck_hw = {
- .hw = {
- .clk = &sysclkout_pre_ck,
- },
- .clksel = sysclkout_pre_sel,
- .clksel_reg = AM33XX_CM_CLKOUT_CTRL,
- .clksel_mask = AM33XX_CLKOUT2SOURCE_MASK,
-};
-
-DEFINE_STRUCT_CLK(sysclkout_pre_ck, sysclkout_ck_parents, gpio_fck_ops);
-
-/* Divide by 8 clock rates with default clock is 1/1*/
-static const struct clk_div_table div8_rates[] = {
- { .div = 1, .val = 0, },
- { .div = 2, .val = 1, },
- { .div = 3, .val = 2, },
- { .div = 4, .val = 3, },
- { .div = 5, .val = 4, },
- { .div = 6, .val = 5, },
- { .div = 7, .val = 6, },
- { .div = 8, .val = 7, },
- { .div = 0 },
-};
-
-DEFINE_CLK_DIVIDER_TABLE(clkout2_div_ck, "sysclkout_pre_ck", &sysclkout_pre_ck,
- 0x0, AM33XX_CM_CLKOUT_CTRL, AM33XX_CLKOUT2DIV_SHIFT,
- AM33XX_CLKOUT2DIV_WIDTH, 0x0, div8_rates, NULL);
-
-DEFINE_CLK_GATE(clkout2_ck, "clkout2_div_ck", &clkout2_div_ck, 0x0,
- AM33XX_CM_CLKOUT_CTRL, AM33XX_CLKOUT2EN_SHIFT, 0x0, NULL);
-
-static const char *wdt_ck_parents[] = {
- "clk_rc32k_ck", "clkdiv32k_ick",
-};
-
-static const struct clksel wdt_clkmux_sel[] = {
- { .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
- { .parent = &clkdiv32k_ick, .rates = div_1_1_rates },
- { .parent = NULL },
-};
-
-static struct clk wdt1_fck;
-
-static struct clk_hw_omap wdt1_fck_hw = {
- .hw = {
- .clk = &wdt1_fck,
- },
- .clkdm_name = "l4_wkup_clkdm",
- .clksel = wdt_clkmux_sel,
- .clksel_reg = AM33XX_CLKSEL_WDT1_CLK,
- .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(wdt1_fck, wdt_ck_parents, gpio_fck_ops);
-
-static const char *pwmss_clk_parents[] = {
- "dpll_per_m2_ck",
-};
-
-static const struct clk_ops ehrpwm_tbclk_ops = {
- .enable = &omap2_dflt_clk_enable,
- .disable = &omap2_dflt_clk_disable,
-};
-
-DEFINE_CLK_OMAP_MUX_GATE(ehrpwm0_tbclk, "l4ls_clkdm",
- NULL, NULL, 0,
- AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
- AM33XX_PWMSS0_TBCLKEN_SHIFT,
- NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
-
-DEFINE_CLK_OMAP_MUX_GATE(ehrpwm1_tbclk, "l4ls_clkdm",
- NULL, NULL, 0,
- AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
- AM33XX_PWMSS1_TBCLKEN_SHIFT,
- NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
-
-DEFINE_CLK_OMAP_MUX_GATE(ehrpwm2_tbclk, "l4ls_clkdm",
- NULL, NULL, 0,
- AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
- AM33XX_PWMSS2_TBCLKEN_SHIFT,
- NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
-
-/*
- * debugss optional clocks
- */
-DEFINE_CLK_GATE(dbg_sysclk_ck, "sys_clkin_ck", &sys_clkin_ck,
- 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
- AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(dbg_clka_ck, "dpll_core_m4_ck", &dpll_core_m4_ck,
- 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
- AM33XX_OPTCLK_DEBUG_CLKA_SHIFT, 0x0, NULL);
-
-static const char *stm_pmd_clock_mux_ck_parents[] = {
- "dbg_sysclk_ck", "dbg_clka_ck",
-};
-
-DEFINE_CLK_MUX(stm_pmd_clock_mux_ck, stm_pmd_clock_mux_ck_parents, NULL, 0x0,
- AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, AM33XX_STM_PMD_CLKSEL_SHIFT,
- AM33XX_STM_PMD_CLKSEL_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_MUX(trace_pmd_clk_mux_ck, stm_pmd_clock_mux_ck_parents, NULL, 0x0,
- AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
- AM33XX_TRC_PMD_CLKSEL_SHIFT,
- AM33XX_TRC_PMD_CLKSEL_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_DIVIDER(stm_clk_div_ck, "stm_pmd_clock_mux_ck",
- &stm_pmd_clock_mux_ck, 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
- AM33XX_STM_PMD_CLKDIVSEL_SHIFT,
- AM33XX_STM_PMD_CLKDIVSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
- NULL);
-
-DEFINE_CLK_DIVIDER(trace_clk_div_ck, "trace_pmd_clk_mux_ck",
- &trace_pmd_clk_mux_ck, 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
- AM33XX_TRC_PMD_CLKDIVSEL_SHIFT,
- AM33XX_TRC_PMD_CLKDIVSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
- NULL);
-
-/*
- * clkdev
- */
-static struct omap_clk am33xx_clks[] = {
- CLK(NULL, "clk_32768_ck", &clk_32768_ck),
- CLK(NULL, "clk_rc32k_ck", &clk_rc32k_ck),
- CLK(NULL, "virt_19200000_ck", &virt_19200000_ck),
- CLK(NULL, "virt_24000000_ck", &virt_24000000_ck),
- CLK(NULL, "virt_25000000_ck", &virt_25000000_ck),
- CLK(NULL, "virt_26000000_ck", &virt_26000000_ck),
- CLK(NULL, "sys_clkin_ck", &sys_clkin_ck),
- CLK(NULL, "tclkin_ck", &tclkin_ck),
- CLK(NULL, "dpll_core_ck", &dpll_core_ck),
- CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck),
- CLK(NULL, "dpll_core_m4_ck", &dpll_core_m4_ck),
- CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck),
- CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck),
- CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck),
- CLK("cpu0", NULL, &dpll_mpu_ck),
- CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck),
- CLK(NULL, "dpll_ddr_ck", &dpll_ddr_ck),
- CLK(NULL, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck),
- CLK(NULL, "dpll_ddr_m2_div2_ck", &dpll_ddr_m2_div2_ck),
- CLK(NULL, "dpll_disp_ck", &dpll_disp_ck),
- CLK(NULL, "dpll_disp_m2_ck", &dpll_disp_m2_ck),
- CLK(NULL, "dpll_per_ck", &dpll_per_ck),
- CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck),
- CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", &dpll_per_m2_div4_wkupdm_ck),
- CLK(NULL, "dpll_per_m2_div4_ck", &dpll_per_m2_div4_ck),
- CLK(NULL, "adc_tsc_fck", &adc_tsc_fck),
- CLK(NULL, "cefuse_fck", &cefuse_fck),
- CLK(NULL, "clkdiv32k_ck", &clkdiv32k_ck),
- CLK(NULL, "clkdiv32k_ick", &clkdiv32k_ick),
- CLK(NULL, "dcan0_fck", &dcan0_fck),
- CLK("481cc000.d_can", NULL, &dcan0_fck),
- CLK(NULL, "dcan1_fck", &dcan1_fck),
- CLK("481d0000.d_can", NULL, &dcan1_fck),
- CLK(NULL, "pruss_ocp_gclk", &pruss_ocp_gclk),
- CLK(NULL, "mcasp0_fck", &mcasp0_fck),
- CLK(NULL, "mcasp1_fck", &mcasp1_fck),
- CLK(NULL, "mmu_fck", &mmu_fck),
- CLK(NULL, "smartreflex0_fck", &smartreflex0_fck),
- CLK(NULL, "smartreflex1_fck", &smartreflex1_fck),
- CLK(NULL, "sha0_fck", &sha0_fck),
- CLK(NULL, "aes0_fck", &aes0_fck),
- CLK(NULL, "rng_fck", &rng_fck),
- CLK(NULL, "timer1_fck", &timer1_fck),
- CLK(NULL, "timer2_fck", &timer2_fck),
- CLK(NULL, "timer3_fck", &timer3_fck),
- CLK(NULL, "timer4_fck", &timer4_fck),
- CLK(NULL, "timer5_fck", &timer5_fck),
- CLK(NULL, "timer6_fck", &timer6_fck),
- CLK(NULL, "timer7_fck", &timer7_fck),
- CLK(NULL, "usbotg_fck", &usbotg_fck),
- CLK(NULL, "ieee5000_fck", &ieee5000_fck),
- CLK(NULL, "wdt1_fck", &wdt1_fck),
- CLK(NULL, "l4_rtc_gclk", &l4_rtc_gclk),
- CLK(NULL, "l3_gclk", &l3_gclk),
- CLK(NULL, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck),
- CLK(NULL, "l4hs_gclk", &l4hs_gclk),
- CLK(NULL, "l3s_gclk", &l3s_gclk),
- CLK(NULL, "l4fw_gclk", &l4fw_gclk),
- CLK(NULL, "l4ls_gclk", &l4ls_gclk),
- CLK(NULL, "clk_24mhz", &clk_24mhz),
- CLK(NULL, "sysclk_div_ck", &sysclk_div_ck),
- CLK(NULL, "cpsw_125mhz_gclk", &cpsw_125mhz_gclk),
- CLK(NULL, "cpsw_cpts_rft_clk", &cpsw_cpts_rft_clk),
- CLK(NULL, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck),
- CLK(NULL, "gpio0_dbclk", &gpio0_dbclk),
- CLK(NULL, "gpio1_dbclk", &gpio1_dbclk),
- CLK(NULL, "gpio2_dbclk", &gpio2_dbclk),
- CLK(NULL, "gpio3_dbclk", &gpio3_dbclk),
- CLK(NULL, "lcd_gclk", &lcd_gclk),
- CLK(NULL, "mmc_clk", &mmc_clk),
- CLK(NULL, "gfx_fclk_clksel_ck", &gfx_fclk_clksel_ck),
- CLK(NULL, "gfx_fck_div_ck", &gfx_fck_div_ck),
- CLK(NULL, "sysclkout_pre_ck", &sysclkout_pre_ck),
- CLK(NULL, "clkout2_div_ck", &clkout2_div_ck),
- CLK(NULL, "timer_32k_ck", &clkdiv32k_ick),
- CLK(NULL, "timer_sys_ck", &sys_clkin_ck),
- CLK(NULL, "dbg_sysclk_ck", &dbg_sysclk_ck),
- CLK(NULL, "dbg_clka_ck", &dbg_clka_ck),
- CLK(NULL, "stm_pmd_clock_mux_ck", &stm_pmd_clock_mux_ck),
- CLK(NULL, "trace_pmd_clk_mux_ck", &trace_pmd_clk_mux_ck),
- CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck),
- CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck),
- CLK(NULL, "clkout2_ck", &clkout2_ck),
- CLK("48300200.ehrpwm", "tbclk", &ehrpwm0_tbclk),
- CLK("48302200.ehrpwm", "tbclk", &ehrpwm1_tbclk),
- CLK("48304200.ehrpwm", "tbclk", &ehrpwm2_tbclk),
-};
-
-
-static const char *enable_init_clks[] = {
- "dpll_ddr_m2_ck",
- "dpll_mpu_m2_ck",
- "l3_gclk",
- "l4hs_gclk",
- "l4fw_gclk",
- "l4ls_gclk",
- "clkout2_ck", /* Required for external peripherals like, Audio codecs */
-};
-
-int __init am33xx_clk_init(void)
-{
- if (soc_is_am33xx())
- cpu_mask = RATE_IN_AM33XX;
-
- omap_clocks_register(am33xx_clks, ARRAY_SIZE(am33xx_clks));
-
- omap2_clk_disable_autoidle_all();
-
- omap2_clk_enable_init_clocks(enable_init_clks,
- ARRAY_SIZE(enable_init_clks));
-
- /* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always
- * physically present, in such a case HWMOD enabling of
- * clock would be failure with default parent. And timer
- * probe thinks clock is already enabled, this leads to
- * crash upon accessing timer 3 & 6 registers in probe.
- * Fix by setting parent of both these timers to master
- * oscillator clock.
- */
-
- clk_set_parent(&timer3_fck, &sys_clkin_ck);
- clk_set_parent(&timer6_fck, &sys_clkin_ck);
- /*
- * The On-Chip 32K RC Osc clock is not an accurate clock-source as per
- * the design/spec, so as a result, for example, timer which supposed
- * to get expired @60Sec, but will expire somewhere ~@40Sec, which is
- * not expected by any use-case, so change WDT1 clock source to PRCM
- * 32KHz clock.
- */
- clk_set_parent(&wdt1_fck, &clkdiv32k_ick);
-
- return 0;
-}
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 1a83c3c..63b77f0 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -2,6 +2,7 @@ ifneq ($(CONFIG_OF),)
obj-y += clk.o dpll.o autoidle.o divider.o \
fixed-factor.o gate.o clockdomain.o \
mux-gate.o mux.o apll.o
+obj-$(CONFIG_SOC_AM33XX) += clk-33xx.o
obj-$(CONFIG_ARCH_OMAP4) += clk-44xx.o
obj-$(CONFIG_SOC_OMAP5) += clk-54xx.o
obj-$(CONFIG_SOC_DRA7XX) += clk-7xx.o
--
1.7.9.5
--
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^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 26/36] ARM: AM33xx: remove old clock data and link in new clock init code
@ 2013-09-25 8:48 ` Tero Kristo
0 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-arm-kernel
AM33xx clocks have now been moved to DT, thus remove the old data file
and use the new init code under OMAP clock driver.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/mach-omap2/Makefile | 1 -
arch/arm/mach-omap2/cclock33xx_data.c | 1064 ---------------------------------
drivers/clk/ti/Makefile | 1 +
3 files changed, 1 insertion(+), 1065 deletions(-)
delete mode 100644 arch/arm/mach-omap2/cclock33xx_data.c
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index f518360..020079e 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -187,7 +187,6 @@ obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o
obj-$(CONFIG_ARCH_OMAP4) += $(clock-common)
obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o
obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o
-obj-$(CONFIG_SOC_AM33XX) += cclock33xx_data.o
obj-$(CONFIG_SOC_OMAP5) += $(clock-common)
obj-$(CONFIG_SOC_OMAP5) += dpll3xxx.o dpll44xx.o
diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c
deleted file mode 100644
index 865d30e..0000000
--- a/arch/arm/mach-omap2/cclock33xx_data.c
+++ /dev/null
@@ -1,1064 +0,0 @@
-/*
- * AM33XX Clock data
- *
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
- * Vaibhav Hiremath <hvaibhav@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/clk-private.h>
-#include <linux/clkdev.h>
-#include <linux/io.h>
-
-#include "am33xx.h"
-#include "soc.h"
-#include "iomap.h"
-#include "clock.h"
-#include "control.h"
-#include "cm.h"
-#include "cm33xx.h"
-#include "cm-regbits-33xx.h"
-#include "prm.h"
-
-/* Modulemode control */
-#define AM33XX_MODULEMODE_HWCTRL_SHIFT 0
-#define AM33XX_MODULEMODE_SWCTRL_SHIFT 1
-
-/*LIST_HEAD(clocks);*/
-
-/* Root clocks */
-
-/* RTC 32k */
-DEFINE_CLK_FIXED_RATE(clk_32768_ck, CLK_IS_ROOT, 32768, 0x0);
-
-/* On-Chip 32KHz RC OSC */
-DEFINE_CLK_FIXED_RATE(clk_rc32k_ck, CLK_IS_ROOT, 32000, 0x0);
-
-/* Crystal input clks */
-DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_24000000_ck, CLK_IS_ROOT, 24000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_25000000_ck, CLK_IS_ROOT, 25000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
-
-/* Oscillator clock */
-/* 19.2, 24, 25 or 26 MHz */
-static const char *sys_clkin_ck_parents[] = {
- "virt_19200000_ck", "virt_24000000_ck", "virt_25000000_ck",
- "virt_26000000_ck",
-};
-
-/*
- * sys_clk in: input to the dpll and also used as funtional clock for,
- * adc_tsc, smartreflex0-1, timer1-7, mcasp0-1, dcan0-1, cefuse
- *
- */
-DEFINE_CLK_MUX(sys_clkin_ck, sys_clkin_ck_parents, NULL, 0x0,
- AM33XX_CTRL_REGADDR(AM33XX_CONTROL_STATUS),
- AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT,
- AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH,
- 0, NULL);
-
-/* External clock - 12 MHz */
-DEFINE_CLK_FIXED_RATE(tclkin_ck, CLK_IS_ROOT, 12000000, 0x0);
-
-/* Module clocks and DPLL outputs */
-
-/* DPLL_CORE */
-static struct dpll_data dpll_core_dd = {
- .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_CORE,
- .clk_bypass = &sys_clkin_ck,
- .clk_ref = &sys_clkin_ck,
- .control_reg = AM33XX_CM_CLKMODE_DPLL_CORE,
- .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
- .idlest_reg = AM33XX_CM_IDLEST_DPLL_CORE,
- .mult_mask = AM33XX_DPLL_MULT_MASK,
- .div1_mask = AM33XX_DPLL_DIV_MASK,
- .enable_mask = AM33XX_DPLL_EN_MASK,
- .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
- .max_multiplier = 2047,
- .max_divider = 128,
- .min_divider = 1,
-};
-
-/* CLKDCOLDO output */
-static const char *dpll_core_ck_parents[] = {
- "sys_clkin_ck",
-};
-
-static struct clk dpll_core_ck;
-
-static const struct clk_ops dpll_core_ck_ops = {
- .recalc_rate = &omap3_dpll_recalc,
- .get_parent = &omap2_init_dpll_parent,
-};
-
-static struct clk_hw_omap dpll_core_ck_hw = {
- .hw = {
- .clk = &dpll_core_ck,
- },
- .dpll_data = &dpll_core_dd,
- .ops = &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops);
-
-static const char *dpll_core_x2_ck_parents[] = {
- "dpll_core_ck",
-};
-
-static struct clk dpll_core_x2_ck;
-
-static const struct clk_ops dpll_x2_ck_ops = {
- .recalc_rate = &omap3_clkoutx2_recalc,
-};
-
-static struct clk_hw_omap dpll_core_x2_ck_hw = {
- .hw = {
- .clk = &dpll_core_x2_ck,
- },
- .flags = CLOCK_CLKOUTX2,
-};
-
-DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_x2_ck_ops);
-
-DEFINE_CLK_DIVIDER(dpll_core_m4_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
- 0x0, AM33XX_CM_DIV_M4_DPLL_CORE,
- AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT,
- AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH, CLK_DIVIDER_ONE_BASED,
- NULL);
-
-DEFINE_CLK_DIVIDER(dpll_core_m5_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
- 0x0, AM33XX_CM_DIV_M5_DPLL_CORE,
- AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT,
- AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH,
- CLK_DIVIDER_ONE_BASED, NULL);
-
-DEFINE_CLK_DIVIDER(dpll_core_m6_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
- 0x0, AM33XX_CM_DIV_M6_DPLL_CORE,
- AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT,
- AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH,
- CLK_DIVIDER_ONE_BASED, NULL);
-
-
-/* DPLL_MPU */
-static struct dpll_data dpll_mpu_dd = {
- .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_MPU,
- .clk_bypass = &sys_clkin_ck,
- .clk_ref = &sys_clkin_ck,
- .control_reg = AM33XX_CM_CLKMODE_DPLL_MPU,
- .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
- .idlest_reg = AM33XX_CM_IDLEST_DPLL_MPU,
- .mult_mask = AM33XX_DPLL_MULT_MASK,
- .div1_mask = AM33XX_DPLL_DIV_MASK,
- .enable_mask = AM33XX_DPLL_EN_MASK,
- .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
- .max_multiplier = 2047,
- .max_divider = 128,
- .min_divider = 1,
-};
-
-/* CLKOUT: fdpll/M2 */
-static struct clk dpll_mpu_ck;
-
-static const struct clk_ops dpll_mpu_ck_ops = {
- .enable = &omap3_noncore_dpll_enable,
- .disable = &omap3_noncore_dpll_disable,
- .recalc_rate = &omap3_dpll_recalc,
- .round_rate = &omap2_dpll_round_rate,
- .set_rate = &omap3_noncore_dpll_set_rate,
- .get_parent = &omap2_init_dpll_parent,
-};
-
-static struct clk_hw_omap dpll_mpu_ck_hw = {
- .hw = {
- .clk = &dpll_mpu_ck,
- },
- .dpll_data = &dpll_mpu_dd,
- .ops = &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_core_ck_parents, dpll_mpu_ck_ops);
-
-/*
- * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
- * and ALT_CLK1/2)
- */
-DEFINE_CLK_DIVIDER(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck,
- 0x0, AM33XX_CM_DIV_M2_DPLL_MPU, AM33XX_DPLL_CLKOUT_DIV_SHIFT,
- AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
-
-/* DPLL_DDR */
-static struct dpll_data dpll_ddr_dd = {
- .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_DDR,
- .clk_bypass = &sys_clkin_ck,
- .clk_ref = &sys_clkin_ck,
- .control_reg = AM33XX_CM_CLKMODE_DPLL_DDR,
- .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
- .idlest_reg = AM33XX_CM_IDLEST_DPLL_DDR,
- .mult_mask = AM33XX_DPLL_MULT_MASK,
- .div1_mask = AM33XX_DPLL_DIV_MASK,
- .enable_mask = AM33XX_DPLL_EN_MASK,
- .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
- .max_multiplier = 2047,
- .max_divider = 128,
- .min_divider = 1,
-};
-
-/* CLKOUT: fdpll/M2 */
-static struct clk dpll_ddr_ck;
-
-static const struct clk_ops dpll_ddr_ck_ops = {
- .recalc_rate = &omap3_dpll_recalc,
- .get_parent = &omap2_init_dpll_parent,
- .round_rate = &omap2_dpll_round_rate,
- .set_rate = &omap3_noncore_dpll_set_rate,
-};
-
-static struct clk_hw_omap dpll_ddr_ck_hw = {
- .hw = {
- .clk = &dpll_ddr_ck,
- },
- .dpll_data = &dpll_ddr_dd,
- .ops = &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_ddr_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
-
-/*
- * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
- * and ALT_CLK1/2)
- */
-DEFINE_CLK_DIVIDER(dpll_ddr_m2_ck, "dpll_ddr_ck", &dpll_ddr_ck,
- 0x0, AM33XX_CM_DIV_M2_DPLL_DDR,
- AM33XX_DPLL_CLKOUT_DIV_SHIFT, AM33XX_DPLL_CLKOUT_DIV_WIDTH,
- CLK_DIVIDER_ONE_BASED, NULL);
-
-/* emif_fck functional clock */
-DEFINE_CLK_FIXED_FACTOR(dpll_ddr_m2_div2_ck, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck,
- 0x0, 1, 2);
-
-/* DPLL_DISP */
-static struct dpll_data dpll_disp_dd = {
- .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_DISP,
- .clk_bypass = &sys_clkin_ck,
- .clk_ref = &sys_clkin_ck,
- .control_reg = AM33XX_CM_CLKMODE_DPLL_DISP,
- .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
- .idlest_reg = AM33XX_CM_IDLEST_DPLL_DISP,
- .mult_mask = AM33XX_DPLL_MULT_MASK,
- .div1_mask = AM33XX_DPLL_DIV_MASK,
- .enable_mask = AM33XX_DPLL_EN_MASK,
- .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
- .max_multiplier = 2047,
- .max_divider = 128,
- .min_divider = 1,
-};
-
-/* CLKOUT: fdpll/M2 */
-static struct clk dpll_disp_ck;
-
-static struct clk_hw_omap dpll_disp_ck_hw = {
- .hw = {
- .clk = &dpll_disp_ck,
- },
- .dpll_data = &dpll_disp_dd,
- .ops = &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_disp_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
-
-/*
- * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
- * and ALT_CLK1/2)
- */
-DEFINE_CLK_DIVIDER(dpll_disp_m2_ck, "dpll_disp_ck", &dpll_disp_ck,
- CLK_SET_RATE_PARENT, AM33XX_CM_DIV_M2_DPLL_DISP,
- AM33XX_DPLL_CLKOUT_DIV_SHIFT, AM33XX_DPLL_CLKOUT_DIV_WIDTH,
- CLK_DIVIDER_ONE_BASED, NULL);
-
-/* DPLL_PER */
-static struct dpll_data dpll_per_dd = {
- .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_PERIPH,
- .clk_bypass = &sys_clkin_ck,
- .clk_ref = &sys_clkin_ck,
- .control_reg = AM33XX_CM_CLKMODE_DPLL_PER,
- .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
- .idlest_reg = AM33XX_CM_IDLEST_DPLL_PER,
- .mult_mask = AM33XX_DPLL_MULT_PERIPH_MASK,
- .div1_mask = AM33XX_DPLL_PER_DIV_MASK,
- .enable_mask = AM33XX_DPLL_EN_MASK,
- .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
- .max_multiplier = 2047,
- .max_divider = 128,
- .min_divider = 1,
- .flags = DPLL_J_TYPE,
-};
-
-/* CLKDCOLDO */
-static struct clk dpll_per_ck;
-
-static struct clk_hw_omap dpll_per_ck_hw = {
- .hw = {
- .clk = &dpll_per_ck,
- },
- .dpll_data = &dpll_per_dd,
- .ops = &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_per_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
-
-/* CLKOUT: fdpll/M2 */
-DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0,
- AM33XX_CM_DIV_M2_DPLL_PER, AM33XX_DPLL_CLKOUT_DIV_SHIFT,
- AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED,
- NULL);
-
-DEFINE_CLK_FIXED_FACTOR(dpll_per_m2_div4_wkupdm_ck, "dpll_per_m2_ck",
- &dpll_per_m2_ck, 0x0, 1, 4);
-
-DEFINE_CLK_FIXED_FACTOR(dpll_per_m2_div4_ck, "dpll_per_m2_ck",
- &dpll_per_m2_ck, 0x0, 1, 4);
-
-DEFINE_CLK_FIXED_FACTOR(dpll_core_m4_div2_ck, "dpll_core_m4_ck",
- &dpll_core_m4_ck, 0x0, 1, 2);
-
-DEFINE_CLK_FIXED_FACTOR(l4_rtc_gclk, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0,
- 1, 2);
-
-DEFINE_CLK_FIXED_FACTOR(clk_24mhz, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1,
- 8);
-
-/*
- * Below clock nodes describes clockdomains derived out
- * of core clock.
- */
-static const struct clk_ops clk_ops_null = {
-};
-
-static const char *l3_gclk_parents[] = {
- "dpll_core_m4_ck"
-};
-
-static struct clk l3_gclk;
-DEFINE_STRUCT_CLK_HW_OMAP(l3_gclk, NULL);
-DEFINE_STRUCT_CLK(l3_gclk, l3_gclk_parents, clk_ops_null);
-
-static struct clk l4hs_gclk;
-DEFINE_STRUCT_CLK_HW_OMAP(l4hs_gclk, NULL);
-DEFINE_STRUCT_CLK(l4hs_gclk, l3_gclk_parents, clk_ops_null);
-
-static const char *l3s_gclk_parents[] = {
- "dpll_core_m4_div2_ck"
-};
-
-static struct clk l3s_gclk;
-DEFINE_STRUCT_CLK_HW_OMAP(l3s_gclk, NULL);
-DEFINE_STRUCT_CLK(l3s_gclk, l3s_gclk_parents, clk_ops_null);
-
-static struct clk l4fw_gclk;
-DEFINE_STRUCT_CLK_HW_OMAP(l4fw_gclk, NULL);
-DEFINE_STRUCT_CLK(l4fw_gclk, l3s_gclk_parents, clk_ops_null);
-
-static struct clk l4ls_gclk;
-DEFINE_STRUCT_CLK_HW_OMAP(l4ls_gclk, NULL);
-DEFINE_STRUCT_CLK(l4ls_gclk, l3s_gclk_parents, clk_ops_null);
-
-static struct clk sysclk_div_ck;
-DEFINE_STRUCT_CLK_HW_OMAP(sysclk_div_ck, NULL);
-DEFINE_STRUCT_CLK(sysclk_div_ck, l3_gclk_parents, clk_ops_null);
-
-/*
- * In order to match the clock domain with hwmod clockdomain entry,
- * separate clock nodes is required for the modules which are
- * directly getting their funtioncal clock from sys_clkin.
- */
-static struct clk adc_tsc_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(adc_tsc_fck, NULL);
-DEFINE_STRUCT_CLK(adc_tsc_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk dcan0_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(dcan0_fck, NULL);
-DEFINE_STRUCT_CLK(dcan0_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk dcan1_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(dcan1_fck, NULL);
-DEFINE_STRUCT_CLK(dcan1_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk mcasp0_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(mcasp0_fck, NULL);
-DEFINE_STRUCT_CLK(mcasp0_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk mcasp1_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(mcasp1_fck, NULL);
-DEFINE_STRUCT_CLK(mcasp1_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk smartreflex0_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(smartreflex0_fck, NULL);
-DEFINE_STRUCT_CLK(smartreflex0_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk smartreflex1_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(smartreflex1_fck, NULL);
-DEFINE_STRUCT_CLK(smartreflex1_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk sha0_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(sha0_fck, NULL);
-DEFINE_STRUCT_CLK(sha0_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk aes0_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(aes0_fck, NULL);
-DEFINE_STRUCT_CLK(aes0_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk rng_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(rng_fck, NULL);
-DEFINE_STRUCT_CLK(rng_fck, dpll_core_ck_parents, clk_ops_null);
-
-/*
- * Modules clock nodes
- *
- * The following clock leaf nodes are added for the moment because:
- *
- * - hwmod data is not present for these modules, either hwmod
- * control is not required or its not populated.
- * - Driver code is not yet migrated to use hwmod/runtime pm
- * - Modules outside kernel access (to disable them by default)
- *
- * - mmu (gfx domain)
- * - cefuse
- * - usbotg_fck (its additional clock and not really a modulemode)
- * - ieee5000
- */
-
-DEFINE_CLK_GATE(mmu_fck, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0,
- AM33XX_CM_GFX_MMUDATA_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
- 0x0, NULL);
-
-DEFINE_CLK_GATE(cefuse_fck, "sys_clkin_ck", &sys_clkin_ck, 0x0,
- AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
- 0x0, NULL);
-
-/*
- * clkdiv32 is generated from fixed division of 732.4219
- */
-DEFINE_CLK_FIXED_FACTOR(clkdiv32k_ck, "clk_24mhz", &clk_24mhz, 0x0, 1, 732);
-
-static struct clk clkdiv32k_ick;
-
-static const char *clkdiv32k_ick_parent_names[] = {
- "clkdiv32k_ck",
-};
-
-static const struct clk_ops clkdiv32k_ick_ops = {
- .enable = &omap2_dflt_clk_enable,
- .disable = &omap2_dflt_clk_disable,
- .is_enabled = &omap2_dflt_clk_is_enabled,
- .init = &omap2_init_clk_clkdm,
-};
-
-static struct clk_hw_omap clkdiv32k_ick_hw = {
- .hw = {
- .clk = &clkdiv32k_ick,
- },
- .enable_reg = AM33XX_CM_PER_CLKDIV32K_CLKCTRL,
- .enable_bit = AM33XX_MODULEMODE_SWCTRL_SHIFT,
- .clkdm_name = "clk_24mhz_clkdm",
-};
-
-DEFINE_STRUCT_CLK(clkdiv32k_ick, clkdiv32k_ick_parent_names, clkdiv32k_ick_ops);
-
-/* "usbotg_fck" is an additional clock and not really a modulemode */
-DEFINE_CLK_GATE(usbotg_fck, "dpll_per_ck", &dpll_per_ck, 0x0,
- AM33XX_CM_CLKDCOLDO_DPLL_PER, AM33XX_ST_DPLL_CLKDCOLDO_SHIFT,
- 0x0, NULL);
-
-DEFINE_CLK_GATE(ieee5000_fck, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck,
- 0x0, AM33XX_CM_PER_IEEE5000_CLKCTRL,
- AM33XX_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-/* Timers */
-static const struct clksel timer1_clkmux_sel[] = {
- { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
- { .parent = &clkdiv32k_ick, .rates = div_1_1_rates },
- { .parent = &tclkin_ck, .rates = div_1_2_rates },
- { .parent = &clk_rc32k_ck, .rates = div_1_3_rates },
- { .parent = &clk_32768_ck, .rates = div_1_4_rates },
- { .parent = NULL },
-};
-
-static const char *timer1_ck_parents[] = {
- "sys_clkin_ck", "clkdiv32k_ick", "tclkin_ck", "clk_rc32k_ck",
- "clk_32768_ck",
-};
-
-static struct clk timer1_fck;
-
-static const struct clk_ops timer1_fck_ops = {
- .recalc_rate = &omap2_clksel_recalc,
- .get_parent = &omap2_clksel_find_parent_index,
- .set_parent = &omap2_clksel_set_parent,
- .init = &omap2_init_clk_clkdm,
-};
-
-static struct clk_hw_omap timer1_fck_hw = {
- .hw = {
- .clk = &timer1_fck,
- },
- .clkdm_name = "l4ls_clkdm",
- .clksel = timer1_clkmux_sel,
- .clksel_reg = AM33XX_CLKSEL_TIMER1MS_CLK,
- .clksel_mask = AM33XX_CLKSEL_0_2_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer1_fck, timer1_ck_parents, timer1_fck_ops);
-
-static const struct clksel timer2_to_7_clk_sel[] = {
- { .parent = &tclkin_ck, .rates = div_1_0_rates },
- { .parent = &sys_clkin_ck, .rates = div_1_1_rates },
- { .parent = &clkdiv32k_ick, .rates = div_1_2_rates },
- { .parent = NULL },
-};
-
-static const char *timer2_to_7_ck_parents[] = {
- "tclkin_ck", "sys_clkin_ck", "clkdiv32k_ick",
-};
-
-static struct clk timer2_fck;
-
-static struct clk_hw_omap timer2_fck_hw = {
- .hw = {
- .clk = &timer2_fck,
- },
- .clkdm_name = "l4ls_clkdm",
- .clksel = timer2_to_7_clk_sel,
- .clksel_reg = AM33XX_CLKSEL_TIMER2_CLK,
- .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer2_fck, timer2_to_7_ck_parents, timer1_fck_ops);
-
-static struct clk timer3_fck;
-
-static struct clk_hw_omap timer3_fck_hw = {
- .hw = {
- .clk = &timer3_fck,
- },
- .clkdm_name = "l4ls_clkdm",
- .clksel = timer2_to_7_clk_sel,
- .clksel_reg = AM33XX_CLKSEL_TIMER3_CLK,
- .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer3_fck, timer2_to_7_ck_parents, timer1_fck_ops);
-
-static struct clk timer4_fck;
-
-static struct clk_hw_omap timer4_fck_hw = {
- .hw = {
- .clk = &timer4_fck,
- },
- .clkdm_name = "l4ls_clkdm",
- .clksel = timer2_to_7_clk_sel,
- .clksel_reg = AM33XX_CLKSEL_TIMER4_CLK,
- .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer4_fck, timer2_to_7_ck_parents, timer1_fck_ops);
-
-static struct clk timer5_fck;
-
-static struct clk_hw_omap timer5_fck_hw = {
- .hw = {
- .clk = &timer5_fck,
- },
- .clkdm_name = "l4ls_clkdm",
- .clksel = timer2_to_7_clk_sel,
- .clksel_reg = AM33XX_CLKSEL_TIMER5_CLK,
- .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer5_fck, timer2_to_7_ck_parents, timer1_fck_ops);
-
-static struct clk timer6_fck;
-
-static struct clk_hw_omap timer6_fck_hw = {
- .hw = {
- .clk = &timer6_fck,
- },
- .clkdm_name = "l4ls_clkdm",
- .clksel = timer2_to_7_clk_sel,
- .clksel_reg = AM33XX_CLKSEL_TIMER6_CLK,
- .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer6_fck, timer2_to_7_ck_parents, timer1_fck_ops);
-
-static struct clk timer7_fck;
-
-static struct clk_hw_omap timer7_fck_hw = {
- .hw = {
- .clk = &timer7_fck,
- },
- .clkdm_name = "l4ls_clkdm",
- .clksel = timer2_to_7_clk_sel,
- .clksel_reg = AM33XX_CLKSEL_TIMER7_CLK,
- .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer7_fck, timer2_to_7_ck_parents, timer1_fck_ops);
-
-DEFINE_CLK_FIXED_FACTOR(cpsw_125mhz_gclk,
- "dpll_core_m5_ck",
- &dpll_core_m5_ck,
- 0x0,
- 1, 2);
-
-static const struct clk_ops cpsw_fck_ops = {
- .recalc_rate = &omap2_clksel_recalc,
- .get_parent = &omap2_clksel_find_parent_index,
- .set_parent = &omap2_clksel_set_parent,
-};
-
-static const struct clksel cpsw_cpts_rft_clkmux_sel[] = {
- { .parent = &dpll_core_m5_ck, .rates = div_1_0_rates },
- { .parent = &dpll_core_m4_ck, .rates = div_1_1_rates },
- { .parent = NULL },
-};
-
-static const char *cpsw_cpts_rft_ck_parents[] = {
- "dpll_core_m5_ck", "dpll_core_m4_ck",
-};
-
-static struct clk cpsw_cpts_rft_clk;
-
-static struct clk_hw_omap cpsw_cpts_rft_clk_hw = {
- .hw = {
- .clk = &cpsw_cpts_rft_clk,
- },
- .clkdm_name = "cpsw_125mhz_clkdm",
- .clksel = cpsw_cpts_rft_clkmux_sel,
- .clksel_reg = AM33XX_CM_CPTS_RFT_CLKSEL,
- .clksel_mask = AM33XX_CLKSEL_0_0_MASK,
-};
-
-DEFINE_STRUCT_CLK(cpsw_cpts_rft_clk, cpsw_cpts_rft_ck_parents, cpsw_fck_ops);
-
-
-/* gpio */
-static const char *gpio0_ck_parents[] = {
- "clk_rc32k_ck", "clk_32768_ck", "clkdiv32k_ick",
-};
-
-static const struct clksel gpio0_dbclk_mux_sel[] = {
- { .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
- { .parent = &clk_32768_ck, .rates = div_1_1_rates },
- { .parent = &clkdiv32k_ick, .rates = div_1_2_rates },
- { .parent = NULL },
-};
-
-static const struct clk_ops gpio_fck_ops = {
- .recalc_rate = &omap2_clksel_recalc,
- .get_parent = &omap2_clksel_find_parent_index,
- .set_parent = &omap2_clksel_set_parent,
- .init = &omap2_init_clk_clkdm,
-};
-
-static struct clk gpio0_dbclk_mux_ck;
-
-static struct clk_hw_omap gpio0_dbclk_mux_ck_hw = {
- .hw = {
- .clk = &gpio0_dbclk_mux_ck,
- },
- .clkdm_name = "l4_wkup_clkdm",
- .clksel = gpio0_dbclk_mux_sel,
- .clksel_reg = AM33XX_CLKSEL_GPIO0_DBCLK,
- .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(gpio0_dbclk_mux_ck, gpio0_ck_parents, gpio_fck_ops);
-
-DEFINE_CLK_GATE(gpio0_dbclk, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck, 0x0,
- AM33XX_CM_WKUP_GPIO0_CLKCTRL,
- AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(gpio1_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
- AM33XX_CM_PER_GPIO1_CLKCTRL,
- AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(gpio2_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
- AM33XX_CM_PER_GPIO2_CLKCTRL,
- AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(gpio3_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
- AM33XX_CM_PER_GPIO3_CLKCTRL,
- AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT, 0x0, NULL);
-
-
-static const char *pruss_ck_parents[] = {
- "l3_gclk", "dpll_disp_m2_ck",
-};
-
-static const struct clksel pruss_ocp_clk_mux_sel[] = {
- { .parent = &l3_gclk, .rates = div_1_0_rates },
- { .parent = &dpll_disp_m2_ck, .rates = div_1_1_rates },
- { .parent = NULL },
-};
-
-static struct clk pruss_ocp_gclk;
-
-static struct clk_hw_omap pruss_ocp_gclk_hw = {
- .hw = {
- .clk = &pruss_ocp_gclk,
- },
- .clkdm_name = "pruss_ocp_clkdm",
- .clksel = pruss_ocp_clk_mux_sel,
- .clksel_reg = AM33XX_CLKSEL_PRUSS_OCP_CLK,
- .clksel_mask = AM33XX_CLKSEL_0_0_MASK,
-};
-
-DEFINE_STRUCT_CLK(pruss_ocp_gclk, pruss_ck_parents, gpio_fck_ops);
-
-static const char *lcd_ck_parents[] = {
- "dpll_disp_m2_ck", "dpll_core_m5_ck", "dpll_per_m2_ck",
-};
-
-static const struct clksel lcd_clk_mux_sel[] = {
- { .parent = &dpll_disp_m2_ck, .rates = div_1_0_rates },
- { .parent = &dpll_core_m5_ck, .rates = div_1_1_rates },
- { .parent = &dpll_per_m2_ck, .rates = div_1_2_rates },
- { .parent = NULL },
-};
-
-static struct clk lcd_gclk;
-
-static struct clk_hw_omap lcd_gclk_hw = {
- .hw = {
- .clk = &lcd_gclk,
- },
- .clkdm_name = "lcdc_clkdm",
- .clksel = lcd_clk_mux_sel,
- .clksel_reg = AM33XX_CLKSEL_LCDC_PIXEL_CLK,
- .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK_FLAGS(lcd_gclk, lcd_ck_parents,
- gpio_fck_ops, CLK_SET_RATE_PARENT);
-
-DEFINE_CLK_FIXED_FACTOR(mmc_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1, 2);
-
-static const char *gfx_ck_parents[] = {
- "dpll_core_m4_ck", "dpll_per_m2_ck",
-};
-
-static const struct clksel gfx_clksel_sel[] = {
- { .parent = &dpll_core_m4_ck, .rates = div_1_0_rates },
- { .parent = &dpll_per_m2_ck, .rates = div_1_1_rates },
- { .parent = NULL },
-};
-
-static struct clk gfx_fclk_clksel_ck;
-
-static struct clk_hw_omap gfx_fclk_clksel_ck_hw = {
- .hw = {
- .clk = &gfx_fclk_clksel_ck,
- },
- .clksel = gfx_clksel_sel,
- .clksel_reg = AM33XX_CLKSEL_GFX_FCLK,
- .clksel_mask = AM33XX_CLKSEL_GFX_FCLK_MASK,
-};
-
-DEFINE_STRUCT_CLK(gfx_fclk_clksel_ck, gfx_ck_parents, gpio_fck_ops);
-
-static const struct clk_div_table div_1_0_2_1_rates[] = {
- { .div = 1, .val = 0, },
- { .div = 2, .val = 1, },
- { .div = 0 },
-};
-
-DEFINE_CLK_DIVIDER_TABLE(gfx_fck_div_ck, "gfx_fclk_clksel_ck",
- &gfx_fclk_clksel_ck, 0x0, AM33XX_CLKSEL_GFX_FCLK,
- AM33XX_CLKSEL_0_0_SHIFT, AM33XX_CLKSEL_0_0_WIDTH,
- 0x0, div_1_0_2_1_rates, NULL);
-
-static const char *sysclkout_ck_parents[] = {
- "clk_32768_ck", "l3_gclk", "dpll_ddr_m2_ck", "dpll_per_m2_ck",
- "lcd_gclk",
-};
-
-static const struct clksel sysclkout_pre_sel[] = {
- { .parent = &clk_32768_ck, .rates = div_1_0_rates },
- { .parent = &l3_gclk, .rates = div_1_1_rates },
- { .parent = &dpll_ddr_m2_ck, .rates = div_1_2_rates },
- { .parent = &dpll_per_m2_ck, .rates = div_1_3_rates },
- { .parent = &lcd_gclk, .rates = div_1_4_rates },
- { .parent = NULL },
-};
-
-static struct clk sysclkout_pre_ck;
-
-static struct clk_hw_omap sysclkout_pre_ck_hw = {
- .hw = {
- .clk = &sysclkout_pre_ck,
- },
- .clksel = sysclkout_pre_sel,
- .clksel_reg = AM33XX_CM_CLKOUT_CTRL,
- .clksel_mask = AM33XX_CLKOUT2SOURCE_MASK,
-};
-
-DEFINE_STRUCT_CLK(sysclkout_pre_ck, sysclkout_ck_parents, gpio_fck_ops);
-
-/* Divide by 8 clock rates with default clock is 1/1*/
-static const struct clk_div_table div8_rates[] = {
- { .div = 1, .val = 0, },
- { .div = 2, .val = 1, },
- { .div = 3, .val = 2, },
- { .div = 4, .val = 3, },
- { .div = 5, .val = 4, },
- { .div = 6, .val = 5, },
- { .div = 7, .val = 6, },
- { .div = 8, .val = 7, },
- { .div = 0 },
-};
-
-DEFINE_CLK_DIVIDER_TABLE(clkout2_div_ck, "sysclkout_pre_ck", &sysclkout_pre_ck,
- 0x0, AM33XX_CM_CLKOUT_CTRL, AM33XX_CLKOUT2DIV_SHIFT,
- AM33XX_CLKOUT2DIV_WIDTH, 0x0, div8_rates, NULL);
-
-DEFINE_CLK_GATE(clkout2_ck, "clkout2_div_ck", &clkout2_div_ck, 0x0,
- AM33XX_CM_CLKOUT_CTRL, AM33XX_CLKOUT2EN_SHIFT, 0x0, NULL);
-
-static const char *wdt_ck_parents[] = {
- "clk_rc32k_ck", "clkdiv32k_ick",
-};
-
-static const struct clksel wdt_clkmux_sel[] = {
- { .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
- { .parent = &clkdiv32k_ick, .rates = div_1_1_rates },
- { .parent = NULL },
-};
-
-static struct clk wdt1_fck;
-
-static struct clk_hw_omap wdt1_fck_hw = {
- .hw = {
- .clk = &wdt1_fck,
- },
- .clkdm_name = "l4_wkup_clkdm",
- .clksel = wdt_clkmux_sel,
- .clksel_reg = AM33XX_CLKSEL_WDT1_CLK,
- .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(wdt1_fck, wdt_ck_parents, gpio_fck_ops);
-
-static const char *pwmss_clk_parents[] = {
- "dpll_per_m2_ck",
-};
-
-static const struct clk_ops ehrpwm_tbclk_ops = {
- .enable = &omap2_dflt_clk_enable,
- .disable = &omap2_dflt_clk_disable,
-};
-
-DEFINE_CLK_OMAP_MUX_GATE(ehrpwm0_tbclk, "l4ls_clkdm",
- NULL, NULL, 0,
- AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
- AM33XX_PWMSS0_TBCLKEN_SHIFT,
- NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
-
-DEFINE_CLK_OMAP_MUX_GATE(ehrpwm1_tbclk, "l4ls_clkdm",
- NULL, NULL, 0,
- AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
- AM33XX_PWMSS1_TBCLKEN_SHIFT,
- NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
-
-DEFINE_CLK_OMAP_MUX_GATE(ehrpwm2_tbclk, "l4ls_clkdm",
- NULL, NULL, 0,
- AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
- AM33XX_PWMSS2_TBCLKEN_SHIFT,
- NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
-
-/*
- * debugss optional clocks
- */
-DEFINE_CLK_GATE(dbg_sysclk_ck, "sys_clkin_ck", &sys_clkin_ck,
- 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
- AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(dbg_clka_ck, "dpll_core_m4_ck", &dpll_core_m4_ck,
- 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
- AM33XX_OPTCLK_DEBUG_CLKA_SHIFT, 0x0, NULL);
-
-static const char *stm_pmd_clock_mux_ck_parents[] = {
- "dbg_sysclk_ck", "dbg_clka_ck",
-};
-
-DEFINE_CLK_MUX(stm_pmd_clock_mux_ck, stm_pmd_clock_mux_ck_parents, NULL, 0x0,
- AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, AM33XX_STM_PMD_CLKSEL_SHIFT,
- AM33XX_STM_PMD_CLKSEL_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_MUX(trace_pmd_clk_mux_ck, stm_pmd_clock_mux_ck_parents, NULL, 0x0,
- AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
- AM33XX_TRC_PMD_CLKSEL_SHIFT,
- AM33XX_TRC_PMD_CLKSEL_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_DIVIDER(stm_clk_div_ck, "stm_pmd_clock_mux_ck",
- &stm_pmd_clock_mux_ck, 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
- AM33XX_STM_PMD_CLKDIVSEL_SHIFT,
- AM33XX_STM_PMD_CLKDIVSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
- NULL);
-
-DEFINE_CLK_DIVIDER(trace_clk_div_ck, "trace_pmd_clk_mux_ck",
- &trace_pmd_clk_mux_ck, 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
- AM33XX_TRC_PMD_CLKDIVSEL_SHIFT,
- AM33XX_TRC_PMD_CLKDIVSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
- NULL);
-
-/*
- * clkdev
- */
-static struct omap_clk am33xx_clks[] = {
- CLK(NULL, "clk_32768_ck", &clk_32768_ck),
- CLK(NULL, "clk_rc32k_ck", &clk_rc32k_ck),
- CLK(NULL, "virt_19200000_ck", &virt_19200000_ck),
- CLK(NULL, "virt_24000000_ck", &virt_24000000_ck),
- CLK(NULL, "virt_25000000_ck", &virt_25000000_ck),
- CLK(NULL, "virt_26000000_ck", &virt_26000000_ck),
- CLK(NULL, "sys_clkin_ck", &sys_clkin_ck),
- CLK(NULL, "tclkin_ck", &tclkin_ck),
- CLK(NULL, "dpll_core_ck", &dpll_core_ck),
- CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck),
- CLK(NULL, "dpll_core_m4_ck", &dpll_core_m4_ck),
- CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck),
- CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck),
- CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck),
- CLK("cpu0", NULL, &dpll_mpu_ck),
- CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck),
- CLK(NULL, "dpll_ddr_ck", &dpll_ddr_ck),
- CLK(NULL, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck),
- CLK(NULL, "dpll_ddr_m2_div2_ck", &dpll_ddr_m2_div2_ck),
- CLK(NULL, "dpll_disp_ck", &dpll_disp_ck),
- CLK(NULL, "dpll_disp_m2_ck", &dpll_disp_m2_ck),
- CLK(NULL, "dpll_per_ck", &dpll_per_ck),
- CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck),
- CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", &dpll_per_m2_div4_wkupdm_ck),
- CLK(NULL, "dpll_per_m2_div4_ck", &dpll_per_m2_div4_ck),
- CLK(NULL, "adc_tsc_fck", &adc_tsc_fck),
- CLK(NULL, "cefuse_fck", &cefuse_fck),
- CLK(NULL, "clkdiv32k_ck", &clkdiv32k_ck),
- CLK(NULL, "clkdiv32k_ick", &clkdiv32k_ick),
- CLK(NULL, "dcan0_fck", &dcan0_fck),
- CLK("481cc000.d_can", NULL, &dcan0_fck),
- CLK(NULL, "dcan1_fck", &dcan1_fck),
- CLK("481d0000.d_can", NULL, &dcan1_fck),
- CLK(NULL, "pruss_ocp_gclk", &pruss_ocp_gclk),
- CLK(NULL, "mcasp0_fck", &mcasp0_fck),
- CLK(NULL, "mcasp1_fck", &mcasp1_fck),
- CLK(NULL, "mmu_fck", &mmu_fck),
- CLK(NULL, "smartreflex0_fck", &smartreflex0_fck),
- CLK(NULL, "smartreflex1_fck", &smartreflex1_fck),
- CLK(NULL, "sha0_fck", &sha0_fck),
- CLK(NULL, "aes0_fck", &aes0_fck),
- CLK(NULL, "rng_fck", &rng_fck),
- CLK(NULL, "timer1_fck", &timer1_fck),
- CLK(NULL, "timer2_fck", &timer2_fck),
- CLK(NULL, "timer3_fck", &timer3_fck),
- CLK(NULL, "timer4_fck", &timer4_fck),
- CLK(NULL, "timer5_fck", &timer5_fck),
- CLK(NULL, "timer6_fck", &timer6_fck),
- CLK(NULL, "timer7_fck", &timer7_fck),
- CLK(NULL, "usbotg_fck", &usbotg_fck),
- CLK(NULL, "ieee5000_fck", &ieee5000_fck),
- CLK(NULL, "wdt1_fck", &wdt1_fck),
- CLK(NULL, "l4_rtc_gclk", &l4_rtc_gclk),
- CLK(NULL, "l3_gclk", &l3_gclk),
- CLK(NULL, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck),
- CLK(NULL, "l4hs_gclk", &l4hs_gclk),
- CLK(NULL, "l3s_gclk", &l3s_gclk),
- CLK(NULL, "l4fw_gclk", &l4fw_gclk),
- CLK(NULL, "l4ls_gclk", &l4ls_gclk),
- CLK(NULL, "clk_24mhz", &clk_24mhz),
- CLK(NULL, "sysclk_div_ck", &sysclk_div_ck),
- CLK(NULL, "cpsw_125mhz_gclk", &cpsw_125mhz_gclk),
- CLK(NULL, "cpsw_cpts_rft_clk", &cpsw_cpts_rft_clk),
- CLK(NULL, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck),
- CLK(NULL, "gpio0_dbclk", &gpio0_dbclk),
- CLK(NULL, "gpio1_dbclk", &gpio1_dbclk),
- CLK(NULL, "gpio2_dbclk", &gpio2_dbclk),
- CLK(NULL, "gpio3_dbclk", &gpio3_dbclk),
- CLK(NULL, "lcd_gclk", &lcd_gclk),
- CLK(NULL, "mmc_clk", &mmc_clk),
- CLK(NULL, "gfx_fclk_clksel_ck", &gfx_fclk_clksel_ck),
- CLK(NULL, "gfx_fck_div_ck", &gfx_fck_div_ck),
- CLK(NULL, "sysclkout_pre_ck", &sysclkout_pre_ck),
- CLK(NULL, "clkout2_div_ck", &clkout2_div_ck),
- CLK(NULL, "timer_32k_ck", &clkdiv32k_ick),
- CLK(NULL, "timer_sys_ck", &sys_clkin_ck),
- CLK(NULL, "dbg_sysclk_ck", &dbg_sysclk_ck),
- CLK(NULL, "dbg_clka_ck", &dbg_clka_ck),
- CLK(NULL, "stm_pmd_clock_mux_ck", &stm_pmd_clock_mux_ck),
- CLK(NULL, "trace_pmd_clk_mux_ck", &trace_pmd_clk_mux_ck),
- CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck),
- CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck),
- CLK(NULL, "clkout2_ck", &clkout2_ck),
- CLK("48300200.ehrpwm", "tbclk", &ehrpwm0_tbclk),
- CLK("48302200.ehrpwm", "tbclk", &ehrpwm1_tbclk),
- CLK("48304200.ehrpwm", "tbclk", &ehrpwm2_tbclk),
-};
-
-
-static const char *enable_init_clks[] = {
- "dpll_ddr_m2_ck",
- "dpll_mpu_m2_ck",
- "l3_gclk",
- "l4hs_gclk",
- "l4fw_gclk",
- "l4ls_gclk",
- "clkout2_ck", /* Required for external peripherals like, Audio codecs */
-};
-
-int __init am33xx_clk_init(void)
-{
- if (soc_is_am33xx())
- cpu_mask = RATE_IN_AM33XX;
-
- omap_clocks_register(am33xx_clks, ARRAY_SIZE(am33xx_clks));
-
- omap2_clk_disable_autoidle_all();
-
- omap2_clk_enable_init_clocks(enable_init_clks,
- ARRAY_SIZE(enable_init_clks));
-
- /* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always
- * physically present, in such a case HWMOD enabling of
- * clock would be failure with default parent. And timer
- * probe thinks clock is already enabled, this leads to
- * crash upon accessing timer 3 & 6 registers in probe.
- * Fix by setting parent of both these timers to master
- * oscillator clock.
- */
-
- clk_set_parent(&timer3_fck, &sys_clkin_ck);
- clk_set_parent(&timer6_fck, &sys_clkin_ck);
- /*
- * The On-Chip 32K RC Osc clock is not an accurate clock-source as per
- * the design/spec, so as a result, for example, timer which supposed
- * to get expired @60Sec, but will expire somewhere ~@40Sec, which is
- * not expected by any use-case, so change WDT1 clock source to PRCM
- * 32KHz clock.
- */
- clk_set_parent(&wdt1_fck, &clkdiv32k_ick);
-
- return 0;
-}
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 1a83c3c..63b77f0 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -2,6 +2,7 @@ ifneq ($(CONFIG_OF),)
obj-y += clk.o dpll.o autoidle.o divider.o \
fixed-factor.o gate.o clockdomain.o \
mux-gate.o mux.o apll.o
+obj-$(CONFIG_SOC_AM33XX) += clk-33xx.o
obj-$(CONFIG_ARCH_OMAP4) += clk-44xx.o
obj-$(CONFIG_SOC_OMAP5) += clk-54xx.o
obj-$(CONFIG_SOC_DRA7XX) += clk-7xx.o
--
1.7.9.5
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 27/36] CLK: TI: add interface clock support for OMAP3
2013-09-25 8:48 ` Tero Kristo
@ 2013-09-25 8:48 ` Tero Kristo
-1 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-omap-u79uwXL29TY76Z2rM5mHXA, paul-DWxLp4Yu+b8AvxtiuMwx3w,
tony-4v6yS6AI5VpBDgjK7y7TUQ, nm-l0cyMroinI0, rnayak-l0cyMroinI0,
bcousson-rdvid1DuHRBWk0Htik3J/w,
mturquette-QSEj5FYQhm4dnm+yROfE0A
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
OMAP3 has interface clocks in addition to functional clocks, which
require special handling for the autoidle and idle status register
offsets mainly.
Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
.../devicetree/bindings/clock/ti/interface.txt | 52 ++++++++
arch/arm/mach-omap2/clock.h | 6 -
drivers/clk/ti/Makefile | 1 +
drivers/clk/ti/interface.c | 124 ++++++++++++++++++++
include/linux/clk/ti.h | 5 +
5 files changed, 182 insertions(+), 6 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/ti/interface.txt
create mode 100644 drivers/clk/ti/interface.c
diff --git a/Documentation/devicetree/bindings/clock/ti/interface.txt b/Documentation/devicetree/bindings/clock/ti/interface.txt
new file mode 100644
index 0000000..f3e43a9
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/interface.txt
@@ -0,0 +1,52 @@
+Binding for Texas Instruments interface clock.
+
+This binding uses the common clock binding[1]. This clock is
+quite much similar to the basic gate-clock [2], however,
+it supports a number of additional features, including
+companion clock finding (match corresponding functional gate
+clock) and hardware autoidle enable / disable.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/clock/gate-clock.txt
+
+Required properties:
+- compatible : shall be one of:
+ "ti,omap3-interface-clock" - basic OMAP3 interface clock
+ "ti,omap3-no-wait-interface-clock" - interface clock which has no hardware
+ capability for waiting clock to be ready
+ "ti,omap3-hsotgusb-interface-clock" - interface clock with USB specific HW
+ handling
+ "ti,omap3-dss-interface-clock" - interface clock with DSS specific HW handling
+ "ti,omap3-ssi-interface-clock" - interface clock with SSI specific HW handling
+ "ti,am35xx-interface-clock" - interface clock with AM35xx specific HW handling
+- #clock-cells : from common clock binding; shall be set to 0
+- clocks : link to phandle of parent clock
+- reg : base address for the control register
+
+Optional properties:
+- ti,bit-shift : bit shift for the bit enabling/disabling the clock (default 0)
+
+Examples:
+ aes1_ick: aes1_ick@48004a14 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&security_l4_ick2>;
+ reg = <0x48004a14 0x4>;
+ ti,bit-shift = <3>;
+ };
+
+ cam_ick: cam_ick@48004f10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-no-wait-interface-clock";
+ clocks = <&l4_ick>;
+ reg = <0x48004f10 0x4>;
+ ti,bit-shift = <0>;
+ };
+
+ ssi_ick_3430es2: ssi_ick_3430es2@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-ssi-interface-clock";
+ clocks = <&ssi_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <0>;
+ };
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 2e6cbeb..d1b227e 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -266,14 +266,8 @@ extern const struct clksel_rate gfx_l3_rates[];
extern const struct clksel_rate dsp_ick_rates[];
extern struct clk dummy_ck;
-extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
-extern const struct clk_hw_omap_ops clkhwops_iclk;
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait;
-extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
-extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
-extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait;
-extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait;
extern const struct clk_hw_omap_ops clkhwops_apll54;
extern const struct clk_hw_omap_ops clkhwops_apll96;
extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll;
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 63b77f0..1ecb1a4 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -3,6 +3,7 @@ obj-y += clk.o dpll.o autoidle.o divider.o \
fixed-factor.o gate.o clockdomain.o \
mux-gate.o mux.o apll.o
obj-$(CONFIG_SOC_AM33XX) += clk-33xx.o
+obj-$(CONFIG_ARCH_OMAP3) += interface.o
obj-$(CONFIG_ARCH_OMAP4) += clk-44xx.o
obj-$(CONFIG_SOC_OMAP5) += clk-54xx.o
obj-$(CONFIG_SOC_DRA7XX) += clk-7xx.o
diff --git a/drivers/clk/ti/interface.c b/drivers/clk/ti/interface.c
new file mode 100644
index 0000000..1e50fba
--- /dev/null
+++ b/drivers/clk/ti/interface.c
@@ -0,0 +1,124 @@
+/*
+ * OMAP interface clock support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk/ti.h>
+
+static const struct clk_ops ti_interface_clk_ops = {
+ .init = &omap2_init_clk_clkdm,
+ .enable = &omap2_dflt_clk_enable,
+ .disable = &omap2_dflt_clk_disable,
+ .is_enabled = &omap2_dflt_clk_is_enabled,
+};
+
+static void __init _of_ti_interface_clk_setup(struct device_node *node,
+ const struct clk_hw_omap_ops *ops)
+{
+ struct clk *clk;
+ struct clk_init_data init = { NULL };
+ struct clk_hw_omap *clk_hw;
+ const char *clk_name = node->name;
+ const char *parent_name;
+ u32 val;
+
+ clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
+ if (!clk_hw) {
+ pr_err("%s: could not allocate clk_hw_omap\n", __func__);
+ return;
+ }
+
+ clk_hw->hw.init = &init;
+ clk_hw->ops = ops;
+ clk_hw->enable_reg = of_iomap(node, 0);
+
+ if (!of_property_read_u32(node, "ti,bit-shift", &val))
+ clk_hw->enable_bit = val;
+
+ of_property_read_string(node, "clock-output-names", &clk_name);
+
+ init.name = clk_name;
+ init.ops = &ti_interface_clk_ops;
+ init.flags = 0;
+
+ parent_name = of_clk_get_parent_name(node, 0);
+ if (!parent_name) {
+ pr_err("%s: %s must have a parent\n", __func__, clk_name);
+ goto cleanup;
+ }
+
+ init.num_parents = 1;
+ init.parent_names = &parent_name;
+
+ clk = clk_register(NULL, &clk_hw->hw);
+
+ if (!IS_ERR(clk)) {
+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
+ omap2_init_clk_hw_omap_clocks(clk);
+ return;
+ }
+
+cleanup:
+ kfree(clk_hw);
+}
+
+static void __init of_ti_interface_clk_setup(struct device_node *node)
+{
+ _of_ti_interface_clk_setup(node, &clkhwops_iclk_wait);
+}
+CLK_OF_DECLARE(ti_interface_clk, "ti,omap3-interface-clock",
+ of_ti_interface_clk_setup);
+
+static void __init of_ti_no_wait_interface_clk_setup(struct device_node *node)
+{
+ _of_ti_interface_clk_setup(node, &clkhwops_iclk);
+}
+CLK_OF_DECLARE(ti_no_wait_interface_clk, "ti,omap3-no-wait-interface-clock",
+ of_ti_no_wait_interface_clk_setup);
+
+static void __init
+of_ti_hsotgusb_interface_clk_setup(struct device_node *node)
+{
+ _of_ti_interface_clk_setup(node,
+ &clkhwops_omap3430es2_iclk_hsotgusb_wait);
+}
+CLK_OF_DECLARE(ti_hsotgusb_interface_clk, "ti,omap3-hsotgusb-interface-clock",
+ of_ti_hsotgusb_interface_clk_setup);
+
+static void __init of_ti_dss_interface_clk_setup(struct device_node *node)
+{
+ _of_ti_interface_clk_setup(node,
+ &clkhwops_omap3430es2_iclk_dss_usbhost_wait);
+}
+CLK_OF_DECLARE(ti_dss_interface_clk, "ti,omap3-dss-interface-clock",
+ of_ti_dss_interface_clk_setup);
+
+static void __init of_ti_ssi_interface_clk_setup(struct device_node *node)
+{
+ _of_ti_interface_clk_setup(node, &clkhwops_omap3430es2_iclk_ssi_wait);
+}
+CLK_OF_DECLARE(ti_ssi_interface_clk, "ti,omap3-ssi-interface-clock",
+ of_ti_ssi_interface_clk_setup);
+
+static void __init of_ti_am35xx_interface_clk_setup(struct device_node *node)
+{
+ _of_ti_interface_clk_setup(node, &clkhwops_am35xx_ipss_wait);
+}
+CLK_OF_DECLARE(ti_am35xx_interface_clk, "ti,am35xx-interface-clock",
+ of_ti_am35xx_interface_clk_setup);
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 0748581..88d7497 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -239,5 +239,10 @@ extern const struct clk_hw_omap_ops clkhwops_wait;
extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
+extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait;
+extern const struct clk_hw_omap_ops clkhwops_iclk;
+extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
+extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
+extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
#endif
--
1.7.9.5
--
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^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 27/36] CLK: TI: add interface clock support for OMAP3
@ 2013-09-25 8:48 ` Tero Kristo
0 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-arm-kernel
OMAP3 has interface clocks in addition to functional clocks, which
require special handling for the autoidle and idle status register
offsets mainly.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
.../devicetree/bindings/clock/ti/interface.txt | 52 ++++++++
arch/arm/mach-omap2/clock.h | 6 -
drivers/clk/ti/Makefile | 1 +
drivers/clk/ti/interface.c | 124 ++++++++++++++++++++
include/linux/clk/ti.h | 5 +
5 files changed, 182 insertions(+), 6 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/ti/interface.txt
create mode 100644 drivers/clk/ti/interface.c
diff --git a/Documentation/devicetree/bindings/clock/ti/interface.txt b/Documentation/devicetree/bindings/clock/ti/interface.txt
new file mode 100644
index 0000000..f3e43a9
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/interface.txt
@@ -0,0 +1,52 @@
+Binding for Texas Instruments interface clock.
+
+This binding uses the common clock binding[1]. This clock is
+quite much similar to the basic gate-clock [2], however,
+it supports a number of additional features, including
+companion clock finding (match corresponding functional gate
+clock) and hardware autoidle enable / disable.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/clock/gate-clock.txt
+
+Required properties:
+- compatible : shall be one of:
+ "ti,omap3-interface-clock" - basic OMAP3 interface clock
+ "ti,omap3-no-wait-interface-clock" - interface clock which has no hardware
+ capability for waiting clock to be ready
+ "ti,omap3-hsotgusb-interface-clock" - interface clock with USB specific HW
+ handling
+ "ti,omap3-dss-interface-clock" - interface clock with DSS specific HW handling
+ "ti,omap3-ssi-interface-clock" - interface clock with SSI specific HW handling
+ "ti,am35xx-interface-clock" - interface clock with AM35xx specific HW handling
+- #clock-cells : from common clock binding; shall be set to 0
+- clocks : link to phandle of parent clock
+- reg : base address for the control register
+
+Optional properties:
+- ti,bit-shift : bit shift for the bit enabling/disabling the clock (default 0)
+
+Examples:
+ aes1_ick: aes1_ick at 48004a14 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&security_l4_ick2>;
+ reg = <0x48004a14 0x4>;
+ ti,bit-shift = <3>;
+ };
+
+ cam_ick: cam_ick at 48004f10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-no-wait-interface-clock";
+ clocks = <&l4_ick>;
+ reg = <0x48004f10 0x4>;
+ ti,bit-shift = <0>;
+ };
+
+ ssi_ick_3430es2: ssi_ick_3430es2 at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-ssi-interface-clock";
+ clocks = <&ssi_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <0>;
+ };
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 2e6cbeb..d1b227e 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -266,14 +266,8 @@ extern const struct clksel_rate gfx_l3_rates[];
extern const struct clksel_rate dsp_ick_rates[];
extern struct clk dummy_ck;
-extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
-extern const struct clk_hw_omap_ops clkhwops_iclk;
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait;
-extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
-extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
-extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait;
-extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait;
extern const struct clk_hw_omap_ops clkhwops_apll54;
extern const struct clk_hw_omap_ops clkhwops_apll96;
extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll;
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 63b77f0..1ecb1a4 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -3,6 +3,7 @@ obj-y += clk.o dpll.o autoidle.o divider.o \
fixed-factor.o gate.o clockdomain.o \
mux-gate.o mux.o apll.o
obj-$(CONFIG_SOC_AM33XX) += clk-33xx.o
+obj-$(CONFIG_ARCH_OMAP3) += interface.o
obj-$(CONFIG_ARCH_OMAP4) += clk-44xx.o
obj-$(CONFIG_SOC_OMAP5) += clk-54xx.o
obj-$(CONFIG_SOC_DRA7XX) += clk-7xx.o
diff --git a/drivers/clk/ti/interface.c b/drivers/clk/ti/interface.c
new file mode 100644
index 0000000..1e50fba
--- /dev/null
+++ b/drivers/clk/ti/interface.c
@@ -0,0 +1,124 @@
+/*
+ * OMAP interface clock support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo <t-kristo@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk/ti.h>
+
+static const struct clk_ops ti_interface_clk_ops = {
+ .init = &omap2_init_clk_clkdm,
+ .enable = &omap2_dflt_clk_enable,
+ .disable = &omap2_dflt_clk_disable,
+ .is_enabled = &omap2_dflt_clk_is_enabled,
+};
+
+static void __init _of_ti_interface_clk_setup(struct device_node *node,
+ const struct clk_hw_omap_ops *ops)
+{
+ struct clk *clk;
+ struct clk_init_data init = { NULL };
+ struct clk_hw_omap *clk_hw;
+ const char *clk_name = node->name;
+ const char *parent_name;
+ u32 val;
+
+ clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
+ if (!clk_hw) {
+ pr_err("%s: could not allocate clk_hw_omap\n", __func__);
+ return;
+ }
+
+ clk_hw->hw.init = &init;
+ clk_hw->ops = ops;
+ clk_hw->enable_reg = of_iomap(node, 0);
+
+ if (!of_property_read_u32(node, "ti,bit-shift", &val))
+ clk_hw->enable_bit = val;
+
+ of_property_read_string(node, "clock-output-names", &clk_name);
+
+ init.name = clk_name;
+ init.ops = &ti_interface_clk_ops;
+ init.flags = 0;
+
+ parent_name = of_clk_get_parent_name(node, 0);
+ if (!parent_name) {
+ pr_err("%s: %s must have a parent\n", __func__, clk_name);
+ goto cleanup;
+ }
+
+ init.num_parents = 1;
+ init.parent_names = &parent_name;
+
+ clk = clk_register(NULL, &clk_hw->hw);
+
+ if (!IS_ERR(clk)) {
+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
+ omap2_init_clk_hw_omap_clocks(clk);
+ return;
+ }
+
+cleanup:
+ kfree(clk_hw);
+}
+
+static void __init of_ti_interface_clk_setup(struct device_node *node)
+{
+ _of_ti_interface_clk_setup(node, &clkhwops_iclk_wait);
+}
+CLK_OF_DECLARE(ti_interface_clk, "ti,omap3-interface-clock",
+ of_ti_interface_clk_setup);
+
+static void __init of_ti_no_wait_interface_clk_setup(struct device_node *node)
+{
+ _of_ti_interface_clk_setup(node, &clkhwops_iclk);
+}
+CLK_OF_DECLARE(ti_no_wait_interface_clk, "ti,omap3-no-wait-interface-clock",
+ of_ti_no_wait_interface_clk_setup);
+
+static void __init
+of_ti_hsotgusb_interface_clk_setup(struct device_node *node)
+{
+ _of_ti_interface_clk_setup(node,
+ &clkhwops_omap3430es2_iclk_hsotgusb_wait);
+}
+CLK_OF_DECLARE(ti_hsotgusb_interface_clk, "ti,omap3-hsotgusb-interface-clock",
+ of_ti_hsotgusb_interface_clk_setup);
+
+static void __init of_ti_dss_interface_clk_setup(struct device_node *node)
+{
+ _of_ti_interface_clk_setup(node,
+ &clkhwops_omap3430es2_iclk_dss_usbhost_wait);
+}
+CLK_OF_DECLARE(ti_dss_interface_clk, "ti,omap3-dss-interface-clock",
+ of_ti_dss_interface_clk_setup);
+
+static void __init of_ti_ssi_interface_clk_setup(struct device_node *node)
+{
+ _of_ti_interface_clk_setup(node, &clkhwops_omap3430es2_iclk_ssi_wait);
+}
+CLK_OF_DECLARE(ti_ssi_interface_clk, "ti,omap3-ssi-interface-clock",
+ of_ti_ssi_interface_clk_setup);
+
+static void __init of_ti_am35xx_interface_clk_setup(struct device_node *node)
+{
+ _of_ti_interface_clk_setup(node, &clkhwops_am35xx_ipss_wait);
+}
+CLK_OF_DECLARE(ti_am35xx_interface_clk, "ti,am35xx-interface-clock",
+ of_ti_am35xx_interface_clk_setup);
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 0748581..88d7497 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -239,5 +239,10 @@ extern const struct clk_hw_omap_ops clkhwops_wait;
extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
+extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait;
+extern const struct clk_hw_omap_ops clkhwops_iclk;
+extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
+extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
+extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 28/36] ARM: OMAP: hwmod: fix an incorrect clk type cast with _get_clkdm
2013-09-25 8:48 ` Tero Kristo
@ 2013-09-25 8:48 ` Tero Kristo
-1 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-omap-u79uwXL29TY76Z2rM5mHXA, paul-DWxLp4Yu+b8AvxtiuMwx3w,
tony-4v6yS6AI5VpBDgjK7y7TUQ, nm-l0cyMroinI0, rnayak-l0cyMroinI0,
bcousson-rdvid1DuHRBWk0Htik3J/w,
mturquette-QSEj5FYQhm4dnm+yROfE0A
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
If the main clock for a hwmod is of basic clock type, it is illegal to type
cast this to clk_hw_omap and will result in bogus data. Fixed by checking
the clock flags before attempting the type cast.
Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
arch/arm/mach-omap2/omap_hwmod.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index d35145d..5f8f587 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -656,6 +656,8 @@ static struct clockdomain *_get_clkdm(struct omap_hwmod *oh)
if (oh->clkdm) {
return oh->clkdm;
} else if (oh->_clk) {
+ if (__clk_get_flags(oh->_clk) & CLK_IS_BASIC)
+ return NULL;
clk = to_clk_hw_omap(__clk_get_hw(oh->_clk));
return clk->clkdm;
}
--
1.7.9.5
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
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^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 28/36] ARM: OMAP: hwmod: fix an incorrect clk type cast with _get_clkdm
@ 2013-09-25 8:48 ` Tero Kristo
0 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-arm-kernel
If the main clock for a hwmod is of basic clock type, it is illegal to type
cast this to clk_hw_omap and will result in bogus data. Fixed by checking
the clock flags before attempting the type cast.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/mach-omap2/omap_hwmod.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index d35145d..5f8f587 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -656,6 +656,8 @@ static struct clockdomain *_get_clkdm(struct omap_hwmod *oh)
if (oh->clkdm) {
return oh->clkdm;
} else if (oh->_clk) {
+ if (__clk_get_flags(oh->_clk) & CLK_IS_BASIC)
+ return NULL;
clk = to_clk_hw_omap(__clk_get_hw(oh->_clk));
return clk->clkdm;
}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 29/36] ARM: OMAP3: hwmod: initialize clkdm from clkdm_name
2013-09-25 8:48 ` Tero Kristo
@ 2013-09-25 8:48 ` Tero Kristo
-1 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-omap-u79uwXL29TY76Z2rM5mHXA, paul-DWxLp4Yu+b8AvxtiuMwx3w,
tony-4v6yS6AI5VpBDgjK7y7TUQ, nm-l0cyMroinI0, rnayak-l0cyMroinI0,
bcousson-rdvid1DuHRBWk0Htik3J/w,
mturquette-QSEj5FYQhm4dnm+yROfE0A
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
DT clocks are mostly missing clkdm info now, and this causes an issue with
counter32k which makes its slave idlemode wrong and prevents core idle.
Fixed by initializing the hwmod clkdm pointers for omap3 also which makes
sure the clkdm flag matching logic works properly.
This patch also changes the return value for _init_clkdm to 0 for
incorrect clkdm_name, as this a warning, not a fatal error.
Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
arch/arm/mach-omap2/omap_hwmod.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 5f8f587..ae33fae 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1546,7 +1546,7 @@ static int _init_clkdm(struct omap_hwmod *oh)
if (!oh->clkdm) {
pr_warning("omap_hwmod: %s: could not associate to clkdm %s\n",
oh->name, oh->clkdm_name);
- return -EINVAL;
+ return 0;
}
pr_debug("omap_hwmod: %s: associated to clkdm %s\n",
@@ -4117,6 +4117,7 @@ void __init omap_hwmod_init(void)
soc_ops.assert_hardreset = _omap2_assert_hardreset;
soc_ops.deassert_hardreset = _omap2_deassert_hardreset;
soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted;
+ soc_ops.init_clkdm = _init_clkdm;
} else if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) {
soc_ops.enable_module = _omap4_enable_module;
soc_ops.disable_module = _omap4_disable_module;
--
1.7.9.5
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 29/36] ARM: OMAP3: hwmod: initialize clkdm from clkdm_name
@ 2013-09-25 8:48 ` Tero Kristo
0 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-arm-kernel
DT clocks are mostly missing clkdm info now, and this causes an issue with
counter32k which makes its slave idlemode wrong and prevents core idle.
Fixed by initializing the hwmod clkdm pointers for omap3 also which makes
sure the clkdm flag matching logic works properly.
This patch also changes the return value for _init_clkdm to 0 for
incorrect clkdm_name, as this a warning, not a fatal error.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/mach-omap2/omap_hwmod.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 5f8f587..ae33fae 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1546,7 +1546,7 @@ static int _init_clkdm(struct omap_hwmod *oh)
if (!oh->clkdm) {
pr_warning("omap_hwmod: %s: could not associate to clkdm %s\n",
oh->name, oh->clkdm_name);
- return -EINVAL;
+ return 0;
}
pr_debug("omap_hwmod: %s: associated to clkdm %s\n",
@@ -4117,6 +4117,7 @@ void __init omap_hwmod_init(void)
soc_ops.assert_hardreset = _omap2_assert_hardreset;
soc_ops.deassert_hardreset = _omap2_deassert_hardreset;
soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted;
+ soc_ops.init_clkdm = _init_clkdm;
} else if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) {
soc_ops.enable_module = _omap4_enable_module;
soc_ops.disable_module = _omap4_disable_module;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 30/36] ARM: dts: omap3 clock data
2013-09-25 8:48 ` Tero Kristo
@ 2013-09-25 8:48 ` Tero Kristo
-1 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-omap-u79uwXL29TY76Z2rM5mHXA, paul-DWxLp4Yu+b8AvxtiuMwx3w,
tony-4v6yS6AI5VpBDgjK7y7TUQ, nm-l0cyMroinI0, rnayak-l0cyMroinI0,
bcousson-rdvid1DuHRBWk0Htik3J/w,
mturquette-QSEj5FYQhm4dnm+yROfE0A
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
This patch creates a unique node for each clock in the OMAP3 power,
reset and clock manager (PRCM).
TODO: add still missing am35xx only clock nodes
Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
arch/arm/boot/dts/am35xx-clocks.dtsi | 101 ++
arch/arm/boot/dts/omap3.dtsi | 7 +
arch/arm/boot/dts/omap3430es1-clocks.dtsi | 145 ++
arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi | 223 ++++
arch/arm/boot/dts/omap34xx.dtsi | 121 +-
.../omap36xx-am35xx-omap3430es2plus-clocks.dtsi | 186 +++
arch/arm/boot/dts/omap36xx-clocks.dtsi | 78 ++
.../boot/dts/omap36xx-omap3430es2plus-clocks.dtsi | 158 +++
arch/arm/boot/dts/omap36xx.dtsi | 122 +-
arch/arm/boot/dts/omap3xxx-clocks.dtsi | 1392 ++++++++++++++++++++
10 files changed, 2531 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/boot/dts/am35xx-clocks.dtsi
create mode 100644 arch/arm/boot/dts/omap3430es1-clocks.dtsi
create mode 100644 arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi
create mode 100644 arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
create mode 100644 arch/arm/boot/dts/omap36xx-clocks.dtsi
create mode 100644 arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
create mode 100644 arch/arm/boot/dts/omap3xxx-clocks.dtsi
diff --git a/arch/arm/boot/dts/am35xx-clocks.dtsi b/arch/arm/boot/dts/am35xx-clocks.dtsi
new file mode 100644
index 0000000..7f3af1a
--- /dev/null
+++ b/arch/arm/boot/dts/am35xx-clocks.dtsi
@@ -0,0 +1,101 @@
+/*
+ * Device Tree Source for AM35xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+ipss_ick: ipss_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,am35xx-interface-clock";
+ clocks = <&core_l3_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <4>;
+};
+
+rmii_ck: rmii_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+};
+
+pclk_ck: pclk_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <27000000>;
+};
+
+emac_ick: emac_ick@4800259c {
+ #clock-cells = <0>;
+ compatible = "ti,am35xx-gate-clock";
+ clocks = <&ipss_ick>;
+ reg = <0x4800259c 0x4>;
+ ti,bit-shift = <1>;
+};
+
+emac_fck: emac_fck@4800259c {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&rmii_ck>;
+ reg = <0x4800259c 0x4>;
+ ti,bit-shift = <9>;
+};
+
+vpfe_ick: vpfe_ick@4800259c {
+ #clock-cells = <0>;
+ compatible = "ti,am35xx-gate-clock";
+ clocks = <&ipss_ick>;
+ reg = <0x4800259c 0x4>;
+ ti,bit-shift = <2>;
+};
+
+vpfe_fck: vpfe_fck@4800259c {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&pclk_ck>;
+ reg = <0x4800259c 0x4>;
+ ti,bit-shift = <10>;
+};
+
+hsotgusb_ick_am35xx: hsotgusb_ick_am35xx@4800259c {
+ #clock-cells = <0>;
+ compatible = "ti,am35xx-gate-clock";
+ clocks = <&ipss_ick>;
+ reg = <0x4800259c 0x4>;
+ ti,bit-shift = <0>;
+};
+
+hsotgusb_fck_am35xx: hsotgusb_fck_am35xx@4800259c {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_ck>;
+ reg = <0x4800259c 0x4>;
+ ti,bit-shift = <8>;
+};
+
+hecc_ck: hecc_ck@4800259c {
+ #clock-cells = <0>;
+ compatible = "ti,am35xx-gate-clock";
+ clocks = <&sys_ck>;
+ reg = <0x4800259c 0x4>;
+ ti,bit-shift = <3>;
+};
+
+uart4_ick_am35xx: uart4_ick_am35xx@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <23>;
+};
+
+uart4_fck_am35xx: uart4_fck_am35xx@48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_48m_fck>;
+ reg = <0x48004a00 0x4>;
+ ti,bit-shift = <23>;
+};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 16420ae..bc11b83 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -533,4 +533,11 @@
ram-bits = <12>;
};
};
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ /include/ "omap3xxx-clocks.dtsi"
+ };
};
diff --git a/arch/arm/boot/dts/omap3430es1-clocks.dtsi b/arch/arm/boot/dts/omap3430es1-clocks.dtsi
new file mode 100644
index 0000000..2a7a137
--- /dev/null
+++ b/arch/arm/boot/dts/omap3430es1-clocks.dtsi
@@ -0,0 +1,145 @@
+/*
+ * Device Tree Source for OMAP3430 ES1 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+gfx_l3_ck: gfx_l3_ck@48004b10 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&l3_ick>;
+ reg = <0x48004b10 0x4>;
+ ti,bit-shift = <0>;
+};
+
+gfx_l3_fck: gfx_l3_fck@48004b40 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&l3_ick>;
+ reg = <0x48004b40 0x4>;
+ ti,max-div = <7>;
+ ti,index-starts-at-one;
+};
+
+gfx_l3_ick: gfx_l3_ick {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&gfx_l3_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+gfx_cg1_ck: gfx_cg1_ck@48004b00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&gfx_l3_fck>;
+ reg = <0x48004b00 0x4>;
+ ti,bit-shift = <1>;
+};
+
+gfx_cg2_ck: gfx_cg2_ck@48004b00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&gfx_l3_fck>;
+ reg = <0x48004b00 0x4>;
+ ti,bit-shift = <2>;
+};
+
+d2d_26m_fck: d2d_26m_fck@48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&sys_ck>;
+ reg = <0x48004a00 0x4>;
+ ti,bit-shift = <3>;
+};
+
+fshostusb_fck: fshostusb_fck@48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_48m_fck>;
+ reg = <0x48004a00 0x4>;
+ ti,bit-shift = <5>;
+};
+
+ssi_ssr_fck_3430es1: ssi_ssr_fck_3430es1@48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,no-wait-mux-gate-clock";
+ clocks = <&corex2_fck>;
+ ti,div-bit-shift = <8>;
+ ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
+ reg-names = "gate-reg", "div-reg";
+ reg = <0x48004a00 0x4>, <0x48004a40 0x4>;
+ ti,gate-bit-shift = <0>;
+};
+
+ssi_sst_fck_3430es1: ssi_sst_fck_3430es1 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&ssi_ssr_fck_3430es1>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+hsotgusb_ick_3430es1: hsotgusb_ick_3430es1@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-no-wait-interface-clock";
+ clocks = <&core_l3_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <4>;
+};
+
+fac_ick: fac_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <8>;
+};
+
+ssi_l4_ick: ssi_l4_ick {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l4_ick>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+ssi_ick_3430es1: ssi_ick_3430es1@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-no-wait-interface-clock";
+ clocks = <&ssi_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <0>;
+};
+
+usb_l4_ick: usb_l4_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-mux-gate-clock";
+ clocks = <&l4_ick>;
+ ti,div-bit-shift = <4>;
+ ti,max-div = <1>;
+ reg-names = "gate-reg", "div-reg";
+ reg = <0x48004a10 0x4>, <0x48004a40 0x4>;
+ ti,gate-bit-shift = <5>;
+ ti,div-index-starts-at-one;
+};
+
+dss1_alwon_fck_3430es1: dss1_alwon_fck_3430es1@48004e00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll4_m4x2_ck>;
+ reg = <0x48004e00 0x4>;
+ ti,bit-shift = <0>;
+};
+
+dss_ick_3430es1: dss_ick_3430es1@48004e10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-no-wait-interface-clock";
+ clocks = <&l4_ick>;
+ reg = <0x48004e10 0x4>;
+ ti,bit-shift = <0>;
+};
diff --git a/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi
new file mode 100644
index 0000000..48b6a5c
--- /dev/null
+++ b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi
@@ -0,0 +1,223 @@
+/*
+ * Device Tree Source for OMAP34xx/OMAP36xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+security_l4_ick2: security_l4_ick2 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l4_ick>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+aes1_ick: aes1_ick@48004a14 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&security_l4_ick2>;
+ ti,bit-shift = <3>;
+ reg = <0x48004a14 0x4>;
+};
+
+rng_ick: rng_ick@48004a14 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&security_l4_ick2>;
+ reg = <0x48004a14 0x4>;
+ ti,bit-shift = <2>;
+};
+
+sha11_ick: sha11_ick@48004a14 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&security_l4_ick2>;
+ reg = <0x48004a14 0x4>;
+ ti,bit-shift = <1>;
+};
+
+des1_ick: des1_ick@48004a14 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&security_l4_ick2>;
+ reg = <0x48004a14 0x4>;
+ ti,bit-shift = <0>;
+};
+
+cam_mclk: cam_mclk@48004f00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll4_m5x2_ck>;
+ ti,bit-shift = <0>;
+ reg = <0x48004f00 0x4>;
+ ti,set-rate-parent;
+};
+
+cam_ick: cam_ick@48004f10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-no-wait-interface-clock";
+ clocks = <&l4_ick>;
+ reg = <0x48004f10 0x4>;
+ ti,bit-shift = <0>;
+};
+
+csi2_96m_fck: csi2_96m_fck@48004f00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&core_96m_fck>;
+ reg = <0x48004f00 0x4>;
+ ti,bit-shift = <1>;
+};
+
+security_l3_ick: security_l3_ick {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l3_ick>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+pka_ick: pka_ick@48004a14 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&security_l3_ick>;
+ reg = <0x48004a14 0x4>;
+ ti,bit-shift = <4>;
+};
+
+icr_ick: icr_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <29>;
+};
+
+des2_ick: des2_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <26>;
+};
+
+mspro_ick: mspro_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <23>;
+};
+
+mailboxes_ick: mailboxes_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <7>;
+};
+
+ssi_l4_ick: ssi_l4_ick {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l4_ick>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+sr1_fck: sr1_fck@48004c00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&sys_ck>;
+ reg = <0x48004c00 0x4>;
+ ti,bit-shift = <6>;
+};
+
+sr2_fck: sr2_fck@48004c00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&sys_ck>;
+ reg = <0x48004c00 0x4>;
+ ti,bit-shift = <7>;
+};
+
+sr_l4_ick: sr_l4_ick {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l4_ick>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dpll2_fck: dpll2_fck@48004040 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&core_ck>;
+ ti,bit-shift = <19>;
+ ti,max-div = <7>;
+ reg = <0x48004040 0x4>;
+ ti,index-starts-at-one;
+};
+
+dpll2_ck: dpll2_ck@48004004 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-dpll-clock";
+ clocks = <&sys_ck>, <&dpll2_fck>;
+ reg = <0x48004004 0x4>, <0x48004024 0x4>, <0x48004034 0x4>, <0x48004040 0x4>;
+ ti,low-power-stop;
+ ti,lock;
+ ti,low-power-bypass;
+};
+
+dpll2_m2_ck: dpll2_m2_ck@48004044 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll2_ck>;
+ reg = <0x48004044 0x4>;
+ ti,max-div = <31>;
+ ti,index-starts-at-one;
+};
+
+iva2_ck: iva2_ck@48004000 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&dpll2_m2_ck>;
+ reg = <0x48004000 0x4>;
+ ti,bit-shift = <0>;
+};
+
+modem_fck: modem_fck@48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&sys_ck>;
+ reg = <0x48004a00 0x4>;
+ ti,bit-shift = <31>;
+};
+
+sad2d_ick: sad2d_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&l3_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <3>;
+};
+
+mad2d_ick: mad2d_ick@48004a18 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&l3_ick>;
+ reg = <0x48004a18 0x4>;
+ ti,bit-shift = <3>;
+};
+
+mspro_fck: mspro_fck@48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_96m_fck>;
+ reg = <0x48004a00 0x4>;
+ ti,bit-shift = <23>;
+};
diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi
index 5355d61..2ed7c69 100644
--- a/arch/arm/boot/dts/omap34xx.dtsi
+++ b/arch/arm/boot/dts/omap34xx.dtsi
@@ -25,4 +25,123 @@
clock-latency = <300000>; /* From legacy driver */
};
};
-};
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ /include/ "omap34xx-omap36xx-clocks.dtsi"
+ /include/ "omap36xx-omap3430es2plus-clocks.dtsi"
+ /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
+ };
+
+ clockdomains {
+ usbhost_clkdm: usbhost_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&usbhost_48m_fck>, <&usbhost_ick>,
+ <&usbhost_120m_fck>;
+ };
+
+ wkup_clkdm: wkup_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&wdt1_ick>, <&sr2_fck>, <&omap_32ksync_ick>,
+ <&wdt2_fck>, <&gpt12_ick>, <&sr1_fck>,
+ <&gpio1_ick>, <&gpt1_ick>, <&wdt2_ick>,
+ <&usim_ick>, <&gpio1_dbck>;
+ };
+
+ cam_clkdm: cam_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&csi2_96m_fck>, <&cam_ick>;
+ };
+
+ dpll4_clkdm: dpll4_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll4_ck>;
+ };
+
+ sgx_clkdm: sgx_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&sgx_ick>;
+ };
+
+ dpll3_clkdm: dpll3_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll3_ck>;
+ };
+
+ iva2_clkdm: iva2_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&iva2_ck>;
+ };
+
+ dpll1_clkdm: dpll1_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll1_ck>;
+ };
+
+ dpll2_clkdm: dpll2_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll2_ck>;
+ };
+
+ dpll5_clkdm: dpll5_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll5_ck>;
+ };
+
+ dss_clkdm: dss_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dss_tv_fck>, <&dss1_alwon_fck_3430es2>,
+ <&dss_96m_fck>, <&dss2_alwon_fck>,
+ <&dss_ick_3430es2>;
+ };
+
+ core_l4_clkdm: core_l4_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&mmchs1_ick>, <&mspro_ick>, <&mmchs2_ick>,
+ <&mcspi4_fck>, <&i2c3_fck>, <&mcspi2_ick>,
+ <&uart2_ick>, <&mcspi3_ick>, <&i2c1_fck>,
+ <&sha12_ick>, <&mcspi3_fck>, <&mailboxes_ick>,
+ <&uart2_fck>, <&mmchs2_fck>, <&usbtll_fck>,
+ <&mmchs3_ick>, <&des2_ick>, <&i2c2_ick>,
+ <&i2c1_ick>, <&icr_ick>, <&hdq_fck>,
+ <&uart1_ick>, <&ts_fck>, <&usbtll_ick>,
+ <&hdq_ick>, <&mcbsp5_ick>, <&aes2_ick>,
+ <&mcspi1_ick>, <&mmchs1_fck>, <&i2c3_ick>,
+ <&mcspi1_fck>, <&mmchs3_fck>, <&mcspi4_ick>,
+ <&omapctrl_ick>, <&mspro_fck>, <&mcbsp1_ick>,
+ <&mcspi2_fck>, <&ssi_ick_3430es2>,
+ <&gpt10_ick>, <&cpefuse_fck>, <&i2c2_fck>,
+ <&gpt11_ick>, <&uart1_fck>;
+ };
+
+ core_l3_clkdm: core_l3_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es2>;
+ };
+
+ per_clkdm: per_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&gpt2_ick>, <&uart3_fck>, <&gpio3_ick>,
+ <&mcbsp2_ick>, <&gpt6_ick>, <&gpio2_dbck>,
+ <&mcbsp4_ick>, <&gpio4_dbck>, <&gpt4_ick>,
+ <&gpio5_dbck>, <&mcbsp3_ick>, <&gpio3_dbck>,
+ <&gpt8_ick>, <&gpt5_ick>, <&gpio6_dbck>,
+ <&uart3_ick>, <&gpt7_ick>, <&gpio2_ick>,
+ <&gpio6_ick>, <&gpt9_ick>, <&gpt3_ick>,
+ <&gpio5_ick>, <&wdt3_fck>, <&gpio4_ick>,
+ <&wdt3_ick>, <&uart4_ick>;
+ };
+
+ emu_clkdm: emu_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&emu_src_ck>;
+ };
+
+ d2d_clkdm: d2d_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&mad2d_ick>, <&sad2d_ick>, <&modem_fck>;
+ };
+ };
+};
\ No newline at end of file
diff --git a/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
new file mode 100644
index 0000000..a31bc85
--- /dev/null
+++ b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
@@ -0,0 +1,186 @@
+/*
+ * Device Tree Source for OMAP36xx/AM35xx/OMAP34xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+dpll5_ck: dpll5_ck@48004d04 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-dpll-clock";
+ clocks = <&sys_ck>, <&sys_ck>;
+ reg = <0x48004d04 0x4>, <0x48004d24 0x4>, <0x48004d34 0x4>, <0x48004d4c 0x4>;
+};
+
+dpll5_m2_ck: dpll5_m2_ck@48004d50 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll5_ck>;
+ reg = <0x48004d50 0x4>;
+ ti,max-div = <31>;
+ ti,index-starts-at-one;
+};
+
+core_d3_ck: core_d3_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&core_ck>;
+ clock-mult = <1>;
+ clock-div = <3>;
+};
+
+core_d4_ck: core_d4_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&core_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+};
+
+core_d6_ck: core_d6_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&core_ck>;
+ clock-mult = <1>;
+ clock-div = <6>;
+};
+
+omap_192m_alwon_fck: omap_192m_alwon_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll4_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+core_d2_ck: core_d2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&core_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+corex2_d3_fck: corex2_d3_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&corex2_fck>;
+ clock-mult = <1>;
+ clock-div = <3>;
+};
+
+corex2_d5_fck: corex2_d5_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&corex2_fck>;
+ clock-mult = <1>;
+ clock-div = <5>;
+};
+
+sgx_fck: sgx_fck@48004b00 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-gate-clock";
+ clocks = <&core_d3_ck>, <&core_d4_ck>, <&core_d6_ck>, <&cm_96m_fck>, <&omap_192m_alwon_fck>, <&core_d2_ck>, <&corex2_d3_fck>, <&corex2_d5_fck>;
+ ti,gate-bit-shift = <1>;
+ reg = <0x48004b00 0x4>, <0x48004b40 0x4>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+sgx_ick: sgx_ick@48004b10 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&l3_ick>;
+ reg = <0x48004b10 0x4>;
+ ti,bit-shift = <0>;
+};
+
+cpefuse_fck: cpefuse_fck@48004a08 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_ck>;
+ reg = <0x48004a08 0x4>;
+ ti,bit-shift = <0>;
+};
+
+ts_fck: ts_fck@48004a08 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&omap_32k_fck>;
+ reg = <0x48004a08 0x4>;
+ ti,bit-shift = <1>;
+};
+
+usbtll_fck: usbtll_fck@48004a08 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&dpll5_m2_ck>;
+ reg = <0x48004a08 0x4>;
+ ti,bit-shift = <2>;
+};
+
+usbtll_ick: usbtll_ick@48004a18 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a18 0x4>;
+ ti,bit-shift = <2>;
+};
+
+mmchs3_ick: mmchs3_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <30>;
+};
+
+mmchs3_fck: mmchs3_fck@48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_96m_fck>;
+ reg = <0x48004a00 0x4>;
+ ti,bit-shift = <30>;
+};
+
+dss1_alwon_fck_3430es2: dss1_alwon_fck_3430es2@48004e00 {
+ #clock-cells = <0>;
+ compatible = "ti,dss-gate-clock";
+ clocks = <&dpll4_m4x2_ck>;
+ reg = <0x48004e00 0x4>;
+ ti,bit-shift = <0>;
+};
+
+dss_ick_3430es2: dss_ick_3430es2@48004e10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-dss-interface-clock";
+ clocks = <&l4_ick>;
+ reg = <0x48004e10 0x4>;
+ ti,bit-shift = <0>;
+};
+
+usbhost_120m_fck: usbhost_120m_fck@48005400 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll5_m2_ck>;
+ reg = <0x48005400 0x4>;
+ ti,bit-shift = <1>;
+};
+
+usbhost_48m_fck: usbhost_48m_fck@48005400 {
+ #clock-cells = <0>;
+ compatible = "ti,dss-gate-clock";
+ clocks = <&omap_48m_fck>;
+ reg = <0x48005400 0x4>;
+ ti,bit-shift = <0>;
+};
+
+usbhost_ick: usbhost_ick@48005410 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-dss-interface-clock";
+ clocks = <&l4_ick>;
+ reg = <0x48005410 0x4>;
+ ti,bit-shift = <0>;
+};
diff --git a/arch/arm/boot/dts/omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap36xx-clocks.dtsi
new file mode 100644
index 0000000..0a3a697
--- /dev/null
+++ b/arch/arm/boot/dts/omap36xx-clocks.dtsi
@@ -0,0 +1,78 @@
+/*
+ * Device Tree Source for OMAP36xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+dpll4_ck: dpll4_ck@48004d00 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-dpll-per-j-type-clock";
+ clocks = <&sys_ck>, <&sys_ck>;
+ reg = <0x48004d00 0x4>, <0x48004d20 0x4>, <0x48004d30 0x4>, <0x48004d44 0x4>;
+};
+
+dpll4_m2x2_ck: dpll4_m2x2_ck@48004d00 {
+ #clock-cells = <0>;
+ compatible = "ti,hsdiv-gate-clock";
+ clocks = <&dpll4_m2x2_mul_ck>;
+ ti,bit-shift = <0x1b>;
+ reg = <0x48004d00 0x4>;
+ ti,set-bit-to-disable;
+};
+
+dpll3_m3x2_ck: dpll3_m3x2_ck@48004d00 {
+ #clock-cells = <0>;
+ compatible = "ti,hsdiv-gate-clock";
+ clocks = <&dpll3_m3x2_mul_ck>;
+ ti,bit-shift = <0xc>;
+ reg = <0x48004d00 0x4>;
+ ti,set-bit-to-disable;
+};
+
+dpll4_m3x2_ck: dpll4_m3x2_ck@48004d00 {
+ #clock-cells = <0>;
+ compatible = "ti,hsdiv-gate-clock";
+ clocks = <&dpll4_m3x2_mul_ck>;
+ ti,bit-shift = <0x1c>;
+ reg = <0x48004d00 0x4>;
+ ti,set-bit-to-disable;
+};
+
+dpll4_m5x2_ck: dpll4_m5x2_ck@48004d00 {
+ #clock-cells = <0>;
+ compatible = "ti,hsdiv-gate-clock";
+ clocks = <&dpll4_m5x2_mul_ck>;
+ ti,bit-shift = <0x1e>;
+ reg = <0x48004d00 0x4>;
+ ti,set-bit-to-disable;
+ ti,set-rate-parent;
+};
+
+dpll4_m6x2_ck: dpll4_m6x2_ck@48004d00 {
+ #clock-cells = <0>;
+ compatible = "ti,hsdiv-gate-clock";
+ clocks = <&dpll4_m6x2_mul_ck>;
+ ti,bit-shift = <0x1f>;
+ reg = <0x48004d00 0x4>;
+ ti,set-bit-to-disable;
+};
+
+omap_192m_alwon_fck: omap_192m_alwon_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll4_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+uart4_fck: uart4_fck@48005000 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&per_48m_fck>;
+ reg = <0x48005000 0x4>;
+ ti,bit-shift = <18>;
+};
diff --git a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
new file mode 100644
index 0000000..a89206c
--- /dev/null
+++ b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
@@ -0,0 +1,158 @@
+/*
+ * Device Tree Source for OMAP34xx/OMAP36xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+ssi_ssr_fck_3430es2: ssi_ssr_fck_3430es2@48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,no-wait-mux-gate-clock";
+ clocks = <&corex2_fck>;
+ ti,div-bit-shift = <8>;
+ ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
+ reg-names = "gate-reg", "div-reg";
+ reg = <0x48004a00 0x4>, <0x48004a40 0x4>;
+ ti,gate-bit-shift = <0>;
+};
+
+ssi_sst_fck_3430es2: ssi_sst_fck_3430es2 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&ssi_ssr_fck_3430es2>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+hsotgusb_ick_3430es2: hsotgusb_ick_3430es2@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-hsotgusb-interface-clock";
+ clocks = <&core_l3_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <4>;
+};
+
+ssi_l4_ick: ssi_l4_ick {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l4_ick>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+ssi_ick_3430es2: ssi_ick_3430es2@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-ssi-interface-clock";
+ clocks = <&ssi_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <0>;
+};
+
+dpll5_ck: dpll5_ck@48004d04 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-dpll-clock";
+ clocks = <&sys_ck>, <&sys_ck>;
+ reg = <0x48004d04 0x4>, <0x48004d24 0x4>, <0x48004d34 0x4>, <0x48004d4c 0x4>;
+};
+
+dpll5_m2_ck: dpll5_m2_ck@48004d50 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll5_ck>;
+ reg = <0x48004d50 0x4>;
+ ti,max-div = <31>;
+ ti,index-starts-at-one;
+};
+
+dpll5_m2_d20_ck: dpll5_m2_d20_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll5_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <20>;
+};
+
+sys_d2_ck: sys_d2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+omap_96m_d2_fck: omap_96m_d2_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_96m_fck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+omap_96m_d4_fck: omap_96m_d4_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_96m_fck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+};
+
+omap_96m_d8_fck: omap_96m_d8_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_96m_fck>;
+ clock-mult = <1>;
+ clock-div = <8>;
+};
+
+omap_96m_d10_fck: omap_96m_d10_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_96m_fck>;
+ clock-mult = <1>;
+ clock-div = <10>;
+};
+
+dpll5_m2_d4_ck: dpll5_m2_d4_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll5_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+};
+
+dpll5_m2_d8_ck: dpll5_m2_d8_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll5_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <8>;
+};
+
+dpll5_m2_d16_ck: dpll5_m2_d16_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll5_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <16>;
+};
+
+usim_fck: usim_fck@48004c00 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-gate-clock";
+ clocks = <&sys_ck>, <&dpll5_m2_d20_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>;
+ ti,gate-bit-shift = <9>;
+ reg = <0x48004c00 0x4>, <0x48004c40 0x4>;
+ ti,mux-bit-shift = <3>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+usim_ick: usim_ick@48004c10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&wkup_l4_ick>;
+ reg = <0x48004c10 0x4>;
+ ti,bit-shift = <9>;
+};
diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi
index f8b3765..71fb6fb 100644
--- a/arch/arm/boot/dts/omap36xx.dtsi
+++ b/arch/arm/boot/dts/omap36xx.dtsi
@@ -35,4 +35,124 @@
clock-frequency = <48000000>;
};
};
-};
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ /include/ "omap36xx-clocks.dtsi"
+ /include/ "omap34xx-omap36xx-clocks.dtsi"
+ /include/ "omap36xx-omap3430es2plus-clocks.dtsi"
+ /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
+ };
+
+ clockdomains {
+ usbhost_clkdm: usbhost_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&usbhost_48m_fck>, <&usbhost_ick>,
+ <&usbhost_120m_fck>;
+ };
+
+ wkup_clkdm: wkup_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&wdt1_ick>, <&sr2_fck>, <&omap_32ksync_ick>,
+ <&wdt2_fck>, <&gpt12_ick>, <&sr1_fck>,
+ <&gpio1_ick>, <&gpt1_ick>, <&wdt2_ick>,
+ <&usim_ick>, <&gpio1_dbck>;
+ };
+
+ cam_clkdm: cam_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&csi2_96m_fck>, <&cam_ick>;
+ };
+
+ dpll4_clkdm: dpll4_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll4_ck>;
+ };
+
+ sgx_clkdm: sgx_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&sgx_ick>;
+ };
+
+ dpll3_clkdm: dpll3_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll3_ck>;
+ };
+
+ iva2_clkdm: iva2_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&iva2_ck>;
+ };
+
+ dpll1_clkdm: dpll1_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll1_ck>;
+ };
+
+ dpll5_clkdm: dpll5_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll5_ck>;
+ };
+
+ dpll2_clkdm: dpll2_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll2_ck>;
+ };
+
+ dss_clkdm: dss_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dss_tv_fck>, <&dss1_alwon_fck_3430es2>,
+ <&dss_96m_fck>, <&dss2_alwon_fck>,
+ <&dss_ick_3430es2>;
+ };
+
+ core_l4_clkdm: core_l4_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&mmchs1_ick>, <&mspro_ick>, <&mmchs2_ick>,
+ <&mcspi4_fck>, <&i2c3_fck>, <&mcspi2_ick>,
+ <&uart2_ick>, <&mcspi3_ick>, <&i2c1_fck>,
+ <&sha12_ick>, <&mcspi3_fck>, <&mailboxes_ick>,
+ <&uart2_fck>, <&mmchs2_fck>, <&usbtll_fck>,
+ <&mmchs3_ick>, <&des2_ick>, <&i2c2_ick>,
+ <&i2c1_ick>, <&icr_ick>, <&hdq_fck>,
+ <&uart1_ick>, <&ts_fck>, <&usbtll_ick>,
+ <&hdq_ick>, <&mcbsp5_ick>, <&aes2_ick>,
+ <&mcspi1_ick>, <&mmchs1_fck>, <&i2c3_ick>,
+ <&mcspi1_fck>, <&mmchs3_fck>, <&mcspi4_ick>,
+ <&omapctrl_ick>, <&mspro_fck>, <&mcbsp1_ick>,
+ <&mcspi2_fck>, <&ssi_ick_3430es2>,
+ <&gpt10_ick>, <&cpefuse_fck>, <&i2c2_fck>,
+ <&gpt11_ick>, <&uart1_fck>;
+ };
+
+ core_l3_clkdm: core_l3_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es2>;
+ };
+
+ per_clkdm: per_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&gpt2_ick>, <&uart3_fck>, <&gpio3_ick>,
+ <&mcbsp2_ick>, <&gpt6_ick>, <&gpio2_dbck>,
+ <&mcbsp4_ick>, <&gpio4_dbck>, <&gpt4_ick>,
+ <&gpio5_dbck>, <&mcbsp3_ick>, <&gpio3_dbck>,
+ <&gpt8_ick>, <&gpt5_ick>, <&uart4_fck>,
+ <&gpio6_dbck>, <&uart3_ick>, <&gpt7_ick>,
+ <&gpio2_ick>, <&gpt9_ick>, <&gpio6_ick>,
+ <&gpt3_ick>, <&gpio5_ick>, <&wdt3_fck>,
+ <&gpio4_ick>, <&wdt3_ick>, <&uart4_ick>;
+ };
+
+ emu_clkdm: emu_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&emu_src_ck>;
+ };
+
+ d2d_clkdm: d2d_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&mad2d_ick>, <&sad2d_ick>, <&modem_fck>;
+ };
+ };
+};
\ No newline at end of file
diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
new file mode 100644
index 0000000..f9ccaf1
--- /dev/null
+++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
@@ -0,0 +1,1392 @@
+/*
+ * Device Tree Source for OMAP3 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+dummy_apb_pclk: dummy_apb_pclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0x0>;
+};
+
+omap_32k_fck: omap_32k_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+};
+
+virt_12m_ck: virt_12m_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+};
+
+virt_13m_ck: virt_13m_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <13000000>;
+};
+
+virt_19200000_ck: virt_19200000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <19200000>;
+};
+
+virt_26000000_ck: virt_26000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <26000000>;
+};
+
+virt_38_4m_ck: virt_38_4m_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <38400000>;
+};
+
+virt_16_8m_ck: virt_16_8m_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <16800000>;
+};
+
+osc_sys_ck: osc_sys_ck@48306d40 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&virt_12m_ck>, <&virt_13m_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_38_4m_ck>, <&virt_16_8m_ck>;
+ reg = <0x48306d40 0x4>;
+};
+
+sys_ck: sys_ck@48307270 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&osc_sys_ck>;
+ ti,bit-shift = <6>;
+ ti,max-div = <3>;
+ reg = <0x48307270 0x4>;
+ ti,index-starts-at-one;
+};
+
+dpll4_ck: dpll4_ck@48004d00 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-dpll-per-clock";
+ clocks = <&sys_ck>, <&sys_ck>;
+ reg = <0x48004d00 0x4>, <0x48004d20 0x4>, <0x48004d30 0x4>, <0x48004d44 0x4>;
+};
+
+dpll4_m2_ck: dpll4_m2_ck@48004d48 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll4_ck>;
+ reg = <0x48004d48 0x4>;
+ ti,max-div = <63>;
+ ti,index-starts-at-one;
+};
+
+dpll4_m2x2_mul_ck: dpll4_m2x2_mul_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll4_m2_ck>;
+ clock-mult = <2>;
+ clock-div = <1>;
+};
+
+dpll4_m2x2_ck: dpll4_m2x2_ck@48004d00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll4_m2x2_mul_ck>;
+ ti,bit-shift = <0x1b>;
+ reg = <0x48004d00 0x4>;
+ ti,set-bit-to-disable;
+};
+
+omap_96m_alwon_fck: omap_96m_alwon_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll4_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dpll3_ck: dpll3_ck@48004d00 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-dpll-core-clock";
+ clocks = <&sys_ck>, <&sys_ck>;
+ reg = <0x48004d00 0x4>, <0x48004d20 0x4>, <0x48004d30 0x4>, <0x48004d40 0x4>;
+};
+
+dpll3_m3_ck: dpll3_m3_ck@48005140 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll3_ck>;
+ ti,bit-shift = <16>;
+ ti,max-div = <31>;
+ reg = <0x48005140 0x4>;
+ ti,index-starts-at-one;
+};
+
+dpll3_m3x2_mul_ck: dpll3_m3x2_mul_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll3_m3_ck>;
+ clock-mult = <2>;
+ clock-div = <1>;
+};
+
+dpll3_m3x2_ck: dpll3_m3x2_ck@48004d00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll3_m3x2_mul_ck>;
+ ti,bit-shift = <0xc>;
+ reg = <0x48004d00 0x4>;
+ ti,set-bit-to-disable;
+};
+
+emu_core_alwon_ck: emu_core_alwon_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll3_m3x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+sys_altclk: sys_altclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0x0>;
+};
+
+mcbsp_clks: mcbsp_clks {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0x0>;
+};
+
+sys_clkout1: sys_clkout1@48306d70 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&osc_sys_ck>;
+ reg = <0x48306d70 0x4>;
+ ti,bit-shift = <7>;
+};
+
+dpll3_m2_ck: dpll3_m2_ck@48004d40 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll3_ck>;
+ ti,bit-shift = <27>;
+ ti,max-div = <31>;
+ reg = <0x48004d40 0x4>;
+ ti,index-starts-at-one;
+};
+
+core_ck: core_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll3_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dpll1_fck: dpll1_fck@48004940 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&core_ck>;
+ ti,bit-shift = <19>;
+ ti,max-div = <7>;
+ reg = <0x48004940 0x4>;
+ ti,index-starts-at-one;
+};
+
+dpll1_ck: dpll1_ck@48004904 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-dpll-clock";
+ clocks = <&sys_ck>, <&dpll1_fck>;
+ reg = <0x48004904 0x4>, <0x48004924 0x4>, <0x48004934 0x4>, <0x48004940 0x4>;
+ ti,low-power-bypass;
+ ti,lock;
+};
+
+dpll1_x2_ck: dpll1_x2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll1_ck>;
+ clock-mult = <2>;
+ clock-div = <1>;
+};
+
+dpll1_x2m2_ck: dpll1_x2m2_ck@48004944 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll1_x2_ck>;
+ reg = <0x48004944 0x4>;
+ ti,max-div = <31>;
+ ti,index-starts-at-one;
+};
+
+dpll3_x2_ck: dpll3_x2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll3_ck>;
+ clock-mult = <2>;
+ clock-div = <1>;
+};
+
+dpll3_m2x2_ck: dpll3_m2x2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll3_m2_ck>;
+ clock-mult = <2>;
+ clock-div = <1>;
+};
+
+dpll4_x2_ck: dpll4_x2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll4_ck>;
+ clock-mult = <2>;
+ clock-div = <1>;
+};
+
+cm_96m_fck: cm_96m_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_96m_alwon_fck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+omap_96m_fck: omap_96m_fck@48004d40 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&cm_96m_fck>, <&sys_ck>;
+ ti,bit-shift = <6>;
+ reg = <0x48004d40 0x4>;
+};
+
+dpll4_m3_ck: dpll4_m3_ck@48004e40 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll4_ck>;
+ ti,bit-shift = <8>;
+ ti,max-div = <63>;
+ reg = <0x48004e40 0x4>;
+ ti,index-starts-at-one;
+};
+
+dpll4_m3x2_mul_ck: dpll4_m3x2_mul_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll4_m3_ck>;
+ clock-mult = <2>;
+ clock-div = <1>;
+};
+
+dpll4_m3x2_ck: dpll4_m3x2_ck@48004d00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll4_m3x2_mul_ck>;
+ ti,bit-shift = <0x1c>;
+ reg = <0x48004d00 0x4>;
+ ti,set-bit-to-disable;
+};
+
+omap_54m_fck: omap_54m_fck@48004d40 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dpll4_m3x2_ck>, <&sys_altclk>;
+ ti,bit-shift = <5>;
+ reg = <0x48004d40 0x4>;
+};
+
+cm_96m_d2_fck: cm_96m_d2_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&cm_96m_fck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+omap_48m_fck: omap_48m_fck@48004d40 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&cm_96m_d2_fck>, <&sys_altclk>;
+ ti,bit-shift = <3>;
+ reg = <0x48004d40 0x4>;
+ ti,table = <&cm_96m_d2_fck 0>, <&sys_altclk 1>;
+};
+
+omap_12m_fck: omap_12m_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_48m_fck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+};
+
+dpll4_m4_ck: dpll4_m4_ck@48004e40 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll4_ck>;
+ reg = <0x48004e40 0x4>;
+ ti,max-div = <63>;
+ ti,index-starts-at-one;
+};
+
+dpll4_m4x2_mul_ck: dpll4_m4x2_mul_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll4_m4_ck>;
+ clock-mult = <2>;
+ clock-div = <1>;
+};
+
+dpll4_m4x2_ck: dpll4_m4x2_ck@48004d00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll4_m4x2_mul_ck>;
+ ti,bit-shift = <0x1d>;
+ reg = <0x48004d00 0x4>;
+ ti,set-bit-to-disable;
+};
+
+dpll4_m5_ck: dpll4_m5_ck@48004f40 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll4_ck>;
+ reg = <0x48004f40 0x4>;
+ ti,max-div = <63>;
+ ti,index-starts-at-one;
+};
+
+dpll4_m5x2_mul_ck: dpll4_m5x2_mul_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll4_m5_ck>;
+ clock-mult = <2>;
+ clock-div = <1>;
+};
+
+dpll4_m5x2_ck: dpll4_m5x2_ck@48004d00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll4_m5x2_mul_ck>;
+ ti,bit-shift = <0x1e>;
+ reg = <0x48004d00 0x4>;
+ ti,set-bit-to-disable;
+};
+
+dpll4_m6_ck: dpll4_m6_ck@48005140 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll4_ck>;
+ ti,bit-shift = <24>;
+ ti,max-div = <63>;
+ reg = <0x48005140 0x4>;
+ ti,index-starts-at-one;
+};
+
+dpll4_m6x2_mul_ck: dpll4_m6x2_mul_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll4_m6_ck>;
+ clock-mult = <2>;
+ clock-div = <1>;
+};
+
+dpll4_m6x2_ck: dpll4_m6x2_ck@48004d00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll4_m6x2_mul_ck>;
+ ti,bit-shift = <0x1f>;
+ reg = <0x48004d00 0x4>;
+ ti,set-bit-to-disable;
+};
+
+emu_per_alwon_ck: emu_per_alwon_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll4_m6x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+clkout2_src_ck: clkout2_src_ck@48004d70 {
+ #clock-cells = <0>;
+ compatible = "ti,no-wait-mux-gate-clock";
+ clocks = <&core_ck>, <&sys_ck>, <&cm_96m_fck>, <&omap_54m_fck>;
+ ti,gate-bit-shift = <7>;
+ reg = <0x48004d70 0x4>, <0x48004d70 0x4>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+sys_clkout2: sys_clkout2@48004d70 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&clkout2_src_ck>;
+ ti,bit-shift = <3>;
+ ti,max-div = <64>;
+ reg = <0x48004d70 0x4>;
+ ti,index-power-of-two;
+};
+
+corex2_fck: corex2_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll3_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+mpu_ck: mpu_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll1_x2m2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+arm_fck: arm_fck@48004924 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&mpu_ck>;
+ reg = <0x48004924 0x4>;
+ ti,max-div = <2>;
+};
+
+emu_mpu_alwon_ck: emu_mpu_alwon_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&mpu_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+l3_ick: l3_ick@48004a40 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&core_ck>;
+ reg = <0x48004a40 0x4>;
+ ti,max-div = <3>;
+ ti,index-starts-at-one;
+};
+
+l4_ick: l4_ick@48004a40 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&l3_ick>;
+ ti,bit-shift = <2>;
+ ti,max-div = <3>;
+ reg = <0x48004a40 0x4>;
+ ti,index-starts-at-one;
+};
+
+rm_ick: rm_ick@48004c40 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&l4_ick>;
+ ti,bit-shift = <1>;
+ ti,max-div = <3>;
+ reg = <0x48004c40 0x4>;
+ ti,index-starts-at-one;
+};
+
+gpt10_fck: gpt10_fck@48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-gate-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ ti,gate-bit-shift = <11>;
+ reg = <0x48004a00 0x4>, <0x48004a40 0x4>;
+ ti,mux-bit-shift = <6>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+gpt11_fck: gpt11_fck@48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-gate-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ ti,gate-bit-shift = <12>;
+ reg = <0x48004a00 0x4>, <0x48004a40 0x4>;
+ ti,mux-bit-shift = <7>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+core_96m_fck: core_96m_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_96m_fck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+mmchs2_fck: mmchs2_fck@48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_96m_fck>;
+ reg = <0x48004a00 0x4>;
+ ti,bit-shift = <25>;
+};
+
+mmchs1_fck: mmchs1_fck@48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_96m_fck>;
+ reg = <0x48004a00 0x4>;
+ ti,bit-shift = <24>;
+};
+
+i2c3_fck: i2c3_fck@48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_96m_fck>;
+ reg = <0x48004a00 0x4>;
+ ti,bit-shift = <17>;
+};
+
+i2c2_fck: i2c2_fck@48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_96m_fck>;
+ reg = <0x48004a00 0x4>;
+ ti,bit-shift = <16>;
+};
+
+i2c1_fck: i2c1_fck@48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_96m_fck>;
+ reg = <0x48004a00 0x4>;
+ ti,bit-shift = <15>;
+};
+
+mcbsp5_fck: mcbsp5_fck@48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-gate-clock";
+ clocks = <&core_96m_fck>, <&mcbsp_clks>;
+ ti,gate-bit-shift = <10>;
+ reg = <0x48004a00 0x4>, <0x480022d8 0x4>;
+ ti,mux-bit-shift = <4>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+mcbsp1_fck: mcbsp1_fck@48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-gate-clock";
+ clocks = <&core_96m_fck>, <&mcbsp_clks>;
+ ti,gate-bit-shift = <9>;
+ reg = <0x48004a00 0x4>, <0x48002274 0x4>;
+ ti,mux-bit-shift = <2>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+core_48m_fck: core_48m_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_48m_fck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+mcspi4_fck: mcspi4_fck@48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_48m_fck>;
+ reg = <0x48004a00 0x4>;
+ ti,bit-shift = <21>;
+};
+
+mcspi3_fck: mcspi3_fck@48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_48m_fck>;
+ reg = <0x48004a00 0x4>;
+ ti,bit-shift = <20>;
+};
+
+mcspi2_fck: mcspi2_fck@48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_48m_fck>;
+ reg = <0x48004a00 0x4>;
+ ti,bit-shift = <19>;
+};
+
+mcspi1_fck: mcspi1_fck@48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_48m_fck>;
+ reg = <0x48004a00 0x4>;
+ ti,bit-shift = <18>;
+};
+
+uart2_fck: uart2_fck@48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_48m_fck>;
+ reg = <0x48004a00 0x4>;
+ ti,bit-shift = <14>;
+};
+
+uart1_fck: uart1_fck@48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_48m_fck>;
+ reg = <0x48004a00 0x4>;
+ ti,bit-shift = <13>;
+};
+
+core_12m_fck: core_12m_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_12m_fck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+hdq_fck: hdq_fck@48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_12m_fck>;
+ reg = <0x48004a00 0x4>;
+ ti,bit-shift = <22>;
+};
+
+core_l3_ick: core_l3_ick {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l3_ick>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+sdrc_ick: sdrc_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_l3_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <1>;
+};
+
+gpmc_fck: gpmc_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&core_l3_ick>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+core_l4_ick: core_l4_ick {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l4_ick>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+mmchs2_ick: mmchs2_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <25>;
+};
+
+mmchs1_ick: mmchs1_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <24>;
+};
+
+hdq_ick: hdq_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <22>;
+};
+
+mcspi4_ick: mcspi4_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <21>;
+};
+
+mcspi3_ick: mcspi3_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <20>;
+};
+
+mcspi2_ick: mcspi2_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <19>;
+};
+
+mcspi1_ick: mcspi1_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <18>;
+};
+
+i2c3_ick: i2c3_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <17>;
+};
+
+i2c2_ick: i2c2_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <16>;
+};
+
+i2c1_ick: i2c1_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <15>;
+};
+
+uart2_ick: uart2_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <14>;
+};
+
+uart1_ick: uart1_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <13>;
+};
+
+gpt11_ick: gpt11_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <12>;
+};
+
+gpt10_ick: gpt10_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <11>;
+};
+
+mcbsp5_ick: mcbsp5_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <10>;
+};
+
+mcbsp1_ick: mcbsp1_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <9>;
+};
+
+omapctrl_ick: omapctrl_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <6>;
+};
+
+dss_tv_fck: dss_tv_fck@48004e00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&omap_54m_fck>;
+ reg = <0x48004e00 0x4>;
+ ti,bit-shift = <2>;
+};
+
+dss_96m_fck: dss_96m_fck@48004e00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&omap_96m_fck>;
+ reg = <0x48004e00 0x4>;
+ ti,bit-shift = <2>;
+};
+
+dss2_alwon_fck: dss2_alwon_fck@48004e00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_ck>;
+ reg = <0x48004e00 0x4>;
+ ti,bit-shift = <1>;
+};
+
+dummy_ck: dummy_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+gpt1_fck: gpt1_fck@48004c00 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-gate-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ ti,gate-bit-shift = <0>;
+ reg = <0x48004c00 0x4>, <0x48004c40 0x4>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+aes2_ick: aes2_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ ti,bit-shift = <28>;
+ reg = <0x48004a10 0x4>;
+};
+
+wkup_32k_fck: wkup_32k_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_32k_fck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+gpio1_dbck: gpio1_dbck@48004c00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&wkup_32k_fck>;
+ reg = <0x48004c00 0x4>;
+ ti,bit-shift = <3>;
+};
+
+sha12_ick: sha12_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <27>;
+};
+
+wdt2_fck: wdt2_fck@48004c00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&wkup_32k_fck>;
+ reg = <0x48004c00 0x4>;
+ ti,bit-shift = <5>;
+};
+
+wkup_l4_ick: wkup_l4_ick {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+wdt2_ick: wdt2_ick@48004c10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&wkup_l4_ick>;
+ reg = <0x48004c10 0x4>;
+ ti,bit-shift = <5>;
+};
+
+wdt1_ick: wdt1_ick@48004c10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&wkup_l4_ick>;
+ reg = <0x48004c10 0x4>;
+ ti,bit-shift = <4>;
+};
+
+gpio1_ick: gpio1_ick@48004c10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&wkup_l4_ick>;
+ reg = <0x48004c10 0x4>;
+ ti,bit-shift = <3>;
+};
+
+omap_32ksync_ick: omap_32ksync_ick@48004c10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&wkup_l4_ick>;
+ reg = <0x48004c10 0x4>;
+ ti,bit-shift = <2>;
+};
+
+gpt12_ick: gpt12_ick@48004c10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&wkup_l4_ick>;
+ reg = <0x48004c10 0x4>;
+ ti,bit-shift = <1>;
+};
+
+gpt1_ick: gpt1_ick@48004c10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&wkup_l4_ick>;
+ reg = <0x48004c10 0x4>;
+ ti,bit-shift = <0>;
+};
+
+per_96m_fck: per_96m_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_96m_alwon_fck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+per_48m_fck: per_48m_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_48m_fck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+uart3_fck: uart3_fck@48005000 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&per_48m_fck>;
+ reg = <0x48005000 0x4>;
+ ti,bit-shift = <11>;
+};
+
+gpt2_fck: gpt2_fck@48005000 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-gate-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ ti,gate-bit-shift = <3>;
+ reg = <0x48005000 0x4>, <0x48005040 0x4>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+gpt3_fck: gpt3_fck@48005000 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-gate-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ ti,gate-bit-shift = <4>;
+ reg = <0x48005000 0x4>, <0x48005040 0x4>;
+ ti,mux-bit-shift = <1>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+gpt4_fck: gpt4_fck@48005000 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-gate-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ ti,gate-bit-shift = <5>;
+ reg = <0x48005000 0x4>, <0x48005040 0x4>;
+ ti,mux-bit-shift = <2>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+gpt5_fck: gpt5_fck@48005000 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-gate-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ ti,gate-bit-shift = <6>;
+ reg = <0x48005000 0x4>, <0x48005040 0x4>;
+ ti,mux-bit-shift = <3>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+gpt6_fck: gpt6_fck@48005000 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-gate-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ ti,gate-bit-shift = <7>;
+ reg = <0x48005000 0x4>, <0x48005040 0x4>;
+ ti,mux-bit-shift = <4>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+gpt7_fck: gpt7_fck@48005000 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-gate-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ ti,gate-bit-shift = <8>;
+ reg = <0x48005000 0x4>, <0x48005040 0x4>;
+ ti,mux-bit-shift = <5>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+gpt8_fck: gpt8_fck@48005000 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-gate-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ ti,gate-bit-shift = <9>;
+ reg = <0x48005000 0x4>, <0x48005040 0x4>;
+ ti,mux-bit-shift = <6>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+gpt9_fck: gpt9_fck@48005000 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-gate-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ ti,gate-bit-shift = <10>;
+ reg = <0x48005000 0x4>, <0x48005040 0x4>;
+ ti,mux-bit-shift = <7>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+per_32k_alwon_fck: per_32k_alwon_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_32k_fck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+gpio6_dbck: gpio6_dbck@48005000 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&per_32k_alwon_fck>;
+ reg = <0x48005000 0x4>;
+ ti,bit-shift = <17>;
+};
+
+gpio5_dbck: gpio5_dbck@48005000 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&per_32k_alwon_fck>;
+ reg = <0x48005000 0x4>;
+ ti,bit-shift = <16>;
+};
+
+gpio4_dbck: gpio4_dbck@48005000 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&per_32k_alwon_fck>;
+ reg = <0x48005000 0x4>;
+ ti,bit-shift = <15>;
+};
+
+gpio3_dbck: gpio3_dbck@48005000 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&per_32k_alwon_fck>;
+ reg = <0x48005000 0x4>;
+ ti,bit-shift = <14>;
+};
+
+gpio2_dbck: gpio2_dbck@48005000 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&per_32k_alwon_fck>;
+ reg = <0x48005000 0x4>;
+ ti,bit-shift = <13>;
+};
+
+wdt3_fck: wdt3_fck@48005000 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&per_32k_alwon_fck>;
+ reg = <0x48005000 0x4>;
+ ti,bit-shift = <12>;
+};
+
+per_l4_ick: per_l4_ick {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l4_ick>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+gpio6_ick: gpio6_ick@48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,bit-shift = <17>;
+};
+
+gpio5_ick: gpio5_ick@48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,bit-shift = <16>;
+};
+
+gpio4_ick: gpio4_ick@48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,bit-shift = <15>;
+};
+
+gpio3_ick: gpio3_ick@48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,bit-shift = <14>;
+};
+
+gpio2_ick: gpio2_ick@48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,bit-shift = <13>;
+};
+
+wdt3_ick: wdt3_ick@48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,bit-shift = <12>;
+};
+
+uart3_ick: uart3_ick@48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,bit-shift = <11>;
+};
+
+uart4_ick: uart4_ick@48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,bit-shift = <18>;
+};
+
+gpt9_ick: gpt9_ick@48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,bit-shift = <10>;
+};
+
+gpt8_ick: gpt8_ick@48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,bit-shift = <9>;
+};
+
+gpt7_ick: gpt7_ick@48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,bit-shift = <8>;
+};
+
+gpt6_ick: gpt6_ick@48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,bit-shift = <7>;
+};
+
+gpt5_ick: gpt5_ick@48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,bit-shift = <6>;
+};
+
+gpt4_ick: gpt4_ick@48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,bit-shift = <5>;
+};
+
+gpt3_ick: gpt3_ick@48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,bit-shift = <4>;
+};
+
+gpt2_ick: gpt2_ick@48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,bit-shift = <3>;
+};
+
+mcbsp2_ick: mcbsp2_ick@48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,bit-shift = <0>;
+};
+
+mcbsp3_ick: mcbsp3_ick@48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,bit-shift = <1>;
+};
+
+mcbsp4_ick: mcbsp4_ick@48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,bit-shift = <2>;
+};
+
+mcbsp2_fck: mcbsp2_fck@48005000 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-gate-clock";
+ clocks = <&per_96m_fck>, <&mcbsp_clks>;
+ ti,gate-bit-shift = <0>;
+ reg = <0x48005000 0x4>, <0x48002274 0x4>;
+ ti,mux-bit-shift = <6>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+mcbsp3_fck: mcbsp3_fck@48005000 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-gate-clock";
+ clocks = <&per_96m_fck>, <&mcbsp_clks>;
+ ti,gate-bit-shift = <1>;
+ reg = <0x48005000 0x4>, <0x480022d8 0x4>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+mcbsp4_fck: mcbsp4_fck@48005000 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-gate-clock";
+ clocks = <&per_96m_fck>, <&mcbsp_clks>;
+ ti,gate-bit-shift = <2>;
+ reg = <0x48005000 0x4>, <0x480022d8 0x4>;
+ ti,mux-bit-shift = <2>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+emu_src_mux_ck: emu_src_mux_ck@48005140 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
+ reg = <0x48005140 0x4>;
+};
+
+emu_src_ck: emu_src_ck {
+ #clock-cells = <0>;
+ compatible = "ti,clkdm-gate-clock";
+ clocks = <&emu_src_mux_ck>;
+};
+
+pclk_fck: pclk_fck@48005140 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&emu_src_ck>;
+ ti,bit-shift = <8>;
+ ti,max-div = <7>;
+ reg = <0x48005140 0x4>;
+ ti,index-starts-at-one;
+};
+
+pclkx2_fck: pclkx2_fck@48005140 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&emu_src_ck>;
+ ti,bit-shift = <6>;
+ ti,max-div = <3>;
+ reg = <0x48005140 0x4>;
+ ti,index-starts-at-one;
+};
+
+atclk_fck: atclk_fck@48005140 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&emu_src_ck>;
+ ti,bit-shift = <4>;
+ ti,max-div = <3>;
+ reg = <0x48005140 0x4>;
+ ti,index-starts-at-one;
+};
+
+traceclk_src_fck: traceclk_src_fck@48005140 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x48005140 0x4>;
+};
+
+traceclk_fck: traceclk_fck@48005140 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&traceclk_src_fck>;
+ ti,bit-shift = <11>;
+ ti,max-div = <7>;
+ reg = <0x48005140 0x4>;
+ ti,index-starts-at-one;
+};
+
+secure_32k_fck: secure_32k_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+};
+
+gpt12_fck: gpt12_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&secure_32k_fck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+wdt1_fck: wdt1_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&secure_32k_fck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
--
1.7.9.5
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^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 30/36] ARM: dts: omap3 clock data
@ 2013-09-25 8:48 ` Tero Kristo
0 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-arm-kernel
This patch creates a unique node for each clock in the OMAP3 power,
reset and clock manager (PRCM).
TODO: add still missing am35xx only clock nodes
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/boot/dts/am35xx-clocks.dtsi | 101 ++
arch/arm/boot/dts/omap3.dtsi | 7 +
arch/arm/boot/dts/omap3430es1-clocks.dtsi | 145 ++
arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi | 223 ++++
arch/arm/boot/dts/omap34xx.dtsi | 121 +-
.../omap36xx-am35xx-omap3430es2plus-clocks.dtsi | 186 +++
arch/arm/boot/dts/omap36xx-clocks.dtsi | 78 ++
.../boot/dts/omap36xx-omap3430es2plus-clocks.dtsi | 158 +++
arch/arm/boot/dts/omap36xx.dtsi | 122 +-
arch/arm/boot/dts/omap3xxx-clocks.dtsi | 1392 ++++++++++++++++++++
10 files changed, 2531 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/boot/dts/am35xx-clocks.dtsi
create mode 100644 arch/arm/boot/dts/omap3430es1-clocks.dtsi
create mode 100644 arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi
create mode 100644 arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
create mode 100644 arch/arm/boot/dts/omap36xx-clocks.dtsi
create mode 100644 arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
create mode 100644 arch/arm/boot/dts/omap3xxx-clocks.dtsi
diff --git a/arch/arm/boot/dts/am35xx-clocks.dtsi b/arch/arm/boot/dts/am35xx-clocks.dtsi
new file mode 100644
index 0000000..7f3af1a
--- /dev/null
+++ b/arch/arm/boot/dts/am35xx-clocks.dtsi
@@ -0,0 +1,101 @@
+/*
+ * Device Tree Source for AM35xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+ipss_ick: ipss_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,am35xx-interface-clock";
+ clocks = <&core_l3_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <4>;
+};
+
+rmii_ck: rmii_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+};
+
+pclk_ck: pclk_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <27000000>;
+};
+
+emac_ick: emac_ick at 4800259c {
+ #clock-cells = <0>;
+ compatible = "ti,am35xx-gate-clock";
+ clocks = <&ipss_ick>;
+ reg = <0x4800259c 0x4>;
+ ti,bit-shift = <1>;
+};
+
+emac_fck: emac_fck at 4800259c {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&rmii_ck>;
+ reg = <0x4800259c 0x4>;
+ ti,bit-shift = <9>;
+};
+
+vpfe_ick: vpfe_ick at 4800259c {
+ #clock-cells = <0>;
+ compatible = "ti,am35xx-gate-clock";
+ clocks = <&ipss_ick>;
+ reg = <0x4800259c 0x4>;
+ ti,bit-shift = <2>;
+};
+
+vpfe_fck: vpfe_fck at 4800259c {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&pclk_ck>;
+ reg = <0x4800259c 0x4>;
+ ti,bit-shift = <10>;
+};
+
+hsotgusb_ick_am35xx: hsotgusb_ick_am35xx at 4800259c {
+ #clock-cells = <0>;
+ compatible = "ti,am35xx-gate-clock";
+ clocks = <&ipss_ick>;
+ reg = <0x4800259c 0x4>;
+ ti,bit-shift = <0>;
+};
+
+hsotgusb_fck_am35xx: hsotgusb_fck_am35xx at 4800259c {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_ck>;
+ reg = <0x4800259c 0x4>;
+ ti,bit-shift = <8>;
+};
+
+hecc_ck: hecc_ck at 4800259c {
+ #clock-cells = <0>;
+ compatible = "ti,am35xx-gate-clock";
+ clocks = <&sys_ck>;
+ reg = <0x4800259c 0x4>;
+ ti,bit-shift = <3>;
+};
+
+uart4_ick_am35xx: uart4_ick_am35xx at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <23>;
+};
+
+uart4_fck_am35xx: uart4_fck_am35xx at 48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_48m_fck>;
+ reg = <0x48004a00 0x4>;
+ ti,bit-shift = <23>;
+};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 16420ae..bc11b83 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -533,4 +533,11 @@
ram-bits = <12>;
};
};
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ /include/ "omap3xxx-clocks.dtsi"
+ };
};
diff --git a/arch/arm/boot/dts/omap3430es1-clocks.dtsi b/arch/arm/boot/dts/omap3430es1-clocks.dtsi
new file mode 100644
index 0000000..2a7a137
--- /dev/null
+++ b/arch/arm/boot/dts/omap3430es1-clocks.dtsi
@@ -0,0 +1,145 @@
+/*
+ * Device Tree Source for OMAP3430 ES1 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+gfx_l3_ck: gfx_l3_ck at 48004b10 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&l3_ick>;
+ reg = <0x48004b10 0x4>;
+ ti,bit-shift = <0>;
+};
+
+gfx_l3_fck: gfx_l3_fck at 48004b40 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&l3_ick>;
+ reg = <0x48004b40 0x4>;
+ ti,max-div = <7>;
+ ti,index-starts-at-one;
+};
+
+gfx_l3_ick: gfx_l3_ick {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&gfx_l3_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+gfx_cg1_ck: gfx_cg1_ck at 48004b00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&gfx_l3_fck>;
+ reg = <0x48004b00 0x4>;
+ ti,bit-shift = <1>;
+};
+
+gfx_cg2_ck: gfx_cg2_ck at 48004b00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&gfx_l3_fck>;
+ reg = <0x48004b00 0x4>;
+ ti,bit-shift = <2>;
+};
+
+d2d_26m_fck: d2d_26m_fck at 48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&sys_ck>;
+ reg = <0x48004a00 0x4>;
+ ti,bit-shift = <3>;
+};
+
+fshostusb_fck: fshostusb_fck at 48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_48m_fck>;
+ reg = <0x48004a00 0x4>;
+ ti,bit-shift = <5>;
+};
+
+ssi_ssr_fck_3430es1: ssi_ssr_fck_3430es1 at 48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,no-wait-mux-gate-clock";
+ clocks = <&corex2_fck>;
+ ti,div-bit-shift = <8>;
+ ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
+ reg-names = "gate-reg", "div-reg";
+ reg = <0x48004a00 0x4>, <0x48004a40 0x4>;
+ ti,gate-bit-shift = <0>;
+};
+
+ssi_sst_fck_3430es1: ssi_sst_fck_3430es1 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&ssi_ssr_fck_3430es1>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+hsotgusb_ick_3430es1: hsotgusb_ick_3430es1 at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-no-wait-interface-clock";
+ clocks = <&core_l3_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <4>;
+};
+
+fac_ick: fac_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <8>;
+};
+
+ssi_l4_ick: ssi_l4_ick {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l4_ick>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+ssi_ick_3430es1: ssi_ick_3430es1 at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-no-wait-interface-clock";
+ clocks = <&ssi_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <0>;
+};
+
+usb_l4_ick: usb_l4_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-mux-gate-clock";
+ clocks = <&l4_ick>;
+ ti,div-bit-shift = <4>;
+ ti,max-div = <1>;
+ reg-names = "gate-reg", "div-reg";
+ reg = <0x48004a10 0x4>, <0x48004a40 0x4>;
+ ti,gate-bit-shift = <5>;
+ ti,div-index-starts-at-one;
+};
+
+dss1_alwon_fck_3430es1: dss1_alwon_fck_3430es1 at 48004e00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll4_m4x2_ck>;
+ reg = <0x48004e00 0x4>;
+ ti,bit-shift = <0>;
+};
+
+dss_ick_3430es1: dss_ick_3430es1 at 48004e10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-no-wait-interface-clock";
+ clocks = <&l4_ick>;
+ reg = <0x48004e10 0x4>;
+ ti,bit-shift = <0>;
+};
diff --git a/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi
new file mode 100644
index 0000000..48b6a5c
--- /dev/null
+++ b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi
@@ -0,0 +1,223 @@
+/*
+ * Device Tree Source for OMAP34xx/OMAP36xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+security_l4_ick2: security_l4_ick2 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l4_ick>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+aes1_ick: aes1_ick at 48004a14 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&security_l4_ick2>;
+ ti,bit-shift = <3>;
+ reg = <0x48004a14 0x4>;
+};
+
+rng_ick: rng_ick at 48004a14 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&security_l4_ick2>;
+ reg = <0x48004a14 0x4>;
+ ti,bit-shift = <2>;
+};
+
+sha11_ick: sha11_ick at 48004a14 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&security_l4_ick2>;
+ reg = <0x48004a14 0x4>;
+ ti,bit-shift = <1>;
+};
+
+des1_ick: des1_ick at 48004a14 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&security_l4_ick2>;
+ reg = <0x48004a14 0x4>;
+ ti,bit-shift = <0>;
+};
+
+cam_mclk: cam_mclk at 48004f00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll4_m5x2_ck>;
+ ti,bit-shift = <0>;
+ reg = <0x48004f00 0x4>;
+ ti,set-rate-parent;
+};
+
+cam_ick: cam_ick at 48004f10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-no-wait-interface-clock";
+ clocks = <&l4_ick>;
+ reg = <0x48004f10 0x4>;
+ ti,bit-shift = <0>;
+};
+
+csi2_96m_fck: csi2_96m_fck at 48004f00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&core_96m_fck>;
+ reg = <0x48004f00 0x4>;
+ ti,bit-shift = <1>;
+};
+
+security_l3_ick: security_l3_ick {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l3_ick>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+pka_ick: pka_ick at 48004a14 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&security_l3_ick>;
+ reg = <0x48004a14 0x4>;
+ ti,bit-shift = <4>;
+};
+
+icr_ick: icr_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <29>;
+};
+
+des2_ick: des2_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <26>;
+};
+
+mspro_ick: mspro_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <23>;
+};
+
+mailboxes_ick: mailboxes_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <7>;
+};
+
+ssi_l4_ick: ssi_l4_ick {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l4_ick>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+sr1_fck: sr1_fck at 48004c00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&sys_ck>;
+ reg = <0x48004c00 0x4>;
+ ti,bit-shift = <6>;
+};
+
+sr2_fck: sr2_fck at 48004c00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&sys_ck>;
+ reg = <0x48004c00 0x4>;
+ ti,bit-shift = <7>;
+};
+
+sr_l4_ick: sr_l4_ick {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l4_ick>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dpll2_fck: dpll2_fck at 48004040 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&core_ck>;
+ ti,bit-shift = <19>;
+ ti,max-div = <7>;
+ reg = <0x48004040 0x4>;
+ ti,index-starts-at-one;
+};
+
+dpll2_ck: dpll2_ck at 48004004 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-dpll-clock";
+ clocks = <&sys_ck>, <&dpll2_fck>;
+ reg = <0x48004004 0x4>, <0x48004024 0x4>, <0x48004034 0x4>, <0x48004040 0x4>;
+ ti,low-power-stop;
+ ti,lock;
+ ti,low-power-bypass;
+};
+
+dpll2_m2_ck: dpll2_m2_ck at 48004044 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll2_ck>;
+ reg = <0x48004044 0x4>;
+ ti,max-div = <31>;
+ ti,index-starts-at-one;
+};
+
+iva2_ck: iva2_ck at 48004000 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&dpll2_m2_ck>;
+ reg = <0x48004000 0x4>;
+ ti,bit-shift = <0>;
+};
+
+modem_fck: modem_fck at 48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&sys_ck>;
+ reg = <0x48004a00 0x4>;
+ ti,bit-shift = <31>;
+};
+
+sad2d_ick: sad2d_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&l3_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <3>;
+};
+
+mad2d_ick: mad2d_ick at 48004a18 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&l3_ick>;
+ reg = <0x48004a18 0x4>;
+ ti,bit-shift = <3>;
+};
+
+mspro_fck: mspro_fck at 48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_96m_fck>;
+ reg = <0x48004a00 0x4>;
+ ti,bit-shift = <23>;
+};
diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi
index 5355d61..2ed7c69 100644
--- a/arch/arm/boot/dts/omap34xx.dtsi
+++ b/arch/arm/boot/dts/omap34xx.dtsi
@@ -25,4 +25,123 @@
clock-latency = <300000>; /* From legacy driver */
};
};
-};
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ /include/ "omap34xx-omap36xx-clocks.dtsi"
+ /include/ "omap36xx-omap3430es2plus-clocks.dtsi"
+ /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
+ };
+
+ clockdomains {
+ usbhost_clkdm: usbhost_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&usbhost_48m_fck>, <&usbhost_ick>,
+ <&usbhost_120m_fck>;
+ };
+
+ wkup_clkdm: wkup_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&wdt1_ick>, <&sr2_fck>, <&omap_32ksync_ick>,
+ <&wdt2_fck>, <&gpt12_ick>, <&sr1_fck>,
+ <&gpio1_ick>, <&gpt1_ick>, <&wdt2_ick>,
+ <&usim_ick>, <&gpio1_dbck>;
+ };
+
+ cam_clkdm: cam_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&csi2_96m_fck>, <&cam_ick>;
+ };
+
+ dpll4_clkdm: dpll4_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll4_ck>;
+ };
+
+ sgx_clkdm: sgx_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&sgx_ick>;
+ };
+
+ dpll3_clkdm: dpll3_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll3_ck>;
+ };
+
+ iva2_clkdm: iva2_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&iva2_ck>;
+ };
+
+ dpll1_clkdm: dpll1_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll1_ck>;
+ };
+
+ dpll2_clkdm: dpll2_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll2_ck>;
+ };
+
+ dpll5_clkdm: dpll5_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll5_ck>;
+ };
+
+ dss_clkdm: dss_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dss_tv_fck>, <&dss1_alwon_fck_3430es2>,
+ <&dss_96m_fck>, <&dss2_alwon_fck>,
+ <&dss_ick_3430es2>;
+ };
+
+ core_l4_clkdm: core_l4_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&mmchs1_ick>, <&mspro_ick>, <&mmchs2_ick>,
+ <&mcspi4_fck>, <&i2c3_fck>, <&mcspi2_ick>,
+ <&uart2_ick>, <&mcspi3_ick>, <&i2c1_fck>,
+ <&sha12_ick>, <&mcspi3_fck>, <&mailboxes_ick>,
+ <&uart2_fck>, <&mmchs2_fck>, <&usbtll_fck>,
+ <&mmchs3_ick>, <&des2_ick>, <&i2c2_ick>,
+ <&i2c1_ick>, <&icr_ick>, <&hdq_fck>,
+ <&uart1_ick>, <&ts_fck>, <&usbtll_ick>,
+ <&hdq_ick>, <&mcbsp5_ick>, <&aes2_ick>,
+ <&mcspi1_ick>, <&mmchs1_fck>, <&i2c3_ick>,
+ <&mcspi1_fck>, <&mmchs3_fck>, <&mcspi4_ick>,
+ <&omapctrl_ick>, <&mspro_fck>, <&mcbsp1_ick>,
+ <&mcspi2_fck>, <&ssi_ick_3430es2>,
+ <&gpt10_ick>, <&cpefuse_fck>, <&i2c2_fck>,
+ <&gpt11_ick>, <&uart1_fck>;
+ };
+
+ core_l3_clkdm: core_l3_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es2>;
+ };
+
+ per_clkdm: per_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&gpt2_ick>, <&uart3_fck>, <&gpio3_ick>,
+ <&mcbsp2_ick>, <&gpt6_ick>, <&gpio2_dbck>,
+ <&mcbsp4_ick>, <&gpio4_dbck>, <&gpt4_ick>,
+ <&gpio5_dbck>, <&mcbsp3_ick>, <&gpio3_dbck>,
+ <&gpt8_ick>, <&gpt5_ick>, <&gpio6_dbck>,
+ <&uart3_ick>, <&gpt7_ick>, <&gpio2_ick>,
+ <&gpio6_ick>, <&gpt9_ick>, <&gpt3_ick>,
+ <&gpio5_ick>, <&wdt3_fck>, <&gpio4_ick>,
+ <&wdt3_ick>, <&uart4_ick>;
+ };
+
+ emu_clkdm: emu_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&emu_src_ck>;
+ };
+
+ d2d_clkdm: d2d_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&mad2d_ick>, <&sad2d_ick>, <&modem_fck>;
+ };
+ };
+};
\ No newline at end of file
diff --git a/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
new file mode 100644
index 0000000..a31bc85
--- /dev/null
+++ b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
@@ -0,0 +1,186 @@
+/*
+ * Device Tree Source for OMAP36xx/AM35xx/OMAP34xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+dpll5_ck: dpll5_ck at 48004d04 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-dpll-clock";
+ clocks = <&sys_ck>, <&sys_ck>;
+ reg = <0x48004d04 0x4>, <0x48004d24 0x4>, <0x48004d34 0x4>, <0x48004d4c 0x4>;
+};
+
+dpll5_m2_ck: dpll5_m2_ck at 48004d50 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll5_ck>;
+ reg = <0x48004d50 0x4>;
+ ti,max-div = <31>;
+ ti,index-starts-at-one;
+};
+
+core_d3_ck: core_d3_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&core_ck>;
+ clock-mult = <1>;
+ clock-div = <3>;
+};
+
+core_d4_ck: core_d4_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&core_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+};
+
+core_d6_ck: core_d6_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&core_ck>;
+ clock-mult = <1>;
+ clock-div = <6>;
+};
+
+omap_192m_alwon_fck: omap_192m_alwon_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll4_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+core_d2_ck: core_d2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&core_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+corex2_d3_fck: corex2_d3_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&corex2_fck>;
+ clock-mult = <1>;
+ clock-div = <3>;
+};
+
+corex2_d5_fck: corex2_d5_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&corex2_fck>;
+ clock-mult = <1>;
+ clock-div = <5>;
+};
+
+sgx_fck: sgx_fck at 48004b00 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-gate-clock";
+ clocks = <&core_d3_ck>, <&core_d4_ck>, <&core_d6_ck>, <&cm_96m_fck>, <&omap_192m_alwon_fck>, <&core_d2_ck>, <&corex2_d3_fck>, <&corex2_d5_fck>;
+ ti,gate-bit-shift = <1>;
+ reg = <0x48004b00 0x4>, <0x48004b40 0x4>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+sgx_ick: sgx_ick at 48004b10 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&l3_ick>;
+ reg = <0x48004b10 0x4>;
+ ti,bit-shift = <0>;
+};
+
+cpefuse_fck: cpefuse_fck at 48004a08 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_ck>;
+ reg = <0x48004a08 0x4>;
+ ti,bit-shift = <0>;
+};
+
+ts_fck: ts_fck at 48004a08 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&omap_32k_fck>;
+ reg = <0x48004a08 0x4>;
+ ti,bit-shift = <1>;
+};
+
+usbtll_fck: usbtll_fck at 48004a08 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&dpll5_m2_ck>;
+ reg = <0x48004a08 0x4>;
+ ti,bit-shift = <2>;
+};
+
+usbtll_ick: usbtll_ick at 48004a18 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a18 0x4>;
+ ti,bit-shift = <2>;
+};
+
+mmchs3_ick: mmchs3_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <30>;
+};
+
+mmchs3_fck: mmchs3_fck at 48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_96m_fck>;
+ reg = <0x48004a00 0x4>;
+ ti,bit-shift = <30>;
+};
+
+dss1_alwon_fck_3430es2: dss1_alwon_fck_3430es2 at 48004e00 {
+ #clock-cells = <0>;
+ compatible = "ti,dss-gate-clock";
+ clocks = <&dpll4_m4x2_ck>;
+ reg = <0x48004e00 0x4>;
+ ti,bit-shift = <0>;
+};
+
+dss_ick_3430es2: dss_ick_3430es2 at 48004e10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-dss-interface-clock";
+ clocks = <&l4_ick>;
+ reg = <0x48004e10 0x4>;
+ ti,bit-shift = <0>;
+};
+
+usbhost_120m_fck: usbhost_120m_fck at 48005400 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll5_m2_ck>;
+ reg = <0x48005400 0x4>;
+ ti,bit-shift = <1>;
+};
+
+usbhost_48m_fck: usbhost_48m_fck at 48005400 {
+ #clock-cells = <0>;
+ compatible = "ti,dss-gate-clock";
+ clocks = <&omap_48m_fck>;
+ reg = <0x48005400 0x4>;
+ ti,bit-shift = <0>;
+};
+
+usbhost_ick: usbhost_ick at 48005410 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-dss-interface-clock";
+ clocks = <&l4_ick>;
+ reg = <0x48005410 0x4>;
+ ti,bit-shift = <0>;
+};
diff --git a/arch/arm/boot/dts/omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap36xx-clocks.dtsi
new file mode 100644
index 0000000..0a3a697
--- /dev/null
+++ b/arch/arm/boot/dts/omap36xx-clocks.dtsi
@@ -0,0 +1,78 @@
+/*
+ * Device Tree Source for OMAP36xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+dpll4_ck: dpll4_ck at 48004d00 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-dpll-per-j-type-clock";
+ clocks = <&sys_ck>, <&sys_ck>;
+ reg = <0x48004d00 0x4>, <0x48004d20 0x4>, <0x48004d30 0x4>, <0x48004d44 0x4>;
+};
+
+dpll4_m2x2_ck: dpll4_m2x2_ck at 48004d00 {
+ #clock-cells = <0>;
+ compatible = "ti,hsdiv-gate-clock";
+ clocks = <&dpll4_m2x2_mul_ck>;
+ ti,bit-shift = <0x1b>;
+ reg = <0x48004d00 0x4>;
+ ti,set-bit-to-disable;
+};
+
+dpll3_m3x2_ck: dpll3_m3x2_ck at 48004d00 {
+ #clock-cells = <0>;
+ compatible = "ti,hsdiv-gate-clock";
+ clocks = <&dpll3_m3x2_mul_ck>;
+ ti,bit-shift = <0xc>;
+ reg = <0x48004d00 0x4>;
+ ti,set-bit-to-disable;
+};
+
+dpll4_m3x2_ck: dpll4_m3x2_ck at 48004d00 {
+ #clock-cells = <0>;
+ compatible = "ti,hsdiv-gate-clock";
+ clocks = <&dpll4_m3x2_mul_ck>;
+ ti,bit-shift = <0x1c>;
+ reg = <0x48004d00 0x4>;
+ ti,set-bit-to-disable;
+};
+
+dpll4_m5x2_ck: dpll4_m5x2_ck at 48004d00 {
+ #clock-cells = <0>;
+ compatible = "ti,hsdiv-gate-clock";
+ clocks = <&dpll4_m5x2_mul_ck>;
+ ti,bit-shift = <0x1e>;
+ reg = <0x48004d00 0x4>;
+ ti,set-bit-to-disable;
+ ti,set-rate-parent;
+};
+
+dpll4_m6x2_ck: dpll4_m6x2_ck at 48004d00 {
+ #clock-cells = <0>;
+ compatible = "ti,hsdiv-gate-clock";
+ clocks = <&dpll4_m6x2_mul_ck>;
+ ti,bit-shift = <0x1f>;
+ reg = <0x48004d00 0x4>;
+ ti,set-bit-to-disable;
+};
+
+omap_192m_alwon_fck: omap_192m_alwon_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll4_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+uart4_fck: uart4_fck at 48005000 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&per_48m_fck>;
+ reg = <0x48005000 0x4>;
+ ti,bit-shift = <18>;
+};
diff --git a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
new file mode 100644
index 0000000..a89206c
--- /dev/null
+++ b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
@@ -0,0 +1,158 @@
+/*
+ * Device Tree Source for OMAP34xx/OMAP36xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+ssi_ssr_fck_3430es2: ssi_ssr_fck_3430es2 at 48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,no-wait-mux-gate-clock";
+ clocks = <&corex2_fck>;
+ ti,div-bit-shift = <8>;
+ ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
+ reg-names = "gate-reg", "div-reg";
+ reg = <0x48004a00 0x4>, <0x48004a40 0x4>;
+ ti,gate-bit-shift = <0>;
+};
+
+ssi_sst_fck_3430es2: ssi_sst_fck_3430es2 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&ssi_ssr_fck_3430es2>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+hsotgusb_ick_3430es2: hsotgusb_ick_3430es2 at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-hsotgusb-interface-clock";
+ clocks = <&core_l3_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <4>;
+};
+
+ssi_l4_ick: ssi_l4_ick {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l4_ick>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+ssi_ick_3430es2: ssi_ick_3430es2 at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-ssi-interface-clock";
+ clocks = <&ssi_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <0>;
+};
+
+dpll5_ck: dpll5_ck at 48004d04 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-dpll-clock";
+ clocks = <&sys_ck>, <&sys_ck>;
+ reg = <0x48004d04 0x4>, <0x48004d24 0x4>, <0x48004d34 0x4>, <0x48004d4c 0x4>;
+};
+
+dpll5_m2_ck: dpll5_m2_ck at 48004d50 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll5_ck>;
+ reg = <0x48004d50 0x4>;
+ ti,max-div = <31>;
+ ti,index-starts-at-one;
+};
+
+dpll5_m2_d20_ck: dpll5_m2_d20_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll5_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <20>;
+};
+
+sys_d2_ck: sys_d2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+omap_96m_d2_fck: omap_96m_d2_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_96m_fck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+omap_96m_d4_fck: omap_96m_d4_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_96m_fck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+};
+
+omap_96m_d8_fck: omap_96m_d8_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_96m_fck>;
+ clock-mult = <1>;
+ clock-div = <8>;
+};
+
+omap_96m_d10_fck: omap_96m_d10_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_96m_fck>;
+ clock-mult = <1>;
+ clock-div = <10>;
+};
+
+dpll5_m2_d4_ck: dpll5_m2_d4_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll5_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+};
+
+dpll5_m2_d8_ck: dpll5_m2_d8_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll5_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <8>;
+};
+
+dpll5_m2_d16_ck: dpll5_m2_d16_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll5_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <16>;
+};
+
+usim_fck: usim_fck at 48004c00 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-gate-clock";
+ clocks = <&sys_ck>, <&dpll5_m2_d20_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>;
+ ti,gate-bit-shift = <9>;
+ reg = <0x48004c00 0x4>, <0x48004c40 0x4>;
+ ti,mux-bit-shift = <3>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+usim_ick: usim_ick at 48004c10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&wkup_l4_ick>;
+ reg = <0x48004c10 0x4>;
+ ti,bit-shift = <9>;
+};
diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi
index f8b3765..71fb6fb 100644
--- a/arch/arm/boot/dts/omap36xx.dtsi
+++ b/arch/arm/boot/dts/omap36xx.dtsi
@@ -35,4 +35,124 @@
clock-frequency = <48000000>;
};
};
-};
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ /include/ "omap36xx-clocks.dtsi"
+ /include/ "omap34xx-omap36xx-clocks.dtsi"
+ /include/ "omap36xx-omap3430es2plus-clocks.dtsi"
+ /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
+ };
+
+ clockdomains {
+ usbhost_clkdm: usbhost_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&usbhost_48m_fck>, <&usbhost_ick>,
+ <&usbhost_120m_fck>;
+ };
+
+ wkup_clkdm: wkup_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&wdt1_ick>, <&sr2_fck>, <&omap_32ksync_ick>,
+ <&wdt2_fck>, <&gpt12_ick>, <&sr1_fck>,
+ <&gpio1_ick>, <&gpt1_ick>, <&wdt2_ick>,
+ <&usim_ick>, <&gpio1_dbck>;
+ };
+
+ cam_clkdm: cam_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&csi2_96m_fck>, <&cam_ick>;
+ };
+
+ dpll4_clkdm: dpll4_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll4_ck>;
+ };
+
+ sgx_clkdm: sgx_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&sgx_ick>;
+ };
+
+ dpll3_clkdm: dpll3_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll3_ck>;
+ };
+
+ iva2_clkdm: iva2_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&iva2_ck>;
+ };
+
+ dpll1_clkdm: dpll1_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll1_ck>;
+ };
+
+ dpll5_clkdm: dpll5_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll5_ck>;
+ };
+
+ dpll2_clkdm: dpll2_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll2_ck>;
+ };
+
+ dss_clkdm: dss_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dss_tv_fck>, <&dss1_alwon_fck_3430es2>,
+ <&dss_96m_fck>, <&dss2_alwon_fck>,
+ <&dss_ick_3430es2>;
+ };
+
+ core_l4_clkdm: core_l4_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&mmchs1_ick>, <&mspro_ick>, <&mmchs2_ick>,
+ <&mcspi4_fck>, <&i2c3_fck>, <&mcspi2_ick>,
+ <&uart2_ick>, <&mcspi3_ick>, <&i2c1_fck>,
+ <&sha12_ick>, <&mcspi3_fck>, <&mailboxes_ick>,
+ <&uart2_fck>, <&mmchs2_fck>, <&usbtll_fck>,
+ <&mmchs3_ick>, <&des2_ick>, <&i2c2_ick>,
+ <&i2c1_ick>, <&icr_ick>, <&hdq_fck>,
+ <&uart1_ick>, <&ts_fck>, <&usbtll_ick>,
+ <&hdq_ick>, <&mcbsp5_ick>, <&aes2_ick>,
+ <&mcspi1_ick>, <&mmchs1_fck>, <&i2c3_ick>,
+ <&mcspi1_fck>, <&mmchs3_fck>, <&mcspi4_ick>,
+ <&omapctrl_ick>, <&mspro_fck>, <&mcbsp1_ick>,
+ <&mcspi2_fck>, <&ssi_ick_3430es2>,
+ <&gpt10_ick>, <&cpefuse_fck>, <&i2c2_fck>,
+ <&gpt11_ick>, <&uart1_fck>;
+ };
+
+ core_l3_clkdm: core_l3_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es2>;
+ };
+
+ per_clkdm: per_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&gpt2_ick>, <&uart3_fck>, <&gpio3_ick>,
+ <&mcbsp2_ick>, <&gpt6_ick>, <&gpio2_dbck>,
+ <&mcbsp4_ick>, <&gpio4_dbck>, <&gpt4_ick>,
+ <&gpio5_dbck>, <&mcbsp3_ick>, <&gpio3_dbck>,
+ <&gpt8_ick>, <&gpt5_ick>, <&uart4_fck>,
+ <&gpio6_dbck>, <&uart3_ick>, <&gpt7_ick>,
+ <&gpio2_ick>, <&gpt9_ick>, <&gpio6_ick>,
+ <&gpt3_ick>, <&gpio5_ick>, <&wdt3_fck>,
+ <&gpio4_ick>, <&wdt3_ick>, <&uart4_ick>;
+ };
+
+ emu_clkdm: emu_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&emu_src_ck>;
+ };
+
+ d2d_clkdm: d2d_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&mad2d_ick>, <&sad2d_ick>, <&modem_fck>;
+ };
+ };
+};
\ No newline at end of file
diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
new file mode 100644
index 0000000..f9ccaf1
--- /dev/null
+++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
@@ -0,0 +1,1392 @@
+/*
+ * Device Tree Source for OMAP3 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+dummy_apb_pclk: dummy_apb_pclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0x0>;
+};
+
+omap_32k_fck: omap_32k_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+};
+
+virt_12m_ck: virt_12m_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+};
+
+virt_13m_ck: virt_13m_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <13000000>;
+};
+
+virt_19200000_ck: virt_19200000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <19200000>;
+};
+
+virt_26000000_ck: virt_26000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <26000000>;
+};
+
+virt_38_4m_ck: virt_38_4m_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <38400000>;
+};
+
+virt_16_8m_ck: virt_16_8m_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <16800000>;
+};
+
+osc_sys_ck: osc_sys_ck at 48306d40 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&virt_12m_ck>, <&virt_13m_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_38_4m_ck>, <&virt_16_8m_ck>;
+ reg = <0x48306d40 0x4>;
+};
+
+sys_ck: sys_ck at 48307270 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&osc_sys_ck>;
+ ti,bit-shift = <6>;
+ ti,max-div = <3>;
+ reg = <0x48307270 0x4>;
+ ti,index-starts-at-one;
+};
+
+dpll4_ck: dpll4_ck at 48004d00 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-dpll-per-clock";
+ clocks = <&sys_ck>, <&sys_ck>;
+ reg = <0x48004d00 0x4>, <0x48004d20 0x4>, <0x48004d30 0x4>, <0x48004d44 0x4>;
+};
+
+dpll4_m2_ck: dpll4_m2_ck at 48004d48 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll4_ck>;
+ reg = <0x48004d48 0x4>;
+ ti,max-div = <63>;
+ ti,index-starts-at-one;
+};
+
+dpll4_m2x2_mul_ck: dpll4_m2x2_mul_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll4_m2_ck>;
+ clock-mult = <2>;
+ clock-div = <1>;
+};
+
+dpll4_m2x2_ck: dpll4_m2x2_ck at 48004d00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll4_m2x2_mul_ck>;
+ ti,bit-shift = <0x1b>;
+ reg = <0x48004d00 0x4>;
+ ti,set-bit-to-disable;
+};
+
+omap_96m_alwon_fck: omap_96m_alwon_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll4_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dpll3_ck: dpll3_ck at 48004d00 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-dpll-core-clock";
+ clocks = <&sys_ck>, <&sys_ck>;
+ reg = <0x48004d00 0x4>, <0x48004d20 0x4>, <0x48004d30 0x4>, <0x48004d40 0x4>;
+};
+
+dpll3_m3_ck: dpll3_m3_ck at 48005140 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll3_ck>;
+ ti,bit-shift = <16>;
+ ti,max-div = <31>;
+ reg = <0x48005140 0x4>;
+ ti,index-starts-at-one;
+};
+
+dpll3_m3x2_mul_ck: dpll3_m3x2_mul_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll3_m3_ck>;
+ clock-mult = <2>;
+ clock-div = <1>;
+};
+
+dpll3_m3x2_ck: dpll3_m3x2_ck at 48004d00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll3_m3x2_mul_ck>;
+ ti,bit-shift = <0xc>;
+ reg = <0x48004d00 0x4>;
+ ti,set-bit-to-disable;
+};
+
+emu_core_alwon_ck: emu_core_alwon_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll3_m3x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+sys_altclk: sys_altclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0x0>;
+};
+
+mcbsp_clks: mcbsp_clks {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0x0>;
+};
+
+sys_clkout1: sys_clkout1 at 48306d70 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&osc_sys_ck>;
+ reg = <0x48306d70 0x4>;
+ ti,bit-shift = <7>;
+};
+
+dpll3_m2_ck: dpll3_m2_ck at 48004d40 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll3_ck>;
+ ti,bit-shift = <27>;
+ ti,max-div = <31>;
+ reg = <0x48004d40 0x4>;
+ ti,index-starts-at-one;
+};
+
+core_ck: core_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll3_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dpll1_fck: dpll1_fck at 48004940 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&core_ck>;
+ ti,bit-shift = <19>;
+ ti,max-div = <7>;
+ reg = <0x48004940 0x4>;
+ ti,index-starts-at-one;
+};
+
+dpll1_ck: dpll1_ck at 48004904 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-dpll-clock";
+ clocks = <&sys_ck>, <&dpll1_fck>;
+ reg = <0x48004904 0x4>, <0x48004924 0x4>, <0x48004934 0x4>, <0x48004940 0x4>;
+ ti,low-power-bypass;
+ ti,lock;
+};
+
+dpll1_x2_ck: dpll1_x2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll1_ck>;
+ clock-mult = <2>;
+ clock-div = <1>;
+};
+
+dpll1_x2m2_ck: dpll1_x2m2_ck at 48004944 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll1_x2_ck>;
+ reg = <0x48004944 0x4>;
+ ti,max-div = <31>;
+ ti,index-starts-at-one;
+};
+
+dpll3_x2_ck: dpll3_x2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll3_ck>;
+ clock-mult = <2>;
+ clock-div = <1>;
+};
+
+dpll3_m2x2_ck: dpll3_m2x2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll3_m2_ck>;
+ clock-mult = <2>;
+ clock-div = <1>;
+};
+
+dpll4_x2_ck: dpll4_x2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll4_ck>;
+ clock-mult = <2>;
+ clock-div = <1>;
+};
+
+cm_96m_fck: cm_96m_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_96m_alwon_fck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+omap_96m_fck: omap_96m_fck at 48004d40 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&cm_96m_fck>, <&sys_ck>;
+ ti,bit-shift = <6>;
+ reg = <0x48004d40 0x4>;
+};
+
+dpll4_m3_ck: dpll4_m3_ck at 48004e40 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll4_ck>;
+ ti,bit-shift = <8>;
+ ti,max-div = <63>;
+ reg = <0x48004e40 0x4>;
+ ti,index-starts-at-one;
+};
+
+dpll4_m3x2_mul_ck: dpll4_m3x2_mul_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll4_m3_ck>;
+ clock-mult = <2>;
+ clock-div = <1>;
+};
+
+dpll4_m3x2_ck: dpll4_m3x2_ck at 48004d00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll4_m3x2_mul_ck>;
+ ti,bit-shift = <0x1c>;
+ reg = <0x48004d00 0x4>;
+ ti,set-bit-to-disable;
+};
+
+omap_54m_fck: omap_54m_fck at 48004d40 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dpll4_m3x2_ck>, <&sys_altclk>;
+ ti,bit-shift = <5>;
+ reg = <0x48004d40 0x4>;
+};
+
+cm_96m_d2_fck: cm_96m_d2_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&cm_96m_fck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+omap_48m_fck: omap_48m_fck at 48004d40 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&cm_96m_d2_fck>, <&sys_altclk>;
+ ti,bit-shift = <3>;
+ reg = <0x48004d40 0x4>;
+ ti,table = <&cm_96m_d2_fck 0>, <&sys_altclk 1>;
+};
+
+omap_12m_fck: omap_12m_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_48m_fck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+};
+
+dpll4_m4_ck: dpll4_m4_ck at 48004e40 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll4_ck>;
+ reg = <0x48004e40 0x4>;
+ ti,max-div = <63>;
+ ti,index-starts-at-one;
+};
+
+dpll4_m4x2_mul_ck: dpll4_m4x2_mul_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll4_m4_ck>;
+ clock-mult = <2>;
+ clock-div = <1>;
+};
+
+dpll4_m4x2_ck: dpll4_m4x2_ck at 48004d00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll4_m4x2_mul_ck>;
+ ti,bit-shift = <0x1d>;
+ reg = <0x48004d00 0x4>;
+ ti,set-bit-to-disable;
+};
+
+dpll4_m5_ck: dpll4_m5_ck at 48004f40 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll4_ck>;
+ reg = <0x48004f40 0x4>;
+ ti,max-div = <63>;
+ ti,index-starts-at-one;
+};
+
+dpll4_m5x2_mul_ck: dpll4_m5x2_mul_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll4_m5_ck>;
+ clock-mult = <2>;
+ clock-div = <1>;
+};
+
+dpll4_m5x2_ck: dpll4_m5x2_ck at 48004d00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll4_m5x2_mul_ck>;
+ ti,bit-shift = <0x1e>;
+ reg = <0x48004d00 0x4>;
+ ti,set-bit-to-disable;
+};
+
+dpll4_m6_ck: dpll4_m6_ck at 48005140 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll4_ck>;
+ ti,bit-shift = <24>;
+ ti,max-div = <63>;
+ reg = <0x48005140 0x4>;
+ ti,index-starts-at-one;
+};
+
+dpll4_m6x2_mul_ck: dpll4_m6x2_mul_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll4_m6_ck>;
+ clock-mult = <2>;
+ clock-div = <1>;
+};
+
+dpll4_m6x2_ck: dpll4_m6x2_ck at 48004d00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll4_m6x2_mul_ck>;
+ ti,bit-shift = <0x1f>;
+ reg = <0x48004d00 0x4>;
+ ti,set-bit-to-disable;
+};
+
+emu_per_alwon_ck: emu_per_alwon_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll4_m6x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+clkout2_src_ck: clkout2_src_ck at 48004d70 {
+ #clock-cells = <0>;
+ compatible = "ti,no-wait-mux-gate-clock";
+ clocks = <&core_ck>, <&sys_ck>, <&cm_96m_fck>, <&omap_54m_fck>;
+ ti,gate-bit-shift = <7>;
+ reg = <0x48004d70 0x4>, <0x48004d70 0x4>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+sys_clkout2: sys_clkout2 at 48004d70 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&clkout2_src_ck>;
+ ti,bit-shift = <3>;
+ ti,max-div = <64>;
+ reg = <0x48004d70 0x4>;
+ ti,index-power-of-two;
+};
+
+corex2_fck: corex2_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll3_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+mpu_ck: mpu_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll1_x2m2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+arm_fck: arm_fck at 48004924 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&mpu_ck>;
+ reg = <0x48004924 0x4>;
+ ti,max-div = <2>;
+};
+
+emu_mpu_alwon_ck: emu_mpu_alwon_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&mpu_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+l3_ick: l3_ick at 48004a40 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&core_ck>;
+ reg = <0x48004a40 0x4>;
+ ti,max-div = <3>;
+ ti,index-starts-at-one;
+};
+
+l4_ick: l4_ick at 48004a40 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&l3_ick>;
+ ti,bit-shift = <2>;
+ ti,max-div = <3>;
+ reg = <0x48004a40 0x4>;
+ ti,index-starts-at-one;
+};
+
+rm_ick: rm_ick at 48004c40 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&l4_ick>;
+ ti,bit-shift = <1>;
+ ti,max-div = <3>;
+ reg = <0x48004c40 0x4>;
+ ti,index-starts-at-one;
+};
+
+gpt10_fck: gpt10_fck at 48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-gate-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ ti,gate-bit-shift = <11>;
+ reg = <0x48004a00 0x4>, <0x48004a40 0x4>;
+ ti,mux-bit-shift = <6>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+gpt11_fck: gpt11_fck at 48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-gate-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ ti,gate-bit-shift = <12>;
+ reg = <0x48004a00 0x4>, <0x48004a40 0x4>;
+ ti,mux-bit-shift = <7>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+core_96m_fck: core_96m_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_96m_fck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+mmchs2_fck: mmchs2_fck at 48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_96m_fck>;
+ reg = <0x48004a00 0x4>;
+ ti,bit-shift = <25>;
+};
+
+mmchs1_fck: mmchs1_fck at 48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_96m_fck>;
+ reg = <0x48004a00 0x4>;
+ ti,bit-shift = <24>;
+};
+
+i2c3_fck: i2c3_fck at 48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_96m_fck>;
+ reg = <0x48004a00 0x4>;
+ ti,bit-shift = <17>;
+};
+
+i2c2_fck: i2c2_fck at 48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_96m_fck>;
+ reg = <0x48004a00 0x4>;
+ ti,bit-shift = <16>;
+};
+
+i2c1_fck: i2c1_fck at 48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_96m_fck>;
+ reg = <0x48004a00 0x4>;
+ ti,bit-shift = <15>;
+};
+
+mcbsp5_fck: mcbsp5_fck at 48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-gate-clock";
+ clocks = <&core_96m_fck>, <&mcbsp_clks>;
+ ti,gate-bit-shift = <10>;
+ reg = <0x48004a00 0x4>, <0x480022d8 0x4>;
+ ti,mux-bit-shift = <4>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+mcbsp1_fck: mcbsp1_fck at 48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-gate-clock";
+ clocks = <&core_96m_fck>, <&mcbsp_clks>;
+ ti,gate-bit-shift = <9>;
+ reg = <0x48004a00 0x4>, <0x48002274 0x4>;
+ ti,mux-bit-shift = <2>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+core_48m_fck: core_48m_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_48m_fck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+mcspi4_fck: mcspi4_fck at 48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_48m_fck>;
+ reg = <0x48004a00 0x4>;
+ ti,bit-shift = <21>;
+};
+
+mcspi3_fck: mcspi3_fck at 48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_48m_fck>;
+ reg = <0x48004a00 0x4>;
+ ti,bit-shift = <20>;
+};
+
+mcspi2_fck: mcspi2_fck at 48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_48m_fck>;
+ reg = <0x48004a00 0x4>;
+ ti,bit-shift = <19>;
+};
+
+mcspi1_fck: mcspi1_fck at 48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_48m_fck>;
+ reg = <0x48004a00 0x4>;
+ ti,bit-shift = <18>;
+};
+
+uart2_fck: uart2_fck at 48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_48m_fck>;
+ reg = <0x48004a00 0x4>;
+ ti,bit-shift = <14>;
+};
+
+uart1_fck: uart1_fck at 48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_48m_fck>;
+ reg = <0x48004a00 0x4>;
+ ti,bit-shift = <13>;
+};
+
+core_12m_fck: core_12m_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_12m_fck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+hdq_fck: hdq_fck at 48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_12m_fck>;
+ reg = <0x48004a00 0x4>;
+ ti,bit-shift = <22>;
+};
+
+core_l3_ick: core_l3_ick {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l3_ick>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+sdrc_ick: sdrc_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_l3_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <1>;
+};
+
+gpmc_fck: gpmc_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&core_l3_ick>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+core_l4_ick: core_l4_ick {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l4_ick>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+mmchs2_ick: mmchs2_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <25>;
+};
+
+mmchs1_ick: mmchs1_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <24>;
+};
+
+hdq_ick: hdq_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <22>;
+};
+
+mcspi4_ick: mcspi4_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <21>;
+};
+
+mcspi3_ick: mcspi3_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <20>;
+};
+
+mcspi2_ick: mcspi2_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <19>;
+};
+
+mcspi1_ick: mcspi1_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <18>;
+};
+
+i2c3_ick: i2c3_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <17>;
+};
+
+i2c2_ick: i2c2_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <16>;
+};
+
+i2c1_ick: i2c1_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <15>;
+};
+
+uart2_ick: uart2_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <14>;
+};
+
+uart1_ick: uart1_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <13>;
+};
+
+gpt11_ick: gpt11_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <12>;
+};
+
+gpt10_ick: gpt10_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <11>;
+};
+
+mcbsp5_ick: mcbsp5_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <10>;
+};
+
+mcbsp1_ick: mcbsp1_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <9>;
+};
+
+omapctrl_ick: omapctrl_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <6>;
+};
+
+dss_tv_fck: dss_tv_fck at 48004e00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&omap_54m_fck>;
+ reg = <0x48004e00 0x4>;
+ ti,bit-shift = <2>;
+};
+
+dss_96m_fck: dss_96m_fck at 48004e00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&omap_96m_fck>;
+ reg = <0x48004e00 0x4>;
+ ti,bit-shift = <2>;
+};
+
+dss2_alwon_fck: dss2_alwon_fck at 48004e00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_ck>;
+ reg = <0x48004e00 0x4>;
+ ti,bit-shift = <1>;
+};
+
+dummy_ck: dummy_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+gpt1_fck: gpt1_fck at 48004c00 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-gate-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ ti,gate-bit-shift = <0>;
+ reg = <0x48004c00 0x4>, <0x48004c40 0x4>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+aes2_ick: aes2_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ ti,bit-shift = <28>;
+ reg = <0x48004a10 0x4>;
+};
+
+wkup_32k_fck: wkup_32k_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_32k_fck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+gpio1_dbck: gpio1_dbck at 48004c00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&wkup_32k_fck>;
+ reg = <0x48004c00 0x4>;
+ ti,bit-shift = <3>;
+};
+
+sha12_ick: sha12_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,bit-shift = <27>;
+};
+
+wdt2_fck: wdt2_fck at 48004c00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&wkup_32k_fck>;
+ reg = <0x48004c00 0x4>;
+ ti,bit-shift = <5>;
+};
+
+wkup_l4_ick: wkup_l4_ick {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+wdt2_ick: wdt2_ick at 48004c10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&wkup_l4_ick>;
+ reg = <0x48004c10 0x4>;
+ ti,bit-shift = <5>;
+};
+
+wdt1_ick: wdt1_ick at 48004c10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&wkup_l4_ick>;
+ reg = <0x48004c10 0x4>;
+ ti,bit-shift = <4>;
+};
+
+gpio1_ick: gpio1_ick at 48004c10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&wkup_l4_ick>;
+ reg = <0x48004c10 0x4>;
+ ti,bit-shift = <3>;
+};
+
+omap_32ksync_ick: omap_32ksync_ick at 48004c10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&wkup_l4_ick>;
+ reg = <0x48004c10 0x4>;
+ ti,bit-shift = <2>;
+};
+
+gpt12_ick: gpt12_ick at 48004c10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&wkup_l4_ick>;
+ reg = <0x48004c10 0x4>;
+ ti,bit-shift = <1>;
+};
+
+gpt1_ick: gpt1_ick at 48004c10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&wkup_l4_ick>;
+ reg = <0x48004c10 0x4>;
+ ti,bit-shift = <0>;
+};
+
+per_96m_fck: per_96m_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_96m_alwon_fck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+per_48m_fck: per_48m_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_48m_fck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+uart3_fck: uart3_fck at 48005000 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&per_48m_fck>;
+ reg = <0x48005000 0x4>;
+ ti,bit-shift = <11>;
+};
+
+gpt2_fck: gpt2_fck at 48005000 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-gate-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ ti,gate-bit-shift = <3>;
+ reg = <0x48005000 0x4>, <0x48005040 0x4>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+gpt3_fck: gpt3_fck at 48005000 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-gate-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ ti,gate-bit-shift = <4>;
+ reg = <0x48005000 0x4>, <0x48005040 0x4>;
+ ti,mux-bit-shift = <1>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+gpt4_fck: gpt4_fck at 48005000 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-gate-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ ti,gate-bit-shift = <5>;
+ reg = <0x48005000 0x4>, <0x48005040 0x4>;
+ ti,mux-bit-shift = <2>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+gpt5_fck: gpt5_fck at 48005000 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-gate-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ ti,gate-bit-shift = <6>;
+ reg = <0x48005000 0x4>, <0x48005040 0x4>;
+ ti,mux-bit-shift = <3>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+gpt6_fck: gpt6_fck at 48005000 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-gate-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ ti,gate-bit-shift = <7>;
+ reg = <0x48005000 0x4>, <0x48005040 0x4>;
+ ti,mux-bit-shift = <4>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+gpt7_fck: gpt7_fck at 48005000 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-gate-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ ti,gate-bit-shift = <8>;
+ reg = <0x48005000 0x4>, <0x48005040 0x4>;
+ ti,mux-bit-shift = <5>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+gpt8_fck: gpt8_fck at 48005000 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-gate-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ ti,gate-bit-shift = <9>;
+ reg = <0x48005000 0x4>, <0x48005040 0x4>;
+ ti,mux-bit-shift = <6>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+gpt9_fck: gpt9_fck at 48005000 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-gate-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ ti,gate-bit-shift = <10>;
+ reg = <0x48005000 0x4>, <0x48005040 0x4>;
+ ti,mux-bit-shift = <7>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+per_32k_alwon_fck: per_32k_alwon_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_32k_fck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+gpio6_dbck: gpio6_dbck at 48005000 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&per_32k_alwon_fck>;
+ reg = <0x48005000 0x4>;
+ ti,bit-shift = <17>;
+};
+
+gpio5_dbck: gpio5_dbck at 48005000 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&per_32k_alwon_fck>;
+ reg = <0x48005000 0x4>;
+ ti,bit-shift = <16>;
+};
+
+gpio4_dbck: gpio4_dbck at 48005000 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&per_32k_alwon_fck>;
+ reg = <0x48005000 0x4>;
+ ti,bit-shift = <15>;
+};
+
+gpio3_dbck: gpio3_dbck at 48005000 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&per_32k_alwon_fck>;
+ reg = <0x48005000 0x4>;
+ ti,bit-shift = <14>;
+};
+
+gpio2_dbck: gpio2_dbck at 48005000 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&per_32k_alwon_fck>;
+ reg = <0x48005000 0x4>;
+ ti,bit-shift = <13>;
+};
+
+wdt3_fck: wdt3_fck at 48005000 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&per_32k_alwon_fck>;
+ reg = <0x48005000 0x4>;
+ ti,bit-shift = <12>;
+};
+
+per_l4_ick: per_l4_ick {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l4_ick>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+gpio6_ick: gpio6_ick at 48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,bit-shift = <17>;
+};
+
+gpio5_ick: gpio5_ick at 48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,bit-shift = <16>;
+};
+
+gpio4_ick: gpio4_ick at 48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,bit-shift = <15>;
+};
+
+gpio3_ick: gpio3_ick at 48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,bit-shift = <14>;
+};
+
+gpio2_ick: gpio2_ick at 48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,bit-shift = <13>;
+};
+
+wdt3_ick: wdt3_ick at 48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,bit-shift = <12>;
+};
+
+uart3_ick: uart3_ick at 48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,bit-shift = <11>;
+};
+
+uart4_ick: uart4_ick at 48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,bit-shift = <18>;
+};
+
+gpt9_ick: gpt9_ick at 48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,bit-shift = <10>;
+};
+
+gpt8_ick: gpt8_ick at 48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,bit-shift = <9>;
+};
+
+gpt7_ick: gpt7_ick at 48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,bit-shift = <8>;
+};
+
+gpt6_ick: gpt6_ick at 48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,bit-shift = <7>;
+};
+
+gpt5_ick: gpt5_ick at 48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,bit-shift = <6>;
+};
+
+gpt4_ick: gpt4_ick at 48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,bit-shift = <5>;
+};
+
+gpt3_ick: gpt3_ick at 48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,bit-shift = <4>;
+};
+
+gpt2_ick: gpt2_ick at 48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,bit-shift = <3>;
+};
+
+mcbsp2_ick: mcbsp2_ick at 48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,bit-shift = <0>;
+};
+
+mcbsp3_ick: mcbsp3_ick at 48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,bit-shift = <1>;
+};
+
+mcbsp4_ick: mcbsp4_ick at 48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,bit-shift = <2>;
+};
+
+mcbsp2_fck: mcbsp2_fck at 48005000 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-gate-clock";
+ clocks = <&per_96m_fck>, <&mcbsp_clks>;
+ ti,gate-bit-shift = <0>;
+ reg = <0x48005000 0x4>, <0x48002274 0x4>;
+ ti,mux-bit-shift = <6>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+mcbsp3_fck: mcbsp3_fck at 48005000 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-gate-clock";
+ clocks = <&per_96m_fck>, <&mcbsp_clks>;
+ ti,gate-bit-shift = <1>;
+ reg = <0x48005000 0x4>, <0x480022d8 0x4>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+mcbsp4_fck: mcbsp4_fck at 48005000 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-gate-clock";
+ clocks = <&per_96m_fck>, <&mcbsp_clks>;
+ ti,gate-bit-shift = <2>;
+ reg = <0x48005000 0x4>, <0x480022d8 0x4>;
+ ti,mux-bit-shift = <2>;
+ reg-names = "gate-reg", "mux-reg";
+};
+
+emu_src_mux_ck: emu_src_mux_ck at 48005140 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
+ reg = <0x48005140 0x4>;
+};
+
+emu_src_ck: emu_src_ck {
+ #clock-cells = <0>;
+ compatible = "ti,clkdm-gate-clock";
+ clocks = <&emu_src_mux_ck>;
+};
+
+pclk_fck: pclk_fck at 48005140 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&emu_src_ck>;
+ ti,bit-shift = <8>;
+ ti,max-div = <7>;
+ reg = <0x48005140 0x4>;
+ ti,index-starts-at-one;
+};
+
+pclkx2_fck: pclkx2_fck at 48005140 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&emu_src_ck>;
+ ti,bit-shift = <6>;
+ ti,max-div = <3>;
+ reg = <0x48005140 0x4>;
+ ti,index-starts-at-one;
+};
+
+atclk_fck: atclk_fck at 48005140 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&emu_src_ck>;
+ ti,bit-shift = <4>;
+ ti,max-div = <3>;
+ reg = <0x48005140 0x4>;
+ ti,index-starts-at-one;
+};
+
+traceclk_src_fck: traceclk_src_fck at 48005140 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x48005140 0x4>;
+};
+
+traceclk_fck: traceclk_fck at 48005140 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&traceclk_src_fck>;
+ ti,bit-shift = <11>;
+ ti,max-div = <7>;
+ reg = <0x48005140 0x4>;
+ ti,index-starts-at-one;
+};
+
+secure_32k_fck: secure_32k_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+};
+
+gpt12_fck: gpt12_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&secure_32k_fck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+wdt1_fck: wdt1_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&secure_32k_fck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 31/36] CLK: TI: add omap3 clock init file
2013-09-25 8:48 ` Tero Kristo
@ 2013-09-25 8:48 ` Tero Kristo
-1 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-omap-u79uwXL29TY76Z2rM5mHXA, paul-DWxLp4Yu+b8AvxtiuMwx3w,
tony-4v6yS6AI5VpBDgjK7y7TUQ, nm-l0cyMroinI0, rnayak-l0cyMroinI0,
bcousson-rdvid1DuHRBWk0Htik3J/w,
mturquette-QSEj5FYQhm4dnm+yROfE0A
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
clk-3xxx.c now contains the clock init functionality for omap3, including
DT clock registration and adding of static clkdev entries.
Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
arch/arm/mach-omap2/clock3xxx.h | 1 -
drivers/clk/ti/Makefile | 2 +-
drivers/clk/ti/clk-3xxx.c | 402 +++++++++++++++++++++++++++++++++++++++
include/linux/clk/ti.h | 5 +
4 files changed, 408 insertions(+), 2 deletions(-)
create mode 100644 drivers/clk/ti/clk-3xxx.c
diff --git a/arch/arm/mach-omap2/clock3xxx.h b/arch/arm/mach-omap2/clock3xxx.h
index dab90e2..78d9f56 100644
--- a/arch/arm/mach-omap2/clock3xxx.h
+++ b/arch/arm/mach-omap2/clock3xxx.h
@@ -11,7 +11,6 @@
int omap3xxx_clk_init(void);
int omap3_core_dpll_m2_set_rate(struct clk_hw *clk, unsigned long rate,
unsigned long parent_rate);
-void omap3_clk_lock_dpll5(void);
extern struct clk *sdrc_ick_p;
extern struct clk *arm_fck_p;
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 1ecb1a4..df226bc 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -3,7 +3,7 @@ obj-y += clk.o dpll.o autoidle.o divider.o \
fixed-factor.o gate.o clockdomain.o \
mux-gate.o mux.o apll.o
obj-$(CONFIG_SOC_AM33XX) += clk-33xx.o
-obj-$(CONFIG_ARCH_OMAP3) += interface.o
+obj-$(CONFIG_ARCH_OMAP3) += interface.o clk-3xxx.o
obj-$(CONFIG_ARCH_OMAP4) += clk-44xx.o
obj-$(CONFIG_SOC_OMAP5) += clk-54xx.o
obj-$(CONFIG_SOC_DRA7XX) += clk-7xx.o
diff --git a/drivers/clk/ti/clk-3xxx.c b/drivers/clk/ti/clk-3xxx.c
new file mode 100644
index 0000000..394324b
--- /dev/null
+++ b/drivers/clk/ti/clk-3xxx.c
@@ -0,0 +1,402 @@
+/*
+ * OMAP3 Clock init
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc
+ * Tero Kristo (t-kristo-l0cyMroinI0@public.gmane.org)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/clk-provider.h>
+#include <linux/clk/ti.h>
+
+
+static struct ti_dt_clk omap3xxx_clks[] = {
+ DT_CLK(NULL, "apb_pclk", "dummy_apb_pclk"),
+ DT_CLK(NULL, "omap_32k_fck", "omap_32k_fck"),
+ DT_CLK(NULL, "virt_12m_ck", "virt_12m_ck"),
+ DT_CLK(NULL, "virt_13m_ck", "virt_13m_ck"),
+ DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
+ DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
+ DT_CLK(NULL, "virt_38_4m_ck", "virt_38_4m_ck"),
+ DT_CLK(NULL, "osc_sys_ck", "osc_sys_ck"),
+ DT_CLK("twl", "fck", "osc_sys_ck"),
+ DT_CLK(NULL, "sys_ck", "sys_ck"),
+ DT_CLK(NULL, "omap_96m_alwon_fck", "omap_96m_alwon_fck"),
+ DT_CLK("etb", "emu_core_alwon_ck", "emu_core_alwon_ck"),
+ DT_CLK(NULL, "sys_altclk", "sys_altclk"),
+ DT_CLK(NULL, "mcbsp_clks", "mcbsp_clks"),
+ DT_CLK(NULL, "sys_clkout1", "sys_clkout1"),
+ DT_CLK(NULL, "dpll1_ck", "dpll1_ck"),
+ DT_CLK(NULL, "dpll1_x2_ck", "dpll1_x2_ck"),
+ DT_CLK(NULL, "dpll1_x2m2_ck", "dpll1_x2m2_ck"),
+ DT_CLK(NULL, "dpll3_ck", "dpll3_ck"),
+ DT_CLK(NULL, "core_ck", "core_ck"),
+ DT_CLK(NULL, "dpll3_x2_ck", "dpll3_x2_ck"),
+ DT_CLK(NULL, "dpll3_m2_ck", "dpll3_m2_ck"),
+ DT_CLK(NULL, "dpll3_m2x2_ck", "dpll3_m2x2_ck"),
+ DT_CLK(NULL, "dpll3_m3_ck", "dpll3_m3_ck"),
+ DT_CLK(NULL, "dpll3_m3x2_ck", "dpll3_m3x2_ck"),
+ DT_CLK(NULL, "dpll4_ck", "dpll4_ck"),
+ DT_CLK(NULL, "dpll4_x2_ck", "dpll4_x2_ck"),
+ DT_CLK(NULL, "omap_96m_fck", "omap_96m_fck"),
+ DT_CLK(NULL, "cm_96m_fck", "cm_96m_fck"),
+ DT_CLK(NULL, "omap_54m_fck", "omap_54m_fck"),
+ DT_CLK(NULL, "omap_48m_fck", "omap_48m_fck"),
+ DT_CLK(NULL, "omap_12m_fck", "omap_12m_fck"),
+ DT_CLK(NULL, "dpll4_m2_ck", "dpll4_m2_ck"),
+ DT_CLK(NULL, "dpll4_m2x2_ck", "dpll4_m2x2_ck"),
+ DT_CLK(NULL, "dpll4_m3_ck", "dpll4_m3_ck"),
+ DT_CLK(NULL, "dpll4_m3x2_ck", "dpll4_m3x2_ck"),
+ DT_CLK(NULL, "dpll4_m4_ck", "dpll4_m4_ck"),
+ DT_CLK(NULL, "dpll4_m4x2_ck", "dpll4_m4x2_ck"),
+ DT_CLK(NULL, "dpll4_m5_ck", "dpll4_m5_ck"),
+ DT_CLK(NULL, "dpll4_m5x2_ck", "dpll4_m5x2_ck"),
+ DT_CLK(NULL, "dpll4_m6_ck", "dpll4_m6_ck"),
+ DT_CLK(NULL, "dpll4_m6x2_ck", "dpll4_m6x2_ck"),
+ DT_CLK("etb", "emu_per_alwon_ck", "emu_per_alwon_ck"),
+ DT_CLK(NULL, "clkout2_src_ck", "clkout2_src_ck"),
+ DT_CLK(NULL, "sys_clkout2", "sys_clkout2"),
+ DT_CLK(NULL, "corex2_fck", "corex2_fck"),
+ DT_CLK(NULL, "dpll1_fck", "dpll1_fck"),
+ DT_CLK(NULL, "mpu_ck", "mpu_ck"),
+ DT_CLK(NULL, "arm_fck", "arm_fck"),
+ DT_CLK("etb", "emu_mpu_alwon_ck", "emu_mpu_alwon_ck"),
+ DT_CLK(NULL, "l3_ick", "l3_ick"),
+ DT_CLK(NULL, "l4_ick", "l4_ick"),
+ DT_CLK(NULL, "rm_ick", "rm_ick"),
+ DT_CLK(NULL, "gpt10_fck", "gpt10_fck"),
+ DT_CLK(NULL, "gpt11_fck", "gpt11_fck"),
+ DT_CLK(NULL, "core_96m_fck", "core_96m_fck"),
+ DT_CLK(NULL, "mmchs2_fck", "mmchs2_fck"),
+ DT_CLK(NULL, "mmchs1_fck", "mmchs1_fck"),
+ DT_CLK(NULL, "i2c3_fck", "i2c3_fck"),
+ DT_CLK(NULL, "i2c2_fck", "i2c2_fck"),
+ DT_CLK(NULL, "i2c1_fck", "i2c1_fck"),
+ DT_CLK(NULL, "mcbsp5_fck", "mcbsp5_fck"),
+ DT_CLK(NULL, "mcbsp1_fck", "mcbsp1_fck"),
+ DT_CLK(NULL, "core_48m_fck", "core_48m_fck"),
+ DT_CLK(NULL, "mcspi4_fck", "mcspi4_fck"),
+ DT_CLK(NULL, "mcspi3_fck", "mcspi3_fck"),
+ DT_CLK(NULL, "mcspi2_fck", "mcspi2_fck"),
+ DT_CLK(NULL, "mcspi1_fck", "mcspi1_fck"),
+ DT_CLK(NULL, "uart2_fck", "uart2_fck"),
+ DT_CLK(NULL, "uart1_fck", "uart1_fck"),
+ DT_CLK(NULL, "core_12m_fck", "core_12m_fck"),
+ DT_CLK("omap_hdq.0", "fck", "hdq_fck"),
+ DT_CLK(NULL, "hdq_fck", "hdq_fck"),
+ DT_CLK(NULL, "core_l3_ick", "core_l3_ick"),
+ DT_CLK(NULL, "sdrc_ick", "sdrc_ick"),
+ DT_CLK(NULL, "gpmc_fck", "gpmc_fck"),
+ DT_CLK(NULL, "core_l4_ick", "core_l4_ick"),
+ DT_CLK("omap_hsmmc.1", "ick", "mmchs2_ick"),
+ DT_CLK("omap_hsmmc.0", "ick", "mmchs1_ick"),
+ DT_CLK(NULL, "mmchs2_ick", "mmchs2_ick"),
+ DT_CLK(NULL, "mmchs1_ick", "mmchs1_ick"),
+ DT_CLK("omap_hdq.0", "ick", "hdq_ick"),
+ DT_CLK(NULL, "hdq_ick", "hdq_ick"),
+ DT_CLK("omap2_mcspi.4", "ick", "mcspi4_ick"),
+ DT_CLK("omap2_mcspi.3", "ick", "mcspi3_ick"),
+ DT_CLK("omap2_mcspi.2", "ick", "mcspi2_ick"),
+ DT_CLK("omap2_mcspi.1", "ick", "mcspi1_ick"),
+ DT_CLK(NULL, "mcspi4_ick", "mcspi4_ick"),
+ DT_CLK(NULL, "mcspi3_ick", "mcspi3_ick"),
+ DT_CLK(NULL, "mcspi2_ick", "mcspi2_ick"),
+ DT_CLK(NULL, "mcspi1_ick", "mcspi1_ick"),
+ DT_CLK("omap_i2c.3", "ick", "i2c3_ick"),
+ DT_CLK("omap_i2c.2", "ick", "i2c2_ick"),
+ DT_CLK("omap_i2c.1", "ick", "i2c1_ick"),
+ DT_CLK(NULL, "i2c3_ick", "i2c3_ick"),
+ DT_CLK(NULL, "i2c2_ick", "i2c2_ick"),
+ DT_CLK(NULL, "i2c1_ick", "i2c1_ick"),
+ DT_CLK(NULL, "uart2_ick", "uart2_ick"),
+ DT_CLK(NULL, "uart1_ick", "uart1_ick"),
+ DT_CLK(NULL, "gpt11_ick", "gpt11_ick"),
+ DT_CLK(NULL, "gpt10_ick", "gpt10_ick"),
+ DT_CLK("omap-mcbsp.5", "ick", "mcbsp5_ick"),
+ DT_CLK("omap-mcbsp.1", "ick", "mcbsp1_ick"),
+ DT_CLK(NULL, "mcbsp5_ick", "mcbsp5_ick"),
+ DT_CLK(NULL, "mcbsp1_ick", "mcbsp1_ick"),
+ DT_CLK(NULL, "omapctrl_ick", "omapctrl_ick"),
+ DT_CLK(NULL, "dss_tv_fck", "dss_tv_fck"),
+ DT_CLK(NULL, "dss_96m_fck", "dss_96m_fck"),
+ DT_CLK(NULL, "dss2_alwon_fck", "dss2_alwon_fck"),
+ DT_CLK(NULL, "utmi_p1_gfclk", "dummy_ck"),
+ DT_CLK(NULL, "utmi_p2_gfclk", "dummy_ck"),
+ DT_CLK(NULL, "xclk60mhsp1_ck", "dummy_ck"),
+ DT_CLK(NULL, "xclk60mhsp2_ck", "dummy_ck"),
+ DT_CLK(NULL, "init_60m_fclk", "dummy_ck"),
+ DT_CLK(NULL, "gpt1_fck", "gpt1_fck"),
+ DT_CLK(NULL, "aes2_ick", "aes2_ick"),
+ DT_CLK(NULL, "wkup_32k_fck", "wkup_32k_fck"),
+ DT_CLK(NULL, "gpio1_dbck", "gpio1_dbck"),
+ DT_CLK(NULL, "sha12_ick", "sha12_ick"),
+ DT_CLK(NULL, "wdt2_fck", "wdt2_fck"),
+ DT_CLK("omap_wdt", "ick", "wdt2_ick"),
+ DT_CLK(NULL, "wdt2_ick", "wdt2_ick"),
+ DT_CLK(NULL, "wdt1_ick", "wdt1_ick"),
+ DT_CLK(NULL, "gpio1_ick", "gpio1_ick"),
+ DT_CLK(NULL, "omap_32ksync_ick", "omap_32ksync_ick"),
+ DT_CLK(NULL, "gpt12_ick", "gpt12_ick"),
+ DT_CLK(NULL, "gpt1_ick", "gpt1_ick"),
+ DT_CLK(NULL, "per_96m_fck", "per_96m_fck"),
+ DT_CLK(NULL, "per_48m_fck", "per_48m_fck"),
+ DT_CLK(NULL, "uart3_fck", "uart3_fck"),
+ DT_CLK(NULL, "gpt2_fck", "gpt2_fck"),
+ DT_CLK(NULL, "gpt3_fck", "gpt3_fck"),
+ DT_CLK(NULL, "gpt4_fck", "gpt4_fck"),
+ DT_CLK(NULL, "gpt5_fck", "gpt5_fck"),
+ DT_CLK(NULL, "gpt6_fck", "gpt6_fck"),
+ DT_CLK(NULL, "gpt7_fck", "gpt7_fck"),
+ DT_CLK(NULL, "gpt8_fck", "gpt8_fck"),
+ DT_CLK(NULL, "gpt9_fck", "gpt9_fck"),
+ DT_CLK(NULL, "per_32k_alwon_fck", "per_32k_alwon_fck"),
+ DT_CLK(NULL, "gpio6_dbck", "gpio6_dbck"),
+ DT_CLK(NULL, "gpio5_dbck", "gpio5_dbck"),
+ DT_CLK(NULL, "gpio4_dbck", "gpio4_dbck"),
+ DT_CLK(NULL, "gpio3_dbck", "gpio3_dbck"),
+ DT_CLK(NULL, "gpio2_dbck", "gpio2_dbck"),
+ DT_CLK(NULL, "wdt3_fck", "wdt3_fck"),
+ DT_CLK(NULL, "per_l4_ick", "per_l4_ick"),
+ DT_CLK(NULL, "gpio6_ick", "gpio6_ick"),
+ DT_CLK(NULL, "gpio5_ick", "gpio5_ick"),
+ DT_CLK(NULL, "gpio4_ick", "gpio4_ick"),
+ DT_CLK(NULL, "gpio3_ick", "gpio3_ick"),
+ DT_CLK(NULL, "gpio2_ick", "gpio2_ick"),
+ DT_CLK(NULL, "wdt3_ick", "wdt3_ick"),
+ DT_CLK(NULL, "uart3_ick", "uart3_ick"),
+ DT_CLK(NULL, "uart4_ick", "uart4_ick"),
+ DT_CLK(NULL, "gpt9_ick", "gpt9_ick"),
+ DT_CLK(NULL, "gpt8_ick", "gpt8_ick"),
+ DT_CLK(NULL, "gpt7_ick", "gpt7_ick"),
+ DT_CLK(NULL, "gpt6_ick", "gpt6_ick"),
+ DT_CLK(NULL, "gpt5_ick", "gpt5_ick"),
+ DT_CLK(NULL, "gpt4_ick", "gpt4_ick"),
+ DT_CLK(NULL, "gpt3_ick", "gpt3_ick"),
+ DT_CLK(NULL, "gpt2_ick", "gpt2_ick"),
+ DT_CLK("omap-mcbsp.2", "ick", "mcbsp2_ick"),
+ DT_CLK("omap-mcbsp.3", "ick", "mcbsp3_ick"),
+ DT_CLK("omap-mcbsp.4", "ick", "mcbsp4_ick"),
+ DT_CLK(NULL, "mcbsp4_ick", "mcbsp2_ick"),
+ DT_CLK(NULL, "mcbsp3_ick", "mcbsp3_ick"),
+ DT_CLK(NULL, "mcbsp2_ick", "mcbsp4_ick"),
+ DT_CLK(NULL, "mcbsp2_fck", "mcbsp2_fck"),
+ DT_CLK(NULL, "mcbsp3_fck", "mcbsp3_fck"),
+ DT_CLK(NULL, "mcbsp4_fck", "mcbsp4_fck"),
+ DT_CLK("etb", "emu_src_ck", "emu_src_ck"),
+ DT_CLK(NULL, "emu_src_ck", "emu_src_ck"),
+ DT_CLK(NULL, "pclk_fck", "pclk_fck"),
+ DT_CLK(NULL, "pclkx2_fck", "pclkx2_fck"),
+ DT_CLK(NULL, "atclk_fck", "atclk_fck"),
+ DT_CLK(NULL, "traceclk_src_fck", "traceclk_src_fck"),
+ DT_CLK(NULL, "traceclk_fck", "traceclk_fck"),
+ DT_CLK(NULL, "secure_32k_fck", "secure_32k_fck"),
+ DT_CLK(NULL, "gpt12_fck", "gpt12_fck"),
+ DT_CLK(NULL, "wdt1_fck", "wdt1_fck"),
+ DT_CLK(NULL, "timer_32k_ck", "omap_32k_fck"),
+ DT_CLK(NULL, "timer_sys_ck", "sys_ck"),
+ DT_CLK(NULL, "cpufreq_ck", "dpll1_ck"),
+ { .node_name = NULL },
+};
+
+static struct ti_dt_clk omap34xx_omap36xx_clks[] = {
+ DT_CLK(NULL, "aes1_ick", "aes1_ick"),
+ DT_CLK("omap_rng", "ick", "rng_ick"),
+ DT_CLK(NULL, "sha11_ick", "sha11_ick"),
+ DT_CLK(NULL, "des1_ick", "des1_ick"),
+ DT_CLK(NULL, "cam_mclk", "cam_mclk"),
+ DT_CLK(NULL, "cam_ick", "cam_ick"),
+ DT_CLK(NULL, "csi2_96m_fck", "csi2_96m_fck"),
+ DT_CLK(NULL, "security_l3_ick", "security_l3_ick"),
+ DT_CLK(NULL, "pka_ick", "pka_ick"),
+ DT_CLK(NULL, "icr_ick", "icr_ick"),
+ DT_CLK("omap-aes", "ick", "aes2_ick"),
+ DT_CLK("omap-sham", "ick", "sha12_ick"),
+ DT_CLK(NULL, "des2_ick", "des2_ick"),
+ DT_CLK(NULL, "mspro_ick", "mspro_ick"),
+ DT_CLK(NULL, "mailboxes_ick", "mailboxes_ick"),
+ DT_CLK(NULL, "ssi_l4_ick", "ssi_l4_ick"),
+ DT_CLK(NULL, "sr1_fck", "sr1_fck"),
+ DT_CLK(NULL, "sr2_fck", "sr2_fck"),
+ DT_CLK(NULL, "sr_l4_ick", "sr_l4_ick"),
+ DT_CLK(NULL, "security_l4_ick2", "security_l4_ick2"),
+ DT_CLK(NULL, "wkup_l4_ick", "wkup_l4_ick"),
+ DT_CLK(NULL, "dpll2_fck", "dpll2_fck"),
+ DT_CLK(NULL, "iva2_ck", "iva2_ck"),
+ DT_CLK(NULL, "modem_fck", "modem_fck"),
+ DT_CLK(NULL, "sad2d_ick", "sad2d_ick"),
+ DT_CLK(NULL, "mad2d_ick", "mad2d_ick"),
+ DT_CLK(NULL, "mspro_fck", "mspro_fck"),
+ DT_CLK(NULL, "dpll2_ck", "dpll2_ck"),
+ DT_CLK(NULL, "dpll2_m2_ck", "dpll2_m2_ck"),
+ { .node_name = NULL },
+};
+
+static struct ti_dt_clk omap36xx_omap3430es2plus_clks[] = {
+ DT_CLK(NULL, "ssi_ssr_fck", "ssi_ssr_fck_3430es2"),
+ DT_CLK(NULL, "ssi_sst_fck", "ssi_sst_fck_3430es2"),
+ DT_CLK("musb-omap2430", "ick", "hsotgusb_ick_3430es2"),
+ DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_3430es2"),
+ DT_CLK(NULL, "ssi_ick", "ssi_ick_3430es2"),
+ DT_CLK(NULL, "usim_fck", "usim_fck"),
+ DT_CLK(NULL, "usim_ick", "usim_ick"),
+ { .node_name = NULL },
+};
+
+static struct ti_dt_clk omap3430es1_clks[] = {
+ DT_CLK(NULL, "gfx_l3_ck", "gfx_l3_ck"),
+ DT_CLK(NULL, "gfx_l3_fck", "gfx_l3_fck"),
+ DT_CLK(NULL, "gfx_l3_ick", "gfx_l3_ick"),
+ DT_CLK(NULL, "gfx_cg1_ck", "gfx_cg1_ck"),
+ DT_CLK(NULL, "gfx_cg2_ck", "gfx_cg2_ck"),
+ DT_CLK(NULL, "d2d_26m_fck", "d2d_26m_fck"),
+ DT_CLK(NULL, "fshostusb_fck", "fshostusb_fck"),
+ DT_CLK(NULL, "ssi_ssr_fck", "ssi_ssr_fck_3430es1"),
+ DT_CLK(NULL, "ssi_sst_fck", "ssi_sst_fck_3430es1"),
+ DT_CLK("musb-omap2430", "ick", "hsotgusb_ick_3430es1"),
+ DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_3430es1"),
+ DT_CLK(NULL, "fac_ick", "fac_ick"),
+ DT_CLK(NULL, "ssi_ick", "ssi_ick_3430es1"),
+ DT_CLK(NULL, "usb_l4_ick", "usb_l4_ick"),
+ DT_CLK(NULL, "dss1_alwon_fck", "dss1_alwon_fck_3430es1"),
+ DT_CLK("omapdss_dss", "ick", "dss_ick_3430es1"),
+ DT_CLK(NULL, "dss_ick", "dss_ick_3430es1"),
+ { .node_name = NULL },
+};
+
+static struct ti_dt_clk omap36xx_am35xx_omap3430es2plus_clks[] = {
+ DT_CLK(NULL, "virt_16_8m_ck", "virt_16_8m_ck"),
+ DT_CLK(NULL, "dpll5_ck", "dpll5_ck"),
+ DT_CLK(NULL, "dpll5_m2_ck", "dpll5_m2_ck"),
+ DT_CLK(NULL, "sgx_fck", "sgx_fck"),
+ DT_CLK(NULL, "sgx_ick", "sgx_ick"),
+ DT_CLK(NULL, "cpefuse_fck", "cpefuse_fck"),
+ DT_CLK(NULL, "ts_fck", "ts_fck"),
+ DT_CLK(NULL, "usbtll_fck", "usbtll_fck"),
+ DT_CLK(NULL, "usbtll_ick", "usbtll_ick"),
+ DT_CLK("omap_hsmmc.2", "ick", "mmchs3_ick"),
+ DT_CLK(NULL, "mmchs3_ick", "mmchs3_ick"),
+ DT_CLK(NULL, "mmchs3_fck", "mmchs3_fck"),
+ DT_CLK(NULL, "dss1_alwon_fck", "dss1_alwon_fck_3430es2"),
+ DT_CLK("omapdss_dss", "ick", "dss_ick_3430es2"),
+ DT_CLK(NULL, "dss_ick", "dss_ick_3430es2"),
+ DT_CLK(NULL, "usbhost_120m_fck", "usbhost_120m_fck"),
+ DT_CLK(NULL, "usbhost_48m_fck", "usbhost_48m_fck"),
+ DT_CLK(NULL, "usbhost_ick", "usbhost_ick"),
+ { .node_name = NULL },
+};
+
+static struct ti_dt_clk am35xx_clks[] = {
+ DT_CLK(NULL, "ipss_ick", "ipss_ick"),
+ DT_CLK(NULL, "rmii_ck", "rmii_ck"),
+ DT_CLK(NULL, "pclk_ck", "pclk_ck"),
+ DT_CLK(NULL, "emac_ick", "emac_ick"),
+ DT_CLK(NULL, "emac_fck", "emac_fck"),
+ DT_CLK("davinci_emac.0", NULL, "emac_ick"),
+ DT_CLK("davinci_mdio.0", NULL, "emac_fck"),
+ DT_CLK("vpfe-capture", "master", "vpfe_ick"),
+ DT_CLK("vpfe-capture", "slave", "vpfe_fck"),
+ DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_am35xx"),
+ DT_CLK(NULL, "hsotgusb_fck", "hsotgusb_fck_am35xx"),
+ DT_CLK(NULL, "hecc_ck", "hecc_ck"),
+ DT_CLK(NULL, "uart4_ick", "uart4_ick_am35xx"),
+ DT_CLK(NULL, "uart4_fck", "uart4_fck_am35xx"),
+ { .node_name = NULL },
+};
+
+static struct ti_dt_clk omap36xx_clks[] = {
+ DT_CLK(NULL, "omap_192m_alwon_fck", "omap_192m_alwon_fck"),
+ DT_CLK(NULL, "uart4_fck", "uart4_fck"),
+ { .node_name = NULL },
+};
+
+static const char *enable_init_clks[] = {
+ "sdrc_ick",
+ "gpmc_fck",
+ "omapctrl_ick",
+};
+
+enum {
+ OMAP3_SOC_AM35XX,
+ OMAP3_SOC_OMAP3430_ES1,
+ OMAP3_SOC_OMAP3430_ES2_PLUS,
+ OMAP3_SOC_OMAP3630,
+ OMAP3_SOC_TI81XX,
+};
+
+static int __init omap3xxx_clk_init(int soc_type)
+{
+ of_clk_init(NULL);
+
+ if (soc_type == OMAP3_SOC_AM35XX || soc_type == OMAP3_SOC_OMAP3630 ||
+ soc_type == OMAP3_SOC_OMAP3430_ES1 ||
+ soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS)
+ ti_dt_clocks_register(omap3xxx_clks);
+
+ if (soc_type == OMAP3_SOC_AM35XX)
+ ti_dt_clocks_register(am35xx_clks);
+
+ if (soc_type == OMAP3_SOC_OMAP3630 || soc_type == OMAP3_SOC_AM35XX ||
+ soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS)
+ ti_dt_clocks_register(omap36xx_am35xx_omap3430es2plus_clks);
+
+ if (soc_type == OMAP3_SOC_OMAP3430_ES1)
+ ti_dt_clocks_register(omap3430es1_clks);
+
+ if (soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS ||
+ soc_type == OMAP3_SOC_OMAP3630)
+ ti_dt_clocks_register(omap36xx_omap3430es2plus_clks);
+
+ if (soc_type == OMAP3_SOC_OMAP3430_ES1 ||
+ soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS ||
+ soc_type == OMAP3_SOC_OMAP3630)
+ ti_dt_clocks_register(omap34xx_omap36xx_clks);
+
+ if (soc_type == OMAP3_SOC_OMAP3630)
+ ti_dt_clocks_register(omap36xx_clks);
+
+ omap2_clk_disable_autoidle_all();
+
+ omap2_clk_enable_init_clocks(enable_init_clks,
+ ARRAY_SIZE(enable_init_clks));
+
+ pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
+ (clk_get_rate(clk_get_sys(NULL, "osc_sys_ck")) / 1000000),
+ (clk_get_rate(clk_get_sys(NULL, "osc_sys_ck")) / 100000) % 10,
+ (clk_get_rate(clk_get_sys(NULL, "core_ck")) / 1000000),
+ (clk_get_rate(clk_get_sys(NULL, "arm_fck")) / 1000000));
+
+ if (soc_type != OMAP3_SOC_TI81XX && soc_type != OMAP3_SOC_OMAP3430_ES1)
+ omap3_clk_lock_dpll5();
+
+ return 0;
+}
+
+int __init omap3430_clk_init(void)
+{
+ return omap3xxx_clk_init(OMAP3_SOC_OMAP3430_ES2_PLUS);
+}
+
+int __init omap3630_clk_init(void)
+{
+ return omap3xxx_clk_init(OMAP3_SOC_OMAP3630);
+}
+
+int __init am35xx_clk_init(void)
+{
+ return omap3xxx_clk_init(OMAP3_SOC_AM35XX);
+}
+
+int __init ti81xx_clk_init(void)
+{
+ return omap3xxx_clk_init(OMAP3_SOC_TI81XX);
+}
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 88d7497..bf8beff 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -214,12 +214,17 @@ int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
int omap2_dflt_clk_enable(struct clk_hw *hw);
void omap2_dflt_clk_disable(struct clk_hw *hw);
int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
+void omap3_clk_lock_dpll5(void);
void ti_dt_clocks_register(struct ti_dt_clk *oclks);
void of_ti_autoidle_setup(struct device_node *node);
struct clk_div_table *ti_clk_get_div_table(struct device_node *node);
+int omap3430_clk_init(void);
+int omap3630_clk_init(void);
+int am35xx_clk_init(void);
+int ti81xx_clk_init(void);
int omap4xxx_clk_init(void);
int omap5xxx_clk_init(void);
int dra7xx_clk_init(void);
--
1.7.9.5
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^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 31/36] CLK: TI: add omap3 clock init file
@ 2013-09-25 8:48 ` Tero Kristo
0 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-arm-kernel
clk-3xxx.c now contains the clock init functionality for omap3, including
DT clock registration and adding of static clkdev entries.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/mach-omap2/clock3xxx.h | 1 -
drivers/clk/ti/Makefile | 2 +-
drivers/clk/ti/clk-3xxx.c | 402 +++++++++++++++++++++++++++++++++++++++
include/linux/clk/ti.h | 5 +
4 files changed, 408 insertions(+), 2 deletions(-)
create mode 100644 drivers/clk/ti/clk-3xxx.c
diff --git a/arch/arm/mach-omap2/clock3xxx.h b/arch/arm/mach-omap2/clock3xxx.h
index dab90e2..78d9f56 100644
--- a/arch/arm/mach-omap2/clock3xxx.h
+++ b/arch/arm/mach-omap2/clock3xxx.h
@@ -11,7 +11,6 @@
int omap3xxx_clk_init(void);
int omap3_core_dpll_m2_set_rate(struct clk_hw *clk, unsigned long rate,
unsigned long parent_rate);
-void omap3_clk_lock_dpll5(void);
extern struct clk *sdrc_ick_p;
extern struct clk *arm_fck_p;
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 1ecb1a4..df226bc 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -3,7 +3,7 @@ obj-y += clk.o dpll.o autoidle.o divider.o \
fixed-factor.o gate.o clockdomain.o \
mux-gate.o mux.o apll.o
obj-$(CONFIG_SOC_AM33XX) += clk-33xx.o
-obj-$(CONFIG_ARCH_OMAP3) += interface.o
+obj-$(CONFIG_ARCH_OMAP3) += interface.o clk-3xxx.o
obj-$(CONFIG_ARCH_OMAP4) += clk-44xx.o
obj-$(CONFIG_SOC_OMAP5) += clk-54xx.o
obj-$(CONFIG_SOC_DRA7XX) += clk-7xx.o
diff --git a/drivers/clk/ti/clk-3xxx.c b/drivers/clk/ti/clk-3xxx.c
new file mode 100644
index 0000000..394324b
--- /dev/null
+++ b/drivers/clk/ti/clk-3xxx.c
@@ -0,0 +1,402 @@
+/*
+ * OMAP3 Clock init
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc
+ * Tero Kristo (t-kristo at ti.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/clk-provider.h>
+#include <linux/clk/ti.h>
+
+
+static struct ti_dt_clk omap3xxx_clks[] = {
+ DT_CLK(NULL, "apb_pclk", "dummy_apb_pclk"),
+ DT_CLK(NULL, "omap_32k_fck", "omap_32k_fck"),
+ DT_CLK(NULL, "virt_12m_ck", "virt_12m_ck"),
+ DT_CLK(NULL, "virt_13m_ck", "virt_13m_ck"),
+ DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
+ DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
+ DT_CLK(NULL, "virt_38_4m_ck", "virt_38_4m_ck"),
+ DT_CLK(NULL, "osc_sys_ck", "osc_sys_ck"),
+ DT_CLK("twl", "fck", "osc_sys_ck"),
+ DT_CLK(NULL, "sys_ck", "sys_ck"),
+ DT_CLK(NULL, "omap_96m_alwon_fck", "omap_96m_alwon_fck"),
+ DT_CLK("etb", "emu_core_alwon_ck", "emu_core_alwon_ck"),
+ DT_CLK(NULL, "sys_altclk", "sys_altclk"),
+ DT_CLK(NULL, "mcbsp_clks", "mcbsp_clks"),
+ DT_CLK(NULL, "sys_clkout1", "sys_clkout1"),
+ DT_CLK(NULL, "dpll1_ck", "dpll1_ck"),
+ DT_CLK(NULL, "dpll1_x2_ck", "dpll1_x2_ck"),
+ DT_CLK(NULL, "dpll1_x2m2_ck", "dpll1_x2m2_ck"),
+ DT_CLK(NULL, "dpll3_ck", "dpll3_ck"),
+ DT_CLK(NULL, "core_ck", "core_ck"),
+ DT_CLK(NULL, "dpll3_x2_ck", "dpll3_x2_ck"),
+ DT_CLK(NULL, "dpll3_m2_ck", "dpll3_m2_ck"),
+ DT_CLK(NULL, "dpll3_m2x2_ck", "dpll3_m2x2_ck"),
+ DT_CLK(NULL, "dpll3_m3_ck", "dpll3_m3_ck"),
+ DT_CLK(NULL, "dpll3_m3x2_ck", "dpll3_m3x2_ck"),
+ DT_CLK(NULL, "dpll4_ck", "dpll4_ck"),
+ DT_CLK(NULL, "dpll4_x2_ck", "dpll4_x2_ck"),
+ DT_CLK(NULL, "omap_96m_fck", "omap_96m_fck"),
+ DT_CLK(NULL, "cm_96m_fck", "cm_96m_fck"),
+ DT_CLK(NULL, "omap_54m_fck", "omap_54m_fck"),
+ DT_CLK(NULL, "omap_48m_fck", "omap_48m_fck"),
+ DT_CLK(NULL, "omap_12m_fck", "omap_12m_fck"),
+ DT_CLK(NULL, "dpll4_m2_ck", "dpll4_m2_ck"),
+ DT_CLK(NULL, "dpll4_m2x2_ck", "dpll4_m2x2_ck"),
+ DT_CLK(NULL, "dpll4_m3_ck", "dpll4_m3_ck"),
+ DT_CLK(NULL, "dpll4_m3x2_ck", "dpll4_m3x2_ck"),
+ DT_CLK(NULL, "dpll4_m4_ck", "dpll4_m4_ck"),
+ DT_CLK(NULL, "dpll4_m4x2_ck", "dpll4_m4x2_ck"),
+ DT_CLK(NULL, "dpll4_m5_ck", "dpll4_m5_ck"),
+ DT_CLK(NULL, "dpll4_m5x2_ck", "dpll4_m5x2_ck"),
+ DT_CLK(NULL, "dpll4_m6_ck", "dpll4_m6_ck"),
+ DT_CLK(NULL, "dpll4_m6x2_ck", "dpll4_m6x2_ck"),
+ DT_CLK("etb", "emu_per_alwon_ck", "emu_per_alwon_ck"),
+ DT_CLK(NULL, "clkout2_src_ck", "clkout2_src_ck"),
+ DT_CLK(NULL, "sys_clkout2", "sys_clkout2"),
+ DT_CLK(NULL, "corex2_fck", "corex2_fck"),
+ DT_CLK(NULL, "dpll1_fck", "dpll1_fck"),
+ DT_CLK(NULL, "mpu_ck", "mpu_ck"),
+ DT_CLK(NULL, "arm_fck", "arm_fck"),
+ DT_CLK("etb", "emu_mpu_alwon_ck", "emu_mpu_alwon_ck"),
+ DT_CLK(NULL, "l3_ick", "l3_ick"),
+ DT_CLK(NULL, "l4_ick", "l4_ick"),
+ DT_CLK(NULL, "rm_ick", "rm_ick"),
+ DT_CLK(NULL, "gpt10_fck", "gpt10_fck"),
+ DT_CLK(NULL, "gpt11_fck", "gpt11_fck"),
+ DT_CLK(NULL, "core_96m_fck", "core_96m_fck"),
+ DT_CLK(NULL, "mmchs2_fck", "mmchs2_fck"),
+ DT_CLK(NULL, "mmchs1_fck", "mmchs1_fck"),
+ DT_CLK(NULL, "i2c3_fck", "i2c3_fck"),
+ DT_CLK(NULL, "i2c2_fck", "i2c2_fck"),
+ DT_CLK(NULL, "i2c1_fck", "i2c1_fck"),
+ DT_CLK(NULL, "mcbsp5_fck", "mcbsp5_fck"),
+ DT_CLK(NULL, "mcbsp1_fck", "mcbsp1_fck"),
+ DT_CLK(NULL, "core_48m_fck", "core_48m_fck"),
+ DT_CLK(NULL, "mcspi4_fck", "mcspi4_fck"),
+ DT_CLK(NULL, "mcspi3_fck", "mcspi3_fck"),
+ DT_CLK(NULL, "mcspi2_fck", "mcspi2_fck"),
+ DT_CLK(NULL, "mcspi1_fck", "mcspi1_fck"),
+ DT_CLK(NULL, "uart2_fck", "uart2_fck"),
+ DT_CLK(NULL, "uart1_fck", "uart1_fck"),
+ DT_CLK(NULL, "core_12m_fck", "core_12m_fck"),
+ DT_CLK("omap_hdq.0", "fck", "hdq_fck"),
+ DT_CLK(NULL, "hdq_fck", "hdq_fck"),
+ DT_CLK(NULL, "core_l3_ick", "core_l3_ick"),
+ DT_CLK(NULL, "sdrc_ick", "sdrc_ick"),
+ DT_CLK(NULL, "gpmc_fck", "gpmc_fck"),
+ DT_CLK(NULL, "core_l4_ick", "core_l4_ick"),
+ DT_CLK("omap_hsmmc.1", "ick", "mmchs2_ick"),
+ DT_CLK("omap_hsmmc.0", "ick", "mmchs1_ick"),
+ DT_CLK(NULL, "mmchs2_ick", "mmchs2_ick"),
+ DT_CLK(NULL, "mmchs1_ick", "mmchs1_ick"),
+ DT_CLK("omap_hdq.0", "ick", "hdq_ick"),
+ DT_CLK(NULL, "hdq_ick", "hdq_ick"),
+ DT_CLK("omap2_mcspi.4", "ick", "mcspi4_ick"),
+ DT_CLK("omap2_mcspi.3", "ick", "mcspi3_ick"),
+ DT_CLK("omap2_mcspi.2", "ick", "mcspi2_ick"),
+ DT_CLK("omap2_mcspi.1", "ick", "mcspi1_ick"),
+ DT_CLK(NULL, "mcspi4_ick", "mcspi4_ick"),
+ DT_CLK(NULL, "mcspi3_ick", "mcspi3_ick"),
+ DT_CLK(NULL, "mcspi2_ick", "mcspi2_ick"),
+ DT_CLK(NULL, "mcspi1_ick", "mcspi1_ick"),
+ DT_CLK("omap_i2c.3", "ick", "i2c3_ick"),
+ DT_CLK("omap_i2c.2", "ick", "i2c2_ick"),
+ DT_CLK("omap_i2c.1", "ick", "i2c1_ick"),
+ DT_CLK(NULL, "i2c3_ick", "i2c3_ick"),
+ DT_CLK(NULL, "i2c2_ick", "i2c2_ick"),
+ DT_CLK(NULL, "i2c1_ick", "i2c1_ick"),
+ DT_CLK(NULL, "uart2_ick", "uart2_ick"),
+ DT_CLK(NULL, "uart1_ick", "uart1_ick"),
+ DT_CLK(NULL, "gpt11_ick", "gpt11_ick"),
+ DT_CLK(NULL, "gpt10_ick", "gpt10_ick"),
+ DT_CLK("omap-mcbsp.5", "ick", "mcbsp5_ick"),
+ DT_CLK("omap-mcbsp.1", "ick", "mcbsp1_ick"),
+ DT_CLK(NULL, "mcbsp5_ick", "mcbsp5_ick"),
+ DT_CLK(NULL, "mcbsp1_ick", "mcbsp1_ick"),
+ DT_CLK(NULL, "omapctrl_ick", "omapctrl_ick"),
+ DT_CLK(NULL, "dss_tv_fck", "dss_tv_fck"),
+ DT_CLK(NULL, "dss_96m_fck", "dss_96m_fck"),
+ DT_CLK(NULL, "dss2_alwon_fck", "dss2_alwon_fck"),
+ DT_CLK(NULL, "utmi_p1_gfclk", "dummy_ck"),
+ DT_CLK(NULL, "utmi_p2_gfclk", "dummy_ck"),
+ DT_CLK(NULL, "xclk60mhsp1_ck", "dummy_ck"),
+ DT_CLK(NULL, "xclk60mhsp2_ck", "dummy_ck"),
+ DT_CLK(NULL, "init_60m_fclk", "dummy_ck"),
+ DT_CLK(NULL, "gpt1_fck", "gpt1_fck"),
+ DT_CLK(NULL, "aes2_ick", "aes2_ick"),
+ DT_CLK(NULL, "wkup_32k_fck", "wkup_32k_fck"),
+ DT_CLK(NULL, "gpio1_dbck", "gpio1_dbck"),
+ DT_CLK(NULL, "sha12_ick", "sha12_ick"),
+ DT_CLK(NULL, "wdt2_fck", "wdt2_fck"),
+ DT_CLK("omap_wdt", "ick", "wdt2_ick"),
+ DT_CLK(NULL, "wdt2_ick", "wdt2_ick"),
+ DT_CLK(NULL, "wdt1_ick", "wdt1_ick"),
+ DT_CLK(NULL, "gpio1_ick", "gpio1_ick"),
+ DT_CLK(NULL, "omap_32ksync_ick", "omap_32ksync_ick"),
+ DT_CLK(NULL, "gpt12_ick", "gpt12_ick"),
+ DT_CLK(NULL, "gpt1_ick", "gpt1_ick"),
+ DT_CLK(NULL, "per_96m_fck", "per_96m_fck"),
+ DT_CLK(NULL, "per_48m_fck", "per_48m_fck"),
+ DT_CLK(NULL, "uart3_fck", "uart3_fck"),
+ DT_CLK(NULL, "gpt2_fck", "gpt2_fck"),
+ DT_CLK(NULL, "gpt3_fck", "gpt3_fck"),
+ DT_CLK(NULL, "gpt4_fck", "gpt4_fck"),
+ DT_CLK(NULL, "gpt5_fck", "gpt5_fck"),
+ DT_CLK(NULL, "gpt6_fck", "gpt6_fck"),
+ DT_CLK(NULL, "gpt7_fck", "gpt7_fck"),
+ DT_CLK(NULL, "gpt8_fck", "gpt8_fck"),
+ DT_CLK(NULL, "gpt9_fck", "gpt9_fck"),
+ DT_CLK(NULL, "per_32k_alwon_fck", "per_32k_alwon_fck"),
+ DT_CLK(NULL, "gpio6_dbck", "gpio6_dbck"),
+ DT_CLK(NULL, "gpio5_dbck", "gpio5_dbck"),
+ DT_CLK(NULL, "gpio4_dbck", "gpio4_dbck"),
+ DT_CLK(NULL, "gpio3_dbck", "gpio3_dbck"),
+ DT_CLK(NULL, "gpio2_dbck", "gpio2_dbck"),
+ DT_CLK(NULL, "wdt3_fck", "wdt3_fck"),
+ DT_CLK(NULL, "per_l4_ick", "per_l4_ick"),
+ DT_CLK(NULL, "gpio6_ick", "gpio6_ick"),
+ DT_CLK(NULL, "gpio5_ick", "gpio5_ick"),
+ DT_CLK(NULL, "gpio4_ick", "gpio4_ick"),
+ DT_CLK(NULL, "gpio3_ick", "gpio3_ick"),
+ DT_CLK(NULL, "gpio2_ick", "gpio2_ick"),
+ DT_CLK(NULL, "wdt3_ick", "wdt3_ick"),
+ DT_CLK(NULL, "uart3_ick", "uart3_ick"),
+ DT_CLK(NULL, "uart4_ick", "uart4_ick"),
+ DT_CLK(NULL, "gpt9_ick", "gpt9_ick"),
+ DT_CLK(NULL, "gpt8_ick", "gpt8_ick"),
+ DT_CLK(NULL, "gpt7_ick", "gpt7_ick"),
+ DT_CLK(NULL, "gpt6_ick", "gpt6_ick"),
+ DT_CLK(NULL, "gpt5_ick", "gpt5_ick"),
+ DT_CLK(NULL, "gpt4_ick", "gpt4_ick"),
+ DT_CLK(NULL, "gpt3_ick", "gpt3_ick"),
+ DT_CLK(NULL, "gpt2_ick", "gpt2_ick"),
+ DT_CLK("omap-mcbsp.2", "ick", "mcbsp2_ick"),
+ DT_CLK("omap-mcbsp.3", "ick", "mcbsp3_ick"),
+ DT_CLK("omap-mcbsp.4", "ick", "mcbsp4_ick"),
+ DT_CLK(NULL, "mcbsp4_ick", "mcbsp2_ick"),
+ DT_CLK(NULL, "mcbsp3_ick", "mcbsp3_ick"),
+ DT_CLK(NULL, "mcbsp2_ick", "mcbsp4_ick"),
+ DT_CLK(NULL, "mcbsp2_fck", "mcbsp2_fck"),
+ DT_CLK(NULL, "mcbsp3_fck", "mcbsp3_fck"),
+ DT_CLK(NULL, "mcbsp4_fck", "mcbsp4_fck"),
+ DT_CLK("etb", "emu_src_ck", "emu_src_ck"),
+ DT_CLK(NULL, "emu_src_ck", "emu_src_ck"),
+ DT_CLK(NULL, "pclk_fck", "pclk_fck"),
+ DT_CLK(NULL, "pclkx2_fck", "pclkx2_fck"),
+ DT_CLK(NULL, "atclk_fck", "atclk_fck"),
+ DT_CLK(NULL, "traceclk_src_fck", "traceclk_src_fck"),
+ DT_CLK(NULL, "traceclk_fck", "traceclk_fck"),
+ DT_CLK(NULL, "secure_32k_fck", "secure_32k_fck"),
+ DT_CLK(NULL, "gpt12_fck", "gpt12_fck"),
+ DT_CLK(NULL, "wdt1_fck", "wdt1_fck"),
+ DT_CLK(NULL, "timer_32k_ck", "omap_32k_fck"),
+ DT_CLK(NULL, "timer_sys_ck", "sys_ck"),
+ DT_CLK(NULL, "cpufreq_ck", "dpll1_ck"),
+ { .node_name = NULL },
+};
+
+static struct ti_dt_clk omap34xx_omap36xx_clks[] = {
+ DT_CLK(NULL, "aes1_ick", "aes1_ick"),
+ DT_CLK("omap_rng", "ick", "rng_ick"),
+ DT_CLK(NULL, "sha11_ick", "sha11_ick"),
+ DT_CLK(NULL, "des1_ick", "des1_ick"),
+ DT_CLK(NULL, "cam_mclk", "cam_mclk"),
+ DT_CLK(NULL, "cam_ick", "cam_ick"),
+ DT_CLK(NULL, "csi2_96m_fck", "csi2_96m_fck"),
+ DT_CLK(NULL, "security_l3_ick", "security_l3_ick"),
+ DT_CLK(NULL, "pka_ick", "pka_ick"),
+ DT_CLK(NULL, "icr_ick", "icr_ick"),
+ DT_CLK("omap-aes", "ick", "aes2_ick"),
+ DT_CLK("omap-sham", "ick", "sha12_ick"),
+ DT_CLK(NULL, "des2_ick", "des2_ick"),
+ DT_CLK(NULL, "mspro_ick", "mspro_ick"),
+ DT_CLK(NULL, "mailboxes_ick", "mailboxes_ick"),
+ DT_CLK(NULL, "ssi_l4_ick", "ssi_l4_ick"),
+ DT_CLK(NULL, "sr1_fck", "sr1_fck"),
+ DT_CLK(NULL, "sr2_fck", "sr2_fck"),
+ DT_CLK(NULL, "sr_l4_ick", "sr_l4_ick"),
+ DT_CLK(NULL, "security_l4_ick2", "security_l4_ick2"),
+ DT_CLK(NULL, "wkup_l4_ick", "wkup_l4_ick"),
+ DT_CLK(NULL, "dpll2_fck", "dpll2_fck"),
+ DT_CLK(NULL, "iva2_ck", "iva2_ck"),
+ DT_CLK(NULL, "modem_fck", "modem_fck"),
+ DT_CLK(NULL, "sad2d_ick", "sad2d_ick"),
+ DT_CLK(NULL, "mad2d_ick", "mad2d_ick"),
+ DT_CLK(NULL, "mspro_fck", "mspro_fck"),
+ DT_CLK(NULL, "dpll2_ck", "dpll2_ck"),
+ DT_CLK(NULL, "dpll2_m2_ck", "dpll2_m2_ck"),
+ { .node_name = NULL },
+};
+
+static struct ti_dt_clk omap36xx_omap3430es2plus_clks[] = {
+ DT_CLK(NULL, "ssi_ssr_fck", "ssi_ssr_fck_3430es2"),
+ DT_CLK(NULL, "ssi_sst_fck", "ssi_sst_fck_3430es2"),
+ DT_CLK("musb-omap2430", "ick", "hsotgusb_ick_3430es2"),
+ DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_3430es2"),
+ DT_CLK(NULL, "ssi_ick", "ssi_ick_3430es2"),
+ DT_CLK(NULL, "usim_fck", "usim_fck"),
+ DT_CLK(NULL, "usim_ick", "usim_ick"),
+ { .node_name = NULL },
+};
+
+static struct ti_dt_clk omap3430es1_clks[] = {
+ DT_CLK(NULL, "gfx_l3_ck", "gfx_l3_ck"),
+ DT_CLK(NULL, "gfx_l3_fck", "gfx_l3_fck"),
+ DT_CLK(NULL, "gfx_l3_ick", "gfx_l3_ick"),
+ DT_CLK(NULL, "gfx_cg1_ck", "gfx_cg1_ck"),
+ DT_CLK(NULL, "gfx_cg2_ck", "gfx_cg2_ck"),
+ DT_CLK(NULL, "d2d_26m_fck", "d2d_26m_fck"),
+ DT_CLK(NULL, "fshostusb_fck", "fshostusb_fck"),
+ DT_CLK(NULL, "ssi_ssr_fck", "ssi_ssr_fck_3430es1"),
+ DT_CLK(NULL, "ssi_sst_fck", "ssi_sst_fck_3430es1"),
+ DT_CLK("musb-omap2430", "ick", "hsotgusb_ick_3430es1"),
+ DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_3430es1"),
+ DT_CLK(NULL, "fac_ick", "fac_ick"),
+ DT_CLK(NULL, "ssi_ick", "ssi_ick_3430es1"),
+ DT_CLK(NULL, "usb_l4_ick", "usb_l4_ick"),
+ DT_CLK(NULL, "dss1_alwon_fck", "dss1_alwon_fck_3430es1"),
+ DT_CLK("omapdss_dss", "ick", "dss_ick_3430es1"),
+ DT_CLK(NULL, "dss_ick", "dss_ick_3430es1"),
+ { .node_name = NULL },
+};
+
+static struct ti_dt_clk omap36xx_am35xx_omap3430es2plus_clks[] = {
+ DT_CLK(NULL, "virt_16_8m_ck", "virt_16_8m_ck"),
+ DT_CLK(NULL, "dpll5_ck", "dpll5_ck"),
+ DT_CLK(NULL, "dpll5_m2_ck", "dpll5_m2_ck"),
+ DT_CLK(NULL, "sgx_fck", "sgx_fck"),
+ DT_CLK(NULL, "sgx_ick", "sgx_ick"),
+ DT_CLK(NULL, "cpefuse_fck", "cpefuse_fck"),
+ DT_CLK(NULL, "ts_fck", "ts_fck"),
+ DT_CLK(NULL, "usbtll_fck", "usbtll_fck"),
+ DT_CLK(NULL, "usbtll_ick", "usbtll_ick"),
+ DT_CLK("omap_hsmmc.2", "ick", "mmchs3_ick"),
+ DT_CLK(NULL, "mmchs3_ick", "mmchs3_ick"),
+ DT_CLK(NULL, "mmchs3_fck", "mmchs3_fck"),
+ DT_CLK(NULL, "dss1_alwon_fck", "dss1_alwon_fck_3430es2"),
+ DT_CLK("omapdss_dss", "ick", "dss_ick_3430es2"),
+ DT_CLK(NULL, "dss_ick", "dss_ick_3430es2"),
+ DT_CLK(NULL, "usbhost_120m_fck", "usbhost_120m_fck"),
+ DT_CLK(NULL, "usbhost_48m_fck", "usbhost_48m_fck"),
+ DT_CLK(NULL, "usbhost_ick", "usbhost_ick"),
+ { .node_name = NULL },
+};
+
+static struct ti_dt_clk am35xx_clks[] = {
+ DT_CLK(NULL, "ipss_ick", "ipss_ick"),
+ DT_CLK(NULL, "rmii_ck", "rmii_ck"),
+ DT_CLK(NULL, "pclk_ck", "pclk_ck"),
+ DT_CLK(NULL, "emac_ick", "emac_ick"),
+ DT_CLK(NULL, "emac_fck", "emac_fck"),
+ DT_CLK("davinci_emac.0", NULL, "emac_ick"),
+ DT_CLK("davinci_mdio.0", NULL, "emac_fck"),
+ DT_CLK("vpfe-capture", "master", "vpfe_ick"),
+ DT_CLK("vpfe-capture", "slave", "vpfe_fck"),
+ DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_am35xx"),
+ DT_CLK(NULL, "hsotgusb_fck", "hsotgusb_fck_am35xx"),
+ DT_CLK(NULL, "hecc_ck", "hecc_ck"),
+ DT_CLK(NULL, "uart4_ick", "uart4_ick_am35xx"),
+ DT_CLK(NULL, "uart4_fck", "uart4_fck_am35xx"),
+ { .node_name = NULL },
+};
+
+static struct ti_dt_clk omap36xx_clks[] = {
+ DT_CLK(NULL, "omap_192m_alwon_fck", "omap_192m_alwon_fck"),
+ DT_CLK(NULL, "uart4_fck", "uart4_fck"),
+ { .node_name = NULL },
+};
+
+static const char *enable_init_clks[] = {
+ "sdrc_ick",
+ "gpmc_fck",
+ "omapctrl_ick",
+};
+
+enum {
+ OMAP3_SOC_AM35XX,
+ OMAP3_SOC_OMAP3430_ES1,
+ OMAP3_SOC_OMAP3430_ES2_PLUS,
+ OMAP3_SOC_OMAP3630,
+ OMAP3_SOC_TI81XX,
+};
+
+static int __init omap3xxx_clk_init(int soc_type)
+{
+ of_clk_init(NULL);
+
+ if (soc_type == OMAP3_SOC_AM35XX || soc_type == OMAP3_SOC_OMAP3630 ||
+ soc_type == OMAP3_SOC_OMAP3430_ES1 ||
+ soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS)
+ ti_dt_clocks_register(omap3xxx_clks);
+
+ if (soc_type == OMAP3_SOC_AM35XX)
+ ti_dt_clocks_register(am35xx_clks);
+
+ if (soc_type == OMAP3_SOC_OMAP3630 || soc_type == OMAP3_SOC_AM35XX ||
+ soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS)
+ ti_dt_clocks_register(omap36xx_am35xx_omap3430es2plus_clks);
+
+ if (soc_type == OMAP3_SOC_OMAP3430_ES1)
+ ti_dt_clocks_register(omap3430es1_clks);
+
+ if (soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS ||
+ soc_type == OMAP3_SOC_OMAP3630)
+ ti_dt_clocks_register(omap36xx_omap3430es2plus_clks);
+
+ if (soc_type == OMAP3_SOC_OMAP3430_ES1 ||
+ soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS ||
+ soc_type == OMAP3_SOC_OMAP3630)
+ ti_dt_clocks_register(omap34xx_omap36xx_clks);
+
+ if (soc_type == OMAP3_SOC_OMAP3630)
+ ti_dt_clocks_register(omap36xx_clks);
+
+ omap2_clk_disable_autoidle_all();
+
+ omap2_clk_enable_init_clocks(enable_init_clks,
+ ARRAY_SIZE(enable_init_clks));
+
+ pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
+ (clk_get_rate(clk_get_sys(NULL, "osc_sys_ck")) / 1000000),
+ (clk_get_rate(clk_get_sys(NULL, "osc_sys_ck")) / 100000) % 10,
+ (clk_get_rate(clk_get_sys(NULL, "core_ck")) / 1000000),
+ (clk_get_rate(clk_get_sys(NULL, "arm_fck")) / 1000000));
+
+ if (soc_type != OMAP3_SOC_TI81XX && soc_type != OMAP3_SOC_OMAP3430_ES1)
+ omap3_clk_lock_dpll5();
+
+ return 0;
+}
+
+int __init omap3430_clk_init(void)
+{
+ return omap3xxx_clk_init(OMAP3_SOC_OMAP3430_ES2_PLUS);
+}
+
+int __init omap3630_clk_init(void)
+{
+ return omap3xxx_clk_init(OMAP3_SOC_OMAP3630);
+}
+
+int __init am35xx_clk_init(void)
+{
+ return omap3xxx_clk_init(OMAP3_SOC_AM35XX);
+}
+
+int __init ti81xx_clk_init(void)
+{
+ return omap3xxx_clk_init(OMAP3_SOC_TI81XX);
+}
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 88d7497..bf8beff 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -214,12 +214,17 @@ int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
int omap2_dflt_clk_enable(struct clk_hw *hw);
void omap2_dflt_clk_disable(struct clk_hw *hw);
int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
+void omap3_clk_lock_dpll5(void);
void ti_dt_clocks_register(struct ti_dt_clk *oclks);
void of_ti_autoidle_setup(struct device_node *node);
struct clk_div_table *ti_clk_get_div_table(struct device_node *node);
+int omap3430_clk_init(void);
+int omap3630_clk_init(void);
+int am35xx_clk_init(void);
+int ti81xx_clk_init(void);
int omap4xxx_clk_init(void);
int omap5xxx_clk_init(void);
int dra7xx_clk_init(void);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 32/36] ARM: dts: AM35xx: use DT clock data
2013-09-25 8:48 ` Tero Kristo
@ 2013-09-25 8:48 ` Tero Kristo
-1 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-omap, paul, tony, nm, rnayak, bcousson, mturquette
Cc: linux-arm-kernel, devicetree
AM35xx now uses the clock data from device tree. Most of the data is
shared with OMAP3xxx, but as there is some delta, a new base .dtsi
file is also created for the SoC.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/boot/dts/am3517-evm.dts | 2 +-
arch/arm/boot/dts/am3517.dtsi | 126 +++++++++++++++++++++++++++++++
arch/arm/boot/dts/am3517_mt_ventoux.dts | 2 +-
3 files changed, 128 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/boot/dts/am3517.dtsi
diff --git a/arch/arm/boot/dts/am3517-evm.dts b/arch/arm/boot/dts/am3517-evm.dts
index e99dfaf..9ff51d7 100644
--- a/arch/arm/boot/dts/am3517-evm.dts
+++ b/arch/arm/boot/dts/am3517-evm.dts
@@ -7,7 +7,7 @@
*/
/dts-v1/;
-#include "omap34xx.dtsi"
+#include "am3517.dtsi"
/ {
model = "TI AM3517 EVM (AM3517/05)";
diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi
new file mode 100644
index 0000000..6f6da91
--- /dev/null
+++ b/arch/arm/boot/dts/am3517.dtsi
@@ -0,0 +1,126 @@
+/*
+ * Device Tree Source for AM3517 SoC
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include "omap3.dtsi"
+
+/ {
+ cpus {
+ cpu@0 {
+ /* OMAP343x/OMAP35xx variants OPP1-5 */
+ operating-points = <
+ /* kHz uV */
+ 125000 975000
+ 250000 1075000
+ 500000 1200000
+ 550000 1270000
+ 600000 1350000
+ >;
+ clock-latency = <300000>; /* From legacy driver */
+ };
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ /include/ "am35xx-clocks.dtsi"
+ /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
+ };
+
+ clockdomains {
+ dss_clkdm: dss_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dss_tv_fck>, <&dss1_alwon_fck_3430es2>,
+ <&dss_96m_fck>, <&dss2_alwon_fck>,
+ <&dss_ick_3430es2>;
+ };
+
+ usbhost_clkdm: usbhost_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&usbhost_48m_fck>, <&usbhost_ick>,
+ <&usbhost_120m_fck>;
+ };
+
+ core_l4_clkdm: core_l4_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&mmchs1_ick>, <&mmchs2_ick>, <&mcspi4_fck>,
+ <&i2c3_fck>, <&mcspi2_ick>, <&uart2_ick>,
+ <&mcspi3_ick>, <&i2c1_fck>, <&sha12_ick>,
+ <&mcspi3_fck>, <&uart4_fck_am35xx>,
+ <&uart2_fck>, <&mmchs2_fck>, <&usbtll_fck>,
+ <&mmchs3_ick>, <&i2c2_ick>, <&i2c1_ick>,
+ <&hdq_fck>, <&ts_fck>, <&uart1_ick>,
+ <&usbtll_ick>, <&hdq_ick>, <&mcbsp5_ick>,
+ <&aes2_ick>, <&mcspi1_ick>,
+ <&uart4_ick_am35xx>, <&mmchs1_fck>,
+ <&i2c3_ick>, <&mcspi1_fck>, <&mmchs3_fck>,
+ <&mcspi4_ick>, <&omapctrl_ick>, <&mcbsp1_ick>,
+ <&mcspi2_fck>, <&gpt10_ick>, <&cpefuse_fck>,
+ <&i2c2_fck>, <&gpt11_ick>, <&uart1_fck>;
+ };
+
+ wkup_clkdm: wkup_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&wdt1_ick>, <&omap_32ksync_ick>, <&wdt2_fck>,
+ <&gpio1_ick>, <&gpt12_ick>, <&gpt1_ick>,
+ <&wdt2_ick>, <&gpio1_dbck>;
+ };
+
+ dpll4_clkdm: dpll4_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll4_ck>;
+ };
+
+ core_l3_clkdm: core_l3_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&sdrc_ick>, <&hsotgusb_fck_am35xx>,
+ <&hecc_ck>, <&hsotgusb_ick_am35xx>,
+ <&vpfe_ick>, <&emac_ick>, <&ipss_ick>;
+ };
+
+ per_clkdm: per_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&gpt2_ick>, <&uart3_fck>, <&gpio3_ick>,
+ <&mcbsp2_ick>, <&gpt6_ick>, <&gpio2_dbck>,
+ <&mcbsp4_ick>, <&gpio4_dbck>, <&gpt4_ick>,
+ <&gpio5_dbck>, <&mcbsp3_ick>, <&gpio3_dbck>,
+ <&gpt8_ick>, <&gpt5_ick>, <&gpio6_dbck>,
+ <&uart3_ick>, <&gpt7_ick>, <&gpio2_ick>,
+ <&gpio6_ick>, <&gpt9_ick>, <&gpt3_ick>,
+ <&gpio5_ick>, <&wdt3_fck>, <&gpio4_ick>,
+ <&wdt3_ick>, <&uart4_ick>;
+ };
+
+ emu_clkdm: emu_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&emu_src_ck>;
+ };
+
+ sgx_clkdm: sgx_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&sgx_ick>;
+ };
+
+ dpll3_clkdm: dpll3_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll3_ck>;
+ };
+
+ dpll5_clkdm: dpll5_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll5_ck>;
+ };
+
+ dpll1_clkdm: dpll1_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll1_ck>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/am3517_mt_ventoux.dts b/arch/arm/boot/dts/am3517_mt_ventoux.dts
index fdf5ce6..d00e934 100644
--- a/arch/arm/boot/dts/am3517_mt_ventoux.dts
+++ b/arch/arm/boot/dts/am3517_mt_ventoux.dts
@@ -7,7 +7,7 @@
*/
/dts-v1/;
-#include "omap34xx.dtsi"
+#include "am3517.dtsi"
/ {
model = "TeeJet Mt.Ventoux";
--
1.7.9.5
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 32/36] ARM: dts: AM35xx: use DT clock data
@ 2013-09-25 8:48 ` Tero Kristo
0 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-arm-kernel
AM35xx now uses the clock data from device tree. Most of the data is
shared with OMAP3xxx, but as there is some delta, a new base .dtsi
file is also created for the SoC.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/boot/dts/am3517-evm.dts | 2 +-
arch/arm/boot/dts/am3517.dtsi | 126 +++++++++++++++++++++++++++++++
arch/arm/boot/dts/am3517_mt_ventoux.dts | 2 +-
3 files changed, 128 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/boot/dts/am3517.dtsi
diff --git a/arch/arm/boot/dts/am3517-evm.dts b/arch/arm/boot/dts/am3517-evm.dts
index e99dfaf..9ff51d7 100644
--- a/arch/arm/boot/dts/am3517-evm.dts
+++ b/arch/arm/boot/dts/am3517-evm.dts
@@ -7,7 +7,7 @@
*/
/dts-v1/;
-#include "omap34xx.dtsi"
+#include "am3517.dtsi"
/ {
model = "TI AM3517 EVM (AM3517/05)";
diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi
new file mode 100644
index 0000000..6f6da91
--- /dev/null
+++ b/arch/arm/boot/dts/am3517.dtsi
@@ -0,0 +1,126 @@
+/*
+ * Device Tree Source for AM3517 SoC
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include "omap3.dtsi"
+
+/ {
+ cpus {
+ cpu at 0 {
+ /* OMAP343x/OMAP35xx variants OPP1-5 */
+ operating-points = <
+ /* kHz uV */
+ 125000 975000
+ 250000 1075000
+ 500000 1200000
+ 550000 1270000
+ 600000 1350000
+ >;
+ clock-latency = <300000>; /* From legacy driver */
+ };
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ /include/ "am35xx-clocks.dtsi"
+ /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
+ };
+
+ clockdomains {
+ dss_clkdm: dss_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dss_tv_fck>, <&dss1_alwon_fck_3430es2>,
+ <&dss_96m_fck>, <&dss2_alwon_fck>,
+ <&dss_ick_3430es2>;
+ };
+
+ usbhost_clkdm: usbhost_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&usbhost_48m_fck>, <&usbhost_ick>,
+ <&usbhost_120m_fck>;
+ };
+
+ core_l4_clkdm: core_l4_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&mmchs1_ick>, <&mmchs2_ick>, <&mcspi4_fck>,
+ <&i2c3_fck>, <&mcspi2_ick>, <&uart2_ick>,
+ <&mcspi3_ick>, <&i2c1_fck>, <&sha12_ick>,
+ <&mcspi3_fck>, <&uart4_fck_am35xx>,
+ <&uart2_fck>, <&mmchs2_fck>, <&usbtll_fck>,
+ <&mmchs3_ick>, <&i2c2_ick>, <&i2c1_ick>,
+ <&hdq_fck>, <&ts_fck>, <&uart1_ick>,
+ <&usbtll_ick>, <&hdq_ick>, <&mcbsp5_ick>,
+ <&aes2_ick>, <&mcspi1_ick>,
+ <&uart4_ick_am35xx>, <&mmchs1_fck>,
+ <&i2c3_ick>, <&mcspi1_fck>, <&mmchs3_fck>,
+ <&mcspi4_ick>, <&omapctrl_ick>, <&mcbsp1_ick>,
+ <&mcspi2_fck>, <&gpt10_ick>, <&cpefuse_fck>,
+ <&i2c2_fck>, <&gpt11_ick>, <&uart1_fck>;
+ };
+
+ wkup_clkdm: wkup_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&wdt1_ick>, <&omap_32ksync_ick>, <&wdt2_fck>,
+ <&gpio1_ick>, <&gpt12_ick>, <&gpt1_ick>,
+ <&wdt2_ick>, <&gpio1_dbck>;
+ };
+
+ dpll4_clkdm: dpll4_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll4_ck>;
+ };
+
+ core_l3_clkdm: core_l3_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&sdrc_ick>, <&hsotgusb_fck_am35xx>,
+ <&hecc_ck>, <&hsotgusb_ick_am35xx>,
+ <&vpfe_ick>, <&emac_ick>, <&ipss_ick>;
+ };
+
+ per_clkdm: per_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&gpt2_ick>, <&uart3_fck>, <&gpio3_ick>,
+ <&mcbsp2_ick>, <&gpt6_ick>, <&gpio2_dbck>,
+ <&mcbsp4_ick>, <&gpio4_dbck>, <&gpt4_ick>,
+ <&gpio5_dbck>, <&mcbsp3_ick>, <&gpio3_dbck>,
+ <&gpt8_ick>, <&gpt5_ick>, <&gpio6_dbck>,
+ <&uart3_ick>, <&gpt7_ick>, <&gpio2_ick>,
+ <&gpio6_ick>, <&gpt9_ick>, <&gpt3_ick>,
+ <&gpio5_ick>, <&wdt3_fck>, <&gpio4_ick>,
+ <&wdt3_ick>, <&uart4_ick>;
+ };
+
+ emu_clkdm: emu_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&emu_src_ck>;
+ };
+
+ sgx_clkdm: sgx_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&sgx_ick>;
+ };
+
+ dpll3_clkdm: dpll3_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll3_ck>;
+ };
+
+ dpll5_clkdm: dpll5_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll5_ck>;
+ };
+
+ dpll1_clkdm: dpll1_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll1_ck>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/am3517_mt_ventoux.dts b/arch/arm/boot/dts/am3517_mt_ventoux.dts
index fdf5ce6..d00e934 100644
--- a/arch/arm/boot/dts/am3517_mt_ventoux.dts
+++ b/arch/arm/boot/dts/am3517_mt_ventoux.dts
@@ -7,7 +7,7 @@
*/
/dts-v1/;
-#include "omap34xx.dtsi"
+#include "am3517.dtsi"
/ {
model = "TeeJet Mt.Ventoux";
--
1.7.9.5
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 33/36] ARM: OMAP3: use DT clock init if DT data is available
2013-09-25 8:48 ` Tero Kristo
@ 2013-09-25 8:48 ` Tero Kristo
-1 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-omap, paul, tony, nm, rnayak, bcousson, mturquette
Cc: linux-arm-kernel, devicetree
OMAP3 platforms support both DT and non-DT boot at the moment, make
the clock init work according to the used setup.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/mach-omap2/clock3xxx.h | 4 ++++
arch/arm/mach-omap2/io.c | 13 ++++++++++++-
2 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap2/clock3xxx.h b/arch/arm/mach-omap2/clock3xxx.h
index 78d9f56..a5e2308 100644
--- a/arch/arm/mach-omap2/clock3xxx.h
+++ b/arch/arm/mach-omap2/clock3xxx.h
@@ -9,6 +9,10 @@
#define __ARCH_ARM_MACH_OMAP2_CLOCK3XXX_H
int omap3xxx_clk_init(void);
+int omap3430_clk_init(void);
+int omap3630_clk_init(void);
+int ti81xx_clk_init(void);
+int am35xx_clk_init(void);
int omap3_core_dpll_m2_set_rate(struct clk_hw *clk, unsigned long rate,
unsigned long parent_rate);
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 1f23182..315a148 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -488,21 +488,29 @@ void __init omap3_init_early(void)
void __init omap3430_init_early(void)
{
omap3_init_early();
+ if (of_have_populated_dt())
+ omap_clk_init = omap3430_clk_init;
}
void __init omap35xx_init_early(void)
{
omap3_init_early();
+ if (of_have_populated_dt())
+ omap_clk_init = omap3430_clk_init;
}
void __init omap3630_init_early(void)
{
omap3_init_early();
+ if (of_have_populated_dt())
+ omap_clk_init = omap3630_clk_init;
}
void __init am35xx_init_early(void)
{
omap3_init_early();
+ if (of_have_populated_dt())
+ omap_clk_init = am35xx_clk_init;
}
void __init ti81xx_init_early(void)
@@ -520,7 +528,10 @@ void __init ti81xx_init_early(void)
omap3xxx_clockdomains_init();
omap3xxx_hwmod_init();
omap_hwmod_init_postsetup();
- omap_clk_init = omap3xxx_clk_init;
+ if (of_have_populated_dt())
+ omap_clk_init = ti81xx_clk_init;
+ else
+ omap_clk_init = omap3xxx_clk_init;
}
void __init omap3_init_late(void)
--
1.7.9.5
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 33/36] ARM: OMAP3: use DT clock init if DT data is available
@ 2013-09-25 8:48 ` Tero Kristo
0 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-arm-kernel
OMAP3 platforms support both DT and non-DT boot at the moment, make
the clock init work according to the used setup.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/mach-omap2/clock3xxx.h | 4 ++++
arch/arm/mach-omap2/io.c | 13 ++++++++++++-
2 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap2/clock3xxx.h b/arch/arm/mach-omap2/clock3xxx.h
index 78d9f56..a5e2308 100644
--- a/arch/arm/mach-omap2/clock3xxx.h
+++ b/arch/arm/mach-omap2/clock3xxx.h
@@ -9,6 +9,10 @@
#define __ARCH_ARM_MACH_OMAP2_CLOCK3XXX_H
int omap3xxx_clk_init(void);
+int omap3430_clk_init(void);
+int omap3630_clk_init(void);
+int ti81xx_clk_init(void);
+int am35xx_clk_init(void);
int omap3_core_dpll_m2_set_rate(struct clk_hw *clk, unsigned long rate,
unsigned long parent_rate);
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 1f23182..315a148 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -488,21 +488,29 @@ void __init omap3_init_early(void)
void __init omap3430_init_early(void)
{
omap3_init_early();
+ if (of_have_populated_dt())
+ omap_clk_init = omap3430_clk_init;
}
void __init omap35xx_init_early(void)
{
omap3_init_early();
+ if (of_have_populated_dt())
+ omap_clk_init = omap3430_clk_init;
}
void __init omap3630_init_early(void)
{
omap3_init_early();
+ if (of_have_populated_dt())
+ omap_clk_init = omap3630_clk_init;
}
void __init am35xx_init_early(void)
{
omap3_init_early();
+ if (of_have_populated_dt())
+ omap_clk_init = am35xx_clk_init;
}
void __init ti81xx_init_early(void)
@@ -520,7 +528,10 @@ void __init ti81xx_init_early(void)
omap3xxx_clockdomains_init();
omap3xxx_hwmod_init();
omap_hwmod_init_postsetup();
- omap_clk_init = omap3xxx_clk_init;
+ if (of_have_populated_dt())
+ omap_clk_init = ti81xx_clk_init;
+ else
+ omap_clk_init = omap3xxx_clk_init;
}
void __init omap3_init_late(void)
--
1.7.9.5
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 34/36] ARM: dts: am43xx clock data
2013-09-25 8:48 ` Tero Kristo
@ 2013-09-25 8:48 ` Tero Kristo
-1 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-omap-u79uwXL29TY76Z2rM5mHXA, paul-DWxLp4Yu+b8AvxtiuMwx3w,
tony-4v6yS6AI5VpBDgjK7y7TUQ, nm-l0cyMroinI0, rnayak-l0cyMroinI0,
bcousson-rdvid1DuHRBWk0Htik3J/w,
mturquette-QSEj5FYQhm4dnm+yROfE0A
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
This patch creates a unique node for each clock in the AM43xx power,
reset and clock manager (PRCM).
Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
arch/arm/boot/dts/am43xx-clocks.dtsi | 656 ++++++++++++++++++++++++++++++++++
1 file changed, 656 insertions(+)
create mode 100644 arch/arm/boot/dts/am43xx-clocks.dtsi
diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi
new file mode 100644
index 0000000..09eaa2a
--- /dev/null
+++ b/arch/arm/boot/dts/am43xx-clocks.dtsi
@@ -0,0 +1,656 @@
+/*
+ * Device Tree Source for AM43xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+clk_32768_ck: clk_32768_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+};
+
+clk_rc32k_ck: clk_rc32k_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+};
+
+virt_19200000_ck: virt_19200000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <19200000>;
+};
+
+virt_24000000_ck: virt_24000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+};
+
+virt_25000000_ck: virt_25000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <25000000>;
+};
+
+virt_26000000_ck: virt_26000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <26000000>;
+};
+
+sys_clkin_ck: sys_clkin_ck@44e10040 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
+ ti,bit-shift = <22>;
+ reg = <0x44e10040 0x4>;
+};
+
+tclkin_ck: tclkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <26000000>;
+};
+
+dpll_core_ck: dpll_core_ck@44df2d20 {
+ #clock-cells = <0>;
+ compatible = "ti,am3-dpll-core-lock";
+ clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+ reg = <0x44df2d20 0x4>, <0x44df2d24 0x4>, <0x44df2d2c 0x4>;
+ ti,low-power-bypass;
+ ti,lock;
+};
+
+dpll_core_x2_ck: dpll_core_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,am3-dpll-x2-clock";
+ clocks = <&dpll_core_ck>;
+};
+
+dpll_core_m4_ck: dpll_core_m4_ck@44df2d38 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x44df2d38 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_core_m5_ck: dpll_core_m5_ck@44df2d3c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x44df2d3c 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_core_m6_ck: dpll_core_m6_ck@44df2d40 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x44df2d40 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_mpu_ck: dpll_mpu_ck@44df2d60 {
+ #clock-cells = <0>;
+ compatible = "ti,am3-dpll-clock";
+ clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+ reg = <0x44df2d60 0x4>, <0x44df2d64 0x4>, <0x44df2d6c 0x4>;
+};
+
+dpll_mpu_m2_ck: dpll_mpu_m2_ck@44df2d70 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_mpu_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x44df2d70 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_ddr_ck: dpll_ddr_ck@44df2da0 {
+ #clock-cells = <0>;
+ compatible = "ti,am3-dpll-clock";
+ clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+ reg = <0x44df2da0 0x4>, <0x44df2da4 0x4>, <0x44df2dac 0x4>;
+};
+
+dpll_ddr_m2_ck: dpll_ddr_m2_ck@44df2db0 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_ddr_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x44df2db0 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_disp_ck: dpll_disp_ck@44df2e20 {
+ #clock-cells = <0>;
+ compatible = "ti,am3-dpll-clock";
+ clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+ reg = <0x44df2e20 0x4>, <0x44df2e24 0x4>, <0x44df2e2c 0x4>;
+};
+
+dpll_disp_m2_ck: dpll_disp_m2_ck@44df2e30 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_disp_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x44df2e30 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_per_ck: dpll_per_ck@44df2de0 {
+ #clock-cells = <0>;
+ compatible = "ti,am3-dpll-j-type-clock";
+ clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+ reg = <0x44df2de0 0x4>, <0x44df2de4 0x4>, <0x44df2dec 0x4>;
+};
+
+dpll_per_m2_ck: dpll_per_m2_ck@44df2df0 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_ck>;
+ ti,max-div = <127>;
+ ti,autoidle-shift = <8>;
+ reg = <0x44df2df0 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+};
+
+dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+};
+
+adc_tsc_fck: adc_tsc_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+clk_24mhz: clk_24mhz {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <8>;
+};
+
+clkdiv32k_ck: clkdiv32k_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&clk_24mhz>;
+ clock-mult = <1>;
+ clock-div = <732>;
+};
+
+clkdiv32k_ick: clkdiv32k_ick@44df2a38 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&clkdiv32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x44df2a38 0x4>;
+};
+
+dcan0_fck: dcan0_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dcan1_fck: dcan1_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+sysclk_div: sysclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m4_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+pruss_ocp_gclk: pruss_ocp_gclk@44df4248 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sysclk_div>, <&dpll_disp_m2_ck>;
+ reg = <0x44df4248 0x4>;
+};
+
+mcasp0_fck: mcasp0_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+mcasp1_fck: mcasp1_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+smartreflex0_fck: smartreflex0_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+smartreflex1_fck: smartreflex1_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+sha0_fck: sha0_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+aes0_fck: aes0_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+clk_32k_tpm_ck: clk_32k_tpm_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+};
+
+timer1_fck: timer1_fck@44df4200 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>;
+ reg = <0x44df4200 0x4>;
+};
+
+timer2_fck: timer2_fck@44df4204 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ reg = <0x44df4204 0x4>;
+};
+
+timer3_fck: timer3_fck@44df4208 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ reg = <0x44df4208 0x4>;
+};
+
+timer4_fck: timer4_fck@44df420c {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ reg = <0x44df420c 0x4>;
+};
+
+timer5_fck: timer5_fck@44df4210 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ reg = <0x44df4210 0x4>;
+};
+
+timer6_fck: timer6_fck@44df4214 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ reg = <0x44df4214 0x4>;
+};
+
+timer7_fck: timer7_fck@44df4218 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ reg = <0x44df4218 0x4>;
+};
+
+wdt1_fck: wdt1_fck@44df422c {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
+ reg = <0x44df422c 0x4>;
+};
+
+l3_gclk: l3_gclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m4_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sysclk_div>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+l4hs_gclk: l4hs_gclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m4_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+l3s_gclk: l3s_gclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m4_div2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+l4ls_gclk: l4ls_gclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m4_div2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+cpsw_125mhz_gclk: cpsw_125mhz_gclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m5_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@44df4238 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sysclk_div>, <&dpll_core_m5_ck>, <&dpll_disp_m2_ck>;
+ reg = <0x44df4238 0x4>;
+};
+
+clk_32k_mosc_ck: clk_32k_mosc_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+};
+
+gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@44df4240 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>, <&clk_32k_mosc_ck>, <&clk_32k_tpm_ck>;
+ reg = <0x44df4240 0x4>;
+};
+
+gpio0_dbclk: gpio0_dbclk@44df2b68 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&gpio0_dbclk_mux_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x44df2b68 0x4>;
+};
+
+gpio1_dbclk: gpio1_dbclk@44df8c78 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&clkdiv32k_ick>;
+ ti,bit-shift = <8>;
+ reg = <0x44df8c78 0x4>;
+};
+
+gpio2_dbclk: gpio2_dbclk@44df8c80 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&clkdiv32k_ick>;
+ ti,bit-shift = <8>;
+ reg = <0x44df8c80 0x4>;
+};
+
+gpio3_dbclk: gpio3_dbclk@44df8c88 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&clkdiv32k_ick>;
+ ti,bit-shift = <8>;
+ reg = <0x44df8c88 0x4>;
+};
+
+gpio4_dbclk: gpio4_dbclk@44df8c90 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&clkdiv32k_ick>;
+ ti,bit-shift = <8>;
+ reg = <0x44df8c90 0x4>;
+};
+
+gpio5_dbclk: gpio5_dbclk@44df8c98 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&clkdiv32k_ick>;
+ ti,bit-shift = <8>;
+ reg = <0x44df8c98 0x4>;
+};
+
+mmc_clk: mmc_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@44df423c {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sysclk_div>, <&dpll_per_m2_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x44df423c 0x4>;
+};
+
+gfx_fck_div_ck: gfx_fck_div_ck@44df423c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&gfx_fclk_clksel_ck>;
+ reg = <0x44df423c 0x4>;
+ ti,max-div = <2>;
+};
+
+disp_clk: disp_clk@44df4244 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
+ reg = <0x44df4244 0x4>;
+};
+
+dpll_extdev_ck: dpll_extdev_ck@44df2e60 {
+ #clock-cells = <0>;
+ compatible = "ti,am3-dpll-clock";
+ clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+ reg = <0x44df2e60 0x4>, <0x44df2e64 0x4>, <0x44df2e6c 0x4>;
+};
+
+dpll_extdev_m2_ck: dpll_extdev_m2_ck@44df2e70 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_extdev_ck>;
+ ti,max-div = <127>;
+ ti,autoidle-shift = <8>;
+ reg = <0x44df2e70 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+mux_synctimer32k_ck: mux_synctimer32k_ck@44df4230 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>, <&clkdiv32k_ick>;
+ reg = <0x44df4230 0x4>;
+};
+
+synctimer_32kclk: synctimer_32kclk@44df2a30 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&mux_synctimer32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x44df2a30 0x4>;
+};
+
+timer8_fck: timer8_fck@44df421c {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
+ reg = <0x44df421c 0x4>;
+};
+
+timer9_fck: timer9_fck@44df4220 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
+ reg = <0x44df4220 0x4>;
+};
+
+timer10_fck: timer10_fck@44df4224 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
+ reg = <0x44df4224 0x4>;
+};
+
+timer11_fck: timer11_fck@44df4228 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
+ reg = <0x44df4228 0x4>;
+};
+
+cpsw_50m_clkdiv: cpsw_50m_clkdiv {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m5_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+cpsw_5m_clkdiv: cpsw_5m_clkdiv {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&cpsw_50m_clkdiv>;
+ clock-mult = <1>;
+ clock-div = <10>;
+};
+
+dpll_ddr_x2_ck: dpll_ddr_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,am3-dpll-x2-clock";
+ clocks = <&dpll_ddr_ck>;
+};
+
+dpll_ddr_m4_ck: dpll_ddr_m4_ck@44df2db8 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_ddr_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x44df2db8 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_per_clkdcoldo: dpll_per_clkdcoldo {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dll_aging_clk_div: dll_aging_clk_div@44df4250 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&sys_clkin_ck>;
+ reg = <0x44df4250 0x4>;
+ ti,dividers = <8>, <16>, <32>;
+};
+
+div_core_25m_ck: div_core_25m_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sysclk_div>;
+ clock-mult = <1>;
+ clock-div = <8>;
+};
+
+func_12m_clk: func_12m_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <16>;
+};
+
+vtp_clk_div: vtp_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+usbphy_32khz_clkmux: usbphy_32khz_clkmux@44df4260 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>;
+ reg = <0x44df4260 0x4>;
+};
--
1.7.9.5
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^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 34/36] ARM: dts: am43xx clock data
@ 2013-09-25 8:48 ` Tero Kristo
0 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-arm-kernel
This patch creates a unique node for each clock in the AM43xx power,
reset and clock manager (PRCM).
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/boot/dts/am43xx-clocks.dtsi | 656 ++++++++++++++++++++++++++++++++++
1 file changed, 656 insertions(+)
create mode 100644 arch/arm/boot/dts/am43xx-clocks.dtsi
diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi
new file mode 100644
index 0000000..09eaa2a
--- /dev/null
+++ b/arch/arm/boot/dts/am43xx-clocks.dtsi
@@ -0,0 +1,656 @@
+/*
+ * Device Tree Source for AM43xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+clk_32768_ck: clk_32768_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+};
+
+clk_rc32k_ck: clk_rc32k_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+};
+
+virt_19200000_ck: virt_19200000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <19200000>;
+};
+
+virt_24000000_ck: virt_24000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+};
+
+virt_25000000_ck: virt_25000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <25000000>;
+};
+
+virt_26000000_ck: virt_26000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <26000000>;
+};
+
+sys_clkin_ck: sys_clkin_ck at 44e10040 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
+ ti,bit-shift = <22>;
+ reg = <0x44e10040 0x4>;
+};
+
+tclkin_ck: tclkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <26000000>;
+};
+
+dpll_core_ck: dpll_core_ck at 44df2d20 {
+ #clock-cells = <0>;
+ compatible = "ti,am3-dpll-core-lock";
+ clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+ reg = <0x44df2d20 0x4>, <0x44df2d24 0x4>, <0x44df2d2c 0x4>;
+ ti,low-power-bypass;
+ ti,lock;
+};
+
+dpll_core_x2_ck: dpll_core_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,am3-dpll-x2-clock";
+ clocks = <&dpll_core_ck>;
+};
+
+dpll_core_m4_ck: dpll_core_m4_ck at 44df2d38 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x44df2d38 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_core_m5_ck: dpll_core_m5_ck at 44df2d3c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x44df2d3c 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_core_m6_ck: dpll_core_m6_ck at 44df2d40 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x44df2d40 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_mpu_ck: dpll_mpu_ck at 44df2d60 {
+ #clock-cells = <0>;
+ compatible = "ti,am3-dpll-clock";
+ clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+ reg = <0x44df2d60 0x4>, <0x44df2d64 0x4>, <0x44df2d6c 0x4>;
+};
+
+dpll_mpu_m2_ck: dpll_mpu_m2_ck at 44df2d70 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_mpu_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x44df2d70 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_ddr_ck: dpll_ddr_ck at 44df2da0 {
+ #clock-cells = <0>;
+ compatible = "ti,am3-dpll-clock";
+ clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+ reg = <0x44df2da0 0x4>, <0x44df2da4 0x4>, <0x44df2dac 0x4>;
+};
+
+dpll_ddr_m2_ck: dpll_ddr_m2_ck at 44df2db0 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_ddr_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x44df2db0 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_disp_ck: dpll_disp_ck at 44df2e20 {
+ #clock-cells = <0>;
+ compatible = "ti,am3-dpll-clock";
+ clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+ reg = <0x44df2e20 0x4>, <0x44df2e24 0x4>, <0x44df2e2c 0x4>;
+};
+
+dpll_disp_m2_ck: dpll_disp_m2_ck at 44df2e30 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_disp_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x44df2e30 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_per_ck: dpll_per_ck at 44df2de0 {
+ #clock-cells = <0>;
+ compatible = "ti,am3-dpll-j-type-clock";
+ clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+ reg = <0x44df2de0 0x4>, <0x44df2de4 0x4>, <0x44df2dec 0x4>;
+};
+
+dpll_per_m2_ck: dpll_per_m2_ck at 44df2df0 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_ck>;
+ ti,max-div = <127>;
+ ti,autoidle-shift = <8>;
+ reg = <0x44df2df0 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+};
+
+dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+};
+
+adc_tsc_fck: adc_tsc_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+clk_24mhz: clk_24mhz {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <8>;
+};
+
+clkdiv32k_ck: clkdiv32k_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&clk_24mhz>;
+ clock-mult = <1>;
+ clock-div = <732>;
+};
+
+clkdiv32k_ick: clkdiv32k_ick at 44df2a38 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&clkdiv32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x44df2a38 0x4>;
+};
+
+dcan0_fck: dcan0_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dcan1_fck: dcan1_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+sysclk_div: sysclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m4_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+pruss_ocp_gclk: pruss_ocp_gclk at 44df4248 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sysclk_div>, <&dpll_disp_m2_ck>;
+ reg = <0x44df4248 0x4>;
+};
+
+mcasp0_fck: mcasp0_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+mcasp1_fck: mcasp1_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+smartreflex0_fck: smartreflex0_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+smartreflex1_fck: smartreflex1_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+sha0_fck: sha0_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+aes0_fck: aes0_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+clk_32k_tpm_ck: clk_32k_tpm_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+};
+
+timer1_fck: timer1_fck at 44df4200 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>;
+ reg = <0x44df4200 0x4>;
+};
+
+timer2_fck: timer2_fck at 44df4204 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ reg = <0x44df4204 0x4>;
+};
+
+timer3_fck: timer3_fck at 44df4208 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ reg = <0x44df4208 0x4>;
+};
+
+timer4_fck: timer4_fck at 44df420c {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ reg = <0x44df420c 0x4>;
+};
+
+timer5_fck: timer5_fck at 44df4210 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ reg = <0x44df4210 0x4>;
+};
+
+timer6_fck: timer6_fck at 44df4214 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ reg = <0x44df4214 0x4>;
+};
+
+timer7_fck: timer7_fck at 44df4218 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ reg = <0x44df4218 0x4>;
+};
+
+wdt1_fck: wdt1_fck at 44df422c {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
+ reg = <0x44df422c 0x4>;
+};
+
+l3_gclk: l3_gclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m4_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sysclk_div>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+l4hs_gclk: l4hs_gclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m4_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+l3s_gclk: l3s_gclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m4_div2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+l4ls_gclk: l4ls_gclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m4_div2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+cpsw_125mhz_gclk: cpsw_125mhz_gclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m5_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+cpsw_cpts_rft_clk: cpsw_cpts_rft_clk at 44df4238 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sysclk_div>, <&dpll_core_m5_ck>, <&dpll_disp_m2_ck>;
+ reg = <0x44df4238 0x4>;
+};
+
+clk_32k_mosc_ck: clk_32k_mosc_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+};
+
+gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck at 44df4240 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>, <&clk_32k_mosc_ck>, <&clk_32k_tpm_ck>;
+ reg = <0x44df4240 0x4>;
+};
+
+gpio0_dbclk: gpio0_dbclk at 44df2b68 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&gpio0_dbclk_mux_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x44df2b68 0x4>;
+};
+
+gpio1_dbclk: gpio1_dbclk at 44df8c78 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&clkdiv32k_ick>;
+ ti,bit-shift = <8>;
+ reg = <0x44df8c78 0x4>;
+};
+
+gpio2_dbclk: gpio2_dbclk at 44df8c80 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&clkdiv32k_ick>;
+ ti,bit-shift = <8>;
+ reg = <0x44df8c80 0x4>;
+};
+
+gpio3_dbclk: gpio3_dbclk at 44df8c88 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&clkdiv32k_ick>;
+ ti,bit-shift = <8>;
+ reg = <0x44df8c88 0x4>;
+};
+
+gpio4_dbclk: gpio4_dbclk at 44df8c90 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&clkdiv32k_ick>;
+ ti,bit-shift = <8>;
+ reg = <0x44df8c90 0x4>;
+};
+
+gpio5_dbclk: gpio5_dbclk at 44df8c98 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&clkdiv32k_ick>;
+ ti,bit-shift = <8>;
+ reg = <0x44df8c98 0x4>;
+};
+
+mmc_clk: mmc_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+gfx_fclk_clksel_ck: gfx_fclk_clksel_ck at 44df423c {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sysclk_div>, <&dpll_per_m2_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x44df423c 0x4>;
+};
+
+gfx_fck_div_ck: gfx_fck_div_ck at 44df423c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&gfx_fclk_clksel_ck>;
+ reg = <0x44df423c 0x4>;
+ ti,max-div = <2>;
+};
+
+disp_clk: disp_clk at 44df4244 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
+ reg = <0x44df4244 0x4>;
+};
+
+dpll_extdev_ck: dpll_extdev_ck at 44df2e60 {
+ #clock-cells = <0>;
+ compatible = "ti,am3-dpll-clock";
+ clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+ reg = <0x44df2e60 0x4>, <0x44df2e64 0x4>, <0x44df2e6c 0x4>;
+};
+
+dpll_extdev_m2_ck: dpll_extdev_m2_ck at 44df2e70 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_extdev_ck>;
+ ti,max-div = <127>;
+ ti,autoidle-shift = <8>;
+ reg = <0x44df2e70 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+mux_synctimer32k_ck: mux_synctimer32k_ck at 44df4230 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>, <&clkdiv32k_ick>;
+ reg = <0x44df4230 0x4>;
+};
+
+synctimer_32kclk: synctimer_32kclk at 44df2a30 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&mux_synctimer32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x44df2a30 0x4>;
+};
+
+timer8_fck: timer8_fck at 44df421c {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
+ reg = <0x44df421c 0x4>;
+};
+
+timer9_fck: timer9_fck at 44df4220 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
+ reg = <0x44df4220 0x4>;
+};
+
+timer10_fck: timer10_fck at 44df4224 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
+ reg = <0x44df4224 0x4>;
+};
+
+timer11_fck: timer11_fck at 44df4228 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
+ reg = <0x44df4228 0x4>;
+};
+
+cpsw_50m_clkdiv: cpsw_50m_clkdiv {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m5_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+cpsw_5m_clkdiv: cpsw_5m_clkdiv {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&cpsw_50m_clkdiv>;
+ clock-mult = <1>;
+ clock-div = <10>;
+};
+
+dpll_ddr_x2_ck: dpll_ddr_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,am3-dpll-x2-clock";
+ clocks = <&dpll_ddr_ck>;
+};
+
+dpll_ddr_m4_ck: dpll_ddr_m4_ck at 44df2db8 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_ddr_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x44df2db8 0x4>;
+ ti,index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_per_clkdcoldo: dpll_per_clkdcoldo {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dll_aging_clk_div: dll_aging_clk_div at 44df4250 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&sys_clkin_ck>;
+ reg = <0x44df4250 0x4>;
+ ti,dividers = <8>, <16>, <32>;
+};
+
+div_core_25m_ck: div_core_25m_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sysclk_div>;
+ clock-mult = <1>;
+ clock-div = <8>;
+};
+
+func_12m_clk: func_12m_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <16>;
+};
+
+vtp_clk_div: vtp_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+usbphy_32khz_clkmux: usbphy_32khz_clkmux at 44df4260 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>;
+ reg = <0x44df4260 0x4>;
+};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 35/36] ARM: dts: AM43xx: link in clock DT data
2013-09-25 8:48 ` Tero Kristo
@ 2013-09-25 8:48 ` Tero Kristo
-1 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-omap, paul, tony, nm, rnayak, bcousson, mturquette
Cc: linux-arm-kernel, devicetree
Clock tree data is now included from base am4372.dtsi file.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/boot/dts/am4372.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 0fe393a..218c1bd 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -412,4 +412,11 @@
status = "disabled";
};
};
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ /include/ "am43xx-clocks.dtsi"
+ };
};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 35/36] ARM: dts: AM43xx: link in clock DT data
@ 2013-09-25 8:48 ` Tero Kristo
0 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-arm-kernel
Clock tree data is now included from base am4372.dtsi file.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/boot/dts/am4372.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 0fe393a..218c1bd 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -412,4 +412,11 @@
status = "disabled";
};
};
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ /include/ "am43xx-clocks.dtsi"
+ };
};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 36/36] CLK: TI: add am43xx clock init file
2013-09-25 8:48 ` Tero Kristo
@ 2013-09-25 8:48 ` Tero Kristo
-1 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-omap-u79uwXL29TY76Z2rM5mHXA, paul-DWxLp4Yu+b8AvxtiuMwx3w,
tony-4v6yS6AI5VpBDgjK7y7TUQ, nm-l0cyMroinI0, rnayak-l0cyMroinI0,
bcousson-rdvid1DuHRBWk0Htik3J/w,
mturquette-QSEj5FYQhm4dnm+yROfE0A
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
clk-43xx.c now contains the clock init functionality for am43xx, including
DT clock registration and adding of static clkdev entries.
Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
drivers/clk/ti/Makefile | 2 +-
drivers/clk/ti/clk-43xx.c | 120 +++++++++++++++++++++++++++++++++++++++++++++
include/linux/clk/ti.h | 1 +
3 files changed, 122 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/ti/clk-43xx.c
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index df226bc..1137c1d 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,7 +1,7 @@
ifneq ($(CONFIG_OF),)
obj-y += clk.o dpll.o autoidle.o divider.o \
fixed-factor.o gate.o clockdomain.o \
- mux-gate.o mux.o apll.o
+ mux-gate.o mux.o apll.o clk-43xx.o
obj-$(CONFIG_SOC_AM33XX) += clk-33xx.o
obj-$(CONFIG_ARCH_OMAP3) += interface.o clk-3xxx.o
obj-$(CONFIG_ARCH_OMAP4) += clk-44xx.o
diff --git a/drivers/clk/ti/clk-43xx.c b/drivers/clk/ti/clk-43xx.c
new file mode 100644
index 0000000..c9c752d
--- /dev/null
+++ b/drivers/clk/ti/clk-43xx.c
@@ -0,0 +1,120 @@
+/*
+ * AM43XX Clock init
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc
+ * Tero Kristo (t-kristo-l0cyMroinI0@public.gmane.org)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/clk-provider.h>
+#include <linux/clk/ti.h>
+
+static struct ti_dt_clk am43xx_clks[] = {
+ DT_CLK(NULL, "clk_32768_ck", "clk_32768_ck"),
+ DT_CLK(NULL, "clk_rc32k_ck", "clk_rc32k_ck"),
+ DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
+ DT_CLK(NULL, "virt_24000000_ck", "virt_24000000_ck"),
+ DT_CLK(NULL, "virt_25000000_ck", "virt_25000000_ck"),
+ DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
+ DT_CLK(NULL, "sys_clkin_ck", "sys_clkin_ck"),
+ DT_CLK(NULL, "tclkin_ck", "tclkin_ck"),
+ DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
+ DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
+ DT_CLK(NULL, "dpll_core_m4_ck", "dpll_core_m4_ck"),
+ DT_CLK(NULL, "dpll_core_m5_ck", "dpll_core_m5_ck"),
+ DT_CLK(NULL, "dpll_core_m6_ck", "dpll_core_m6_ck"),
+ DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"),
+ DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"),
+ DT_CLK(NULL, "dpll_ddr_ck", "dpll_ddr_ck"),
+ DT_CLK(NULL, "dpll_ddr_m2_ck", "dpll_ddr_m2_ck"),
+ DT_CLK(NULL, "dpll_disp_ck", "dpll_disp_ck"),
+ DT_CLK(NULL, "dpll_disp_m2_ck", "dpll_disp_m2_ck"),
+ DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"),
+ DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"),
+ DT_CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", "dpll_per_m2_div4_wkupdm_ck"),
+ DT_CLK(NULL, "dpll_per_m2_div4_ck", "dpll_per_m2_div4_ck"),
+ DT_CLK(NULL, "adc_tsc_fck", "adc_tsc_fck"),
+ DT_CLK(NULL, "clkdiv32k_ck", "clkdiv32k_ck"),
+ DT_CLK(NULL, "clkdiv32k_ick", "clkdiv32k_ick"),
+ DT_CLK(NULL, "dcan0_fck", "dcan0_fck"),
+ DT_CLK(NULL, "dcan1_fck", "dcan1_fck"),
+ DT_CLK(NULL, "pruss_ocp_gclk", "pruss_ocp_gclk"),
+ DT_CLK(NULL, "mcasp0_fck", "mcasp0_fck"),
+ DT_CLK(NULL, "mcasp1_fck", "mcasp1_fck"),
+ DT_CLK(NULL, "smartreflex0_fck", "smartreflex0_fck"),
+ DT_CLK(NULL, "smartreflex1_fck", "smartreflex1_fck"),
+ DT_CLK(NULL, "sha0_fck", "sha0_fck"),
+ DT_CLK(NULL, "aes0_fck", "aes0_fck"),
+ DT_CLK(NULL, "timer1_fck", "timer1_fck"),
+ DT_CLK(NULL, "timer2_fck", "timer2_fck"),
+ DT_CLK(NULL, "timer3_fck", "timer3_fck"),
+ DT_CLK(NULL, "timer4_fck", "timer4_fck"),
+ DT_CLK(NULL, "timer5_fck", "timer5_fck"),
+ DT_CLK(NULL, "timer6_fck", "timer6_fck"),
+ DT_CLK(NULL, "timer7_fck", "timer7_fck"),
+ DT_CLK(NULL, "wdt1_fck", "wdt1_fck"),
+ DT_CLK(NULL, "l3_gclk", "l3_gclk"),
+ DT_CLK(NULL, "dpll_core_m4_div2_ck", "dpll_core_m4_div2_ck"),
+ DT_CLK(NULL, "l4hs_gclk", "l4hs_gclk"),
+ DT_CLK(NULL, "l3s_gclk", "l3s_gclk"),
+ DT_CLK(NULL, "l4ls_gclk", "l4ls_gclk"),
+ DT_CLK(NULL, "clk_24mhz", "clk_24mhz"),
+ DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"),
+ DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"),
+ DT_CLK(NULL, "gpio0_dbclk_mux_ck", "gpio0_dbclk_mux_ck"),
+ DT_CLK(NULL, "gpio0_dbclk", "gpio0_dbclk"),
+ DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
+ DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"),
+ DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"),
+ DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"),
+ DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"),
+ DT_CLK(NULL, "mmc_clk", "mmc_clk"),
+ DT_CLK(NULL, "gfx_fclk_clksel_ck", "gfx_fclk_clksel_ck"),
+ DT_CLK(NULL, "gfx_fck_div_ck", "gfx_fck_div_ck"),
+ DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"),
+ DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
+ DT_CLK(NULL, "sysclk_div", "sysclk_div"),
+ DT_CLK(NULL, "disp_clk", "disp_clk"),
+ DT_CLK(NULL, "clk_32k_mosc_ck", "clk_32k_mosc_ck"),
+ DT_CLK(NULL, "clk_32k_tpm_ck", "clk_32k_tpm_ck"),
+ DT_CLK(NULL, "dpll_extdev_ck", "dpll_extdev_ck"),
+ DT_CLK(NULL, "dpll_extdev_m2_ck", "dpll_extdev_m2_ck"),
+ DT_CLK(NULL, "mux_synctimer32k_ck", "mux_synctimer32k_ck"),
+ DT_CLK(NULL, "synctimer_32kclk", "synctimer_32kclk"),
+ DT_CLK(NULL, "timer8_fck", "timer8_fck"),
+ DT_CLK(NULL, "timer9_fck", "timer9_fck"),
+ DT_CLK(NULL, "timer10_fck", "timer10_fck"),
+ DT_CLK(NULL, "timer11_fck", "timer11_fck"),
+ DT_CLK(NULL, "cpsw_50m_clkdiv", "cpsw_50m_clkdiv"),
+ DT_CLK(NULL, "cpsw_5m_clkdiv", "cpsw_5m_clkdiv"),
+ DT_CLK(NULL, "dpll_ddr_x2_ck", "dpll_ddr_x2_ck"),
+ DT_CLK(NULL, "dpll_ddr_m4_ck", "dpll_ddr_m4_ck"),
+ DT_CLK(NULL, "dpll_per_clkdcoldo", "dpll_per_clkdcoldo"),
+ DT_CLK(NULL, "dll_aging_clk_div", "dll_aging_clk_div"),
+ DT_CLK(NULL, "div_core_25m_ck", "div_core_25m_ck"),
+ DT_CLK(NULL, "func_12m_clk", "func_12m_clk"),
+ DT_CLK(NULL, "vtp_clk_div", "vtp_clk_div"),
+ DT_CLK(NULL, "usbphy_32khz_clkmux", "usbphy_32khz_clkmux"),
+ { .node_name = NULL },
+};
+
+int __init am43xx_clk_init(void)
+{
+ of_clk_init(NULL);
+
+ ti_dt_clocks_register(am43xx_clks);
+
+ omap2_clk_disable_autoidle_all();
+
+ return 0;
+}
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index bf8beff..21ceed6 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -229,6 +229,7 @@ int omap4xxx_clk_init(void);
int omap5xxx_clk_init(void);
int dra7xx_clk_init(void);
int am33xx_clk_init(void);
+int am43xx_clk_init(void);
#ifdef CONFIG_OF
void of_ti_clk_allow_autoidle_all(void);
--
1.7.9.5
--
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^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 36/36] CLK: TI: add am43xx clock init file
@ 2013-09-25 8:48 ` Tero Kristo
0 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-09-25 8:48 UTC (permalink / raw)
To: linux-arm-kernel
clk-43xx.c now contains the clock init functionality for am43xx, including
DT clock registration and adding of static clkdev entries.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
drivers/clk/ti/Makefile | 2 +-
drivers/clk/ti/clk-43xx.c | 120 +++++++++++++++++++++++++++++++++++++++++++++
include/linux/clk/ti.h | 1 +
3 files changed, 122 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/ti/clk-43xx.c
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index df226bc..1137c1d 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,7 +1,7 @@
ifneq ($(CONFIG_OF),)
obj-y += clk.o dpll.o autoidle.o divider.o \
fixed-factor.o gate.o clockdomain.o \
- mux-gate.o mux.o apll.o
+ mux-gate.o mux.o apll.o clk-43xx.o
obj-$(CONFIG_SOC_AM33XX) += clk-33xx.o
obj-$(CONFIG_ARCH_OMAP3) += interface.o clk-3xxx.o
obj-$(CONFIG_ARCH_OMAP4) += clk-44xx.o
diff --git a/drivers/clk/ti/clk-43xx.c b/drivers/clk/ti/clk-43xx.c
new file mode 100644
index 0000000..c9c752d
--- /dev/null
+++ b/drivers/clk/ti/clk-43xx.c
@@ -0,0 +1,120 @@
+/*
+ * AM43XX Clock init
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc
+ * Tero Kristo (t-kristo at ti.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/clk-provider.h>
+#include <linux/clk/ti.h>
+
+static struct ti_dt_clk am43xx_clks[] = {
+ DT_CLK(NULL, "clk_32768_ck", "clk_32768_ck"),
+ DT_CLK(NULL, "clk_rc32k_ck", "clk_rc32k_ck"),
+ DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
+ DT_CLK(NULL, "virt_24000000_ck", "virt_24000000_ck"),
+ DT_CLK(NULL, "virt_25000000_ck", "virt_25000000_ck"),
+ DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
+ DT_CLK(NULL, "sys_clkin_ck", "sys_clkin_ck"),
+ DT_CLK(NULL, "tclkin_ck", "tclkin_ck"),
+ DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
+ DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
+ DT_CLK(NULL, "dpll_core_m4_ck", "dpll_core_m4_ck"),
+ DT_CLK(NULL, "dpll_core_m5_ck", "dpll_core_m5_ck"),
+ DT_CLK(NULL, "dpll_core_m6_ck", "dpll_core_m6_ck"),
+ DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"),
+ DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"),
+ DT_CLK(NULL, "dpll_ddr_ck", "dpll_ddr_ck"),
+ DT_CLK(NULL, "dpll_ddr_m2_ck", "dpll_ddr_m2_ck"),
+ DT_CLK(NULL, "dpll_disp_ck", "dpll_disp_ck"),
+ DT_CLK(NULL, "dpll_disp_m2_ck", "dpll_disp_m2_ck"),
+ DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"),
+ DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"),
+ DT_CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", "dpll_per_m2_div4_wkupdm_ck"),
+ DT_CLK(NULL, "dpll_per_m2_div4_ck", "dpll_per_m2_div4_ck"),
+ DT_CLK(NULL, "adc_tsc_fck", "adc_tsc_fck"),
+ DT_CLK(NULL, "clkdiv32k_ck", "clkdiv32k_ck"),
+ DT_CLK(NULL, "clkdiv32k_ick", "clkdiv32k_ick"),
+ DT_CLK(NULL, "dcan0_fck", "dcan0_fck"),
+ DT_CLK(NULL, "dcan1_fck", "dcan1_fck"),
+ DT_CLK(NULL, "pruss_ocp_gclk", "pruss_ocp_gclk"),
+ DT_CLK(NULL, "mcasp0_fck", "mcasp0_fck"),
+ DT_CLK(NULL, "mcasp1_fck", "mcasp1_fck"),
+ DT_CLK(NULL, "smartreflex0_fck", "smartreflex0_fck"),
+ DT_CLK(NULL, "smartreflex1_fck", "smartreflex1_fck"),
+ DT_CLK(NULL, "sha0_fck", "sha0_fck"),
+ DT_CLK(NULL, "aes0_fck", "aes0_fck"),
+ DT_CLK(NULL, "timer1_fck", "timer1_fck"),
+ DT_CLK(NULL, "timer2_fck", "timer2_fck"),
+ DT_CLK(NULL, "timer3_fck", "timer3_fck"),
+ DT_CLK(NULL, "timer4_fck", "timer4_fck"),
+ DT_CLK(NULL, "timer5_fck", "timer5_fck"),
+ DT_CLK(NULL, "timer6_fck", "timer6_fck"),
+ DT_CLK(NULL, "timer7_fck", "timer7_fck"),
+ DT_CLK(NULL, "wdt1_fck", "wdt1_fck"),
+ DT_CLK(NULL, "l3_gclk", "l3_gclk"),
+ DT_CLK(NULL, "dpll_core_m4_div2_ck", "dpll_core_m4_div2_ck"),
+ DT_CLK(NULL, "l4hs_gclk", "l4hs_gclk"),
+ DT_CLK(NULL, "l3s_gclk", "l3s_gclk"),
+ DT_CLK(NULL, "l4ls_gclk", "l4ls_gclk"),
+ DT_CLK(NULL, "clk_24mhz", "clk_24mhz"),
+ DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"),
+ DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"),
+ DT_CLK(NULL, "gpio0_dbclk_mux_ck", "gpio0_dbclk_mux_ck"),
+ DT_CLK(NULL, "gpio0_dbclk", "gpio0_dbclk"),
+ DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
+ DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"),
+ DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"),
+ DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"),
+ DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"),
+ DT_CLK(NULL, "mmc_clk", "mmc_clk"),
+ DT_CLK(NULL, "gfx_fclk_clksel_ck", "gfx_fclk_clksel_ck"),
+ DT_CLK(NULL, "gfx_fck_div_ck", "gfx_fck_div_ck"),
+ DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"),
+ DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
+ DT_CLK(NULL, "sysclk_div", "sysclk_div"),
+ DT_CLK(NULL, "disp_clk", "disp_clk"),
+ DT_CLK(NULL, "clk_32k_mosc_ck", "clk_32k_mosc_ck"),
+ DT_CLK(NULL, "clk_32k_tpm_ck", "clk_32k_tpm_ck"),
+ DT_CLK(NULL, "dpll_extdev_ck", "dpll_extdev_ck"),
+ DT_CLK(NULL, "dpll_extdev_m2_ck", "dpll_extdev_m2_ck"),
+ DT_CLK(NULL, "mux_synctimer32k_ck", "mux_synctimer32k_ck"),
+ DT_CLK(NULL, "synctimer_32kclk", "synctimer_32kclk"),
+ DT_CLK(NULL, "timer8_fck", "timer8_fck"),
+ DT_CLK(NULL, "timer9_fck", "timer9_fck"),
+ DT_CLK(NULL, "timer10_fck", "timer10_fck"),
+ DT_CLK(NULL, "timer11_fck", "timer11_fck"),
+ DT_CLK(NULL, "cpsw_50m_clkdiv", "cpsw_50m_clkdiv"),
+ DT_CLK(NULL, "cpsw_5m_clkdiv", "cpsw_5m_clkdiv"),
+ DT_CLK(NULL, "dpll_ddr_x2_ck", "dpll_ddr_x2_ck"),
+ DT_CLK(NULL, "dpll_ddr_m4_ck", "dpll_ddr_m4_ck"),
+ DT_CLK(NULL, "dpll_per_clkdcoldo", "dpll_per_clkdcoldo"),
+ DT_CLK(NULL, "dll_aging_clk_div", "dll_aging_clk_div"),
+ DT_CLK(NULL, "div_core_25m_ck", "div_core_25m_ck"),
+ DT_CLK(NULL, "func_12m_clk", "func_12m_clk"),
+ DT_CLK(NULL, "vtp_clk_div", "vtp_clk_div"),
+ DT_CLK(NULL, "usbphy_32khz_clkmux", "usbphy_32khz_clkmux"),
+ { .node_name = NULL },
+};
+
+int __init am43xx_clk_init(void)
+{
+ of_clk_init(NULL);
+
+ ti_dt_clocks_register(am43xx_clks);
+
+ omap2_clk_disable_autoidle_all();
+
+ return 0;
+}
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index bf8beff..21ceed6 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -229,6 +229,7 @@ int omap4xxx_clk_init(void);
int omap5xxx_clk_init(void);
int dra7xx_clk_init(void);
int am33xx_clk_init(void);
+int am43xx_clk_init(void);
#ifdef CONFIG_OF
void of_ti_clk_allow_autoidle_all(void);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 136+ messages in thread
* Re: [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
2013-09-25 8:48 ` Tero Kristo
@ 2013-09-26 15:21 ` Nishanth Menon
-1 siblings, 0 replies; 136+ messages in thread
From: Nishanth Menon @ 2013-09-26 15:21 UTC (permalink / raw)
To: Tero Kristo, linux-omap-u79uwXL29TY76Z2rM5mHXA,
paul-DWxLp4Yu+b8AvxtiuMwx3w, tony-4v6yS6AI5VpBDgjK7y7TUQ,
rnayak-l0cyMroinI0, bcousson-rdvid1DuHRBWk0Htik3J/w,
mturquette-QSEj5FYQhm4dnm+yROfE0A
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
On 09/25/2013 03:48 AM, Tero Kristo wrote:
[...]
> Test branch available here:
> https://github.com/t-kristo/linux-pm.git
> branch: mainline-3.12-rc2-ti-dt-clks-v7
>
> Testing done:
> - am335x-bone : boot only
> - omap5-sevm : boot only
> - dra7-evm : boot only
> - omap3-beagle : boot + suspend/resume (ret + off)
> - omap4-panda-es : boot + suspend/resume
>
> Nishanth has also been doing some tests with omap3-beagle-xm with some WIP
> versions of this branch, but not with this latest one. Nishanth, maybe you
> can provide test results to this one also?
I rebased the branch on top of benoit's for_3.13/dts merged with
v3.12-rc2 tag
45646cd ARM: dts: AM33XX: don't redefine OCP bus and device nodes
All platforms were to MMC filesystem boot (SD card). u-boot used
v2013.10-rc3 on all platforms (mainline u-boot).
OMAP3630: Beagle-XM:
http://pastebin.pandaboard.org/index.php/view/96577127
(needs additional patch
-> https://patchwork.kernel.org/patch/2919661/ )
OMAP4460: Panda-ES: http://pastebin.pandaboard.org/index.php/view/85143661
OMAP5432: OMAP5-UEVM:
http://pastebin.pandaboard.org/index.php/view/91361843
(nice to have patch
-> https://patchwork.kernel.org/patch/2907761/ )
AM335x: BeagleBone Black:
http://pastebin.pandaboard.org/index.php/view/42000597
(needs additional patches:
https://patchwork.kernel.org/patch/2902711/
https://patchwork.kernel.org/patch/2902711/
)
DRA7: DRA7-EVM: http://pastebin.pandaboard.org/index.php/view/38362805
(needs additional patches:
-> https://patchwork.kernel.org/patch/2849391/
-> https://patchwork.kernel.org/patch/2849601/
-> https://patchwork.kernel.org/patch/2849602/
-> https://patchwork.kernel.org/patch/2907761/
)
So, for the entire series:
Tested-by: Nishanth Menon <nm-l0cyMroinI0@public.gmane.org>
--
Regards,
Nishanth Menon
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 136+ messages in thread
* [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
@ 2013-09-26 15:21 ` Nishanth Menon
0 siblings, 0 replies; 136+ messages in thread
From: Nishanth Menon @ 2013-09-26 15:21 UTC (permalink / raw)
To: linux-arm-kernel
On 09/25/2013 03:48 AM, Tero Kristo wrote:
[...]
> Test branch available here:
> https://github.com/t-kristo/linux-pm.git
> branch: mainline-3.12-rc2-ti-dt-clks-v7
>
> Testing done:
> - am335x-bone : boot only
> - omap5-sevm : boot only
> - dra7-evm : boot only
> - omap3-beagle : boot + suspend/resume (ret + off)
> - omap4-panda-es : boot + suspend/resume
>
> Nishanth has also been doing some tests with omap3-beagle-xm with some WIP
> versions of this branch, but not with this latest one. Nishanth, maybe you
> can provide test results to this one also?
I rebased the branch on top of benoit's for_3.13/dts merged with
v3.12-rc2 tag
45646cd ARM: dts: AM33XX: don't redefine OCP bus and device nodes
All platforms were to MMC filesystem boot (SD card). u-boot used
v2013.10-rc3 on all platforms (mainline u-boot).
OMAP3630: Beagle-XM:
http://pastebin.pandaboard.org/index.php/view/96577127
(needs additional patch
-> https://patchwork.kernel.org/patch/2919661/ )
OMAP4460: Panda-ES: http://pastebin.pandaboard.org/index.php/view/85143661
OMAP5432: OMAP5-UEVM:
http://pastebin.pandaboard.org/index.php/view/91361843
(nice to have patch
-> https://patchwork.kernel.org/patch/2907761/ )
AM335x: BeagleBone Black:
http://pastebin.pandaboard.org/index.php/view/42000597
(needs additional patches:
https://patchwork.kernel.org/patch/2902711/
https://patchwork.kernel.org/patch/2902711/
)
DRA7: DRA7-EVM: http://pastebin.pandaboard.org/index.php/view/38362805
(needs additional patches:
-> https://patchwork.kernel.org/patch/2849391/
-> https://patchwork.kernel.org/patch/2849601/
-> https://patchwork.kernel.org/patch/2849602/
-> https://patchwork.kernel.org/patch/2907761/
)
So, for the entire series:
Tested-by: Nishanth Menon <nm@ti.com>
--
Regards,
Nishanth Menon
^ permalink raw reply [flat|nested] 136+ messages in thread
* Re: [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
2013-09-26 15:21 ` Nishanth Menon
@ 2013-09-26 15:29 ` Nishanth Menon
-1 siblings, 0 replies; 136+ messages in thread
From: Nishanth Menon @ 2013-09-26 15:29 UTC (permalink / raw)
To: Tero Kristo, linux-omap, paul, tony, rnayak, bcousson, mturquette
Cc: linux-arm-kernel, devicetree
On 09/26/2013 10:21 AM, Nishanth Menon wrote:
> On 09/25/2013 03:48 AM, Tero Kristo wrote:
> [...]
>> Test branch available here:
>> https://github.com/t-kristo/linux-pm.git
>> branch: mainline-3.12-rc2-ti-dt-clks-v7
>>
>> Testing done:
>> - am335x-bone : boot only
>> - omap5-sevm : boot only
>> - dra7-evm : boot only
>> - omap3-beagle : boot + suspend/resume (ret + off)
>> - omap4-panda-es : boot + suspend/resume
>>
>> Nishanth has also been doing some tests with omap3-beagle-xm with some WIP
>> versions of this branch, but not with this latest one. Nishanth, maybe you
>> can provide test results to this one also?
> I rebased the branch on top of benoit's for_3.13/dts merged with
> v3.12-rc2 tag
> 45646cd ARM: dts: AM33XX: don't redefine OCP bus and device nodes
>
> All platforms were to MMC filesystem boot (SD card). u-boot used
> v2013.10-rc3 on all platforms (mainline u-boot).
>
> OMAP3630: Beagle-XM:
> http://pastebin.pandaboard.org/index.php/view/96577127
> (needs additional patch
> -> https://patchwork.kernel.org/patch/2919661/ )
dependency patch needs rework
>
> OMAP4460: Panda-ES: http://pastebin.pandaboard.org/index.php/view/85143661
>
> OMAP5432: OMAP5-UEVM:
> http://pastebin.pandaboard.org/index.php/view/91361843
> (nice to have patch
> -> https://patchwork.kernel.org/patch/2907761/ )
Acked,tested, pending merge from maintainers
>
> AM335x: BeagleBone Black:
> http://pastebin.pandaboard.org/index.php/view/42000597
> (needs additional patches:
> https://patchwork.kernel.org/patch/2902711/
-> merged to Shekar's davinci branch -> pending upstream.
> https://patchwork.kernel.org/patch/2902711/
Correction on ^^: should have been:
https://patchwork.kernel.org/patch/2919661/
tested, pending ack, merge.
> )
>
> DRA7: DRA7-EVM: http://pastebin.pandaboard.org/index.php/view/38362805
> (needs additional patches:
> -> https://patchwork.kernel.org/patch/2849391/
> -> https://patchwork.kernel.org/patch/2849601/
> -> https://patchwork.kernel.org/patch/2849602/
> -> https://patchwork.kernel.org/patch/2907761/
All of the above:
Acked,tested, pending merge from maintainers
> )
>
> So, for the entire series:
> Tested-by: Nishanth Menon <nm@ti.com>
>
Maybe Benoit and Tony could help reduce few of these acked patches
pending merge from having to be cherry-picked by folks.
--
Regards,
Nishanth Menon
^ permalink raw reply [flat|nested] 136+ messages in thread
* [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
@ 2013-09-26 15:29 ` Nishanth Menon
0 siblings, 0 replies; 136+ messages in thread
From: Nishanth Menon @ 2013-09-26 15:29 UTC (permalink / raw)
To: linux-arm-kernel
On 09/26/2013 10:21 AM, Nishanth Menon wrote:
> On 09/25/2013 03:48 AM, Tero Kristo wrote:
> [...]
>> Test branch available here:
>> https://github.com/t-kristo/linux-pm.git
>> branch: mainline-3.12-rc2-ti-dt-clks-v7
>>
>> Testing done:
>> - am335x-bone : boot only
>> - omap5-sevm : boot only
>> - dra7-evm : boot only
>> - omap3-beagle : boot + suspend/resume (ret + off)
>> - omap4-panda-es : boot + suspend/resume
>>
>> Nishanth has also been doing some tests with omap3-beagle-xm with some WIP
>> versions of this branch, but not with this latest one. Nishanth, maybe you
>> can provide test results to this one also?
> I rebased the branch on top of benoit's for_3.13/dts merged with
> v3.12-rc2 tag
> 45646cd ARM: dts: AM33XX: don't redefine OCP bus and device nodes
>
> All platforms were to MMC filesystem boot (SD card). u-boot used
> v2013.10-rc3 on all platforms (mainline u-boot).
>
> OMAP3630: Beagle-XM:
> http://pastebin.pandaboard.org/index.php/view/96577127
> (needs additional patch
> -> https://patchwork.kernel.org/patch/2919661/ )
dependency patch needs rework
>
> OMAP4460: Panda-ES: http://pastebin.pandaboard.org/index.php/view/85143661
>
> OMAP5432: OMAP5-UEVM:
> http://pastebin.pandaboard.org/index.php/view/91361843
> (nice to have patch
> -> https://patchwork.kernel.org/patch/2907761/ )
Acked,tested, pending merge from maintainers
>
> AM335x: BeagleBone Black:
> http://pastebin.pandaboard.org/index.php/view/42000597
> (needs additional patches:
> https://patchwork.kernel.org/patch/2902711/
-> merged to Shekar's davinci branch -> pending upstream.
> https://patchwork.kernel.org/patch/2902711/
Correction on ^^: should have been:
https://patchwork.kernel.org/patch/2919661/
tested, pending ack, merge.
> )
>
> DRA7: DRA7-EVM: http://pastebin.pandaboard.org/index.php/view/38362805
> (needs additional patches:
> -> https://patchwork.kernel.org/patch/2849391/
> -> https://patchwork.kernel.org/patch/2849601/
> -> https://patchwork.kernel.org/patch/2849602/
> -> https://patchwork.kernel.org/patch/2907761/
All of the above:
Acked,tested, pending merge from maintainers
> )
>
> So, for the entire series:
> Tested-by: Nishanth Menon <nm@ti.com>
>
Maybe Benoit and Tony could help reduce few of these acked patches
pending merge from having to be cherry-picked by folks.
--
Regards,
Nishanth Menon
^ permalink raw reply [flat|nested] 136+ messages in thread
* Re: [PATCHv7 30/36] ARM: dts: omap3 clock data
2013-09-25 8:48 ` Tero Kristo
@ 2013-09-26 16:06 ` Nishanth Menon
-1 siblings, 0 replies; 136+ messages in thread
From: Nishanth Menon @ 2013-09-26 16:06 UTC (permalink / raw)
To: Tero Kristo
Cc: linux-omap, paul, tony, rnayak, bcousson, mturquette,
linux-arm-kernel, devicetree
On 11:48-20130925, Tero Kristo wrote:
> diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
> index 16420ae..bc11b83 100644
> --- a/arch/arm/boot/dts/omap3.dtsi
> +++ b/arch/arm/boot/dts/omap3.dtsi
> @@ -533,4 +533,11 @@
> ram-bits = <12>;
> };
> };
> +
> + clocks {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + /include/ "omap3xxx-clocks.dtsi"
> + };
> };
Clocks are introduced towards the tail of the dts -> this has a problem
associated with it -> device nodes should be able to reference phandle
like:
devicex {
clocks = <&sys_ck>;
}
Since all the devices on ocp and cpu0 node appears above the definition
they fail to catch the phandle. instead, moving the clocks node as high
in the tree as possible resolves this: something like:
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index bc11b83..0b2161d 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -24,6 +24,13 @@
serial2 = &uart3;
};
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ /include/ "omap3xxx-clocks.dtsi"
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -534,10 +541,4 @@
};
};
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- /include/ "omap3xxx-clocks.dtsi"
- };
};
What do you think of the change? applies for all clock nodes in other
dtsi as well - I will mark them as I find them.
Further,
> diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi
> index 5355d61..2ed7c69 100644
> --- a/arch/arm/boot/dts/omap34xx.dtsi
> +++ b/arch/arm/boot/dts/omap34xx.dtsi
> @@ -25,4 +25,123 @@
> clock-latency = <300000>; /* From legacy driver */
> };
> };
> -};
> +
> + clocks {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
dont need to state the above two -> already done in omap3.dtsi.
> + /include/ "omap34xx-omap36xx-clocks.dtsi"
> + /include/ "omap36xx-omap3430es2plus-clocks.dtsi"
> + /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
> + };
> +};
[...]
> \ No newline at end of file
^^
[...]
> diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi
> index f8b3765..71fb6fb 100644
> --- a/arch/arm/boot/dts/omap36xx.dtsi
> +++ b/arch/arm/boot/dts/omap36xx.dtsi
> @@ -35,4 +35,124 @@
> clock-frequency = <48000000>;
> };
> };
> -};
> +
> + clocks {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
^^ here as well.
> + /include/ "omap36xx-clocks.dtsi"
> + /include/ "omap34xx-omap36xx-clocks.dtsi"
> + /include/ "omap36xx-omap3430es2plus-clocks.dtsi"
> + /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
> + };
[...]
> +};
> \ No newline at end of file
^^ this need fix as well.
--
Regards,
Nishanth Menon
^ permalink raw reply related [flat|nested] 136+ messages in thread
* [PATCHv7 30/36] ARM: dts: omap3 clock data
@ 2013-09-26 16:06 ` Nishanth Menon
0 siblings, 0 replies; 136+ messages in thread
From: Nishanth Menon @ 2013-09-26 16:06 UTC (permalink / raw)
To: linux-arm-kernel
On 11:48-20130925, Tero Kristo wrote:
> diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
> index 16420ae..bc11b83 100644
> --- a/arch/arm/boot/dts/omap3.dtsi
> +++ b/arch/arm/boot/dts/omap3.dtsi
> @@ -533,4 +533,11 @@
> ram-bits = <12>;
> };
> };
> +
> + clocks {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + /include/ "omap3xxx-clocks.dtsi"
> + };
> };
Clocks are introduced towards the tail of the dts -> this has a problem
associated with it -> device nodes should be able to reference phandle
like:
devicex {
clocks = <&sys_ck>;
}
Since all the devices on ocp and cpu0 node appears above the definition
they fail to catch the phandle. instead, moving the clocks node as high
in the tree as possible resolves this: something like:
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index bc11b83..0b2161d 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -24,6 +24,13 @@
serial2 = &uart3;
};
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ /include/ "omap3xxx-clocks.dtsi"
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -534,10 +541,4 @@
};
};
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- /include/ "omap3xxx-clocks.dtsi"
- };
};
What do you think of the change? applies for all clock nodes in other
dtsi as well - I will mark them as I find them.
Further,
> diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi
> index 5355d61..2ed7c69 100644
> --- a/arch/arm/boot/dts/omap34xx.dtsi
> +++ b/arch/arm/boot/dts/omap34xx.dtsi
> @@ -25,4 +25,123 @@
> clock-latency = <300000>; /* From legacy driver */
> };
> };
> -};
> +
> + clocks {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
dont need to state the above two -> already done in omap3.dtsi.
> + /include/ "omap34xx-omap36xx-clocks.dtsi"
> + /include/ "omap36xx-omap3430es2plus-clocks.dtsi"
> + /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
> + };
> +};
[...]
> \ No newline at end of file
^^
[...]
> diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi
> index f8b3765..71fb6fb 100644
> --- a/arch/arm/boot/dts/omap36xx.dtsi
> +++ b/arch/arm/boot/dts/omap36xx.dtsi
> @@ -35,4 +35,124 @@
> clock-frequency = <48000000>;
> };
> };
> -};
> +
> + clocks {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
^^ here as well.
> + /include/ "omap36xx-clocks.dtsi"
> + /include/ "omap34xx-omap36xx-clocks.dtsi"
> + /include/ "omap36xx-omap3430es2plus-clocks.dtsi"
> + /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
> + };
[...]
> +};
> \ No newline at end of file
^^ this need fix as well.
--
Regards,
Nishanth Menon
^ permalink raw reply related [flat|nested] 136+ messages in thread
* Re: [PATCHv7 30/36] ARM: dts: omap3 clock data
2013-09-26 16:06 ` Nishanth Menon
@ 2013-09-26 16:23 ` Nishanth Menon
-1 siblings, 0 replies; 136+ messages in thread
From: Nishanth Menon @ 2013-09-26 16:23 UTC (permalink / raw)
To: Tero Kristo
Cc: linux-omap-u79uwXL29TY76Z2rM5mHXA, paul-DWxLp4Yu+b8AvxtiuMwx3w,
tony-4v6yS6AI5VpBDgjK7y7TUQ, rnayak-l0cyMroinI0,
bcousson-rdvid1DuHRBWk0Htik3J/w,
mturquette-QSEj5FYQhm4dnm+yROfE0A,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
On 09/26/2013 11:06 AM, Nishanth Menon wrote:
> On 11:48-20130925, Tero Kristo wrote:
>> diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
>> index 16420ae..bc11b83 100644
>> --- a/arch/arm/boot/dts/omap3.dtsi
>> +++ b/arch/arm/boot/dts/omap3.dtsi
>> @@ -533,4 +533,11 @@
>> ram-bits = <12>;
>> };
>> };
>> +
>> + clocks {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> + /include/ "omap3xxx-clocks.dtsi"
>> + };
>> };
> Clocks are introduced towards the tail of the dts -> this has a problem
> associated with it -> device nodes should be able to reference phandle
> like:
>
> devicex {
> clocks = <&sys_ck>;
> }
>
> Since all the devices on ocp and cpu0 node appears above the definition
> they fail to catch the phandle. instead, moving the clocks node as high
> in the tree as possible resolves this: something like:
> diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
> index bc11b83..0b2161d 100644
> --- a/arch/arm/boot/dts/omap3.dtsi
> +++ b/arch/arm/boot/dts/omap3.dtsi
> @@ -24,6 +24,13 @@
> serial2 = &uart3;
> };
>
> + clocks {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + /include/ "omap3xxx-clocks.dtsi"
> + };
> +
> cpus {
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -534,10 +541,4 @@
> };
> };
>
> - clocks {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - ranges;
> - /include/ "omap3xxx-clocks.dtsi"
> - };
> };
>
> What do you think of the change? applies for all clock nodes in other
> dtsi as well - I will mark them as I find them.
Digging further, the above is not needed. Apologies on the noise.
below changes will be nice though..
>
> Further,
>> diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi
>> index 5355d61..2ed7c69 100644
>> --- a/arch/arm/boot/dts/omap34xx.dtsi
>> +++ b/arch/arm/boot/dts/omap34xx.dtsi
>> @@ -25,4 +25,123 @@
>> clock-latency = <300000>; /* From legacy driver */
>> };
>> };
>> -};
>> +
>> + clocks {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
> dont need to state the above two -> already done in omap3.dtsi.
>> + /include/ "omap34xx-omap36xx-clocks.dtsi"
>> + /include/ "omap36xx-omap3430es2plus-clocks.dtsi"
>> + /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
>> + };
>> +};
> [...]
>> \ No newline at end of file
> ^^
> [...]
>> diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi
>> index f8b3765..71fb6fb 100644
>> --- a/arch/arm/boot/dts/omap36xx.dtsi
>> +++ b/arch/arm/boot/dts/omap36xx.dtsi
>> @@ -35,4 +35,124 @@
>> clock-frequency = <48000000>;
>> };
>> };
>> -};
>> +
>> + clocks {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
> ^^ here as well.
>> + /include/ "omap36xx-clocks.dtsi"
>> + /include/ "omap34xx-omap36xx-clocks.dtsi"
>> + /include/ "omap36xx-omap3430es2plus-clocks.dtsi"
>> + /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
>> + };
> [...]
>> +};
>> \ No newline at end of file
> ^^ this need fix as well.
>
--
Regards,
Nishanth Menon
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^ permalink raw reply [flat|nested] 136+ messages in thread
* [PATCHv7 30/36] ARM: dts: omap3 clock data
@ 2013-09-26 16:23 ` Nishanth Menon
0 siblings, 0 replies; 136+ messages in thread
From: Nishanth Menon @ 2013-09-26 16:23 UTC (permalink / raw)
To: linux-arm-kernel
On 09/26/2013 11:06 AM, Nishanth Menon wrote:
> On 11:48-20130925, Tero Kristo wrote:
>> diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
>> index 16420ae..bc11b83 100644
>> --- a/arch/arm/boot/dts/omap3.dtsi
>> +++ b/arch/arm/boot/dts/omap3.dtsi
>> @@ -533,4 +533,11 @@
>> ram-bits = <12>;
>> };
>> };
>> +
>> + clocks {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> + /include/ "omap3xxx-clocks.dtsi"
>> + };
>> };
> Clocks are introduced towards the tail of the dts -> this has a problem
> associated with it -> device nodes should be able to reference phandle
> like:
>
> devicex {
> clocks = <&sys_ck>;
> }
>
> Since all the devices on ocp and cpu0 node appears above the definition
> they fail to catch the phandle. instead, moving the clocks node as high
> in the tree as possible resolves this: something like:
> diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
> index bc11b83..0b2161d 100644
> --- a/arch/arm/boot/dts/omap3.dtsi
> +++ b/arch/arm/boot/dts/omap3.dtsi
> @@ -24,6 +24,13 @@
> serial2 = &uart3;
> };
>
> + clocks {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + /include/ "omap3xxx-clocks.dtsi"
> + };
> +
> cpus {
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -534,10 +541,4 @@
> };
> };
>
> - clocks {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - ranges;
> - /include/ "omap3xxx-clocks.dtsi"
> - };
> };
>
> What do you think of the change? applies for all clock nodes in other
> dtsi as well - I will mark them as I find them.
Digging further, the above is not needed. Apologies on the noise.
below changes will be nice though..
>
> Further,
>> diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi
>> index 5355d61..2ed7c69 100644
>> --- a/arch/arm/boot/dts/omap34xx.dtsi
>> +++ b/arch/arm/boot/dts/omap34xx.dtsi
>> @@ -25,4 +25,123 @@
>> clock-latency = <300000>; /* From legacy driver */
>> };
>> };
>> -};
>> +
>> + clocks {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
> dont need to state the above two -> already done in omap3.dtsi.
>> + /include/ "omap34xx-omap36xx-clocks.dtsi"
>> + /include/ "omap36xx-omap3430es2plus-clocks.dtsi"
>> + /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
>> + };
>> +};
> [...]
>> \ No newline at end of file
> ^^
> [...]
>> diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi
>> index f8b3765..71fb6fb 100644
>> --- a/arch/arm/boot/dts/omap36xx.dtsi
>> +++ b/arch/arm/boot/dts/omap36xx.dtsi
>> @@ -35,4 +35,124 @@
>> clock-frequency = <48000000>;
>> };
>> };
>> -};
>> +
>> + clocks {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
> ^^ here as well.
>> + /include/ "omap36xx-clocks.dtsi"
>> + /include/ "omap34xx-omap36xx-clocks.dtsi"
>> + /include/ "omap36xx-omap3430es2plus-clocks.dtsi"
>> + /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
>> + };
> [...]
>> +};
>> \ No newline at end of file
> ^^ this need fix as well.
>
--
Regards,
Nishanth Menon
^ permalink raw reply [flat|nested] 136+ messages in thread
* Re: [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
2013-09-25 8:48 ` Tero Kristo
@ 2013-10-04 15:34 ` Tero Kristo
-1 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-10-04 15:34 UTC (permalink / raw)
To: linux-omap-u79uwXL29TY76Z2rM5mHXA, paul-DWxLp4Yu+b8AvxtiuMwx3w,
tony-4v6yS6AI5VpBDgjK7y7TUQ, nm-l0cyMroinI0, rnayak-l0cyMroinI0,
bcousson-rdvid1DuHRBWk0Htik3J/w,
mturquette-QSEj5FYQhm4dnm+yROfE0A
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
Hi,
Just a gentle reminder, anybody have any comments on this series or
should we start queuing stuff?
-Tero
On 09/25/2013 11:48 AM, Tero Kristo wrote:
> Hi all,
>
> Version 7 contains following high level changes:
> - Dropped support for basic bindings from Mike Turquette, instead using
> vendor specific bindings for all clocks
> - Mux clock + divider clock vendor specific bindings get rid of use
> of the bit-masks, instead these are generated runtime based on parent
> clock / divider min/max info, see individual patches for details
> - Added support for dummy_ck nodes, was missing from previous version
> - Fixed support for omap3630
> - Added support for new clock node type: ti,mux-gate-clock (using composite
> clock type)
> - OMAP4 / OMAP5 only build fixes (compiler flag checks added to some files)
> - most of the of_omap_* calls renamed to of_ti_*
> - Rebased on top of v3.12-rc2
>
> Some detailed comments about patch level changes (if no mention, no major
> changes):
> - Patch #1:
> * removed use of reg-names property, instead registers mapped using
> compatible string
> * removed ti,modes property, instead uses DPLL mode flags now
> * separated AM33XX DPLLs under their own compatible strings
> - Patch #4 & #5: new patches
> - Patch #6: merged basic gate support from Mike to this patch as vendor
> specific gate clock support
> - Patch #9 & #10: new patches
> - Patch #11: dummy clocks added, USB / ABE DPLL setup ordering changed
> - Patch #14: dummy clocks added
> - Patch #20: dropped usage of reg-names property
> - Patch #21: dummy clocks added
> - Patch #22 & #23: new patches
> - Patch #30: AM35XX clock data added to this patch
> - Patch #31:
> * dummy clocks added
> * added missing 3630 clocks
>
> Test branch available here:
> https://github.com/t-kristo/linux-pm.git
> branch: mainline-3.12-rc2-ti-dt-clks-v7
>
> Testing done:
> - am335x-bone : boot only
> - omap5-sevm : boot only
> - dra7-evm : boot only
> - omap3-beagle : boot + suspend/resume (ret + off)
> - omap4-panda-es : boot + suspend/resume
>
> Nishanth has also been doing some tests with omap3-beagle-xm with some WIP
> versions of this branch, but not with this latest one. Nishanth, maybe you
> can provide test results to this one also?
>
> -Tero
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
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^ permalink raw reply [flat|nested] 136+ messages in thread
* [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
@ 2013-10-04 15:34 ` Tero Kristo
0 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-10-04 15:34 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
Just a gentle reminder, anybody have any comments on this series or
should we start queuing stuff?
-Tero
On 09/25/2013 11:48 AM, Tero Kristo wrote:
> Hi all,
>
> Version 7 contains following high level changes:
> - Dropped support for basic bindings from Mike Turquette, instead using
> vendor specific bindings for all clocks
> - Mux clock + divider clock vendor specific bindings get rid of use
> of the bit-masks, instead these are generated runtime based on parent
> clock / divider min/max info, see individual patches for details
> - Added support for dummy_ck nodes, was missing from previous version
> - Fixed support for omap3630
> - Added support for new clock node type: ti,mux-gate-clock (using composite
> clock type)
> - OMAP4 / OMAP5 only build fixes (compiler flag checks added to some files)
> - most of the of_omap_* calls renamed to of_ti_*
> - Rebased on top of v3.12-rc2
>
> Some detailed comments about patch level changes (if no mention, no major
> changes):
> - Patch #1:
> * removed use of reg-names property, instead registers mapped using
> compatible string
> * removed ti,modes property, instead uses DPLL mode flags now
> * separated AM33XX DPLLs under their own compatible strings
> - Patch #4 & #5: new patches
> - Patch #6: merged basic gate support from Mike to this patch as vendor
> specific gate clock support
> - Patch #9 & #10: new patches
> - Patch #11: dummy clocks added, USB / ABE DPLL setup ordering changed
> - Patch #14: dummy clocks added
> - Patch #20: dropped usage of reg-names property
> - Patch #21: dummy clocks added
> - Patch #22 & #23: new patches
> - Patch #30: AM35XX clock data added to this patch
> - Patch #31:
> * dummy clocks added
> * added missing 3630 clocks
>
> Test branch available here:
> https://github.com/t-kristo/linux-pm.git
> branch: mainline-3.12-rc2-ti-dt-clks-v7
>
> Testing done:
> - am335x-bone : boot only
> - omap5-sevm : boot only
> - dra7-evm : boot only
> - omap3-beagle : boot + suspend/resume (ret + off)
> - omap4-panda-es : boot + suspend/resume
>
> Nishanth has also been doing some tests with omap3-beagle-xm with some WIP
> versions of this branch, but not with this latest one. Nishanth, maybe you
> can provide test results to this one also?
>
> -Tero
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply [flat|nested] 136+ messages in thread
* Re: [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
2013-10-04 15:34 ` Tero Kristo
@ 2013-10-07 2:15 ` Tony Lindgren
-1 siblings, 0 replies; 136+ messages in thread
From: Tony Lindgren @ 2013-10-07 2:15 UTC (permalink / raw)
To: Tero Kristo
Cc: linux-omap, paul, nm, rnayak, bcousson, mturquette,
linux-arm-kernel, devicetree
* Tero Kristo <t-kristo@ti.com> [131004 08:42]:
> Hi,
>
> Just a gentle reminder, anybody have any comments on this series or
> should we start queuing stuff?
Well omap4 seems to work for me just fine, and omap3 in legacy
mode. But looks like omap3 device tree based booting is breaking
after I pulled in your test branch. I get the following on
3630 based dm3730.
Regards,
Tony
[ 0.187652] omap_hwmod: uart4: cannot clk_get main_clk uart4_fck
[ 0.187713] omap_hwmod: uart4: cannot _init_clocks
[ 0.187713] ------------[ cut here ]------------
[ 0.187774] WARNING: CPU: 0 PID: 1 at arch/arm/mach-omap2/omap_hwmod.c:2434 _init+0x6c/0x80()
[ 0.187774] omap_hwmod: uart4: couldn't init clocks
[ 0.187774] Modules linked in:
[ 0.187805] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.12.0-rc2-00020-gdea1778-dirty #791
[ 0.187866] [<c001cd54>] (unwind_backtrace+0x0/0xf4) from [<c0018e80>] (show_stack+0x14/0x1c)
[ 0.187896] [<c0018e80>] (show_stack+0x14/0x1c) from [<c0554400>] (dump_stack+0x6c/0x9c)
[ 0.187927] [<c0554400>] (dump_stack+0x6c/0x9c) from [<c00488a8>] (warn_slowpath_common+0x64/0x84)
[ 0.187957] [<c00488a8>] (warn_slowpath_common+0x64/0x84) from [<c004895c>] (warn_slowpath_fmt+0x30/0x40)
[ 0.187988] [<c004895c>] (warn_slowpath_fmt+0x30/0x40) from [<c07a4bec>] (_init+0x6c/0x80)
[ 0.188018] [<c07a4bec>] (_init+0x6c/0x80) from [<c002e068>] (omap_hwmod_for_each+0x50/0x64)
[ 0.188049] [<c002e068>] (omap_hwmod_for_each+0x50/0x64) from [<c07a5440>] (__omap_hwmod_setup_all+0x34/0x4c)
[ 0.188079] [<c07a5440>] (__omap_hwmod_setup_all+0x34/0x4c) from [<c00087ac>] (do_one_initcall+0x2c/0x150)
[ 0.188110] [<c00087ac>] (do_one_initcall+0x2c/0x150) from [<c0797508>] (do_basic_setup+0x94/0xd0)
[ 0.188140] [<c0797508>] (do_basic_setup+0x94/0xd0) from [<c07975c0>] (kernel_init_freeable+0x7c/0x120)
[ 0.188171] [<c07975c0>] (kernel_init_freeable+0x7c/0x120) from [<c05526b4>] (kernel_init+0xc/0x164)
[ 0.188201] [<c05526b4>] (kernel_init+0xc/0x164) from [<c00149c8>] (ret_from_fork+0x14/0x2c)
[ 0.188415] ---[ end trace 1b75b31a2719ed1c ]---
[ 0.810241] ------------[ cut here ]------------
[ 0.810302] WARNING: CPU: 0 PID: 1 at arch/arm/mach-omap2/omap_hwmod.c:2126 _enable+0x254/0x280()
[ 0.810302] omap_hwmod: timer12: enabled state can only be entered from initialized, idle, or disabled state
[ 0.810333] Modules linked in:
[ 0.810363] CPU: 0 PID: 1 Comm: swapper/0 Tainted: G W 3.12.0-rc2-00020-gdea1778-dirty #791
[ 0.810394] [<c001cd54>] (unwind_backtrace+0x0/0xf4) from [<c0018e80>] (show_stack+0x14/0x1c)
[ 0.810424] [<c0018e80>] (show_stack+0x14/0x1c) from [<c0554400>] (dump_stack+0x6c/0x9c)
[ 0.810455] [<c0554400>] (dump_stack+0x6c/0x9c) from [<c00488a8>] (warn_slowpath_common+0x64/0x84)
[ 0.810485] [<c00488a8>] (warn_slowpath_common+0x64/0x84) from [<c004895c>] (warn_slowpath_fmt+0x30/0x40)
[ 0.810516] [<c004895c>] (warn_slowpath_fmt+0x30/0x40) from [<c003085c>] (_enable+0x254/0x280)
[ 0.810546] [<c003085c>] (_enable+0x254/0x280) from [<c00308b0>] (omap_hwmod_enable+0x28/0x40)
[ 0.810577] [<c00308b0>] (omap_hwmod_enable+0x28/0x40) from [<c0030f8c>] (omap_device_enable+0x3c/0x80)
[ 0.810607] [<c0030f8c>] (omap_device_enable+0x3c/0x80) from [<c0030fe0>] (_od_runtime_resume+0x10/0x1c)
[ 0.810638] [<c0030fe0>] (_od_runtime_resume+0x10/0x1c) from [<c036e120>] (__rpm_callback+0x2c/0x80)
[ 0.810668] [<c036e120>] (__rpm_callback+0x2c/0x80) from [<c036e198>] (rpm_callback+0x24/0x78)
[ 0.810699] [<c036e198>] (rpm_callback+0x24/0x78) from [<c036f444>] (rpm_resume+0x3c0/0x60c)
[ 0.810729] [<c036f444>] (rpm_resume+0x3c0/0x60c) from [<c036f970>] (__pm_runtime_resume+0x4c/0x68)
[ 0.810760] [<c036f970>] (__pm_runtime_resume+0x4c/0x68) from [<c0044954>] (omap_dm_timer_probe+0x234/0x334)
[ 0.810791] [<c0044954>] (omap_dm_timer_probe+0x234/0x334) from [<c03659ac>] (platform_drv_probe+0x1c/0x24)
[ 0.810821] [<c03659ac>] (platform_drv_probe+0x1c/0x24) from [<c03645e4>] (really_probe+0x70/0x200)
[ 0.810852] [<c03645e4>] (really_probe+0x70/0x200) from [<c03647a8>] (driver_probe_device+0x34/0x50)
[ 0.810852] [<c03647a8>] (driver_probe_device+0x34/0x50) from [<c0364858>] (__driver_attach+0x94/0x98)
[ 0.810882] [<c0364858>] (__driver_attach+0x94/0x98) from [<c0362cd4>] (bus_for_each_dev+0x74/0x98)
[ 0.810913] [<c0362cd4>] (bus_for_each_dev+0x74/0x98) from [<c0363510>] (bus_add_driver+0xe8/0x278)
[ 0.810943] [<c0363510>] (bus_add_driver+0xe8/0x278) from [<c0364e30>] (driver_register+0x5c/0xf8)
[ 0.810974] [<c0364e30>] (driver_register+0x5c/0xf8) from [<c00087ac>] (do_one_initcall+0x2c/0x150)
[ 0.811004] [<c00087ac>] (do_one_initcall+0x2c/0x150) from [<c0797508>] (do_basic_setup+0x94/0xd0)
[ 0.811035] [<c0797508>] (do_basic_setup+0x94/0xd0) from [<c07975c0>] (kernel_init_freeable+0x7c/0x120)
[ 0.811065] [<c07975c0>] (kernel_init_freeable+0x7c/0x120) from [<c05526b4>] (kernel_init+0xc/0x164)
[ 0.811096] [<c05526b4>] (kernel_init+0xc/0x164) from [<c00149c8>] (ret_from_fork+0x14/0x2c)
[ 0.811126] ---[ end trace 1b75b31a2719ed1d ]---
[ 0.811889] ------------[ cut here ]------------
[ 0.811920] WARNING: CPU: 0 PID: 46 at arch/arm/mach-omap2/omap_hwmod.c:2224 _idle+0xd4/0xf8()
[ 0.811920] omap_hwmod: timer12: idle state can only be entered from enabled state
[ 0.811950] Modules linked in:
[ 0.811981] CPU: 0 PID: 46 Comm: kworker/0:1 Tainted: G W 3.12.0-rc2-00020-gdea1778-dirty #791
[ 0.812011] Workqueue: pm pm_runtime_work
[ 0.812042] [<c001cd54>] (unwind_backtrace+0x0/0xf4) from [<c0018e80>] (show_stack+0x14/0x1c)
[ 0.812072] [<c0018e80>] (show_stack+0x14/0x1c) from [<c0554400>] (dump_stack+0x6c/0x9c)
[ 0.812103] [<c0554400>] (dump_stack+0x6c/0x9c) from [<c00488a8>] (warn_slowpath_common+0x64/0x84)
[ 0.812133] [<c00488a8>] (warn_slowpath_common+0x64/0x84) from [<c004895c>] (warn_slowpath_fmt+0x30/0x40)
[ 0.812164] [<c004895c>] (warn_slowpath_fmt+0x30/0x40) from [<c003099c>] (_idle+0xd4/0xf8)
[ 0.812194] [<c003099c>] (_idle+0xd4/0xf8) from [<c0030c9c>] (omap_hwmod_idle+0x28/0x3c)
[ 0.812225] [<c0030c9c>] (omap_hwmod_idle+0x28/0x3c) from [<c0030e6c>] (omap_device_idle+0x3c/0x80)
[ 0.812225] [<c0030e6c>] (omap_device_idle+0x3c/0x80) from [<c0030ed0>] (_od_runtime_suspend+0x20/0x2c)
[ 0.812255] [<c0030ed0>] (_od_runtime_suspend+0x20/0x2c) from [<c036e120>] (__rpm_callback+0x2c/0x80)
[ 0.812286] [<c036e120>] (__rpm_callback+0x2c/0x80) from [<c036e198>] (rpm_callback+0x24/0x78)
[ 0.812316] [<c036e198>] (rpm_callback+0x24/0x78) from [<c036e5bc>] (rpm_suspend+0xf4/0x5e4)
[ 0.812347] [<c036e5bc>] (rpm_suspend+0xf4/0x5e4) from [<c036fb78>] (pm_runtime_work+0x80/0xa4)
[ 0.812377] [<c036fb78>] (pm_runtime_work+0x80/0xa4) from [<c0064058>] (process_one_work+0x204/0x594)
[ 0.812408] [<c0064058>] (process_one_work+0x204/0x594) from [<c0064530>] (worker_thread+0x148/0x480)
[ 0.812438] [<c0064530>] (worker_thread+0x148/0x480) from [<c0069c20>] (kthread+0xa0/0xac)
[ 0.812469] [<c0069c20>] (kthread+0xa0/0xac) from [<c00149c8>] (ret_from_fork+0x14/0x2c)
[ 0.812499] ---[ end trace 1b75b31a2719ed1e ]---
[ 2.595031] ------------[ cut here ]------------
[ 2.599945] WARNING: CPU: 0 PID: 1 at arch/arm/mach-omap2/omap_hwmod.c:2126 _enable+0x254/0x280()
[ 2.609313] omap_hwmod: uart4: enabled state can only be entered from initialized, idle, or disabled state
[ 2.619506] Modules linked in:
[ 2.622772] CPU: 0 PID: 1 Comm: swapper/0 Tainted: G W 3.12.0-rc2-00020-gdea1778-dirty #791
[ 2.632537] [<c001cd54>] (unwind_backtrace+0x0/0xf4) from [<c0018e80>] (show_stack+0x14/0x1c)
[ 2.641540] [<c0018e80>] (show_stack+0x14/0x1c) from [<c0554400>] (dump_stack+0x6c/0x9c)
[ 2.650115] [<c0554400>] (dump_stack+0x6c/0x9c) from [<c00488a8>] (warn_slowpath_common+0x64/0x84)
[ 2.659576] [<c00488a8>] (warn_slowpath_common+0x64/0x84) from [<c004895c>] (warn_slowpath_fmt+0x30/0x40)
[ 2.669708] [<c004895c>] (warn_slowpath_fmt+0x30/0x40) from [<c003085c>] (_enable+0x254/0x280)
[ 2.678802] [<c003085c>] (_enable+0x254/0x280) from [<c00308b0>] (omap_hwmod_enable+0x28/0x40)
[ 2.687927] [<c00308b0>] (omap_hwmod_enable+0x28/0x40) from [<c0030f8c>] (omap_device_enable+0x3c/0x80)
[ 2.697875] [<c0030f8c>] (omap_device_enable+0x3c/0x80) from [<c0030fe0>] (_od_runtime_resume+0x10/0x1c)
[ 2.707916] [<c0030fe0>] (_od_runtime_resume+0x10/0x1c) from [<c036e120>] (__rpm_callback+0x2c/0x80)
[ 2.717559] [<c036e120>] (__rpm_callback+0x2c/0x80) from [<c036e198>] (rpm_callback+0x24/0x78)
[ 2.726684] [<c036e198>] (rpm_callback+0x24/0x78) from [<c036f444>] (rpm_resume+0x3c0/0x60c)
[ 2.735595] [<c036f444>] (rpm_resume+0x3c0/0x60c) from [<c036f970>] (__pm_runtime_resume+0x4c/0x68)
[ 2.745178] [<c036f970>] (__pm_runtime_resume+0x4c/0x68) from [<c035ae30>] (serial_omap_probe+0x294/0x4fc)
[ 2.755401] [<c035ae30>] (serial_omap_probe+0x294/0x4fc) from [<c03659ac>] (platform_drv_probe+0x1c/0x24)
[ 2.765502] [<c03659ac>] (platform_drv_probe+0x1c/0x24) from [<c03645e4>] (really_probe+0x70/0x200)
[ 2.775054] [<c03645e4>] (really_probe+0x70/0x200) from [<c03647a8>] (driver_probe_device+0x34/0x50)
[ 2.784729] [<c03647a8>] (driver_probe_device+0x34/0x50) from [<c0364858>] (__driver_attach+0x94/0x98)
[ 2.794555] [<c0364858>] (__driver_attach+0x94/0x98) from [<c0362cd4>] (bus_for_each_dev+0x74/0x98)
[ 2.804138] [<c0362cd4>] (bus_for_each_dev+0x74/0x98) from [<c0363510>] (bus_add_driver+0xe8/0x278)
[ 2.813690] [<c0363510>] (bus_add_driver+0xe8/0x278) from [<c0364e30>] (driver_register+0x5c/0xf8)
[ 2.823181] [<c0364e30>] (driver_register+0x5c/0xf8) from [<c07d0028>] (serial_omap_init+0x28/0x44)
[ 2.832763] [<c07d0028>] (serial_omap_init+0x28/0x44) from [<c00087ac>] (do_one_initcall+0x2c/0x150)
[ 2.842407] [<c00087ac>] (do_one_initcall+0x2c/0x150) from [<c0797508>] (do_basic_setup+0x94/0xd0)
[ 2.851898] [<c0797508>] (do_basic_setup+0x94/0xd0) from [<c07975c0>] (kernel_init_freeable+0x7c/0x120)
[ 2.861846] [<c07975c0>] (kernel_init_freeable+0x7c/0x120) from [<c05526b4>] (kernel_init+0xc/0x164)
[ 2.871490] [<c05526b4>] (kernel_init+0xc/0x164) from [<c00149c8>] (ret_from_fork+0x14/0x2c)
[ 2.880432] ---[ end trace 1b75b31a2719ed1f ]---
^ permalink raw reply [flat|nested] 136+ messages in thread
* [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
@ 2013-10-07 2:15 ` Tony Lindgren
0 siblings, 0 replies; 136+ messages in thread
From: Tony Lindgren @ 2013-10-07 2:15 UTC (permalink / raw)
To: linux-arm-kernel
* Tero Kristo <t-kristo@ti.com> [131004 08:42]:
> Hi,
>
> Just a gentle reminder, anybody have any comments on this series or
> should we start queuing stuff?
Well omap4 seems to work for me just fine, and omap3 in legacy
mode. But looks like omap3 device tree based booting is breaking
after I pulled in your test branch. I get the following on
3630 based dm3730.
Regards,
Tony
[ 0.187652] omap_hwmod: uart4: cannot clk_get main_clk uart4_fck
[ 0.187713] omap_hwmod: uart4: cannot _init_clocks
[ 0.187713] ------------[ cut here ]------------
[ 0.187774] WARNING: CPU: 0 PID: 1 at arch/arm/mach-omap2/omap_hwmod.c:2434 _init+0x6c/0x80()
[ 0.187774] omap_hwmod: uart4: couldn't init clocks
[ 0.187774] Modules linked in:
[ 0.187805] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.12.0-rc2-00020-gdea1778-dirty #791
[ 0.187866] [<c001cd54>] (unwind_backtrace+0x0/0xf4) from [<c0018e80>] (show_stack+0x14/0x1c)
[ 0.187896] [<c0018e80>] (show_stack+0x14/0x1c) from [<c0554400>] (dump_stack+0x6c/0x9c)
[ 0.187927] [<c0554400>] (dump_stack+0x6c/0x9c) from [<c00488a8>] (warn_slowpath_common+0x64/0x84)
[ 0.187957] [<c00488a8>] (warn_slowpath_common+0x64/0x84) from [<c004895c>] (warn_slowpath_fmt+0x30/0x40)
[ 0.187988] [<c004895c>] (warn_slowpath_fmt+0x30/0x40) from [<c07a4bec>] (_init+0x6c/0x80)
[ 0.188018] [<c07a4bec>] (_init+0x6c/0x80) from [<c002e068>] (omap_hwmod_for_each+0x50/0x64)
[ 0.188049] [<c002e068>] (omap_hwmod_for_each+0x50/0x64) from [<c07a5440>] (__omap_hwmod_setup_all+0x34/0x4c)
[ 0.188079] [<c07a5440>] (__omap_hwmod_setup_all+0x34/0x4c) from [<c00087ac>] (do_one_initcall+0x2c/0x150)
[ 0.188110] [<c00087ac>] (do_one_initcall+0x2c/0x150) from [<c0797508>] (do_basic_setup+0x94/0xd0)
[ 0.188140] [<c0797508>] (do_basic_setup+0x94/0xd0) from [<c07975c0>] (kernel_init_freeable+0x7c/0x120)
[ 0.188171] [<c07975c0>] (kernel_init_freeable+0x7c/0x120) from [<c05526b4>] (kernel_init+0xc/0x164)
[ 0.188201] [<c05526b4>] (kernel_init+0xc/0x164) from [<c00149c8>] (ret_from_fork+0x14/0x2c)
[ 0.188415] ---[ end trace 1b75b31a2719ed1c ]---
[ 0.810241] ------------[ cut here ]------------
[ 0.810302] WARNING: CPU: 0 PID: 1 at arch/arm/mach-omap2/omap_hwmod.c:2126 _enable+0x254/0x280()
[ 0.810302] omap_hwmod: timer12: enabled state can only be entered from initialized, idle, or disabled state
[ 0.810333] Modules linked in:
[ 0.810363] CPU: 0 PID: 1 Comm: swapper/0 Tainted: G W 3.12.0-rc2-00020-gdea1778-dirty #791
[ 0.810394] [<c001cd54>] (unwind_backtrace+0x0/0xf4) from [<c0018e80>] (show_stack+0x14/0x1c)
[ 0.810424] [<c0018e80>] (show_stack+0x14/0x1c) from [<c0554400>] (dump_stack+0x6c/0x9c)
[ 0.810455] [<c0554400>] (dump_stack+0x6c/0x9c) from [<c00488a8>] (warn_slowpath_common+0x64/0x84)
[ 0.810485] [<c00488a8>] (warn_slowpath_common+0x64/0x84) from [<c004895c>] (warn_slowpath_fmt+0x30/0x40)
[ 0.810516] [<c004895c>] (warn_slowpath_fmt+0x30/0x40) from [<c003085c>] (_enable+0x254/0x280)
[ 0.810546] [<c003085c>] (_enable+0x254/0x280) from [<c00308b0>] (omap_hwmod_enable+0x28/0x40)
[ 0.810577] [<c00308b0>] (omap_hwmod_enable+0x28/0x40) from [<c0030f8c>] (omap_device_enable+0x3c/0x80)
[ 0.810607] [<c0030f8c>] (omap_device_enable+0x3c/0x80) from [<c0030fe0>] (_od_runtime_resume+0x10/0x1c)
[ 0.810638] [<c0030fe0>] (_od_runtime_resume+0x10/0x1c) from [<c036e120>] (__rpm_callback+0x2c/0x80)
[ 0.810668] [<c036e120>] (__rpm_callback+0x2c/0x80) from [<c036e198>] (rpm_callback+0x24/0x78)
[ 0.810699] [<c036e198>] (rpm_callback+0x24/0x78) from [<c036f444>] (rpm_resume+0x3c0/0x60c)
[ 0.810729] [<c036f444>] (rpm_resume+0x3c0/0x60c) from [<c036f970>] (__pm_runtime_resume+0x4c/0x68)
[ 0.810760] [<c036f970>] (__pm_runtime_resume+0x4c/0x68) from [<c0044954>] (omap_dm_timer_probe+0x234/0x334)
[ 0.810791] [<c0044954>] (omap_dm_timer_probe+0x234/0x334) from [<c03659ac>] (platform_drv_probe+0x1c/0x24)
[ 0.810821] [<c03659ac>] (platform_drv_probe+0x1c/0x24) from [<c03645e4>] (really_probe+0x70/0x200)
[ 0.810852] [<c03645e4>] (really_probe+0x70/0x200) from [<c03647a8>] (driver_probe_device+0x34/0x50)
[ 0.810852] [<c03647a8>] (driver_probe_device+0x34/0x50) from [<c0364858>] (__driver_attach+0x94/0x98)
[ 0.810882] [<c0364858>] (__driver_attach+0x94/0x98) from [<c0362cd4>] (bus_for_each_dev+0x74/0x98)
[ 0.810913] [<c0362cd4>] (bus_for_each_dev+0x74/0x98) from [<c0363510>] (bus_add_driver+0xe8/0x278)
[ 0.810943] [<c0363510>] (bus_add_driver+0xe8/0x278) from [<c0364e30>] (driver_register+0x5c/0xf8)
[ 0.810974] [<c0364e30>] (driver_register+0x5c/0xf8) from [<c00087ac>] (do_one_initcall+0x2c/0x150)
[ 0.811004] [<c00087ac>] (do_one_initcall+0x2c/0x150) from [<c0797508>] (do_basic_setup+0x94/0xd0)
[ 0.811035] [<c0797508>] (do_basic_setup+0x94/0xd0) from [<c07975c0>] (kernel_init_freeable+0x7c/0x120)
[ 0.811065] [<c07975c0>] (kernel_init_freeable+0x7c/0x120) from [<c05526b4>] (kernel_init+0xc/0x164)
[ 0.811096] [<c05526b4>] (kernel_init+0xc/0x164) from [<c00149c8>] (ret_from_fork+0x14/0x2c)
[ 0.811126] ---[ end trace 1b75b31a2719ed1d ]---
[ 0.811889] ------------[ cut here ]------------
[ 0.811920] WARNING: CPU: 0 PID: 46 at arch/arm/mach-omap2/omap_hwmod.c:2224 _idle+0xd4/0xf8()
[ 0.811920] omap_hwmod: timer12: idle state can only be entered from enabled state
[ 0.811950] Modules linked in:
[ 0.811981] CPU: 0 PID: 46 Comm: kworker/0:1 Tainted: G W 3.12.0-rc2-00020-gdea1778-dirty #791
[ 0.812011] Workqueue: pm pm_runtime_work
[ 0.812042] [<c001cd54>] (unwind_backtrace+0x0/0xf4) from [<c0018e80>] (show_stack+0x14/0x1c)
[ 0.812072] [<c0018e80>] (show_stack+0x14/0x1c) from [<c0554400>] (dump_stack+0x6c/0x9c)
[ 0.812103] [<c0554400>] (dump_stack+0x6c/0x9c) from [<c00488a8>] (warn_slowpath_common+0x64/0x84)
[ 0.812133] [<c00488a8>] (warn_slowpath_common+0x64/0x84) from [<c004895c>] (warn_slowpath_fmt+0x30/0x40)
[ 0.812164] [<c004895c>] (warn_slowpath_fmt+0x30/0x40) from [<c003099c>] (_idle+0xd4/0xf8)
[ 0.812194] [<c003099c>] (_idle+0xd4/0xf8) from [<c0030c9c>] (omap_hwmod_idle+0x28/0x3c)
[ 0.812225] [<c0030c9c>] (omap_hwmod_idle+0x28/0x3c) from [<c0030e6c>] (omap_device_idle+0x3c/0x80)
[ 0.812225] [<c0030e6c>] (omap_device_idle+0x3c/0x80) from [<c0030ed0>] (_od_runtime_suspend+0x20/0x2c)
[ 0.812255] [<c0030ed0>] (_od_runtime_suspend+0x20/0x2c) from [<c036e120>] (__rpm_callback+0x2c/0x80)
[ 0.812286] [<c036e120>] (__rpm_callback+0x2c/0x80) from [<c036e198>] (rpm_callback+0x24/0x78)
[ 0.812316] [<c036e198>] (rpm_callback+0x24/0x78) from [<c036e5bc>] (rpm_suspend+0xf4/0x5e4)
[ 0.812347] [<c036e5bc>] (rpm_suspend+0xf4/0x5e4) from [<c036fb78>] (pm_runtime_work+0x80/0xa4)
[ 0.812377] [<c036fb78>] (pm_runtime_work+0x80/0xa4) from [<c0064058>] (process_one_work+0x204/0x594)
[ 0.812408] [<c0064058>] (process_one_work+0x204/0x594) from [<c0064530>] (worker_thread+0x148/0x480)
[ 0.812438] [<c0064530>] (worker_thread+0x148/0x480) from [<c0069c20>] (kthread+0xa0/0xac)
[ 0.812469] [<c0069c20>] (kthread+0xa0/0xac) from [<c00149c8>] (ret_from_fork+0x14/0x2c)
[ 0.812499] ---[ end trace 1b75b31a2719ed1e ]---
[ 2.595031] ------------[ cut here ]------------
[ 2.599945] WARNING: CPU: 0 PID: 1 at arch/arm/mach-omap2/omap_hwmod.c:2126 _enable+0x254/0x280()
[ 2.609313] omap_hwmod: uart4: enabled state can only be entered from initialized, idle, or disabled state
[ 2.619506] Modules linked in:
[ 2.622772] CPU: 0 PID: 1 Comm: swapper/0 Tainted: G W 3.12.0-rc2-00020-gdea1778-dirty #791
[ 2.632537] [<c001cd54>] (unwind_backtrace+0x0/0xf4) from [<c0018e80>] (show_stack+0x14/0x1c)
[ 2.641540] [<c0018e80>] (show_stack+0x14/0x1c) from [<c0554400>] (dump_stack+0x6c/0x9c)
[ 2.650115] [<c0554400>] (dump_stack+0x6c/0x9c) from [<c00488a8>] (warn_slowpath_common+0x64/0x84)
[ 2.659576] [<c00488a8>] (warn_slowpath_common+0x64/0x84) from [<c004895c>] (warn_slowpath_fmt+0x30/0x40)
[ 2.669708] [<c004895c>] (warn_slowpath_fmt+0x30/0x40) from [<c003085c>] (_enable+0x254/0x280)
[ 2.678802] [<c003085c>] (_enable+0x254/0x280) from [<c00308b0>] (omap_hwmod_enable+0x28/0x40)
[ 2.687927] [<c00308b0>] (omap_hwmod_enable+0x28/0x40) from [<c0030f8c>] (omap_device_enable+0x3c/0x80)
[ 2.697875] [<c0030f8c>] (omap_device_enable+0x3c/0x80) from [<c0030fe0>] (_od_runtime_resume+0x10/0x1c)
[ 2.707916] [<c0030fe0>] (_od_runtime_resume+0x10/0x1c) from [<c036e120>] (__rpm_callback+0x2c/0x80)
[ 2.717559] [<c036e120>] (__rpm_callback+0x2c/0x80) from [<c036e198>] (rpm_callback+0x24/0x78)
[ 2.726684] [<c036e198>] (rpm_callback+0x24/0x78) from [<c036f444>] (rpm_resume+0x3c0/0x60c)
[ 2.735595] [<c036f444>] (rpm_resume+0x3c0/0x60c) from [<c036f970>] (__pm_runtime_resume+0x4c/0x68)
[ 2.745178] [<c036f970>] (__pm_runtime_resume+0x4c/0x68) from [<c035ae30>] (serial_omap_probe+0x294/0x4fc)
[ 2.755401] [<c035ae30>] (serial_omap_probe+0x294/0x4fc) from [<c03659ac>] (platform_drv_probe+0x1c/0x24)
[ 2.765502] [<c03659ac>] (platform_drv_probe+0x1c/0x24) from [<c03645e4>] (really_probe+0x70/0x200)
[ 2.775054] [<c03645e4>] (really_probe+0x70/0x200) from [<c03647a8>] (driver_probe_device+0x34/0x50)
[ 2.784729] [<c03647a8>] (driver_probe_device+0x34/0x50) from [<c0364858>] (__driver_attach+0x94/0x98)
[ 2.794555] [<c0364858>] (__driver_attach+0x94/0x98) from [<c0362cd4>] (bus_for_each_dev+0x74/0x98)
[ 2.804138] [<c0362cd4>] (bus_for_each_dev+0x74/0x98) from [<c0363510>] (bus_add_driver+0xe8/0x278)
[ 2.813690] [<c0363510>] (bus_add_driver+0xe8/0x278) from [<c0364e30>] (driver_register+0x5c/0xf8)
[ 2.823181] [<c0364e30>] (driver_register+0x5c/0xf8) from [<c07d0028>] (serial_omap_init+0x28/0x44)
[ 2.832763] [<c07d0028>] (serial_omap_init+0x28/0x44) from [<c00087ac>] (do_one_initcall+0x2c/0x150)
[ 2.842407] [<c00087ac>] (do_one_initcall+0x2c/0x150) from [<c0797508>] (do_basic_setup+0x94/0xd0)
[ 2.851898] [<c0797508>] (do_basic_setup+0x94/0xd0) from [<c07975c0>] (kernel_init_freeable+0x7c/0x120)
[ 2.861846] [<c07975c0>] (kernel_init_freeable+0x7c/0x120) from [<c05526b4>] (kernel_init+0xc/0x164)
[ 2.871490] [<c05526b4>] (kernel_init+0xc/0x164) from [<c00149c8>] (ret_from_fork+0x14/0x2c)
[ 2.880432] ---[ end trace 1b75b31a2719ed1f ]---
^ permalink raw reply [flat|nested] 136+ messages in thread
* Re: [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
2013-10-07 2:15 ` Tony Lindgren
@ 2013-10-07 6:35 ` Tero Kristo
-1 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-10-07 6:35 UTC (permalink / raw)
To: Tony Lindgren
Cc: linux-omap, paul, nm, rnayak, bcousson, mturquette,
linux-arm-kernel, devicetree
On 10/07/2013 05:15 AM, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [131004 08:42]:
>> Hi,
>>
>> Just a gentle reminder, anybody have any comments on this series or
>> should we start queuing stuff?
>
> Well omap4 seems to work for me just fine, and omap3 in legacy
> mode. But looks like omap3 device tree based booting is breaking
> after I pulled in your test branch. I get the following on
> 3630 based dm3730.
Uart4 breaks because of the issue with basic DT blobs. You need at least
this patch:
http://linux-kernel.2935.n7.nabble.com/RFC-PATCH-ARM-OMAP3630-Add-generic-machine-descriptor-td722791.html
... from Nishanth to get it to work right. Otherwise the clock init
tries to use omap3430 clock data for omap3630 which leaves uart4 nodes out.
-Tero
>
> Regards,
>
> Tony
>
>
> [ 0.187652] omap_hwmod: uart4: cannot clk_get main_clk uart4_fck
> [ 0.187713] omap_hwmod: uart4: cannot _init_clocks
> [ 0.187713] ------------[ cut here ]------------
> [ 0.187774] WARNING: CPU: 0 PID: 1 at arch/arm/mach-omap2/omap_hwmod.c:2434 _init+0x6c/0x80()
> [ 0.187774] omap_hwmod: uart4: couldn't init clocks
> [ 0.187774] Modules linked in:
> [ 0.187805] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.12.0-rc2-00020-gdea1778-dirty #791
> [ 0.187866] [<c001cd54>] (unwind_backtrace+0x0/0xf4) from [<c0018e80>] (show_stack+0x14/0x1c)
> [ 0.187896] [<c0018e80>] (show_stack+0x14/0x1c) from [<c0554400>] (dump_stack+0x6c/0x9c)
> [ 0.187927] [<c0554400>] (dump_stack+0x6c/0x9c) from [<c00488a8>] (warn_slowpath_common+0x64/0x84)
> [ 0.187957] [<c00488a8>] (warn_slowpath_common+0x64/0x84) from [<c004895c>] (warn_slowpath_fmt+0x30/0x40)
> [ 0.187988] [<c004895c>] (warn_slowpath_fmt+0x30/0x40) from [<c07a4bec>] (_init+0x6c/0x80)
> [ 0.188018] [<c07a4bec>] (_init+0x6c/0x80) from [<c002e068>] (omap_hwmod_for_each+0x50/0x64)
> [ 0.188049] [<c002e068>] (omap_hwmod_for_each+0x50/0x64) from [<c07a5440>] (__omap_hwmod_setup_all+0x34/0x4c)
> [ 0.188079] [<c07a5440>] (__omap_hwmod_setup_all+0x34/0x4c) from [<c00087ac>] (do_one_initcall+0x2c/0x150)
> [ 0.188110] [<c00087ac>] (do_one_initcall+0x2c/0x150) from [<c0797508>] (do_basic_setup+0x94/0xd0)
> [ 0.188140] [<c0797508>] (do_basic_setup+0x94/0xd0) from [<c07975c0>] (kernel_init_freeable+0x7c/0x120)
> [ 0.188171] [<c07975c0>] (kernel_init_freeable+0x7c/0x120) from [<c05526b4>] (kernel_init+0xc/0x164)
> [ 0.188201] [<c05526b4>] (kernel_init+0xc/0x164) from [<c00149c8>] (ret_from_fork+0x14/0x2c)
> [ 0.188415] ---[ end trace 1b75b31a2719ed1c ]---
>
> [ 0.810241] ------------[ cut here ]------------
> [ 0.810302] WARNING: CPU: 0 PID: 1 at arch/arm/mach-omap2/omap_hwmod.c:2126 _enable+0x254/0x280()
> [ 0.810302] omap_hwmod: timer12: enabled state can only be entered from initialized, idle, or disabled state
> [ 0.810333] Modules linked in:
> [ 0.810363] CPU: 0 PID: 1 Comm: swapper/0 Tainted: G W 3.12.0-rc2-00020-gdea1778-dirty #791
> [ 0.810394] [<c001cd54>] (unwind_backtrace+0x0/0xf4) from [<c0018e80>] (show_stack+0x14/0x1c)
> [ 0.810424] [<c0018e80>] (show_stack+0x14/0x1c) from [<c0554400>] (dump_stack+0x6c/0x9c)
> [ 0.810455] [<c0554400>] (dump_stack+0x6c/0x9c) from [<c00488a8>] (warn_slowpath_common+0x64/0x84)
> [ 0.810485] [<c00488a8>] (warn_slowpath_common+0x64/0x84) from [<c004895c>] (warn_slowpath_fmt+0x30/0x40)
> [ 0.810516] [<c004895c>] (warn_slowpath_fmt+0x30/0x40) from [<c003085c>] (_enable+0x254/0x280)
> [ 0.810546] [<c003085c>] (_enable+0x254/0x280) from [<c00308b0>] (omap_hwmod_enable+0x28/0x40)
> [ 0.810577] [<c00308b0>] (omap_hwmod_enable+0x28/0x40) from [<c0030f8c>] (omap_device_enable+0x3c/0x80)
> [ 0.810607] [<c0030f8c>] (omap_device_enable+0x3c/0x80) from [<c0030fe0>] (_od_runtime_resume+0x10/0x1c)
> [ 0.810638] [<c0030fe0>] (_od_runtime_resume+0x10/0x1c) from [<c036e120>] (__rpm_callback+0x2c/0x80)
> [ 0.810668] [<c036e120>] (__rpm_callback+0x2c/0x80) from [<c036e198>] (rpm_callback+0x24/0x78)
> [ 0.810699] [<c036e198>] (rpm_callback+0x24/0x78) from [<c036f444>] (rpm_resume+0x3c0/0x60c)
> [ 0.810729] [<c036f444>] (rpm_resume+0x3c0/0x60c) from [<c036f970>] (__pm_runtime_resume+0x4c/0x68)
> [ 0.810760] [<c036f970>] (__pm_runtime_resume+0x4c/0x68) from [<c0044954>] (omap_dm_timer_probe+0x234/0x334)
> [ 0.810791] [<c0044954>] (omap_dm_timer_probe+0x234/0x334) from [<c03659ac>] (platform_drv_probe+0x1c/0x24)
> [ 0.810821] [<c03659ac>] (platform_drv_probe+0x1c/0x24) from [<c03645e4>] (really_probe+0x70/0x200)
> [ 0.810852] [<c03645e4>] (really_probe+0x70/0x200) from [<c03647a8>] (driver_probe_device+0x34/0x50)
> [ 0.810852] [<c03647a8>] (driver_probe_device+0x34/0x50) from [<c0364858>] (__driver_attach+0x94/0x98)
> [ 0.810882] [<c0364858>] (__driver_attach+0x94/0x98) from [<c0362cd4>] (bus_for_each_dev+0x74/0x98)
> [ 0.810913] [<c0362cd4>] (bus_for_each_dev+0x74/0x98) from [<c0363510>] (bus_add_driver+0xe8/0x278)
> [ 0.810943] [<c0363510>] (bus_add_driver+0xe8/0x278) from [<c0364e30>] (driver_register+0x5c/0xf8)
> [ 0.810974] [<c0364e30>] (driver_register+0x5c/0xf8) from [<c00087ac>] (do_one_initcall+0x2c/0x150)
> [ 0.811004] [<c00087ac>] (do_one_initcall+0x2c/0x150) from [<c0797508>] (do_basic_setup+0x94/0xd0)
> [ 0.811035] [<c0797508>] (do_basic_setup+0x94/0xd0) from [<c07975c0>] (kernel_init_freeable+0x7c/0x120)
> [ 0.811065] [<c07975c0>] (kernel_init_freeable+0x7c/0x120) from [<c05526b4>] (kernel_init+0xc/0x164)
> [ 0.811096] [<c05526b4>] (kernel_init+0xc/0x164) from [<c00149c8>] (ret_from_fork+0x14/0x2c)
> [ 0.811126] ---[ end trace 1b75b31a2719ed1d ]---
>
> [ 0.811889] ------------[ cut here ]------------
> [ 0.811920] WARNING: CPU: 0 PID: 46 at arch/arm/mach-omap2/omap_hwmod.c:2224 _idle+0xd4/0xf8()
> [ 0.811920] omap_hwmod: timer12: idle state can only be entered from enabled state
> [ 0.811950] Modules linked in:
> [ 0.811981] CPU: 0 PID: 46 Comm: kworker/0:1 Tainted: G W 3.12.0-rc2-00020-gdea1778-dirty #791
> [ 0.812011] Workqueue: pm pm_runtime_work
> [ 0.812042] [<c001cd54>] (unwind_backtrace+0x0/0xf4) from [<c0018e80>] (show_stack+0x14/0x1c)
> [ 0.812072] [<c0018e80>] (show_stack+0x14/0x1c) from [<c0554400>] (dump_stack+0x6c/0x9c)
> [ 0.812103] [<c0554400>] (dump_stack+0x6c/0x9c) from [<c00488a8>] (warn_slowpath_common+0x64/0x84)
> [ 0.812133] [<c00488a8>] (warn_slowpath_common+0x64/0x84) from [<c004895c>] (warn_slowpath_fmt+0x30/0x40)
> [ 0.812164] [<c004895c>] (warn_slowpath_fmt+0x30/0x40) from [<c003099c>] (_idle+0xd4/0xf8)
> [ 0.812194] [<c003099c>] (_idle+0xd4/0xf8) from [<c0030c9c>] (omap_hwmod_idle+0x28/0x3c)
> [ 0.812225] [<c0030c9c>] (omap_hwmod_idle+0x28/0x3c) from [<c0030e6c>] (omap_device_idle+0x3c/0x80)
> [ 0.812225] [<c0030e6c>] (omap_device_idle+0x3c/0x80) from [<c0030ed0>] (_od_runtime_suspend+0x20/0x2c)
> [ 0.812255] [<c0030ed0>] (_od_runtime_suspend+0x20/0x2c) from [<c036e120>] (__rpm_callback+0x2c/0x80)
> [ 0.812286] [<c036e120>] (__rpm_callback+0x2c/0x80) from [<c036e198>] (rpm_callback+0x24/0x78)
> [ 0.812316] [<c036e198>] (rpm_callback+0x24/0x78) from [<c036e5bc>] (rpm_suspend+0xf4/0x5e4)
> [ 0.812347] [<c036e5bc>] (rpm_suspend+0xf4/0x5e4) from [<c036fb78>] (pm_runtime_work+0x80/0xa4)
> [ 0.812377] [<c036fb78>] (pm_runtime_work+0x80/0xa4) from [<c0064058>] (process_one_work+0x204/0x594)
> [ 0.812408] [<c0064058>] (process_one_work+0x204/0x594) from [<c0064530>] (worker_thread+0x148/0x480)
> [ 0.812438] [<c0064530>] (worker_thread+0x148/0x480) from [<c0069c20>] (kthread+0xa0/0xac)
> [ 0.812469] [<c0069c20>] (kthread+0xa0/0xac) from [<c00149c8>] (ret_from_fork+0x14/0x2c)
> [ 0.812499] ---[ end trace 1b75b31a2719ed1e ]---
>
>
> [ 2.595031] ------------[ cut here ]------------
> [ 2.599945] WARNING: CPU: 0 PID: 1 at arch/arm/mach-omap2/omap_hwmod.c:2126 _enable+0x254/0x280()
> [ 2.609313] omap_hwmod: uart4: enabled state can only be entered from initialized, idle, or disabled state
> [ 2.619506] Modules linked in:
> [ 2.622772] CPU: 0 PID: 1 Comm: swapper/0 Tainted: G W 3.12.0-rc2-00020-gdea1778-dirty #791
> [ 2.632537] [<c001cd54>] (unwind_backtrace+0x0/0xf4) from [<c0018e80>] (show_stack+0x14/0x1c)
> [ 2.641540] [<c0018e80>] (show_stack+0x14/0x1c) from [<c0554400>] (dump_stack+0x6c/0x9c)
> [ 2.650115] [<c0554400>] (dump_stack+0x6c/0x9c) from [<c00488a8>] (warn_slowpath_common+0x64/0x84)
> [ 2.659576] [<c00488a8>] (warn_slowpath_common+0x64/0x84) from [<c004895c>] (warn_slowpath_fmt+0x30/0x40)
> [ 2.669708] [<c004895c>] (warn_slowpath_fmt+0x30/0x40) from [<c003085c>] (_enable+0x254/0x280)
> [ 2.678802] [<c003085c>] (_enable+0x254/0x280) from [<c00308b0>] (omap_hwmod_enable+0x28/0x40)
> [ 2.687927] [<c00308b0>] (omap_hwmod_enable+0x28/0x40) from [<c0030f8c>] (omap_device_enable+0x3c/0x80)
> [ 2.697875] [<c0030f8c>] (omap_device_enable+0x3c/0x80) from [<c0030fe0>] (_od_runtime_resume+0x10/0x1c)
> [ 2.707916] [<c0030fe0>] (_od_runtime_resume+0x10/0x1c) from [<c036e120>] (__rpm_callback+0x2c/0x80)
> [ 2.717559] [<c036e120>] (__rpm_callback+0x2c/0x80) from [<c036e198>] (rpm_callback+0x24/0x78)
> [ 2.726684] [<c036e198>] (rpm_callback+0x24/0x78) from [<c036f444>] (rpm_resume+0x3c0/0x60c)
> [ 2.735595] [<c036f444>] (rpm_resume+0x3c0/0x60c) from [<c036f970>] (__pm_runtime_resume+0x4c/0x68)
> [ 2.745178] [<c036f970>] (__pm_runtime_resume+0x4c/0x68) from [<c035ae30>] (serial_omap_probe+0x294/0x4fc)
> [ 2.755401] [<c035ae30>] (serial_omap_probe+0x294/0x4fc) from [<c03659ac>] (platform_drv_probe+0x1c/0x24)
> [ 2.765502] [<c03659ac>] (platform_drv_probe+0x1c/0x24) from [<c03645e4>] (really_probe+0x70/0x200)
> [ 2.775054] [<c03645e4>] (really_probe+0x70/0x200) from [<c03647a8>] (driver_probe_device+0x34/0x50)
> [ 2.784729] [<c03647a8>] (driver_probe_device+0x34/0x50) from [<c0364858>] (__driver_attach+0x94/0x98)
> [ 2.794555] [<c0364858>] (__driver_attach+0x94/0x98) from [<c0362cd4>] (bus_for_each_dev+0x74/0x98)
> [ 2.804138] [<c0362cd4>] (bus_for_each_dev+0x74/0x98) from [<c0363510>] (bus_add_driver+0xe8/0x278)
> [ 2.813690] [<c0363510>] (bus_add_driver+0xe8/0x278) from [<c0364e30>] (driver_register+0x5c/0xf8)
> [ 2.823181] [<c0364e30>] (driver_register+0x5c/0xf8) from [<c07d0028>] (serial_omap_init+0x28/0x44)
> [ 2.832763] [<c07d0028>] (serial_omap_init+0x28/0x44) from [<c00087ac>] (do_one_initcall+0x2c/0x150)
> [ 2.842407] [<c00087ac>] (do_one_initcall+0x2c/0x150) from [<c0797508>] (do_basic_setup+0x94/0xd0)
> [ 2.851898] [<c0797508>] (do_basic_setup+0x94/0xd0) from [<c07975c0>] (kernel_init_freeable+0x7c/0x120)
> [ 2.861846] [<c07975c0>] (kernel_init_freeable+0x7c/0x120) from [<c05526b4>] (kernel_init+0xc/0x164)
> [ 2.871490] [<c05526b4>] (kernel_init+0xc/0x164) from [<c00149c8>] (ret_from_fork+0x14/0x2c)
> [ 2.880432] ---[ end trace 1b75b31a2719ed1f ]---
>
^ permalink raw reply [flat|nested] 136+ messages in thread
* [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
@ 2013-10-07 6:35 ` Tero Kristo
0 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-10-07 6:35 UTC (permalink / raw)
To: linux-arm-kernel
On 10/07/2013 05:15 AM, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [131004 08:42]:
>> Hi,
>>
>> Just a gentle reminder, anybody have any comments on this series or
>> should we start queuing stuff?
>
> Well omap4 seems to work for me just fine, and omap3 in legacy
> mode. But looks like omap3 device tree based booting is breaking
> after I pulled in your test branch. I get the following on
> 3630 based dm3730.
Uart4 breaks because of the issue with basic DT blobs. You need at least
this patch:
http://linux-kernel.2935.n7.nabble.com/RFC-PATCH-ARM-OMAP3630-Add-generic-machine-descriptor-td722791.html
... from Nishanth to get it to work right. Otherwise the clock init
tries to use omap3430 clock data for omap3630 which leaves uart4 nodes out.
-Tero
>
> Regards,
>
> Tony
>
>
> [ 0.187652] omap_hwmod: uart4: cannot clk_get main_clk uart4_fck
> [ 0.187713] omap_hwmod: uart4: cannot _init_clocks
> [ 0.187713] ------------[ cut here ]------------
> [ 0.187774] WARNING: CPU: 0 PID: 1 at arch/arm/mach-omap2/omap_hwmod.c:2434 _init+0x6c/0x80()
> [ 0.187774] omap_hwmod: uart4: couldn't init clocks
> [ 0.187774] Modules linked in:
> [ 0.187805] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.12.0-rc2-00020-gdea1778-dirty #791
> [ 0.187866] [<c001cd54>] (unwind_backtrace+0x0/0xf4) from [<c0018e80>] (show_stack+0x14/0x1c)
> [ 0.187896] [<c0018e80>] (show_stack+0x14/0x1c) from [<c0554400>] (dump_stack+0x6c/0x9c)
> [ 0.187927] [<c0554400>] (dump_stack+0x6c/0x9c) from [<c00488a8>] (warn_slowpath_common+0x64/0x84)
> [ 0.187957] [<c00488a8>] (warn_slowpath_common+0x64/0x84) from [<c004895c>] (warn_slowpath_fmt+0x30/0x40)
> [ 0.187988] [<c004895c>] (warn_slowpath_fmt+0x30/0x40) from [<c07a4bec>] (_init+0x6c/0x80)
> [ 0.188018] [<c07a4bec>] (_init+0x6c/0x80) from [<c002e068>] (omap_hwmod_for_each+0x50/0x64)
> [ 0.188049] [<c002e068>] (omap_hwmod_for_each+0x50/0x64) from [<c07a5440>] (__omap_hwmod_setup_all+0x34/0x4c)
> [ 0.188079] [<c07a5440>] (__omap_hwmod_setup_all+0x34/0x4c) from [<c00087ac>] (do_one_initcall+0x2c/0x150)
> [ 0.188110] [<c00087ac>] (do_one_initcall+0x2c/0x150) from [<c0797508>] (do_basic_setup+0x94/0xd0)
> [ 0.188140] [<c0797508>] (do_basic_setup+0x94/0xd0) from [<c07975c0>] (kernel_init_freeable+0x7c/0x120)
> [ 0.188171] [<c07975c0>] (kernel_init_freeable+0x7c/0x120) from [<c05526b4>] (kernel_init+0xc/0x164)
> [ 0.188201] [<c05526b4>] (kernel_init+0xc/0x164) from [<c00149c8>] (ret_from_fork+0x14/0x2c)
> [ 0.188415] ---[ end trace 1b75b31a2719ed1c ]---
>
> [ 0.810241] ------------[ cut here ]------------
> [ 0.810302] WARNING: CPU: 0 PID: 1 at arch/arm/mach-omap2/omap_hwmod.c:2126 _enable+0x254/0x280()
> [ 0.810302] omap_hwmod: timer12: enabled state can only be entered from initialized, idle, or disabled state
> [ 0.810333] Modules linked in:
> [ 0.810363] CPU: 0 PID: 1 Comm: swapper/0 Tainted: G W 3.12.0-rc2-00020-gdea1778-dirty #791
> [ 0.810394] [<c001cd54>] (unwind_backtrace+0x0/0xf4) from [<c0018e80>] (show_stack+0x14/0x1c)
> [ 0.810424] [<c0018e80>] (show_stack+0x14/0x1c) from [<c0554400>] (dump_stack+0x6c/0x9c)
> [ 0.810455] [<c0554400>] (dump_stack+0x6c/0x9c) from [<c00488a8>] (warn_slowpath_common+0x64/0x84)
> [ 0.810485] [<c00488a8>] (warn_slowpath_common+0x64/0x84) from [<c004895c>] (warn_slowpath_fmt+0x30/0x40)
> [ 0.810516] [<c004895c>] (warn_slowpath_fmt+0x30/0x40) from [<c003085c>] (_enable+0x254/0x280)
> [ 0.810546] [<c003085c>] (_enable+0x254/0x280) from [<c00308b0>] (omap_hwmod_enable+0x28/0x40)
> [ 0.810577] [<c00308b0>] (omap_hwmod_enable+0x28/0x40) from [<c0030f8c>] (omap_device_enable+0x3c/0x80)
> [ 0.810607] [<c0030f8c>] (omap_device_enable+0x3c/0x80) from [<c0030fe0>] (_od_runtime_resume+0x10/0x1c)
> [ 0.810638] [<c0030fe0>] (_od_runtime_resume+0x10/0x1c) from [<c036e120>] (__rpm_callback+0x2c/0x80)
> [ 0.810668] [<c036e120>] (__rpm_callback+0x2c/0x80) from [<c036e198>] (rpm_callback+0x24/0x78)
> [ 0.810699] [<c036e198>] (rpm_callback+0x24/0x78) from [<c036f444>] (rpm_resume+0x3c0/0x60c)
> [ 0.810729] [<c036f444>] (rpm_resume+0x3c0/0x60c) from [<c036f970>] (__pm_runtime_resume+0x4c/0x68)
> [ 0.810760] [<c036f970>] (__pm_runtime_resume+0x4c/0x68) from [<c0044954>] (omap_dm_timer_probe+0x234/0x334)
> [ 0.810791] [<c0044954>] (omap_dm_timer_probe+0x234/0x334) from [<c03659ac>] (platform_drv_probe+0x1c/0x24)
> [ 0.810821] [<c03659ac>] (platform_drv_probe+0x1c/0x24) from [<c03645e4>] (really_probe+0x70/0x200)
> [ 0.810852] [<c03645e4>] (really_probe+0x70/0x200) from [<c03647a8>] (driver_probe_device+0x34/0x50)
> [ 0.810852] [<c03647a8>] (driver_probe_device+0x34/0x50) from [<c0364858>] (__driver_attach+0x94/0x98)
> [ 0.810882] [<c0364858>] (__driver_attach+0x94/0x98) from [<c0362cd4>] (bus_for_each_dev+0x74/0x98)
> [ 0.810913] [<c0362cd4>] (bus_for_each_dev+0x74/0x98) from [<c0363510>] (bus_add_driver+0xe8/0x278)
> [ 0.810943] [<c0363510>] (bus_add_driver+0xe8/0x278) from [<c0364e30>] (driver_register+0x5c/0xf8)
> [ 0.810974] [<c0364e30>] (driver_register+0x5c/0xf8) from [<c00087ac>] (do_one_initcall+0x2c/0x150)
> [ 0.811004] [<c00087ac>] (do_one_initcall+0x2c/0x150) from [<c0797508>] (do_basic_setup+0x94/0xd0)
> [ 0.811035] [<c0797508>] (do_basic_setup+0x94/0xd0) from [<c07975c0>] (kernel_init_freeable+0x7c/0x120)
> [ 0.811065] [<c07975c0>] (kernel_init_freeable+0x7c/0x120) from [<c05526b4>] (kernel_init+0xc/0x164)
> [ 0.811096] [<c05526b4>] (kernel_init+0xc/0x164) from [<c00149c8>] (ret_from_fork+0x14/0x2c)
> [ 0.811126] ---[ end trace 1b75b31a2719ed1d ]---
>
> [ 0.811889] ------------[ cut here ]------------
> [ 0.811920] WARNING: CPU: 0 PID: 46 at arch/arm/mach-omap2/omap_hwmod.c:2224 _idle+0xd4/0xf8()
> [ 0.811920] omap_hwmod: timer12: idle state can only be entered from enabled state
> [ 0.811950] Modules linked in:
> [ 0.811981] CPU: 0 PID: 46 Comm: kworker/0:1 Tainted: G W 3.12.0-rc2-00020-gdea1778-dirty #791
> [ 0.812011] Workqueue: pm pm_runtime_work
> [ 0.812042] [<c001cd54>] (unwind_backtrace+0x0/0xf4) from [<c0018e80>] (show_stack+0x14/0x1c)
> [ 0.812072] [<c0018e80>] (show_stack+0x14/0x1c) from [<c0554400>] (dump_stack+0x6c/0x9c)
> [ 0.812103] [<c0554400>] (dump_stack+0x6c/0x9c) from [<c00488a8>] (warn_slowpath_common+0x64/0x84)
> [ 0.812133] [<c00488a8>] (warn_slowpath_common+0x64/0x84) from [<c004895c>] (warn_slowpath_fmt+0x30/0x40)
> [ 0.812164] [<c004895c>] (warn_slowpath_fmt+0x30/0x40) from [<c003099c>] (_idle+0xd4/0xf8)
> [ 0.812194] [<c003099c>] (_idle+0xd4/0xf8) from [<c0030c9c>] (omap_hwmod_idle+0x28/0x3c)
> [ 0.812225] [<c0030c9c>] (omap_hwmod_idle+0x28/0x3c) from [<c0030e6c>] (omap_device_idle+0x3c/0x80)
> [ 0.812225] [<c0030e6c>] (omap_device_idle+0x3c/0x80) from [<c0030ed0>] (_od_runtime_suspend+0x20/0x2c)
> [ 0.812255] [<c0030ed0>] (_od_runtime_suspend+0x20/0x2c) from [<c036e120>] (__rpm_callback+0x2c/0x80)
> [ 0.812286] [<c036e120>] (__rpm_callback+0x2c/0x80) from [<c036e198>] (rpm_callback+0x24/0x78)
> [ 0.812316] [<c036e198>] (rpm_callback+0x24/0x78) from [<c036e5bc>] (rpm_suspend+0xf4/0x5e4)
> [ 0.812347] [<c036e5bc>] (rpm_suspend+0xf4/0x5e4) from [<c036fb78>] (pm_runtime_work+0x80/0xa4)
> [ 0.812377] [<c036fb78>] (pm_runtime_work+0x80/0xa4) from [<c0064058>] (process_one_work+0x204/0x594)
> [ 0.812408] [<c0064058>] (process_one_work+0x204/0x594) from [<c0064530>] (worker_thread+0x148/0x480)
> [ 0.812438] [<c0064530>] (worker_thread+0x148/0x480) from [<c0069c20>] (kthread+0xa0/0xac)
> [ 0.812469] [<c0069c20>] (kthread+0xa0/0xac) from [<c00149c8>] (ret_from_fork+0x14/0x2c)
> [ 0.812499] ---[ end trace 1b75b31a2719ed1e ]---
>
>
> [ 2.595031] ------------[ cut here ]------------
> [ 2.599945] WARNING: CPU: 0 PID: 1 at arch/arm/mach-omap2/omap_hwmod.c:2126 _enable+0x254/0x280()
> [ 2.609313] omap_hwmod: uart4: enabled state can only be entered from initialized, idle, or disabled state
> [ 2.619506] Modules linked in:
> [ 2.622772] CPU: 0 PID: 1 Comm: swapper/0 Tainted: G W 3.12.0-rc2-00020-gdea1778-dirty #791
> [ 2.632537] [<c001cd54>] (unwind_backtrace+0x0/0xf4) from [<c0018e80>] (show_stack+0x14/0x1c)
> [ 2.641540] [<c0018e80>] (show_stack+0x14/0x1c) from [<c0554400>] (dump_stack+0x6c/0x9c)
> [ 2.650115] [<c0554400>] (dump_stack+0x6c/0x9c) from [<c00488a8>] (warn_slowpath_common+0x64/0x84)
> [ 2.659576] [<c00488a8>] (warn_slowpath_common+0x64/0x84) from [<c004895c>] (warn_slowpath_fmt+0x30/0x40)
> [ 2.669708] [<c004895c>] (warn_slowpath_fmt+0x30/0x40) from [<c003085c>] (_enable+0x254/0x280)
> [ 2.678802] [<c003085c>] (_enable+0x254/0x280) from [<c00308b0>] (omap_hwmod_enable+0x28/0x40)
> [ 2.687927] [<c00308b0>] (omap_hwmod_enable+0x28/0x40) from [<c0030f8c>] (omap_device_enable+0x3c/0x80)
> [ 2.697875] [<c0030f8c>] (omap_device_enable+0x3c/0x80) from [<c0030fe0>] (_od_runtime_resume+0x10/0x1c)
> [ 2.707916] [<c0030fe0>] (_od_runtime_resume+0x10/0x1c) from [<c036e120>] (__rpm_callback+0x2c/0x80)
> [ 2.717559] [<c036e120>] (__rpm_callback+0x2c/0x80) from [<c036e198>] (rpm_callback+0x24/0x78)
> [ 2.726684] [<c036e198>] (rpm_callback+0x24/0x78) from [<c036f444>] (rpm_resume+0x3c0/0x60c)
> [ 2.735595] [<c036f444>] (rpm_resume+0x3c0/0x60c) from [<c036f970>] (__pm_runtime_resume+0x4c/0x68)
> [ 2.745178] [<c036f970>] (__pm_runtime_resume+0x4c/0x68) from [<c035ae30>] (serial_omap_probe+0x294/0x4fc)
> [ 2.755401] [<c035ae30>] (serial_omap_probe+0x294/0x4fc) from [<c03659ac>] (platform_drv_probe+0x1c/0x24)
> [ 2.765502] [<c03659ac>] (platform_drv_probe+0x1c/0x24) from [<c03645e4>] (really_probe+0x70/0x200)
> [ 2.775054] [<c03645e4>] (really_probe+0x70/0x200) from [<c03647a8>] (driver_probe_device+0x34/0x50)
> [ 2.784729] [<c03647a8>] (driver_probe_device+0x34/0x50) from [<c0364858>] (__driver_attach+0x94/0x98)
> [ 2.794555] [<c0364858>] (__driver_attach+0x94/0x98) from [<c0362cd4>] (bus_for_each_dev+0x74/0x98)
> [ 2.804138] [<c0362cd4>] (bus_for_each_dev+0x74/0x98) from [<c0363510>] (bus_add_driver+0xe8/0x278)
> [ 2.813690] [<c0363510>] (bus_add_driver+0xe8/0x278) from [<c0364e30>] (driver_register+0x5c/0xf8)
> [ 2.823181] [<c0364e30>] (driver_register+0x5c/0xf8) from [<c07d0028>] (serial_omap_init+0x28/0x44)
> [ 2.832763] [<c07d0028>] (serial_omap_init+0x28/0x44) from [<c00087ac>] (do_one_initcall+0x2c/0x150)
> [ 2.842407] [<c00087ac>] (do_one_initcall+0x2c/0x150) from [<c0797508>] (do_basic_setup+0x94/0xd0)
> [ 2.851898] [<c0797508>] (do_basic_setup+0x94/0xd0) from [<c07975c0>] (kernel_init_freeable+0x7c/0x120)
> [ 2.861846] [<c07975c0>] (kernel_init_freeable+0x7c/0x120) from [<c05526b4>] (kernel_init+0xc/0x164)
> [ 2.871490] [<c05526b4>] (kernel_init+0xc/0x164) from [<c00149c8>] (ret_from_fork+0x14/0x2c)
> [ 2.880432] ---[ end trace 1b75b31a2719ed1f ]---
>
^ permalink raw reply [flat|nested] 136+ messages in thread
* Re: [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
2013-10-07 6:35 ` Tero Kristo
@ 2013-10-07 15:41 ` Tony Lindgren
-1 siblings, 0 replies; 136+ messages in thread
From: Tony Lindgren @ 2013-10-07 15:41 UTC (permalink / raw)
To: Tero Kristo
Cc: linux-omap, paul, nm, rnayak, bcousson, mturquette,
linux-arm-kernel, devicetree
* Tero Kristo <t-kristo@ti.com> [131006 23:43]:
> On 10/07/2013 05:15 AM, Tony Lindgren wrote:
> >* Tero Kristo <t-kristo@ti.com> [131004 08:42]:
> >>Hi,
> >>
> >>Just a gentle reminder, anybody have any comments on this series or
> >>should we start queuing stuff?
> >
> >Well omap4 seems to work for me just fine, and omap3 in legacy
> >mode. But looks like omap3 device tree based booting is breaking
> >after I pulled in your test branch. I get the following on
> >3630 based dm3730.
>
> Uart4 breaks because of the issue with basic DT blobs. You need at
> least this patch:
>
> http://linux-kernel.2935.n7.nabble.com/RFC-PATCH-ARM-OMAP3630-Add-generic-machine-descriptor-td722791.html
>
> ... from Nishanth to get it to work right. Otherwise the clock init
> tries to use omap3430 clock data for omap3630 which leaves uart4
> nodes out.
OK thanks yes that solves it, I was missing the compatible flag
for my not quite ready test boards (3730-evm and zoom3).
I'll apply Nishant's fix with some changes.
Then for this series, once you have the necessary acks, can you
please split into following two separate immutable branches
against v3.12-rc3:
1. clock code changes
2. dts changes
Then those can be pulled in as needed by Benoit, Mike and I.
For the whole series, I think this quite nicely removes some
nasty kernel data dependencies for omaps, so feel free to add:
Acked-by: Tony Lindgren <tony@atomide.com>
Regards,
Tony
^ permalink raw reply [flat|nested] 136+ messages in thread
* [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
@ 2013-10-07 15:41 ` Tony Lindgren
0 siblings, 0 replies; 136+ messages in thread
From: Tony Lindgren @ 2013-10-07 15:41 UTC (permalink / raw)
To: linux-arm-kernel
* Tero Kristo <t-kristo@ti.com> [131006 23:43]:
> On 10/07/2013 05:15 AM, Tony Lindgren wrote:
> >* Tero Kristo <t-kristo@ti.com> [131004 08:42]:
> >>Hi,
> >>
> >>Just a gentle reminder, anybody have any comments on this series or
> >>should we start queuing stuff?
> >
> >Well omap4 seems to work for me just fine, and omap3 in legacy
> >mode. But looks like omap3 device tree based booting is breaking
> >after I pulled in your test branch. I get the following on
> >3630 based dm3730.
>
> Uart4 breaks because of the issue with basic DT blobs. You need at
> least this patch:
>
> http://linux-kernel.2935.n7.nabble.com/RFC-PATCH-ARM-OMAP3630-Add-generic-machine-descriptor-td722791.html
>
> ... from Nishanth to get it to work right. Otherwise the clock init
> tries to use omap3430 clock data for omap3630 which leaves uart4
> nodes out.
OK thanks yes that solves it, I was missing the compatible flag
for my not quite ready test boards (3730-evm and zoom3).
I'll apply Nishant's fix with some changes.
Then for this series, once you have the necessary acks, can you
please split into following two separate immutable branches
against v3.12-rc3:
1. clock code changes
2. dts changes
Then those can be pulled in as needed by Benoit, Mike and I.
For the whole series, I think this quite nicely removes some
nasty kernel data dependencies for omaps, so feel free to add:
Acked-by: Tony Lindgren <tony@atomide.com>
Regards,
Tony
^ permalink raw reply [flat|nested] 136+ messages in thread
* Re: [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
2013-10-07 15:41 ` Tony Lindgren
@ 2013-10-07 16:13 ` Nishanth Menon
-1 siblings, 0 replies; 136+ messages in thread
From: Nishanth Menon @ 2013-10-07 16:13 UTC (permalink / raw)
To: Tony Lindgren, Tero Kristo
Cc: linux-omap, paul, rnayak, bcousson, mturquette, linux-arm-kernel,
devicetree
On 10/07/2013 10:41 AM, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [131006 23:43]:
>> On 10/07/2013 05:15 AM, Tony Lindgren wrote:
>>> * Tero Kristo <t-kristo@ti.com> [131004 08:42]:
>>>> Hi,
>>>>
>>>> Just a gentle reminder, anybody have any comments on this series or
>>>> should we start queuing stuff?
>>>
>>> Well omap4 seems to work for me just fine, and omap3 in legacy
>>> mode. But looks like omap3 device tree based booting is breaking
>>> after I pulled in your test branch. I get the following on
>>> 3630 based dm3730.
>>
>> Uart4 breaks because of the issue with basic DT blobs. You need at
>> least this patch:
>>
>> http://linux-kernel.2935.n7.nabble.com/RFC-PATCH-ARM-OMAP3630-Add-generic-machine-descriptor-td722791.html
>>
>> ... from Nishanth to get it to work right. Otherwise the clock init
>> tries to use omap3430 clock data for omap3630 which leaves uart4
>> nodes out.
>
> OK thanks yes that solves it, I was missing the compatible flag
> for my not quite ready test boards (3730-evm and zoom3).
> I'll apply Nishant's fix with some changes.
>
I will post out an RFC based on Olof's suggestion in a few mins. will
be nice to see any deltas needed.
--
Regards,
Nishanth Menon
^ permalink raw reply [flat|nested] 136+ messages in thread
* [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
@ 2013-10-07 16:13 ` Nishanth Menon
0 siblings, 0 replies; 136+ messages in thread
From: Nishanth Menon @ 2013-10-07 16:13 UTC (permalink / raw)
To: linux-arm-kernel
On 10/07/2013 10:41 AM, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [131006 23:43]:
>> On 10/07/2013 05:15 AM, Tony Lindgren wrote:
>>> * Tero Kristo <t-kristo@ti.com> [131004 08:42]:
>>>> Hi,
>>>>
>>>> Just a gentle reminder, anybody have any comments on this series or
>>>> should we start queuing stuff?
>>>
>>> Well omap4 seems to work for me just fine, and omap3 in legacy
>>> mode. But looks like omap3 device tree based booting is breaking
>>> after I pulled in your test branch. I get the following on
>>> 3630 based dm3730.
>>
>> Uart4 breaks because of the issue with basic DT blobs. You need at
>> least this patch:
>>
>> http://linux-kernel.2935.n7.nabble.com/RFC-PATCH-ARM-OMAP3630-Add-generic-machine-descriptor-td722791.html
>>
>> ... from Nishanth to get it to work right. Otherwise the clock init
>> tries to use omap3430 clock data for omap3630 which leaves uart4
>> nodes out.
>
> OK thanks yes that solves it, I was missing the compatible flag
> for my not quite ready test boards (3730-evm and zoom3).
> I'll apply Nishant's fix with some changes.
>
I will post out an RFC based on Olof's suggestion in a few mins. will
be nice to see any deltas needed.
--
Regards,
Nishanth Menon
^ permalink raw reply [flat|nested] 136+ messages in thread
* Re: [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
2013-10-07 15:41 ` Tony Lindgren
@ 2013-10-07 19:03 ` Tony Lindgren
-1 siblings, 0 replies; 136+ messages in thread
From: Tony Lindgren @ 2013-10-07 19:03 UTC (permalink / raw)
To: Tero Kristo
Cc: linux-omap, paul, nm, rnayak, bcousson, mturquette,
linux-arm-kernel, devicetree
* Tony Lindgren <tony@atomide.com> [131007 08:49]:
> * Tero Kristo <t-kristo@ti.com> [131006 23:43]:
> > On 10/07/2013 05:15 AM, Tony Lindgren wrote:
> > >* Tero Kristo <t-kristo@ti.com> [131004 08:42]:
> > >>Hi,
> > >>
> > >>Just a gentle reminder, anybody have any comments on this series or
> > >>should we start queuing stuff?
> > >
> > >Well omap4 seems to work for me just fine, and omap3 in legacy
> > >mode. But looks like omap3 device tree based booting is breaking
> > >after I pulled in your test branch. I get the following on
> > >3630 based dm3730.
> >
> > Uart4 breaks because of the issue with basic DT blobs. You need at
> > least this patch:
> >
> > http://linux-kernel.2935.n7.nabble.com/RFC-PATCH-ARM-OMAP3630-Add-generic-machine-descriptor-td722791.html
> >
> > ... from Nishanth to get it to work right. Otherwise the clock init
> > tries to use omap3430 clock data for omap3630 which leaves uart4
> > nodes out.
>
> OK thanks yes that solves it, I was missing the compatible flag
> for my not quite ready test boards (3730-evm and zoom3).
> I'll apply Nishant's fix with some changes.
>
> Then for this series, once you have the necessary acks, can you
> please split into following two separate immutable branches
> against v3.12-rc3:
>
> 1. clock code changes
>
> 2. dts changes
>
> Then those can be pulled in as needed by Benoit, Mike and I.
And Paul too natuarlly if these patches conflict with stuff
that's he's merging. And assuming Paul is OK with these patches
in general.
> For the whole series, I think this quite nicely removes some
> nasty kernel data dependencies for omaps, so feel free to add:
>
> Acked-by: Tony Lindgren <tony@atomide.com>
>
> Regards,
>
> Tony
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 136+ messages in thread
* [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
@ 2013-10-07 19:03 ` Tony Lindgren
0 siblings, 0 replies; 136+ messages in thread
From: Tony Lindgren @ 2013-10-07 19:03 UTC (permalink / raw)
To: linux-arm-kernel
* Tony Lindgren <tony@atomide.com> [131007 08:49]:
> * Tero Kristo <t-kristo@ti.com> [131006 23:43]:
> > On 10/07/2013 05:15 AM, Tony Lindgren wrote:
> > >* Tero Kristo <t-kristo@ti.com> [131004 08:42]:
> > >>Hi,
> > >>
> > >>Just a gentle reminder, anybody have any comments on this series or
> > >>should we start queuing stuff?
> > >
> > >Well omap4 seems to work for me just fine, and omap3 in legacy
> > >mode. But looks like omap3 device tree based booting is breaking
> > >after I pulled in your test branch. I get the following on
> > >3630 based dm3730.
> >
> > Uart4 breaks because of the issue with basic DT blobs. You need at
> > least this patch:
> >
> > http://linux-kernel.2935.n7.nabble.com/RFC-PATCH-ARM-OMAP3630-Add-generic-machine-descriptor-td722791.html
> >
> > ... from Nishanth to get it to work right. Otherwise the clock init
> > tries to use omap3430 clock data for omap3630 which leaves uart4
> > nodes out.
>
> OK thanks yes that solves it, I was missing the compatible flag
> for my not quite ready test boards (3730-evm and zoom3).
> I'll apply Nishant's fix with some changes.
>
> Then for this series, once you have the necessary acks, can you
> please split into following two separate immutable branches
> against v3.12-rc3:
>
> 1. clock code changes
>
> 2. dts changes
>
> Then those can be pulled in as needed by Benoit, Mike and I.
And Paul too natuarlly if these patches conflict with stuff
that's he's merging. And assuming Paul is OK with these patches
in general.
> For the whole series, I think this quite nicely removes some
> nasty kernel data dependencies for omaps, so feel free to add:
>
> Acked-by: Tony Lindgren <tony@atomide.com>
>
> Regards,
>
> Tony
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 136+ messages in thread
* Re: [PATCHv7 20/36] CLK: TI: DRA7: Add APLL support
2013-09-25 8:48 ` Tero Kristo
@ 2013-10-08 5:16 ` Mike Turquette
-1 siblings, 0 replies; 136+ messages in thread
From: Mike Turquette @ 2013-10-08 5:16 UTC (permalink / raw)
To: Tero Kristo, linux-omap, paul, tony, nm, rnayak, bcousson
Cc: linux-arm-kernel, devicetree, Keerthy
Quoting Tero Kristo (2013-09-25 01:48:26)
> +
> +static const struct clk_ops apll_ck_ops = {
> + .enable = &dra7_apll_enable,
> + .disable = &dra7_apll_disable,
Looks like .is_enabled is missing?
Also have you thought about using .prepare or .unprepare for these PLLs
which might take some time to lock? The code there doesn't sleep or
schedule, but it does poll for some time while under a spinlock.
Something to think about for a future patch.
Regards,
Mike
^ permalink raw reply [flat|nested] 136+ messages in thread
* [PATCHv7 20/36] CLK: TI: DRA7: Add APLL support
@ 2013-10-08 5:16 ` Mike Turquette
0 siblings, 0 replies; 136+ messages in thread
From: Mike Turquette @ 2013-10-08 5:16 UTC (permalink / raw)
To: linux-arm-kernel
Quoting Tero Kristo (2013-09-25 01:48:26)
> +
> +static const struct clk_ops apll_ck_ops = {
> + .enable = &dra7_apll_enable,
> + .disable = &dra7_apll_disable,
Looks like .is_enabled is missing?
Also have you thought about using .prepare or .unprepare for these PLLs
which might take some time to lock? The code there doesn't sleep or
schedule, but it does poll for some time while under a spinlock.
Something to think about for a future patch.
Regards,
Mike
^ permalink raw reply [flat|nested] 136+ messages in thread
* Re: [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
2013-09-25 8:48 ` Tero Kristo
@ 2013-10-08 5:40 ` Mike Turquette
-1 siblings, 0 replies; 136+ messages in thread
From: Mike Turquette @ 2013-10-08 5:40 UTC (permalink / raw)
To: Tero Kristo, linux-omap, paul, tony, nm, rnayak, bcousson
Cc: linux-arm-kernel, devicetree
Quoting Tero Kristo (2013-09-25 01:48:06)
> Hi all,
>
> Version 7 contains following high level changes:
> - Dropped support for basic bindings from Mike Turquette, instead using
> vendor specific bindings for all clocks
> - Mux clock + divider clock vendor specific bindings get rid of use
> of the bit-masks, instead these are generated runtime based on parent
> clock / divider min/max info, see individual patches for details
> - Added support for dummy_ck nodes, was missing from previous version
> - Fixed support for omap3630
> - Added support for new clock node type: ti,mux-gate-clock (using composite
> clock type)
> - OMAP4 / OMAP5 only build fixes (compiler flag checks added to some files)
> - most of the of_omap_* calls renamed to of_ti_*
> - Rebased on top of v3.12-rc2
Hi Tero,
I had one really minor request for one of the patches, otherwise I'm
pretty happy with this series and I can take in the clock parts for
3.13. A few general comments:
1) I think I mentioned some time back that it would be
wise to put a disclaimer at the top of each DT binding description
stating something to the effect: "Binding status: Unstable - ABI
compatibility may be broken in the future". Are you OK merging these
bindings as-is without that kind of a disclaimer?
2) I hope to see the clockdomain stuff go away in the future. I'm OK to
take it for now to aid in this DT transition but I would like some
commitment that it will not stay in drivers/clk/omap forever. I guess
for clockdomain you'll need to figure out how to handle those in a
generic driver way.
3) Same concern as above but for the DT clkdev alias stuff. I guess
you'll need to make all of the dependent drivers play nice with DT. Do
you plan to remove it within a reasonable timeframe? It would be a nice
reduction in LoC and more importantly it would mean that drivers were
using clkdev in a more-correct fashion.
Regards,
Mike
>
> Some detailed comments about patch level changes (if no mention, no major
> changes):
> - Patch #1:
> * removed use of reg-names property, instead registers mapped using
> compatible string
> * removed ti,modes property, instead uses DPLL mode flags now
> * separated AM33XX DPLLs under their own compatible strings
> - Patch #4 & #5: new patches
> - Patch #6: merged basic gate support from Mike to this patch as vendor
> specific gate clock support
> - Patch #9 & #10: new patches
> - Patch #11: dummy clocks added, USB / ABE DPLL setup ordering changed
> - Patch #14: dummy clocks added
> - Patch #20: dropped usage of reg-names property
> - Patch #21: dummy clocks added
> - Patch #22 & #23: new patches
> - Patch #30: AM35XX clock data added to this patch
> - Patch #31:
> * dummy clocks added
> * added missing 3630 clocks
>
> Test branch available here:
> https://github.com/t-kristo/linux-pm.git
> branch: mainline-3.12-rc2-ti-dt-clks-v7
>
> Testing done:
> - am335x-bone : boot only
> - omap5-sevm : boot only
> - dra7-evm : boot only
> - omap3-beagle : boot + suspend/resume (ret + off)
> - omap4-panda-es : boot + suspend/resume
>
> Nishanth has also been doing some tests with omap3-beagle-xm with some WIP
> versions of this branch, but not with this latest one. Nishanth, maybe you
> can provide test results to this one also?
>
> -Tero
^ permalink raw reply [flat|nested] 136+ messages in thread
* [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
@ 2013-10-08 5:40 ` Mike Turquette
0 siblings, 0 replies; 136+ messages in thread
From: Mike Turquette @ 2013-10-08 5:40 UTC (permalink / raw)
To: linux-arm-kernel
Quoting Tero Kristo (2013-09-25 01:48:06)
> Hi all,
>
> Version 7 contains following high level changes:
> - Dropped support for basic bindings from Mike Turquette, instead using
> vendor specific bindings for all clocks
> - Mux clock + divider clock vendor specific bindings get rid of use
> of the bit-masks, instead these are generated runtime based on parent
> clock / divider min/max info, see individual patches for details
> - Added support for dummy_ck nodes, was missing from previous version
> - Fixed support for omap3630
> - Added support for new clock node type: ti,mux-gate-clock (using composite
> clock type)
> - OMAP4 / OMAP5 only build fixes (compiler flag checks added to some files)
> - most of the of_omap_* calls renamed to of_ti_*
> - Rebased on top of v3.12-rc2
Hi Tero,
I had one really minor request for one of the patches, otherwise I'm
pretty happy with this series and I can take in the clock parts for
3.13. A few general comments:
1) I think I mentioned some time back that it would be
wise to put a disclaimer at the top of each DT binding description
stating something to the effect: "Binding status: Unstable - ABI
compatibility may be broken in the future". Are you OK merging these
bindings as-is without that kind of a disclaimer?
2) I hope to see the clockdomain stuff go away in the future. I'm OK to
take it for now to aid in this DT transition but I would like some
commitment that it will not stay in drivers/clk/omap forever. I guess
for clockdomain you'll need to figure out how to handle those in a
generic driver way.
3) Same concern as above but for the DT clkdev alias stuff. I guess
you'll need to make all of the dependent drivers play nice with DT. Do
you plan to remove it within a reasonable timeframe? It would be a nice
reduction in LoC and more importantly it would mean that drivers were
using clkdev in a more-correct fashion.
Regards,
Mike
>
> Some detailed comments about patch level changes (if no mention, no major
> changes):
> - Patch #1:
> * removed use of reg-names property, instead registers mapped using
> compatible string
> * removed ti,modes property, instead uses DPLL mode flags now
> * separated AM33XX DPLLs under their own compatible strings
> - Patch #4 & #5: new patches
> - Patch #6: merged basic gate support from Mike to this patch as vendor
> specific gate clock support
> - Patch #9 & #10: new patches
> - Patch #11: dummy clocks added, USB / ABE DPLL setup ordering changed
> - Patch #14: dummy clocks added
> - Patch #20: dropped usage of reg-names property
> - Patch #21: dummy clocks added
> - Patch #22 & #23: new patches
> - Patch #30: AM35XX clock data added to this patch
> - Patch #31:
> * dummy clocks added
> * added missing 3630 clocks
>
> Test branch available here:
> https://github.com/t-kristo/linux-pm.git
> branch: mainline-3.12-rc2-ti-dt-clks-v7
>
> Testing done:
> - am335x-bone : boot only
> - omap5-sevm : boot only
> - dra7-evm : boot only
> - omap3-beagle : boot + suspend/resume (ret + off)
> - omap4-panda-es : boot + suspend/resume
>
> Nishanth has also been doing some tests with omap3-beagle-xm with some WIP
> versions of this branch, but not with this latest one. Nishanth, maybe you
> can provide test results to this one also?
>
> -Tero
^ permalink raw reply [flat|nested] 136+ messages in thread
* Re: [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
2013-10-08 5:40 ` Mike Turquette
@ 2013-10-08 8:17 ` Tero Kristo
-1 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-10-08 8:17 UTC (permalink / raw)
To: Mike Turquette, linux-omap, paul, tony, nm, rnayak, bcousson
Cc: devicetree, linux-arm-kernel
On 10/08/2013 08:40 AM, Mike Turquette wrote:
> Quoting Tero Kristo (2013-09-25 01:48:06)
>> Hi all,
>>
>> Version 7 contains following high level changes:
>> - Dropped support for basic bindings from Mike Turquette, instead using
>> vendor specific bindings for all clocks
>> - Mux clock + divider clock vendor specific bindings get rid of use
>> of the bit-masks, instead these are generated runtime based on parent
>> clock / divider min/max info, see individual patches for details
>> - Added support for dummy_ck nodes, was missing from previous version
>> - Fixed support for omap3630
>> - Added support for new clock node type: ti,mux-gate-clock (using composite
>> clock type)
>> - OMAP4 / OMAP5 only build fixes (compiler flag checks added to some files)
>> - most of the of_omap_* calls renamed to of_ti_*
>> - Rebased on top of v3.12-rc2
>
> Hi Tero,
>
> I had one really minor request for one of the patches, otherwise I'm
> pretty happy with this series and I can take in the clock parts for
> 3.13. A few general comments:
Yea, I'll add the is_enabled check to the APLL and repost.
>
> 1) I think I mentioned some time back that it would be
> wise to put a disclaimer at the top of each DT binding description
> stating something to the effect: "Binding status: Unstable - ABI
> compatibility may be broken in the future". Are you OK merging these
> bindings as-is without that kind of a disclaimer?
Well, personally I don't mind, but if you think this would be good, I'll
add this to next rev.
> 2) I hope to see the clockdomain stuff go away in the future. I'm OK to
> take it for now to aid in this DT transition but I would like some
> commitment that it will not stay in drivers/clk/omap forever. I guess
> for clockdomain you'll need to figure out how to handle those in a
> generic driver way.
I think the clockdomain stuff should be possible to move to wherever CM
driver is going to move. drivers/power/omap/... or something maybe. I
have been starting some initial work on the CM driver cleanup for this
purpose.
> 3) Same concern as above but for the DT clkdev alias stuff. I guess
> you'll need to make all of the dependent drivers play nice with DT. Do
> you plan to remove it within a reasonable timeframe? It would be a nice
> reduction in LoC and more importantly it would mean that drivers were
> using clkdev in a more-correct fashion.
This is probably harder, I think Tony is better to comment here, but my
idea is that in the worst case we can just break non-conforming drivers
by dropping the clkdev tables if nothing else helps. :) Most of the
tables are currently needed by hwmod, and there are already patches
around for adding DT clock support for hwmods, so once these go in, we
can at least reduce the table sizes considerably already.
-Tero
>
> Regards,
> Mike
>
>>
>> Some detailed comments about patch level changes (if no mention, no major
>> changes):
>> - Patch #1:
>> * removed use of reg-names property, instead registers mapped using
>> compatible string
>> * removed ti,modes property, instead uses DPLL mode flags now
>> * separated AM33XX DPLLs under their own compatible strings
>> - Patch #4 & #5: new patches
>> - Patch #6: merged basic gate support from Mike to this patch as vendor
>> specific gate clock support
>> - Patch #9 & #10: new patches
>> - Patch #11: dummy clocks added, USB / ABE DPLL setup ordering changed
>> - Patch #14: dummy clocks added
>> - Patch #20: dropped usage of reg-names property
>> - Patch #21: dummy clocks added
>> - Patch #22 & #23: new patches
>> - Patch #30: AM35XX clock data added to this patch
>> - Patch #31:
>> * dummy clocks added
>> * added missing 3630 clocks
>>
>> Test branch available here:
>> https://github.com/t-kristo/linux-pm.git
>> branch: mainline-3.12-rc2-ti-dt-clks-v7
>>
>> Testing done:
>> - am335x-bone : boot only
>> - omap5-sevm : boot only
>> - dra7-evm : boot only
>> - omap3-beagle : boot + suspend/resume (ret + off)
>> - omap4-panda-es : boot + suspend/resume
>>
>> Nishanth has also been doing some tests with omap3-beagle-xm with some WIP
>> versions of this branch, but not with this latest one. Nishanth, maybe you
>> can provide test results to this one also?
>>
>> -Tero
^ permalink raw reply [flat|nested] 136+ messages in thread
* [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
@ 2013-10-08 8:17 ` Tero Kristo
0 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-10-08 8:17 UTC (permalink / raw)
To: linux-arm-kernel
On 10/08/2013 08:40 AM, Mike Turquette wrote:
> Quoting Tero Kristo (2013-09-25 01:48:06)
>> Hi all,
>>
>> Version 7 contains following high level changes:
>> - Dropped support for basic bindings from Mike Turquette, instead using
>> vendor specific bindings for all clocks
>> - Mux clock + divider clock vendor specific bindings get rid of use
>> of the bit-masks, instead these are generated runtime based on parent
>> clock / divider min/max info, see individual patches for details
>> - Added support for dummy_ck nodes, was missing from previous version
>> - Fixed support for omap3630
>> - Added support for new clock node type: ti,mux-gate-clock (using composite
>> clock type)
>> - OMAP4 / OMAP5 only build fixes (compiler flag checks added to some files)
>> - most of the of_omap_* calls renamed to of_ti_*
>> - Rebased on top of v3.12-rc2
>
> Hi Tero,
>
> I had one really minor request for one of the patches, otherwise I'm
> pretty happy with this series and I can take in the clock parts for
> 3.13. A few general comments:
Yea, I'll add the is_enabled check to the APLL and repost.
>
> 1) I think I mentioned some time back that it would be
> wise to put a disclaimer at the top of each DT binding description
> stating something to the effect: "Binding status: Unstable - ABI
> compatibility may be broken in the future". Are you OK merging these
> bindings as-is without that kind of a disclaimer?
Well, personally I don't mind, but if you think this would be good, I'll
add this to next rev.
> 2) I hope to see the clockdomain stuff go away in the future. I'm OK to
> take it for now to aid in this DT transition but I would like some
> commitment that it will not stay in drivers/clk/omap forever. I guess
> for clockdomain you'll need to figure out how to handle those in a
> generic driver way.
I think the clockdomain stuff should be possible to move to wherever CM
driver is going to move. drivers/power/omap/... or something maybe. I
have been starting some initial work on the CM driver cleanup for this
purpose.
> 3) Same concern as above but for the DT clkdev alias stuff. I guess
> you'll need to make all of the dependent drivers play nice with DT. Do
> you plan to remove it within a reasonable timeframe? It would be a nice
> reduction in LoC and more importantly it would mean that drivers were
> using clkdev in a more-correct fashion.
This is probably harder, I think Tony is better to comment here, but my
idea is that in the worst case we can just break non-conforming drivers
by dropping the clkdev tables if nothing else helps. :) Most of the
tables are currently needed by hwmod, and there are already patches
around for adding DT clock support for hwmods, so once these go in, we
can at least reduce the table sizes considerably already.
-Tero
>
> Regards,
> Mike
>
>>
>> Some detailed comments about patch level changes (if no mention, no major
>> changes):
>> - Patch #1:
>> * removed use of reg-names property, instead registers mapped using
>> compatible string
>> * removed ti,modes property, instead uses DPLL mode flags now
>> * separated AM33XX DPLLs under their own compatible strings
>> - Patch #4 & #5: new patches
>> - Patch #6: merged basic gate support from Mike to this patch as vendor
>> specific gate clock support
>> - Patch #9 & #10: new patches
>> - Patch #11: dummy clocks added, USB / ABE DPLL setup ordering changed
>> - Patch #14: dummy clocks added
>> - Patch #20: dropped usage of reg-names property
>> - Patch #21: dummy clocks added
>> - Patch #22 & #23: new patches
>> - Patch #30: AM35XX clock data added to this patch
>> - Patch #31:
>> * dummy clocks added
>> * added missing 3630 clocks
>>
>> Test branch available here:
>> https://github.com/t-kristo/linux-pm.git
>> branch: mainline-3.12-rc2-ti-dt-clks-v7
>>
>> Testing done:
>> - am335x-bone : boot only
>> - omap5-sevm : boot only
>> - dra7-evm : boot only
>> - omap3-beagle : boot + suspend/resume (ret + off)
>> - omap4-panda-es : boot + suspend/resume
>>
>> Nishanth has also been doing some tests with omap3-beagle-xm with some WIP
>> versions of this branch, but not with this latest one. Nishanth, maybe you
>> can provide test results to this one also?
>>
>> -Tero
^ permalink raw reply [flat|nested] 136+ messages in thread
* Re: [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
2013-10-08 8:17 ` Tero Kristo
@ 2013-10-08 16:47 ` Tony Lindgren
-1 siblings, 0 replies; 136+ messages in thread
From: Tony Lindgren @ 2013-10-08 16:47 UTC (permalink / raw)
To: Tero Kristo
Cc: Mike Turquette, linux-omap, paul, nm, rnayak, bcousson,
linux-arm-kernel, devicetree
* Tero Kristo <t-kristo@ti.com> [131008 01:26]:
> On 10/08/2013 08:40 AM, Mike Turquette wrote:
>
> >3) Same concern as above but for the DT clkdev alias stuff. I guess
> >you'll need to make all of the dependent drivers play nice with DT. Do
> >you plan to remove it within a reasonable timeframe? It would be a nice
> >reduction in LoC and more importantly it would mean that drivers were
> >using clkdev in a more-correct fashion.
>
> This is probably harder, I think Tony is better to comment here, but
> my idea is that in the worst case we can just break non-conforming
> drivers by dropping the clkdev tables if nothing else helps. :) Most
> of the tables are currently needed by hwmod, and there are already
> patches around for adding DT clock support for hwmods, so once these
> go in, we can at least reduce the table sizes considerably already.
It should be possible to remove these as we go as things become DT only.
Probably the biggest blocker right now is making omap3 DT only.
But let's not start breaking things intentionally!
Tony
^ permalink raw reply [flat|nested] 136+ messages in thread
* [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
@ 2013-10-08 16:47 ` Tony Lindgren
0 siblings, 0 replies; 136+ messages in thread
From: Tony Lindgren @ 2013-10-08 16:47 UTC (permalink / raw)
To: linux-arm-kernel
* Tero Kristo <t-kristo@ti.com> [131008 01:26]:
> On 10/08/2013 08:40 AM, Mike Turquette wrote:
>
> >3) Same concern as above but for the DT clkdev alias stuff. I guess
> >you'll need to make all of the dependent drivers play nice with DT. Do
> >you plan to remove it within a reasonable timeframe? It would be a nice
> >reduction in LoC and more importantly it would mean that drivers were
> >using clkdev in a more-correct fashion.
>
> This is probably harder, I think Tony is better to comment here, but
> my idea is that in the worst case we can just break non-conforming
> drivers by dropping the clkdev tables if nothing else helps. :) Most
> of the tables are currently needed by hwmod, and there are already
> patches around for adding DT clock support for hwmods, so once these
> go in, we can at least reduce the table sizes considerably already.
It should be possible to remove these as we go as things become DT only.
Probably the biggest blocker right now is making omap3 DT only.
But let's not start breaking things intentionally!
Tony
^ permalink raw reply [flat|nested] 136+ messages in thread
* Re: [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
2013-10-07 19:03 ` Tony Lindgren
@ 2013-10-09 18:55 ` Paul Walmsley
-1 siblings, 0 replies; 136+ messages in thread
From: Paul Walmsley @ 2013-10-09 18:55 UTC (permalink / raw)
To: Tony Lindgren, Tero Kristo, mturquette-QSEj5FYQhm4dnm+yROfE0A
Cc: linux-omap-u79uwXL29TY76Z2rM5mHXA, nm-l0cyMroinI0,
khilman-QSEj5FYQhm4dnm+yROfE0A,
pdeschrijver-DDmLM1+adcrQT0dZR+AlfA, rnayak-l0cyMroinI0,
bcousson-rdvid1DuHRBWk0Htik3J/w,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
swarren-DDmLM1+adcrQT0dZR+AlfA, mark.rutland-5wv7dgnIgG8
On Mon, 7 Oct 2013, Tony Lindgren wrote:
> And assuming Paul is OK with these patches in general.
Actually, I have several concerns with this series, as you and I
discussed. Some of us have been talking them over with other folks for
the past few months to try to figure out what to do. Most of the concerns
have fairly easy technical solutions, but we shouldn't merge these patches
until they're resolved.
The issues are:
1. whether the clock data should go into DT
2. what the right place for DT clock data is in the DT
3. whether it makes sense to merge "experimental" DT bindings in this case
4. where clockdomain data belongs
The first issue - and the one I'm least concerned about - is that, in my
view, it still does not make technical sense to move this data into DT.
This is chip-level hardware data that never needs to be changed by board
designers or end users. Adding it to DT is going to result in a boot-time
cost (due to DT parse overhead) and additional memory consumption for very
little benefit, compared to an implementation that places this data into a
dynamically loadable module. For some users, the boot-time bloat is a big
deal: the example that's been mentioned to me recently is an automotive
back-up camera that needs to cold-boot to complete functionality in a few
hundred microseconds.
However, according to some other upstream maintainers, Linus's goal is to
move most of the device-specific static data out of the kernel tree, into
DT files (in the ARM case). If that non-technical constraint is indeed
the dominant consideration, then I agree that moving this data to DT is
the only viable course of action.
...
The second issue concerns where the SoC clock nodes should go in the DT.
In these patches, the clock data has been encoded in a large "clocks" node
off the top level. This is almost certainly not the right thing to do
from a device hardware point of view. These clocks don't exist as
standalone devices with their own address spaces decoded on the
interconnect. In all of the SoC cases that I'm aware of, clock control
registers are part of larger IP blocks.
For example, in the OMAP case, most of the system integration clock
control registers are part of the OMAP-specific PRCM block, PRM block, or
CM block. Then there are other device-specific clocks, like DSS PLLs or
UART dividers. The control registers for these are generally located in
the subsystem or device IP block itself, and are inaccessible when the
subsystem or IP block is disabled. These device-specific clocks belong to
the IP block, not the SoC integration. So, for example, if two SoCs use
the same IP block, then the clock registers, and their offsets from the IP
block address space base, are likely to be identical.
So in my view, the right things to do here are to:
1. associate SoC DT clock data with the device node that contains the
clock control registers
2. specify relative offsets for clock registers from the start of
the IP block address range, rather than absolute addresses for clock
registers
3. place the responsibility for registering clocks into the IP block
drivers themselves
This naturally separates clocks into per-IP block DT files. It also
provides the CCF with an easy way to ensure that the device that
encloses the clock is enabled and accessible by the CPU core, before
trying to access registers inside.
Similarly, non-SoC off-chip clock data (such as for dedicated I2C PLLs)
should also be associated with their I2C device node.
Making these changes to Tero's existing patches should be relatively
straightforward, based on what I've seen.
...
Regarding the third issue: let's postulate for the moment that the clock
binding issues that I mention in #2 above are ignored (ha!), and that the
existing DT clock data is merged. These bindings are currently marked as
"Unstable - ABI compatibility may be broken in the future". What happens
if, when we meet to discuss clock bindings at the kernel summit, we decide
that significant changes are needed? We could easily wind up with kernels
that won't boot at all when used with newer DT data.
Not to mention, merging such a large amount of code and data before the
bindings are stable will increase the risk of massive churn as the
bindings evolve towards stability.
So IMHO, the way to fix this is to consider the clock data to be IP-block
specific, as mentioned in #2. Then there's no need for global clock
bindings for the SoC clock cases.
Otherwise, it seems prudent to at least wait until the global clock
bindings are no longer marked as unstable. The whole DT migration was
predicated on the ideas of reducing churn in the Linux codebase, and
preserving forward compatibility for DT data. We shouldn't discard these
goals just to merge something a little sooner.
...
The fourth issue is where the clockdomain data should go. The basic issue
here is that the notion of "clockdomains" here is completely
OMAP-specific. OMAP clockdomains demarcate a group of clocks or IP blocks
that share the same automatic idle behavior, controlled by their enclosing
IP block (e.g., PRCM, PRM, CM, etc.). Clockdomains are also used in the
OMAP kernel code to link the clocks to their enclosing power domains,
voltage rail control, etc.
So since these are OMAP PRCM/CM/PRM-specific constructs, the right place
for OMAP clockdomain data is underneath the OMAP-specific CM/PRCM DT
nodes. Again this should be an easy change to Tero's existing patches.
...
So hey, if you've made it this far, thanks for reading. My sense is that
implementing #2 and #4 are relatively straightforward.
Also, since this seems to have been a problem for some folks in the past,
I want to make clear that I think both Mike and Tero have been doing good
jobs on the CCF and OMAP clock patches so far.
regards
- Paul
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^ permalink raw reply [flat|nested] 136+ messages in thread
* [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
@ 2013-10-09 18:55 ` Paul Walmsley
0 siblings, 0 replies; 136+ messages in thread
From: Paul Walmsley @ 2013-10-09 18:55 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, 7 Oct 2013, Tony Lindgren wrote:
> And assuming Paul is OK with these patches in general.
Actually, I have several concerns with this series, as you and I
discussed. Some of us have been talking them over with other folks for
the past few months to try to figure out what to do. Most of the concerns
have fairly easy technical solutions, but we shouldn't merge these patches
until they're resolved.
The issues are:
1. whether the clock data should go into DT
2. what the right place for DT clock data is in the DT
3. whether it makes sense to merge "experimental" DT bindings in this case
4. where clockdomain data belongs
The first issue - and the one I'm least concerned about - is that, in my
view, it still does not make technical sense to move this data into DT.
This is chip-level hardware data that never needs to be changed by board
designers or end users. Adding it to DT is going to result in a boot-time
cost (due to DT parse overhead) and additional memory consumption for very
little benefit, compared to an implementation that places this data into a
dynamically loadable module. For some users, the boot-time bloat is a big
deal: the example that's been mentioned to me recently is an automotive
back-up camera that needs to cold-boot to complete functionality in a few
hundred microseconds.
However, according to some other upstream maintainers, Linus's goal is to
move most of the device-specific static data out of the kernel tree, into
DT files (in the ARM case). If that non-technical constraint is indeed
the dominant consideration, then I agree that moving this data to DT is
the only viable course of action.
...
The second issue concerns where the SoC clock nodes should go in the DT.
In these patches, the clock data has been encoded in a large "clocks" node
off the top level. This is almost certainly not the right thing to do
from a device hardware point of view. These clocks don't exist as
standalone devices with their own address spaces decoded on the
interconnect. In all of the SoC cases that I'm aware of, clock control
registers are part of larger IP blocks.
For example, in the OMAP case, most of the system integration clock
control registers are part of the OMAP-specific PRCM block, PRM block, or
CM block. Then there are other device-specific clocks, like DSS PLLs or
UART dividers. The control registers for these are generally located in
the subsystem or device IP block itself, and are inaccessible when the
subsystem or IP block is disabled. These device-specific clocks belong to
the IP block, not the SoC integration. So, for example, if two SoCs use
the same IP block, then the clock registers, and their offsets from the IP
block address space base, are likely to be identical.
So in my view, the right things to do here are to:
1. associate SoC DT clock data with the device node that contains the
clock control registers
2. specify relative offsets for clock registers from the start of
the IP block address range, rather than absolute addresses for clock
registers
3. place the responsibility for registering clocks into the IP block
drivers themselves
This naturally separates clocks into per-IP block DT files. It also
provides the CCF with an easy way to ensure that the device that
encloses the clock is enabled and accessible by the CPU core, before
trying to access registers inside.
Similarly, non-SoC off-chip clock data (such as for dedicated I2C PLLs)
should also be associated with their I2C device node.
Making these changes to Tero's existing patches should be relatively
straightforward, based on what I've seen.
...
Regarding the third issue: let's postulate for the moment that the clock
binding issues that I mention in #2 above are ignored (ha!), and that the
existing DT clock data is merged. These bindings are currently marked as
"Unstable - ABI compatibility may be broken in the future". What happens
if, when we meet to discuss clock bindings at the kernel summit, we decide
that significant changes are needed? We could easily wind up with kernels
that won't boot at all when used with newer DT data.
Not to mention, merging such a large amount of code and data before the
bindings are stable will increase the risk of massive churn as the
bindings evolve towards stability.
So IMHO, the way to fix this is to consider the clock data to be IP-block
specific, as mentioned in #2. Then there's no need for global clock
bindings for the SoC clock cases.
Otherwise, it seems prudent to at least wait until the global clock
bindings are no longer marked as unstable. The whole DT migration was
predicated on the ideas of reducing churn in the Linux codebase, and
preserving forward compatibility for DT data. We shouldn't discard these
goals just to merge something a little sooner.
...
The fourth issue is where the clockdomain data should go. The basic issue
here is that the notion of "clockdomains" here is completely
OMAP-specific. OMAP clockdomains demarcate a group of clocks or IP blocks
that share the same automatic idle behavior, controlled by their enclosing
IP block (e.g., PRCM, PRM, CM, etc.). Clockdomains are also used in the
OMAP kernel code to link the clocks to their enclosing power domains,
voltage rail control, etc.
So since these are OMAP PRCM/CM/PRM-specific constructs, the right place
for OMAP clockdomain data is underneath the OMAP-specific CM/PRCM DT
nodes. Again this should be an easy change to Tero's existing patches.
...
So hey, if you've made it this far, thanks for reading. My sense is that
implementing #2 and #4 are relatively straightforward.
Also, since this seems to have been a problem for some folks in the past,
I want to make clear that I think both Mike and Tero have been doing good
jobs on the CCF and OMAP clock patches so far.
regards
- Paul
^ permalink raw reply [flat|nested] 136+ messages in thread
* Re: [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
2013-10-09 18:55 ` Paul Walmsley
@ 2013-10-09 18:59 ` Paul Walmsley
-1 siblings, 0 replies; 136+ messages in thread
From: Paul Walmsley @ 2013-10-09 18:59 UTC (permalink / raw)
To: Tony Lindgren, Tero Kristo, mturquette
Cc: linux-omap, nm, khilman, pdeschrijver, rnayak, bcousson,
linux-arm-kernel, devicetree, swarren, mark.rutland
Eh, one correction:
On Wed, 9 Oct 2013, Paul Walmsley wrote:
> We could easily wind up with kernels that won't boot at all when used
> with newer DT data.
This is a misstatement of the issue: the concern here is that newer
kernels may not boot at all with older DT data - which could easily be in
locked areas of the flash or firmware.
- Paul
^ permalink raw reply [flat|nested] 136+ messages in thread
* [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
@ 2013-10-09 18:59 ` Paul Walmsley
0 siblings, 0 replies; 136+ messages in thread
From: Paul Walmsley @ 2013-10-09 18:59 UTC (permalink / raw)
To: linux-arm-kernel
Eh, one correction:
On Wed, 9 Oct 2013, Paul Walmsley wrote:
> We could easily wind up with kernels that won't boot at all when used
> with newer DT data.
This is a misstatement of the issue: the concern here is that newer
kernels may not boot at all with older DT data - which could easily be in
locked areas of the flash or firmware.
- Paul
^ permalink raw reply [flat|nested] 136+ messages in thread
* Re: [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
2013-10-09 18:55 ` Paul Walmsley
@ 2013-10-09 19:22 ` Tony Lindgren
-1 siblings, 0 replies; 136+ messages in thread
From: Tony Lindgren @ 2013-10-09 19:22 UTC (permalink / raw)
To: Paul Walmsley
Cc: Tero Kristo, mturquette, linux-omap, nm, khilman, pdeschrijver,
rnayak, bcousson, linux-arm-kernel, devicetree, swarren,
mark.rutland
* Paul Walmsley <paul@pwsan.com> [131009 12:04]:
> On Mon, 7 Oct 2013, Tony Lindgren wrote:
>
> > And assuming Paul is OK with these patches in general.
>
> Actually, I have several concerns with this series, as you and I
> discussed. Some of us have been talking them over with other folks for
> the past few months to try to figure out what to do. Most of the concerns
> have fairly easy technical solutions, but we shouldn't merge these patches
> until they're resolved.
>
> The issues are:
>
> 1. whether the clock data should go into DT
> 2. what the right place for DT clock data is in the DT
> 3. whether it makes sense to merge "experimental" DT bindings in this case
> 4. where clockdomain data belongs
>
> The first issue - and the one I'm least concerned about - is that, in my
> view, it still does not make technical sense to move this data into DT.
> This is chip-level hardware data that never needs to be changed by board
> designers or end users. Adding it to DT is going to result in a boot-time
> cost (due to DT parse overhead) and additional memory consumption for very
> little benefit, compared to an implementation that places this data into a
> dynamically loadable module. For some users, the boot-time bloat is a big
> deal: the example that's been mentioned to me recently is an automotive
> back-up camera that needs to cold-boot to complete functionality in a few
> hundred microseconds.
>
> However, according to some other upstream maintainers, Linus's goal is to
> move most of the device-specific static data out of the kernel tree, into
> DT files (in the ARM case). If that non-technical constraint is indeed
> the dominant consideration, then I agree that moving this data to DT is
> the only viable course of action.
I've been advocating that any combination of dt defined clocks, loadable
module clocks and clocks loaded via /lib/firmware should be allowed.
That allows mapping just the bootime clocks in DT, or all the clocks
in DT depending what suits the use case.
And yes, based on the flames I've received over the years, Linus clearly
wants the SoC specific data out of the kernel. And there's already a lot
of the SoC specific data that's now building up in various linux generic
frameworks..
> The second issue concerns where the SoC clock nodes should go in the DT.
> In these patches, the clock data has been encoded in a large "clocks" node
> off the top level. This is almost certainly not the right thing to do
> from a device hardware point of view. These clocks don't exist as
> standalone devices with their own address spaces decoded on the
> interconnect. In all of the SoC cases that I'm aware of, clock control
> registers are part of larger IP blocks.
>
> For example, in the OMAP case, most of the system integration clock
> control registers are part of the OMAP-specific PRCM block, PRM block, or
> CM block. Then there are other device-specific clocks, like DSS PLLs or
> UART dividers. The control registers for these are generally located in
> the subsystem or device IP block itself, and are inaccessible when the
> subsystem or IP block is disabled. These device-specific clocks belong to
> the IP block, not the SoC integration. So, for example, if two SoCs use
> the same IP block, then the clock registers, and their offsets from the IP
> block address space base, are likely to be identical.
>
> So in my view, the right things to do here are to:
>
> 1. associate SoC DT clock data with the device node that contains the
> clock control registers
>
> 2. specify relative offsets for clock registers from the start of
> the IP block address range, rather than absolute addresses for clock
> registers
>
> 3. place the responsibility for registering clocks into the IP block
> drivers themselves
>
> This naturally separates clocks into per-IP block DT files. It also
> provides the CCF with an easy way to ensure that the device that
> encloses the clock is enabled and accessible by the CPU core, before
> trying to access registers inside.
>
> Similarly, non-SoC off-chip clock data (such as for dedicated I2C PLLs)
> should also be associated with their I2C device node.
>
> Making these changes to Tero's existing patches should be relatively
> straightforward, based on what I've seen.
Yes that's a valid concern and makes sense to me. It also it seems that
moving clocks around with this approach does not break the binding ABI.
> Regarding the third issue: let's postulate for the moment that the clock
> binding issues that I mention in #2 above are ignored (ha!), and that the
> existing DT clock data is merged. These bindings are currently marked as
> "Unstable - ABI compatibility may be broken in the future". What happens
> if, when we meet to discuss clock bindings at the kernel summit, we decide
> that significant changes are needed? We could easily wind up with kernels
> that won't boot at all when used with newer DT data.
>
> Not to mention, merging such a large amount of code and data before the
> bindings are stable will increase the risk of massive churn as the
> bindings evolve towards stability.
>
> So IMHO, the way to fix this is to consider the clock data to be IP-block
> specific, as mentioned in #2. Then there's no need for global clock
> bindings for the SoC clock cases.
>
> Otherwise, it seems prudent to at least wait until the global clock
> bindings are no longer marked as unstable. The whole DT migration was
> predicated on the ideas of reducing churn in the Linux codebase, and
> preserving forward compatibility for DT data. We shouldn't discard these
> goals just to merge something a little sooner.
Mike suggested using ti specific bindings as the generic bindings may not
be ready for quite some time. In any case, these bindings seem like they
can be easily supported in the long run no matter what happens with the
Linux generic clock bindings.
> The fourth issue is where the clockdomain data should go. The basic issue
> here is that the notion of "clockdomains" here is completely
> OMAP-specific. OMAP clockdomains demarcate a group of clocks or IP blocks
> that share the same automatic idle behavior, controlled by their enclosing
> IP block (e.g., PRCM, PRM, CM, etc.). Clockdomains are also used in the
> OMAP kernel code to link the clocks to their enclosing power domains,
> voltage rail control, etc.
>
> So since these are OMAP PRCM/CM/PRM-specific constructs, the right place
> for OMAP clockdomain data is underneath the OMAP-specific CM/PRCM DT
> nodes. Again this should be an easy change to Tero's existing patches.
I believe Mike has made it a requirement that the clockdomains will be
moved out of the clock code in follow up patches.
> So hey, if you've made it this far, thanks for reading. My sense is that
> implementing #2 and #4 are relatively straightforward.
>
> Also, since this seems to have been a problem for some folks in the past,
> I want to make clear that I think both Mike and Tero have been doing good
> jobs on the CCF and OMAP clock patches so far.
Yes I agree.
Tony
^ permalink raw reply [flat|nested] 136+ messages in thread
* [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
@ 2013-10-09 19:22 ` Tony Lindgren
0 siblings, 0 replies; 136+ messages in thread
From: Tony Lindgren @ 2013-10-09 19:22 UTC (permalink / raw)
To: linux-arm-kernel
* Paul Walmsley <paul@pwsan.com> [131009 12:04]:
> On Mon, 7 Oct 2013, Tony Lindgren wrote:
>
> > And assuming Paul is OK with these patches in general.
>
> Actually, I have several concerns with this series, as you and I
> discussed. Some of us have been talking them over with other folks for
> the past few months to try to figure out what to do. Most of the concerns
> have fairly easy technical solutions, but we shouldn't merge these patches
> until they're resolved.
>
> The issues are:
>
> 1. whether the clock data should go into DT
> 2. what the right place for DT clock data is in the DT
> 3. whether it makes sense to merge "experimental" DT bindings in this case
> 4. where clockdomain data belongs
>
> The first issue - and the one I'm least concerned about - is that, in my
> view, it still does not make technical sense to move this data into DT.
> This is chip-level hardware data that never needs to be changed by board
> designers or end users. Adding it to DT is going to result in a boot-time
> cost (due to DT parse overhead) and additional memory consumption for very
> little benefit, compared to an implementation that places this data into a
> dynamically loadable module. For some users, the boot-time bloat is a big
> deal: the example that's been mentioned to me recently is an automotive
> back-up camera that needs to cold-boot to complete functionality in a few
> hundred microseconds.
>
> However, according to some other upstream maintainers, Linus's goal is to
> move most of the device-specific static data out of the kernel tree, into
> DT files (in the ARM case). If that non-technical constraint is indeed
> the dominant consideration, then I agree that moving this data to DT is
> the only viable course of action.
I've been advocating that any combination of dt defined clocks, loadable
module clocks and clocks loaded via /lib/firmware should be allowed.
That allows mapping just the bootime clocks in DT, or all the clocks
in DT depending what suits the use case.
And yes, based on the flames I've received over the years, Linus clearly
wants the SoC specific data out of the kernel. And there's already a lot
of the SoC specific data that's now building up in various linux generic
frameworks..
> The second issue concerns where the SoC clock nodes should go in the DT.
> In these patches, the clock data has been encoded in a large "clocks" node
> off the top level. This is almost certainly not the right thing to do
> from a device hardware point of view. These clocks don't exist as
> standalone devices with their own address spaces decoded on the
> interconnect. In all of the SoC cases that I'm aware of, clock control
> registers are part of larger IP blocks.
>
> For example, in the OMAP case, most of the system integration clock
> control registers are part of the OMAP-specific PRCM block, PRM block, or
> CM block. Then there are other device-specific clocks, like DSS PLLs or
> UART dividers. The control registers for these are generally located in
> the subsystem or device IP block itself, and are inaccessible when the
> subsystem or IP block is disabled. These device-specific clocks belong to
> the IP block, not the SoC integration. So, for example, if two SoCs use
> the same IP block, then the clock registers, and their offsets from the IP
> block address space base, are likely to be identical.
>
> So in my view, the right things to do here are to:
>
> 1. associate SoC DT clock data with the device node that contains the
> clock control registers
>
> 2. specify relative offsets for clock registers from the start of
> the IP block address range, rather than absolute addresses for clock
> registers
>
> 3. place the responsibility for registering clocks into the IP block
> drivers themselves
>
> This naturally separates clocks into per-IP block DT files. It also
> provides the CCF with an easy way to ensure that the device that
> encloses the clock is enabled and accessible by the CPU core, before
> trying to access registers inside.
>
> Similarly, non-SoC off-chip clock data (such as for dedicated I2C PLLs)
> should also be associated with their I2C device node.
>
> Making these changes to Tero's existing patches should be relatively
> straightforward, based on what I've seen.
Yes that's a valid concern and makes sense to me. It also it seems that
moving clocks around with this approach does not break the binding ABI.
> Regarding the third issue: let's postulate for the moment that the clock
> binding issues that I mention in #2 above are ignored (ha!), and that the
> existing DT clock data is merged. These bindings are currently marked as
> "Unstable - ABI compatibility may be broken in the future". What happens
> if, when we meet to discuss clock bindings at the kernel summit, we decide
> that significant changes are needed? We could easily wind up with kernels
> that won't boot at all when used with newer DT data.
>
> Not to mention, merging such a large amount of code and data before the
> bindings are stable will increase the risk of massive churn as the
> bindings evolve towards stability.
>
> So IMHO, the way to fix this is to consider the clock data to be IP-block
> specific, as mentioned in #2. Then there's no need for global clock
> bindings for the SoC clock cases.
>
> Otherwise, it seems prudent to at least wait until the global clock
> bindings are no longer marked as unstable. The whole DT migration was
> predicated on the ideas of reducing churn in the Linux codebase, and
> preserving forward compatibility for DT data. We shouldn't discard these
> goals just to merge something a little sooner.
Mike suggested using ti specific bindings as the generic bindings may not
be ready for quite some time. In any case, these bindings seem like they
can be easily supported in the long run no matter what happens with the
Linux generic clock bindings.
> The fourth issue is where the clockdomain data should go. The basic issue
> here is that the notion of "clockdomains" here is completely
> OMAP-specific. OMAP clockdomains demarcate a group of clocks or IP blocks
> that share the same automatic idle behavior, controlled by their enclosing
> IP block (e.g., PRCM, PRM, CM, etc.). Clockdomains are also used in the
> OMAP kernel code to link the clocks to their enclosing power domains,
> voltage rail control, etc.
>
> So since these are OMAP PRCM/CM/PRM-specific constructs, the right place
> for OMAP clockdomain data is underneath the OMAP-specific CM/PRCM DT
> nodes. Again this should be an easy change to Tero's existing patches.
I believe Mike has made it a requirement that the clockdomains will be
moved out of the clock code in follow up patches.
> So hey, if you've made it this far, thanks for reading. My sense is that
> implementing #2 and #4 are relatively straightforward.
>
> Also, since this seems to have been a problem for some folks in the past,
> I want to make clear that I think both Mike and Tero have been doing good
> jobs on the CCF and OMAP clock patches so far.
Yes I agree.
Tony
^ permalink raw reply [flat|nested] 136+ messages in thread
* Re: [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
2013-10-09 18:59 ` Paul Walmsley
@ 2013-10-09 19:24 ` Tony Lindgren
-1 siblings, 0 replies; 136+ messages in thread
From: Tony Lindgren @ 2013-10-09 19:24 UTC (permalink / raw)
To: Paul Walmsley
Cc: Tero Kristo, mturquette, linux-omap, nm, khilman, pdeschrijver,
rnayak, bcousson, linux-arm-kernel, devicetree, swarren,
mark.rutland
* Paul Walmsley <paul@pwsan.com> [131009 12:07]:
> Eh, one correction:
>
> On Wed, 9 Oct 2013, Paul Walmsley wrote:
>
> > We could easily wind up with kernels that won't boot at all when used
> > with newer DT data.
>
> This is a misstatement of the issue: the concern here is that newer
> kernels may not boot at all with older DT data - which could easily be in
> locked areas of the flash or firmware.
That's easy to avoid by allowing any combination of DT defined clocks,
loadable module clocks and /lib/firmware clocks depending on the use
case.
The older kernels have the clocks defined in DT, the newer kernels just
need to parse them.
Regards,
Tony
^ permalink raw reply [flat|nested] 136+ messages in thread
* [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
@ 2013-10-09 19:24 ` Tony Lindgren
0 siblings, 0 replies; 136+ messages in thread
From: Tony Lindgren @ 2013-10-09 19:24 UTC (permalink / raw)
To: linux-arm-kernel
* Paul Walmsley <paul@pwsan.com> [131009 12:07]:
> Eh, one correction:
>
> On Wed, 9 Oct 2013, Paul Walmsley wrote:
>
> > We could easily wind up with kernels that won't boot at all when used
> > with newer DT data.
>
> This is a misstatement of the issue: the concern here is that newer
> kernels may not boot at all with older DT data - which could easily be in
> locked areas of the flash or firmware.
That's easy to avoid by allowing any combination of DT defined clocks,
loadable module clocks and /lib/firmware clocks depending on the use
case.
The older kernels have the clocks defined in DT, the newer kernels just
need to parse them.
Regards,
Tony
^ permalink raw reply [flat|nested] 136+ messages in thread
* Re: [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
2013-10-09 18:59 ` Paul Walmsley
@ 2013-10-10 7:18 ` Tero Kristo
-1 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-10-10 7:18 UTC (permalink / raw)
To: Paul Walmsley, Tony Lindgren, mturquette
Cc: linux-omap, nm, khilman, pdeschrijver, rnayak, bcousson,
linux-arm-kernel, devicetree, swarren, mark.rutland
On 10/09/2013 09:59 PM, Paul Walmsley wrote:
> Eh, one correction:
>
> On Wed, 9 Oct 2013, Paul Walmsley wrote:
>
>> We could easily wind up with kernels that won't boot at all when used
>> with newer DT data.
>
> This is a misstatement of the issue: the concern here is that newer
> kernels may not boot at all with older DT data - which could easily be in
> locked areas of the flash or firmware.
I wonder who would be crazy enough to put DT data into a locked area,
and to what purpose. If you can update the kernel, there is no point
locking down DT data, this will just cause you unnecessary misery.
-Tero
^ permalink raw reply [flat|nested] 136+ messages in thread
* [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
@ 2013-10-10 7:18 ` Tero Kristo
0 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-10-10 7:18 UTC (permalink / raw)
To: linux-arm-kernel
On 10/09/2013 09:59 PM, Paul Walmsley wrote:
> Eh, one correction:
>
> On Wed, 9 Oct 2013, Paul Walmsley wrote:
>
>> We could easily wind up with kernels that won't boot at all when used
>> with newer DT data.
>
> This is a misstatement of the issue: the concern here is that newer
> kernels may not boot at all with older DT data - which could easily be in
> locked areas of the flash or firmware.
I wonder who would be crazy enough to put DT data into a locked area,
and to what purpose. If you can update the kernel, there is no point
locking down DT data, this will just cause you unnecessary misery.
-Tero
^ permalink raw reply [flat|nested] 136+ messages in thread
* Re: [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
2013-10-09 18:55 ` Paul Walmsley
@ 2013-10-10 8:17 ` Tero Kristo
-1 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-10-10 8:17 UTC (permalink / raw)
To: Paul Walmsley, Tony Lindgren, mturquette
Cc: linux-omap, nm, khilman, pdeschrijver, rnayak, bcousson,
linux-arm-kernel, devicetree, swarren, mark.rutland
Hey Paul,
My dibs on this below.
On 10/09/2013 09:55 PM, Paul Walmsley wrote:
> On Mon, 7 Oct 2013, Tony Lindgren wrote:
>
>> And assuming Paul is OK with these patches in general.
>
> Actually, I have several concerns with this series, as you and I
> discussed. Some of us have been talking them over with other folks for
> the past few months to try to figure out what to do. Most of the concerns
> have fairly easy technical solutions, but we shouldn't merge these patches
> until they're resolved.
>
> The issues are:
>
> 1. whether the clock data should go into DT
> 2. what the right place for DT clock data is in the DT
> 3. whether it makes sense to merge "experimental" DT bindings in this case
> 4. where clockdomain data belongs
>
> The first issue - and the one I'm least concerned about - is that, in my
> view, it still does not make technical sense to move this data into DT.
> This is chip-level hardware data that never needs to be changed by board
> designers or end users. Adding it to DT is going to result in a boot-time
> cost (due to DT parse overhead) and additional memory consumption for very
> little benefit, compared to an implementation that places this data into a
> dynamically loadable module. For some users, the boot-time bloat is a big
> deal: the example that's been mentioned to me recently is an automotive
> back-up camera that needs to cold-boot to complete functionality in a few
> hundred microseconds.
Personally I share the concern, I don't see much point in using the DT
for any kind of purpose... it is just another binary compatibility
breaker in the picture in addition to boot-loader, and it basically does
not solve any _real_ problems either.
Boot time issues can be solved by adding alternative clock data sources
like Tony pointed out, granted, we don't have support for those yet, but
we need to start somewhere.
> However, according to some other upstream maintainers, Linus's goal is to
> move most of the device-specific static data out of the kernel tree, into
> DT files (in the ARM case). If that non-technical constraint is indeed
> the dominant consideration, then I agree that moving this data to DT is
> the only viable course of action.
Yeah... Personally I can't see any other way forward right now either as
I was basically given the option to use DT for this work or not do it at
all...
>
> ...
>
> The second issue concerns where the SoC clock nodes should go in the DT.
> In these patches, the clock data has been encoded in a large "clocks" node
> off the top level. This is almost certainly not the right thing to do
> from a device hardware point of view. These clocks don't exist as
> standalone devices with their own address spaces decoded on the
> interconnect. In all of the SoC cases that I'm aware of, clock control
> registers are part of larger IP blocks.
>
> For example, in the OMAP case, most of the system integration clock
> control registers are part of the OMAP-specific PRCM block, PRM block, or
> CM block. Then there are other device-specific clocks, like DSS PLLs or
> UART dividers. The control registers for these are generally located in
> the subsystem or device IP block itself, and are inaccessible when the
> subsystem or IP block is disabled. These device-specific clocks belong to
> the IP block, not the SoC integration. So, for example, if two SoCs use
> the same IP block, then the clock registers, and their offsets from the IP
> block address space base, are likely to be identical.
None of the clock registers defined in this set reside outside PRCM /
control module, so they are always accessible. IP block internal
dividers for UART and like, are defined and used only internally by the
device drivers.
>
> So in my view, the right things to do here are to:
>
> 1. associate SoC DT clock data with the device node that contains the
> clock control registers
So, either "cm", "prcm", and maybe "control_module" instead of current
"clocks". How much do we benefit from this? This would get rid of need
to call of_iomap() for each register basically.
>
> 2. specify relative offsets for clock registers from the start of
> the IP block address range, rather than absolute addresses for clock
> registers
>
> 3. place the responsibility for registering clocks into the IP block
> drivers themselves
>
> This naturally separates clocks into per-IP block DT files. It also
> provides the CCF with an easy way to ensure that the device that
> encloses the clock is enabled and accessible by the CPU core, before
> trying to access registers inside.
>
> Similarly, non-SoC off-chip clock data (such as for dedicated I2C PLLs)
> should also be associated with their I2C device node.
>
> Making these changes to Tero's existing patches should be relatively
> straightforward, based on what I've seen.
For the set, it doesn't matter where the clock nodes reside, if someone
can point me out where to put them, they can be easily moved around.
Separating the individual clocks based on their IP mapping can probably
just be done by checking their register address.
Anyway, I would like to have a concensus if something like this should
be done or not before starting to do the changes, as this is going to
change the layout of the clock data completely, and will require a
complete new testing + debugging round to be done, in addition to script
changes.
> ...
>
> Regarding the third issue: let's postulate for the moment that the clock
> binding issues that I mention in #2 above are ignored (ha!), and that the
> existing DT clock data is merged. These bindings are currently marked as
> "Unstable - ABI compatibility may be broken in the future". What happens
> if, when we meet to discuss clock bindings at the kernel summit, we decide
> that significant changes are needed? We could easily wind up with kernels
> that won't boot at all when used with newer DT data.
>
> Not to mention, merging such a large amount of code and data before the
> bindings are stable will increase the risk of massive churn as the
> bindings evolve towards stability.
>
> So IMHO, the way to fix this is to consider the clock data to be IP-block
> specific, as mentioned in #2. Then there's no need for global clock
> bindings for the SoC clock cases.
>
> Otherwise, it seems prudent to at least wait until the global clock
> bindings are no longer marked as unstable. The whole DT migration was
> predicated on the ideas of reducing churn in the Linux codebase, and
> preserving forward compatibility for DT data. We shouldn't discard these
> goals just to merge something a little sooner.
Well, we can keep support for the vendor specific clock bindings in the
kernel and if generic bindings will eventually go forward, we can evolve
towards that. A pressing problem for this work to proceed is that we
need to get boot support for some new SoCs in rather sooner than again
wait two years and work with TI internal trees. And getting the boot
support quickly in, it seems the only way to get it done is via vendor
specific bindings, which are unstable in a sense that _if_ the generic
bindings go forward, we should start using those instead.
> ...
>
> The fourth issue is where the clockdomain data should go. The basic issue
> here is that the notion of "clockdomains" here is completely
> OMAP-specific. OMAP clockdomains demarcate a group of clocks or IP blocks
> that share the same automatic idle behavior, controlled by their enclosing
> IP block (e.g., PRCM, PRM, CM, etc.). Clockdomains are also used in the
> OMAP kernel code to link the clocks to their enclosing power domains,
> voltage rail control, etc.
>
> So since these are OMAP PRCM/CM/PRM-specific constructs, the right place
> for OMAP clockdomain data is underneath the OMAP-specific CM/PRCM DT
> nodes. Again this should be an easy change to Tero's existing patches.
Yea, does not matter where in the dts files these reside. Clockdomain
bindings / code implementation can be moved to wherever the CM code is
going to move, and this should not cause any changes to the clockdomain
binding definitions. Anyway, again I would like to have a clear
concensus if the bindings should move someplace else before doing the
changes.
-Tero
>
> ...
>
> So hey, if you've made it this far, thanks for reading. My sense is that
> implementing #2 and #4 are relatively straightforward.
>
> Also, since this seems to have been a problem for some folks in the past,
> I want to make clear that I think both Mike and Tero have been doing good
> jobs on the CCF and OMAP clock patches so far.
>
> regards
>
> - Paul
>
^ permalink raw reply [flat|nested] 136+ messages in thread
* [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
@ 2013-10-10 8:17 ` Tero Kristo
0 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-10-10 8:17 UTC (permalink / raw)
To: linux-arm-kernel
Hey Paul,
My dibs on this below.
On 10/09/2013 09:55 PM, Paul Walmsley wrote:
> On Mon, 7 Oct 2013, Tony Lindgren wrote:
>
>> And assuming Paul is OK with these patches in general.
>
> Actually, I have several concerns with this series, as you and I
> discussed. Some of us have been talking them over with other folks for
> the past few months to try to figure out what to do. Most of the concerns
> have fairly easy technical solutions, but we shouldn't merge these patches
> until they're resolved.
>
> The issues are:
>
> 1. whether the clock data should go into DT
> 2. what the right place for DT clock data is in the DT
> 3. whether it makes sense to merge "experimental" DT bindings in this case
> 4. where clockdomain data belongs
>
> The first issue - and the one I'm least concerned about - is that, in my
> view, it still does not make technical sense to move this data into DT.
> This is chip-level hardware data that never needs to be changed by board
> designers or end users. Adding it to DT is going to result in a boot-time
> cost (due to DT parse overhead) and additional memory consumption for very
> little benefit, compared to an implementation that places this data into a
> dynamically loadable module. For some users, the boot-time bloat is a big
> deal: the example that's been mentioned to me recently is an automotive
> back-up camera that needs to cold-boot to complete functionality in a few
> hundred microseconds.
Personally I share the concern, I don't see much point in using the DT
for any kind of purpose... it is just another binary compatibility
breaker in the picture in addition to boot-loader, and it basically does
not solve any _real_ problems either.
Boot time issues can be solved by adding alternative clock data sources
like Tony pointed out, granted, we don't have support for those yet, but
we need to start somewhere.
> However, according to some other upstream maintainers, Linus's goal is to
> move most of the device-specific static data out of the kernel tree, into
> DT files (in the ARM case). If that non-technical constraint is indeed
> the dominant consideration, then I agree that moving this data to DT is
> the only viable course of action.
Yeah... Personally I can't see any other way forward right now either as
I was basically given the option to use DT for this work or not do it at
all...
>
> ...
>
> The second issue concerns where the SoC clock nodes should go in the DT.
> In these patches, the clock data has been encoded in a large "clocks" node
> off the top level. This is almost certainly not the right thing to do
> from a device hardware point of view. These clocks don't exist as
> standalone devices with their own address spaces decoded on the
> interconnect. In all of the SoC cases that I'm aware of, clock control
> registers are part of larger IP blocks.
>
> For example, in the OMAP case, most of the system integration clock
> control registers are part of the OMAP-specific PRCM block, PRM block, or
> CM block. Then there are other device-specific clocks, like DSS PLLs or
> UART dividers. The control registers for these are generally located in
> the subsystem or device IP block itself, and are inaccessible when the
> subsystem or IP block is disabled. These device-specific clocks belong to
> the IP block, not the SoC integration. So, for example, if two SoCs use
> the same IP block, then the clock registers, and their offsets from the IP
> block address space base, are likely to be identical.
None of the clock registers defined in this set reside outside PRCM /
control module, so they are always accessible. IP block internal
dividers for UART and like, are defined and used only internally by the
device drivers.
>
> So in my view, the right things to do here are to:
>
> 1. associate SoC DT clock data with the device node that contains the
> clock control registers
So, either "cm", "prcm", and maybe "control_module" instead of current
"clocks". How much do we benefit from this? This would get rid of need
to call of_iomap() for each register basically.
>
> 2. specify relative offsets for clock registers from the start of
> the IP block address range, rather than absolute addresses for clock
> registers
>
> 3. place the responsibility for registering clocks into the IP block
> drivers themselves
>
> This naturally separates clocks into per-IP block DT files. It also
> provides the CCF with an easy way to ensure that the device that
> encloses the clock is enabled and accessible by the CPU core, before
> trying to access registers inside.
>
> Similarly, non-SoC off-chip clock data (such as for dedicated I2C PLLs)
> should also be associated with their I2C device node.
>
> Making these changes to Tero's existing patches should be relatively
> straightforward, based on what I've seen.
For the set, it doesn't matter where the clock nodes reside, if someone
can point me out where to put them, they can be easily moved around.
Separating the individual clocks based on their IP mapping can probably
just be done by checking their register address.
Anyway, I would like to have a concensus if something like this should
be done or not before starting to do the changes, as this is going to
change the layout of the clock data completely, and will require a
complete new testing + debugging round to be done, in addition to script
changes.
> ...
>
> Regarding the third issue: let's postulate for the moment that the clock
> binding issues that I mention in #2 above are ignored (ha!), and that the
> existing DT clock data is merged. These bindings are currently marked as
> "Unstable - ABI compatibility may be broken in the future". What happens
> if, when we meet to discuss clock bindings at the kernel summit, we decide
> that significant changes are needed? We could easily wind up with kernels
> that won't boot at all when used with newer DT data.
>
> Not to mention, merging such a large amount of code and data before the
> bindings are stable will increase the risk of massive churn as the
> bindings evolve towards stability.
>
> So IMHO, the way to fix this is to consider the clock data to be IP-block
> specific, as mentioned in #2. Then there's no need for global clock
> bindings for the SoC clock cases.
>
> Otherwise, it seems prudent to at least wait until the global clock
> bindings are no longer marked as unstable. The whole DT migration was
> predicated on the ideas of reducing churn in the Linux codebase, and
> preserving forward compatibility for DT data. We shouldn't discard these
> goals just to merge something a little sooner.
Well, we can keep support for the vendor specific clock bindings in the
kernel and if generic bindings will eventually go forward, we can evolve
towards that. A pressing problem for this work to proceed is that we
need to get boot support for some new SoCs in rather sooner than again
wait two years and work with TI internal trees. And getting the boot
support quickly in, it seems the only way to get it done is via vendor
specific bindings, which are unstable in a sense that _if_ the generic
bindings go forward, we should start using those instead.
> ...
>
> The fourth issue is where the clockdomain data should go. The basic issue
> here is that the notion of "clockdomains" here is completely
> OMAP-specific. OMAP clockdomains demarcate a group of clocks or IP blocks
> that share the same automatic idle behavior, controlled by their enclosing
> IP block (e.g., PRCM, PRM, CM, etc.). Clockdomains are also used in the
> OMAP kernel code to link the clocks to their enclosing power domains,
> voltage rail control, etc.
>
> So since these are OMAP PRCM/CM/PRM-specific constructs, the right place
> for OMAP clockdomain data is underneath the OMAP-specific CM/PRCM DT
> nodes. Again this should be an easy change to Tero's existing patches.
Yea, does not matter where in the dts files these reside. Clockdomain
bindings / code implementation can be moved to wherever the CM code is
going to move, and this should not cause any changes to the clockdomain
binding definitions. Anyway, again I would like to have a clear
concensus if the bindings should move someplace else before doing the
changes.
-Tero
>
> ...
>
> So hey, if you've made it this far, thanks for reading. My sense is that
> implementing #2 and #4 are relatively straightforward.
>
> Also, since this seems to have been a problem for some folks in the past,
> I want to make clear that I think both Mike and Tero have been doing good
> jobs on the CCF and OMAP clock patches so far.
>
> regards
>
> - Paul
>
^ permalink raw reply [flat|nested] 136+ messages in thread
* Re: [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
2013-10-10 7:18 ` Tero Kristo
@ 2013-10-11 17:54 ` Paul Walmsley
-1 siblings, 0 replies; 136+ messages in thread
From: Paul Walmsley @ 2013-10-11 17:54 UTC (permalink / raw)
To: Tero Kristo
Cc: Tony Lindgren, mturquette, linux-omap, nm, khilman, pdeschrijver,
rnayak, bcousson, linux-arm-kernel, devicetree, swarren,
mark.rutland
On Thu, 10 Oct 2013, Tero Kristo wrote:
> On 10/09/2013 09:59 PM, Paul Walmsley wrote:
> > Eh, one correction:
> >
> > On Wed, 9 Oct 2013, Paul Walmsley wrote:
> >
> > > We could easily wind up with kernels that won't boot at all when used
> > > with newer DT data.
> >
> > This is a misstatement of the issue: the concern here is that newer
> > kernels may not boot at all with older DT data - which could easily be in
> > locked areas of the flash or firmware.
>
> I wonder who would be crazy enough to put DT data into a locked area, and to
> what purpose. If you can update the kernel, there is no point locking down DT
> data, this will just cause you unnecessary misery.
The DT data will be used by bootloaders also :-(
In situations where the bootloaders are signed and locked, the security
people are also insisting that the DT data be signed and locked.
- Paul
^ permalink raw reply [flat|nested] 136+ messages in thread
* [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
@ 2013-10-11 17:54 ` Paul Walmsley
0 siblings, 0 replies; 136+ messages in thread
From: Paul Walmsley @ 2013-10-11 17:54 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, 10 Oct 2013, Tero Kristo wrote:
> On 10/09/2013 09:59 PM, Paul Walmsley wrote:
> > Eh, one correction:
> >
> > On Wed, 9 Oct 2013, Paul Walmsley wrote:
> >
> > > We could easily wind up with kernels that won't boot at all when used
> > > with newer DT data.
> >
> > This is a misstatement of the issue: the concern here is that newer
> > kernels may not boot at all with older DT data - which could easily be in
> > locked areas of the flash or firmware.
>
> I wonder who would be crazy enough to put DT data into a locked area, and to
> what purpose. If you can update the kernel, there is no point locking down DT
> data, this will just cause you unnecessary misery.
The DT data will be used by bootloaders also :-(
In situations where the bootloaders are signed and locked, the security
people are also insisting that the DT data be signed and locked.
- Paul
^ permalink raw reply [flat|nested] 136+ messages in thread
* Re: [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
2013-10-11 17:54 ` Paul Walmsley
@ 2013-10-11 18:23 ` Tero Kristo
-1 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-10-11 18:23 UTC (permalink / raw)
To: Paul Walmsley
Cc: Tony Lindgren, mturquette, linux-omap, nm, khilman, pdeschrijver,
rnayak, bcousson, linux-arm-kernel, devicetree, swarren,
mark.rutland
On 10/11/2013 08:54 PM, Paul Walmsley wrote:
> On Thu, 10 Oct 2013, Tero Kristo wrote:
>
>> On 10/09/2013 09:59 PM, Paul Walmsley wrote:
>>> Eh, one correction:
>>>
>>> On Wed, 9 Oct 2013, Paul Walmsley wrote:
>>>
>>>> We could easily wind up with kernels that won't boot at all when used
>>>> with newer DT data.
>>>
>>> This is a misstatement of the issue: the concern here is that newer
>>> kernels may not boot at all with older DT data - which could easily be in
>>> locked areas of the flash or firmware.
>>
>> I wonder who would be crazy enough to put DT data into a locked area, and to
>> what purpose. If you can update the kernel, there is no point locking down DT
>> data, this will just cause you unnecessary misery.
>
> The DT data will be used by bootloaders also :-(
>
> In situations where the bootloaders are signed and locked, the security
> people are also insisting that the DT data be signed and locked.
Well, even if you sign something, you can still update it. Writing any
software to true OTP memory is one way to commit suicide IMO. How many
nasty bugs have you seen with ROM code? Also, if people want to make
their custom security solutions which are not supported by the kernel,
why should the kernel care about it? We don't know the details, and
can't influence the design, so we can't prepare for it anyway.
-Tero
^ permalink raw reply [flat|nested] 136+ messages in thread
* [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
@ 2013-10-11 18:23 ` Tero Kristo
0 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-10-11 18:23 UTC (permalink / raw)
To: linux-arm-kernel
On 10/11/2013 08:54 PM, Paul Walmsley wrote:
> On Thu, 10 Oct 2013, Tero Kristo wrote:
>
>> On 10/09/2013 09:59 PM, Paul Walmsley wrote:
>>> Eh, one correction:
>>>
>>> On Wed, 9 Oct 2013, Paul Walmsley wrote:
>>>
>>>> We could easily wind up with kernels that won't boot at all when used
>>>> with newer DT data.
>>>
>>> This is a misstatement of the issue: the concern here is that newer
>>> kernels may not boot at all with older DT data - which could easily be in
>>> locked areas of the flash or firmware.
>>
>> I wonder who would be crazy enough to put DT data into a locked area, and to
>> what purpose. If you can update the kernel, there is no point locking down DT
>> data, this will just cause you unnecessary misery.
>
> The DT data will be used by bootloaders also :-(
>
> In situations where the bootloaders are signed and locked, the security
> people are also insisting that the DT data be signed and locked.
Well, even if you sign something, you can still update it. Writing any
software to true OTP memory is one way to commit suicide IMO. How many
nasty bugs have you seen with ROM code? Also, if people want to make
their custom security solutions which are not supported by the kernel,
why should the kernel care about it? We don't know the details, and
can't influence the design, so we can't prepare for it anyway.
-Tero
^ permalink raw reply [flat|nested] 136+ messages in thread
* Re: [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
2013-10-11 17:54 ` Paul Walmsley
@ 2013-10-11 18:46 ` Tero Kristo
-1 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-10-11 18:46 UTC (permalink / raw)
To: Paul Walmsley
Cc: Tony Lindgren, mturquette, linux-omap, nm, khilman, pdeschrijver,
rnayak, bcousson, linux-arm-kernel, devicetree, swarren,
mark.rutland
On 10/11/2013 08:54 PM, Paul Walmsley wrote:
> On Thu, 10 Oct 2013, Tero Kristo wrote:
>
>> On 10/09/2013 09:59 PM, Paul Walmsley wrote:
>>> Eh, one correction:
>>>
>>> On Wed, 9 Oct 2013, Paul Walmsley wrote:
>>>
>>>> We could easily wind up with kernels that won't boot at all when used
>>>> with newer DT data.
>>>
>>> This is a misstatement of the issue: the concern here is that newer
>>> kernels may not boot at all with older DT data - which could easily be in
>>> locked areas of the flash or firmware.
>>
>> I wonder who would be crazy enough to put DT data into a locked area, and to
>> what purpose. If you can update the kernel, there is no point locking down DT
>> data, this will just cause you unnecessary misery.
>
> The DT data will be used by bootloaders also :-(
>
> In situations where the bootloaders are signed and locked, the security
> people are also insisting that the DT data be signed and locked.
Oh yea, one additional note you probably have missed. Mike asked us to
fall back to vendor specific bindings at around v6 or so of this set.
Take a look at v8, we have dropped the use of generic bindings, we are
not trying to declare those with this set. This set introduces vendor
specific bindings only, and even these are claimed 'unstable', which
should be enough to discourage people from burning those to OTP type memory.
-Tero
^ permalink raw reply [flat|nested] 136+ messages in thread
* [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
@ 2013-10-11 18:46 ` Tero Kristo
0 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-10-11 18:46 UTC (permalink / raw)
To: linux-arm-kernel
On 10/11/2013 08:54 PM, Paul Walmsley wrote:
> On Thu, 10 Oct 2013, Tero Kristo wrote:
>
>> On 10/09/2013 09:59 PM, Paul Walmsley wrote:
>>> Eh, one correction:
>>>
>>> On Wed, 9 Oct 2013, Paul Walmsley wrote:
>>>
>>>> We could easily wind up with kernels that won't boot at all when used
>>>> with newer DT data.
>>>
>>> This is a misstatement of the issue: the concern here is that newer
>>> kernels may not boot at all with older DT data - which could easily be in
>>> locked areas of the flash or firmware.
>>
>> I wonder who would be crazy enough to put DT data into a locked area, and to
>> what purpose. If you can update the kernel, there is no point locking down DT
>> data, this will just cause you unnecessary misery.
>
> The DT data will be used by bootloaders also :-(
>
> In situations where the bootloaders are signed and locked, the security
> people are also insisting that the DT data be signed and locked.
Oh yea, one additional note you probably have missed. Mike asked us to
fall back to vendor specific bindings at around v6 or so of this set.
Take a look at v8, we have dropped the use of generic bindings, we are
not trying to declare those with this set. This set introduces vendor
specific bindings only, and even these are claimed 'unstable', which
should be enough to discourage people from burning those to OTP type memory.
-Tero
^ permalink raw reply [flat|nested] 136+ messages in thread
* Re: [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
2013-10-11 18:23 ` Tero Kristo
@ 2013-10-11 22:26 ` Paul Walmsley
-1 siblings, 0 replies; 136+ messages in thread
From: Paul Walmsley @ 2013-10-11 22:26 UTC (permalink / raw)
To: Tero Kristo
Cc: Tony Lindgren, mturquette, linux-omap, nm, khilman, pdeschrijver,
rnayak, bcousson, linux-arm-kernel, devicetree, swarren,
mark.rutland
On Fri, 11 Oct 2013, Tero Kristo wrote:
> Well, even if you sign something, you can still update it. Writing any
> software to true OTP memory is one way to commit suicide IMO. How many nasty
> bugs have you seen with ROM code? Also, if people want to make their custom
> security solutions which are not supported by the kernel, why should the
> kernel care about it? We don't know the details, and can't influence the
> design, so we can't prepare for it anyway.
The point is that newer kernels need to be compatible with older DT data:
that's the "stable ABI" criterion that's been discussed quite a bit. The
worst-case scenario if the bindings are at a top-level node and not fully
cooked is that it can make it very difficult, if not impossible, to have
this forward compatibility for the DT data without having extremely nasty
hacks.
- Paul
^ permalink raw reply [flat|nested] 136+ messages in thread
* [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
@ 2013-10-11 22:26 ` Paul Walmsley
0 siblings, 0 replies; 136+ messages in thread
From: Paul Walmsley @ 2013-10-11 22:26 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, 11 Oct 2013, Tero Kristo wrote:
> Well, even if you sign something, you can still update it. Writing any
> software to true OTP memory is one way to commit suicide IMO. How many nasty
> bugs have you seen with ROM code? Also, if people want to make their custom
> security solutions which are not supported by the kernel, why should the
> kernel care about it? We don't know the details, and can't influence the
> design, so we can't prepare for it anyway.
The point is that newer kernels need to be compatible with older DT data:
that's the "stable ABI" criterion that's been discussed quite a bit. The
worst-case scenario if the bindings are at a top-level node and not fully
cooked is that it can make it very difficult, if not impossible, to have
this forward compatibility for the DT data without having extremely nasty
hacks.
- Paul
^ permalink raw reply [flat|nested] 136+ messages in thread
* Re: [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
2013-10-11 18:46 ` Tero Kristo
@ 2013-10-11 22:37 ` Paul Walmsley
-1 siblings, 0 replies; 136+ messages in thread
From: Paul Walmsley @ 2013-10-11 22:37 UTC (permalink / raw)
To: devicetree, Tero Kristo
Cc: Tony Lindgren, mturquette, linux-omap, nm, khilman, pdeschrijver,
rnayak, bcousson, linux-arm-kernel, swarren, mark.rutland
On Fri, 11 Oct 2013, Tero Kristo wrote:
> Oh yea, one additional note you probably have missed. Mike asked us to fall
> back to vendor specific bindings at around v6 or so of this set. Take a look
> at v8, we have dropped the use of generic bindings, we are not trying to
> declare those with this set.
No, I didn't miss it.
> This set introduces vendor specific bindings only, and even these are
> claimed 'unstable', which should be enough to discourage people from
> burning those to OTP type memory.
Better to just avoid merging unstable bindings in the first place.
Please keep this in mind: any change that anyone makes to the DT data
needs to be supportable by the kernel into the indefinite future, once it
makes it into arch/arm/boot/dts or the DT binding documentation. Also,
any changes need to work for other OSes, i.e., the changes should not be
Linux-specific.
Those have been stated goals for the Linux DT project since day one.
Some folks haven't been monitoring those goals very closely and that's
unfortunate. We could have avoided some pretty big messes.
- Paul
^ permalink raw reply [flat|nested] 136+ messages in thread
* [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
@ 2013-10-11 22:37 ` Paul Walmsley
0 siblings, 0 replies; 136+ messages in thread
From: Paul Walmsley @ 2013-10-11 22:37 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, 11 Oct 2013, Tero Kristo wrote:
> Oh yea, one additional note you probably have missed. Mike asked us to fall
> back to vendor specific bindings at around v6 or so of this set. Take a look
> at v8, we have dropped the use of generic bindings, we are not trying to
> declare those with this set.
No, I didn't miss it.
> This set introduces vendor specific bindings only, and even these are
> claimed 'unstable', which should be enough to discourage people from
> burning those to OTP type memory.
Better to just avoid merging unstable bindings in the first place.
Please keep this in mind: any change that anyone makes to the DT data
needs to be supportable by the kernel into the indefinite future, once it
makes it into arch/arm/boot/dts or the DT binding documentation. Also,
any changes need to work for other OSes, i.e., the changes should not be
Linux-specific.
Those have been stated goals for the Linux DT project since day one.
Some folks haven't been monitoring those goals very closely and that's
unfortunate. We could have avoided some pretty big messes.
- Paul
^ permalink raw reply [flat|nested] 136+ messages in thread
* Re: [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
2013-10-10 8:17 ` Tero Kristo
@ 2013-10-11 22:53 ` Tony Lindgren
-1 siblings, 0 replies; 136+ messages in thread
From: Tony Lindgren @ 2013-10-11 22:53 UTC (permalink / raw)
To: Tero Kristo
Cc: Paul Walmsley, mturquette, linux-omap, nm, khilman, pdeschrijver,
rnayak, bcousson, linux-arm-kernel, devicetree, swarren,
mark.rutland
* Tero Kristo <t-kristo@ti.com> [131010 01:25]:
> On 10/09/2013 09:55 PM, Paul Walmsley wrote:
> >So in my view, the right things to do here are to:
> >
> >1. associate SoC DT clock data with the device node that contains the
> > clock control registers
>
> So, either "cm", "prcm", and maybe "control_module" instead of
> current "clocks". How much do we benefit from this? This would get
> rid of need to call of_iomap() for each register basically.
It seems that all you need to do for that is to set up two or three
clock driver instances and have the clocks registered under them.
Then later on those can be children of cm, prcm and scm core drivers
as needed without much of an issue.
Regards,
Tony
^ permalink raw reply [flat|nested] 136+ messages in thread
* [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
@ 2013-10-11 22:53 ` Tony Lindgren
0 siblings, 0 replies; 136+ messages in thread
From: Tony Lindgren @ 2013-10-11 22:53 UTC (permalink / raw)
To: linux-arm-kernel
* Tero Kristo <t-kristo@ti.com> [131010 01:25]:
> On 10/09/2013 09:55 PM, Paul Walmsley wrote:
> >So in my view, the right things to do here are to:
> >
> >1. associate SoC DT clock data with the device node that contains the
> > clock control registers
>
> So, either "cm", "prcm", and maybe "control_module" instead of
> current "clocks". How much do we benefit from this? This would get
> rid of need to call of_iomap() for each register basically.
It seems that all you need to do for that is to set up two or three
clock driver instances and have the clocks registered under them.
Then later on those can be children of cm, prcm and scm core drivers
as needed without much of an issue.
Regards,
Tony
^ permalink raw reply [flat|nested] 136+ messages in thread
* Re: [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
2013-10-11 22:37 ` Paul Walmsley
@ 2013-10-12 10:25 ` Tero Kristo
-1 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-10-12 10:25 UTC (permalink / raw)
To: Paul Walmsley, devicetree
Cc: Tony Lindgren, mturquette, linux-omap, nm, khilman, pdeschrijver,
rnayak, bcousson, linux-arm-kernel, swarren, mark.rutland
On 10/12/2013 01:37 AM, Paul Walmsley wrote:
> On Fri, 11 Oct 2013, Tero Kristo wrote:
>
>> Oh yea, one additional note you probably have missed. Mike asked us to fall
>> back to vendor specific bindings at around v6 or so of this set. Take a look
>> at v8, we have dropped the use of generic bindings, we are not trying to
>> declare those with this set.
>
> No, I didn't miss it.
>
>> This set introduces vendor specific bindings only, and even these are
>> claimed 'unstable', which should be enough to discourage people from
>> burning those to OTP type memory.
>
> Better to just avoid merging unstable bindings in the first place.
>
> Please keep this in mind: any change that anyone makes to the DT data
> needs to be supportable by the kernel into the indefinite future, once it
> makes it into arch/arm/boot/dts or the DT binding documentation. Also,
> any changes need to work for other OSes, i.e., the changes should not be
> Linux-specific.
As pointed out earlier, the unstable claim just points to the fact that
we might have some generic clock bindings in distant future at which
point we _might_ evolve that way. Personally I have no problems carrying
these binding to the far future, as they are vendor specific, and pretty
much also device specific (am3-dpll-* omap4-dpll-* etc.)
Later on, we can add also support for clock firmware or whatever if we
want to optimize stuff.
If we do not merge the bindings now, what is your proposal then? We have
a couple of new SoC:s in queue and getting them boot mainline currently
we only have this option to get them to work. Hardware is not going to
wait for two years so we can have generic clock bindings in place. I
would rather have this resolved as soon as possible, and it would have
been much better if you came forward with your claims at version 1 or 2
of this set, rather than at v8 and saying all should be forfeit.
-Tero
>
> Those have been stated goals for the Linux DT project since day one.
> Some folks haven't been monitoring those goals very closely and that's
> unfortunate. We could have avoided some pretty big messes.
>
>
> - Paul
>
^ permalink raw reply [flat|nested] 136+ messages in thread
* [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
@ 2013-10-12 10:25 ` Tero Kristo
0 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-10-12 10:25 UTC (permalink / raw)
To: linux-arm-kernel
On 10/12/2013 01:37 AM, Paul Walmsley wrote:
> On Fri, 11 Oct 2013, Tero Kristo wrote:
>
>> Oh yea, one additional note you probably have missed. Mike asked us to fall
>> back to vendor specific bindings at around v6 or so of this set. Take a look
>> at v8, we have dropped the use of generic bindings, we are not trying to
>> declare those with this set.
>
> No, I didn't miss it.
>
>> This set introduces vendor specific bindings only, and even these are
>> claimed 'unstable', which should be enough to discourage people from
>> burning those to OTP type memory.
>
> Better to just avoid merging unstable bindings in the first place.
>
> Please keep this in mind: any change that anyone makes to the DT data
> needs to be supportable by the kernel into the indefinite future, once it
> makes it into arch/arm/boot/dts or the DT binding documentation. Also,
> any changes need to work for other OSes, i.e., the changes should not be
> Linux-specific.
As pointed out earlier, the unstable claim just points to the fact that
we might have some generic clock bindings in distant future at which
point we _might_ evolve that way. Personally I have no problems carrying
these binding to the far future, as they are vendor specific, and pretty
much also device specific (am3-dpll-* omap4-dpll-* etc.)
Later on, we can add also support for clock firmware or whatever if we
want to optimize stuff.
If we do not merge the bindings now, what is your proposal then? We have
a couple of new SoC:s in queue and getting them boot mainline currently
we only have this option to get them to work. Hardware is not going to
wait for two years so we can have generic clock bindings in place. I
would rather have this resolved as soon as possible, and it would have
been much better if you came forward with your claims at version 1 or 2
of this set, rather than at v8 and saying all should be forfeit.
-Tero
>
> Those have been stated goals for the Linux DT project since day one.
> Some folks haven't been monitoring those goals very closely and that's
> unfortunate. We could have avoided some pretty big messes.
>
>
> - Paul
>
^ permalink raw reply [flat|nested] 136+ messages in thread
* Re: [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
2013-10-12 10:25 ` Tero Kristo
@ 2013-10-13 23:45 ` Paul Walmsley
-1 siblings, 0 replies; 136+ messages in thread
From: Paul Walmsley @ 2013-10-13 23:45 UTC (permalink / raw)
To: Tero Kristo
Cc: devicetree, Tony Lindgren, mturquette, linux-omap, nm, khilman,
pdeschrijver, rnayak, bcousson, linux-arm-kernel, swarren,
mark.rutland
Here you go:
1. Create DT nodes for the IP blocks that contain the clock control
registers, underneath the appropriate bus node. So for example OMAP4
would have:
/ocp {
prm@4a306000 {
compatible = xxx;
regs = <0x4a306000 xxxx>;
};
cm1@4a004000 {
compatible = xxx;
regs = <0x4a004000 xxxx>;
};
cm2@4a008000 {
compatible = xxx;
regs = <0x4a008000 xxxx>;
};
};
This is pure OS-independent hardware description (with the unfortunate
exception of the "ocp" part).
2. Create the clock data underneath the corresponding PRCM/CM/PRM device
nodes that their control registers exist in. So for example, dpll_per_ck
would belong to the "cm1" device, since that's where its control registers
are located. Something like this:
cm1@4a004000 {
...
clocks {
dpll_per_ck@.... {
<clock data goes here>
};
};
};
The DT data is intended to portray addressable devices from the
perspective of the CPUs that are booted with that data, organized by bus
structure. From this point of view, clocks that are controlled via a
particular IP block should have their data associated with that block.
3. Place clock register accesses in the low-level PRCM/CM/PRM device
driver. If other kernel code needs some resource that's provided by the
IP block, it should either come from common Linux framework routines (like
the clock code), or use functions exported from the low-level driver that
don't expose register addresses.
Otherwise, if MMIO accesses to that device are allowed from all over the
codebase, it creates an undebuggable mess:
A. It could result in IP blocks being partially programmed before they are
probed by their drivers. If their drivers (or the integration code) reset
the IP blocks, the non-driver code has no way of knowing that it needs to
reprogram the underlying IP block.
B. If any preparation is needed before the clock registers can be
accessed, like runtime PM calls or device_enable()-type calls, this should
be coordinated by the low-level IP block itself. We don't expect this to
be the case for PRCM/CM/PRM, but we do expect it to be the case for UART,
DSS, some audio clocks, etc.
C. The low-level IP block drivers may want to implement some caching layer
like regmap. If some register writes bypass the low-level driver, then
someone is likely to get a big unpleasant surprise.
D. It impairs the common debugging technique of adding code to the IP
block MMIO read/write functions to log register accesses.
4. Use relative register offsets from the top of the containing IP block's
base address, rather than absolute addresses.
cm1@4a004000 {
...
clocks {
dpll_per_ck@4140 {
<clock data goes here>
};
};
};
This makes it possible to reuse the same DT clock data in cases where the
same IP block is used, but at a different base address. This is probably
not a big issue with the system integration IP blocks, but quite possible
with the non-SoC-integration IP blocks. It also makes it obvious if
someone tries to sneak clocks into the IP block data that aren't
controlled by that IP block.
5. Register the clocks from the low-level IP block drivers, rather than
from external code. That way there's no need to export low-level register
manipulation functions off to other kernel code. This registration can be
done when the PRCM/CM/PRM driver probes.
6. Move the OMAP clockdomain data underneath the DT node for the low-level
IP block that contains them:
cm1@4a004000 {
...
clocks {
...
};
clockdomains {
l3_init_clkdm: l3_init_clkdm@... {
...
};
};
};
For non-OMAP folks reading this thread, OMAP clockdomains have control
registers associated with them, located in the PRCM/CM/PRM IP block
address space, so that's where they belong.
7. drivers/clk/ti is probably the wrong place for most of the low-level
drivers for IP blocks like the PRM/PRCM/CM. Most of these IP blocks do
more than just control clocks: they also control other system entities
like reset lines, OMAP powerdomains, AVS, or OMAP "clockdomains" (which in
some cases may have nothing to do with clocks).
drivers/clk/ti is almost defensible for CM, if it weren't for the OMAP
"clockdomain" registers that are there. However, for the other OMAP
integration IP blocks, drivers/clk/ti definitely seems out of place. And
since some OMAP chips like OMAP2420 or AM43XX don't have separate CM and
PRM blocks -- they combine them both into a single PRCM module -- it seems
best to place CM, PRM, and other related code into a single common
directory, so they can easily share code across chips.
I'd suggest putting them in drivers/sysctrl/omap/. This would be intended
for low-level SoC IP block drivers that control system integration.
Otherwise drivers/clk/XXX is going to turn into another drivers/mfd.
8. A few random comments about the individual clock binding data formats
themselves, based on a quick look:
A. It seems pretty odd and unnecessarily obscure to do something like
this:
dpll_usb_ck: dpll_usb_ck@... {
...
reg = <0x4a008180 0x4>, <0x4a008184 0x4>, <0x4a008188 0x4>, <0x4a00818c 0x4>;
...
};
It's at least self-documenting to do something like this:
dpll_usb_ck: dpll_usb_ck@... {
...
control-reg = < ... >;
idlest-reg = < ... >;
.. etc. ..
};
Which itself might not even be needed, depending on how the DPLL control
code is implemented. For example, if the relative offsets are always the
same for all OMAP4-family devices, maybe there's not even a need to
explicitly encode that into the DT data.
B. Seems like you can remove the "ti," prefix on the properties, since
they have no pretentions at genericity: they are specific to the
PRCM/CM/PRM IP block data, and registered by those drivers.
C. Looks like the patches use the property "autoidle-low" to indicate that
the autoidle bit should be inverted. "Low" seems like the wrong
expression here - it invokes the actual voltage logic level of a hardware
signal, and we have no idea whether the hardware signal is using a low
voltage or a high voltage to express this condition. Would suggest
something like 'invert-autoidle-bit' instead.
D. Regarding "ti,index-starts-at-one", it seems best to explicitly state
which index starts at one. The code mentions a "mux index" so please
consider renaming this something like "mux-index-starts-at-one" or
"one-based-mux-index"
- Paul
^ permalink raw reply [flat|nested] 136+ messages in thread
* [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
@ 2013-10-13 23:45 ` Paul Walmsley
0 siblings, 0 replies; 136+ messages in thread
From: Paul Walmsley @ 2013-10-13 23:45 UTC (permalink / raw)
To: linux-arm-kernel
Here you go:
1. Create DT nodes for the IP blocks that contain the clock control
registers, underneath the appropriate bus node. So for example OMAP4
would have:
/ocp {
prm at 4a306000 {
compatible = xxx;
regs = <0x4a306000 xxxx>;
};
cm1 at 4a004000 {
compatible = xxx;
regs = <0x4a004000 xxxx>;
};
cm2 at 4a008000 {
compatible = xxx;
regs = <0x4a008000 xxxx>;
};
};
This is pure OS-independent hardware description (with the unfortunate
exception of the "ocp" part).
2. Create the clock data underneath the corresponding PRCM/CM/PRM device
nodes that their control registers exist in. So for example, dpll_per_ck
would belong to the "cm1" device, since that's where its control registers
are located. Something like this:
cm1 at 4a004000 {
...
clocks {
dpll_per_ck at .... {
<clock data goes here>
};
};
};
The DT data is intended to portray addressable devices from the
perspective of the CPUs that are booted with that data, organized by bus
structure. From this point of view, clocks that are controlled via a
particular IP block should have their data associated with that block.
3. Place clock register accesses in the low-level PRCM/CM/PRM device
driver. If other kernel code needs some resource that's provided by the
IP block, it should either come from common Linux framework routines (like
the clock code), or use functions exported from the low-level driver that
don't expose register addresses.
Otherwise, if MMIO accesses to that device are allowed from all over the
codebase, it creates an undebuggable mess:
A. It could result in IP blocks being partially programmed before they are
probed by their drivers. If their drivers (or the integration code) reset
the IP blocks, the non-driver code has no way of knowing that it needs to
reprogram the underlying IP block.
B. If any preparation is needed before the clock registers can be
accessed, like runtime PM calls or device_enable()-type calls, this should
be coordinated by the low-level IP block itself. We don't expect this to
be the case for PRCM/CM/PRM, but we do expect it to be the case for UART,
DSS, some audio clocks, etc.
C. The low-level IP block drivers may want to implement some caching layer
like regmap. If some register writes bypass the low-level driver, then
someone is likely to get a big unpleasant surprise.
D. It impairs the common debugging technique of adding code to the IP
block MMIO read/write functions to log register accesses.
4. Use relative register offsets from the top of the containing IP block's
base address, rather than absolute addresses.
cm1 at 4a004000 {
...
clocks {
dpll_per_ck at 4140 {
<clock data goes here>
};
};
};
This makes it possible to reuse the same DT clock data in cases where the
same IP block is used, but at a different base address. This is probably
not a big issue with the system integration IP blocks, but quite possible
with the non-SoC-integration IP blocks. It also makes it obvious if
someone tries to sneak clocks into the IP block data that aren't
controlled by that IP block.
5. Register the clocks from the low-level IP block drivers, rather than
from external code. That way there's no need to export low-level register
manipulation functions off to other kernel code. This registration can be
done when the PRCM/CM/PRM driver probes.
6. Move the OMAP clockdomain data underneath the DT node for the low-level
IP block that contains them:
cm1 at 4a004000 {
...
clocks {
...
};
clockdomains {
l3_init_clkdm: l3_init_clkdm at ... {
...
};
};
};
For non-OMAP folks reading this thread, OMAP clockdomains have control
registers associated with them, located in the PRCM/CM/PRM IP block
address space, so that's where they belong.
7. drivers/clk/ti is probably the wrong place for most of the low-level
drivers for IP blocks like the PRM/PRCM/CM. Most of these IP blocks do
more than just control clocks: they also control other system entities
like reset lines, OMAP powerdomains, AVS, or OMAP "clockdomains" (which in
some cases may have nothing to do with clocks).
drivers/clk/ti is almost defensible for CM, if it weren't for the OMAP
"clockdomain" registers that are there. However, for the other OMAP
integration IP blocks, drivers/clk/ti definitely seems out of place. And
since some OMAP chips like OMAP2420 or AM43XX don't have separate CM and
PRM blocks -- they combine them both into a single PRCM module -- it seems
best to place CM, PRM, and other related code into a single common
directory, so they can easily share code across chips.
I'd suggest putting them in drivers/sysctrl/omap/. This would be intended
for low-level SoC IP block drivers that control system integration.
Otherwise drivers/clk/XXX is going to turn into another drivers/mfd.
8. A few random comments about the individual clock binding data formats
themselves, based on a quick look:
A. It seems pretty odd and unnecessarily obscure to do something like
this:
dpll_usb_ck: dpll_usb_ck at ... {
...
reg = <0x4a008180 0x4>, <0x4a008184 0x4>, <0x4a008188 0x4>, <0x4a00818c 0x4>;
...
};
It's at least self-documenting to do something like this:
dpll_usb_ck: dpll_usb_ck at ... {
...
control-reg = < ... >;
idlest-reg = < ... >;
.. etc. ..
};
Which itself might not even be needed, depending on how the DPLL control
code is implemented. For example, if the relative offsets are always the
same for all OMAP4-family devices, maybe there's not even a need to
explicitly encode that into the DT data.
B. Seems like you can remove the "ti," prefix on the properties, since
they have no pretentions at genericity: they are specific to the
PRCM/CM/PRM IP block data, and registered by those drivers.
C. Looks like the patches use the property "autoidle-low" to indicate that
the autoidle bit should be inverted. "Low" seems like the wrong
expression here - it invokes the actual voltage logic level of a hardware
signal, and we have no idea whether the hardware signal is using a low
voltage or a high voltage to express this condition. Would suggest
something like 'invert-autoidle-bit' instead.
D. Regarding "ti,index-starts-at-one", it seems best to explicitly state
which index starts at one. The code mentions a "mux index" so please
consider renaming this something like "mux-index-starts-at-one" or
"one-based-mux-index"
- Paul
^ permalink raw reply [flat|nested] 136+ messages in thread
* Re: [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
2013-10-13 23:45 ` Paul Walmsley
@ 2013-10-14 14:57 ` Tero Kristo
-1 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-10-14 14:57 UTC (permalink / raw)
To: Paul Walmsley
Cc: devicetree, Tony Lindgren, mturquette, linux-omap, nm, khilman,
pdeschrijver, rnayak, bcousson, linux-arm-kernel, swarren,
mark.rutland
Hi Paul,
I've been looking at this stuff today, and this will cause pretty huge
changes to the set. This probably means a few weeks delay in
implementation at least.
Some comments on the technical perspectives below.
On 10/14/2013 02:45 AM, Paul Walmsley wrote:
>
> Here you go:
>
> 1. Create DT nodes for the IP blocks that contain the clock control
> registers, underneath the appropriate bus node. So for example OMAP4
> would have:
>
> /ocp {
>
> prm@4a306000 {
> compatible = xxx;
> regs = <0x4a306000 xxxx>;
> };
>
> cm1@4a004000 {
> compatible = xxx;
> regs = <0x4a004000 xxxx>;
> };
>
> cm2@4a008000 {
> compatible = xxx;
> regs = <0x4a008000 xxxx>;
> };
>
> };
>
> This is pure OS-independent hardware description (with the unfortunate
> exception of the "ocp" part).
>
>
> 2. Create the clock data underneath the corresponding PRCM/CM/PRM device
> nodes that their control registers exist in. So for example, dpll_per_ck
> would belong to the "cm1" device, since that's where its control registers
> are located. Something like this:
>
> cm1@4a004000 {
> ...
> clocks {
> dpll_per_ck@.... {
> <clock data goes here>
> };
> };
> };
>
>
> The DT data is intended to portray addressable devices from the
> perspective of the CPUs that are booted with that data, organized by bus
> structure. From this point of view, clocks that are controlled via a
> particular IP block should have their data associated with that block.
>
>
> 3. Place clock register accesses in the low-level PRCM/CM/PRM device
> driver. If other kernel code needs some resource that's provided by the
> IP block, it should either come from common Linux framework routines (like
> the clock code), or use functions exported from the low-level driver that
> don't expose register addresses.
>
> Otherwise, if MMIO accesses to that device are allowed from all over the
> codebase, it creates an undebuggable mess:
>
> A. It could result in IP blocks being partially programmed before they are
> probed by their drivers. If their drivers (or the integration code) reset
> the IP blocks, the non-driver code has no way of knowing that it needs to
> reprogram the underlying IP block.
>
> B. If any preparation is needed before the clock registers can be
> accessed, like runtime PM calls or device_enable()-type calls, this should
> be coordinated by the low-level IP block itself. We don't expect this to
> be the case for PRCM/CM/PRM, but we do expect it to be the case for UART,
> DSS, some audio clocks, etc.
>
> C. The low-level IP block drivers may want to implement some caching layer
> like regmap. If some register writes bypass the low-level driver, then
> someone is likely to get a big unpleasant surprise.
>
> D. It impairs the common debugging technique of adding code to the IP
> block MMIO read/write functions to log register accesses.
>
>
>
> 4. Use relative register offsets from the top of the containing IP block's
> base address, rather than absolute addresses.
>
> cm1@4a004000 {
> ...
> clocks {
> dpll_per_ck@4140 {
> <clock data goes here>
> };
> };
> };
>
> This makes it possible to reuse the same DT clock data in cases where the
> same IP block is used, but at a different base address. This is probably
> not a big issue with the system integration IP blocks, but quite possible
> with the non-SoC-integration IP blocks. It also makes it obvious if
> someone tries to sneak clocks into the IP block data that aren't
> controlled by that IP block.
Relative addressing basically means I need to copy paste the code for
clk_divider + clk_mux from drivers/clk to drivers/clk/ti. Or
alternatively add a way to provide register read/write ops to the basic
clock.
> 5. Register the clocks from the low-level IP block drivers, rather than
> from external code. That way there's no need to export low-level register
> manipulation functions off to other kernel code. This registration can be
> done when the PRCM/CM/PRM driver probes.
>
>
> 6. Move the OMAP clockdomain data underneath the DT node for the low-level
> IP block that contains them:
>
>
> cm1@4a004000 {
> ...
> clocks {
> ...
> };
>
> clockdomains {
> l3_init_clkdm: l3_init_clkdm@... {
> ...
> };
> };
> };
I think clocks + clockdomains grouping nodes are unnecessary in this
case. Same can be accomplished with simply using the compatible string
for mapping to corresponding types. (This is probably valid for current
code also.)
> For non-OMAP folks reading this thread, OMAP clockdomains have control
> registers associated with them, located in the PRCM/CM/PRM IP block
> address space, so that's where they belong.
>
>
> 7. drivers/clk/ti is probably the wrong place for most of the low-level
> drivers for IP blocks like the PRM/PRCM/CM. Most of these IP blocks do
> more than just control clocks: they also control other system entities
> like reset lines, OMAP powerdomains, AVS, or OMAP "clockdomains" (which in
> some cases may have nothing to do with clocks).
>
> drivers/clk/ti is almost defensible for CM, if it weren't for the OMAP
> "clockdomain" registers that are there. However, for the other OMAP
> integration IP blocks, drivers/clk/ti definitely seems out of place. And
> since some OMAP chips like OMAP2420 or AM43XX don't have separate CM and
> PRM blocks -- they combine them both into a single PRCM module -- it seems
> best to place CM, PRM, and other related code into a single common
> directory, so they can easily share code across chips.
>
> I'd suggest putting them in drivers/sysctrl/omap/. This would be intended
> for low-level SoC IP block drivers that control system integration.
> Otherwise drivers/clk/XXX is going to turn into another drivers/mfd.
I think initially I would place this stuff under mach-omap2. Much better
than to try to introduce multiple new drivers with a single set.
> 8. A few random comments about the individual clock binding data formats
> themselves, based on a quick look:
>
> A. It seems pretty odd and unnecessarily obscure to do something like
> this:
>
> dpll_usb_ck: dpll_usb_ck@... {
> ...
> reg = <0x4a008180 0x4>, <0x4a008184 0x4>, <0x4a008188 0x4>, <0x4a00818c 0x4>;
> ...
> };
>
> It's at least self-documenting to do something like this:
>
> dpll_usb_ck: dpll_usb_ck@... {
> ...
> control-reg = < ... >;
> idlest-reg = < ... >;
> .. etc. ..
> };
Some earlier version had something along these lines, but it was turned
down. I had also reg-names as documentation purposes along, but this was
unnecessary and was dropped also.
> Which itself might not even be needed, depending on how the DPLL control
> code is implemented. For example, if the relative offsets are always the
> same for all OMAP4-family devices, maybe there's not even a need to
> explicitly encode that into the DT data.
If I want to get rid of these, I need to add extra compatible strings
for the dpll types. There are several weird register offsets for
omap3/am3 devices. omap4/5/dra7/am4 behave more sanely.
> B. Seems like you can remove the "ti," prefix on the properties, since
> they have no pretentions at genericity: they are specific to the
> PRCM/CM/PRM IP block data, and registered by those drivers.
Can or should? It seems existing bindings use "ti," prefix even on
non-generic bindings, meaning if I look at any other data in DT.
> C. Looks like the patches use the property "autoidle-low" to indicate that
> the autoidle bit should be inverted. "Low" seems like the wrong
> expression here - it invokes the actual voltage logic level of a hardware
> signal, and we have no idea whether the hardware signal is using a low
> voltage or a high voltage to express this condition. Would suggest
> something like 'invert-autoidle-bit' instead.
>
> D. Regarding "ti,index-starts-at-one", it seems best to explicitly state
> which index starts at one. The code mentions a "mux index" so please
> consider renaming this something like "mux-index-starts-at-one" or
> "one-based-mux-index"
The index is explicitly defined by the clock node where this is present.
If it is a mux-clock, then it is for mux-index. If for divider clock, it
is index for the divider.
-Tero
^ permalink raw reply [flat|nested] 136+ messages in thread
* [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
@ 2013-10-14 14:57 ` Tero Kristo
0 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-10-14 14:57 UTC (permalink / raw)
To: linux-arm-kernel
Hi Paul,
I've been looking at this stuff today, and this will cause pretty huge
changes to the set. This probably means a few weeks delay in
implementation at least.
Some comments on the technical perspectives below.
On 10/14/2013 02:45 AM, Paul Walmsley wrote:
>
> Here you go:
>
> 1. Create DT nodes for the IP blocks that contain the clock control
> registers, underneath the appropriate bus node. So for example OMAP4
> would have:
>
> /ocp {
>
> prm at 4a306000 {
> compatible = xxx;
> regs = <0x4a306000 xxxx>;
> };
>
> cm1 at 4a004000 {
> compatible = xxx;
> regs = <0x4a004000 xxxx>;
> };
>
> cm2 at 4a008000 {
> compatible = xxx;
> regs = <0x4a008000 xxxx>;
> };
>
> };
>
> This is pure OS-independent hardware description (with the unfortunate
> exception of the "ocp" part).
>
>
> 2. Create the clock data underneath the corresponding PRCM/CM/PRM device
> nodes that their control registers exist in. So for example, dpll_per_ck
> would belong to the "cm1" device, since that's where its control registers
> are located. Something like this:
>
> cm1 at 4a004000 {
> ...
> clocks {
> dpll_per_ck at .... {
> <clock data goes here>
> };
> };
> };
>
>
> The DT data is intended to portray addressable devices from the
> perspective of the CPUs that are booted with that data, organized by bus
> structure. From this point of view, clocks that are controlled via a
> particular IP block should have their data associated with that block.
>
>
> 3. Place clock register accesses in the low-level PRCM/CM/PRM device
> driver. If other kernel code needs some resource that's provided by the
> IP block, it should either come from common Linux framework routines (like
> the clock code), or use functions exported from the low-level driver that
> don't expose register addresses.
>
> Otherwise, if MMIO accesses to that device are allowed from all over the
> codebase, it creates an undebuggable mess:
>
> A. It could result in IP blocks being partially programmed before they are
> probed by their drivers. If their drivers (or the integration code) reset
> the IP blocks, the non-driver code has no way of knowing that it needs to
> reprogram the underlying IP block.
>
> B. If any preparation is needed before the clock registers can be
> accessed, like runtime PM calls or device_enable()-type calls, this should
> be coordinated by the low-level IP block itself. We don't expect this to
> be the case for PRCM/CM/PRM, but we do expect it to be the case for UART,
> DSS, some audio clocks, etc.
>
> C. The low-level IP block drivers may want to implement some caching layer
> like regmap. If some register writes bypass the low-level driver, then
> someone is likely to get a big unpleasant surprise.
>
> D. It impairs the common debugging technique of adding code to the IP
> block MMIO read/write functions to log register accesses.
>
>
>
> 4. Use relative register offsets from the top of the containing IP block's
> base address, rather than absolute addresses.
>
> cm1 at 4a004000 {
> ...
> clocks {
> dpll_per_ck at 4140 {
> <clock data goes here>
> };
> };
> };
>
> This makes it possible to reuse the same DT clock data in cases where the
> same IP block is used, but at a different base address. This is probably
> not a big issue with the system integration IP blocks, but quite possible
> with the non-SoC-integration IP blocks. It also makes it obvious if
> someone tries to sneak clocks into the IP block data that aren't
> controlled by that IP block.
Relative addressing basically means I need to copy paste the code for
clk_divider + clk_mux from drivers/clk to drivers/clk/ti. Or
alternatively add a way to provide register read/write ops to the basic
clock.
> 5. Register the clocks from the low-level IP block drivers, rather than
> from external code. That way there's no need to export low-level register
> manipulation functions off to other kernel code. This registration can be
> done when the PRCM/CM/PRM driver probes.
>
>
> 6. Move the OMAP clockdomain data underneath the DT node for the low-level
> IP block that contains them:
>
>
> cm1 at 4a004000 {
> ...
> clocks {
> ...
> };
>
> clockdomains {
> l3_init_clkdm: l3_init_clkdm at ... {
> ...
> };
> };
> };
I think clocks + clockdomains grouping nodes are unnecessary in this
case. Same can be accomplished with simply using the compatible string
for mapping to corresponding types. (This is probably valid for current
code also.)
> For non-OMAP folks reading this thread, OMAP clockdomains have control
> registers associated with them, located in the PRCM/CM/PRM IP block
> address space, so that's where they belong.
>
>
> 7. drivers/clk/ti is probably the wrong place for most of the low-level
> drivers for IP blocks like the PRM/PRCM/CM. Most of these IP blocks do
> more than just control clocks: they also control other system entities
> like reset lines, OMAP powerdomains, AVS, or OMAP "clockdomains" (which in
> some cases may have nothing to do with clocks).
>
> drivers/clk/ti is almost defensible for CM, if it weren't for the OMAP
> "clockdomain" registers that are there. However, for the other OMAP
> integration IP blocks, drivers/clk/ti definitely seems out of place. And
> since some OMAP chips like OMAP2420 or AM43XX don't have separate CM and
> PRM blocks -- they combine them both into a single PRCM module -- it seems
> best to place CM, PRM, and other related code into a single common
> directory, so they can easily share code across chips.
>
> I'd suggest putting them in drivers/sysctrl/omap/. This would be intended
> for low-level SoC IP block drivers that control system integration.
> Otherwise drivers/clk/XXX is going to turn into another drivers/mfd.
I think initially I would place this stuff under mach-omap2. Much better
than to try to introduce multiple new drivers with a single set.
> 8. A few random comments about the individual clock binding data formats
> themselves, based on a quick look:
>
> A. It seems pretty odd and unnecessarily obscure to do something like
> this:
>
> dpll_usb_ck: dpll_usb_ck at ... {
> ...
> reg = <0x4a008180 0x4>, <0x4a008184 0x4>, <0x4a008188 0x4>, <0x4a00818c 0x4>;
> ...
> };
>
> It's at least self-documenting to do something like this:
>
> dpll_usb_ck: dpll_usb_ck at ... {
> ...
> control-reg = < ... >;
> idlest-reg = < ... >;
> .. etc. ..
> };
Some earlier version had something along these lines, but it was turned
down. I had also reg-names as documentation purposes along, but this was
unnecessary and was dropped also.
> Which itself might not even be needed, depending on how the DPLL control
> code is implemented. For example, if the relative offsets are always the
> same for all OMAP4-family devices, maybe there's not even a need to
> explicitly encode that into the DT data.
If I want to get rid of these, I need to add extra compatible strings
for the dpll types. There are several weird register offsets for
omap3/am3 devices. omap4/5/dra7/am4 behave more sanely.
> B. Seems like you can remove the "ti," prefix on the properties, since
> they have no pretentions at genericity: they are specific to the
> PRCM/CM/PRM IP block data, and registered by those drivers.
Can or should? It seems existing bindings use "ti," prefix even on
non-generic bindings, meaning if I look at any other data in DT.
> C. Looks like the patches use the property "autoidle-low" to indicate that
> the autoidle bit should be inverted. "Low" seems like the wrong
> expression here - it invokes the actual voltage logic level of a hardware
> signal, and we have no idea whether the hardware signal is using a low
> voltage or a high voltage to express this condition. Would suggest
> something like 'invert-autoidle-bit' instead.
>
> D. Regarding "ti,index-starts-at-one", it seems best to explicitly state
> which index starts at one. The code mentions a "mux index" so please
> consider renaming this something like "mux-index-starts-at-one" or
> "one-based-mux-index"
The index is explicitly defined by the clock node where this is present.
If it is a mux-clock, then it is for mux-index. If for divider clock, it
is index for the divider.
-Tero
^ permalink raw reply [flat|nested] 136+ messages in thread
* Re: [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
2013-10-14 14:57 ` Tero Kristo
@ 2013-10-14 18:27 ` Paul Walmsley
-1 siblings, 0 replies; 136+ messages in thread
From: Paul Walmsley @ 2013-10-14 18:27 UTC (permalink / raw)
To: Tero Kristo
Cc: devicetree, Tony Lindgren, mturquette, linux-omap, nm, khilman,
pdeschrijver, rnayak, bcousson, linux-arm-kernel, swarren,
mark.rutland
On Mon, 14 Oct 2013, Tero Kristo wrote:
> On 10/14/2013 02:45 AM, Paul Walmsley wrote:
>
> > 8. A few random comments about the individual clock binding data formats
> > themselves, based on a quick look:
> >
> > A. It seems pretty odd and unnecessarily obscure to do something like
> > this:
> >
> > dpll_usb_ck: dpll_usb_ck@... {
> > ...
> > reg = <0x4a008180 0x4>, <0x4a008184 0x4>, <0x4a008188 0x4>,
> > <0x4a00818c 0x4>;
> > ...
> > };
> >
> > It's at least self-documenting to do something like this:
> >
> > dpll_usb_ck: dpll_usb_ck@... {
> > ...
> > control-reg = < ... >;
> > idlest-reg = < ... >;
> > .. etc. ..
> > };
>
> Some earlier version had something along these lines, but it was turned down.
> I had also reg-names as documentation purposes along, but this was unnecessary
> and was dropped also.
>
> > Which itself might not even be needed, depending on how the DPLL control
> > code is implemented. For example, if the relative offsets are always the
> > same for all OMAP4-family devices, maybe there's not even a need to
> > explicitly encode that into the DT data.
>
> If I want to get rid of these, I need to add extra compatible strings for the
> dpll types. There are several weird register offsets for omap3/am3 devices.
> omap4/5/dra7/am4 behave more sanely.
>
> > B. Seems like you can remove the "ti," prefix on the properties, since
> > they have no pretentions at genericity: they are specific to the
> > PRCM/CM/PRM IP block data, and registered by those drivers.
>
> Can or should? It seems existing bindings use "ti," prefix even on non-generic
> bindings, meaning if I look at any other data in DT.
My comments in #8 are just regarding minor issues that don't seem
right. I don't have a significant objection to staying with the
existing property names here if you think that they are important.
> > C. Looks like the patches use the property "autoidle-low" to indicate that
> > the autoidle bit should be inverted. "Low" seems like the wrong
> > expression here - it invokes the actual voltage logic level of a hardware
> > signal, and we have no idea whether the hardware signal is using a low
> > voltage or a high voltage to express this condition. Would suggest
> > something like 'invert-autoidle-bit' instead.
> >
> > D. Regarding "ti,index-starts-at-one", it seems best to explicitly state
> > which index starts at one. The code mentions a "mux index" so please
> > consider renaming this something like "mux-index-starts-at-one" or
> > "one-based-mux-index"
>
> The index is explicitly defined by the clock node where this is present. If it
> is a mux-clock, then it is for mux-index. If for divider clock, it is index
> for the divider.
- Paul
^ permalink raw reply [flat|nested] 136+ messages in thread
* [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
@ 2013-10-14 18:27 ` Paul Walmsley
0 siblings, 0 replies; 136+ messages in thread
From: Paul Walmsley @ 2013-10-14 18:27 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, 14 Oct 2013, Tero Kristo wrote:
> On 10/14/2013 02:45 AM, Paul Walmsley wrote:
>
> > 8. A few random comments about the individual clock binding data formats
> > themselves, based on a quick look:
> >
> > A. It seems pretty odd and unnecessarily obscure to do something like
> > this:
> >
> > dpll_usb_ck: dpll_usb_ck at ... {
> > ...
> > reg = <0x4a008180 0x4>, <0x4a008184 0x4>, <0x4a008188 0x4>,
> > <0x4a00818c 0x4>;
> > ...
> > };
> >
> > It's at least self-documenting to do something like this:
> >
> > dpll_usb_ck: dpll_usb_ck at ... {
> > ...
> > control-reg = < ... >;
> > idlest-reg = < ... >;
> > .. etc. ..
> > };
>
> Some earlier version had something along these lines, but it was turned down.
> I had also reg-names as documentation purposes along, but this was unnecessary
> and was dropped also.
>
> > Which itself might not even be needed, depending on how the DPLL control
> > code is implemented. For example, if the relative offsets are always the
> > same for all OMAP4-family devices, maybe there's not even a need to
> > explicitly encode that into the DT data.
>
> If I want to get rid of these, I need to add extra compatible strings for the
> dpll types. There are several weird register offsets for omap3/am3 devices.
> omap4/5/dra7/am4 behave more sanely.
>
> > B. Seems like you can remove the "ti," prefix on the properties, since
> > they have no pretentions at genericity: they are specific to the
> > PRCM/CM/PRM IP block data, and registered by those drivers.
>
> Can or should? It seems existing bindings use "ti," prefix even on non-generic
> bindings, meaning if I look at any other data in DT.
My comments in #8 are just regarding minor issues that don't seem
right. I don't have a significant objection to staying with the
existing property names here if you think that they are important.
> > C. Looks like the patches use the property "autoidle-low" to indicate that
> > the autoidle bit should be inverted. "Low" seems like the wrong
> > expression here - it invokes the actual voltage logic level of a hardware
> > signal, and we have no idea whether the hardware signal is using a low
> > voltage or a high voltage to express this condition. Would suggest
> > something like 'invert-autoidle-bit' instead.
> >
> > D. Regarding "ti,index-starts-at-one", it seems best to explicitly state
> > which index starts at one. The code mentions a "mux index" so please
> > consider renaming this something like "mux-index-starts-at-one" or
> > "one-based-mux-index"
>
> The index is explicitly defined by the clock node where this is present. If it
> is a mux-clock, then it is for mux-index. If for divider clock, it is index
> for the divider.
- Paul
^ permalink raw reply [flat|nested] 136+ messages in thread
* Re: [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
2013-10-14 18:27 ` Paul Walmsley
@ 2013-10-14 18:34 ` Tero Kristo
-1 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-10-14 18:34 UTC (permalink / raw)
To: Paul Walmsley
Cc: nm, devicetree, khilman, mturquette, Tony Lindgren, pdeschrijver,
rnayak, bcousson, swarren, mark.rutland, linux-omap,
linux-arm-kernel
On 10/14/2013 09:27 PM, Paul Walmsley wrote:
> On Mon, 14 Oct 2013, Tero Kristo wrote:
>
>> On 10/14/2013 02:45 AM, Paul Walmsley wrote:
>>
>>> 8. A few random comments about the individual clock binding data formats
>>> themselves, based on a quick look:
>>>
>>> A. It seems pretty odd and unnecessarily obscure to do something like
>>> this:
>>>
>>> dpll_usb_ck: dpll_usb_ck@... {
>>> ...
>>> reg = <0x4a008180 0x4>, <0x4a008184 0x4>, <0x4a008188 0x4>,
>>> <0x4a00818c 0x4>;
>>> ...
>>> };
>>>
>>> It's at least self-documenting to do something like this:
>>>
>>> dpll_usb_ck: dpll_usb_ck@... {
>>> ...
>>> control-reg = < ... >;
>>> idlest-reg = < ... >;
>>> .. etc. ..
>>> };
>>
>> Some earlier version had something along these lines, but it was turned down.
>> I had also reg-names as documentation purposes along, but this was unnecessary
>> and was dropped also.
>>
>>> Which itself might not even be needed, depending on how the DPLL control
>>> code is implemented. For example, if the relative offsets are always the
>>> same for all OMAP4-family devices, maybe there's not even a need to
>>> explicitly encode that into the DT data.
>>
>> If I want to get rid of these, I need to add extra compatible strings for the
>> dpll types. There are several weird register offsets for omap3/am3 devices.
>> omap4/5/dra7/am4 behave more sanely.
>>
>>> B. Seems like you can remove the "ti," prefix on the properties, since
>>> they have no pretentions at genericity: they are specific to the
>>> PRCM/CM/PRM IP block data, and registered by those drivers.
>>
>> Can or should? It seems existing bindings use "ti," prefix even on non-generic
>> bindings, meaning if I look at any other data in DT.
>
> My comments in #8 are just regarding minor issues that don't seem
> right. I don't have a significant objection to staying with the
> existing property names here if you think that they are important.
Ok thanks, I'll be reworking most of the other items and will hopefully
have something ready soonish. Taking care of the register mappings is
rather nasty thing to do.
-Tero
>>> C. Looks like the patches use the property "autoidle-low" to indicate that
>>> the autoidle bit should be inverted. "Low" seems like the wrong
>>> expression here - it invokes the actual voltage logic level of a hardware
>>> signal, and we have no idea whether the hardware signal is using a low
>>> voltage or a high voltage to express this condition. Would suggest
>>> something like 'invert-autoidle-bit' instead.
>>>
>>> D. Regarding "ti,index-starts-at-one", it seems best to explicitly state
>>> which index starts at one. The code mentions a "mux index" so please
>>> consider renaming this something like "mux-index-starts-at-one" or
>>> "one-based-mux-index"
>>
>> The index is explicitly defined by the clock node where this is present. If it
>> is a mux-clock, then it is for mux-index. If for divider clock, it is index
>> for the divider.
>
>
>
> - Paul
>
^ permalink raw reply [flat|nested] 136+ messages in thread
* [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
@ 2013-10-14 18:34 ` Tero Kristo
0 siblings, 0 replies; 136+ messages in thread
From: Tero Kristo @ 2013-10-14 18:34 UTC (permalink / raw)
To: linux-arm-kernel
On 10/14/2013 09:27 PM, Paul Walmsley wrote:
> On Mon, 14 Oct 2013, Tero Kristo wrote:
>
>> On 10/14/2013 02:45 AM, Paul Walmsley wrote:
>>
>>> 8. A few random comments about the individual clock binding data formats
>>> themselves, based on a quick look:
>>>
>>> A. It seems pretty odd and unnecessarily obscure to do something like
>>> this:
>>>
>>> dpll_usb_ck: dpll_usb_ck at ... {
>>> ...
>>> reg = <0x4a008180 0x4>, <0x4a008184 0x4>, <0x4a008188 0x4>,
>>> <0x4a00818c 0x4>;
>>> ...
>>> };
>>>
>>> It's at least self-documenting to do something like this:
>>>
>>> dpll_usb_ck: dpll_usb_ck at ... {
>>> ...
>>> control-reg = < ... >;
>>> idlest-reg = < ... >;
>>> .. etc. ..
>>> };
>>
>> Some earlier version had something along these lines, but it was turned down.
>> I had also reg-names as documentation purposes along, but this was unnecessary
>> and was dropped also.
>>
>>> Which itself might not even be needed, depending on how the DPLL control
>>> code is implemented. For example, if the relative offsets are always the
>>> same for all OMAP4-family devices, maybe there's not even a need to
>>> explicitly encode that into the DT data.
>>
>> If I want to get rid of these, I need to add extra compatible strings for the
>> dpll types. There are several weird register offsets for omap3/am3 devices.
>> omap4/5/dra7/am4 behave more sanely.
>>
>>> B. Seems like you can remove the "ti," prefix on the properties, since
>>> they have no pretentions at genericity: they are specific to the
>>> PRCM/CM/PRM IP block data, and registered by those drivers.
>>
>> Can or should? It seems existing bindings use "ti," prefix even on non-generic
>> bindings, meaning if I look at any other data in DT.
>
> My comments in #8 are just regarding minor issues that don't seem
> right. I don't have a significant objection to staying with the
> existing property names here if you think that they are important.
Ok thanks, I'll be reworking most of the other items and will hopefully
have something ready soonish. Taking care of the register mappings is
rather nasty thing to do.
-Tero
>>> C. Looks like the patches use the property "autoidle-low" to indicate that
>>> the autoidle bit should be inverted. "Low" seems like the wrong
>>> expression here - it invokes the actual voltage logic level of a hardware
>>> signal, and we have no idea whether the hardware signal is using a low
>>> voltage or a high voltage to express this condition. Would suggest
>>> something like 'invert-autoidle-bit' instead.
>>>
>>> D. Regarding "ti,index-starts-at-one", it seems best to explicitly state
>>> which index starts at one. The code mentions a "mux index" so please
>>> consider renaming this something like "mux-index-starts-at-one" or
>>> "one-based-mux-index"
>>
>> The index is explicitly defined by the clock node where this is present. If it
>> is a mux-clock, then it is for mux-index. If for divider clock, it is index
>> for the divider.
>
>
>
> - Paul
>
^ permalink raw reply [flat|nested] 136+ messages in thread
end of thread, other threads:[~2013-10-14 18:34 UTC | newest]
Thread overview: 136+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2013-09-25 8:48 [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT Tero Kristo
2013-09-25 8:48 ` Tero Kristo
2013-09-25 8:48 ` [PATCHv7 01/36] CLK: TI: Add DPLL clock support Tero Kristo
2013-09-25 8:48 ` Tero Kristo
2013-09-25 8:48 ` [PATCHv7 04/36] CLK: ti: add support for ti divider-clock Tero Kristo
2013-09-25 8:48 ` Tero Kristo
2013-09-25 8:48 ` [PATCHv7 07/36] CLK: TI: add support for clockdomain binding Tero Kristo
2013-09-25 8:48 ` Tero Kristo
2013-09-25 8:48 ` [PATCHv7 08/36] ARM: dts: omap4 clock data Tero Kristo
2013-09-25 8:48 ` Tero Kristo
2013-09-25 8:48 ` [PATCHv7 10/36] clk: ti: add support for basic mux clock Tero Kristo
2013-09-25 8:48 ` Tero Kristo
2013-09-25 8:48 ` [PATCHv7 11/36] CLK: TI: add omap4 clock init file Tero Kristo
2013-09-25 8:48 ` Tero Kristo
2013-09-25 8:48 ` [PATCHv7 12/36] ARM: OMAP4: remove old clock data and link in new clock init code Tero Kristo
2013-09-25 8:48 ` Tero Kristo
2013-09-25 8:48 ` [PATCHv7 13/36] ARM: dts: omap5 clock data Tero Kristo
2013-09-25 8:48 ` Tero Kristo
2013-09-25 8:48 ` [PATCHv7 15/36] CLK: TI: omap5: Initialize USB_DPLL at boot Tero Kristo
2013-09-25 8:48 ` Tero Kristo
2013-09-25 8:48 ` [PATCHv7 18/36] ARM: dts: DRA7: Change apll_pcie_m2_ck to fixed factor clock Tero Kristo
2013-09-25 8:48 ` Tero Kristo
2013-09-25 8:48 ` [PATCHv7 19/36] ARM: dts: DRA7: Add PCIe related clock nodes Tero Kristo
2013-09-25 8:48 ` Tero Kristo
[not found] ` <1380098922-30340-1-git-send-email-t-kristo-l0cyMroinI0@public.gmane.org>
2013-09-25 8:48 ` [PATCHv7 02/36] CLK: TI: add DT alias clock registration mechanism Tero Kristo
2013-09-25 8:48 ` Tero Kristo
2013-09-25 8:48 ` [PATCHv7 03/36] CLK: TI: add autoidle support Tero Kristo
2013-09-25 8:48 ` Tero Kristo
2013-09-25 8:48 ` [PATCHv7 05/36] clk: ti: add support for TI fixed factor clock Tero Kristo
2013-09-25 8:48 ` Tero Kristo
2013-09-25 8:48 ` [PATCHv7 06/36] CLK: TI: add support for OMAP gate clock Tero Kristo
2013-09-25 8:48 ` Tero Kristo
2013-09-25 8:48 ` [PATCHv7 09/36] clk: ti: add mux-gate clock support Tero Kristo
2013-09-25 8:48 ` Tero Kristo
2013-09-25 8:48 ` [PATCHv7 14/36] CLK: TI: add omap5 clock init file Tero Kristo
2013-09-25 8:48 ` Tero Kristo
2013-09-25 8:48 ` [PATCHv7 16/36] ARM: dts: dra7 clock data Tero Kristo
2013-09-25 8:48 ` Tero Kristo
2013-09-25 8:48 ` [PATCHv7 17/36] ARM: dts: clk: Add apll related clocks Tero Kristo
2013-09-25 8:48 ` Tero Kristo
2013-09-25 8:48 ` [PATCHv7 20/36] CLK: TI: DRA7: Add APLL support Tero Kristo
2013-09-25 8:48 ` Tero Kristo
2013-10-08 5:16 ` Mike Turquette
2013-10-08 5:16 ` Mike Turquette
2013-09-25 8:48 ` [PATCHv7 21/36] CLK: TI: add dra7 clock init file Tero Kristo
2013-09-25 8:48 ` Tero Kristo
2013-09-25 8:48 ` [PATCHv7 22/36] ARM: OMAP: DRA7: Enable clock init Tero Kristo
2013-09-25 8:48 ` Tero Kristo
2013-09-25 8:48 ` [PATCHv7 25/36] CLK: TI: add am33xx clock init file Tero Kristo
2013-09-25 8:48 ` Tero Kristo
2013-09-25 8:48 ` [PATCHv7 26/36] ARM: AM33xx: remove old clock data and link in new clock init code Tero Kristo
2013-09-25 8:48 ` Tero Kristo
2013-09-25 8:48 ` [PATCHv7 27/36] CLK: TI: add interface clock support for OMAP3 Tero Kristo
2013-09-25 8:48 ` Tero Kristo
2013-09-25 8:48 ` [PATCHv7 28/36] ARM: OMAP: hwmod: fix an incorrect clk type cast with _get_clkdm Tero Kristo
2013-09-25 8:48 ` Tero Kristo
2013-09-25 8:48 ` [PATCHv7 29/36] ARM: OMAP3: hwmod: initialize clkdm from clkdm_name Tero Kristo
2013-09-25 8:48 ` Tero Kristo
2013-09-25 8:48 ` [PATCHv7 30/36] ARM: dts: omap3 clock data Tero Kristo
2013-09-25 8:48 ` Tero Kristo
2013-09-26 16:06 ` Nishanth Menon
2013-09-26 16:06 ` Nishanth Menon
2013-09-26 16:23 ` Nishanth Menon
2013-09-26 16:23 ` Nishanth Menon
2013-09-25 8:48 ` [PATCHv7 31/36] CLK: TI: add omap3 clock init file Tero Kristo
2013-09-25 8:48 ` Tero Kristo
2013-09-25 8:48 ` [PATCHv7 34/36] ARM: dts: am43xx clock data Tero Kristo
2013-09-25 8:48 ` Tero Kristo
2013-09-25 8:48 ` [PATCHv7 36/36] CLK: TI: add am43xx clock init file Tero Kristo
2013-09-25 8:48 ` Tero Kristo
2013-09-26 15:21 ` [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT Nishanth Menon
2013-09-26 15:21 ` Nishanth Menon
2013-09-26 15:29 ` Nishanth Menon
2013-09-26 15:29 ` Nishanth Menon
2013-10-04 15:34 ` Tero Kristo
2013-10-04 15:34 ` Tero Kristo
2013-10-07 2:15 ` Tony Lindgren
2013-10-07 2:15 ` Tony Lindgren
2013-10-07 6:35 ` Tero Kristo
2013-10-07 6:35 ` Tero Kristo
2013-10-07 15:41 ` Tony Lindgren
2013-10-07 15:41 ` Tony Lindgren
2013-10-07 16:13 ` Nishanth Menon
2013-10-07 16:13 ` Nishanth Menon
2013-10-07 19:03 ` Tony Lindgren
2013-10-07 19:03 ` Tony Lindgren
[not found] ` <20131007190322.GY8949-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
2013-10-09 18:55 ` Paul Walmsley
2013-10-09 18:55 ` Paul Walmsley
2013-10-09 18:59 ` Paul Walmsley
2013-10-09 18:59 ` Paul Walmsley
2013-10-09 19:24 ` Tony Lindgren
2013-10-09 19:24 ` Tony Lindgren
2013-10-10 7:18 ` Tero Kristo
2013-10-10 7:18 ` Tero Kristo
2013-10-11 17:54 ` Paul Walmsley
2013-10-11 17:54 ` Paul Walmsley
2013-10-11 18:23 ` Tero Kristo
2013-10-11 18:23 ` Tero Kristo
2013-10-11 22:26 ` Paul Walmsley
2013-10-11 22:26 ` Paul Walmsley
2013-10-11 18:46 ` Tero Kristo
2013-10-11 18:46 ` Tero Kristo
2013-10-11 22:37 ` Paul Walmsley
2013-10-11 22:37 ` Paul Walmsley
2013-10-12 10:25 ` Tero Kristo
2013-10-12 10:25 ` Tero Kristo
2013-10-13 23:45 ` Paul Walmsley
2013-10-13 23:45 ` Paul Walmsley
2013-10-14 14:57 ` Tero Kristo
2013-10-14 14:57 ` Tero Kristo
2013-10-14 18:27 ` Paul Walmsley
2013-10-14 18:27 ` Paul Walmsley
2013-10-14 18:34 ` Tero Kristo
2013-10-14 18:34 ` Tero Kristo
2013-10-09 19:22 ` Tony Lindgren
2013-10-09 19:22 ` Tony Lindgren
2013-10-10 8:17 ` Tero Kristo
2013-10-10 8:17 ` Tero Kristo
2013-10-11 22:53 ` Tony Lindgren
2013-10-11 22:53 ` Tony Lindgren
2013-09-25 8:48 ` [PATCHv7 23/36] ARM: dts: DRA7: link in clock DT data Tero Kristo
2013-09-25 8:48 ` Tero Kristo
2013-09-25 8:48 ` [PATCHv7 24/36] ARM: dts: am33xx clock data Tero Kristo
2013-09-25 8:48 ` Tero Kristo
2013-09-25 8:48 ` [PATCHv7 32/36] ARM: dts: AM35xx: use DT " Tero Kristo
2013-09-25 8:48 ` Tero Kristo
2013-09-25 8:48 ` [PATCHv7 33/36] ARM: OMAP3: use DT clock init if DT data is available Tero Kristo
2013-09-25 8:48 ` Tero Kristo
2013-09-25 8:48 ` [PATCHv7 35/36] ARM: dts: AM43xx: link in clock DT data Tero Kristo
2013-09-25 8:48 ` Tero Kristo
2013-10-08 5:40 ` [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT Mike Turquette
2013-10-08 5:40 ` Mike Turquette
2013-10-08 8:17 ` Tero Kristo
2013-10-08 8:17 ` Tero Kristo
2013-10-08 16:47 ` Tony Lindgren
2013-10-08 16:47 ` Tony Lindgren
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