[PATCH v3 00/20] ARM: shmobile: r8a7779, marzen: CCF and multiplatform

[PATCH v3 00/20] ARM: shmobile: r8a7779, marzen: CCF and multiplatform

[Simon Horman]

The aim of this series is to add common clock framework and in turn
multiplatform support to the r8a7779 SoC and marzen-reference.  It
subsequently removes non-multiplatform support from marzen-reference.


This is based on work for R-Car Gen2 by Laurent Pinchart and Magnus Damm.


This series is based on the renesas-devel-v3.14-rc4-20140225
tag of my renesas tree.

This series is known not to work when
booting with SMP enabled and maxcpus not set to 0.


Simon Horman (20):
  clk: shmobile: r8a7779: Add clocks support
  clk: shmobile: r8a7779: Add MSTP clock support
  ARM: shmobile: r8a7779: Add clock index macros for DT sources
  ARM: shmobile: r8a7779: Add clocks
  ARM: shmobile: Sync Marzen DTS with Marzen reference DTS
  ARM: shmobile: marzen: Specify external clock frequency in DT
  ARM: shmobile: marzen: Reference clocks
  ARM: shmobile: r8a7779: Reference clocks
  ARM: shmobile: r8a7779: Add helper to read mode pins
  ARM: shmobile: r8a7779: Move r8a7779_earlytimer_init to
    clock-r8a7779.c
  ARM: shmobile: marzen-reference: Move clock and OF device
    initialisation into board code
  ARM: shmobile: r8a7779: Do not include sh_clk.h in r8a7779.h
  ARM: shmobile: r8a7779: Initial multiplatform support
  ARM: shmobile: marzen-reference: Initialize CPG device
  ARM: shmobile: marzen-reference: Instantiate clkdevs for SCIF and TMU
  ARM: shmobile: marzen: Add to shmobile defconfig
  ARM: shmobile: Remove non-multiplatform Marzen reference support
  ARM: shmobile: Let Marzen multiplatform boot with Marzen DTB
  ARM: shmobile: Remove Marzen reference DTS
  ARM: shmobile: marzen-reference: Remove legacy clock support

 .../bindings/clock/renesas,cpg-mstp-clocks.txt     |   1 +
 .../bindings/clock/renesas,r8a7779-cpg-clocks.txt  |  26 +++
 arch/arm/boot/dts/Makefile                         |   4 +-
 arch/arm/boot/dts/r8a7779-marzen-reference.dts     | 120 -------------
 arch/arm/boot/dts/r8a7779-marzen.dts               |  98 +++++++++++
 arch/arm/boot/dts/r8a7779.dtsi                     | 141 +++++++++++++++
 arch/arm/configs/shmobile_defconfig                |   2 +
 arch/arm/mach-shmobile/Kconfig                     |  22 +--
 arch/arm/mach-shmobile/Makefile                    |   2 +-
 arch/arm/mach-shmobile/Makefile.boot               |   1 -
 arch/arm/mach-shmobile/board-marzen-reference.c    |  40 +++++
 arch/arm/mach-shmobile/clock-r8a7779.c             |  22 ++-
 arch/arm/mach-shmobile/include/mach/r8a7779.h      |   2 +-
 arch/arm/mach-shmobile/setup-r8a7779.c             |  28 +--
 drivers/clk/shmobile/Makefile                      |   1 +
 drivers/clk/shmobile/clk-r8a7779.c                 | 191 +++++++++++++++++++++
 include/dt-bindings/clock/r8a7779-clock.h          |  63 +++++++
 include/linux/clk/shmobile.h                       |   3 +
 18 files changed, 606 insertions(+), 161 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
 delete mode 100644 arch/arm/boot/dts/r8a7779-marzen-reference.dts
 create mode 100644 drivers/clk/shmobile/clk-r8a7779.c
 create mode 100644 include/dt-bindings/clock/r8a7779-clock.h

-- 
1.8.5.2

[PATCH v3 00/20] ARM: shmobile: r8a7779, marzen: CCF and multiplatform

[Simon Horman]

The aim of this series is to add common clock framework and in turn
multiplatform support to the r8a7779 SoC and marzen-reference.  It
subsequently removes non-multiplatform support from marzen-reference.


This is based on work for R-Car Gen2 by Laurent Pinchart and Magnus Damm.


This series is based on the renesas-devel-v3.14-rc4-20140225
tag of my renesas tree.

This series is known not to work when
booting with SMP enabled and maxcpus not set to 0.


Simon Horman (20):
  clk: shmobile: r8a7779: Add clocks support
  clk: shmobile: r8a7779: Add MSTP clock support
  ARM: shmobile: r8a7779: Add clock index macros for DT sources
  ARM: shmobile: r8a7779: Add clocks
  ARM: shmobile: Sync Marzen DTS with Marzen reference DTS
  ARM: shmobile: marzen: Specify external clock frequency in DT
  ARM: shmobile: marzen: Reference clocks
  ARM: shmobile: r8a7779: Reference clocks
  ARM: shmobile: r8a7779: Add helper to read mode pins
  ARM: shmobile: r8a7779: Move r8a7779_earlytimer_init to
    clock-r8a7779.c
  ARM: shmobile: marzen-reference: Move clock and OF device
    initialisation into board code
  ARM: shmobile: r8a7779: Do not include sh_clk.h in r8a7779.h
  ARM: shmobile: r8a7779: Initial multiplatform support
  ARM: shmobile: marzen-reference: Initialize CPG device
  ARM: shmobile: marzen-reference: Instantiate clkdevs for SCIF and TMU
  ARM: shmobile: marzen: Add to shmobile defconfig
  ARM: shmobile: Remove non-multiplatform Marzen reference support
  ARM: shmobile: Let Marzen multiplatform boot with Marzen DTB
  ARM: shmobile: Remove Marzen reference DTS
  ARM: shmobile: marzen-reference: Remove legacy clock support

 .../bindings/clock/renesas,cpg-mstp-clocks.txt     |   1 +
 .../bindings/clock/renesas,r8a7779-cpg-clocks.txt  |  26 +++
 arch/arm/boot/dts/Makefile                         |   4 +-
 arch/arm/boot/dts/r8a7779-marzen-reference.dts     | 120 -------------
 arch/arm/boot/dts/r8a7779-marzen.dts               |  98 +++++++++++
 arch/arm/boot/dts/r8a7779.dtsi                     | 141 +++++++++++++++
 arch/arm/configs/shmobile_defconfig                |   2 +
 arch/arm/mach-shmobile/Kconfig                     |  22 +--
 arch/arm/mach-shmobile/Makefile                    |   2 +-
 arch/arm/mach-shmobile/Makefile.boot               |   1 -
 arch/arm/mach-shmobile/board-marzen-reference.c    |  40 +++++
 arch/arm/mach-shmobile/clock-r8a7779.c             |  22 ++-
 arch/arm/mach-shmobile/include/mach/r8a7779.h      |   2 +-
 arch/arm/mach-shmobile/setup-r8a7779.c             |  28 +--
 drivers/clk/shmobile/Makefile                      |   1 +
 drivers/clk/shmobile/clk-r8a7779.c                 | 191 +++++++++++++++++++++
 include/dt-bindings/clock/r8a7779-clock.h          |  63 +++++++
 include/linux/clk/shmobile.h                       |   3 +
 18 files changed, 606 insertions(+), 161 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
 delete mode 100644 arch/arm/boot/dts/r8a7779-marzen-reference.dts
 create mode 100644 drivers/clk/shmobile/clk-r8a7779.c
 create mode 100644 include/dt-bindings/clock/r8a7779-clock.h

-- 
1.8.5.2

[PATCH v3 01/20] clk: shmobile: r8a7779: Add clocks support

[Simon Horman]

The R8A7779 SoC has several clocks that are too custom to be supported in a
generic driver. Those clocks can be divided in two categories:

- Fixed rate clocks with multiplier and divisor set according to boot
  mode configuration

- Custom divider clocks with SoC-specific divider values

This driver supports both.

Based on work for R-Car Gen2 SoCs by Laurent Pinchart.

Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

---
v3
* As suggested by Laurent Pinchart
  - Added external clock input
  - Use PLLA ratio set bu MD11 and MD12
  - Add _div suffixes of fields of struct cpt_clk_config
  - Register PLLA as a fixed factor clock
  - Use sizeof() instead of sizeof
  - Use num_clks instead of CPG_NUM_CLOCKS in r8a7779_cpg_clocks_init()

  - I kept this as r8a7779 binding rather than moving to a R-Car Gen1
    binding which could be shared with other SoCs as I do not believe that
    the SoCs is are sufficiently similar.
---
 .../bindings/clock/renesas,r8a7779-cpg-clocks.txt  |  26 +++
 drivers/clk/shmobile/Makefile                      |   1 +
 drivers/clk/shmobile/clk-r8a7779.c                 | 191 +++++++++++++++++++++
 include/linux/clk/shmobile.h                       |   3 +
 4 files changed, 221 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
 create mode 100644 drivers/clk/shmobile/clk-r8a7779.c

diff --git a/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
new file mode 100644
index 0000000..1461323
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
@@ -0,0 +1,26 @@
+* Renesas R8A7779 Clock Pulse Generator (CPG)
+
+The CPG generates core clocks for the R8A7779. It includes one PLL and
+and several fixed ratio dividers
+
+Required Properties:
+
+  - compatible: Must be "renesas,r8a7779-cpg-clocks"
+  - reg: Base address and length of the memory resource used by the CPG
+
+  - clocks: Reference to the parent clock
+  - #clock-cells: Must be 1
+  - clock-output-names: The names of the clocks. Supported clocks are "plla",
+    "z", "zs", "s", "s1", "p", "out".
+
+
+Example
+-------
+
+	cpg_clocks: cpg_clocks@ffc80000 {
+		compatible = "renesas,r8a7779-cpg-clocks";
+		reg = <0 0xffc80000 0 0x80>;
+		clocks = <&extal_clk>;
+		#clock-cells = <1>;
+		clock-output-names = "plla", "z", "zs", "s", "s1", "p", "out";
+	};
diff --git a/drivers/clk/shmobile/Makefile b/drivers/clk/shmobile/Makefile
index 9ecef14..2121ba0 100644
--- a/drivers/clk/shmobile/Makefile
+++ b/drivers/clk/shmobile/Makefile
@@ -1,4 +1,5 @@
 obj-$(CONFIG_ARCH_EMEV2)		+= clk-emev2.o
+obj-$(CONFIG_ARCH_R8A7779)		+= clk-r8a7779.o
 obj-$(CONFIG_ARCH_R8A7790)		+= clk-rcar-gen2.o
 obj-$(CONFIG_ARCH_R8A7791)		+= clk-rcar-gen2.o
 obj-$(CONFIG_ARCH_SHMOBILE_MULTI)	+= clk-div6.o
diff --git a/drivers/clk/shmobile/clk-r8a7779.c b/drivers/clk/shmobile/clk-r8a7779.c
new file mode 100644
index 0000000..2ca2d67
--- /dev/null
+++ b/drivers/clk/shmobile/clk-r8a7779.c
@@ -0,0 +1,191 @@
+/*
+ * r8a7779 Core CPG Clocks
+ *
+ * Copyright (C) 2013, 2014 Horms Solutions Ltd.
+ *
+ * Contact: Simon Horman <horms@verge.net.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/clk/shmobile.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/spinlock.h>
+
+#include <dt-bindings/clock/r8a7779-clock.h>
+
+#define CPG_NUM_CLOCKS			(R8A7779_CLK_OUT + 1)
+
+struct r8a7779_cpg {
+	struct clk_onecell_data data;
+	spinlock_t lock;
+	void __iomem *reg;
+};
+
+/* -----------------------------------------------------------------------------
+ * CPG Clock Data
+ */
+
+/*
+ *		MD1 = 1			MD1 = 0
+ *		(PLLA = 1500)		(PLLA = 1600)
+ *		(MHz)			(MHz)
+ *------------------------------------------------+--------------------
+ * clkz		1000   (2/3)		800   (1/2)
+ * clkzs	 250   (1/6)		200   (1/8)
+ * clki		 750   (1/2)		800   (1/2)
+ * clks		 250   (1/6)		200   (1/8)
+ * clks1	 125   (1/12)		100   (1/16)
+ * clks3	 187.5 (1/8)		200   (1/8)
+ * clks4	  93.7 (1/16)		100   (1/16)
+ * clkp		  62.5 (1/24)		 50   (1/32)
+ * clkg		  62.5 (1/24)		 66.6 (1/24)
+ * clkb, CLKOUT
+ * (MD2 = 0)	  62.5 (1/24)		 66.6 (1/24)
+ * (MD2 = 1)	  41.6 (1/36)		 50   (1/32)
+ */
+
+#define CPG_CLK_CONFIG_INDEX(md)	(((md) & (BIT(1)|BIT(2))) >> 1)
+
+struct cpg_clk_config {
+	unsigned int z_mult;
+	unsigned int z_div;
+	unsigned int zs_and_s_div;
+	unsigned int s1_div;
+	unsigned int p_div;
+	unsigned int out_div;
+};
+
+static const struct cpg_clk_config cpg_clk_configs[4] __initconst = {
+	{ 1, 2, 8, 16, 32, 24 },
+	{ 1, 2, 8, 16, 32, 24 },
+	{ 2, 3, 6, 12, 24, 36 },
+	{ 2, 3, 6, 12, 24, 32 },
+};
+
+/*
+ *   MD		PLLA Ratio
+ * 12 11
+ *------------------------
+ * 0  0		x42
+ * 0  1		x48
+ * 1  0		x56
+ * 1  1		x64
+ */
+#define CPG_PLL_CONFIG_INDEX(md)	((((md) & BIT(14)) >> 12) | \
+					 (((md) & BIT(13)) >> 12) | \
+					 (((md) & BIT(19)) >> 19))
+struct cpg_pll_config {
+	unsigned int extal_div;
+	unsigned int pll1_mult;
+	unsigned int pll3_mult;
+};
+
+#define CPG_PLLA_MULT_INDEX(md)	(((md) & (BIT(12)|BIT(11))) >> 11)
+
+static const unsigned int cpg_plla_mult[4] __initconst = { 42, 48, 56, 64 };
+
+/* -----------------------------------------------------------------------------
+ * Initialization
+ */
+
+static u32 cpg_mode __initdata;
+
+static struct clk * __init
+r8a7779_cpg_register_clock(struct device_node *np, struct r8a7779_cpg *cpg,
+			   const struct cpg_clk_config *config,
+			   unsigned int plla_mult, const char *name)
+{
+	const char *parent_name = "plla";
+	unsigned int mult = 1;
+	unsigned int div = 1;
+
+	if (!strcmp(name, "plla")) {
+		parent_name = of_clk_get_parent_name(np, 0);
+		mult = plla_mult;
+	} else if (!strcmp(name, "z")) {
+		div = config->z_div;
+		mult = config->z_mult;
+	} else if (!strcmp(name, "zs") || !strcmp(name, "s")) {
+		div = config->zs_and_s_div;
+	} else if (!strcmp(name, "s1")) {
+		div = config->s1_div;
+	} else if (!strcmp(name, "p")) {
+		div = config->p_div;
+	} else if (!strcmp(name, "out")) {
+		div = config->out_div;
+	}
+
+	return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, div);
+}
+
+static void __init r8a7779_cpg_clocks_init(struct device_node *np)
+{
+	const struct cpg_clk_config *config;
+	struct r8a7779_cpg *cpg;
+	struct clk **clks;
+	unsigned int i, plla_mult;
+	int num_clks;
+
+	num_clks = of_property_count_strings(np, "clock-output-names");
+	if (num_clks < 0) {
+		pr_err("%s: failed to count clocks\n", __func__);
+		return;
+	}
+
+	cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
+	clks = kzalloc(CPG_NUM_CLOCKS * sizeof(*clks), GFP_KERNEL);
+	if (cpg = NULL || clks = NULL) {
+		/* We're leaking memory on purpose, there's no point in cleaning
+		 * up as the system won't boot anyway.
+		 */
+		pr_err("%s: failed to allocate cpg\n", __func__);
+		return;
+	}
+
+	spin_lock_init(&cpg->lock);
+
+	cpg->data.clks = clks;
+	cpg->data.clk_num = num_clks;
+
+	cpg->reg = of_iomap(np, 0);
+	if (WARN_ON(cpg->reg = NULL))
+		return;
+
+	config = &cpg_clk_configs[CPG_CLK_CONFIG_INDEX(cpg_mode)];
+	plla_mult = cpg_plla_mult[CPG_PLLA_MULT_INDEX(cpg_mode)];
+
+	for (i = 0; i < num_clks; ++i) {
+		const char *name;
+		struct clk *clk;
+
+		of_property_read_string_index(np, "clock-output-names", i,
+					      &name);
+
+		clk = r8a7779_cpg_register_clock(np, cpg, config,
+						 plla_mult, name);
+		if (IS_ERR(clk))
+			pr_err("%s: failed to register %s %s clock (%ld)\n",
+			       __func__, np->name, name, PTR_ERR(clk));
+		else
+			cpg->data.clks[i] = clk;
+	}
+
+	of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
+}
+CLK_OF_DECLARE(r8a7779_cpg_clks, "renesas,r8a7779-cpg-clocks",
+	       r8a7779_cpg_clocks_init);
+
+void __init r8a7779_clocks_init(u32 mode)
+{
+	cpg_mode = mode;
+
+	of_clk_init(NULL);
+}
diff --git a/include/linux/clk/shmobile.h b/include/linux/clk/shmobile.h
index f9bf080..7667f49 100644
--- a/include/linux/clk/shmobile.h
+++ b/include/linux/clk/shmobile.h
@@ -1,7 +1,9 @@
 /*
  * Copyright 2013 Ideas On Board SPRL
+ * Copyright 2013 Horms Solutions Ltd.
  *
  * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+ * Contact: Simon Horman <horms@verge.net.au>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -14,6 +16,7 @@
 
 #include <linux/types.h>
 
+void r8a7779_clocks_init(u32 mode);
 void rcar_gen2_clocks_init(u32 mode);
 
 #endif
-- 
1.8.5.2

[PATCH v3 01/20] clk: shmobile: r8a7779: Add clocks support

[Simon Horman]

The R8A7779 SoC has several clocks that are too custom to be supported in a
generic driver. Those clocks can be divided in two categories:

- Fixed rate clocks with multiplier and divisor set according to boot
  mode configuration

- Custom divider clocks with SoC-specific divider values

This driver supports both.

Based on work for R-Car Gen2 SoCs by Laurent Pinchart.

Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

---
v3
* As suggested by Laurent Pinchart
  - Added external clock input
  - Use PLLA ratio set bu MD11 and MD12
  - Add _div suffixes of fields of struct cpt_clk_config
  - Register PLLA as a fixed factor clock
  - Use sizeof() instead of sizeof
  - Use num_clks instead of CPG_NUM_CLOCKS in r8a7779_cpg_clocks_init()

  - I kept this as r8a7779 binding rather than moving to a R-Car Gen1
    binding which could be shared with other SoCs as I do not believe that
    the SoCs is are sufficiently similar.
---
 .../bindings/clock/renesas,r8a7779-cpg-clocks.txt  |  26 +++
 drivers/clk/shmobile/Makefile                      |   1 +
 drivers/clk/shmobile/clk-r8a7779.c                 | 191 +++++++++++++++++++++
 include/linux/clk/shmobile.h                       |   3 +
 4 files changed, 221 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
 create mode 100644 drivers/clk/shmobile/clk-r8a7779.c

diff --git a/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
new file mode 100644
index 0000000..1461323
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
@@ -0,0 +1,26 @@
+* Renesas R8A7779 Clock Pulse Generator (CPG)
+
+The CPG generates core clocks for the R8A7779. It includes one PLL and
+and several fixed ratio dividers
+
+Required Properties:
+
+  - compatible: Must be "renesas,r8a7779-cpg-clocks"
+  - reg: Base address and length of the memory resource used by the CPG
+
+  - clocks: Reference to the parent clock
+  - #clock-cells: Must be 1
+  - clock-output-names: The names of the clocks. Supported clocks are "plla",
+    "z", "zs", "s", "s1", "p", "out".
+
+
+Example
+-------
+
+	cpg_clocks: cpg_clocks at ffc80000 {
+		compatible = "renesas,r8a7779-cpg-clocks";
+		reg = <0 0xffc80000 0 0x80>;
+		clocks = <&extal_clk>;
+		#clock-cells = <1>;
+		clock-output-names = "plla", "z", "zs", "s", "s1", "p", "out";
+	};
diff --git a/drivers/clk/shmobile/Makefile b/drivers/clk/shmobile/Makefile
index 9ecef14..2121ba0 100644
--- a/drivers/clk/shmobile/Makefile
+++ b/drivers/clk/shmobile/Makefile
@@ -1,4 +1,5 @@
 obj-$(CONFIG_ARCH_EMEV2)		+= clk-emev2.o
+obj-$(CONFIG_ARCH_R8A7779)		+= clk-r8a7779.o
 obj-$(CONFIG_ARCH_R8A7790)		+= clk-rcar-gen2.o
 obj-$(CONFIG_ARCH_R8A7791)		+= clk-rcar-gen2.o
 obj-$(CONFIG_ARCH_SHMOBILE_MULTI)	+= clk-div6.o
diff --git a/drivers/clk/shmobile/clk-r8a7779.c b/drivers/clk/shmobile/clk-r8a7779.c
new file mode 100644
index 0000000..2ca2d67
--- /dev/null
+++ b/drivers/clk/shmobile/clk-r8a7779.c
@@ -0,0 +1,191 @@
+/*
+ * r8a7779 Core CPG Clocks
+ *
+ * Copyright (C) 2013, 2014 Horms Solutions Ltd.
+ *
+ * Contact: Simon Horman <horms@verge.net.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/clk/shmobile.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/spinlock.h>
+
+#include <dt-bindings/clock/r8a7779-clock.h>
+
+#define CPG_NUM_CLOCKS			(R8A7779_CLK_OUT + 1)
+
+struct r8a7779_cpg {
+	struct clk_onecell_data data;
+	spinlock_t lock;
+	void __iomem *reg;
+};
+
+/* -----------------------------------------------------------------------------
+ * CPG Clock Data
+ */
+
+/*
+ *		MD1 = 1			MD1 = 0
+ *		(PLLA = 1500)		(PLLA = 1600)
+ *		(MHz)			(MHz)
+ *------------------------------------------------+--------------------
+ * clkz		1000   (2/3)		800   (1/2)
+ * clkzs	 250   (1/6)		200   (1/8)
+ * clki		 750   (1/2)		800   (1/2)
+ * clks		 250   (1/6)		200   (1/8)
+ * clks1	 125   (1/12)		100   (1/16)
+ * clks3	 187.5 (1/8)		200   (1/8)
+ * clks4	  93.7 (1/16)		100   (1/16)
+ * clkp		  62.5 (1/24)		 50   (1/32)
+ * clkg		  62.5 (1/24)		 66.6 (1/24)
+ * clkb, CLKOUT
+ * (MD2 = 0)	  62.5 (1/24)		 66.6 (1/24)
+ * (MD2 = 1)	  41.6 (1/36)		 50   (1/32)
+ */
+
+#define CPG_CLK_CONFIG_INDEX(md)	(((md) & (BIT(1)|BIT(2))) >> 1)
+
+struct cpg_clk_config {
+	unsigned int z_mult;
+	unsigned int z_div;
+	unsigned int zs_and_s_div;
+	unsigned int s1_div;
+	unsigned int p_div;
+	unsigned int out_div;
+};
+
+static const struct cpg_clk_config cpg_clk_configs[4] __initconst = {
+	{ 1, 2, 8, 16, 32, 24 },
+	{ 1, 2, 8, 16, 32, 24 },
+	{ 2, 3, 6, 12, 24, 36 },
+	{ 2, 3, 6, 12, 24, 32 },
+};
+
+/*
+ *   MD		PLLA Ratio
+ * 12 11
+ *------------------------
+ * 0  0		x42
+ * 0  1		x48
+ * 1  0		x56
+ * 1  1		x64
+ */
+#define CPG_PLL_CONFIG_INDEX(md)	((((md) & BIT(14)) >> 12) | \
+					 (((md) & BIT(13)) >> 12) | \
+					 (((md) & BIT(19)) >> 19))
+struct cpg_pll_config {
+	unsigned int extal_div;
+	unsigned int pll1_mult;
+	unsigned int pll3_mult;
+};
+
+#define CPG_PLLA_MULT_INDEX(md)	(((md) & (BIT(12)|BIT(11))) >> 11)
+
+static const unsigned int cpg_plla_mult[4] __initconst = { 42, 48, 56, 64 };
+
+/* -----------------------------------------------------------------------------
+ * Initialization
+ */
+
+static u32 cpg_mode __initdata;
+
+static struct clk * __init
+r8a7779_cpg_register_clock(struct device_node *np, struct r8a7779_cpg *cpg,
+			   const struct cpg_clk_config *config,
+			   unsigned int plla_mult, const char *name)
+{
+	const char *parent_name = "plla";
+	unsigned int mult = 1;
+	unsigned int div = 1;
+
+	if (!strcmp(name, "plla")) {
+		parent_name = of_clk_get_parent_name(np, 0);
+		mult = plla_mult;
+	} else if (!strcmp(name, "z")) {
+		div = config->z_div;
+		mult = config->z_mult;
+	} else if (!strcmp(name, "zs") || !strcmp(name, "s")) {
+		div = config->zs_and_s_div;
+	} else if (!strcmp(name, "s1")) {
+		div = config->s1_div;
+	} else if (!strcmp(name, "p")) {
+		div = config->p_div;
+	} else if (!strcmp(name, "out")) {
+		div = config->out_div;
+	}
+
+	return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, div);
+}
+
+static void __init r8a7779_cpg_clocks_init(struct device_node *np)
+{
+	const struct cpg_clk_config *config;
+	struct r8a7779_cpg *cpg;
+	struct clk **clks;
+	unsigned int i, plla_mult;
+	int num_clks;
+
+	num_clks = of_property_count_strings(np, "clock-output-names");
+	if (num_clks < 0) {
+		pr_err("%s: failed to count clocks\n", __func__);
+		return;
+	}
+
+	cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
+	clks = kzalloc(CPG_NUM_CLOCKS * sizeof(*clks), GFP_KERNEL);
+	if (cpg == NULL || clks == NULL) {
+		/* We're leaking memory on purpose, there's no point in cleaning
+		 * up as the system won't boot anyway.
+		 */
+		pr_err("%s: failed to allocate cpg\n", __func__);
+		return;
+	}
+
+	spin_lock_init(&cpg->lock);
+
+	cpg->data.clks = clks;
+	cpg->data.clk_num = num_clks;
+
+	cpg->reg = of_iomap(np, 0);
+	if (WARN_ON(cpg->reg == NULL))
+		return;
+
+	config = &cpg_clk_configs[CPG_CLK_CONFIG_INDEX(cpg_mode)];
+	plla_mult = cpg_plla_mult[CPG_PLLA_MULT_INDEX(cpg_mode)];
+
+	for (i = 0; i < num_clks; ++i) {
+		const char *name;
+		struct clk *clk;
+
+		of_property_read_string_index(np, "clock-output-names", i,
+					      &name);
+
+		clk = r8a7779_cpg_register_clock(np, cpg, config,
+						 plla_mult, name);
+		if (IS_ERR(clk))
+			pr_err("%s: failed to register %s %s clock (%ld)\n",
+			       __func__, np->name, name, PTR_ERR(clk));
+		else
+			cpg->data.clks[i] = clk;
+	}
+
+	of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
+}
+CLK_OF_DECLARE(r8a7779_cpg_clks, "renesas,r8a7779-cpg-clocks",
+	       r8a7779_cpg_clocks_init);
+
+void __init r8a7779_clocks_init(u32 mode)
+{
+	cpg_mode = mode;
+
+	of_clk_init(NULL);
+}
diff --git a/include/linux/clk/shmobile.h b/include/linux/clk/shmobile.h
index f9bf080..7667f49 100644
--- a/include/linux/clk/shmobile.h
+++ b/include/linux/clk/shmobile.h
@@ -1,7 +1,9 @@
 /*
  * Copyright 2013 Ideas On Board SPRL
+ * Copyright 2013 Horms Solutions Ltd.
  *
  * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+ * Contact: Simon Horman <horms@verge.net.au>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -14,6 +16,7 @@
 
 #include <linux/types.h>
 
+void r8a7779_clocks_init(u32 mode);
 void rcar_gen2_clocks_init(u32 mode);
 
 #endif
-- 
1.8.5.2

[PATCH v3 02/20] clk: shmobile: r8a7779: Add MSTP clock support

[Simon Horman]

Add MSTP clock support for the r8a7779 SoC

The only change required appears to be to note a new
compatibility string in the bindings.

Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

---
v3
* As suggested by Laurent Pinchart
  - Add entry in numerical order
---
 Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
index a6a352c..f3226ac 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
@@ -10,6 +10,7 @@ index in the group, from 0 to 31.
 Required Properties:
 
   - compatible: Must be one of the following
+    - "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks
     - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks
     - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2) MSTP gate clocks
     - "renesas,cpg-mstp-clock" for generic MSTP gate clocks
-- 
1.8.5.2

[PATCH v3 02/20] clk: shmobile: r8a7779: Add MSTP clock support

[Simon Horman]

Add MSTP clock support for the r8a7779 SoC

The only change required appears to be to note a new
compatibility string in the bindings.

Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

---
v3
* As suggested by Laurent Pinchart
  - Add entry in numerical order
---
 Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
index a6a352c..f3226ac 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
@@ -10,6 +10,7 @@ index in the group, from 0 to 31.
 Required Properties:
 
   - compatible: Must be one of the following
+    - "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks
     - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks
     - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2) MSTP gate clocks
     - "renesas,cpg-mstp-clock" for generic MSTP gate clocks
-- 
1.8.5.2

[PATCH v3 03/20] ARM: shmobile: r8a7779: Add clock index macros for DT sources

[Simon Horman]

Add macros usable by device tree sources to reference r8a7779 clocks by
index.

Based on work for the r8a7791 SoC by Laurent Pinchart.

Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
v3
* As suggested by Laurent Pinchart
  - Consolidate R8A7779_CLK_HSPI{0,1,2} into R8A7779_CLK_HSPI
  - Correct inverted indexes of R8A7779_CLK_TMU{1,2}
  - Consolidate R8A7779_CLK_{E,O}HCI{0,1} into R8A7779_CLK_USB{0,1}
  - Add ethernet, MMC and HSCIF entries
  - Replace R8A7779_SCIF6 with R8A7779_CLK_SCIF5

* Add R8A7779_CLK_PCIE

v2
* No change
---
 include/dt-bindings/clock/r8a7779-clock.h | 63 +++++++++++++++++++++++++++++++
 1 file changed, 63 insertions(+)
 create mode 100644 include/dt-bindings/clock/r8a7779-clock.h

diff --git a/include/dt-bindings/clock/r8a7779-clock.h b/include/dt-bindings/clock/r8a7779-clock.h
new file mode 100644
index 0000000..8ab8007
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7779-clock.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (C) 2013  Horms Solutions Ltd.
+ *
+ * Contact: Simon Horman <horms@verge.net.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7779_H__
+#define __DT_BINDINGS_CLOCK_R8A7779_H__
+
+/* CPG */
+#define R8A7779_CLK_PLLA	0
+#define R8A7779_CLK_Z		1
+#define R8A7779_CLK_ZS		2
+#define R8A7779_CLK_S		3
+#define R8A7779_CLK_S1		4
+#define R8A7779_CLK_P		5
+#define R8A7779_CLK_OUT		6
+
+/* MSTP 0 */
+#define R8A7779_CLK_HSPI	7
+#define R8A7779_CLK_TMU2	14
+#define R8A7779_CLK_TMU1	15
+#define R8A7779_CLK_TMU0	16
+#define R8A7779_CLK_HSCIF1	18
+#define R8A7779_CLK_HSCIF0	19
+#define R8A7779_CLK_SCIF5	21
+#define R8A7779_CLK_SCIF4	22
+#define R8A7779_CLK_SCIF3	23
+#define R8A7779_CLK_SCIF2	24
+#define R8A7779_CLK_SCIF1	25
+#define R8A7779_CLK_SCIF0	26
+#define R8A7779_CLK_I2C3	27
+#define R8A7779_CLK_I2C2	28
+#define R8A7779_CLK_I2C1	29
+#define R8A7779_CLK_I2C0	30
+
+/* MSTP 1 */
+#define R8A7779_CLK_USB01	0
+#define R8A7779_CLK_USB2	1
+#define R8A7779_CLK_DU		3
+#define R8A7779_CLK_VIN2	8
+#define R8A7779_CLK_VIN1	9
+#define R8A7779_CLK_VIN0	10
+#define R8A7779_CLK_ETHER	14
+#define R8A7779_CLK_SATA	15
+#define R8A7779_CLK_PCIE	16
+#define R8A7779_CLK_VIN3	20
+
+/* MSTP 3 */
+#define R8A7779_CLK_SDHI3	20
+#define R8A7779_CLK_SDHI2	21
+#define R8A7779_CLK_SDHI1	22
+#define R8A7779_CLK_SDHI0	23
+#define R8A7779_CLK_MMC1	30
+#define R8A7779_CLK_MMC0	31
+
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7779_H__ */
-- 
1.8.5.2

[PATCH v3 03/20] ARM: shmobile: r8a7779: Add clock index macros for DT sources

[Simon Horman]

Add macros usable by device tree sources to reference r8a7779 clocks by
index.

Based on work for the r8a7791 SoC by Laurent Pinchart.

Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
v3
* As suggested by Laurent Pinchart
  - Consolidate R8A7779_CLK_HSPI{0,1,2} into R8A7779_CLK_HSPI
  - Correct inverted indexes of R8A7779_CLK_TMU{1,2}
  - Consolidate R8A7779_CLK_{E,O}HCI{0,1} into R8A7779_CLK_USB{0,1}
  - Add ethernet, MMC and HSCIF entries
  - Replace R8A7779_SCIF6 with R8A7779_CLK_SCIF5

* Add R8A7779_CLK_PCIE

v2
* No change
---
 include/dt-bindings/clock/r8a7779-clock.h | 63 +++++++++++++++++++++++++++++++
 1 file changed, 63 insertions(+)
 create mode 100644 include/dt-bindings/clock/r8a7779-clock.h

diff --git a/include/dt-bindings/clock/r8a7779-clock.h b/include/dt-bindings/clock/r8a7779-clock.h
new file mode 100644
index 0000000..8ab8007
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7779-clock.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (C) 2013  Horms Solutions Ltd.
+ *
+ * Contact: Simon Horman <horms@verge.net.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7779_H__
+#define __DT_BINDINGS_CLOCK_R8A7779_H__
+
+/* CPG */
+#define R8A7779_CLK_PLLA	0
+#define R8A7779_CLK_Z		1
+#define R8A7779_CLK_ZS		2
+#define R8A7779_CLK_S		3
+#define R8A7779_CLK_S1		4
+#define R8A7779_CLK_P		5
+#define R8A7779_CLK_OUT		6
+
+/* MSTP 0 */
+#define R8A7779_CLK_HSPI	7
+#define R8A7779_CLK_TMU2	14
+#define R8A7779_CLK_TMU1	15
+#define R8A7779_CLK_TMU0	16
+#define R8A7779_CLK_HSCIF1	18
+#define R8A7779_CLK_HSCIF0	19
+#define R8A7779_CLK_SCIF5	21
+#define R8A7779_CLK_SCIF4	22
+#define R8A7779_CLK_SCIF3	23
+#define R8A7779_CLK_SCIF2	24
+#define R8A7779_CLK_SCIF1	25
+#define R8A7779_CLK_SCIF0	26
+#define R8A7779_CLK_I2C3	27
+#define R8A7779_CLK_I2C2	28
+#define R8A7779_CLK_I2C1	29
+#define R8A7779_CLK_I2C0	30
+
+/* MSTP 1 */
+#define R8A7779_CLK_USB01	0
+#define R8A7779_CLK_USB2	1
+#define R8A7779_CLK_DU		3
+#define R8A7779_CLK_VIN2	8
+#define R8A7779_CLK_VIN1	9
+#define R8A7779_CLK_VIN0	10
+#define R8A7779_CLK_ETHER	14
+#define R8A7779_CLK_SATA	15
+#define R8A7779_CLK_PCIE	16
+#define R8A7779_CLK_VIN3	20
+
+/* MSTP 3 */
+#define R8A7779_CLK_SDHI3	20
+#define R8A7779_CLK_SDHI2	21
+#define R8A7779_CLK_SDHI1	22
+#define R8A7779_CLK_SDHI0	23
+#define R8A7779_CLK_MMC1	30
+#define R8A7779_CLK_MMC0	31
+
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7779_H__ */
-- 
1.8.5.2

[PATCH v3 04/20] ARM: shmobile: r8a7779: Add clocks

[Simon Horman]

Declare all core and MSTP clocks currently used by r8a7779-based boards.

Based on work by Laurent Pinchart for the r8a7790 and r8a7791 SoCs.

Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

---
v3
* As suggested by Laurent Pinchart
  - Add and use extal_clk
  - Fix bogus status register use for MSTP clocks
  - Fix bogus mstp3_cls to use its own entries rather than
    that of mstp1_clks

* Update to use "main" in cpg_clocks as per updated
  binding in previous patch
* Update for new, consolidated and renamed index macros
  - R8A7779_CLK_ETHER
  - R8A7779_CLK_HSCIF
  - R8A7779_CLK_HSPI
  - R8A7779_CLK_MMC0,1
  - R8A7779_CLK_PCIE
  - R8A7779_CLK_USB01,2
---
 arch/arm/boot/dts/r8a7779.dtsi | 129 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 129 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index d0561d4..240a03e 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -11,6 +11,7 @@
 
 /include/ "skeleton.dtsi"
 
+#include <dt-bindings/clock/r8a7779-clock.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 
 / {
@@ -278,4 +279,132 @@
 		interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
 		status = "disabled";
 	};
+
+	clocks {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		/* External root clock */
+		extal_clk: extal_clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			/* This value must be overriden by the board. */
+			clock-frequency = <0>;
+			clock-output-names = "extal";
+		};
+
+		/* Special CPG clocks */
+		cpg_clocks: cpg_clocks@0xe6150000 {
+			compatible = "renesas,r8a7779-cpg-clocks";
+			reg = <0 0xe6150000 0 0x1000>;
+			clocks = <&extal_clk>;
+			#clock-cells = <1>;
+			clock-output-names = "plla", "z", "zs", "s",
+					     "s1", "p", "out";
+		};
+
+		/* Fixed factor clocks */
+		i_clk: i_clk {
+			compatible = "fixed-factor-clock";
+			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
+			#clock-cells = <0>;
+			clock-div = <2>;
+			clock-mult = <1>;
+			clock-output-names = "i";
+		};
+		s3_clk: s3_clk {
+			compatible = "fixed-factor-clock";
+			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
+			#clock-cells = <0>;
+			clock-div = <8>;
+			clock-mult = <1>;
+			clock-output-names = "s3";
+		};
+		s4_clk: s4_clk {
+			compatible = "fixed-factor-clock";
+			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
+			#clock-cells = <0>;
+			clock-div = <16>;
+			clock-mult = <1>;
+			clock-output-names = "s4";
+		};
+		g_clk: g_clk {
+			compatible = "fixed-factor-clock";
+			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
+			#clock-cells = <0>;
+			clock-div = <24>;
+			clock-mult = <1>;
+			clock-output-names = "g";
+		};
+
+		/* Gate clocks */
+		mstp0_clks: mstp0_clks {
+			compatible = "renesas,r8a7779-mstp-clocks", "renesas,cpg-mstp-clocks";
+			reg = <0 0xffc80030 0 4>;
+			clocks = <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
+				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
+				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
+				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
+				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
+				 <&cpg_clocks R8A7779_CLK_P>;
+			#clock-cells = <1>;
+			renesas,clock-indices = <
+				R8A7779_CLK_HSPI R8A7779_CLK_TMU0 R8A7779_CLK_TMU0
+				R8A7779_CLK_TMU0 R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
+				R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2 R8A7779_CLK_SCIF1
+				R8A7779_CLK_SCIF0 R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
+				R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
+			>;
+			clock-output-names +				"hspi", "tmu00", "tmu01",
+				"tmu02", "scif5", "scif4",
+				"scif3", "scif2", "scif1",
+				"scif0", "i2c3", "i2c2",
+				"i2c1", "i2c0";
+		};
+		mstp1_clks: mstp1_clks {
+			compatible = "renesas,r8a7779-mstp-clocks", "renesas,cpg-mstp-clocks";
+			reg = <0 0xffc80034 0 4>, <0 0xffc80044 0 4>;
+			clocks = <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
+				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
+				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
+				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
+				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
+				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>;
+			#clock-cells = <1>;
+			renesas,clock-indices = <
+				R8A7779_CLK_USB01 R8A7779_CLK_USB01
+				R8A7779_CLK_USB2 R8A7779_CLK_USB2
+				R8A7779_CLK_DU R8A7779_CLK_VIN2
+				R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
+				R8A7779_CLK_ETHER R8A7779_CLK_SATA
+				R8A7779_CLK_PCIE R8A7779_CLK_VIN3
+			>;
+			clock-output-names +				"ehci0", "ohci0",
+				"ehci1", "ohci1",
+				"du", "vin2",
+				"vin1", "vin0",
+				"ether", "sata",
+				"pcie", "vin3";
+		};
+		mstp3_clks: mstp3_clks {
+			compatible = "renesas,r8a7779-mstp-clocks", "renesas,cpg-mstp-clocks";
+			reg = <0 0xffc8003c 0 4>;
+			clocks = <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
+				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
+				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>;
+			#clock-cells = <1>;
+			renesas,clock-indices = <
+				R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
+				R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
+				R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
+			>;
+			clock-output-names +				"sdhi3", "sdhi2",
+				"sdhi1", "sdhi0",
+				"mmc1", "mmc0";
+		};
+	};
 };
-- 
1.8.5.2

[PATCH v3 04/20] ARM: shmobile: r8a7779: Add clocks

[Simon Horman]

Declare all core and MSTP clocks currently used by r8a7779-based boards.

Based on work by Laurent Pinchart for the r8a7790 and r8a7791 SoCs.

Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

---
v3
* As suggested by Laurent Pinchart
  - Add and use extal_clk
  - Fix bogus status register use for MSTP clocks
  - Fix bogus mstp3_cls to use its own entries rather than
    that of mstp1_clks

* Update to use "main" in cpg_clocks as per updated
  binding in previous patch
* Update for new, consolidated and renamed index macros
  - R8A7779_CLK_ETHER
  - R8A7779_CLK_HSCIF
  - R8A7779_CLK_HSPI
  - R8A7779_CLK_MMC0,1
  - R8A7779_CLK_PCIE
  - R8A7779_CLK_USB01,2
---
 arch/arm/boot/dts/r8a7779.dtsi | 129 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 129 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index d0561d4..240a03e 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -11,6 +11,7 @@
 
 /include/ "skeleton.dtsi"
 
+#include <dt-bindings/clock/r8a7779-clock.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 
 / {
@@ -278,4 +279,132 @@
 		interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
 		status = "disabled";
 	};
+
+	clocks {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		/* External root clock */
+		extal_clk: extal_clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			/* This value must be overriden by the board. */
+			clock-frequency = <0>;
+			clock-output-names = "extal";
+		};
+
+		/* Special CPG clocks */
+		cpg_clocks: cpg_clocks at 0xe6150000 {
+			compatible = "renesas,r8a7779-cpg-clocks";
+			reg = <0 0xe6150000 0 0x1000>;
+			clocks = <&extal_clk>;
+			#clock-cells = <1>;
+			clock-output-names = "plla", "z", "zs", "s",
+					     "s1", "p", "out";
+		};
+
+		/* Fixed factor clocks */
+		i_clk: i_clk {
+			compatible = "fixed-factor-clock";
+			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
+			#clock-cells = <0>;
+			clock-div = <2>;
+			clock-mult = <1>;
+			clock-output-names = "i";
+		};
+		s3_clk: s3_clk {
+			compatible = "fixed-factor-clock";
+			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
+			#clock-cells = <0>;
+			clock-div = <8>;
+			clock-mult = <1>;
+			clock-output-names = "s3";
+		};
+		s4_clk: s4_clk {
+			compatible = "fixed-factor-clock";
+			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
+			#clock-cells = <0>;
+			clock-div = <16>;
+			clock-mult = <1>;
+			clock-output-names = "s4";
+		};
+		g_clk: g_clk {
+			compatible = "fixed-factor-clock";
+			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
+			#clock-cells = <0>;
+			clock-div = <24>;
+			clock-mult = <1>;
+			clock-output-names = "g";
+		};
+
+		/* Gate clocks */
+		mstp0_clks: mstp0_clks {
+			compatible = "renesas,r8a7779-mstp-clocks", "renesas,cpg-mstp-clocks";
+			reg = <0 0xffc80030 0 4>;
+			clocks = <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
+				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
+				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
+				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
+				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
+				 <&cpg_clocks R8A7779_CLK_P>;
+			#clock-cells = <1>;
+			renesas,clock-indices = <
+				R8A7779_CLK_HSPI R8A7779_CLK_TMU0 R8A7779_CLK_TMU0
+				R8A7779_CLK_TMU0 R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
+				R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2 R8A7779_CLK_SCIF1
+				R8A7779_CLK_SCIF0 R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
+				R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
+			>;
+			clock-output-names =
+				"hspi", "tmu00", "tmu01",
+				"tmu02", "scif5", "scif4",
+				"scif3", "scif2", "scif1",
+				"scif0", "i2c3", "i2c2",
+				"i2c1", "i2c0";
+		};
+		mstp1_clks: mstp1_clks {
+			compatible = "renesas,r8a7779-mstp-clocks", "renesas,cpg-mstp-clocks";
+			reg = <0 0xffc80034 0 4>, <0 0xffc80044 0 4>;
+			clocks = <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
+				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
+				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
+				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
+				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
+				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>;
+			#clock-cells = <1>;
+			renesas,clock-indices = <
+				R8A7779_CLK_USB01 R8A7779_CLK_USB01
+				R8A7779_CLK_USB2 R8A7779_CLK_USB2
+				R8A7779_CLK_DU R8A7779_CLK_VIN2
+				R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
+				R8A7779_CLK_ETHER R8A7779_CLK_SATA
+				R8A7779_CLK_PCIE R8A7779_CLK_VIN3
+			>;
+			clock-output-names =
+				"ehci0", "ohci0",
+				"ehci1", "ohci1",
+				"du", "vin2",
+				"vin1", "vin0",
+				"ether", "sata",
+				"pcie", "vin3";
+		};
+		mstp3_clks: mstp3_clks {
+			compatible = "renesas,r8a7779-mstp-clocks", "renesas,cpg-mstp-clocks";
+			reg = <0 0xffc8003c 0 4>;
+			clocks = <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
+				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
+				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>;
+			#clock-cells = <1>;
+			renesas,clock-indices = <
+				R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
+				R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
+				R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
+			>;
+			clock-output-names =
+				"sdhi3", "sdhi2",
+				"sdhi1", "sdhi0",
+				"mmc1", "mmc0";
+		};
+	};
 };
-- 
1.8.5.2

[PATCH v3 05/20] ARM: shmobile: Sync Marzen DTS with Marzen reference DTS

[Simon Horman]

Copy the device nodes from Marzen reference into the Marzen device tree
file. This will allow us to use a single DTS file regardless of kernel
configuration. In case of legacy C board code the device nodes may or
may not be used, but in the multiplatform case all the DT device nodes
will be used.

Based on a similar change for the Lager board by Laurent Pinchart.

Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

---
v3
* Updated for recent changes to Marzen reference DTS
---
 arch/arm/boot/dts/r8a7779-marzen.dts | 93 ++++++++++++++++++++++++++++++++++++
 1 file changed, 93 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts
index a7af2c2..eda6240 100644
--- a/arch/arm/boot/dts/r8a7779-marzen.dts
+++ b/arch/arm/boot/dts/r8a7779-marzen.dts
@@ -11,6 +11,8 @@
 
 /dts-v1/;
 #include "r8a7779.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 
 / {
 	model = "marzen";
@@ -24,4 +26,95 @@
 		device_type = "memory";
 		reg = <0x60000000 0x40000000>;
 	};
+
+	fixedregulator3v3: fixedregulator@0 {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	lan0@18000000 {
+		compatible = "smsc,lan9220", "smsc,lan9115";
+		reg = <0x18000000 0x100>;
+		pinctrl-0 = <&lan0_pins>;
+		pinctrl-names = "default";
+
+		phy-mode = "mii";
+		interrupt-parent = <&irqpin0>;
+		interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+		reg-io-width = <4>;
+		vddvario-supply = <&fixedregulator3v3>;
+		vdd33a-supply = <&fixedregulator3v3>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		led2 {
+			gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
+		};
+		led3 {
+			gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
+		};
+		led4 {
+			gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
+
+&irqpin0 {
+	status = "okay";
+};
+
+&pfc {
+	pinctrl-0 = <&scif2_pins &scif4_pins>;
+	pinctrl-names = "default";
+
+	lan0_pins: lan0 {
+		intc {
+			renesas,groups = "intc_irq1_b";
+			renesas,function = "intc";
+		};
+		lbsc {
+			renesas,groups = "lbsc_ex_cs0";
+			renesas,function = "lbsc";
+		};
+	};
+
+	scif2_pins: serial2 {
+		renesas,groups = "scif2_data_c";
+		renesas,function = "scif2";
+	};
+
+	scif4_pins: serial4 {
+		renesas,groups = "scif4_data";
+		renesas,function = "scif4";
+	};
+
+	sdhi0_pins: sd0 {
+		renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
+		renesas,function = "sdhi0";
+	};
+
+	hspi0_pins: hspi0 {
+		renesas,groups = "hspi0";
+		renesas,function = "hspi0";
+	};
+};
+
+&sdhi0 {
+	pinctrl-0 = <&sdhi0_pins>;
+	pinctrl-names = "default";
+
+	vmmc-supply = <&fixedregulator3v3>;
+	bus-width = <4>;
+	status = "okay";
+};
+
+&hspi0 {
+	pinctrl-0 = <&hspi0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
 };
-- 
1.8.5.2

[PATCH v3 05/20] ARM: shmobile: Sync Marzen DTS with Marzen reference DTS

[Simon Horman]

Copy the device nodes from Marzen reference into the Marzen device tree
file. This will allow us to use a single DTS file regardless of kernel
configuration. In case of legacy C board code the device nodes may or
may not be used, but in the multiplatform case all the DT device nodes
will be used.

Based on a similar change for the Lager board by Laurent Pinchart.

Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

---
v3
* Updated for recent changes to Marzen reference DTS
---
 arch/arm/boot/dts/r8a7779-marzen.dts | 93 ++++++++++++++++++++++++++++++++++++
 1 file changed, 93 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts
index a7af2c2..eda6240 100644
--- a/arch/arm/boot/dts/r8a7779-marzen.dts
+++ b/arch/arm/boot/dts/r8a7779-marzen.dts
@@ -11,6 +11,8 @@
 
 /dts-v1/;
 #include "r8a7779.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 
 / {
 	model = "marzen";
@@ -24,4 +26,95 @@
 		device_type = "memory";
 		reg = <0x60000000 0x40000000>;
 	};
+
+	fixedregulator3v3: fixedregulator at 0 {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	lan0 at 18000000 {
+		compatible = "smsc,lan9220", "smsc,lan9115";
+		reg = <0x18000000 0x100>;
+		pinctrl-0 = <&lan0_pins>;
+		pinctrl-names = "default";
+
+		phy-mode = "mii";
+		interrupt-parent = <&irqpin0>;
+		interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+		reg-io-width = <4>;
+		vddvario-supply = <&fixedregulator3v3>;
+		vdd33a-supply = <&fixedregulator3v3>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		led2 {
+			gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
+		};
+		led3 {
+			gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
+		};
+		led4 {
+			gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
+
+&irqpin0 {
+	status = "okay";
+};
+
+&pfc {
+	pinctrl-0 = <&scif2_pins &scif4_pins>;
+	pinctrl-names = "default";
+
+	lan0_pins: lan0 {
+		intc {
+			renesas,groups = "intc_irq1_b";
+			renesas,function = "intc";
+		};
+		lbsc {
+			renesas,groups = "lbsc_ex_cs0";
+			renesas,function = "lbsc";
+		};
+	};
+
+	scif2_pins: serial2 {
+		renesas,groups = "scif2_data_c";
+		renesas,function = "scif2";
+	};
+
+	scif4_pins: serial4 {
+		renesas,groups = "scif4_data";
+		renesas,function = "scif4";
+	};
+
+	sdhi0_pins: sd0 {
+		renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
+		renesas,function = "sdhi0";
+	};
+
+	hspi0_pins: hspi0 {
+		renesas,groups = "hspi0";
+		renesas,function = "hspi0";
+	};
+};
+
+&sdhi0 {
+	pinctrl-0 = <&sdhi0_pins>;
+	pinctrl-names = "default";
+
+	vmmc-supply = <&fixedregulator3v3>;
+	bus-width = <4>;
+	status = "okay";
+};
+
+&hspi0 {
+	pinctrl-0 = <&hspi0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
 };
-- 
1.8.5.2

[PATCH v3 06/20] ARM: shmobile: marzen: Specify external clock frequency in DT

[Simon Horman]

The external crystal frequency is 31.25 on the Marzen board.
Specify it in the device tree.

Based on work for the Lager board by Laurent Pinchart.

Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

---
v3
* Update r8a7779-marzen.dts instead of r8a7779-marzen-reference.dts
---
 arch/arm/boot/dts/r8a7779-marzen.dts | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts
index eda6240..2c727cd 100644
--- a/arch/arm/boot/dts/r8a7779-marzen.dts
+++ b/arch/arm/boot/dts/r8a7779-marzen.dts
@@ -68,6 +68,10 @@
 	status = "okay";
 };
 
+&extal_clk {
+	clock-frequency = <31250000>;
+};
+
 &pfc {
 	pinctrl-0 = <&scif2_pins &scif4_pins>;
 	pinctrl-names = "default";
-- 
1.8.5.2

[PATCH v3 06/20] ARM: shmobile: marzen: Specify external clock frequency in DT

[Simon Horman]

The external crystal frequency is 31.25 on the Marzen board.
Specify it in the device tree.

Based on work for the Lager board by Laurent Pinchart.

Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

---
v3
* Update r8a7779-marzen.dts instead of r8a7779-marzen-reference.dts
---
 arch/arm/boot/dts/r8a7779-marzen.dts | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts
index eda6240..2c727cd 100644
--- a/arch/arm/boot/dts/r8a7779-marzen.dts
+++ b/arch/arm/boot/dts/r8a7779-marzen.dts
@@ -68,6 +68,10 @@
 	status = "okay";
 };
 
+&extal_clk {
+	clock-frequency = <31250000>;
+};
+
 &pfc {
 	pinctrl-0 = <&scif2_pins &scif4_pins>;
 	pinctrl-names = "default";
-- 
1.8.5.2

[PATCH v3 07/20] ARM: shmobile: marzen: Reference clocks

[Simon Horman]

Reference clocks using a "clocks" property in all nodes corresponding to
devices that require a clock: that is, the lan0 node.

Based on work by Laurent Pinchart for the r8a7790 and r8a7791 SoCs.

Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

---
v3
* New
---
 arch/arm/boot/dts/r8a7779-marzen.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts
index 2c727cd..30f57e9 100644
--- a/arch/arm/boot/dts/r8a7779-marzen.dts
+++ b/arch/arm/boot/dts/r8a7779-marzen.dts
@@ -41,6 +41,7 @@
 		reg = <0x18000000 0x100>;
 		pinctrl-0 = <&lan0_pins>;
 		pinctrl-names = "default";
+		clocks = <&mstp1_clks R8A7779_CLK_ETHER>;
 
 		phy-mode = "mii";
 		interrupt-parent = <&irqpin0>;
-- 
1.8.5.2

[PATCH v3 07/20] ARM: shmobile: marzen: Reference clocks

[Simon Horman]

Reference clocks using a "clocks" property in all nodes corresponding to
devices that require a clock: that is, the lan0 node.

Based on work by Laurent Pinchart for the r8a7790 and r8a7791 SoCs.

Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

---
v3
* New
---
 arch/arm/boot/dts/r8a7779-marzen.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts
index 2c727cd..30f57e9 100644
--- a/arch/arm/boot/dts/r8a7779-marzen.dts
+++ b/arch/arm/boot/dts/r8a7779-marzen.dts
@@ -41,6 +41,7 @@
 		reg = <0x18000000 0x100>;
 		pinctrl-0 = <&lan0_pins>;
 		pinctrl-names = "default";
+		clocks = <&mstp1_clks R8A7779_CLK_ETHER>;
 
 		phy-mode = "mii";
 		interrupt-parent = <&irqpin0>;
-- 
1.8.5.2

[PATCH v3 08/20] ARM: shmobile: r8a7779: Reference clocks

[Simon Horman]

Reference clocks using a "clocks" property in all nodes corresponding to
devices that require a clock.

Based on work by Laurent Pinchart for the r8a7790 and r8a7791 SoC.

Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

---
v3
* Also update the following nodes which are now present
  - hspi{0,1,2}
  - sata: Suggested by Laurent Pinchart
---
 arch/arm/boot/dts/r8a7779.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index 240a03e..7352987 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -166,6 +166,7 @@
 		reg = <0xffc70000 0x1000>;
 		interrupt-parent = <&gic>;
 		interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
 		status = "disabled";
 	};
 
@@ -176,6 +177,7 @@
 		reg = <0xffc71000 0x1000>;
 		interrupt-parent = <&gic>;
 		interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
 		status = "disabled";
 	};
 
@@ -186,6 +188,7 @@
 		reg = <0xffc72000 0x1000>;
 		interrupt-parent = <&gic>;
 		interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
 		status = "disabled";
 	};
 
@@ -196,6 +199,7 @@
 		reg = <0xffc73000 0x1000>;
 		interrupt-parent = <&gic>;
 		interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
 		status = "disabled";
 	};
 
@@ -214,6 +218,7 @@
 		reg = <0xfc600000 0x2000>;
 		interrupt-parent = <&gic>;
 		interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp1_clks R8A7779_CLK_SATA>;
 	};
 
 	sdhi0: sd@ffe4c000 {
@@ -221,6 +226,7 @@
 		reg = <0xffe4c000 0x100>;
 		interrupt-parent = <&gic>;
 		interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
 		cap-sd-highspeed;
 		cap-sdio-irq;
 		status = "disabled";
@@ -231,6 +237,7 @@
 		reg = <0xffe4d000 0x100>;
 		interrupt-parent = <&gic>;
 		interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
 		cap-sd-highspeed;
 		cap-sdio-irq;
 		status = "disabled";
@@ -241,6 +248,7 @@
 		reg = <0xffe4e000 0x100>;
 		interrupt-parent = <&gic>;
 		interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
 		cap-sd-highspeed;
 		cap-sdio-irq;
 		status = "disabled";
@@ -251,6 +259,7 @@
 		reg = <0xffe4f000 0x100>;
 		interrupt-parent = <&gic>;
 		interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
 		cap-sd-highspeed;
 		cap-sdio-irq;
 		status = "disabled";
@@ -261,6 +270,7 @@
 		reg = <0xfffc7000 0x18>;
 		interrupt-controller = <&gic>;
 		interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
 		status = "disabled";
 	};
 
@@ -269,6 +279,7 @@
 		reg = <0xfffc8000 0x18>;
 		interrupt-controller = <&gic>;
 		interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
 		status = "disabled";
 	};
 
@@ -277,6 +288,7 @@
 		reg = <0xfffc6000 0x18>;
 		interrupt-controller = <&gic>;
 		interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
 		status = "disabled";
 	};
 
-- 
1.8.5.2

[PATCH v3 08/20] ARM: shmobile: r8a7779: Reference clocks

[Simon Horman]

Reference clocks using a "clocks" property in all nodes corresponding to
devices that require a clock.

Based on work by Laurent Pinchart for the r8a7790 and r8a7791 SoC.

Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

---
v3
* Also update the following nodes which are now present
  - hspi{0,1,2}
  - sata: Suggested by Laurent Pinchart
---
 arch/arm/boot/dts/r8a7779.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index 240a03e..7352987 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -166,6 +166,7 @@
 		reg = <0xffc70000 0x1000>;
 		interrupt-parent = <&gic>;
 		interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
 		status = "disabled";
 	};
 
@@ -176,6 +177,7 @@
 		reg = <0xffc71000 0x1000>;
 		interrupt-parent = <&gic>;
 		interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
 		status = "disabled";
 	};
 
@@ -186,6 +188,7 @@
 		reg = <0xffc72000 0x1000>;
 		interrupt-parent = <&gic>;
 		interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
 		status = "disabled";
 	};
 
@@ -196,6 +199,7 @@
 		reg = <0xffc73000 0x1000>;
 		interrupt-parent = <&gic>;
 		interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
 		status = "disabled";
 	};
 
@@ -214,6 +218,7 @@
 		reg = <0xfc600000 0x2000>;
 		interrupt-parent = <&gic>;
 		interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp1_clks R8A7779_CLK_SATA>;
 	};
 
 	sdhi0: sd at ffe4c000 {
@@ -221,6 +226,7 @@
 		reg = <0xffe4c000 0x100>;
 		interrupt-parent = <&gic>;
 		interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
 		cap-sd-highspeed;
 		cap-sdio-irq;
 		status = "disabled";
@@ -231,6 +237,7 @@
 		reg = <0xffe4d000 0x100>;
 		interrupt-parent = <&gic>;
 		interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
 		cap-sd-highspeed;
 		cap-sdio-irq;
 		status = "disabled";
@@ -241,6 +248,7 @@
 		reg = <0xffe4e000 0x100>;
 		interrupt-parent = <&gic>;
 		interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
 		cap-sd-highspeed;
 		cap-sdio-irq;
 		status = "disabled";
@@ -251,6 +259,7 @@
 		reg = <0xffe4f000 0x100>;
 		interrupt-parent = <&gic>;
 		interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
 		cap-sd-highspeed;
 		cap-sdio-irq;
 		status = "disabled";
@@ -261,6 +270,7 @@
 		reg = <0xfffc7000 0x18>;
 		interrupt-controller = <&gic>;
 		interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
 		status = "disabled";
 	};
 
@@ -269,6 +279,7 @@
 		reg = <0xfffc8000 0x18>;
 		interrupt-controller = <&gic>;
 		interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
 		status = "disabled";
 	};
 
@@ -277,6 +288,7 @@
 		reg = <0xfffc6000 0x18>;
 		interrupt-controller = <&gic>;
 		interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
 		status = "disabled";
 	};
 
-- 
1.8.5.2

[PATCH v3 09/20] ARM: shmobile: r8a7779: Add helper to read mode pins

[Simon Horman]

Add and use helper to read mode pins.
This will be re-used when moving marzen-reference to
the common clock framework.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/clock-r8a7779.c        | 11 ++---------
 arch/arm/mach-shmobile/include/mach/r8a7779.h |  1 +
 arch/arm/mach-shmobile/setup-r8a7779.c        | 14 ++++++++++++++
 3 files changed, 17 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index 8e403ae..b1a5065 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -25,6 +25,7 @@
 #include <linux/clkdev.h>
 #include <mach/clock.h>
 #include <mach/common.h>
+#include <mach/r8a7779.h>
 
 /*
  *		MD1 = 1			MD1 = 0
@@ -52,9 +53,6 @@
 #define MSTPCR3		IOMEM(0xffc8003c)
 #define MSTPSR1		IOMEM(0xffc80044)
 
-#define MODEMR		0xffcc0020
-
-
 /* ioremap() through clock mapping mandatory to avoid
  * collision with ARM coherent DMA virtual memory range.
  */
@@ -209,14 +207,9 @@ static struct clk_lookup lookups[] = {
 
 void __init r8a7779_clock_init(void)
 {
-	void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
-	u32 mode;
+	u32 mode = r8a7779_read_mode_pins();
 	int k, ret = 0;
 
-	BUG_ON(!modemr);
-	mode = ioread32(modemr);
-	iounmap(modemr);
-
 	if (mode & MD(1)) {
 		plla_clk.rate = 1500000000;
 
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h
index 88eecea..d5ba2d8 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7779.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h
@@ -32,6 +32,7 @@ extern void r8a7779_add_early_devices(void);
 extern void r8a7779_add_standard_devices(void);
 extern void r8a7779_add_standard_devices_dt(void);
 extern void r8a7779_init_late(void);
+extern u32 r8a7779_read_mode_pins(void);
 extern void r8a7779_clock_init(void);
 extern void r8a7779_pinmux_init(void);
 extern void r8a7779_pm_init(void);
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index 8e860b3..f6aeb7f 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -802,6 +802,20 @@ void __init r8a7779_add_standard_devices_dt(void)
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
+#define MODEMR		0xffcc0020
+
+u32 __init r8a7779_read_mode_pins(void)
+{
+	void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
+	u32 mode;
+
+	BUG_ON(!modemr);
+	mode = ioread32(modemr);
+	iounmap(modemr);
+
+	return mode;
+}
+
 static const char *r8a7779_compat_dt[] __initdata = {
 	"renesas,r8a7779",
 	NULL,
-- 
1.8.5.2

[PATCH v3 09/20] ARM: shmobile: r8a7779: Add helper to read mode pins

[Simon Horman]

Add and use helper to read mode pins.
This will be re-used when moving marzen-reference to
the common clock framework.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/clock-r8a7779.c        | 11 ++---------
 arch/arm/mach-shmobile/include/mach/r8a7779.h |  1 +
 arch/arm/mach-shmobile/setup-r8a7779.c        | 14 ++++++++++++++
 3 files changed, 17 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index 8e403ae..b1a5065 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -25,6 +25,7 @@
 #include <linux/clkdev.h>
 #include <mach/clock.h>
 #include <mach/common.h>
+#include <mach/r8a7779.h>
 
 /*
  *		MD1 = 1			MD1 = 0
@@ -52,9 +53,6 @@
 #define MSTPCR3		IOMEM(0xffc8003c)
 #define MSTPSR1		IOMEM(0xffc80044)
 
-#define MODEMR		0xffcc0020
-
-
 /* ioremap() through clock mapping mandatory to avoid
  * collision with ARM coherent DMA virtual memory range.
  */
@@ -209,14 +207,9 @@ static struct clk_lookup lookups[] = {
 
 void __init r8a7779_clock_init(void)
 {
-	void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
-	u32 mode;
+	u32 mode = r8a7779_read_mode_pins();
 	int k, ret = 0;
 
-	BUG_ON(!modemr);
-	mode = ioread32(modemr);
-	iounmap(modemr);
-
 	if (mode & MD(1)) {
 		plla_clk.rate = 1500000000;
 
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h
index 88eecea..d5ba2d8 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7779.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h
@@ -32,6 +32,7 @@ extern void r8a7779_add_early_devices(void);
 extern void r8a7779_add_standard_devices(void);
 extern void r8a7779_add_standard_devices_dt(void);
 extern void r8a7779_init_late(void);
+extern u32 r8a7779_read_mode_pins(void);
 extern void r8a7779_clock_init(void);
 extern void r8a7779_pinmux_init(void);
 extern void r8a7779_pm_init(void);
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index 8e860b3..f6aeb7f 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -802,6 +802,20 @@ void __init r8a7779_add_standard_devices_dt(void)
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
+#define MODEMR		0xffcc0020
+
+u32 __init r8a7779_read_mode_pins(void)
+{
+	void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
+	u32 mode;
+
+	BUG_ON(!modemr);
+	mode = ioread32(modemr);
+	iounmap(modemr);
+
+	return mode;
+}
+
 static const char *r8a7779_compat_dt[] __initdata = {
 	"renesas,r8a7779",
 	NULL,
-- 
1.8.5.2

[PATCH v3 10/20] ARM: shmobile: r8a7779: Move r8a7779_earlytimer_init to clock-r8a7779.c

[Simon Horman]

r8a7779_earlytimer_init() calls r8a7779_clock_init() and
r8a7779_clock_init() is defined in clock-r8a7779.c.

If both CONFIG_COMMON_CLK and CONFIG_ARCH_R8A7779 are enabled,
as will be the case when marzen-reference moves to use
the common clock framework, then setup-r8a7779.c is compiled
but clock-r8a7779.c is not.

As r8a7779_earlytimer_init() is not used by marzen-reference
simply move it to clock-r8a7779.c.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/clock-r8a7779.c | 11 +++++++++++
 arch/arm/mach-shmobile/setup-r8a7779.c | 10 ----------
 2 files changed, 11 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index b1a5065..e4fc7df 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -23,6 +23,7 @@
 #include <linux/io.h>
 #include <linux/sh_clk.h>
 #include <linux/clkdev.h>
+#include <linux/sh_timer.h>
 #include <mach/clock.h>
 #include <mach/common.h>
 #include <mach/r8a7779.h>
@@ -263,3 +264,13 @@ void __init r8a7779_clock_init(void)
 	else
 		panic("failed to setup r8a7779 clocks\n");
 }
+
+/* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
+void __init __weak r8a7779_register_twd(void) { }
+
+void __init r8a7779_earlytimer_init(void)
+{
+	r8a7779_clock_init();
+	r8a7779_register_twd();
+	shmobile_earlytimer_init();
+}
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index f6aeb7f..f28b8c7 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -714,16 +714,6 @@ void __init r8a7779_add_standard_devices(void)
 	r8a7779_register_hpb_dmae();
 }
 
-/* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
-void __init __weak r8a7779_register_twd(void) { }
-
-void __init r8a7779_earlytimer_init(void)
-{
-	r8a7779_clock_init();
-	r8a7779_register_twd();
-	shmobile_earlytimer_init();
-}
-
 void __init r8a7779_add_early_devices(void)
 {
 	early_platform_add_devices(r8a7779_devices_dt,
-- 
1.8.5.2

[PATCH v3 10/20] ARM: shmobile: r8a7779: Move r8a7779_earlytimer_init to clock-r8a7779.c

[Simon Horman]

r8a7779_earlytimer_init() calls r8a7779_clock_init() and
r8a7779_clock_init() is defined in clock-r8a7779.c.

If both CONFIG_COMMON_CLK and CONFIG_ARCH_R8A7779 are enabled,
as will be the case when marzen-reference moves to use
the common clock framework, then setup-r8a7779.c is compiled
but clock-r8a7779.c is not.

As r8a7779_earlytimer_init() is not used by marzen-reference
simply move it to clock-r8a7779.c.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/clock-r8a7779.c | 11 +++++++++++
 arch/arm/mach-shmobile/setup-r8a7779.c | 10 ----------
 2 files changed, 11 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index b1a5065..e4fc7df 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -23,6 +23,7 @@
 #include <linux/io.h>
 #include <linux/sh_clk.h>
 #include <linux/clkdev.h>
+#include <linux/sh_timer.h>
 #include <mach/clock.h>
 #include <mach/common.h>
 #include <mach/r8a7779.h>
@@ -263,3 +264,13 @@ void __init r8a7779_clock_init(void)
 	else
 		panic("failed to setup r8a7779 clocks\n");
 }
+
+/* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
+void __init __weak r8a7779_register_twd(void) { }
+
+void __init r8a7779_earlytimer_init(void)
+{
+	r8a7779_clock_init();
+	r8a7779_register_twd();
+	shmobile_earlytimer_init();
+}
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index f6aeb7f..f28b8c7 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -714,16 +714,6 @@ void __init r8a7779_add_standard_devices(void)
 	r8a7779_register_hpb_dmae();
 }
 
-/* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
-void __init __weak r8a7779_register_twd(void) { }
-
-void __init r8a7779_earlytimer_init(void)
-{
-	r8a7779_clock_init();
-	r8a7779_register_twd();
-	shmobile_earlytimer_init();
-}
-
 void __init r8a7779_add_early_devices(void)
 {
 	early_platform_add_devices(r8a7779_devices_dt,
-- 
1.8.5.2

[PATCH v3 11/20] ARM: shmobile: marzen-reference: Move clock and OF device initialisation into board

[Simon Horman]

Move the clock initialisation and OF device population from
SoC to board code. This is in keeping with the pattern used by Lager.
And the clock portion is part of decoupling clock initialisation
from SoC code in preparation for moving to the common clock framework.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/board-marzen-reference.c | 3 +++
 arch/arm/mach-shmobile/setup-r8a7779.c          | 4 ----
 2 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c b/arch/arm/mach-shmobile/board-marzen-reference.c
index 2773936..c22e5c2 100644
--- a/arch/arm/mach-shmobile/board-marzen-reference.c
+++ b/arch/arm/mach-shmobile/board-marzen-reference.c
@@ -19,6 +19,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 
+#include <linux/of_platform.h>
 #include <mach/r8a7779.h>
 #include <mach/common.h>
 #include <mach/irqs.h>
@@ -27,7 +28,9 @@
 
 static void __init marzen_init(void)
 {
+	r8a7779_clock_init();
 	r8a7779_add_standard_devices_dt();
+	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 	r8a7779_init_irq_extpin_dt(1); /* IRQ1 as individual interrupt */
 }
 
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index f28b8c7..3471a9b 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -784,12 +784,8 @@ void __init r8a7779_init_delay(void)
 
 void __init r8a7779_add_standard_devices_dt(void)
 {
-	/* clocks are setup late during boot in the case of DT */
-	r8a7779_clock_init();
-
 	platform_add_devices(r8a7779_devices_dt,
 			     ARRAY_SIZE(r8a7779_devices_dt));
-	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
 #define MODEMR		0xffcc0020
-- 
1.8.5.2

[PATCH v3 11/20] ARM: shmobile: marzen-reference: Move clock and OF device initialisation into board code

[Simon Horman]

Move the clock initialisation and OF device population from
SoC to board code. This is in keeping with the pattern used by Lager.
And the clock portion is part of decoupling clock initialisation
from SoC code in preparation for moving to the common clock framework.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/board-marzen-reference.c | 3 +++
 arch/arm/mach-shmobile/setup-r8a7779.c          | 4 ----
 2 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c b/arch/arm/mach-shmobile/board-marzen-reference.c
index 2773936..c22e5c2 100644
--- a/arch/arm/mach-shmobile/board-marzen-reference.c
+++ b/arch/arm/mach-shmobile/board-marzen-reference.c
@@ -19,6 +19,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 
+#include <linux/of_platform.h>
 #include <mach/r8a7779.h>
 #include <mach/common.h>
 #include <mach/irqs.h>
@@ -27,7 +28,9 @@
 
 static void __init marzen_init(void)
 {
+	r8a7779_clock_init();
 	r8a7779_add_standard_devices_dt();
+	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 	r8a7779_init_irq_extpin_dt(1); /* IRQ1 as individual interrupt */
 }
 
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index f28b8c7..3471a9b 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -784,12 +784,8 @@ void __init r8a7779_init_delay(void)
 
 void __init r8a7779_add_standard_devices_dt(void)
 {
-	/* clocks are setup late during boot in the case of DT */
-	r8a7779_clock_init();
-
 	platform_add_devices(r8a7779_devices_dt,
 			     ARRAY_SIZE(r8a7779_devices_dt));
-	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
 #define MODEMR		0xffcc0020
-- 
1.8.5.2

[PATCH v3 12/20] ARM: shmobile: r8a7779: Do not include sh_clk.h in r8a7779.h

[Simon Horman]

Do not include sh_clk.h in r8a7779.h as it is not necessary.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/include/mach/r8a7779.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h
index d5ba2d8..757b903 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7779.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h
@@ -1,7 +1,6 @@
 #ifndef __ASM_R8A7779_H__
 #define __ASM_R8A7779_H__
 
-#include <linux/sh_clk.h>
 #include <linux/pm_domain.h>
 #include <mach/pm-rcar.h>
 
-- 
1.8.5.2

[PATCH v3 12/20] ARM: shmobile: r8a7779: Do not include sh_clk.h in r8a7779.h

[Simon Horman]

Do not include sh_clk.h in r8a7779.h as it is not necessary.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/include/mach/r8a7779.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h
index d5ba2d8..757b903 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7779.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h
@@ -1,7 +1,6 @@
 #ifndef __ASM_R8A7779_H__
 #define __ASM_R8A7779_H__
 
-#include <linux/sh_clk.h>
 #include <linux/pm_domain.h>
 #include <mach/pm-rcar.h>
 
-- 
1.8.5.2

[PATCH v3 13/20] ARM: shmobile: r8a7779: Initial multiplatform support

[Simon Horman]

Add Marzen and r8a7779 to CONFIG_SHMOBILE_MULTI. At this
point CCF is not yet supported so you cannot run this code
yet. For CCF support to happen several different components
are needed, and this is one simple portion that moves us
forward. Other patches need to build on top of this one.

Marzen board support exists in 3 flavours:
1) SHMOBILE_MULTI, MACH_MARZEN - board-marzen-reference.c (CCF + DT)
2) SHMOBILE, MACH_MARZEN_REFERENCE - board-marzen-reference.c (DT)
3) SHMOBILE, MACH_MARZEN - board-marzen.c (legacy C code)

When CCF is done then 2) will be removed. When 1) includes same features
as 3) then 3) will be removed.

Based on work for the Koelsch and r8a7791 by Magnus Damm.

Cc: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

---
v3
* Select RENESAS_INTC_IRQPIN
---
 arch/arm/boot/dts/Makefile                      | 3 ++-
 arch/arm/mach-shmobile/Kconfig                  | 9 +++++++++
 arch/arm/mach-shmobile/Makefile                 | 1 +
 arch/arm/mach-shmobile/board-marzen-reference.c | 5 +++++
 4 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 0320303..cac7179 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -263,7 +263,8 @@ dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += emev2-kzm9d.dtb \
 dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb \
 	r7s72100-genmai-reference.dtb \
 	r8a7791-koelsch.dtb \
-	r8a7790-lager.dtb
+	r8a7790-lager.dtb \
+	r8a7779-marzen-reference.dtb
 dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \
 	socfpga_cyclone5_socdk.dtb \
 	socfpga_cyclone5_sockit.dtb \
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index d27bff3..8ba4172 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -23,6 +23,10 @@ if ARCH_SHMOBILE_MULTI
 
 comment "Renesas ARM SoCs System Type"
 
+config ARCH_R8A7779
+	bool "R-Car H1 (R8A77790)"
+	select RENESAS_INTC_IRQPIN
+
 config ARCH_EMEV2
 	bool "Emma Mobile EV2"
 
@@ -53,6 +57,11 @@ config MACH_LAGER
 	depends on ARCH_R8A7790
 	select MICREL_PHY if SH_ETH
 
+config MACH_MARZEN
+	bool "MARZEN board"
+	depends on ARCH_R8A7779
+	select REGULATOR_FIXED_VOLTAGE if REGULATOR
+
 comment "Renesas ARM SoCs System Configuration"
 endif
 
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 4caffc9..b02dac5 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -60,6 +60,7 @@ ifdef CONFIG_ARCH_SHMOBILE_MULTI
 obj-$(CONFIG_MACH_GENMAI)	+= board-genmai-reference.o
 obj-$(CONFIG_MACH_KOELSCH)	+= board-koelsch-reference.o
 obj-$(CONFIG_MACH_LAGER)	+= board-lager-reference.o
+obj-$(CONFIG_MACH_MARZEN)	+= board-marzen-reference.o
 else
 obj-$(CONFIG_MACH_APE6EVM)	+= board-ape6evm.o
 obj-$(CONFIG_MACH_APE6EVM_REFERENCE)	+= board-ape6evm-reference.o
diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c b/arch/arm/mach-shmobile/board-marzen-reference.c
index c22e5c2..d3e8319 100644
--- a/arch/arm/mach-shmobile/board-marzen-reference.c
+++ b/arch/arm/mach-shmobile/board-marzen-reference.c
@@ -19,6 +19,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 
+#include <linux/clk-provider.h>
 #include <linux/of_platform.h>
 #include <mach/r8a7779.h>
 #include <mach/common.h>
@@ -28,7 +29,11 @@
 
 static void __init marzen_init(void)
 {
+#ifdef CONFIG_COMMON_CLK
+	of_clk_init(NULL);
+#else
 	r8a7779_clock_init();
+#endif
 	r8a7779_add_standard_devices_dt();
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 	r8a7779_init_irq_extpin_dt(1); /* IRQ1 as individual interrupt */
-- 
1.8.5.2

[PATCH v3 13/20] ARM: shmobile: r8a7779: Initial multiplatform support

[Simon Horman]

Add Marzen and r8a7779 to CONFIG_SHMOBILE_MULTI. At this
point CCF is not yet supported so you cannot run this code
yet. For CCF support to happen several different components
are needed, and this is one simple portion that moves us
forward. Other patches need to build on top of this one.

Marzen board support exists in 3 flavours:
1) SHMOBILE_MULTI, MACH_MARZEN - board-marzen-reference.c (CCF + DT)
2) SHMOBILE, MACH_MARZEN_REFERENCE - board-marzen-reference.c (DT)
3) SHMOBILE, MACH_MARZEN - board-marzen.c (legacy C code)

When CCF is done then 2) will be removed. When 1) includes same features
as 3) then 3) will be removed.

Based on work for the Koelsch and r8a7791 by Magnus Damm.

Cc: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

---
v3
* Select RENESAS_INTC_IRQPIN
---
 arch/arm/boot/dts/Makefile                      | 3 ++-
 arch/arm/mach-shmobile/Kconfig                  | 9 +++++++++
 arch/arm/mach-shmobile/Makefile                 | 1 +
 arch/arm/mach-shmobile/board-marzen-reference.c | 5 +++++
 4 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 0320303..cac7179 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -263,7 +263,8 @@ dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += emev2-kzm9d.dtb \
 dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb \
 	r7s72100-genmai-reference.dtb \
 	r8a7791-koelsch.dtb \
-	r8a7790-lager.dtb
+	r8a7790-lager.dtb \
+	r8a7779-marzen-reference.dtb
 dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \
 	socfpga_cyclone5_socdk.dtb \
 	socfpga_cyclone5_sockit.dtb \
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index d27bff3..8ba4172 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -23,6 +23,10 @@ if ARCH_SHMOBILE_MULTI
 
 comment "Renesas ARM SoCs System Type"
 
+config ARCH_R8A7779
+	bool "R-Car H1 (R8A77790)"
+	select RENESAS_INTC_IRQPIN
+
 config ARCH_EMEV2
 	bool "Emma Mobile EV2"
 
@@ -53,6 +57,11 @@ config MACH_LAGER
 	depends on ARCH_R8A7790
 	select MICREL_PHY if SH_ETH
 
+config MACH_MARZEN
+	bool "MARZEN board"
+	depends on ARCH_R8A7779
+	select REGULATOR_FIXED_VOLTAGE if REGULATOR
+
 comment "Renesas ARM SoCs System Configuration"
 endif
 
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 4caffc9..b02dac5 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -60,6 +60,7 @@ ifdef CONFIG_ARCH_SHMOBILE_MULTI
 obj-$(CONFIG_MACH_GENMAI)	+= board-genmai-reference.o
 obj-$(CONFIG_MACH_KOELSCH)	+= board-koelsch-reference.o
 obj-$(CONFIG_MACH_LAGER)	+= board-lager-reference.o
+obj-$(CONFIG_MACH_MARZEN)	+= board-marzen-reference.o
 else
 obj-$(CONFIG_MACH_APE6EVM)	+= board-ape6evm.o
 obj-$(CONFIG_MACH_APE6EVM_REFERENCE)	+= board-ape6evm-reference.o
diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c b/arch/arm/mach-shmobile/board-marzen-reference.c
index c22e5c2..d3e8319 100644
--- a/arch/arm/mach-shmobile/board-marzen-reference.c
+++ b/arch/arm/mach-shmobile/board-marzen-reference.c
@@ -19,6 +19,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 
+#include <linux/clk-provider.h>
 #include <linux/of_platform.h>
 #include <mach/r8a7779.h>
 #include <mach/common.h>
@@ -28,7 +29,11 @@
 
 static void __init marzen_init(void)
 {
+#ifdef CONFIG_COMMON_CLK
+	of_clk_init(NULL);
+#else
 	r8a7779_clock_init();
+#endif
 	r8a7779_add_standard_devices_dt();
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 	r8a7779_init_irq_extpin_dt(1); /* IRQ1 as individual interrupt */
-- 
1.8.5.2

[PATCH v3 14/20] ARM: shmobile: marzen-reference: Initialize CPG device

[Simon Horman]

On multiplatform kernels clocks are handled by the CCF CPG driver. It
must be explicitly initialized by a call to r8a7779_clocks_init() with
the value of the boot mode pins.

Based on similar work for the Koelsch board by Laurent Pinchart.

Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/board-marzen-reference.c | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c b/arch/arm/mach-shmobile/board-marzen-reference.c
index d3e8319..e261431 100644
--- a/arch/arm/mach-shmobile/board-marzen-reference.c
+++ b/arch/arm/mach-shmobile/board-marzen-reference.c
@@ -19,7 +19,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 
-#include <linux/clk-provider.h>
+#include <linux/clk/shmobile.h>
+#include <linux/clocksource.h>
 #include <linux/of_platform.h>
 #include <mach/r8a7779.h>
 #include <mach/common.h>
@@ -27,11 +28,17 @@
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 
-static void __init marzen_init(void)
+static void __init marzen_init_timer(void)
 {
 #ifdef CONFIG_COMMON_CLK
-	of_clk_init(NULL);
-#else
+	r8a7779_clocks_init(r8a7779_read_mode_pins());
+#endif
+	clocksource_of_init();
+}
+
+static void __init marzen_init(void)
+{
+#ifndef CONFIG_COMMON_CLK
 	r8a7779_clock_init();
 #endif
 	r8a7779_add_standard_devices_dt();
@@ -48,6 +55,7 @@ DT_MACHINE_START(MARZEN, "marzen")
 	.smp		= smp_ops(r8a7779_smp_ops),
 	.map_io		= r8a7779_map_io,
 	.init_early	= r8a7779_init_delay,
+	.init_time	= marzen_init_timer,
 	.nr_irqs	= NR_IRQS_LEGACY,
 	.init_irq	= r8a7779_init_irq_dt,
 	.init_machine	= marzen_init,
-- 
1.8.5.2

[PATCH v3 14/20] ARM: shmobile: marzen-reference: Initialize CPG device

[Simon Horman]

On multiplatform kernels clocks are handled by the CCF CPG driver. It
must be explicitly initialized by a call to r8a7779_clocks_init() with
the value of the boot mode pins.

Based on similar work for the Koelsch board by Laurent Pinchart.

Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/board-marzen-reference.c | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c b/arch/arm/mach-shmobile/board-marzen-reference.c
index d3e8319..e261431 100644
--- a/arch/arm/mach-shmobile/board-marzen-reference.c
+++ b/arch/arm/mach-shmobile/board-marzen-reference.c
@@ -19,7 +19,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 
-#include <linux/clk-provider.h>
+#include <linux/clk/shmobile.h>
+#include <linux/clocksource.h>
 #include <linux/of_platform.h>
 #include <mach/r8a7779.h>
 #include <mach/common.h>
@@ -27,11 +28,17 @@
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 
-static void __init marzen_init(void)
+static void __init marzen_init_timer(void)
 {
 #ifdef CONFIG_COMMON_CLK
-	of_clk_init(NULL);
-#else
+	r8a7779_clocks_init(r8a7779_read_mode_pins());
+#endif
+	clocksource_of_init();
+}
+
+static void __init marzen_init(void)
+{
+#ifndef CONFIG_COMMON_CLK
 	r8a7779_clock_init();
 #endif
 	r8a7779_add_standard_devices_dt();
@@ -48,6 +55,7 @@ DT_MACHINE_START(MARZEN, "marzen")
 	.smp		= smp_ops(r8a7779_smp_ops),
 	.map_io		= r8a7779_map_io,
 	.init_early	= r8a7779_init_delay,
+	.init_time	= marzen_init_timer,
 	.nr_irqs	= NR_IRQS_LEGACY,
 	.init_irq	= r8a7779_init_irq_dt,
 	.init_machine	= marzen_init,
-- 
1.8.5.2

[PATCH v3 15/20] ARM: shmobile: marzen-reference: Instantiate clkdevs for SCIF and TMU

[Simon Horman]

Now that the common clock framework is supported, the clock lookup
entries in clock-r8a7779.c are not registered anymore. Devices must
instead reference their clocks in the device tree. However, SCIF and CMT
devices are still instantiated through platform code, and thus need a
clock lookup entry.

Retrieve the SCIF and CMT clock entries by name and register clkdevs for
the corresponding devices. This will be removed when the SCIF and CMT
devices will be instantiated from the device tree.

Based on work for the Koelsch board by Laurent Pinchart.

Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

---
v3
* Initialise TMU clocks instead of CMT clocks
  - It is TMU that Marzen uses as a clocksource
* Refactor clock initialisation hack as per more recent mainline
  code for Koelsch
* Use IS_ERR to check the return value of clk_get()
---
 arch/arm/mach-shmobile/board-marzen-reference.c | 31 ++++++++++++++++++++++++-
 1 file changed, 30 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c b/arch/arm/mach-shmobile/board-marzen-reference.c
index e261431..a5974d2 100644
--- a/arch/arm/mach-shmobile/board-marzen-reference.c
+++ b/arch/arm/mach-shmobile/board-marzen-reference.c
@@ -19,7 +19,9 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 
+#include <linux/clk.h>
 #include <linux/clk/shmobile.h>
+#include <linux/clkdev.h>
 #include <linux/clocksource.h>
 #include <linux/of_platform.h>
 #include <mach/r8a7779.h>
@@ -38,7 +40,34 @@ static void __init marzen_init_timer(void)
 
 static void __init marzen_init(void)
 {
-#ifndef CONFIG_COMMON_CLK
+#ifdef CONFIG_COMMON_CLK
+	static const struct clk_name {
+		const char *clk;
+		const char *con_id;
+		const char *dev_id;
+	} clk_names[] = {
+		{ "scif0", NULL, "sh-sci.0" },
+		{ "scif1", NULL, "sh-sci.1" },
+		{ "scif2", NULL, "sh-sci.2" },
+		{ "scif3", NULL, "sh-sci.3" },
+		{ "scif4", NULL, "sh-sci.4" },
+		{ "scif5", NULL, "sh-sci.5" },
+		{ "tmu00", NULL, "sh_tmu.0" },
+		{ "tmu01", NULL, "sh_tmu.1" },
+		{ "tmu02", NULL, "sh_tmu.2" },
+	};
+	struct clk *clk;
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(clk_names); ++i) {
+		clk = clk_get(NULL, clk_names[i].clk);
+		if (!IS_ERR(clk)) {
+			clk_register_clkdev(clk, clk_names[i].con_id,
+					    clk_names[i].dev_id);
+			clk_put(clk);
+		}
+	}
+#else
 	r8a7779_clock_init();
 #endif
 	r8a7779_add_standard_devices_dt();
-- 
1.8.5.2

[PATCH v3 15/20] ARM: shmobile: marzen-reference: Instantiate clkdevs for SCIF and TMU

[Simon Horman]

Now that the common clock framework is supported, the clock lookup
entries in clock-r8a7779.c are not registered anymore. Devices must
instead reference their clocks in the device tree. However, SCIF and CMT
devices are still instantiated through platform code, and thus need a
clock lookup entry.

Retrieve the SCIF and CMT clock entries by name and register clkdevs for
the corresponding devices. This will be removed when the SCIF and CMT
devices will be instantiated from the device tree.

Based on work for the Koelsch board by Laurent Pinchart.

Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

---
v3
* Initialise TMU clocks instead of CMT clocks
  - It is TMU that Marzen uses as a clocksource
* Refactor clock initialisation hack as per more recent mainline
  code for Koelsch
* Use IS_ERR to check the return value of clk_get()
---
 arch/arm/mach-shmobile/board-marzen-reference.c | 31 ++++++++++++++++++++++++-
 1 file changed, 30 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c b/arch/arm/mach-shmobile/board-marzen-reference.c
index e261431..a5974d2 100644
--- a/arch/arm/mach-shmobile/board-marzen-reference.c
+++ b/arch/arm/mach-shmobile/board-marzen-reference.c
@@ -19,7 +19,9 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 
+#include <linux/clk.h>
 #include <linux/clk/shmobile.h>
+#include <linux/clkdev.h>
 #include <linux/clocksource.h>
 #include <linux/of_platform.h>
 #include <mach/r8a7779.h>
@@ -38,7 +40,34 @@ static void __init marzen_init_timer(void)
 
 static void __init marzen_init(void)
 {
-#ifndef CONFIG_COMMON_CLK
+#ifdef CONFIG_COMMON_CLK
+	static const struct clk_name {
+		const char *clk;
+		const char *con_id;
+		const char *dev_id;
+	} clk_names[] = {
+		{ "scif0", NULL, "sh-sci.0" },
+		{ "scif1", NULL, "sh-sci.1" },
+		{ "scif2", NULL, "sh-sci.2" },
+		{ "scif3", NULL, "sh-sci.3" },
+		{ "scif4", NULL, "sh-sci.4" },
+		{ "scif5", NULL, "sh-sci.5" },
+		{ "tmu00", NULL, "sh_tmu.0" },
+		{ "tmu01", NULL, "sh_tmu.1" },
+		{ "tmu02", NULL, "sh_tmu.2" },
+	};
+	struct clk *clk;
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(clk_names); ++i) {
+		clk = clk_get(NULL, clk_names[i].clk);
+		if (!IS_ERR(clk)) {
+			clk_register_clkdev(clk, clk_names[i].con_id,
+					    clk_names[i].dev_id);
+			clk_put(clk);
+		}
+	}
+#else
 	r8a7779_clock_init();
 #endif
 	r8a7779_add_standard_devices_dt();
-- 
1.8.5.2

[PATCH v3 16/20] ARM: shmobile: marzen: Add to shmobile defconfig

[Simon Horman]

Add marzen to shmobile defconfig now that it supports multiplatform

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/configs/shmobile_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig
index 83b0725..23cb9ab 100644
--- a/arch/arm/configs/shmobile_defconfig
+++ b/arch/arm/configs/shmobile_defconfig
@@ -9,11 +9,13 @@ CONFIG_EMBEDDED=y
 CONFIG_PERF_EVENTS=y
 CONFIG_SLAB=y
 CONFIG_ARCH_SHMOBILE_MULTI=y
+CONFIG_ARCH_R8A7779=y
 CONFIG_ARCH_EMEV2=y
 CONFIG_ARCH_R8A7790=y
 CONFIG_ARCH_R8A7791=y
 CONFIG_MACH_KOELSCH=y
 CONFIG_MACH_LAGER=y
+CONFIG_MACH_MARZEN=y
 # CONFIG_SWP_EMULATE is not set
 CONFIG_CPU_BPREDICT_DISABLE=y
 CONFIG_PL310_ERRATA_588369=y
-- 
1.8.5.2

[PATCH v3 16/20] ARM: shmobile: marzen: Add to shmobile defconfig

[Simon Horman]

Add marzen to shmobile defconfig now that it supports multiplatform

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/configs/shmobile_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig
index 83b0725..23cb9ab 100644
--- a/arch/arm/configs/shmobile_defconfig
+++ b/arch/arm/configs/shmobile_defconfig
@@ -9,11 +9,13 @@ CONFIG_EMBEDDED=y
 CONFIG_PERF_EVENTS=y
 CONFIG_SLAB=y
 CONFIG_ARCH_SHMOBILE_MULTI=y
+CONFIG_ARCH_R8A7779=y
 CONFIG_ARCH_EMEV2=y
 CONFIG_ARCH_R8A7790=y
 CONFIG_ARCH_R8A7791=y
 CONFIG_MACH_KOELSCH=y
 CONFIG_MACH_LAGER=y
+CONFIG_MACH_MARZEN=y
 # CONFIG_SWP_EMULATE is not set
 CONFIG_CPU_BPREDICT_DISABLE=y
 CONFIG_PL310_ERRATA_588369=y
-- 
1.8.5.2

[PATCH v3 17/20] ARM: shmobile: Remove non-multiplatform Marzen reference support

[Simon Horman]

Now that r8a7779 has CCF support remove the legacy Marzen reference
Kconfig bits CONFIG_MACH_MARZEN_REFERENCE for the non-multiplatform
case.

Starting from this commit Marzen board support is always enabled via
CONFIG_MACH_MARZEN, and CONFIG_ARCH_MULTIPLATFORM is used to select
between board-marzen.c and board-marzen-reference.c

The file board-marzen-reference.c can no longer be used together with
the legacy sh-clk clock framework, instead CCF is used.

Based on work for the Koelsch board by Laurent Pinchart.

Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/boot/dts/Makefile           |  1 -
 arch/arm/mach-shmobile/Kconfig       | 13 -------------
 arch/arm/mach-shmobile/Makefile      |  1 -
 arch/arm/mach-shmobile/Makefile.boot |  1 -
 4 files changed, 16 deletions(-)

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index cac7179..ad09142 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -252,7 +252,6 @@ dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += emev2-kzm9d.dtb \
 	r8a7778-bockw-reference.dtb \
 	r8a7740-armadillo800eva-reference.dtb \
 	r8a7779-marzen.dtb \
-	r8a7779-marzen-reference.dtb \
 	r8a7791-koelsch.dtb \
 	r8a7790-lager.dtb \
 	sh73a0-kzm9g.dtb \
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 8ba4172..a141fb4 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -258,19 +258,6 @@ config MACH_MARZEN
 	select REGULATOR_FIXED_VOLTAGE if REGULATOR
 	select USE_OF
 
-config MACH_MARZEN_REFERENCE
-	bool "MARZEN board - Reference Device Tree Implementation"
-	depends on ARCH_R8A7779
-	select ARCH_REQUIRE_GPIOLIB
-	select REGULATOR_FIXED_VOLTAGE if REGULATOR
-	select USE_OF
-	---help---
-	   Use reference implementation of Marzen board support
-	   which makes use of device tree at the expense
-	   of not supporting a number of devices.
-
-	   This is intended to aid developers
-
 config MACH_LAGER
 	bool "Lager board"
 	depends on ARCH_R8A7790
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index b02dac5..0aaceef 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -70,7 +70,6 @@ obj-$(CONFIG_MACH_BOCKW_REFERENCE)	+= board-bockw-reference.o
 obj-$(CONFIG_MACH_GENMAI)	+= board-genmai.o
 obj-$(CONFIG_MACH_GENMAI_REFERENCE)	+= board-genmai-reference.o
 obj-$(CONFIG_MACH_MARZEN)	+= board-marzen.o
-obj-$(CONFIG_MACH_MARZEN_REFERENCE)	+= board-marzen-reference.o
 obj-$(CONFIG_MACH_LAGER)	+= board-lager.o
 obj-$(CONFIG_MACH_ARMADILLO800EVA)	+= board-armadillo800eva.o
 obj-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE)	+= board-armadillo800eva-reference.o
diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot
index 99455ec..4200b94 100644
--- a/arch/arm/mach-shmobile/Makefile.boot
+++ b/arch/arm/mach-shmobile/Makefile.boot
@@ -14,7 +14,6 @@ loadaddr-$(CONFIG_MACH_KZM9G_REFERENCE) += 0x41008000
 loadaddr-$(CONFIG_MACH_LAGER) += 0x40008000
 loadaddr-$(CONFIG_MACH_MACKEREL) += 0x40008000
 loadaddr-$(CONFIG_MACH_MARZEN) += 0x60008000
-loadaddr-$(CONFIG_MACH_MARZEN_REFERENCE) += 0x60008000
 
 __ZRELADDR	:= $(sort $(loadaddr-y))
    zreladdr-y   += $(__ZRELADDR)
-- 
1.8.5.2

[PATCH v3 17/20] ARM: shmobile: Remove non-multiplatform Marzen reference support

[Simon Horman]

Now that r8a7779 has CCF support remove the legacy Marzen reference
Kconfig bits CONFIG_MACH_MARZEN_REFERENCE for the non-multiplatform
case.

Starting from this commit Marzen board support is always enabled via
CONFIG_MACH_MARZEN, and CONFIG_ARCH_MULTIPLATFORM is used to select
between board-marzen.c and board-marzen-reference.c

The file board-marzen-reference.c can no longer be used together with
the legacy sh-clk clock framework, instead CCF is used.

Based on work for the Koelsch board by Laurent Pinchart.

Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/boot/dts/Makefile           |  1 -
 arch/arm/mach-shmobile/Kconfig       | 13 -------------
 arch/arm/mach-shmobile/Makefile      |  1 -
 arch/arm/mach-shmobile/Makefile.boot |  1 -
 4 files changed, 16 deletions(-)

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index cac7179..ad09142 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -252,7 +252,6 @@ dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += emev2-kzm9d.dtb \
 	r8a7778-bockw-reference.dtb \
 	r8a7740-armadillo800eva-reference.dtb \
 	r8a7779-marzen.dtb \
-	r8a7779-marzen-reference.dtb \
 	r8a7791-koelsch.dtb \
 	r8a7790-lager.dtb \
 	sh73a0-kzm9g.dtb \
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 8ba4172..a141fb4 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -258,19 +258,6 @@ config MACH_MARZEN
 	select REGULATOR_FIXED_VOLTAGE if REGULATOR
 	select USE_OF
 
-config MACH_MARZEN_REFERENCE
-	bool "MARZEN board - Reference Device Tree Implementation"
-	depends on ARCH_R8A7779
-	select ARCH_REQUIRE_GPIOLIB
-	select REGULATOR_FIXED_VOLTAGE if REGULATOR
-	select USE_OF
-	---help---
-	   Use reference implementation of Marzen board support
-	   which makes use of device tree at the expense
-	   of not supporting a number of devices.
-
-	   This is intended to aid developers
-
 config MACH_LAGER
 	bool "Lager board"
 	depends on ARCH_R8A7790
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index b02dac5..0aaceef 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -70,7 +70,6 @@ obj-$(CONFIG_MACH_BOCKW_REFERENCE)	+= board-bockw-reference.o
 obj-$(CONFIG_MACH_GENMAI)	+= board-genmai.o
 obj-$(CONFIG_MACH_GENMAI_REFERENCE)	+= board-genmai-reference.o
 obj-$(CONFIG_MACH_MARZEN)	+= board-marzen.o
-obj-$(CONFIG_MACH_MARZEN_REFERENCE)	+= board-marzen-reference.o
 obj-$(CONFIG_MACH_LAGER)	+= board-lager.o
 obj-$(CONFIG_MACH_ARMADILLO800EVA)	+= board-armadillo800eva.o
 obj-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE)	+= board-armadillo800eva-reference.o
diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot
index 99455ec..4200b94 100644
--- a/arch/arm/mach-shmobile/Makefile.boot
+++ b/arch/arm/mach-shmobile/Makefile.boot
@@ -14,7 +14,6 @@ loadaddr-$(CONFIG_MACH_KZM9G_REFERENCE) += 0x41008000
 loadaddr-$(CONFIG_MACH_LAGER) += 0x40008000
 loadaddr-$(CONFIG_MACH_MACKEREL) += 0x40008000
 loadaddr-$(CONFIG_MACH_MARZEN) += 0x60008000
-loadaddr-$(CONFIG_MACH_MARZEN_REFERENCE) += 0x60008000
 
 __ZRELADDR	:= $(sort $(loadaddr-y))
    zreladdr-y   += $(__ZRELADDR)
-- 
1.8.5.2

[PATCH v3 18/20] ARM: shmobile: Let Marzen multiplatform boot with Marzen DTB

[Simon Horman]

Let the multiplatform Marzen support boot with the legacy DTS for
Marzen as well as the Marzen reference DTS.

Based on work for the Koelsch board by Laurent Pinchart.

Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/boot/dts/Makefile                      | 2 +-
 arch/arm/mach-shmobile/board-marzen-reference.c | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index ad09142..989f272 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -263,7 +263,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb \
 	r7s72100-genmai-reference.dtb \
 	r8a7791-koelsch.dtb \
 	r8a7790-lager.dtb \
-	r8a7779-marzen-reference.dtb
+	r8a7779-marzen.dtb
 dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \
 	socfpga_cyclone5_socdk.dtb \
 	socfpga_cyclone5_sockit.dtb \
diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c b/arch/arm/mach-shmobile/board-marzen-reference.c
index a5974d2..20cf1dc 100644
--- a/arch/arm/mach-shmobile/board-marzen-reference.c
+++ b/arch/arm/mach-shmobile/board-marzen-reference.c
@@ -76,6 +76,7 @@ static void __init marzen_init(void)
 }
 
 static const char *marzen_boards_compat_dt[] __initdata = {
+	"renesas,marzen",
 	"renesas,marzen-reference",
 	NULL,
 };
-- 
1.8.5.2

[PATCH v3 18/20] ARM: shmobile: Let Marzen multiplatform boot with Marzen DTB

[Simon Horman]

Let the multiplatform Marzen support boot with the legacy DTS for
Marzen as well as the Marzen reference DTS.

Based on work for the Koelsch board by Laurent Pinchart.

Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/boot/dts/Makefile                      | 2 +-
 arch/arm/mach-shmobile/board-marzen-reference.c | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index ad09142..989f272 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -263,7 +263,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb \
 	r7s72100-genmai-reference.dtb \
 	r8a7791-koelsch.dtb \
 	r8a7790-lager.dtb \
-	r8a7779-marzen-reference.dtb
+	r8a7779-marzen.dtb
 dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \
 	socfpga_cyclone5_socdk.dtb \
 	socfpga_cyclone5_sockit.dtb \
diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c b/arch/arm/mach-shmobile/board-marzen-reference.c
index a5974d2..20cf1dc 100644
--- a/arch/arm/mach-shmobile/board-marzen-reference.c
+++ b/arch/arm/mach-shmobile/board-marzen-reference.c
@@ -76,6 +76,7 @@ static void __init marzen_init(void)
 }
 
 static const char *marzen_boards_compat_dt[] __initdata = {
+	"renesas,marzen",
 	"renesas,marzen-reference",
 	NULL,
 };
-- 
1.8.5.2

[PATCH v3 19/20] ARM: shmobile: Remove Marzen reference DTS

[Simon Horman]

Now that the DTS file r8a7790-marzen.dts can be used with
board-marzen.c and board-marzen-reference.c, proceed with removing
r8a7790-marzen-reference.dts.

Based on work for the Koelsch board by Laurent Pinchart.

Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/boot/dts/r8a7779-marzen-reference.dts | 120 -------------------------
 1 file changed, 120 deletions(-)
 delete mode 100644 arch/arm/boot/dts/r8a7779-marzen-reference.dts

diff --git a/arch/arm/boot/dts/r8a7779-marzen-reference.dts b/arch/arm/boot/dts/r8a7779-marzen-reference.dts
deleted file mode 100644
index 76f5eef..0000000
--- a/arch/arm/boot/dts/r8a7779-marzen-reference.dts
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * Reference Device Tree Source for the Marzen board
- *
- * Copyright (C) 2013 Renesas Solutions Corp.
- * Copyright (C) 2013 Simon Horman
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-/dts-v1/;
-#include "r8a7779.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/ {
-	model = "marzen";
-	compatible = "renesas,marzen-reference", "renesas,r8a7779";
-
-	chosen {
-		bootargs = "console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel root=/dev/nfs ip=on rw";
-	};
-
-	memory {
-		device_type = "memory";
-		reg = <0x60000000 0x40000000>;
-	};
-
-	fixedregulator3v3: fixedregulator@0 {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-3.3V";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	lan0@18000000 {
-		compatible = "smsc,lan9220", "smsc,lan9115";
-		reg = <0x18000000 0x100>;
-		pinctrl-0 = <&lan0_pins>;
-		pinctrl-names = "default";
-
-		phy-mode = "mii";
-		interrupt-parent = <&irqpin0>;
-		interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
-		reg-io-width = <4>;
-		vddvario-supply = <&fixedregulator3v3>;
-		vdd33a-supply = <&fixedregulator3v3>;
-	};
-
-	leds {
-		compatible = "gpio-leds";
-		led2 {
-			gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
-		};
-		led3 {
-			gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
-		};
-		led4 {
-			gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;
-		};
-	};
-};
-
-&irqpin0 {
-	status = "okay";
-};
-
-&pfc {
-	pinctrl-0 = <&scif2_pins &scif4_pins>;
-	pinctrl-names = "default";
-
-	lan0_pins: lan0 {
-		intc {
-			renesas,groups = "intc_irq1_b";
-			renesas,function = "intc";
-		};
-		lbsc {
-			renesas,groups = "lbsc_ex_cs0";
-			renesas,function = "lbsc";
-		};
-	};
-
-	scif2_pins: serial2 {
-		renesas,groups = "scif2_data_c";
-		renesas,function = "scif2";
-	};
-
-	scif4_pins: serial4 {
-		renesas,groups = "scif4_data";
-		renesas,function = "scif4";
-	};
-
-	sdhi0_pins: sd0 {
-		renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
-		renesas,function = "sdhi0";
-	};
-
-	hspi0_pins: hspi0 {
-		renesas,groups = "hspi0";
-		renesas,function = "hspi0";
-	};
-};
-
-&sdhi0 {
-	pinctrl-0 = <&sdhi0_pins>;
-	pinctrl-names = "default";
-
-	vmmc-supply = <&fixedregulator3v3>;
-	bus-width = <4>;
-	status = "okay";
-};
-
-&hspi0 {
-	pinctrl-0 = <&hspi0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-- 
1.8.5.2

[PATCH v3 19/20] ARM: shmobile: Remove Marzen reference DTS

[Simon Horman]

Now that the DTS file r8a7790-marzen.dts can be used with
board-marzen.c and board-marzen-reference.c, proceed with removing
r8a7790-marzen-reference.dts.

Based on work for the Koelsch board by Laurent Pinchart.

Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/boot/dts/r8a7779-marzen-reference.dts | 120 -------------------------
 1 file changed, 120 deletions(-)
 delete mode 100644 arch/arm/boot/dts/r8a7779-marzen-reference.dts

diff --git a/arch/arm/boot/dts/r8a7779-marzen-reference.dts b/arch/arm/boot/dts/r8a7779-marzen-reference.dts
deleted file mode 100644
index 76f5eef..0000000
--- a/arch/arm/boot/dts/r8a7779-marzen-reference.dts
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * Reference Device Tree Source for the Marzen board
- *
- * Copyright (C) 2013 Renesas Solutions Corp.
- * Copyright (C) 2013 Simon Horman
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-/dts-v1/;
-#include "r8a7779.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/ {
-	model = "marzen";
-	compatible = "renesas,marzen-reference", "renesas,r8a7779";
-
-	chosen {
-		bootargs = "console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel root=/dev/nfs ip=on rw";
-	};
-
-	memory {
-		device_type = "memory";
-		reg = <0x60000000 0x40000000>;
-	};
-
-	fixedregulator3v3: fixedregulator at 0 {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-3.3V";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	lan0 at 18000000 {
-		compatible = "smsc,lan9220", "smsc,lan9115";
-		reg = <0x18000000 0x100>;
-		pinctrl-0 = <&lan0_pins>;
-		pinctrl-names = "default";
-
-		phy-mode = "mii";
-		interrupt-parent = <&irqpin0>;
-		interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
-		reg-io-width = <4>;
-		vddvario-supply = <&fixedregulator3v3>;
-		vdd33a-supply = <&fixedregulator3v3>;
-	};
-
-	leds {
-		compatible = "gpio-leds";
-		led2 {
-			gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
-		};
-		led3 {
-			gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
-		};
-		led4 {
-			gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;
-		};
-	};
-};
-
-&irqpin0 {
-	status = "okay";
-};
-
-&pfc {
-	pinctrl-0 = <&scif2_pins &scif4_pins>;
-	pinctrl-names = "default";
-
-	lan0_pins: lan0 {
-		intc {
-			renesas,groups = "intc_irq1_b";
-			renesas,function = "intc";
-		};
-		lbsc {
-			renesas,groups = "lbsc_ex_cs0";
-			renesas,function = "lbsc";
-		};
-	};
-
-	scif2_pins: serial2 {
-		renesas,groups = "scif2_data_c";
-		renesas,function = "scif2";
-	};
-
-	scif4_pins: serial4 {
-		renesas,groups = "scif4_data";
-		renesas,function = "scif4";
-	};
-
-	sdhi0_pins: sd0 {
-		renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
-		renesas,function = "sdhi0";
-	};
-
-	hspi0_pins: hspi0 {
-		renesas,groups = "hspi0";
-		renesas,function = "hspi0";
-	};
-};
-
-&sdhi0 {
-	pinctrl-0 = <&sdhi0_pins>;
-	pinctrl-names = "default";
-
-	vmmc-supply = <&fixedregulator3v3>;
-	bus-width = <4>;
-	status = "okay";
-};
-
-&hspi0 {
-	pinctrl-0 = <&hspi0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-- 
1.8.5.2

[PATCH v3 20/20] ARM: shmobile: marzen-reference: Remove legacy clock support

[Simon Horman]

Marzen DT reference is these now only built for multiplatform
which means that CCF comes with the package. Remove unused legacy
code ifdefs to clean up the code.

Based on similar work for the Koelsch board by Magnus Damm.

Cc: Magnus Damm <damm@opensource.se>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/board-marzen-reference.c | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c b/arch/arm/mach-shmobile/board-marzen-reference.c
index 20cf1dc..0b2e7c4 100644
--- a/arch/arm/mach-shmobile/board-marzen-reference.c
+++ b/arch/arm/mach-shmobile/board-marzen-reference.c
@@ -32,15 +32,12 @@
 
 static void __init marzen_init_timer(void)
 {
-#ifdef CONFIG_COMMON_CLK
 	r8a7779_clocks_init(r8a7779_read_mode_pins());
-#endif
 	clocksource_of_init();
 }
 
 static void __init marzen_init(void)
 {
-#ifdef CONFIG_COMMON_CLK
 	static const struct clk_name {
 		const char *clk;
 		const char *con_id;
@@ -67,9 +64,6 @@ static void __init marzen_init(void)
 			clk_put(clk);
 		}
 	}
-#else
-	r8a7779_clock_init();
-#endif
 	r8a7779_add_standard_devices_dt();
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 	r8a7779_init_irq_extpin_dt(1); /* IRQ1 as individual interrupt */
-- 
1.8.5.2

[PATCH v3 20/20] ARM: shmobile: marzen-reference: Remove legacy clock support

[Simon Horman]

Marzen DT reference is these now only built for multiplatform
which means that CCF comes with the package. Remove unused legacy
code ifdefs to clean up the code.

Based on similar work for the Koelsch board by Magnus Damm.

Cc: Magnus Damm <damm@opensource.se>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/board-marzen-reference.c | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c b/arch/arm/mach-shmobile/board-marzen-reference.c
index 20cf1dc..0b2e7c4 100644
--- a/arch/arm/mach-shmobile/board-marzen-reference.c
+++ b/arch/arm/mach-shmobile/board-marzen-reference.c
@@ -32,15 +32,12 @@
 
 static void __init marzen_init_timer(void)
 {
-#ifdef CONFIG_COMMON_CLK
 	r8a7779_clocks_init(r8a7779_read_mode_pins());
-#endif
 	clocksource_of_init();
 }
 
 static void __init marzen_init(void)
 {
-#ifdef CONFIG_COMMON_CLK
 	static const struct clk_name {
 		const char *clk;
 		const char *con_id;
@@ -67,9 +64,6 @@ static void __init marzen_init(void)
 			clk_put(clk);
 		}
 	}
-#else
-	r8a7779_clock_init();
-#endif
 	r8a7779_add_standard_devices_dt();
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 	r8a7779_init_irq_extpin_dt(1); /* IRQ1 as individual interrupt */
-- 
1.8.5.2

Re: [PATCH v3 01/20] clk: shmobile: r8a7779: Add clocks support

[Geert Uytterhoeven]

On Wed, Feb 26, 2014 at 8:33 AM, Simon Horman
<horms+renesas@verge.net.au> wrote:
> +++ b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
> @@ -0,0 +1,26 @@
> +* Renesas R8A7779 Clock Pulse Generator (CPG)
> +
> +The CPG generates core clocks for the R8A7779. It includes one PLL and
> +and several fixed ratio dividers

Double "and"

> +++ b/drivers/clk/shmobile/clk-r8a7779.c

> +/*
> + *             MD1 = 1                 MD1 = 0
> + *             (PLLA = 1500)           (PLLA = 1600)
> + *             (MHz)                   (MHz)
> + *------------------------------------------------+--------------------
> + * clkz                1000   (2/3)            800   (1/2)
> + * clkzs        250   (1/6)            200   (1/8)
> + * clki                 750   (1/2)            800   (1/2)
> + * clks                 250   (1/6)            200   (1/8)
> + * clks1        125   (1/12)           100   (1/16)
> + * clks3        187.5 (1/8)            200   (1/8)
> + * clks4         93.7 (1/16)           100   (1/16)
> + * clkp                  62.5 (1/24)            50   (1/32)
> + * clkg                  62.5 (1/24)            66.6 (1/24)
> + * clkb, CLKOUT
> + * (MD2 = 0)     62.5 (1/24)            66.6 (1/24)
> + * (MD2 = 1)     41.6 (1/36)            50   (1/32)
> + */
> +
> +#define CPG_CLK_CONFIG_INDEX(md)       (((md) & (BIT(1)|BIT(2))) >> 1)
> +
> +struct cpg_clk_config {
> +       unsigned int z_mult;
> +       unsigned int z_div;
> +       unsigned int zs_and_s_div;
> +       unsigned int s1_div;
> +       unsigned int p_div;
> +       unsigned int out_div;
> +};
> +
> +static const struct cpg_clk_config cpg_clk_configs[4] __initconst = {
> +       { 1, 2, 8, 16, 32, 24 },
> +       { 1, 2, 8, 16, 32, 24 },
> +       { 2, 3, 6, 12, 24, 36 },
> +       { 2, 3, 6, 12, 24, 32 },
> +};

Shouldn't this be

+static const struct cpg_clk_config cpg_clk_configs[4] __initconst = {
+       { 1, 2, 8, 16, 32, 24 },
+       { 2, 3, 6, 12, 24, 24 },
+       { 1, 2, 8, 16, 32, 32 },
+       { 2, 3, 6, 12, 24, 36 },
+};

?

I think you got confused by writing the bitmask as "BIT(1)|BIT(2)" instead
of "BIT(2)|BIT(1)".

> +/*
> + *   MD                PLLA Ratio
> + * 12 11
> + *------------------------
> + * 0  0                x42
> + * 0  1                x48
> + * 1  0                x56
> + * 1  1                x64
> + */
> +#define CPG_PLL_CONFIG_INDEX(md)       ((((md) & BIT(14)) >> 12) | \
> +                                        (((md) & BIT(13)) >> 12) | \
> +                                        (((md) & BIT(19)) >> 19))
> +struct cpg_pll_config {
> +       unsigned int extal_div;
> +       unsigned int pll1_mult;
> +       unsigned int pll3_mult;
> +};

CPG_PLL_CONFIG_INDEX() and struct cpg_pll_config are unused, and
disrupt the reading experience for the casual reviewer, as they split the
section about MD12 and M11 in two.

> +
> +#define CPG_PLLA_MULT_INDEX(md)        (((md) & (BIT(12)|BIT(11))) >> 11)

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH v3 01/20] clk: shmobile: r8a7779: Add clocks support

[Geert Uytterhoeven]

On Wed, Feb 26, 2014 at 8:33 AM, Simon Horman
<horms+renesas@verge.net.au> wrote:
> +++ b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
> @@ -0,0 +1,26 @@
> +* Renesas R8A7779 Clock Pulse Generator (CPG)
> +
> +The CPG generates core clocks for the R8A7779. It includes one PLL and
> +and several fixed ratio dividers

Double "and"

> +++ b/drivers/clk/shmobile/clk-r8a7779.c

> +/*
> + *             MD1 = 1                 MD1 = 0
> + *             (PLLA = 1500)           (PLLA = 1600)
> + *             (MHz)                   (MHz)
> + *------------------------------------------------+--------------------
> + * clkz                1000   (2/3)            800   (1/2)
> + * clkzs        250   (1/6)            200   (1/8)
> + * clki                 750   (1/2)            800   (1/2)
> + * clks                 250   (1/6)            200   (1/8)
> + * clks1        125   (1/12)           100   (1/16)
> + * clks3        187.5 (1/8)            200   (1/8)
> + * clks4         93.7 (1/16)           100   (1/16)
> + * clkp                  62.5 (1/24)            50   (1/32)
> + * clkg                  62.5 (1/24)            66.6 (1/24)
> + * clkb, CLKOUT
> + * (MD2 = 0)     62.5 (1/24)            66.6 (1/24)
> + * (MD2 = 1)     41.6 (1/36)            50   (1/32)
> + */
> +
> +#define CPG_CLK_CONFIG_INDEX(md)       (((md) & (BIT(1)|BIT(2))) >> 1)
> +
> +struct cpg_clk_config {
> +       unsigned int z_mult;
> +       unsigned int z_div;
> +       unsigned int zs_and_s_div;
> +       unsigned int s1_div;
> +       unsigned int p_div;
> +       unsigned int out_div;
> +};
> +
> +static const struct cpg_clk_config cpg_clk_configs[4] __initconst = {
> +       { 1, 2, 8, 16, 32, 24 },
> +       { 1, 2, 8, 16, 32, 24 },
> +       { 2, 3, 6, 12, 24, 36 },
> +       { 2, 3, 6, 12, 24, 32 },
> +};

Shouldn't this be

+static const struct cpg_clk_config cpg_clk_configs[4] __initconst = {
+       { 1, 2, 8, 16, 32, 24 },
+       { 2, 3, 6, 12, 24, 24 },
+       { 1, 2, 8, 16, 32, 32 },
+       { 2, 3, 6, 12, 24, 36 },
+};

?

I think you got confused by writing the bitmask as "BIT(1)|BIT(2)" instead
of "BIT(2)|BIT(1)".

> +/*
> + *   MD                PLLA Ratio
> + * 12 11
> + *------------------------
> + * 0  0                x42
> + * 0  1                x48
> + * 1  0                x56
> + * 1  1                x64
> + */
> +#define CPG_PLL_CONFIG_INDEX(md)       ((((md) & BIT(14)) >> 12) | \
> +                                        (((md) & BIT(13)) >> 12) | \
> +                                        (((md) & BIT(19)) >> 19))
> +struct cpg_pll_config {
> +       unsigned int extal_div;
> +       unsigned int pll1_mult;
> +       unsigned int pll3_mult;
> +};

CPG_PLL_CONFIG_INDEX() and struct cpg_pll_config are unused, and
disrupt the reading experience for the casual reviewer, as they split the
section about MD12 and M11 in two.

> +
> +#define CPG_PLLA_MULT_INDEX(md)        (((md) & (BIT(12)|BIT(11))) >> 11)

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v3 04/20] ARM: shmobile: r8a7779: Add clocks

[Geert Uytterhoeven]

On Wed, Feb 26, 2014 at 8:33 AM, Simon Horman
<horms+renesas@verge.net.au> wrote:
> +               /* Gate clocks */
> +               mstp0_clks: mstp0_clks {
> +                       compatible = "renesas,r8a7779-mstp-clocks", "renesas,cpg-mstp-clocks";
> +                       reg = <0 0xffc80030 0 4>;
> +                       clocks = <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> +                                <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> +                                <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> +                                <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> +                                <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> +                                <&cpg_clocks R8A7779_CLK_P>;

Is there any rationale behind the decision to (not) split long lines?
The above are really long.

> +                       #clock-cells = <1>;
> +                       renesas,clock-indices = <
> +                               R8A7779_CLK_HSPI R8A7779_CLK_TMU0 R8A7779_CLK_TMU0
> +                               R8A7779_CLK_TMU0 R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
> +                               R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2 R8A7779_CLK_SCIF1
> +                               R8A7779_CLK_SCIF0 R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
> +                               R8A7779_CLK_I2C1 R8A7779_CLK_I2C0

A bit longer than 80 characters (fine for me, though).

> +                       >;
> +                       clock-output-names > +                               "hspi", "tmu00", "tmu01",
> +                               "tmu02", "scif5", "scif4",
> +                               "scif3", "scif2", "scif1",
> +                               "scif0", "i2c3", "i2c2",
> +                               "i2c1", "i2c0";

Much shorter than 80 characters (to match the above?).

> +               };
> +               mstp1_clks: mstp1_clks {
> +                       compatible = "renesas,r8a7779-mstp-clocks", "renesas,cpg-mstp-clocks";
> +                       reg = <0 0xffc80034 0 4>, <0 0xffc80044 0 4>;
> +                       clocks = <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> +                                <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> +                                <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> +                                <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> +                                <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> +                                <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>;
> +                       #clock-cells = <1>;
> +                       renesas,clock-indices = <
> +                               R8A7779_CLK_USB01 R8A7779_CLK_USB01

Fits in 80 characters.

> +                               R8A7779_CLK_USB2 R8A7779_CLK_USB2
> +                               R8A7779_CLK_DU R8A7779_CLK_VIN2
> +                               R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
> +                               R8A7779_CLK_ETHER R8A7779_CLK_SATA
> +                               R8A7779_CLK_PCIE R8A7779_CLK_VIN3
> +                       >;
> +                       clock-output-names > +                               "ehci0", "ohci0",
> +                               "ehci1", "ohci1",
> +                               "du", "vin2",
> +                               "vin1", "vin0",
> +                               "ether", "sata",
> +                               "pcie", "vin3";

Reallt short, could be compacted a lot.

> +               };

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH v3 04/20] ARM: shmobile: r8a7779: Add clocks

[Geert Uytterhoeven]

On Wed, Feb 26, 2014 at 8:33 AM, Simon Horman
<horms+renesas@verge.net.au> wrote:
> +               /* Gate clocks */
> +               mstp0_clks: mstp0_clks {
> +                       compatible = "renesas,r8a7779-mstp-clocks", "renesas,cpg-mstp-clocks";
> +                       reg = <0 0xffc80030 0 4>;
> +                       clocks = <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> +                                <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> +                                <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> +                                <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> +                                <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> +                                <&cpg_clocks R8A7779_CLK_P>;

Is there any rationale behind the decision to (not) split long lines?
The above are really long.

> +                       #clock-cells = <1>;
> +                       renesas,clock-indices = <
> +                               R8A7779_CLK_HSPI R8A7779_CLK_TMU0 R8A7779_CLK_TMU0
> +                               R8A7779_CLK_TMU0 R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
> +                               R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2 R8A7779_CLK_SCIF1
> +                               R8A7779_CLK_SCIF0 R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
> +                               R8A7779_CLK_I2C1 R8A7779_CLK_I2C0

A bit longer than 80 characters (fine for me, though).

> +                       >;
> +                       clock-output-names =
> +                               "hspi", "tmu00", "tmu01",
> +                               "tmu02", "scif5", "scif4",
> +                               "scif3", "scif2", "scif1",
> +                               "scif0", "i2c3", "i2c2",
> +                               "i2c1", "i2c0";

Much shorter than 80 characters (to match the above?).

> +               };
> +               mstp1_clks: mstp1_clks {
> +                       compatible = "renesas,r8a7779-mstp-clocks", "renesas,cpg-mstp-clocks";
> +                       reg = <0 0xffc80034 0 4>, <0 0xffc80044 0 4>;
> +                       clocks = <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> +                                <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> +                                <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> +                                <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> +                                <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> +                                <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>;
> +                       #clock-cells = <1>;
> +                       renesas,clock-indices = <
> +                               R8A7779_CLK_USB01 R8A7779_CLK_USB01

Fits in 80 characters.

> +                               R8A7779_CLK_USB2 R8A7779_CLK_USB2
> +                               R8A7779_CLK_DU R8A7779_CLK_VIN2
> +                               R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
> +                               R8A7779_CLK_ETHER R8A7779_CLK_SATA
> +                               R8A7779_CLK_PCIE R8A7779_CLK_VIN3
> +                       >;
> +                       clock-output-names =
> +                               "ehci0", "ohci0",
> +                               "ehci1", "ohci1",
> +                               "du", "vin2",
> +                               "vin1", "vin0",
> +                               "ether", "sata",
> +                               "pcie", "vin3";

Reallt short, could be compacted a lot.

> +               };

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v3 15/20] ARM: shmobile: marzen-reference: Instantiate clkdevs for SCIF and TMU

[Geert Uytterhoeven]

On Wed, Feb 26, 2014 at 8:33 AM, Simon Horman
<horms+renesas@verge.net.au> wrote:
> Now that the common clock framework is supported, the clock lookup
> entries in clock-r8a7779.c are not registered anymore. Devices must
> instead reference their clocks in the device tree. However, SCIF and CMT
> devices are still instantiated through platform code, and thus need a
> clock lookup entry.
>
> Retrieve the SCIF and CMT clock entries by name and register clkdevs for
> the corresponding devices. This will be removed when the SCIF and CMT
> devices will be instantiated from the device tree.
>
> Based on work for the Koelsch board by Laurent Pinchart.

Would be nice to do this on top of Magnu's shmobile_clk_workaround().

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH v3 15/20] ARM: shmobile: marzen-reference: Instantiate clkdevs for SCIF and TMU

[Geert Uytterhoeven]

On Wed, Feb 26, 2014 at 8:33 AM, Simon Horman
<horms+renesas@verge.net.au> wrote:
> Now that the common clock framework is supported, the clock lookup
> entries in clock-r8a7779.c are not registered anymore. Devices must
> instead reference their clocks in the device tree. However, SCIF and CMT
> devices are still instantiated through platform code, and thus need a
> clock lookup entry.
>
> Retrieve the SCIF and CMT clock entries by name and register clkdevs for
> the corresponding devices. This will be removed when the SCIF and CMT
> devices will be instantiated from the device tree.
>
> Based on work for the Koelsch board by Laurent Pinchart.

Would be nice to do this on top of Magnu's shmobile_clk_workaround().

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v3 20/20] ARM: shmobile: marzen-reference: Remove legacy clock support

[Geert Uytterhoeven]

On Wed, Feb 26, 2014 at 8:33 AM, Simon Horman
<horms+renesas@verge.net.au> wrote:
> Marzen DT reference is these now only built for multiplatform

Bogus "these"

> which means that CCF comes with the package. Remove unused legacy
> code ifdefs to clean up the code.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH v3 20/20] ARM: shmobile: marzen-reference: Remove legacy clock support

[Geert Uytterhoeven]

On Wed, Feb 26, 2014 at 8:33 AM, Simon Horman
<horms+renesas@verge.net.au> wrote:
> Marzen DT reference is these now only built for multiplatform

Bogus "these"

> which means that CCF comes with the package. Remove unused legacy
> code ifdefs to clean up the code.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v3 04/20] ARM: shmobile: r8a7779: Add clocks

[Simon Horman]

On Wed, Feb 26, 2014 at 09:13:47AM +0100, Geert Uytterhoeven wrote:
> On Wed, Feb 26, 2014 at 8:33 AM, Simon Horman
> <horms+renesas@verge.net.au> wrote:
> > +               /* Gate clocks */
> > +               mstp0_clks: mstp0_clks {
> > +                       compatible = "renesas,r8a7779-mstp-clocks", "renesas,cpg-mstp-clocks";
> > +                       reg = <0 0xffc80030 0 4>;
> > +                       clocks = <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> > +                                <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> > +                                <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> > +                                <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> > +                                <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> > +                                <&cpg_clocks R8A7779_CLK_P>;
> 
> Is there any rationale behind the decision to (not) split long lines?
> The above are really long.
> 
> > +                       #clock-cells = <1>;
> > +                       renesas,clock-indices = <
> > +                               R8A7779_CLK_HSPI R8A7779_CLK_TMU0 R8A7779_CLK_TMU0
> > +                               R8A7779_CLK_TMU0 R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
> > +                               R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2 R8A7779_CLK_SCIF1
> > +                               R8A7779_CLK_SCIF0 R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
> > +                               R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
> 
> A bit longer than 80 characters (fine for me, though).
> 
> > +                       >;
> > +                       clock-output-names > > +                               "hspi", "tmu00", "tmu01",
> > +                               "tmu02", "scif5", "scif4",
> > +                               "scif3", "scif2", "scif1",
> > +                               "scif0", "i2c3", "i2c2",
> > +                               "i2c1", "i2c0";
> 
> Much shorter than 80 characters (to match the above?).
> 
> > +               };
> > +               mstp1_clks: mstp1_clks {
> > +                       compatible = "renesas,r8a7779-mstp-clocks", "renesas,cpg-mstp-clocks";
> > +                       reg = <0 0xffc80034 0 4>, <0 0xffc80044 0 4>;
> > +                       clocks = <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> > +                                <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> > +                                <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> > +                                <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> > +                                <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> > +                                <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>;
> > +                       #clock-cells = <1>;
> > +                       renesas,clock-indices = <
> > +                               R8A7779_CLK_USB01 R8A7779_CLK_USB01
> 
> Fits in 80 characters.
> 
> > +                               R8A7779_CLK_USB2 R8A7779_CLK_USB2
> > +                               R8A7779_CLK_DU R8A7779_CLK_VIN2
> > +                               R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
> > +                               R8A7779_CLK_ETHER R8A7779_CLK_SATA
> > +                               R8A7779_CLK_PCIE R8A7779_CLK_VIN3
> > +                       >;
> > +                       clock-output-names > > +                               "ehci0", "ohci0",
> > +                               "ehci1", "ohci1",
> > +                               "du", "vin2",
> > +                               "vin1", "vin0",
> > +                               "ether", "sata",
> > +                               "pcie", "vin3";
> 
> Reallt short, could be compacted a lot.

The rationale to have lines in clocks, renesas,clock-indices and
clock-output-names corresponding with each other. Which I found
made it easier out weed out inconsistencies.

But I'm happy to rearrange things as you suggest.

> 
> > +               };
> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds
> --
> To unsubscribe from this list: send the line "unsubscribe linux-sh" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 

[PATCH v3 04/20] ARM: shmobile: r8a7779: Add clocks

[Simon Horman]

On Wed, Feb 26, 2014 at 09:13:47AM +0100, Geert Uytterhoeven wrote:
> On Wed, Feb 26, 2014 at 8:33 AM, Simon Horman
> <horms+renesas@verge.net.au> wrote:
> > +               /* Gate clocks */
> > +               mstp0_clks: mstp0_clks {
> > +                       compatible = "renesas,r8a7779-mstp-clocks", "renesas,cpg-mstp-clocks";
> > +                       reg = <0 0xffc80030 0 4>;
> > +                       clocks = <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> > +                                <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> > +                                <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> > +                                <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> > +                                <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> > +                                <&cpg_clocks R8A7779_CLK_P>;
> 
> Is there any rationale behind the decision to (not) split long lines?
> The above are really long.
> 
> > +                       #clock-cells = <1>;
> > +                       renesas,clock-indices = <
> > +                               R8A7779_CLK_HSPI R8A7779_CLK_TMU0 R8A7779_CLK_TMU0
> > +                               R8A7779_CLK_TMU0 R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
> > +                               R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2 R8A7779_CLK_SCIF1
> > +                               R8A7779_CLK_SCIF0 R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
> > +                               R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
> 
> A bit longer than 80 characters (fine for me, though).
> 
> > +                       >;
> > +                       clock-output-names =
> > +                               "hspi", "tmu00", "tmu01",
> > +                               "tmu02", "scif5", "scif4",
> > +                               "scif3", "scif2", "scif1",
> > +                               "scif0", "i2c3", "i2c2",
> > +                               "i2c1", "i2c0";
> 
> Much shorter than 80 characters (to match the above?).
> 
> > +               };
> > +               mstp1_clks: mstp1_clks {
> > +                       compatible = "renesas,r8a7779-mstp-clocks", "renesas,cpg-mstp-clocks";
> > +                       reg = <0 0xffc80034 0 4>, <0 0xffc80044 0 4>;
> > +                       clocks = <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> > +                                <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> > +                                <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> > +                                <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> > +                                <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> > +                                <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>;
> > +                       #clock-cells = <1>;
> > +                       renesas,clock-indices = <
> > +                               R8A7779_CLK_USB01 R8A7779_CLK_USB01
> 
> Fits in 80 characters.
> 
> > +                               R8A7779_CLK_USB2 R8A7779_CLK_USB2
> > +                               R8A7779_CLK_DU R8A7779_CLK_VIN2
> > +                               R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
> > +                               R8A7779_CLK_ETHER R8A7779_CLK_SATA
> > +                               R8A7779_CLK_PCIE R8A7779_CLK_VIN3
> > +                       >;
> > +                       clock-output-names =
> > +                               "ehci0", "ohci0",
> > +                               "ehci1", "ohci1",
> > +                               "du", "vin2",
> > +                               "vin1", "vin0",
> > +                               "ether", "sata",
> > +                               "pcie", "vin3";
> 
> Reallt short, could be compacted a lot.

The rationale to have lines in clocks, renesas,clock-indices and
clock-output-names corresponding with each other. Which I found
made it easier out weed out inconsistencies.

But I'm happy to rearrange things as you suggest.

> 
> > +               };
> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds
> --
> To unsubscribe from this list: send the line "unsubscribe linux-sh" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 

Re: [PATCH v3 15/20] ARM: shmobile: marzen-reference: Instantiate clkdevs for SCIF and TMU

[Simon Horman]

On Wed, Feb 26, 2014 at 09:29:52AM +0100, Geert Uytterhoeven wrote:
> On Wed, Feb 26, 2014 at 8:33 AM, Simon Horman
> <horms+renesas@verge.net.au> wrote:
> > Now that the common clock framework is supported, the clock lookup
> > entries in clock-r8a7779.c are not registered anymore. Devices must
> > instead reference their clocks in the device tree. However, SCIF and CMT
> > devices are still instantiated through platform code, and thus need a
> > clock lookup entry.
> >
> > Retrieve the SCIF and CMT clock entries by name and register clkdevs for
> > the corresponding devices. This will be removed when the SCIF and CMT
> > devices will be instantiated from the device tree.
> >
> > Based on work for the Koelsch board by Laurent Pinchart.
> 
> Would be nice to do this on top of Magnu's shmobile_clk_workaround().

Yes, I plan to either do so. Either by updating this
patch or providing an incremental change.

[PATCH v3 15/20] ARM: shmobile: marzen-reference: Instantiate clkdevs for SCIF and TMU

[Simon Horman]

On Wed, Feb 26, 2014 at 09:29:52AM +0100, Geert Uytterhoeven wrote:
> On Wed, Feb 26, 2014 at 8:33 AM, Simon Horman
> <horms+renesas@verge.net.au> wrote:
> > Now that the common clock framework is supported, the clock lookup
> > entries in clock-r8a7779.c are not registered anymore. Devices must
> > instead reference their clocks in the device tree. However, SCIF and CMT
> > devices are still instantiated through platform code, and thus need a
> > clock lookup entry.
> >
> > Retrieve the SCIF and CMT clock entries by name and register clkdevs for
> > the corresponding devices. This will be removed when the SCIF and CMT
> > devices will be instantiated from the device tree.
> >
> > Based on work for the Koelsch board by Laurent Pinchart.
> 
> Would be nice to do this on top of Magnu's shmobile_clk_workaround().

Yes, I plan to either do so. Either by updating this
patch or providing an incremental change.

Re: [PATCH v3 20/20] ARM: shmobile: marzen-reference: Remove legacy clock support

[Simon Horman]

On Wed, Feb 26, 2014 at 09:33:29AM +0100, Geert Uytterhoeven wrote:
> On Wed, Feb 26, 2014 at 8:33 AM, Simon Horman
> <horms+renesas@verge.net.au> wrote:
> > Marzen DT reference is these now only built for multiplatform
> 
> Bogus "these"

Thanks.

[PATCH v3 20/20] ARM: shmobile: marzen-reference: Remove legacy clock support

[Simon Horman]

On Wed, Feb 26, 2014 at 09:33:29AM +0100, Geert Uytterhoeven wrote:
> On Wed, Feb 26, 2014 at 8:33 AM, Simon Horman
> <horms+renesas@verge.net.au> wrote:
> > Marzen DT reference is these now only built for multiplatform
> 
> Bogus "these"

Thanks.

Re: [PATCH v3 01/20] clk: shmobile: r8a7779: Add clocks support

[Simon Horman]

On Wed, Feb 26, 2014 at 09:05:05AM +0100, Geert Uytterhoeven wrote:
> On Wed, Feb 26, 2014 at 8:33 AM, Simon Horman
> <horms+renesas@verge.net.au> wrote:
> > +++ b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
> > @@ -0,0 +1,26 @@
> > +* Renesas R8A7779 Clock Pulse Generator (CPG)
> > +
> > +The CPG generates core clocks for the R8A7779. It includes one PLL and
> > +and several fixed ratio dividers
> 
> Double "and"
> 
> > +++ b/drivers/clk/shmobile/clk-r8a7779.c
> 
> > +/*
> > + *             MD1 = 1                 MD1 = 0
> > + *             (PLLA = 1500)           (PLLA = 1600)
> > + *             (MHz)                   (MHz)
> > + *------------------------------------------------+--------------------
> > + * clkz                1000   (2/3)            800   (1/2)
> > + * clkzs        250   (1/6)            200   (1/8)
> > + * clki                 750   (1/2)            800   (1/2)
> > + * clks                 250   (1/6)            200   (1/8)
> > + * clks1        125   (1/12)           100   (1/16)
> > + * clks3        187.5 (1/8)            200   (1/8)
> > + * clks4         93.7 (1/16)           100   (1/16)
> > + * clkp                  62.5 (1/24)            50   (1/32)
> > + * clkg                  62.5 (1/24)            66.6 (1/24)
> > + * clkb, CLKOUT
> > + * (MD2 = 0)     62.5 (1/24)            66.6 (1/24)
> > + * (MD2 = 1)     41.6 (1/36)            50   (1/32)
> > + */
> > +
> > +#define CPG_CLK_CONFIG_INDEX(md)       (((md) & (BIT(1)|BIT(2))) >> 1)
> > +
> > +struct cpg_clk_config {
> > +       unsigned int z_mult;
> > +       unsigned int z_div;
> > +       unsigned int zs_and_s_div;
> > +       unsigned int s1_div;
> > +       unsigned int p_div;
> > +       unsigned int out_div;
> > +};
> > +
> > +static const struct cpg_clk_config cpg_clk_configs[4] __initconst = {
> > +       { 1, 2, 8, 16, 32, 24 },
> > +       { 1, 2, 8, 16, 32, 24 },
> > +       { 2, 3, 6, 12, 24, 36 },
> > +       { 2, 3, 6, 12, 24, 32 },
> > +};
> 
> Shouldn't this be
> 
> +static const struct cpg_clk_config cpg_clk_configs[4] __initconst = {
> +       { 1, 2, 8, 16, 32, 24 },
> +       { 2, 3, 6, 12, 24, 24 },
> +       { 1, 2, 8, 16, 32, 32 },
> +       { 2, 3, 6, 12, 24, 36 },
> +};
> 
> ?
> 
> I think you got confused by writing the bitmask as "BIT(1)|BIT(2)" instead
> of "BIT(2)|BIT(1)".

Probably, thanks for noticing.

> > +/*
> > + *   MD                PLLA Ratio
> > + * 12 11
> > + *------------------------
> > + * 0  0                x42
> > + * 0  1                x48
> > + * 1  0                x56
> > + * 1  1                x64
> > + */
> > +#define CPG_PLL_CONFIG_INDEX(md)       ((((md) & BIT(14)) >> 12) | \
> > +                                        (((md) & BIT(13)) >> 12) | \
> > +                                        (((md) & BIT(19)) >> 19))
> > +struct cpg_pll_config {
> > +       unsigned int extal_div;
> > +       unsigned int pll1_mult;
> > +       unsigned int pll3_mult;
> > +};
> 
> CPG_PLL_CONFIG_INDEX() and struct cpg_pll_config are unused, and
> disrupt the reading experience for the casual reviewer, as they split the
> section about MD12 and M11 in two.
> 
> > +
> > +#define CPG_PLLA_MULT_INDEX(md)        (((md) & (BIT(12)|BIT(11))) >> 11)

Thanks, I will remove them.

[PATCH v3 01/20] clk: shmobile: r8a7779: Add clocks support

[Simon Horman]

On Wed, Feb 26, 2014 at 09:05:05AM +0100, Geert Uytterhoeven wrote:
> On Wed, Feb 26, 2014 at 8:33 AM, Simon Horman
> <horms+renesas@verge.net.au> wrote:
> > +++ b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
> > @@ -0,0 +1,26 @@
> > +* Renesas R8A7779 Clock Pulse Generator (CPG)
> > +
> > +The CPG generates core clocks for the R8A7779. It includes one PLL and
> > +and several fixed ratio dividers
> 
> Double "and"
> 
> > +++ b/drivers/clk/shmobile/clk-r8a7779.c
> 
> > +/*
> > + *             MD1 = 1                 MD1 = 0
> > + *             (PLLA = 1500)           (PLLA = 1600)
> > + *             (MHz)                   (MHz)
> > + *------------------------------------------------+--------------------
> > + * clkz                1000   (2/3)            800   (1/2)
> > + * clkzs        250   (1/6)            200   (1/8)
> > + * clki                 750   (1/2)            800   (1/2)
> > + * clks                 250   (1/6)            200   (1/8)
> > + * clks1        125   (1/12)           100   (1/16)
> > + * clks3        187.5 (1/8)            200   (1/8)
> > + * clks4         93.7 (1/16)           100   (1/16)
> > + * clkp                  62.5 (1/24)            50   (1/32)
> > + * clkg                  62.5 (1/24)            66.6 (1/24)
> > + * clkb, CLKOUT
> > + * (MD2 = 0)     62.5 (1/24)            66.6 (1/24)
> > + * (MD2 = 1)     41.6 (1/36)            50   (1/32)
> > + */
> > +
> > +#define CPG_CLK_CONFIG_INDEX(md)       (((md) & (BIT(1)|BIT(2))) >> 1)
> > +
> > +struct cpg_clk_config {
> > +       unsigned int z_mult;
> > +       unsigned int z_div;
> > +       unsigned int zs_and_s_div;
> > +       unsigned int s1_div;
> > +       unsigned int p_div;
> > +       unsigned int out_div;
> > +};
> > +
> > +static const struct cpg_clk_config cpg_clk_configs[4] __initconst = {
> > +       { 1, 2, 8, 16, 32, 24 },
> > +       { 1, 2, 8, 16, 32, 24 },
> > +       { 2, 3, 6, 12, 24, 36 },
> > +       { 2, 3, 6, 12, 24, 32 },
> > +};
> 
> Shouldn't this be
> 
> +static const struct cpg_clk_config cpg_clk_configs[4] __initconst = {
> +       { 1, 2, 8, 16, 32, 24 },
> +       { 2, 3, 6, 12, 24, 24 },
> +       { 1, 2, 8, 16, 32, 32 },
> +       { 2, 3, 6, 12, 24, 36 },
> +};
> 
> ?
> 
> I think you got confused by writing the bitmask as "BIT(1)|BIT(2)" instead
> of "BIT(2)|BIT(1)".

Probably, thanks for noticing.

> > +/*
> > + *   MD                PLLA Ratio
> > + * 12 11
> > + *------------------------
> > + * 0  0                x42
> > + * 0  1                x48
> > + * 1  0                x56
> > + * 1  1                x64
> > + */
> > +#define CPG_PLL_CONFIG_INDEX(md)       ((((md) & BIT(14)) >> 12) | \
> > +                                        (((md) & BIT(13)) >> 12) | \
> > +                                        (((md) & BIT(19)) >> 19))
> > +struct cpg_pll_config {
> > +       unsigned int extal_div;
> > +       unsigned int pll1_mult;
> > +       unsigned int pll3_mult;
> > +};
> 
> CPG_PLL_CONFIG_INDEX() and struct cpg_pll_config are unused, and
> disrupt the reading experience for the casual reviewer, as they split the
> section about MD12 and M11 in two.
> 
> > +
> > +#define CPG_PLLA_MULT_INDEX(md)        (((md) & (BIT(12)|BIT(11))) >> 11)

Thanks, I will remove them.

Re: [PATCH v3 01/20] clk: shmobile: r8a7779: Add clocks support

[Geert Uytterhoeven]

On Wed, Feb 26, 2014 at 9:59 AM, Simon Horman <horms@verge.net.au> wrote:
>> > +/*
>> > + *             MD1 = 1                 MD1 = 0
>> > + *             (PLLA = 1500)           (PLLA = 1600)
>> > + *             (MHz)                   (MHz)
>> > + *------------------------------------------------+--------------------
>> > + * clkz                1000   (2/3)            800   (1/2)
>> > + * clkzs        250   (1/6)            200   (1/8)
>> > + * clki                 750   (1/2)            800   (1/2)
>> > + * clks                 250   (1/6)            200   (1/8)
>> > + * clks1        125   (1/12)           100   (1/16)
>> > + * clks3        187.5 (1/8)            200   (1/8)
>> > + * clks4         93.7 (1/16)           100   (1/16)
>> > + * clkp                  62.5 (1/24)            50   (1/32)
>> > + * clkg                  62.5 (1/24)            66.6 (1/24)
>> > + * clkb, CLKOUT
>> > + * (MD2 = 0)     62.5 (1/24)            66.6 (1/24)
>> > + * (MD2 = 1)     41.6 (1/36)            50   (1/32)
>> > + */
>> > +
>> > +#define CPG_CLK_CONFIG_INDEX(md)       (((md) & (BIT(1)|BIT(2))) >> 1)
>> > +
>> > +struct cpg_clk_config {
>> > +       unsigned int z_mult;
>> > +       unsigned int z_div;
>> > +       unsigned int zs_and_s_div;
>> > +       unsigned int s1_div;
>> > +       unsigned int p_div;
>> > +       unsigned int out_div;
>> > +};
>> > +
>> > +static const struct cpg_clk_config cpg_clk_configs[4] __initconst = {
>> > +       { 1, 2, 8, 16, 32, 24 },
>> > +       { 1, 2, 8, 16, 32, 24 },
>> > +       { 2, 3, 6, 12, 24, 36 },
>> > +       { 2, 3, 6, 12, 24, 32 },
>> > +};
>>
>> Shouldn't this be
>>
>> +static const struct cpg_clk_config cpg_clk_configs[4] __initconst = {
>> +       { 1, 2, 8, 16, 32, 24 },
>> +       { 2, 3, 6, 12, 24, 24 },
>> +       { 1, 2, 8, 16, 32, 32 },
>> +       { 2, 3, 6, 12, 24, 36 },
>> +};
>>
>> ?
>>
>> I think you got confused by writing the bitmask as "BIT(1)|BIT(2)" instead
>> of "BIT(2)|BIT(1)".
>
> Probably, thanks for noticing.

Note that I based my review on the table above, not on the actual datasheet.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH v3 01/20] clk: shmobile: r8a7779: Add clocks support

[Geert Uytterhoeven]

On Wed, Feb 26, 2014 at 9:59 AM, Simon Horman <horms@verge.net.au> wrote:
>> > +/*
>> > + *             MD1 = 1                 MD1 = 0
>> > + *             (PLLA = 1500)           (PLLA = 1600)
>> > + *             (MHz)                   (MHz)
>> > + *------------------------------------------------+--------------------
>> > + * clkz                1000   (2/3)            800   (1/2)
>> > + * clkzs        250   (1/6)            200   (1/8)
>> > + * clki                 750   (1/2)            800   (1/2)
>> > + * clks                 250   (1/6)            200   (1/8)
>> > + * clks1        125   (1/12)           100   (1/16)
>> > + * clks3        187.5 (1/8)            200   (1/8)
>> > + * clks4         93.7 (1/16)           100   (1/16)
>> > + * clkp                  62.5 (1/24)            50   (1/32)
>> > + * clkg                  62.5 (1/24)            66.6 (1/24)
>> > + * clkb, CLKOUT
>> > + * (MD2 = 0)     62.5 (1/24)            66.6 (1/24)
>> > + * (MD2 = 1)     41.6 (1/36)            50   (1/32)
>> > + */
>> > +
>> > +#define CPG_CLK_CONFIG_INDEX(md)       (((md) & (BIT(1)|BIT(2))) >> 1)
>> > +
>> > +struct cpg_clk_config {
>> > +       unsigned int z_mult;
>> > +       unsigned int z_div;
>> > +       unsigned int zs_and_s_div;
>> > +       unsigned int s1_div;
>> > +       unsigned int p_div;
>> > +       unsigned int out_div;
>> > +};
>> > +
>> > +static const struct cpg_clk_config cpg_clk_configs[4] __initconst = {
>> > +       { 1, 2, 8, 16, 32, 24 },
>> > +       { 1, 2, 8, 16, 32, 24 },
>> > +       { 2, 3, 6, 12, 24, 36 },
>> > +       { 2, 3, 6, 12, 24, 32 },
>> > +};
>>
>> Shouldn't this be
>>
>> +static const struct cpg_clk_config cpg_clk_configs[4] __initconst = {
>> +       { 1, 2, 8, 16, 32, 24 },
>> +       { 2, 3, 6, 12, 24, 24 },
>> +       { 1, 2, 8, 16, 32, 32 },
>> +       { 2, 3, 6, 12, 24, 36 },
>> +};
>>
>> ?
>>
>> I think you got confused by writing the bitmask as "BIT(1)|BIT(2)" instead
>> of "BIT(2)|BIT(1)".
>
> Probably, thanks for noticing.

Note that I based my review on the table above, not on the actual datasheet.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v3 01/20] clk: shmobile: r8a7779: Add clocks support

[Laurent Pinchart]

Hi Simon,

Thank you for the patch.

On Wednesday 26 February 2014 16:33:17 Simon Horman wrote:
> The R8A7779 SoC has several clocks that are too custom to be supported in a
> generic driver. Those clocks can be divided in two categories:
> 
> - Fixed rate clocks with multiplier and divisor set according to boot
>   mode configuration
> 
> - Custom divider clocks with SoC-specific divider values
> 
> This driver supports both.

Looking at the R8A7779 datasheet it looks like we only have fixed rate clocks, 
without any configurable divider clock. Did I miss something ?

> Based on work for R-Car Gen2 SoCs by Laurent Pinchart.
> 
> Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> 
> ---
> v3
> * As suggested by Laurent Pinchart
>   - Added external clock input
>   - Use PLLA ratio set bu MD11 and MD12
>   - Add _div suffixes of fields of struct cpt_clk_config
>   - Register PLLA as a fixed factor clock
>   - Use sizeof() instead of sizeof
>   - Use num_clks instead of CPG_NUM_CLOCKS in r8a7779_cpg_clocks_init()
> 
>   - I kept this as r8a7779 binding rather than moving to a R-Car Gen1
>     binding which could be shared with other SoCs as I do not believe that
>     the SoCs is are sufficiently similar.

I had a look at the M1 datasheet and I still find its CPG very similar with 
the H1 CPG. The PLLA multiplier and divider are different, but if you look 
closely, they're both exactly twice the value compared to H1, so there's no 
difference in practice.

What differences do you see that would make it impractical to share a single 
driver for both ?

> ---
>  .../bindings/clock/renesas,r8a7779-cpg-clocks.txt  |  26 +++
>  drivers/clk/shmobile/Makefile                      |   1 +
>  drivers/clk/shmobile/clk-r8a7779.c                 | 191 ++++++++++++++++++
>  include/linux/clk/shmobile.h                       |   3 +
>  4 files changed, 221 insertions(+)
>  create mode 100644
> Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
> create mode 100644 drivers/clk/shmobile/clk-r8a7779.c
> 
> diff --git
> a/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
> b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
> new file mode 100644
> index 0000000..1461323
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
> @@ -0,0 +1,26 @@
> +* Renesas R8A7779 Clock Pulse Generator (CPG)
> +
> +The CPG generates core clocks for the R8A7779. It includes one PLL and
> +and several fixed ratio dividers
> +
> +Required Properties:
> +
> +  - compatible: Must be "renesas,r8a7779-cpg-clocks"
> +  - reg: Base address and length of the memory resource used by the CPG
> +
> +  - clocks: Reference to the parent clock
> +  - #clock-cells: Must be 1
> +  - clock-output-names: The names of the clocks. Supported clocks are
> "plla",
> +    "z", "zs", "s", "s1", "p", "out".

What about clki, clks3, clks4, clkb and clkg ? Should pllb be exposed as well 
?

> +Example
> +-------
> +
> +	cpg_clocks: cpg_clocks@ffc80000 {
> +		compatible = "renesas,r8a7779-cpg-clocks";
> +		reg = <0 0xffc80000 0 0x80>;

Shouldn't the range be restricted not to include the MSTP registers ? 0x30 
should be enough.

> +		clocks = <&extal_clk>;
> +		#clock-cells = <1>;
> +		clock-output-names = "plla", "z", "zs", "s", "s1", "p", "out";
> +	};
> diff --git a/drivers/clk/shmobile/Makefile b/drivers/clk/shmobile/Makefile
> index 9ecef14..2121ba0 100644
> --- a/drivers/clk/shmobile/Makefile
> +++ b/drivers/clk/shmobile/Makefile
> @@ -1,4 +1,5 @@
>  obj-$(CONFIG_ARCH_EMEV2)		+= clk-emev2.o
> +obj-$(CONFIG_ARCH_R8A7779)		+= clk-r8a7779.o
>  obj-$(CONFIG_ARCH_R8A7790)		+= clk-rcar-gen2.o
>  obj-$(CONFIG_ARCH_R8A7791)		+= clk-rcar-gen2.o
>  obj-$(CONFIG_ARCH_SHMOBILE_MULTI)	+= clk-div6.o
> diff --git a/drivers/clk/shmobile/clk-r8a7779.c
> b/drivers/clk/shmobile/clk-r8a7779.c new file mode 100644
> index 0000000..2ca2d67
> --- /dev/null
> +++ b/drivers/clk/shmobile/clk-r8a7779.c
> @@ -0,0 +1,191 @@
> +/*
> + * r8a7779 Core CPG Clocks
> + *
> + * Copyright (C) 2013, 2014 Horms Solutions Ltd.
> + *
> + * Contact: Simon Horman <horms@verge.net.au>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; version 2 of the License.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/clkdev.h>
> +#include <linux/clk/shmobile.h>
> +#include <linux/init.h>
> +#include <linux/kernel.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/spinlock.h>
> +
> +#include <dt-bindings/clock/r8a7779-clock.h>
> +
> +#define CPG_NUM_CLOCKS			(R8A7779_CLK_OUT + 1)
> +
> +struct r8a7779_cpg {
> +	struct clk_onecell_data data;
> +	spinlock_t lock;
> +	void __iomem *reg;
> +};
> +
> +/*
> ---------------------------------------------------------------------------
> -- + * CPG Clock Data
> + */
> +
> +/*
> + *		MD1 = 1			MD1 = 0
> + *		(PLLA = 1500)		(PLLA = 1600)
> + *		(MHz)			(MHz)
> + *------------------------------------------------+--------------------
> + * clkz		1000   (2/3)		800   (1/2)
> + * clkzs	 250   (1/6)		200   (1/8)
> + * clki		 750   (1/2)		800   (1/2)
> + * clks		 250   (1/6)		200   (1/8)
> + * clks1	 125   (1/12)		100   (1/16)
> + * clks3	 187.5 (1/8)		200   (1/8)
> + * clks4	  93.7 (1/16)		100   (1/16)
> + * clkp		  62.5 (1/24)		 50   (1/32)
> + * clkg		  62.5 (1/24)		 66.6 (1/24)
> + * clkb, CLKOUT
> + * (MD2 = 0)	  62.5 (1/24)		 66.6 (1/24)
> + * (MD2 = 1)	  41.6 (1/36)		 50   (1/32)
> + */
> +
> +#define CPG_CLK_CONFIG_INDEX(md)	(((md) & (BIT(1)|BIT(2))) >> 1)
> +
> +struct cpg_clk_config {
> +	unsigned int z_mult;
> +	unsigned int z_div;
> +	unsigned int zs_and_s_div;
> +	unsigned int s1_div;
> +	unsigned int p_div;
> +	unsigned int out_div;
> +};
> +
> +static const struct cpg_clk_config cpg_clk_configs[4] __initconst = {
> +	{ 1, 2, 8, 16, 32, 24 },
> +	{ 1, 2, 8, 16, 32, 24 },
> +	{ 2, 3, 6, 12, 24, 36 },
> +	{ 2, 3, 6, 12, 24, 32 },
> +};
> +
> +/*
> + *   MD		PLLA Ratio
> + * 12 11
> + *------------------------
> + * 0  0		x42
> + * 0  1		x48
> + * 1  0		x56
> + * 1  1		x64
> + */
> +#define CPG_PLL_CONFIG_INDEX(md)	((((md) & BIT(14)) >> 12) | \
> +					 (((md) & BIT(13)) >> 12) | \
> +					 (((md) & BIT(19)) >> 19))
> +struct cpg_pll_config {
> +	unsigned int extal_div;
> +	unsigned int pll1_mult;
> +	unsigned int pll3_mult;
> +};
> +
> +#define CPG_PLLA_MULT_INDEX(md)	(((md) & (BIT(12)|BIT(11))) >> 11)
> +
> +static const unsigned int cpg_plla_mult[4] __initconst = { 42, 48, 56, 64
> };
> +
> +/* ------------------------------------------------------------------------
> + * Initialization
> + */
> +
> +static u32 cpg_mode __initdata;
> +
> +static struct clk * __init
> +r8a7779_cpg_register_clock(struct device_node *np, struct r8a7779_cpg *cpg,
> +			   const struct cpg_clk_config *config,
> +			   unsigned int plla_mult, const char *name)
> +{
> +	const char *parent_name = "plla";
> +	unsigned int mult = 1;
> +	unsigned int div = 1;
> +
> +	if (!strcmp(name, "plla")) {
> +		parent_name = of_clk_get_parent_name(np, 0);
> +		mult = plla_mult;
> +	} else if (!strcmp(name, "z")) {
> +		div = config->z_div;
> +		mult = config->z_mult;
> +	} else if (!strcmp(name, "zs") || !strcmp(name, "s")) {
> +		div = config->zs_and_s_div;
> +	} else if (!strcmp(name, "s1")) {
> +		div = config->s1_div;
> +	} else if (!strcmp(name, "p")) {
> +		div = config->p_div;
> +	} else if (!strcmp(name, "out")) {
> +		div = config->out_div;
> +	}

You're missing an

	else {
		return ERR_PTR5-EINVAL);
	}

I was tempted to say that it would make sense to read the div values from the 
FRQMR register instead and remove the need to pass the boot mode bits to the 
driver, but we need them for the PLLA multiplier anyway :-/

> +
> +	return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, div);
> +}
> +
> +static void __init r8a7779_cpg_clocks_init(struct device_node *np)
> +{
> +	const struct cpg_clk_config *config;
> +	struct r8a7779_cpg *cpg;
> +	struct clk **clks;
> +	unsigned int i, plla_mult;
> +	int num_clks;
> +
> +	num_clks = of_property_count_strings(np, "clock-output-names");
> +	if (num_clks < 0) {
> +		pr_err("%s: failed to count clocks\n", __func__);
> +		return;
> +	}
> +
> +	cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
> +	clks = kzalloc(CPG_NUM_CLOCKS * sizeof(*clks), GFP_KERNEL);
> +	if (cpg = NULL || clks = NULL) {
> +		/* We're leaking memory on purpose, there's no point in cleaning
> +		 * up as the system won't boot anyway.
> +		 */
> +		pr_err("%s: failed to allocate cpg\n", __func__);
> +		return;
> +	}
> +
> +	spin_lock_init(&cpg->lock);
> +
> +	cpg->data.clks = clks;
> +	cpg->data.clk_num = num_clks;
> +
> +	cpg->reg = of_iomap(np, 0);
> +	if (WARN_ON(cpg->reg = NULL))
> +		return;
> +
> +	config = &cpg_clk_configs[CPG_CLK_CONFIG_INDEX(cpg_mode)];
> +	plla_mult = cpg_plla_mult[CPG_PLLA_MULT_INDEX(cpg_mode)];

Given that plla_mult is only used for a single clock, I would move that inside 
the if (!strcmp(name, "plla")) { } above.

> +
> +	for (i = 0; i < num_clks; ++i) {
> +		const char *name;
> +		struct clk *clk;
> +
> +		of_property_read_string_index(np, "clock-output-names", i,
> +					      &name);
> +
> +		clk = r8a7779_cpg_register_clock(np, cpg, config,
> +						 plla_mult, name);
> +		if (IS_ERR(clk))
> +			pr_err("%s: failed to register %s %s clock (%ld)\n",
> +			       __func__, np->name, name, PTR_ERR(clk));
> +		else
> +			cpg->data.clks[i] = clk;
> +	}
> +
> +	of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
> +}
> +CLK_OF_DECLARE(r8a7779_cpg_clks, "renesas,r8a7779-cpg-clocks",
> +	       r8a7779_cpg_clocks_init);
> +
> +void __init r8a7779_clocks_init(u32 mode)
> +{
> +	cpg_mode = mode;
> +
> +	of_clk_init(NULL);
> +}
> diff --git a/include/linux/clk/shmobile.h b/include/linux/clk/shmobile.h
> index f9bf080..7667f49 100644
> --- a/include/linux/clk/shmobile.h
> +++ b/include/linux/clk/shmobile.h
> @@ -1,7 +1,9 @@
>  /*
>   * Copyright 2013 Ideas On Board SPRL
> + * Copyright 2013 Horms Solutions Ltd.

2014 ?

>   *
>   * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> + * Contact: Simon Horman <horms@verge.net.au>
>   *
>   * This program is free software; you can redistribute it and/or modify
>   * it under the terms of the GNU General Public License as published by
> @@ -14,6 +16,7 @@
> 
>  #include <linux/types.h>
> 
> +void r8a7779_clocks_init(u32 mode);
>  void rcar_gen2_clocks_init(u32 mode);
> 
>  #endif

-- 
Regards,

Laurent Pinchart

[PATCH v3 01/20] clk: shmobile: r8a7779: Add clocks support

[Laurent Pinchart]

Hi Simon,

Thank you for the patch.

On Wednesday 26 February 2014 16:33:17 Simon Horman wrote:
> The R8A7779 SoC has several clocks that are too custom to be supported in a
> generic driver. Those clocks can be divided in two categories:
> 
> - Fixed rate clocks with multiplier and divisor set according to boot
>   mode configuration
> 
> - Custom divider clocks with SoC-specific divider values
> 
> This driver supports both.

Looking at the R8A7779 datasheet it looks like we only have fixed rate clocks, 
without any configurable divider clock. Did I miss something ?

> Based on work for R-Car Gen2 SoCs by Laurent Pinchart.
> 
> Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> 
> ---
> v3
> * As suggested by Laurent Pinchart
>   - Added external clock input
>   - Use PLLA ratio set bu MD11 and MD12
>   - Add _div suffixes of fields of struct cpt_clk_config
>   - Register PLLA as a fixed factor clock
>   - Use sizeof() instead of sizeof
>   - Use num_clks instead of CPG_NUM_CLOCKS in r8a7779_cpg_clocks_init()
> 
>   - I kept this as r8a7779 binding rather than moving to a R-Car Gen1
>     binding which could be shared with other SoCs as I do not believe that
>     the SoCs is are sufficiently similar.

I had a look at the M1 datasheet and I still find its CPG very similar with 
the H1 CPG. The PLLA multiplier and divider are different, but if you look 
closely, they're both exactly twice the value compared to H1, so there's no 
difference in practice.

What differences do you see that would make it impractical to share a single 
driver for both ?

> ---
>  .../bindings/clock/renesas,r8a7779-cpg-clocks.txt  |  26 +++
>  drivers/clk/shmobile/Makefile                      |   1 +
>  drivers/clk/shmobile/clk-r8a7779.c                 | 191 ++++++++++++++++++
>  include/linux/clk/shmobile.h                       |   3 +
>  4 files changed, 221 insertions(+)
>  create mode 100644
> Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
> create mode 100644 drivers/clk/shmobile/clk-r8a7779.c
> 
> diff --git
> a/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
> b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
> new file mode 100644
> index 0000000..1461323
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
> @@ -0,0 +1,26 @@
> +* Renesas R8A7779 Clock Pulse Generator (CPG)
> +
> +The CPG generates core clocks for the R8A7779. It includes one PLL and
> +and several fixed ratio dividers
> +
> +Required Properties:
> +
> +  - compatible: Must be "renesas,r8a7779-cpg-clocks"
> +  - reg: Base address and length of the memory resource used by the CPG
> +
> +  - clocks: Reference to the parent clock
> +  - #clock-cells: Must be 1
> +  - clock-output-names: The names of the clocks. Supported clocks are
> "plla",
> +    "z", "zs", "s", "s1", "p", "out".

What about clki, clks3, clks4, clkb and clkg ? Should pllb be exposed as well 
?

> +Example
> +-------
> +
> +	cpg_clocks: cpg_clocks at ffc80000 {
> +		compatible = "renesas,r8a7779-cpg-clocks";
> +		reg = <0 0xffc80000 0 0x80>;

Shouldn't the range be restricted not to include the MSTP registers ? 0x30 
should be enough.

> +		clocks = <&extal_clk>;
> +		#clock-cells = <1>;
> +		clock-output-names = "plla", "z", "zs", "s", "s1", "p", "out";
> +	};
> diff --git a/drivers/clk/shmobile/Makefile b/drivers/clk/shmobile/Makefile
> index 9ecef14..2121ba0 100644
> --- a/drivers/clk/shmobile/Makefile
> +++ b/drivers/clk/shmobile/Makefile
> @@ -1,4 +1,5 @@
>  obj-$(CONFIG_ARCH_EMEV2)		+= clk-emev2.o
> +obj-$(CONFIG_ARCH_R8A7779)		+= clk-r8a7779.o
>  obj-$(CONFIG_ARCH_R8A7790)		+= clk-rcar-gen2.o
>  obj-$(CONFIG_ARCH_R8A7791)		+= clk-rcar-gen2.o
>  obj-$(CONFIG_ARCH_SHMOBILE_MULTI)	+= clk-div6.o
> diff --git a/drivers/clk/shmobile/clk-r8a7779.c
> b/drivers/clk/shmobile/clk-r8a7779.c new file mode 100644
> index 0000000..2ca2d67
> --- /dev/null
> +++ b/drivers/clk/shmobile/clk-r8a7779.c
> @@ -0,0 +1,191 @@
> +/*
> + * r8a7779 Core CPG Clocks
> + *
> + * Copyright (C) 2013, 2014 Horms Solutions Ltd.
> + *
> + * Contact: Simon Horman <horms@verge.net.au>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; version 2 of the License.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/clkdev.h>
> +#include <linux/clk/shmobile.h>
> +#include <linux/init.h>
> +#include <linux/kernel.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/spinlock.h>
> +
> +#include <dt-bindings/clock/r8a7779-clock.h>
> +
> +#define CPG_NUM_CLOCKS			(R8A7779_CLK_OUT + 1)
> +
> +struct r8a7779_cpg {
> +	struct clk_onecell_data data;
> +	spinlock_t lock;
> +	void __iomem *reg;
> +};
> +
> +/*
> ---------------------------------------------------------------------------
> -- + * CPG Clock Data
> + */
> +
> +/*
> + *		MD1 = 1			MD1 = 0
> + *		(PLLA = 1500)		(PLLA = 1600)
> + *		(MHz)			(MHz)
> + *------------------------------------------------+--------------------
> + * clkz		1000   (2/3)		800   (1/2)
> + * clkzs	 250   (1/6)		200   (1/8)
> + * clki		 750   (1/2)		800   (1/2)
> + * clks		 250   (1/6)		200   (1/8)
> + * clks1	 125   (1/12)		100   (1/16)
> + * clks3	 187.5 (1/8)		200   (1/8)
> + * clks4	  93.7 (1/16)		100   (1/16)
> + * clkp		  62.5 (1/24)		 50   (1/32)
> + * clkg		  62.5 (1/24)		 66.6 (1/24)
> + * clkb, CLKOUT
> + * (MD2 = 0)	  62.5 (1/24)		 66.6 (1/24)
> + * (MD2 = 1)	  41.6 (1/36)		 50   (1/32)
> + */
> +
> +#define CPG_CLK_CONFIG_INDEX(md)	(((md) & (BIT(1)|BIT(2))) >> 1)
> +
> +struct cpg_clk_config {
> +	unsigned int z_mult;
> +	unsigned int z_div;
> +	unsigned int zs_and_s_div;
> +	unsigned int s1_div;
> +	unsigned int p_div;
> +	unsigned int out_div;
> +};
> +
> +static const struct cpg_clk_config cpg_clk_configs[4] __initconst = {
> +	{ 1, 2, 8, 16, 32, 24 },
> +	{ 1, 2, 8, 16, 32, 24 },
> +	{ 2, 3, 6, 12, 24, 36 },
> +	{ 2, 3, 6, 12, 24, 32 },
> +};
> +
> +/*
> + *   MD		PLLA Ratio
> + * 12 11
> + *------------------------
> + * 0  0		x42
> + * 0  1		x48
> + * 1  0		x56
> + * 1  1		x64
> + */
> +#define CPG_PLL_CONFIG_INDEX(md)	((((md) & BIT(14)) >> 12) | \
> +					 (((md) & BIT(13)) >> 12) | \
> +					 (((md) & BIT(19)) >> 19))
> +struct cpg_pll_config {
> +	unsigned int extal_div;
> +	unsigned int pll1_mult;
> +	unsigned int pll3_mult;
> +};
> +
> +#define CPG_PLLA_MULT_INDEX(md)	(((md) & (BIT(12)|BIT(11))) >> 11)
> +
> +static const unsigned int cpg_plla_mult[4] __initconst = { 42, 48, 56, 64
> };
> +
> +/* ------------------------------------------------------------------------
> + * Initialization
> + */
> +
> +static u32 cpg_mode __initdata;
> +
> +static struct clk * __init
> +r8a7779_cpg_register_clock(struct device_node *np, struct r8a7779_cpg *cpg,
> +			   const struct cpg_clk_config *config,
> +			   unsigned int plla_mult, const char *name)
> +{
> +	const char *parent_name = "plla";
> +	unsigned int mult = 1;
> +	unsigned int div = 1;
> +
> +	if (!strcmp(name, "plla")) {
> +		parent_name = of_clk_get_parent_name(np, 0);
> +		mult = plla_mult;
> +	} else if (!strcmp(name, "z")) {
> +		div = config->z_div;
> +		mult = config->z_mult;
> +	} else if (!strcmp(name, "zs") || !strcmp(name, "s")) {
> +		div = config->zs_and_s_div;
> +	} else if (!strcmp(name, "s1")) {
> +		div = config->s1_div;
> +	} else if (!strcmp(name, "p")) {
> +		div = config->p_div;
> +	} else if (!strcmp(name, "out")) {
> +		div = config->out_div;
> +	}

You're missing an

	else {
		return ERR_PTR5-EINVAL);
	}

I was tempted to say that it would make sense to read the div values from the 
FRQMR register instead and remove the need to pass the boot mode bits to the 
driver, but we need them for the PLLA multiplier anyway :-/

> +
> +	return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, div);
> +}
> +
> +static void __init r8a7779_cpg_clocks_init(struct device_node *np)
> +{
> +	const struct cpg_clk_config *config;
> +	struct r8a7779_cpg *cpg;
> +	struct clk **clks;
> +	unsigned int i, plla_mult;
> +	int num_clks;
> +
> +	num_clks = of_property_count_strings(np, "clock-output-names");
> +	if (num_clks < 0) {
> +		pr_err("%s: failed to count clocks\n", __func__);
> +		return;
> +	}
> +
> +	cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
> +	clks = kzalloc(CPG_NUM_CLOCKS * sizeof(*clks), GFP_KERNEL);
> +	if (cpg == NULL || clks == NULL) {
> +		/* We're leaking memory on purpose, there's no point in cleaning
> +		 * up as the system won't boot anyway.
> +		 */
> +		pr_err("%s: failed to allocate cpg\n", __func__);
> +		return;
> +	}
> +
> +	spin_lock_init(&cpg->lock);
> +
> +	cpg->data.clks = clks;
> +	cpg->data.clk_num = num_clks;
> +
> +	cpg->reg = of_iomap(np, 0);
> +	if (WARN_ON(cpg->reg == NULL))
> +		return;
> +
> +	config = &cpg_clk_configs[CPG_CLK_CONFIG_INDEX(cpg_mode)];
> +	plla_mult = cpg_plla_mult[CPG_PLLA_MULT_INDEX(cpg_mode)];

Given that plla_mult is only used for a single clock, I would move that inside 
the if (!strcmp(name, "plla")) { } above.

> +
> +	for (i = 0; i < num_clks; ++i) {
> +		const char *name;
> +		struct clk *clk;
> +
> +		of_property_read_string_index(np, "clock-output-names", i,
> +					      &name);
> +
> +		clk = r8a7779_cpg_register_clock(np, cpg, config,
> +						 plla_mult, name);
> +		if (IS_ERR(clk))
> +			pr_err("%s: failed to register %s %s clock (%ld)\n",
> +			       __func__, np->name, name, PTR_ERR(clk));
> +		else
> +			cpg->data.clks[i] = clk;
> +	}
> +
> +	of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
> +}
> +CLK_OF_DECLARE(r8a7779_cpg_clks, "renesas,r8a7779-cpg-clocks",
> +	       r8a7779_cpg_clocks_init);
> +
> +void __init r8a7779_clocks_init(u32 mode)
> +{
> +	cpg_mode = mode;
> +
> +	of_clk_init(NULL);
> +}
> diff --git a/include/linux/clk/shmobile.h b/include/linux/clk/shmobile.h
> index f9bf080..7667f49 100644
> --- a/include/linux/clk/shmobile.h
> +++ b/include/linux/clk/shmobile.h
> @@ -1,7 +1,9 @@
>  /*
>   * Copyright 2013 Ideas On Board SPRL
> + * Copyright 2013 Horms Solutions Ltd.

2014 ?

>   *
>   * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> + * Contact: Simon Horman <horms@verge.net.au>
>   *
>   * This program is free software; you can redistribute it and/or modify
>   * it under the terms of the GNU General Public License as published by
> @@ -14,6 +16,7 @@
> 
>  #include <linux/types.h>
> 
> +void r8a7779_clocks_init(u32 mode);
>  void rcar_gen2_clocks_init(u32 mode);
> 
>  #endif

-- 
Regards,

Laurent Pinchart

Re: [PATCH v3 02/20] clk: shmobile: r8a7779: Add MSTP clock support

[Laurent Pinchart]

Hi Simon,

Thank you for the patch.

On Wednesday 26 February 2014 16:33:18 Simon Horman wrote:
> Add MSTP clock support for the r8a7779 SoC
> 
> The only change required appears to be to note a new
> compatibility string in the bindings.
> 
> Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

> 
> ---
> v3
> * As suggested by Laurent Pinchart
>   - Add entry in numerical order
> ---
>  Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git
> a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
> b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt index
> a6a352c..f3226ac 100644
> --- a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
> +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
> @@ -10,6 +10,7 @@ index in the group, from 0 to 31.
>  Required Properties:
> 
>    - compatible: Must be one of the following
> +    - "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks
> - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks -
> "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2) MSTP gate clocks -
> "renesas,cpg-mstp-clock" for generic MSTP gate clocks

-- 
Regards,

Laurent Pinchart

[PATCH v3 02/20] clk: shmobile: r8a7779: Add MSTP clock support

[Laurent Pinchart]

Hi Simon,

Thank you for the patch.

On Wednesday 26 February 2014 16:33:18 Simon Horman wrote:
> Add MSTP clock support for the r8a7779 SoC
> 
> The only change required appears to be to note a new
> compatibility string in the bindings.
> 
> Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

> 
> ---
> v3
> * As suggested by Laurent Pinchart
>   - Add entry in numerical order
> ---
>  Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git
> a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
> b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt index
> a6a352c..f3226ac 100644
> --- a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
> +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
> @@ -10,6 +10,7 @@ index in the group, from 0 to 31.
>  Required Properties:
> 
>    - compatible: Must be one of the following
> +    - "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks
> - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks -
> "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2) MSTP gate clocks -
> "renesas,cpg-mstp-clock" for generic MSTP gate clocks

-- 
Regards,

Laurent Pinchart

Re: [PATCH v3 03/20] ARM: shmobile: r8a7779: Add clock index macros for DT sources

[Laurent Pinchart]

Hi Simon,

Thank you for the patch.

On Wednesday 26 February 2014 16:33:19 Simon Horman wrote:
> Add macros usable by device tree sources to reference r8a7779 clocks by
> index.
> 
> Based on work for the r8a7791 SoC by Laurent Pinchart.
> 
> Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

> ---
> v3
> * As suggested by Laurent Pinchart
>   - Consolidate R8A7779_CLK_HSPI{0,1,2} into R8A7779_CLK_HSPI
>   - Correct inverted indexes of R8A7779_CLK_TMU{1,2}
>   - Consolidate R8A7779_CLK_{E,O}HCI{0,1} into R8A7779_CLK_USB{0,1}
>   - Add ethernet, MMC and HSCIF entries
>   - Replace R8A7779_SCIF6 with R8A7779_CLK_SCIF5
> 
> * Add R8A7779_CLK_PCIE
> 
> v2
> * No change
> ---
>  include/dt-bindings/clock/r8a7779-clock.h | 63
> +++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+)
>  create mode 100644 include/dt-bindings/clock/r8a7779-clock.h
> 
> diff --git a/include/dt-bindings/clock/r8a7779-clock.h
> b/include/dt-bindings/clock/r8a7779-clock.h new file mode 100644
> index 0000000..8ab8007
> --- /dev/null
> +++ b/include/dt-bindings/clock/r8a7779-clock.h
> @@ -0,0 +1,63 @@
> +/*
> + * Copyright (C) 2013  Horms Solutions Ltd.
> + *
> + * Contact: Simon Horman <horms@verge.net.au>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +
> +#ifndef __DT_BINDINGS_CLOCK_R8A7779_H__
> +#define __DT_BINDINGS_CLOCK_R8A7779_H__
> +
> +/* CPG */
> +#define R8A7779_CLK_PLLA	0
> +#define R8A7779_CLK_Z		1
> +#define R8A7779_CLK_ZS		2
> +#define R8A7779_CLK_S		3
> +#define R8A7779_CLK_S1		4
> +#define R8A7779_CLK_P		5
> +#define R8A7779_CLK_OUT		6
> +
> +/* MSTP 0 */
> +#define R8A7779_CLK_HSPI	7
> +#define R8A7779_CLK_TMU2	14
> +#define R8A7779_CLK_TMU1	15
> +#define R8A7779_CLK_TMU0	16
> +#define R8A7779_CLK_HSCIF1	18
> +#define R8A7779_CLK_HSCIF0	19
> +#define R8A7779_CLK_SCIF5	21
> +#define R8A7779_CLK_SCIF4	22
> +#define R8A7779_CLK_SCIF3	23
> +#define R8A7779_CLK_SCIF2	24
> +#define R8A7779_CLK_SCIF1	25
> +#define R8A7779_CLK_SCIF0	26
> +#define R8A7779_CLK_I2C3	27
> +#define R8A7779_CLK_I2C2	28
> +#define R8A7779_CLK_I2C1	29
> +#define R8A7779_CLK_I2C0	30
> +
> +/* MSTP 1 */
> +#define R8A7779_CLK_USB01	0
> +#define R8A7779_CLK_USB2	1
> +#define R8A7779_CLK_DU		3
> +#define R8A7779_CLK_VIN2	8
> +#define R8A7779_CLK_VIN1	9
> +#define R8A7779_CLK_VIN0	10
> +#define R8A7779_CLK_ETHER	14
> +#define R8A7779_CLK_SATA	15
> +#define R8A7779_CLK_PCIE	16
> +#define R8A7779_CLK_VIN3	20
> +
> +/* MSTP 3 */
> +#define R8A7779_CLK_SDHI3	20
> +#define R8A7779_CLK_SDHI2	21
> +#define R8A7779_CLK_SDHI1	22
> +#define R8A7779_CLK_SDHI0	23
> +#define R8A7779_CLK_MMC1	30
> +#define R8A7779_CLK_MMC0	31
> +
> +
> +#endif /* __DT_BINDINGS_CLOCK_R8A7779_H__ */

-- 
Regards,

Laurent Pinchart

[PATCH v3 03/20] ARM: shmobile: r8a7779: Add clock index macros for DT sources

[Laurent Pinchart]

Hi Simon,

Thank you for the patch.

On Wednesday 26 February 2014 16:33:19 Simon Horman wrote:
> Add macros usable by device tree sources to reference r8a7779 clocks by
> index.
> 
> Based on work for the r8a7791 SoC by Laurent Pinchart.
> 
> Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

> ---
> v3
> * As suggested by Laurent Pinchart
>   - Consolidate R8A7779_CLK_HSPI{0,1,2} into R8A7779_CLK_HSPI
>   - Correct inverted indexes of R8A7779_CLK_TMU{1,2}
>   - Consolidate R8A7779_CLK_{E,O}HCI{0,1} into R8A7779_CLK_USB{0,1}
>   - Add ethernet, MMC and HSCIF entries
>   - Replace R8A7779_SCIF6 with R8A7779_CLK_SCIF5
> 
> * Add R8A7779_CLK_PCIE
> 
> v2
> * No change
> ---
>  include/dt-bindings/clock/r8a7779-clock.h | 63
> +++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+)
>  create mode 100644 include/dt-bindings/clock/r8a7779-clock.h
> 
> diff --git a/include/dt-bindings/clock/r8a7779-clock.h
> b/include/dt-bindings/clock/r8a7779-clock.h new file mode 100644
> index 0000000..8ab8007
> --- /dev/null
> +++ b/include/dt-bindings/clock/r8a7779-clock.h
> @@ -0,0 +1,63 @@
> +/*
> + * Copyright (C) 2013  Horms Solutions Ltd.
> + *
> + * Contact: Simon Horman <horms@verge.net.au>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +
> +#ifndef __DT_BINDINGS_CLOCK_R8A7779_H__
> +#define __DT_BINDINGS_CLOCK_R8A7779_H__
> +
> +/* CPG */
> +#define R8A7779_CLK_PLLA	0
> +#define R8A7779_CLK_Z		1
> +#define R8A7779_CLK_ZS		2
> +#define R8A7779_CLK_S		3
> +#define R8A7779_CLK_S1		4
> +#define R8A7779_CLK_P		5
> +#define R8A7779_CLK_OUT		6
> +
> +/* MSTP 0 */
> +#define R8A7779_CLK_HSPI	7
> +#define R8A7779_CLK_TMU2	14
> +#define R8A7779_CLK_TMU1	15
> +#define R8A7779_CLK_TMU0	16
> +#define R8A7779_CLK_HSCIF1	18
> +#define R8A7779_CLK_HSCIF0	19
> +#define R8A7779_CLK_SCIF5	21
> +#define R8A7779_CLK_SCIF4	22
> +#define R8A7779_CLK_SCIF3	23
> +#define R8A7779_CLK_SCIF2	24
> +#define R8A7779_CLK_SCIF1	25
> +#define R8A7779_CLK_SCIF0	26
> +#define R8A7779_CLK_I2C3	27
> +#define R8A7779_CLK_I2C2	28
> +#define R8A7779_CLK_I2C1	29
> +#define R8A7779_CLK_I2C0	30
> +
> +/* MSTP 1 */
> +#define R8A7779_CLK_USB01	0
> +#define R8A7779_CLK_USB2	1
> +#define R8A7779_CLK_DU		3
> +#define R8A7779_CLK_VIN2	8
> +#define R8A7779_CLK_VIN1	9
> +#define R8A7779_CLK_VIN0	10
> +#define R8A7779_CLK_ETHER	14
> +#define R8A7779_CLK_SATA	15
> +#define R8A7779_CLK_PCIE	16
> +#define R8A7779_CLK_VIN3	20
> +
> +/* MSTP 3 */
> +#define R8A7779_CLK_SDHI3	20
> +#define R8A7779_CLK_SDHI2	21
> +#define R8A7779_CLK_SDHI1	22
> +#define R8A7779_CLK_SDHI0	23
> +#define R8A7779_CLK_MMC1	30
> +#define R8A7779_CLK_MMC0	31
> +
> +
> +#endif /* __DT_BINDINGS_CLOCK_R8A7779_H__ */

-- 
Regards,

Laurent Pinchart

Re: [PATCH v3 01/20] clk: shmobile: r8a7779: Add clocks support

[Laurent Pinchart]

Hi Simon,

Two more small comments.

On Wednesday 26 February 2014 13:53:17 Laurent Pinchart wrote:
> On Wednesday 26 February 2014 16:33:17 Simon Horman wrote:
> > The R8A7779 SoC has several clocks that are too custom to be supported in
> > a generic driver. Those clocks can be divided in two categories:
> > 
> > - Fixed rate clocks with multiplier and divisor set according to boot
> >   mode configuration
> > 
> > - Custom divider clocks with SoC-specific divider values
> > 
> > This driver supports both.
> 
> Looking at the R8A7779 datasheet it looks like we only have fixed rate
> clocks, without any configurable divider clock. Did I miss something ?
> 
> > Based on work for R-Car Gen2 SoCs by Laurent Pinchart.
> > 
> > Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> > 
> > ---
> > v3
> > * As suggested by Laurent Pinchart
> > 
> >   - Added external clock input
> >   - Use PLLA ratio set bu MD11 and MD12
> >   - Add _div suffixes of fields of struct cpt_clk_config
> >   - Register PLLA as a fixed factor clock
> >   - Use sizeof() instead of sizeof
> >   - Use num_clks instead of CPG_NUM_CLOCKS in r8a7779_cpg_clocks_init()
> >   
> >   - I kept this as r8a7779 binding rather than moving to a R-Car Gen1
> >   
> >     binding which could be shared with other SoCs as I do not believe that
> >     the SoCs is are sufficiently similar.
> 
> I had a look at the M1 datasheet and I still find its CPG very similar with
> the H1 CPG. The PLLA multiplier and divider are different, but if you look
> closely, they're both exactly twice the value compared to H1, so there's no
> difference in practice.
> 
> What differences do you see that would make it impractical to share a single
> driver for both ?
> 
> > ---
> > 
> >  .../bindings/clock/renesas,r8a7779-cpg-clocks.txt  |  26 +++
> >  drivers/clk/shmobile/Makefile                      |   1 +
> >  drivers/clk/shmobile/clk-r8a7779.c                 | 191
> >  ++++++++++++++++++
> >  include/linux/clk/shmobile.h                       |   3 +
> >  4 files changed, 221 insertions(+)
> >  create mode 100644
> > 
> > Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
> > create mode 100644 drivers/clk/shmobile/clk-r8a7779.c
> > 
> > diff --git
> > a/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
> > b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
> > new file mode 100644
> > index 0000000..1461323
> > --- /dev/null
> > +++
> > b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
> > @@ -0,0 +1,26 @@
> > +* Renesas R8A7779 Clock Pulse Generator (CPG)
> > +
> > +The CPG generates core clocks for the R8A7779. It includes one PLL and
> > +and several fixed ratio dividers
> > +
> > +Required Properties:
> > +
> > +  - compatible: Must be "renesas,r8a7779-cpg-clocks"
> > +  - reg: Base address and length of the memory resource used by the CPG
> > +
> > +  - clocks: Reference to the parent clock
> > +  - #clock-cells: Must be 1
> > +  - clock-output-names: The names of the clocks. Supported clocks are
> > "plla",
> > +    "z", "zs", "s", "s1", "p", "out".
> 
> What about clki, clks3, clks4, clkb and clkg ? Should pllb be exposed as
> well ?

I spoke too fast, clki, clks3, clks4 and clkg are fixed factor clocks 
expressed in DT, my bad. What about clkb though ?

> 
> > +Example
> > +-------
> > +
> > +	cpg_clocks: cpg_clocks@ffc80000 {
> > +		compatible = "renesas,r8a7779-cpg-clocks";
> > +		reg = <0 0xffc80000 0 0x80>;
> 
> Shouldn't the range be restricted not to include the MSTP registers ? 0x30
> should be enough.
> 
> > +		clocks = <&extal_clk>;
> > +		#clock-cells = <1>;
> > +		clock-output-names = "plla", "z", "zs", "s", "s1", "p", "out";
> > +	};
> > diff --git a/drivers/clk/shmobile/Makefile b/drivers/clk/shmobile/Makefile
> > index 9ecef14..2121ba0 100644
> > --- a/drivers/clk/shmobile/Makefile
> > +++ b/drivers/clk/shmobile/Makefile
> > @@ -1,4 +1,5 @@
> > 
> >  obj-$(CONFIG_ARCH_EMEV2)		+= clk-emev2.o
> > 
> > +obj-$(CONFIG_ARCH_R8A7779)		+= clk-r8a7779.o
> > 
> >  obj-$(CONFIG_ARCH_R8A7790)		+= clk-rcar-gen2.o
> >  obj-$(CONFIG_ARCH_R8A7791)		+= clk-rcar-gen2.o
> >  obj-$(CONFIG_ARCH_SHMOBILE_MULTI)	+= clk-div6.o
> > 
> > diff --git a/drivers/clk/shmobile/clk-r8a7779.c
> > b/drivers/clk/shmobile/clk-r8a7779.c new file mode 100644
> > index 0000000..2ca2d67
> > --- /dev/null
> > +++ b/drivers/clk/shmobile/clk-r8a7779.c
> > @@ -0,0 +1,191 @@
> > +/*
> > + * r8a7779 Core CPG Clocks
> > + *
> > + * Copyright (C) 2013, 2014 Horms Solutions Ltd.
> > + *
> > + * Contact: Simon Horman <horms@verge.net.au>
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation; version 2 of the License.
> > + */
> > +
> > +#include <linux/clk-provider.h>
> > +#include <linux/clkdev.h>
> > +#include <linux/clk/shmobile.h>
> > +#include <linux/init.h>
> > +#include <linux/kernel.h>
> > +#include <linux/of.h>
> > +#include <linux/of_address.h>
> > +#include <linux/spinlock.h>
> > +
> > +#include <dt-bindings/clock/r8a7779-clock.h>
> > +
> > +#define CPG_NUM_CLOCKS			(R8A7779_CLK_OUT + 1)
> > +
> > +struct r8a7779_cpg {
> > +	struct clk_onecell_data data;
> > +	spinlock_t lock;
> > +	void __iomem *reg;
> > +};
> > +
> > +/*
> > --------------------------------------------------------------------------
> > -
> > -- + * CPG Clock Data
> > + */
> > +
> > +/*
> > + *		MD1 = 1			MD1 = 0
> > + *		(PLLA = 1500)		(PLLA = 1600)
> > + *		(MHz)			(MHz)
> > + *------------------------------------------------+--------------------
> > + * clkz		1000   (2/3)		800   (1/2)
> > + * clkzs	 250   (1/6)		200   (1/8)
> > + * clki		 750   (1/2)		800   (1/2)
> > + * clks		 250   (1/6)		200   (1/8)
> > + * clks1	 125   (1/12)		100   (1/16)
> > + * clks3	 187.5 (1/8)		200   (1/8)
> > + * clks4	  93.7 (1/16)		100   (1/16)
> > + * clkp		  62.5 (1/24)		 50   (1/32)
> > + * clkg		  62.5 (1/24)		 66.6 (1/24)
> > + * clkb, CLKOUT
> > + * (MD2 = 0)	  62.5 (1/24)		 66.6 (1/24)
> > + * (MD2 = 1)	  41.6 (1/36)		 50   (1/32)
> > + */
> > +
> > +#define CPG_CLK_CONFIG_INDEX(md)	(((md) & (BIT(1)|BIT(2))) >> 1)
> > +
> > +struct cpg_clk_config {
> > +	unsigned int z_mult;
> > +	unsigned int z_div;
> > +	unsigned int zs_and_s_div;
> > +	unsigned int s1_div;
> > +	unsigned int p_div;
> > +	unsigned int out_div;
> > +};
> > +
> > +static const struct cpg_clk_config cpg_clk_configs[4] __initconst = {
> > +	{ 1, 2, 8, 16, 32, 24 },
> > +	{ 1, 2, 8, 16, 32, 24 },
> > +	{ 2, 3, 6, 12, 24, 36 },
> > +	{ 2, 3, 6, 12, 24, 32 },
> > +};
> > +
> > +/*
> > + *   MD		PLLA Ratio
> > + * 12 11
> > + *------------------------
> > + * 0  0		x42
> > + * 0  1		x48
> > + * 1  0		x56
> > + * 1  1		x64
> > + */
> > +#define CPG_PLL_CONFIG_INDEX(md)	((((md) & BIT(14)) >> 12) | \
> > +					 (((md) & BIT(13)) >> 12) | \
> > +					 (((md) & BIT(19)) >> 19))
> > +struct cpg_pll_config {
> > +	unsigned int extal_div;
> > +	unsigned int pll1_mult;
> > +	unsigned int pll3_mult;
> > +};
> > +
> > +#define CPG_PLLA_MULT_INDEX(md)	(((md) & (BIT(12)|BIT(11))) >> 11)
> > +
> > +static const unsigned int cpg_plla_mult[4] __initconst = { 42, 48, 56, 64
> > };
> > +
> > +/*
> > ------------------------------------------------------------------------
> > + * Initialization
> > + */
> > +
> > +static u32 cpg_mode __initdata;
> > +
> > +static struct clk * __init
> > +r8a7779_cpg_register_clock(struct device_node *np, struct r8a7779_cpg
> > *cpg, +			   const struct cpg_clk_config *config,
> > +			   unsigned int plla_mult, const char *name)
> > +{
> > +	const char *parent_name = "plla";
> > +	unsigned int mult = 1;
> > +	unsigned int div = 1;
> > +
> > +	if (!strcmp(name, "plla")) {
> > +		parent_name = of_clk_get_parent_name(np, 0);
> > +		mult = plla_mult;
> > +	} else if (!strcmp(name, "z")) {
> > +		div = config->z_div;
> > +		mult = config->z_mult;
> > +	} else if (!strcmp(name, "zs") || !strcmp(name, "s")) {
> > +		div = config->zs_and_s_div;
> > +	} else if (!strcmp(name, "s1")) {
> > +		div = config->s1_div;
> > +	} else if (!strcmp(name, "p")) {
> > +		div = config->p_div;
> > +	} else if (!strcmp(name, "out")) {
> > +		div = config->out_div;
> > +	}
> 
> You're missing an
> 
> 	else {
> 		return ERR_PTR5-EINVAL);
> 	}
> 
> I was tempted to say that it would make sense to read the div values from
> the FRQMR register instead and remove the need to pass the boot mode bits
> to the driver, but we need them for the PLLA multiplier anyway :-/
> 
> > +
> > +	return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, 
div);
> > +}
> > +
> > +static void __init r8a7779_cpg_clocks_init(struct device_node *np)
> > +{
> > +	const struct cpg_clk_config *config;
> > +	struct r8a7779_cpg *cpg;
> > +	struct clk **clks;
> > +	unsigned int i, plla_mult;
> > +	int num_clks;
> > +
> > +	num_clks = of_property_count_strings(np, "clock-output-names");
> > +	if (num_clks < 0) {
> > +		pr_err("%s: failed to count clocks\n", __func__);
> > +		return;
> > +	}
> > +
> > +	cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
> > +	clks = kzalloc(CPG_NUM_CLOCKS * sizeof(*clks), GFP_KERNEL);
> > +	if (cpg = NULL || clks = NULL) {
> > +		/* We're leaking memory on purpose, there's no point in cleaning
> > +		 * up as the system won't boot anyway.
> > +		 */
> > +		pr_err("%s: failed to allocate cpg\n", __func__);
> > +		return;
> > +	}
> > +
> > +	spin_lock_init(&cpg->lock);
> > +
> > +	cpg->data.clks = clks;
> > +	cpg->data.clk_num = num_clks;
> > +
> > +	cpg->reg = of_iomap(np, 0);
> > +	if (WARN_ON(cpg->reg = NULL))
> > +		return;

As the driver doesn't access any of the CPG registers this could even be 
removed.

> > +
> > +	config = &cpg_clk_configs[CPG_CLK_CONFIG_INDEX(cpg_mode)];
> > +	plla_mult = cpg_plla_mult[CPG_PLLA_MULT_INDEX(cpg_mode)];
> 
> Given that plla_mult is only used for a single clock, I would move that
> inside the if (!strcmp(name, "plla")) { } above.
> 
> > +
> > +	for (i = 0; i < num_clks; ++i) {
> > +		const char *name;
> > +		struct clk *clk;
> > +
> > +		of_property_read_string_index(np, "clock-output-names", i,
> > +					      &name);
> > +
> > +		clk = r8a7779_cpg_register_clock(np, cpg, config,
> > +						 plla_mult, name);
> > +		if (IS_ERR(clk))
> > +			pr_err("%s: failed to register %s %s clock (%ld)\n",
> > +			       __func__, np->name, name, PTR_ERR(clk));
> > +		else
> > +			cpg->data.clks[i] = clk;
> > +	}
> > +
> > +	of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
> > +}
> > +CLK_OF_DECLARE(r8a7779_cpg_clks, "renesas,r8a7779-cpg-clocks",
> > +	       r8a7779_cpg_clocks_init);
> > +
> > +void __init r8a7779_clocks_init(u32 mode)
> > +{
> > +	cpg_mode = mode;
> > +
> > +	of_clk_init(NULL);
> > +}
> > diff --git a/include/linux/clk/shmobile.h b/include/linux/clk/shmobile.h
> > index f9bf080..7667f49 100644
> > --- a/include/linux/clk/shmobile.h
> > +++ b/include/linux/clk/shmobile.h
> > @@ -1,7 +1,9 @@
> >  /*
> >   * Copyright 2013 Ideas On Board SPRL
> > + * Copyright 2013 Horms Solutions Ltd.
> 
> 2014 ?
> 
> >   *
> >   * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> > + * Contact: Simon Horman <horms@verge.net.au>
> >   *
> >   * This program is free software; you can redistribute it and/or modify
> >   * it under the terms of the GNU General Public License as published by
> > @@ -14,6 +16,7 @@
> > 
> >  #include <linux/types.h>
> > 
> > +void r8a7779_clocks_init(u32 mode);
> >  void rcar_gen2_clocks_init(u32 mode);
> >  
> >  #endif

-- 
Regards,

Laurent Pinchart

[PATCH v3 01/20] clk: shmobile: r8a7779: Add clocks support

[Laurent Pinchart]

Hi Simon,

Two more small comments.

On Wednesday 26 February 2014 13:53:17 Laurent Pinchart wrote:
> On Wednesday 26 February 2014 16:33:17 Simon Horman wrote:
> > The R8A7779 SoC has several clocks that are too custom to be supported in
> > a generic driver. Those clocks can be divided in two categories:
> > 
> > - Fixed rate clocks with multiplier and divisor set according to boot
> >   mode configuration
> > 
> > - Custom divider clocks with SoC-specific divider values
> > 
> > This driver supports both.
> 
> Looking at the R8A7779 datasheet it looks like we only have fixed rate
> clocks, without any configurable divider clock. Did I miss something ?
> 
> > Based on work for R-Car Gen2 SoCs by Laurent Pinchart.
> > 
> > Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> > 
> > ---
> > v3
> > * As suggested by Laurent Pinchart
> > 
> >   - Added external clock input
> >   - Use PLLA ratio set bu MD11 and MD12
> >   - Add _div suffixes of fields of struct cpt_clk_config
> >   - Register PLLA as a fixed factor clock
> >   - Use sizeof() instead of sizeof
> >   - Use num_clks instead of CPG_NUM_CLOCKS in r8a7779_cpg_clocks_init()
> >   
> >   - I kept this as r8a7779 binding rather than moving to a R-Car Gen1
> >   
> >     binding which could be shared with other SoCs as I do not believe that
> >     the SoCs is are sufficiently similar.
> 
> I had a look at the M1 datasheet and I still find its CPG very similar with
> the H1 CPG. The PLLA multiplier and divider are different, but if you look
> closely, they're both exactly twice the value compared to H1, so there's no
> difference in practice.
> 
> What differences do you see that would make it impractical to share a single
> driver for both ?
> 
> > ---
> > 
> >  .../bindings/clock/renesas,r8a7779-cpg-clocks.txt  |  26 +++
> >  drivers/clk/shmobile/Makefile                      |   1 +
> >  drivers/clk/shmobile/clk-r8a7779.c                 | 191
> >  ++++++++++++++++++
> >  include/linux/clk/shmobile.h                       |   3 +
> >  4 files changed, 221 insertions(+)
> >  create mode 100644
> > 
> > Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
> > create mode 100644 drivers/clk/shmobile/clk-r8a7779.c
> > 
> > diff --git
> > a/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
> > b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
> > new file mode 100644
> > index 0000000..1461323
> > --- /dev/null
> > +++
> > b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
> > @@ -0,0 +1,26 @@
> > +* Renesas R8A7779 Clock Pulse Generator (CPG)
> > +
> > +The CPG generates core clocks for the R8A7779. It includes one PLL and
> > +and several fixed ratio dividers
> > +
> > +Required Properties:
> > +
> > +  - compatible: Must be "renesas,r8a7779-cpg-clocks"
> > +  - reg: Base address and length of the memory resource used by the CPG
> > +
> > +  - clocks: Reference to the parent clock
> > +  - #clock-cells: Must be 1
> > +  - clock-output-names: The names of the clocks. Supported clocks are
> > "plla",
> > +    "z", "zs", "s", "s1", "p", "out".
> 
> What about clki, clks3, clks4, clkb and clkg ? Should pllb be exposed as
> well ?

I spoke too fast, clki, clks3, clks4 and clkg are fixed factor clocks 
expressed in DT, my bad. What about clkb though ?

> 
> > +Example
> > +-------
> > +
> > +	cpg_clocks: cpg_clocks at ffc80000 {
> > +		compatible = "renesas,r8a7779-cpg-clocks";
> > +		reg = <0 0xffc80000 0 0x80>;
> 
> Shouldn't the range be restricted not to include the MSTP registers ? 0x30
> should be enough.
> 
> > +		clocks = <&extal_clk>;
> > +		#clock-cells = <1>;
> > +		clock-output-names = "plla", "z", "zs", "s", "s1", "p", "out";
> > +	};
> > diff --git a/drivers/clk/shmobile/Makefile b/drivers/clk/shmobile/Makefile
> > index 9ecef14..2121ba0 100644
> > --- a/drivers/clk/shmobile/Makefile
> > +++ b/drivers/clk/shmobile/Makefile
> > @@ -1,4 +1,5 @@
> > 
> >  obj-$(CONFIG_ARCH_EMEV2)		+= clk-emev2.o
> > 
> > +obj-$(CONFIG_ARCH_R8A7779)		+= clk-r8a7779.o
> > 
> >  obj-$(CONFIG_ARCH_R8A7790)		+= clk-rcar-gen2.o
> >  obj-$(CONFIG_ARCH_R8A7791)		+= clk-rcar-gen2.o
> >  obj-$(CONFIG_ARCH_SHMOBILE_MULTI)	+= clk-div6.o
> > 
> > diff --git a/drivers/clk/shmobile/clk-r8a7779.c
> > b/drivers/clk/shmobile/clk-r8a7779.c new file mode 100644
> > index 0000000..2ca2d67
> > --- /dev/null
> > +++ b/drivers/clk/shmobile/clk-r8a7779.c
> > @@ -0,0 +1,191 @@
> > +/*
> > + * r8a7779 Core CPG Clocks
> > + *
> > + * Copyright (C) 2013, 2014 Horms Solutions Ltd.
> > + *
> > + * Contact: Simon Horman <horms@verge.net.au>
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation; version 2 of the License.
> > + */
> > +
> > +#include <linux/clk-provider.h>
> > +#include <linux/clkdev.h>
> > +#include <linux/clk/shmobile.h>
> > +#include <linux/init.h>
> > +#include <linux/kernel.h>
> > +#include <linux/of.h>
> > +#include <linux/of_address.h>
> > +#include <linux/spinlock.h>
> > +
> > +#include <dt-bindings/clock/r8a7779-clock.h>
> > +
> > +#define CPG_NUM_CLOCKS			(R8A7779_CLK_OUT + 1)
> > +
> > +struct r8a7779_cpg {
> > +	struct clk_onecell_data data;
> > +	spinlock_t lock;
> > +	void __iomem *reg;
> > +};
> > +
> > +/*
> > --------------------------------------------------------------------------
> > -
> > -- + * CPG Clock Data
> > + */
> > +
> > +/*
> > + *		MD1 = 1			MD1 = 0
> > + *		(PLLA = 1500)		(PLLA = 1600)
> > + *		(MHz)			(MHz)
> > + *------------------------------------------------+--------------------
> > + * clkz		1000   (2/3)		800   (1/2)
> > + * clkzs	 250   (1/6)		200   (1/8)
> > + * clki		 750   (1/2)		800   (1/2)
> > + * clks		 250   (1/6)		200   (1/8)
> > + * clks1	 125   (1/12)		100   (1/16)
> > + * clks3	 187.5 (1/8)		200   (1/8)
> > + * clks4	  93.7 (1/16)		100   (1/16)
> > + * clkp		  62.5 (1/24)		 50   (1/32)
> > + * clkg		  62.5 (1/24)		 66.6 (1/24)
> > + * clkb, CLKOUT
> > + * (MD2 = 0)	  62.5 (1/24)		 66.6 (1/24)
> > + * (MD2 = 1)	  41.6 (1/36)		 50   (1/32)
> > + */
> > +
> > +#define CPG_CLK_CONFIG_INDEX(md)	(((md) & (BIT(1)|BIT(2))) >> 1)
> > +
> > +struct cpg_clk_config {
> > +	unsigned int z_mult;
> > +	unsigned int z_div;
> > +	unsigned int zs_and_s_div;
> > +	unsigned int s1_div;
> > +	unsigned int p_div;
> > +	unsigned int out_div;
> > +};
> > +
> > +static const struct cpg_clk_config cpg_clk_configs[4] __initconst = {
> > +	{ 1, 2, 8, 16, 32, 24 },
> > +	{ 1, 2, 8, 16, 32, 24 },
> > +	{ 2, 3, 6, 12, 24, 36 },
> > +	{ 2, 3, 6, 12, 24, 32 },
> > +};
> > +
> > +/*
> > + *   MD		PLLA Ratio
> > + * 12 11
> > + *------------------------
> > + * 0  0		x42
> > + * 0  1		x48
> > + * 1  0		x56
> > + * 1  1		x64
> > + */
> > +#define CPG_PLL_CONFIG_INDEX(md)	((((md) & BIT(14)) >> 12) | \
> > +					 (((md) & BIT(13)) >> 12) | \
> > +					 (((md) & BIT(19)) >> 19))
> > +struct cpg_pll_config {
> > +	unsigned int extal_div;
> > +	unsigned int pll1_mult;
> > +	unsigned int pll3_mult;
> > +};
> > +
> > +#define CPG_PLLA_MULT_INDEX(md)	(((md) & (BIT(12)|BIT(11))) >> 11)
> > +
> > +static const unsigned int cpg_plla_mult[4] __initconst = { 42, 48, 56, 64
> > };
> > +
> > +/*
> > ------------------------------------------------------------------------
> > + * Initialization
> > + */
> > +
> > +static u32 cpg_mode __initdata;
> > +
> > +static struct clk * __init
> > +r8a7779_cpg_register_clock(struct device_node *np, struct r8a7779_cpg
> > *cpg, +			   const struct cpg_clk_config *config,
> > +			   unsigned int plla_mult, const char *name)
> > +{
> > +	const char *parent_name = "plla";
> > +	unsigned int mult = 1;
> > +	unsigned int div = 1;
> > +
> > +	if (!strcmp(name, "plla")) {
> > +		parent_name = of_clk_get_parent_name(np, 0);
> > +		mult = plla_mult;
> > +	} else if (!strcmp(name, "z")) {
> > +		div = config->z_div;
> > +		mult = config->z_mult;
> > +	} else if (!strcmp(name, "zs") || !strcmp(name, "s")) {
> > +		div = config->zs_and_s_div;
> > +	} else if (!strcmp(name, "s1")) {
> > +		div = config->s1_div;
> > +	} else if (!strcmp(name, "p")) {
> > +		div = config->p_div;
> > +	} else if (!strcmp(name, "out")) {
> > +		div = config->out_div;
> > +	}
> 
> You're missing an
> 
> 	else {
> 		return ERR_PTR5-EINVAL);
> 	}
> 
> I was tempted to say that it would make sense to read the div values from
> the FRQMR register instead and remove the need to pass the boot mode bits
> to the driver, but we need them for the PLLA multiplier anyway :-/
> 
> > +
> > +	return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, 
div);
> > +}
> > +
> > +static void __init r8a7779_cpg_clocks_init(struct device_node *np)
> > +{
> > +	const struct cpg_clk_config *config;
> > +	struct r8a7779_cpg *cpg;
> > +	struct clk **clks;
> > +	unsigned int i, plla_mult;
> > +	int num_clks;
> > +
> > +	num_clks = of_property_count_strings(np, "clock-output-names");
> > +	if (num_clks < 0) {
> > +		pr_err("%s: failed to count clocks\n", __func__);
> > +		return;
> > +	}
> > +
> > +	cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
> > +	clks = kzalloc(CPG_NUM_CLOCKS * sizeof(*clks), GFP_KERNEL);
> > +	if (cpg == NULL || clks == NULL) {
> > +		/* We're leaking memory on purpose, there's no point in cleaning
> > +		 * up as the system won't boot anyway.
> > +		 */
> > +		pr_err("%s: failed to allocate cpg\n", __func__);
> > +		return;
> > +	}
> > +
> > +	spin_lock_init(&cpg->lock);
> > +
> > +	cpg->data.clks = clks;
> > +	cpg->data.clk_num = num_clks;
> > +
> > +	cpg->reg = of_iomap(np, 0);
> > +	if (WARN_ON(cpg->reg == NULL))
> > +		return;

As the driver doesn't access any of the CPG registers this could even be 
removed.

> > +
> > +	config = &cpg_clk_configs[CPG_CLK_CONFIG_INDEX(cpg_mode)];
> > +	plla_mult = cpg_plla_mult[CPG_PLLA_MULT_INDEX(cpg_mode)];
> 
> Given that plla_mult is only used for a single clock, I would move that
> inside the if (!strcmp(name, "plla")) { } above.
> 
> > +
> > +	for (i = 0; i < num_clks; ++i) {
> > +		const char *name;
> > +		struct clk *clk;
> > +
> > +		of_property_read_string_index(np, "clock-output-names", i,
> > +					      &name);
> > +
> > +		clk = r8a7779_cpg_register_clock(np, cpg, config,
> > +						 plla_mult, name);
> > +		if (IS_ERR(clk))
> > +			pr_err("%s: failed to register %s %s clock (%ld)\n",
> > +			       __func__, np->name, name, PTR_ERR(clk));
> > +		else
> > +			cpg->data.clks[i] = clk;
> > +	}
> > +
> > +	of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
> > +}
> > +CLK_OF_DECLARE(r8a7779_cpg_clks, "renesas,r8a7779-cpg-clocks",
> > +	       r8a7779_cpg_clocks_init);
> > +
> > +void __init r8a7779_clocks_init(u32 mode)
> > +{
> > +	cpg_mode = mode;
> > +
> > +	of_clk_init(NULL);
> > +}
> > diff --git a/include/linux/clk/shmobile.h b/include/linux/clk/shmobile.h
> > index f9bf080..7667f49 100644
> > --- a/include/linux/clk/shmobile.h
> > +++ b/include/linux/clk/shmobile.h
> > @@ -1,7 +1,9 @@
> >  /*
> >   * Copyright 2013 Ideas On Board SPRL
> > + * Copyright 2013 Horms Solutions Ltd.
> 
> 2014 ?
> 
> >   *
> >   * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> > + * Contact: Simon Horman <horms@verge.net.au>
> >   *
> >   * This program is free software; you can redistribute it and/or modify
> >   * it under the terms of the GNU General Public License as published by
> > @@ -14,6 +16,7 @@
> > 
> >  #include <linux/types.h>
> > 
> > +void r8a7779_clocks_init(u32 mode);
> >  void rcar_gen2_clocks_init(u32 mode);
> >  
> >  #endif

-- 
Regards,

Laurent Pinchart

Re: [PATCH v3 04/20] ARM: shmobile: r8a7779: Add clocks

[Laurent Pinchart]

Hi Simon,

Thank you for the patch.

On Wednesday 26 February 2014 16:33:20 Simon Horman wrote:
> Declare all core and MSTP clocks currently used by r8a7779-based boards.
> 
> Based on work by Laurent Pinchart for the r8a7790 and r8a7791 SoCs.
> 
> Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> 
> ---
> v3
> * As suggested by Laurent Pinchart
>   - Add and use extal_clk
>   - Fix bogus status register use for MSTP clocks
>   - Fix bogus mstp3_cls to use its own entries rather than
>     that of mstp1_clks
> 
> * Update to use "main" in cpg_clocks as per updated
>   binding in previous patch
> * Update for new, consolidated and renamed index macros
>   - R8A7779_CLK_ETHER
>   - R8A7779_CLK_HSCIF
>   - R8A7779_CLK_HSPI
>   - R8A7779_CLK_MMC0,1
>   - R8A7779_CLK_PCIE
>   - R8A7779_CLK_USB01,2
> ---
>  arch/arm/boot/dts/r8a7779.dtsi | 129 ++++++++++++++++++++++++++++++++++++++
>  1 file changed, 129 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
> index d0561d4..240a03e 100644
> --- a/arch/arm/boot/dts/r8a7779.dtsi
> +++ b/arch/arm/boot/dts/r8a7779.dtsi
> @@ -11,6 +11,7 @@
> 
>  /include/ "skeleton.dtsi"
> 
> +#include <dt-bindings/clock/r8a7779-clock.h>
>  #include <dt-bindings/interrupt-controller/irq.h>
> 
>  / {
> @@ -278,4 +279,132 @@
>  		interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
>  		status = "disabled";
>  	};
> +
> +	clocks {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		/* External root clock */
> +		extal_clk: extal_clk {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +			/* This value must be overriden by the board. */
> +			clock-frequency = <0>;
> +			clock-output-names = "extal";
> +		};
> +
> +		/* Special CPG clocks */
> +		cpg_clocks: cpg_clocks@0xe6150000 {
> +			compatible = "renesas,r8a7779-cpg-clocks";
> +			reg = <0 0xe6150000 0 0x1000>;
> +			clocks = <&extal_clk>;
> +			#clock-cells = <1>;
> +			clock-output-names = "plla", "z", "zs", "s",
> +					     "s1", "p", "out";
> +		};
> +
> +		/* Fixed factor clocks */
> +		i_clk: i_clk {
> +			compatible = "fixed-factor-clock";
> +			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
> +			#clock-cells = <0>;
> +			clock-div = <2>;
> +			clock-mult = <1>;
> +			clock-output-names = "i";
> +		};
> +		s3_clk: s3_clk {
> +			compatible = "fixed-factor-clock";
> +			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
> +			#clock-cells = <0>;
> +			clock-div = <8>;
> +			clock-mult = <1>;
> +			clock-output-names = "s3";
> +		};
> +		s4_clk: s4_clk {
> +			compatible = "fixed-factor-clock";
> +			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
> +			#clock-cells = <0>;
> +			clock-div = <16>;
> +			clock-mult = <1>;
> +			clock-output-names = "s4";
> +		};
> +		g_clk: g_clk {
> +			compatible = "fixed-factor-clock";
> +			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
> +			#clock-cells = <0>;
> +			clock-div = <24>;
> +			clock-mult = <1>;
> +			clock-output-names = "g";
> +		};
> +
> +		/* Gate clocks */
> +		mstp0_clks: mstp0_clks {
> +			compatible = "renesas,r8a7779-mstp-clocks", "renesas,cpg-mstp-
clocks";
> +			reg = <0 0xffc80030 0 4>;
> +			clocks = <&cpg_clocks R8A7779_CLK_P>,
> <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> <&cpg_clocks R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> <&cpg_clocks R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> <&cpg_clocks R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> <&cpg_clocks R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>;

Aren't the HSPI and HSCIF parent clocks clks ? Aren't the SCIF parent clocks 
clks1 ?

> +			#clock-cells = <1>;
> +			renesas,clock-indices = <
> +				R8A7779_CLK_HSPI R8A7779_CLK_TMU0 R8A7779_CLK_TMU0
> +				R8A7779_CLK_TMU0 R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
> +				R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2 R8A7779_CLK_SCIF1
> +				R8A7779_CLK_SCIF0 R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
> +				R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
> +			>;
> +			clock-output-names > +				"hspi", "tmu00", "tmu01",
> +				"tmu02", "scif5", "scif4",

The clock names should be tmu0, tmu1 and tmu2, not tmu00, tmu01 and tmu02.

> +				"scif3", "scif2", "scif1",
> +				"scif0", "i2c3", "i2c2",
> +				"i2c1", "i2c0";
> +		};
> +		mstp1_clks: mstp1_clks {
> +			compatible = "renesas,r8a7779-mstp-clocks", "renesas,cpg-mstp-
clocks";
> +			reg = <0 0xffc80034 0 4>, <0 0xffc80044 0 4>;
> +			clocks = <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks 
R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>;

Please verify the clock parents here as well.

> +			#clock-cells = <1>;
> +			renesas,clock-indices = <
> +				R8A7779_CLK_USB01 R8A7779_CLK_USB01
> +				R8A7779_CLK_USB2 R8A7779_CLK_USB2
> +				R8A7779_CLK_DU R8A7779_CLK_VIN2
> +				R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
> +				R8A7779_CLK_ETHER R8A7779_CLK_SATA
> +				R8A7779_CLK_PCIE R8A7779_CLK_VIN3
> +			>;
> +			clock-output-names > +				"ehci0", "ohci0",
> +				"ehci1", "ohci1",
> +				"du", "vin2",
> +				"vin1", "vin0",
> +				"ether", "sata",
> +				"pcie", "vin3";
> +		};
> +		mstp3_clks: mstp3_clks {
> +			compatible = "renesas,r8a7779-mstp-clocks", "renesas,cpg-mstp-
clocks";
> +			reg = <0 0xffc8003c 0 4>;
> +			clocks = <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks 
R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>;

Aren't the MMC and SDHI parent clocks clks4 ?

> +			#clock-cells = <1>;
> +			renesas,clock-indices = <
> +				R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
> +				R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
> +				R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
> +			>;
> +			clock-output-names > +				"sdhi3", "sdhi2",
> +				"sdhi1", "sdhi0",
> +				"mmc1", "mmc0";
> +		};
> +	};
>  };

-- 
Regards,

Laurent Pinchart

[PATCH v3 04/20] ARM: shmobile: r8a7779: Add clocks

[Laurent Pinchart]

Hi Simon,

Thank you for the patch.

On Wednesday 26 February 2014 16:33:20 Simon Horman wrote:
> Declare all core and MSTP clocks currently used by r8a7779-based boards.
> 
> Based on work by Laurent Pinchart for the r8a7790 and r8a7791 SoCs.
> 
> Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> 
> ---
> v3
> * As suggested by Laurent Pinchart
>   - Add and use extal_clk
>   - Fix bogus status register use for MSTP clocks
>   - Fix bogus mstp3_cls to use its own entries rather than
>     that of mstp1_clks
> 
> * Update to use "main" in cpg_clocks as per updated
>   binding in previous patch
> * Update for new, consolidated and renamed index macros
>   - R8A7779_CLK_ETHER
>   - R8A7779_CLK_HSCIF
>   - R8A7779_CLK_HSPI
>   - R8A7779_CLK_MMC0,1
>   - R8A7779_CLK_PCIE
>   - R8A7779_CLK_USB01,2
> ---
>  arch/arm/boot/dts/r8a7779.dtsi | 129 ++++++++++++++++++++++++++++++++++++++
>  1 file changed, 129 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
> index d0561d4..240a03e 100644
> --- a/arch/arm/boot/dts/r8a7779.dtsi
> +++ b/arch/arm/boot/dts/r8a7779.dtsi
> @@ -11,6 +11,7 @@
> 
>  /include/ "skeleton.dtsi"
> 
> +#include <dt-bindings/clock/r8a7779-clock.h>
>  #include <dt-bindings/interrupt-controller/irq.h>
> 
>  / {
> @@ -278,4 +279,132 @@
>  		interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
>  		status = "disabled";
>  	};
> +
> +	clocks {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		/* External root clock */
> +		extal_clk: extal_clk {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +			/* This value must be overriden by the board. */
> +			clock-frequency = <0>;
> +			clock-output-names = "extal";
> +		};
> +
> +		/* Special CPG clocks */
> +		cpg_clocks: cpg_clocks at 0xe6150000 {
> +			compatible = "renesas,r8a7779-cpg-clocks";
> +			reg = <0 0xe6150000 0 0x1000>;
> +			clocks = <&extal_clk>;
> +			#clock-cells = <1>;
> +			clock-output-names = "plla", "z", "zs", "s",
> +					     "s1", "p", "out";
> +		};
> +
> +		/* Fixed factor clocks */
> +		i_clk: i_clk {
> +			compatible = "fixed-factor-clock";
> +			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
> +			#clock-cells = <0>;
> +			clock-div = <2>;
> +			clock-mult = <1>;
> +			clock-output-names = "i";
> +		};
> +		s3_clk: s3_clk {
> +			compatible = "fixed-factor-clock";
> +			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
> +			#clock-cells = <0>;
> +			clock-div = <8>;
> +			clock-mult = <1>;
> +			clock-output-names = "s3";
> +		};
> +		s4_clk: s4_clk {
> +			compatible = "fixed-factor-clock";
> +			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
> +			#clock-cells = <0>;
> +			clock-div = <16>;
> +			clock-mult = <1>;
> +			clock-output-names = "s4";
> +		};
> +		g_clk: g_clk {
> +			compatible = "fixed-factor-clock";
> +			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
> +			#clock-cells = <0>;
> +			clock-div = <24>;
> +			clock-mult = <1>;
> +			clock-output-names = "g";
> +		};
> +
> +		/* Gate clocks */
> +		mstp0_clks: mstp0_clks {
> +			compatible = "renesas,r8a7779-mstp-clocks", "renesas,cpg-mstp-
clocks";
> +			reg = <0 0xffc80030 0 4>;
> +			clocks = <&cpg_clocks R8A7779_CLK_P>,
> <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> <&cpg_clocks R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> <&cpg_clocks R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> <&cpg_clocks R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> <&cpg_clocks R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>;

Aren't the HSPI and HSCIF parent clocks clks ? Aren't the SCIF parent clocks 
clks1 ?

> +			#clock-cells = <1>;
> +			renesas,clock-indices = <
> +				R8A7779_CLK_HSPI R8A7779_CLK_TMU0 R8A7779_CLK_TMU0
> +				R8A7779_CLK_TMU0 R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
> +				R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2 R8A7779_CLK_SCIF1
> +				R8A7779_CLK_SCIF0 R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
> +				R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
> +			>;
> +			clock-output-names =
> +				"hspi", "tmu00", "tmu01",
> +				"tmu02", "scif5", "scif4",

The clock names should be tmu0, tmu1 and tmu2, not tmu00, tmu01 and tmu02.

> +				"scif3", "scif2", "scif1",
> +				"scif0", "i2c3", "i2c2",
> +				"i2c1", "i2c0";
> +		};
> +		mstp1_clks: mstp1_clks {
> +			compatible = "renesas,r8a7779-mstp-clocks", "renesas,cpg-mstp-
clocks";
> +			reg = <0 0xffc80034 0 4>, <0 0xffc80044 0 4>;
> +			clocks = <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks 
R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>;

Please verify the clock parents here as well.

> +			#clock-cells = <1>;
> +			renesas,clock-indices = <
> +				R8A7779_CLK_USB01 R8A7779_CLK_USB01
> +				R8A7779_CLK_USB2 R8A7779_CLK_USB2
> +				R8A7779_CLK_DU R8A7779_CLK_VIN2
> +				R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
> +				R8A7779_CLK_ETHER R8A7779_CLK_SATA
> +				R8A7779_CLK_PCIE R8A7779_CLK_VIN3
> +			>;
> +			clock-output-names =
> +				"ehci0", "ohci0",
> +				"ehci1", "ohci1",
> +				"du", "vin2",
> +				"vin1", "vin0",
> +				"ether", "sata",
> +				"pcie", "vin3";
> +		};
> +		mstp3_clks: mstp3_clks {
> +			compatible = "renesas,r8a7779-mstp-clocks", "renesas,cpg-mstp-
clocks";
> +			reg = <0 0xffc8003c 0 4>;
> +			clocks = <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks 
R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>;

Aren't the MMC and SDHI parent clocks clks4 ?

> +			#clock-cells = <1>;
> +			renesas,clock-indices = <
> +				R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
> +				R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
> +				R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
> +			>;
> +			clock-output-names =
> +				"sdhi3", "sdhi2",
> +				"sdhi1", "sdhi0",
> +				"mmc1", "mmc0";
> +		};
> +	};
>  };

-- 
Regards,

Laurent Pinchart

Re: [PATCH v3 05/20] ARM: shmobile: Sync Marzen DTS with Marzen reference DTS

[Laurent Pinchart]

Hi Simon,

Thank you for the patch.

On Wednesday 26 February 2014 16:33:21 Simon Horman wrote:
> Copy the device nodes from Marzen reference into the Marzen device tree
> file. This will allow us to use a single DTS file regardless of kernel
> configuration. In case of legacy C board code the device nodes may or
> may not be used, but in the multiplatform case all the DT device nodes
> will be used.
> 
> Based on a similar change for the Lager board by Laurent Pinchart.
> 
> Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

> 
> ---
> v3
> * Updated for recent changes to Marzen reference DTS
> ---
>  arch/arm/boot/dts/r8a7779-marzen.dts | 93
> ++++++++++++++++++++++++++++++++++++ 1 file changed, 93 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts
> b/arch/arm/boot/dts/r8a7779-marzen.dts index a7af2c2..eda6240 100644
> --- a/arch/arm/boot/dts/r8a7779-marzen.dts
> +++ b/arch/arm/boot/dts/r8a7779-marzen.dts
> @@ -11,6 +11,8 @@
> 
>  /dts-v1/;
>  #include "r8a7779.dtsi"
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> 
>  / {
>  	model = "marzen";
> @@ -24,4 +26,95 @@
>  		device_type = "memory";
>  		reg = <0x60000000 0x40000000>;
>  	};
> +
> +	fixedregulator3v3: fixedregulator@0 {
> +		compatible = "regulator-fixed";
> +		regulator-name = "fixed-3.3V";
> +		regulator-min-microvolt = <3300000>;
> +		regulator-max-microvolt = <3300000>;
> +		regulator-boot-on;
> +		regulator-always-on;
> +	};
> +
> +	lan0@18000000 {
> +		compatible = "smsc,lan9220", "smsc,lan9115";
> +		reg = <0x18000000 0x100>;
> +		pinctrl-0 = <&lan0_pins>;
> +		pinctrl-names = "default";
> +
> +		phy-mode = "mii";
> +		interrupt-parent = <&irqpin0>;
> +		interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
> +		reg-io-width = <4>;
> +		vddvario-supply = <&fixedregulator3v3>;
> +		vdd33a-supply = <&fixedregulator3v3>;
> +	};
> +
> +	leds {
> +		compatible = "gpio-leds";
> +		led2 {
> +			gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
> +		};
> +		led3 {
> +			gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
> +		};
> +		led4 {
> +			gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;
> +		};
> +	};
> +};
> +
> +&irqpin0 {
> +	status = "okay";
> +};
> +
> +&pfc {
> +	pinctrl-0 = <&scif2_pins &scif4_pins>;
> +	pinctrl-names = "default";
> +
> +	lan0_pins: lan0 {
> +		intc {
> +			renesas,groups = "intc_irq1_b";
> +			renesas,function = "intc";
> +		};
> +		lbsc {
> +			renesas,groups = "lbsc_ex_cs0";
> +			renesas,function = "lbsc";
> +		};
> +	};
> +
> +	scif2_pins: serial2 {
> +		renesas,groups = "scif2_data_c";
> +		renesas,function = "scif2";
> +	};
> +
> +	scif4_pins: serial4 {
> +		renesas,groups = "scif4_data";
> +		renesas,function = "scif4";
> +	};
> +
> +	sdhi0_pins: sd0 {
> +		renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
> +		renesas,function = "sdhi0";
> +	};
> +
> +	hspi0_pins: hspi0 {
> +		renesas,groups = "hspi0";
> +		renesas,function = "hspi0";
> +	};
> +};
> +
> +&sdhi0 {
> +	pinctrl-0 = <&sdhi0_pins>;
> +	pinctrl-names = "default";
> +
> +	vmmc-supply = <&fixedregulator3v3>;
> +	bus-width = <4>;
> +	status = "okay";
> +};
> +
> +&hspi0 {
> +	pinctrl-0 = <&hspi0_pins>;
> +	pinctrl-names = "default";
> +	status = "okay";
>  };

-- 
Regards,

Laurent Pinchart

[PATCH v3 05/20] ARM: shmobile: Sync Marzen DTS with Marzen reference DTS

[Laurent Pinchart]

Hi Simon,

Thank you for the patch.

On Wednesday 26 February 2014 16:33:21 Simon Horman wrote:
> Copy the device nodes from Marzen reference into the Marzen device tree
> file. This will allow us to use a single DTS file regardless of kernel
> configuration. In case of legacy C board code the device nodes may or
> may not be used, but in the multiplatform case all the DT device nodes
> will be used.
> 
> Based on a similar change for the Lager board by Laurent Pinchart.
> 
> Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

> 
> ---
> v3
> * Updated for recent changes to Marzen reference DTS
> ---
>  arch/arm/boot/dts/r8a7779-marzen.dts | 93
> ++++++++++++++++++++++++++++++++++++ 1 file changed, 93 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts
> b/arch/arm/boot/dts/r8a7779-marzen.dts index a7af2c2..eda6240 100644
> --- a/arch/arm/boot/dts/r8a7779-marzen.dts
> +++ b/arch/arm/boot/dts/r8a7779-marzen.dts
> @@ -11,6 +11,8 @@
> 
>  /dts-v1/;
>  #include "r8a7779.dtsi"
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> 
>  / {
>  	model = "marzen";
> @@ -24,4 +26,95 @@
>  		device_type = "memory";
>  		reg = <0x60000000 0x40000000>;
>  	};
> +
> +	fixedregulator3v3: fixedregulator at 0 {
> +		compatible = "regulator-fixed";
> +		regulator-name = "fixed-3.3V";
> +		regulator-min-microvolt = <3300000>;
> +		regulator-max-microvolt = <3300000>;
> +		regulator-boot-on;
> +		regulator-always-on;
> +	};
> +
> +	lan0 at 18000000 {
> +		compatible = "smsc,lan9220", "smsc,lan9115";
> +		reg = <0x18000000 0x100>;
> +		pinctrl-0 = <&lan0_pins>;
> +		pinctrl-names = "default";
> +
> +		phy-mode = "mii";
> +		interrupt-parent = <&irqpin0>;
> +		interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
> +		reg-io-width = <4>;
> +		vddvario-supply = <&fixedregulator3v3>;
> +		vdd33a-supply = <&fixedregulator3v3>;
> +	};
> +
> +	leds {
> +		compatible = "gpio-leds";
> +		led2 {
> +			gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
> +		};
> +		led3 {
> +			gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
> +		};
> +		led4 {
> +			gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;
> +		};
> +	};
> +};
> +
> +&irqpin0 {
> +	status = "okay";
> +};
> +
> +&pfc {
> +	pinctrl-0 = <&scif2_pins &scif4_pins>;
> +	pinctrl-names = "default";
> +
> +	lan0_pins: lan0 {
> +		intc {
> +			renesas,groups = "intc_irq1_b";
> +			renesas,function = "intc";
> +		};
> +		lbsc {
> +			renesas,groups = "lbsc_ex_cs0";
> +			renesas,function = "lbsc";
> +		};
> +	};
> +
> +	scif2_pins: serial2 {
> +		renesas,groups = "scif2_data_c";
> +		renesas,function = "scif2";
> +	};
> +
> +	scif4_pins: serial4 {
> +		renesas,groups = "scif4_data";
> +		renesas,function = "scif4";
> +	};
> +
> +	sdhi0_pins: sd0 {
> +		renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
> +		renesas,function = "sdhi0";
> +	};
> +
> +	hspi0_pins: hspi0 {
> +		renesas,groups = "hspi0";
> +		renesas,function = "hspi0";
> +	};
> +};
> +
> +&sdhi0 {
> +	pinctrl-0 = <&sdhi0_pins>;
> +	pinctrl-names = "default";
> +
> +	vmmc-supply = <&fixedregulator3v3>;
> +	bus-width = <4>;
> +	status = "okay";
> +};
> +
> +&hspi0 {
> +	pinctrl-0 = <&hspi0_pins>;
> +	pinctrl-names = "default";
> +	status = "okay";
>  };

-- 
Regards,

Laurent Pinchart

Re: [PATCH v3 06/20] ARM: shmobile: marzen: Specify external clock frequency in DT

[Laurent Pinchart]

Hi Simon,

Thank you for the patch.

On Wednesday 26 February 2014 16:33:22 Simon Horman wrote:
> The external crystal frequency is 31.25 on the Marzen board.
> Specify it in the device tree.
> 
> Based on work for the Lager board by Laurent Pinchart.
> 
> Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

> ---
> v3
> * Update r8a7779-marzen.dts instead of r8a7779-marzen-reference.dts
> ---
>  arch/arm/boot/dts/r8a7779-marzen.dts | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts
> b/arch/arm/boot/dts/r8a7779-marzen.dts index eda6240..2c727cd 100644
> --- a/arch/arm/boot/dts/r8a7779-marzen.dts
> +++ b/arch/arm/boot/dts/r8a7779-marzen.dts
> @@ -68,6 +68,10 @@
>  	status = "okay";
>  };
> 
> +&extal_clk {
> +	clock-frequency = <31250000>;
> +};
> +
>  &pfc {
>  	pinctrl-0 = <&scif2_pins &scif4_pins>;
>  	pinctrl-names = "default";

-- 
Regards,

Laurent Pinchart

[PATCH v3 06/20] ARM: shmobile: marzen: Specify external clock frequency in DT

[Laurent Pinchart]

Hi Simon,

Thank you for the patch.

On Wednesday 26 February 2014 16:33:22 Simon Horman wrote:
> The external crystal frequency is 31.25 on the Marzen board.
> Specify it in the device tree.
> 
> Based on work for the Lager board by Laurent Pinchart.
> 
> Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

> ---
> v3
> * Update r8a7779-marzen.dts instead of r8a7779-marzen-reference.dts
> ---
>  arch/arm/boot/dts/r8a7779-marzen.dts | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts
> b/arch/arm/boot/dts/r8a7779-marzen.dts index eda6240..2c727cd 100644
> --- a/arch/arm/boot/dts/r8a7779-marzen.dts
> +++ b/arch/arm/boot/dts/r8a7779-marzen.dts
> @@ -68,6 +68,10 @@
>  	status = "okay";
>  };
> 
> +&extal_clk {
> +	clock-frequency = <31250000>;
> +};
> +
>  &pfc {
>  	pinctrl-0 = <&scif2_pins &scif4_pins>;
>  	pinctrl-names = "default";

-- 
Regards,

Laurent Pinchart

Re: [PATCH v3 07/20] ARM: shmobile: marzen: Reference clocks

[Laurent Pinchart]

Hi Simon,

Thank you for the patch.

On Wednesday 26 February 2014 16:33:23 Simon Horman wrote:
> Reference clocks using a "clocks" property in all nodes corresponding to
> devices that require a clock: that is, the lan0 node.
> 
> Based on work by Laurent Pinchart for the r8a7790 and r8a7791 SoCs.
> 
> Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

> ---
> v3
> * New
> ---
>  arch/arm/boot/dts/r8a7779-marzen.dts | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts
> b/arch/arm/boot/dts/r8a7779-marzen.dts index 2c727cd..30f57e9 100644
> --- a/arch/arm/boot/dts/r8a7779-marzen.dts
> +++ b/arch/arm/boot/dts/r8a7779-marzen.dts
> @@ -41,6 +41,7 @@
>  		reg = <0x18000000 0x100>;
>  		pinctrl-0 = <&lan0_pins>;
>  		pinctrl-names = "default";
> +		clocks = <&mstp1_clks R8A7779_CLK_ETHER>;
> 
>  		phy-mode = "mii";
>  		interrupt-parent = <&irqpin0>;

-- 
Regards,

Laurent Pinchart

[PATCH v3 07/20] ARM: shmobile: marzen: Reference clocks

[Laurent Pinchart]

Hi Simon,

Thank you for the patch.

On Wednesday 26 February 2014 16:33:23 Simon Horman wrote:
> Reference clocks using a "clocks" property in all nodes corresponding to
> devices that require a clock: that is, the lan0 node.
> 
> Based on work by Laurent Pinchart for the r8a7790 and r8a7791 SoCs.
> 
> Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

> ---
> v3
> * New
> ---
>  arch/arm/boot/dts/r8a7779-marzen.dts | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts
> b/arch/arm/boot/dts/r8a7779-marzen.dts index 2c727cd..30f57e9 100644
> --- a/arch/arm/boot/dts/r8a7779-marzen.dts
> +++ b/arch/arm/boot/dts/r8a7779-marzen.dts
> @@ -41,6 +41,7 @@
>  		reg = <0x18000000 0x100>;
>  		pinctrl-0 = <&lan0_pins>;
>  		pinctrl-names = "default";
> +		clocks = <&mstp1_clks R8A7779_CLK_ETHER>;
> 
>  		phy-mode = "mii";
>  		interrupt-parent = <&irqpin0>;

-- 
Regards,

Laurent Pinchart

Re: [PATCH v3 08/20] ARM: shmobile: r8a7779: Reference clocks

[Laurent Pinchart]

Hi Simon,

Thank you for the patch.

On Wednesday 26 February 2014 16:33:24 Simon Horman wrote:
> Reference clocks using a "clocks" property in all nodes corresponding to
> devices that require a clock.
> 
> Based on work by Laurent Pinchart for the r8a7790 and r8a7791 SoC.
> 
> Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

> ---
> v3
> * Also update the following nodes which are now present
>   - hspi{0,1,2}
>   - sata: Suggested by Laurent Pinchart
> ---
>  arch/arm/boot/dts/r8a7779.dtsi | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
> index 240a03e..7352987 100644
> --- a/arch/arm/boot/dts/r8a7779.dtsi
> +++ b/arch/arm/boot/dts/r8a7779.dtsi
> @@ -166,6 +166,7 @@
>  		reg = <0xffc70000 0x1000>;
>  		interrupt-parent = <&gic>;
>  		interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
>  		status = "disabled";
>  	};
> 
> @@ -176,6 +177,7 @@
>  		reg = <0xffc71000 0x1000>;
>  		interrupt-parent = <&gic>;
>  		interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
>  		status = "disabled";
>  	};
> 
> @@ -186,6 +188,7 @@
>  		reg = <0xffc72000 0x1000>;
>  		interrupt-parent = <&gic>;
>  		interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
>  		status = "disabled";
>  	};
> 
> @@ -196,6 +199,7 @@
>  		reg = <0xffc73000 0x1000>;
>  		interrupt-parent = <&gic>;
>  		interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
>  		status = "disabled";
>  	};
> 
> @@ -214,6 +218,7 @@
>  		reg = <0xfc600000 0x2000>;
>  		interrupt-parent = <&gic>;
>  		interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&mstp1_clks R8A7779_CLK_SATA>;
>  	};
> 
>  	sdhi0: sd@ffe4c000 {
> @@ -221,6 +226,7 @@
>  		reg = <0xffe4c000 0x100>;
>  		interrupt-parent = <&gic>;
>  		interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
>  		cap-sd-highspeed;
>  		cap-sdio-irq;
>  		status = "disabled";
> @@ -231,6 +237,7 @@
>  		reg = <0xffe4d000 0x100>;
>  		interrupt-parent = <&gic>;
>  		interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
>  		cap-sd-highspeed;
>  		cap-sdio-irq;
>  		status = "disabled";
> @@ -241,6 +248,7 @@
>  		reg = <0xffe4e000 0x100>;
>  		interrupt-parent = <&gic>;
>  		interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
>  		cap-sd-highspeed;
>  		cap-sdio-irq;
>  		status = "disabled";
> @@ -251,6 +259,7 @@
>  		reg = <0xffe4f000 0x100>;
>  		interrupt-parent = <&gic>;
>  		interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
>  		cap-sd-highspeed;
>  		cap-sdio-irq;
>  		status = "disabled";
> @@ -261,6 +270,7 @@
>  		reg = <0xfffc7000 0x18>;
>  		interrupt-controller = <&gic>;
>  		interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
>  		status = "disabled";
>  	};
> 
> @@ -269,6 +279,7 @@
>  		reg = <0xfffc8000 0x18>;
>  		interrupt-controller = <&gic>;
>  		interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
>  		status = "disabled";
>  	};
> 
> @@ -277,6 +288,7 @@
>  		reg = <0xfffc6000 0x18>;
>  		interrupt-controller = <&gic>;
>  		interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
>  		status = "disabled";
>  	};

-- 
Regards,

Laurent Pinchart

[PATCH v3 08/20] ARM: shmobile: r8a7779: Reference clocks

[Laurent Pinchart]

Hi Simon,

Thank you for the patch.

On Wednesday 26 February 2014 16:33:24 Simon Horman wrote:
> Reference clocks using a "clocks" property in all nodes corresponding to
> devices that require a clock.
> 
> Based on work by Laurent Pinchart for the r8a7790 and r8a7791 SoC.
> 
> Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

> ---
> v3
> * Also update the following nodes which are now present
>   - hspi{0,1,2}
>   - sata: Suggested by Laurent Pinchart
> ---
>  arch/arm/boot/dts/r8a7779.dtsi | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
> index 240a03e..7352987 100644
> --- a/arch/arm/boot/dts/r8a7779.dtsi
> +++ b/arch/arm/boot/dts/r8a7779.dtsi
> @@ -166,6 +166,7 @@
>  		reg = <0xffc70000 0x1000>;
>  		interrupt-parent = <&gic>;
>  		interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
>  		status = "disabled";
>  	};
> 
> @@ -176,6 +177,7 @@
>  		reg = <0xffc71000 0x1000>;
>  		interrupt-parent = <&gic>;
>  		interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
>  		status = "disabled";
>  	};
> 
> @@ -186,6 +188,7 @@
>  		reg = <0xffc72000 0x1000>;
>  		interrupt-parent = <&gic>;
>  		interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
>  		status = "disabled";
>  	};
> 
> @@ -196,6 +199,7 @@
>  		reg = <0xffc73000 0x1000>;
>  		interrupt-parent = <&gic>;
>  		interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
>  		status = "disabled";
>  	};
> 
> @@ -214,6 +218,7 @@
>  		reg = <0xfc600000 0x2000>;
>  		interrupt-parent = <&gic>;
>  		interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&mstp1_clks R8A7779_CLK_SATA>;
>  	};
> 
>  	sdhi0: sd at ffe4c000 {
> @@ -221,6 +226,7 @@
>  		reg = <0xffe4c000 0x100>;
>  		interrupt-parent = <&gic>;
>  		interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
>  		cap-sd-highspeed;
>  		cap-sdio-irq;
>  		status = "disabled";
> @@ -231,6 +237,7 @@
>  		reg = <0xffe4d000 0x100>;
>  		interrupt-parent = <&gic>;
>  		interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
>  		cap-sd-highspeed;
>  		cap-sdio-irq;
>  		status = "disabled";
> @@ -241,6 +248,7 @@
>  		reg = <0xffe4e000 0x100>;
>  		interrupt-parent = <&gic>;
>  		interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
>  		cap-sd-highspeed;
>  		cap-sdio-irq;
>  		status = "disabled";
> @@ -251,6 +259,7 @@
>  		reg = <0xffe4f000 0x100>;
>  		interrupt-parent = <&gic>;
>  		interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
>  		cap-sd-highspeed;
>  		cap-sdio-irq;
>  		status = "disabled";
> @@ -261,6 +270,7 @@
>  		reg = <0xfffc7000 0x18>;
>  		interrupt-controller = <&gic>;
>  		interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
>  		status = "disabled";
>  	};
> 
> @@ -269,6 +279,7 @@
>  		reg = <0xfffc8000 0x18>;
>  		interrupt-controller = <&gic>;
>  		interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
>  		status = "disabled";
>  	};
> 
> @@ -277,6 +288,7 @@
>  		reg = <0xfffc6000 0x18>;
>  		interrupt-controller = <&gic>;
>  		interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
>  		status = "disabled";
>  	};

-- 
Regards,

Laurent Pinchart

Re: [PATCH v3 14/20] ARM: shmobile: marzen-reference: Initialize CPG device

[Laurent Pinchart]

Hi Simon,

Thank you for the patch.

On Wednesday 26 February 2014 16:33:30 Simon Horman wrote:
> On multiplatform kernels clocks are handled by the CCF CPG driver. It
> must be explicitly initialized by a call to r8a7779_clocks_init() with
> the value of the boot mode pins.
> 
> Based on similar work for the Koelsch board by Laurent Pinchart.
> 
> Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

> ---
>  arch/arm/mach-shmobile/board-marzen-reference.c | 16 ++++++++++++----
>  1 file changed, 12 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c
> b/arch/arm/mach-shmobile/board-marzen-reference.c index d3e8319..e261431
> 100644
> --- a/arch/arm/mach-shmobile/board-marzen-reference.c
> +++ b/arch/arm/mach-shmobile/board-marzen-reference.c
> @@ -19,7 +19,8 @@
>   * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 
> USA */
> 
> -#include <linux/clk-provider.h>
> +#include <linux/clk/shmobile.h>
> +#include <linux/clocksource.h>
>  #include <linux/of_platform.h>
>  #include <mach/r8a7779.h>
>  #include <mach/common.h>
> @@ -27,11 +28,17 @@
>  #include <asm/irq.h>
>  #include <asm/mach/arch.h>
> 
> -static void __init marzen_init(void)
> +static void __init marzen_init_timer(void)
>  {
>  #ifdef CONFIG_COMMON_CLK
> -	of_clk_init(NULL);
> -#else
> +	r8a7779_clocks_init(r8a7779_read_mode_pins());
> +#endif
> +	clocksource_of_init();
> +}
> +
> +static void __init marzen_init(void)
> +{
> +#ifndef CONFIG_COMMON_CLK
>  	r8a7779_clock_init();
>  #endif
>  	r8a7779_add_standard_devices_dt();
> @@ -48,6 +55,7 @@ DT_MACHINE_START(MARZEN, "marzen")
>  	.smp		= smp_ops(r8a7779_smp_ops),
>  	.map_io		= r8a7779_map_io,
>  	.init_early	= r8a7779_init_delay,
> +	.init_time	= marzen_init_timer,
>  	.nr_irqs	= NR_IRQS_LEGACY,
>  	.init_irq	= r8a7779_init_irq_dt,
>  	.init_machine	= marzen_init,

-- 
Regards,

Laurent Pinchart

[PATCH v3 14/20] ARM: shmobile: marzen-reference: Initialize CPG device

[Laurent Pinchart]

Hi Simon,

Thank you for the patch.

On Wednesday 26 February 2014 16:33:30 Simon Horman wrote:
> On multiplatform kernels clocks are handled by the CCF CPG driver. It
> must be explicitly initialized by a call to r8a7779_clocks_init() with
> the value of the boot mode pins.
> 
> Based on similar work for the Koelsch board by Laurent Pinchart.
> 
> Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

> ---
>  arch/arm/mach-shmobile/board-marzen-reference.c | 16 ++++++++++++----
>  1 file changed, 12 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c
> b/arch/arm/mach-shmobile/board-marzen-reference.c index d3e8319..e261431
> 100644
> --- a/arch/arm/mach-shmobile/board-marzen-reference.c
> +++ b/arch/arm/mach-shmobile/board-marzen-reference.c
> @@ -19,7 +19,8 @@
>   * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 
> USA */
> 
> -#include <linux/clk-provider.h>
> +#include <linux/clk/shmobile.h>
> +#include <linux/clocksource.h>
>  #include <linux/of_platform.h>
>  #include <mach/r8a7779.h>
>  #include <mach/common.h>
> @@ -27,11 +28,17 @@
>  #include <asm/irq.h>
>  #include <asm/mach/arch.h>
> 
> -static void __init marzen_init(void)
> +static void __init marzen_init_timer(void)
>  {
>  #ifdef CONFIG_COMMON_CLK
> -	of_clk_init(NULL);
> -#else
> +	r8a7779_clocks_init(r8a7779_read_mode_pins());
> +#endif
> +	clocksource_of_init();
> +}
> +
> +static void __init marzen_init(void)
> +{
> +#ifndef CONFIG_COMMON_CLK
>  	r8a7779_clock_init();
>  #endif
>  	r8a7779_add_standard_devices_dt();
> @@ -48,6 +55,7 @@ DT_MACHINE_START(MARZEN, "marzen")
>  	.smp		= smp_ops(r8a7779_smp_ops),
>  	.map_io		= r8a7779_map_io,
>  	.init_early	= r8a7779_init_delay,
> +	.init_time	= marzen_init_timer,
>  	.nr_irqs	= NR_IRQS_LEGACY,
>  	.init_irq	= r8a7779_init_irq_dt,
>  	.init_machine	= marzen_init,

-- 
Regards,

Laurent Pinchart

Re: [PATCH v3 15/20] ARM: shmobile: marzen-reference: Instantiate clkdevs for SCIF and TMU

[Laurent Pinchart]

Hi Simon,

Thank you for the patch.

On Wednesday 26 February 2014 16:33:31 Simon Horman wrote:
> Now that the common clock framework is supported, the clock lookup
> entries in clock-r8a7779.c are not registered anymore. Devices must
> instead reference their clocks in the device tree. However, SCIF and CMT
> devices are still instantiated through platform code, and thus need a
> clock lookup entry.
> 
> Retrieve the SCIF and CMT clock entries by name and register clkdevs for
> the corresponding devices. This will be removed when the SCIF and CMT
> devices will be instantiated from the device tree.
> 
> Based on work for the Koelsch board by Laurent Pinchart.
> 
> Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> 
> ---
> v3
> * Initialise TMU clocks instead of CMT clocks
>   - It is TMU that Marzen uses as a clocksource
> * Refactor clock initialisation hack as per more recent mainline
>   code for Koelsch
> * Use IS_ERR to check the return value of clk_get()
> ---
>  arch/arm/mach-shmobile/board-marzen-reference.c | 31 +++++++++++++++++++++-
> 1 file changed, 30 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c
> b/arch/arm/mach-shmobile/board-marzen-reference.c index e261431..a5974d2
> 100644
> --- a/arch/arm/mach-shmobile/board-marzen-reference.c
> +++ b/arch/arm/mach-shmobile/board-marzen-reference.c
> @@ -19,7 +19,9 @@
>   * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 
> USA */
> 
> +#include <linux/clk.h>
>  #include <linux/clk/shmobile.h>
> +#include <linux/clkdev.h>
>  #include <linux/clocksource.h>
>  #include <linux/of_platform.h>
>  #include <mach/r8a7779.h>
> @@ -38,7 +40,34 @@ static void __init marzen_init_timer(void)
> 
>  static void __init marzen_init(void)
>  {
> -#ifndef CONFIG_COMMON_CLK
> +#ifdef CONFIG_COMMON_CLK
> +	static const struct clk_name {
> +		const char *clk;
> +		const char *con_id;
> +		const char *dev_id;
> +	} clk_names[] = {
> +		{ "scif0", NULL, "sh-sci.0" },
> +		{ "scif1", NULL, "sh-sci.1" },
> +		{ "scif2", NULL, "sh-sci.2" },
> +		{ "scif3", NULL, "sh-sci.3" },
> +		{ "scif4", NULL, "sh-sci.4" },
> +		{ "scif5", NULL, "sh-sci.5" },

Any chance to switch the board the DT-based SCIF instead ? ;-)

> +		{ "tmu00", NULL, "sh_tmu.0" },
> +		{ "tmu01", NULL, "sh_tmu.1" },
> +		{ "tmu02", NULL, "sh_tmu.2" },

Those clocks should be tmu0, tmu1 and tmu2.

> +	};
> +	struct clk *clk;
> +	unsigned int i;
> +
> +	for (i = 0; i < ARRAY_SIZE(clk_names); ++i) {
> +		clk = clk_get(NULL, clk_names[i].clk);
> +		if (!IS_ERR(clk)) {
> +			clk_register_clkdev(clk, clk_names[i].con_id,
> +					    clk_names[i].dev_id);
> +			clk_put(clk);
> +		}
> +	}
> +#else
>  	r8a7779_clock_init();
>  #endif
>  	r8a7779_add_standard_devices_dt();

-- 
Regards,

Laurent Pinchart

[PATCH v3 15/20] ARM: shmobile: marzen-reference: Instantiate clkdevs for SCIF and TMU

[Laurent Pinchart]

Hi Simon,

Thank you for the patch.

On Wednesday 26 February 2014 16:33:31 Simon Horman wrote:
> Now that the common clock framework is supported, the clock lookup
> entries in clock-r8a7779.c are not registered anymore. Devices must
> instead reference their clocks in the device tree. However, SCIF and CMT
> devices are still instantiated through platform code, and thus need a
> clock lookup entry.
> 
> Retrieve the SCIF and CMT clock entries by name and register clkdevs for
> the corresponding devices. This will be removed when the SCIF and CMT
> devices will be instantiated from the device tree.
> 
> Based on work for the Koelsch board by Laurent Pinchart.
> 
> Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> 
> ---
> v3
> * Initialise TMU clocks instead of CMT clocks
>   - It is TMU that Marzen uses as a clocksource
> * Refactor clock initialisation hack as per more recent mainline
>   code for Koelsch
> * Use IS_ERR to check the return value of clk_get()
> ---
>  arch/arm/mach-shmobile/board-marzen-reference.c | 31 +++++++++++++++++++++-
> 1 file changed, 30 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c
> b/arch/arm/mach-shmobile/board-marzen-reference.c index e261431..a5974d2
> 100644
> --- a/arch/arm/mach-shmobile/board-marzen-reference.c
> +++ b/arch/arm/mach-shmobile/board-marzen-reference.c
> @@ -19,7 +19,9 @@
>   * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 
> USA */
> 
> +#include <linux/clk.h>
>  #include <linux/clk/shmobile.h>
> +#include <linux/clkdev.h>
>  #include <linux/clocksource.h>
>  #include <linux/of_platform.h>
>  #include <mach/r8a7779.h>
> @@ -38,7 +40,34 @@ static void __init marzen_init_timer(void)
> 
>  static void __init marzen_init(void)
>  {
> -#ifndef CONFIG_COMMON_CLK
> +#ifdef CONFIG_COMMON_CLK
> +	static const struct clk_name {
> +		const char *clk;
> +		const char *con_id;
> +		const char *dev_id;
> +	} clk_names[] = {
> +		{ "scif0", NULL, "sh-sci.0" },
> +		{ "scif1", NULL, "sh-sci.1" },
> +		{ "scif2", NULL, "sh-sci.2" },
> +		{ "scif3", NULL, "sh-sci.3" },
> +		{ "scif4", NULL, "sh-sci.4" },
> +		{ "scif5", NULL, "sh-sci.5" },

Any chance to switch the board the DT-based SCIF instead ? ;-)

> +		{ "tmu00", NULL, "sh_tmu.0" },
> +		{ "tmu01", NULL, "sh_tmu.1" },
> +		{ "tmu02", NULL, "sh_tmu.2" },

Those clocks should be tmu0, tmu1 and tmu2.

> +	};
> +	struct clk *clk;
> +	unsigned int i;
> +
> +	for (i = 0; i < ARRAY_SIZE(clk_names); ++i) {
> +		clk = clk_get(NULL, clk_names[i].clk);
> +		if (!IS_ERR(clk)) {
> +			clk_register_clkdev(clk, clk_names[i].con_id,
> +					    clk_names[i].dev_id);
> +			clk_put(clk);
> +		}
> +	}
> +#else
>  	r8a7779_clock_init();
>  #endif
>  	r8a7779_add_standard_devices_dt();

-- 
Regards,

Laurent Pinchart

Re: [PATCH v3 07/20] ARM: shmobile: marzen: Reference clocks

[Sergei Shtylyov]

Hello.

On 02/26/2014 10:33 AM, Simon Horman wrote:

> Reference clocks using a "clocks" property in all nodes corresponding to
> devices that require a clock: that is, the lan0 node.

    Simon, "lan0" (should be "ethernet" BTW) is the SMC chip, it can't use 
Ether clock.

> Based on work by Laurent Pinchart for the r8a7790 and r8a7791 SoCs.

> Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
>
> ---
> v3
> * New
> ---
>   arch/arm/boot/dts/r8a7779-marzen.dts | 1 +
>   1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts
> index 2c727cd..30f57e9 100644
> --- a/arch/arm/boot/dts/r8a7779-marzen.dts
> +++ b/arch/arm/boot/dts/r8a7779-marzen.dts
> @@ -41,6 +41,7 @@
>   		reg = <0x18000000 0x100>;
>   		pinctrl-0 = <&lan0_pins>;
>   		pinctrl-names = "default";
> +		clocks = <&mstp1_clks R8A7779_CLK_ETHER>;
>
>   		phy-mode = "mii";
>   		interrupt-parent = <&irqpin0>;

WBR, Sergei

Re: [PATCH v3 04/20] ARM: shmobile: r8a7779: Add clocks

[Laurent Pinchart]

Hi Simon,

One more comment.

On Wednesday 26 February 2014 16:33:20 Simon Horman wrote:
> Declare all core and MSTP clocks currently used by r8a7779-based boards.
> 
> Based on work by Laurent Pinchart for the r8a7790 and r8a7791 SoCs.
> 
> Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> 
> ---
> v3
> * As suggested by Laurent Pinchart
>   - Add and use extal_clk
>   - Fix bogus status register use for MSTP clocks
>   - Fix bogus mstp3_cls to use its own entries rather than
>     that of mstp1_clks
> 
> * Update to use "main" in cpg_clocks as per updated
>   binding in previous patch
> * Update for new, consolidated and renamed index macros
>   - R8A7779_CLK_ETHER
>   - R8A7779_CLK_HSCIF
>   - R8A7779_CLK_HSPI
>   - R8A7779_CLK_MMC0,1
>   - R8A7779_CLK_PCIE
>   - R8A7779_CLK_USB01,2
> ---
>  arch/arm/boot/dts/r8a7779.dtsi | 129 ++++++++++++++++++++++++++++++++++++++
>  1 file changed, 129 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
> index d0561d4..240a03e 100644
> --- a/arch/arm/boot/dts/r8a7779.dtsi
> +++ b/arch/arm/boot/dts/r8a7779.dtsi
> @@ -11,6 +11,7 @@
> 
>  /include/ "skeleton.dtsi"
> 
> +#include <dt-bindings/clock/r8a7779-clock.h>
>  #include <dt-bindings/interrupt-controller/irq.h>
> 
>  / {
> @@ -278,4 +279,132 @@
>  		interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
>  		status = "disabled";
>  	};
> +
> +	clocks {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		/* External root clock */
> +		extal_clk: extal_clk {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +			/* This value must be overriden by the board. */
> +			clock-frequency = <0>;
> +			clock-output-names = "extal";
> +		};
> +
> +		/* Special CPG clocks */
> +		cpg_clocks: cpg_clocks@0xe6150000 {
> +			compatible = "renesas,r8a7779-cpg-clocks";
> +			reg = <0 0xe6150000 0 0x1000>;

Copied from H2 ? :-) This should probably be

	reg = <0 0xffc80000 0 0x30>;

> +			clocks = <&extal_clk>;
> +			#clock-cells = <1>;
> +			clock-output-names = "plla", "z", "zs", "s",
> +					     "s1", "p", "out";
> +		};
> +
> +		/* Fixed factor clocks */
> +		i_clk: i_clk {
> +			compatible = "fixed-factor-clock";
> +			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
> +			#clock-cells = <0>;
> +			clock-div = <2>;
> +			clock-mult = <1>;
> +			clock-output-names = "i";
> +		};
> +		s3_clk: s3_clk {
> +			compatible = "fixed-factor-clock";
> +			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
> +			#clock-cells = <0>;
> +			clock-div = <8>;
> +			clock-mult = <1>;
> +			clock-output-names = "s3";
> +		};
> +		s4_clk: s4_clk {
> +			compatible = "fixed-factor-clock";
> +			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
> +			#clock-cells = <0>;
> +			clock-div = <16>;
> +			clock-mult = <1>;
> +			clock-output-names = "s4";
> +		};
> +		g_clk: g_clk {
> +			compatible = "fixed-factor-clock";
> +			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
> +			#clock-cells = <0>;
> +			clock-div = <24>;
> +			clock-mult = <1>;
> +			clock-output-names = "g";
> +		};
> +
> +		/* Gate clocks */
> +		mstp0_clks: mstp0_clks {
> +			compatible = "renesas,r8a7779-mstp-clocks", "renesas,cpg-mstp-
clocks";
> +			reg = <0 0xffc80030 0 4>;
> +			clocks = <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks 
R8A7779_CLK_P>,
> <&cpg_clocks R8A7779_CLK_P>, +				 <&cpg_clocks R8A7779_CLK_P>,
> <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>, +				
> <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks
> R8A7779_CLK_P>, +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks
> R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>, +				 <&cpg_clocks
> R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>;
> +			#clock-cells = <1>;
> +			renesas,clock-indices = <
> +				R8A7779_CLK_HSPI R8A7779_CLK_TMU0 R8A7779_CLK_TMU0
> +				R8A7779_CLK_TMU0 R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
> +				R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2 R8A7779_CLK_SCIF1
> +				R8A7779_CLK_SCIF0 R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
> +				R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
> +			>;
> +			clock-output-names > +				"hspi", "tmu00", "tmu01",
> +				"tmu02", "scif5", "scif4",
> +				"scif3", "scif2", "scif1",
> +				"scif0", "i2c3", "i2c2",
> +				"i2c1", "i2c0";
> +		};
> +		mstp1_clks: mstp1_clks {
> +			compatible = "renesas,r8a7779-mstp-clocks", "renesas,cpg-mstp-
clocks";
> +			reg = <0 0xffc80034 0 4>, <0 0xffc80044 0 4>;
> +			clocks = <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks 
R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>;
> +			#clock-cells = <1>;
> +			renesas,clock-indices = <
> +				R8A7779_CLK_USB01 R8A7779_CLK_USB01
> +				R8A7779_CLK_USB2 R8A7779_CLK_USB2
> +				R8A7779_CLK_DU R8A7779_CLK_VIN2
> +				R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
> +				R8A7779_CLK_ETHER R8A7779_CLK_SATA
> +				R8A7779_CLK_PCIE R8A7779_CLK_VIN3
> +			>;
> +			clock-output-names > +				"ehci0", "ohci0",
> +				"ehci1", "ohci1",
> +				"du", "vin2",
> +				"vin1", "vin0",
> +				"ether", "sata",
> +				"pcie", "vin3";
> +		};
> +		mstp3_clks: mstp3_clks {
> +			compatible = "renesas,r8a7779-mstp-clocks", "renesas,cpg-mstp-
clocks";
> +			reg = <0 0xffc8003c 0 4>;
> +			clocks = <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks 
R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>;
> +			#clock-cells = <1>;
> +			renesas,clock-indices = <
> +				R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
> +				R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
> +				R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
> +			>;
> +			clock-output-names > +				"sdhi3", "sdhi2",
> +				"sdhi1", "sdhi0",
> +				"mmc1", "mmc0";
> +		};
> +	};
>  };

-- 
Regards,

Laurent Pinchart

[PATCH v3 04/20] ARM: shmobile: r8a7779: Add clocks

[Laurent Pinchart]

Hi Simon,

One more comment.

On Wednesday 26 February 2014 16:33:20 Simon Horman wrote:
> Declare all core and MSTP clocks currently used by r8a7779-based boards.
> 
> Based on work by Laurent Pinchart for the r8a7790 and r8a7791 SoCs.
> 
> Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> 
> ---
> v3
> * As suggested by Laurent Pinchart
>   - Add and use extal_clk
>   - Fix bogus status register use for MSTP clocks
>   - Fix bogus mstp3_cls to use its own entries rather than
>     that of mstp1_clks
> 
> * Update to use "main" in cpg_clocks as per updated
>   binding in previous patch
> * Update for new, consolidated and renamed index macros
>   - R8A7779_CLK_ETHER
>   - R8A7779_CLK_HSCIF
>   - R8A7779_CLK_HSPI
>   - R8A7779_CLK_MMC0,1
>   - R8A7779_CLK_PCIE
>   - R8A7779_CLK_USB01,2
> ---
>  arch/arm/boot/dts/r8a7779.dtsi | 129 ++++++++++++++++++++++++++++++++++++++
>  1 file changed, 129 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
> index d0561d4..240a03e 100644
> --- a/arch/arm/boot/dts/r8a7779.dtsi
> +++ b/arch/arm/boot/dts/r8a7779.dtsi
> @@ -11,6 +11,7 @@
> 
>  /include/ "skeleton.dtsi"
> 
> +#include <dt-bindings/clock/r8a7779-clock.h>
>  #include <dt-bindings/interrupt-controller/irq.h>
> 
>  / {
> @@ -278,4 +279,132 @@
>  		interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
>  		status = "disabled";
>  	};
> +
> +	clocks {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		/* External root clock */
> +		extal_clk: extal_clk {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +			/* This value must be overriden by the board. */
> +			clock-frequency = <0>;
> +			clock-output-names = "extal";
> +		};
> +
> +		/* Special CPG clocks */
> +		cpg_clocks: cpg_clocks at 0xe6150000 {
> +			compatible = "renesas,r8a7779-cpg-clocks";
> +			reg = <0 0xe6150000 0 0x1000>;

Copied from H2 ? :-) This should probably be

	reg = <0 0xffc80000 0 0x30>;

> +			clocks = <&extal_clk>;
> +			#clock-cells = <1>;
> +			clock-output-names = "plla", "z", "zs", "s",
> +					     "s1", "p", "out";
> +		};
> +
> +		/* Fixed factor clocks */
> +		i_clk: i_clk {
> +			compatible = "fixed-factor-clock";
> +			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
> +			#clock-cells = <0>;
> +			clock-div = <2>;
> +			clock-mult = <1>;
> +			clock-output-names = "i";
> +		};
> +		s3_clk: s3_clk {
> +			compatible = "fixed-factor-clock";
> +			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
> +			#clock-cells = <0>;
> +			clock-div = <8>;
> +			clock-mult = <1>;
> +			clock-output-names = "s3";
> +		};
> +		s4_clk: s4_clk {
> +			compatible = "fixed-factor-clock";
> +			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
> +			#clock-cells = <0>;
> +			clock-div = <16>;
> +			clock-mult = <1>;
> +			clock-output-names = "s4";
> +		};
> +		g_clk: g_clk {
> +			compatible = "fixed-factor-clock";
> +			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
> +			#clock-cells = <0>;
> +			clock-div = <24>;
> +			clock-mult = <1>;
> +			clock-output-names = "g";
> +		};
> +
> +		/* Gate clocks */
> +		mstp0_clks: mstp0_clks {
> +			compatible = "renesas,r8a7779-mstp-clocks", "renesas,cpg-mstp-
clocks";
> +			reg = <0 0xffc80030 0 4>;
> +			clocks = <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks 
R8A7779_CLK_P>,
> <&cpg_clocks R8A7779_CLK_P>, +				 <&cpg_clocks R8A7779_CLK_P>,
> <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>, +				
> <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks
> R8A7779_CLK_P>, +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks
> R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>, +				 <&cpg_clocks
> R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>;
> +			#clock-cells = <1>;
> +			renesas,clock-indices = <
> +				R8A7779_CLK_HSPI R8A7779_CLK_TMU0 R8A7779_CLK_TMU0
> +				R8A7779_CLK_TMU0 R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
> +				R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2 R8A7779_CLK_SCIF1
> +				R8A7779_CLK_SCIF0 R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
> +				R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
> +			>;
> +			clock-output-names =
> +				"hspi", "tmu00", "tmu01",
> +				"tmu02", "scif5", "scif4",
> +				"scif3", "scif2", "scif1",
> +				"scif0", "i2c3", "i2c2",
> +				"i2c1", "i2c0";
> +		};
> +		mstp1_clks: mstp1_clks {
> +			compatible = "renesas,r8a7779-mstp-clocks", "renesas,cpg-mstp-
clocks";
> +			reg = <0 0xffc80034 0 4>, <0 0xffc80044 0 4>;
> +			clocks = <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks 
R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>;
> +			#clock-cells = <1>;
> +			renesas,clock-indices = <
> +				R8A7779_CLK_USB01 R8A7779_CLK_USB01
> +				R8A7779_CLK_USB2 R8A7779_CLK_USB2
> +				R8A7779_CLK_DU R8A7779_CLK_VIN2
> +				R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
> +				R8A7779_CLK_ETHER R8A7779_CLK_SATA
> +				R8A7779_CLK_PCIE R8A7779_CLK_VIN3
> +			>;
> +			clock-output-names =
> +				"ehci0", "ohci0",
> +				"ehci1", "ohci1",
> +				"du", "vin2",
> +				"vin1", "vin0",
> +				"ether", "sata",
> +				"pcie", "vin3";
> +		};
> +		mstp3_clks: mstp3_clks {
> +			compatible = "renesas,r8a7779-mstp-clocks", "renesas,cpg-mstp-
clocks";
> +			reg = <0 0xffc8003c 0 4>;
> +			clocks = <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks 
R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>;
> +			#clock-cells = <1>;
> +			renesas,clock-indices = <
> +				R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
> +				R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
> +				R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
> +			>;
> +			clock-output-names =
> +				"sdhi3", "sdhi2",
> +				"sdhi1", "sdhi0",
> +				"mmc1", "mmc0";
> +		};
> +	};
>  };

-- 
Regards,

Laurent Pinchart

[PATCH v3 07/20] ARM: shmobile: marzen: Reference clocks

[Sergei Shtylyov]

Hello.

On 02/26/2014 10:33 AM, Simon Horman wrote:

> Reference clocks using a "clocks" property in all nodes corresponding to
> devices that require a clock: that is, the lan0 node.

    Simon, "lan0" (should be "ethernet" BTW) is the SMC chip, it can't use 
Ether clock.

> Based on work by Laurent Pinchart for the r8a7790 and r8a7791 SoCs.

> Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
>
> ---
> v3
> * New
> ---
>   arch/arm/boot/dts/r8a7779-marzen.dts | 1 +
>   1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts
> index 2c727cd..30f57e9 100644
> --- a/arch/arm/boot/dts/r8a7779-marzen.dts
> +++ b/arch/arm/boot/dts/r8a7779-marzen.dts
> @@ -41,6 +41,7 @@
>   		reg = <0x18000000 0x100>;
>   		pinctrl-0 = <&lan0_pins>;
>   		pinctrl-names = "default";
> +		clocks = <&mstp1_clks R8A7779_CLK_ETHER>;
>
>   		phy-mode = "mii";
>   		interrupt-parent = <&irqpin0>;

WBR, Sergei

Re: [PATCH v3 01/20] clk: shmobile: r8a7779: Add clocks support

[Simon Horman]

On Wed, Feb 26, 2014 at 10:06:06AM +0100, Geert Uytterhoeven wrote:
> On Wed, Feb 26, 2014 at 9:59 AM, Simon Horman <horms@verge.net.au> wrote:
> >> > +/*
> >> > + *             MD1 = 1                 MD1 = 0
> >> > + *             (PLLA = 1500)           (PLLA = 1600)
> >> > + *             (MHz)                   (MHz)
> >> > + *------------------------------------------------+--------------------
> >> > + * clkz                1000   (2/3)            800   (1/2)
> >> > + * clkzs        250   (1/6)            200   (1/8)
> >> > + * clki                 750   (1/2)            800   (1/2)
> >> > + * clks                 250   (1/6)            200   (1/8)
> >> > + * clks1        125   (1/12)           100   (1/16)
> >> > + * clks3        187.5 (1/8)            200   (1/8)
> >> > + * clks4         93.7 (1/16)           100   (1/16)
> >> > + * clkp                  62.5 (1/24)            50   (1/32)
> >> > + * clkg                  62.5 (1/24)            66.6 (1/24)
> >> > + * clkb, CLKOUT
> >> > + * (MD2 = 0)     62.5 (1/24)            66.6 (1/24)
> >> > + * (MD2 = 1)     41.6 (1/36)            50   (1/32)
> >> > + */
> >> > +
> >> > +#define CPG_CLK_CONFIG_INDEX(md)       (((md) & (BIT(1)|BIT(2))) >> 1)
> >> > +
> >> > +struct cpg_clk_config {
> >> > +       unsigned int z_mult;
> >> > +       unsigned int z_div;
> >> > +       unsigned int zs_and_s_div;
> >> > +       unsigned int s1_div;
> >> > +       unsigned int p_div;
> >> > +       unsigned int out_div;
> >> > +};
> >> > +
> >> > +static const struct cpg_clk_config cpg_clk_configs[4] __initconst = {
> >> > +       { 1, 2, 8, 16, 32, 24 },
> >> > +       { 1, 2, 8, 16, 32, 24 },
> >> > +       { 2, 3, 6, 12, 24, 36 },
> >> > +       { 2, 3, 6, 12, 24, 32 },
> >> > +};
> >>
> >> Shouldn't this be
> >>
> >> +static const struct cpg_clk_config cpg_clk_configs[4] __initconst = {
> >> +       { 1, 2, 8, 16, 32, 24 },
> >> +       { 2, 3, 6, 12, 24, 24 },
> >> +       { 1, 2, 8, 16, 32, 32 },
> >> +       { 2, 3, 6, 12, 24, 36 },
> >> +};
> >>
> >> ?
> >>
> >> I think you got confused by writing the bitmask as "BIT(1)|BIT(2)" instead
> >> of "BIT(2)|BIT(1)".
> >
> > Probably, thanks for noticing.
> 
> Note that I based my review on the table above, not on the actual datasheet.

Understood. I'll double check the datasheet against my code and your comment.

[PATCH v3 01/20] clk: shmobile: r8a7779: Add clocks support

[Simon Horman]

On Wed, Feb 26, 2014 at 10:06:06AM +0100, Geert Uytterhoeven wrote:
> On Wed, Feb 26, 2014 at 9:59 AM, Simon Horman <horms@verge.net.au> wrote:
> >> > +/*
> >> > + *             MD1 = 1                 MD1 = 0
> >> > + *             (PLLA = 1500)           (PLLA = 1600)
> >> > + *             (MHz)                   (MHz)
> >> > + *------------------------------------------------+--------------------
> >> > + * clkz                1000   (2/3)            800   (1/2)
> >> > + * clkzs        250   (1/6)            200   (1/8)
> >> > + * clki                 750   (1/2)            800   (1/2)
> >> > + * clks                 250   (1/6)            200   (1/8)
> >> > + * clks1        125   (1/12)           100   (1/16)
> >> > + * clks3        187.5 (1/8)            200   (1/8)
> >> > + * clks4         93.7 (1/16)           100   (1/16)
> >> > + * clkp                  62.5 (1/24)            50   (1/32)
> >> > + * clkg                  62.5 (1/24)            66.6 (1/24)
> >> > + * clkb, CLKOUT
> >> > + * (MD2 = 0)     62.5 (1/24)            66.6 (1/24)
> >> > + * (MD2 = 1)     41.6 (1/36)            50   (1/32)
> >> > + */
> >> > +
> >> > +#define CPG_CLK_CONFIG_INDEX(md)       (((md) & (BIT(1)|BIT(2))) >> 1)
> >> > +
> >> > +struct cpg_clk_config {
> >> > +       unsigned int z_mult;
> >> > +       unsigned int z_div;
> >> > +       unsigned int zs_and_s_div;
> >> > +       unsigned int s1_div;
> >> > +       unsigned int p_div;
> >> > +       unsigned int out_div;
> >> > +};
> >> > +
> >> > +static const struct cpg_clk_config cpg_clk_configs[4] __initconst = {
> >> > +       { 1, 2, 8, 16, 32, 24 },
> >> > +       { 1, 2, 8, 16, 32, 24 },
> >> > +       { 2, 3, 6, 12, 24, 36 },
> >> > +       { 2, 3, 6, 12, 24, 32 },
> >> > +};
> >>
> >> Shouldn't this be
> >>
> >> +static const struct cpg_clk_config cpg_clk_configs[4] __initconst = {
> >> +       { 1, 2, 8, 16, 32, 24 },
> >> +       { 2, 3, 6, 12, 24, 24 },
> >> +       { 1, 2, 8, 16, 32, 32 },
> >> +       { 2, 3, 6, 12, 24, 36 },
> >> +};
> >>
> >> ?
> >>
> >> I think you got confused by writing the bitmask as "BIT(1)|BIT(2)" instead
> >> of "BIT(2)|BIT(1)".
> >
> > Probably, thanks for noticing.
> 
> Note that I based my review on the table above, not on the actual datasheet.

Understood. I'll double check the datasheet against my code and your comment.

Re: [PATCH v3 01/20] clk: shmobile: r8a7779: Add clocks support

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 1512 bytes --]


> +	cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
> +	clks = kzalloc(CPG_NUM_CLOCKS * sizeof(*clks), GFP_KERNEL);
> +	if (cpg == NULL || clks == NULL) {
> +		/* We're leaking memory on purpose, there's no point in cleaning
> +		 * up as the system won't boot anyway.
> +		 */
> +		pr_err("%s: failed to allocate cpg\n", __func__);
> +		return;
> +	}

I have problems with this sloppiness. Writing the comment took probably
the same time as writing the proper exit path :) On the drawback side,
static code checkers will keep reporting this.

> +	cpg->reg = of_iomap(np, 0);
> +	if (WARN_ON(cpg->reg == NULL))
> +		return;

if (WARN(!cpg->reg, "can't ioremap CPG\n"))

?

> diff --git a/include/linux/clk/shmobile.h b/include/linux/clk/shmobile.h
> index f9bf080..7667f49 100644
> --- a/include/linux/clk/shmobile.h
> +++ b/include/linux/clk/shmobile.h
> @@ -1,7 +1,9 @@
>  /*
>   * Copyright 2013 Ideas On Board SPRL
> + * Copyright 2013 Horms Solutions Ltd.
>   *
>   * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> + * Contact: Simon Horman <horms@verge.net.au>
>   *
>   * This program is free software; you can redistribute it and/or modify
>   * it under the terms of the GNU General Public License as published by
> @@ -14,6 +16,7 @@
>  
>  #include <linux/types.h>
>  
> +void r8a7779_clocks_init(u32 mode);
>  void rcar_gen2_clocks_init(u32 mode);

Shouldn't the init functions be protected by #ifdef CONFIG_ARCH...?

Regards,

   Wolfram


[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 836 bytes --]

[PATCH v3 01/20] clk: shmobile: r8a7779: Add clocks support

[Wolfram Sang]

> +	cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
> +	clks = kzalloc(CPG_NUM_CLOCKS * sizeof(*clks), GFP_KERNEL);
> +	if (cpg == NULL || clks == NULL) {
> +		/* We're leaking memory on purpose, there's no point in cleaning
> +		 * up as the system won't boot anyway.
> +		 */
> +		pr_err("%s: failed to allocate cpg\n", __func__);
> +		return;
> +	}

I have problems with this sloppiness. Writing the comment took probably
the same time as writing the proper exit path :) On the drawback side,
static code checkers will keep reporting this.

> +	cpg->reg = of_iomap(np, 0);
> +	if (WARN_ON(cpg->reg == NULL))
> +		return;

if (WARN(!cpg->reg, "can't ioremap CPG\n"))

?

> diff --git a/include/linux/clk/shmobile.h b/include/linux/clk/shmobile.h
> index f9bf080..7667f49 100644
> --- a/include/linux/clk/shmobile.h
> +++ b/include/linux/clk/shmobile.h
> @@ -1,7 +1,9 @@
>  /*
>   * Copyright 2013 Ideas On Board SPRL
> + * Copyright 2013 Horms Solutions Ltd.
>   *
>   * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> + * Contact: Simon Horman <horms@verge.net.au>
>   *
>   * This program is free software; you can redistribute it and/or modify
>   * it under the terms of the GNU General Public License as published by
> @@ -14,6 +16,7 @@
>  
>  #include <linux/types.h>
>  
> +void r8a7779_clocks_init(u32 mode);
>  void rcar_gen2_clocks_init(u32 mode);

Shouldn't the init functions be protected by #ifdef CONFIG_ARCH...?

Regards,

   Wolfram

-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: Digital signature
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20140301/44525a28/attachment.sig>

Re: [PATCH v3 04/20] ARM: shmobile: r8a7779: Add clocks

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 453 bytes --]

On Wed, Feb 26, 2014 at 04:33:20PM +0900, Simon Horman wrote:
> Declare all core and MSTP clocks currently used by r8a7779-based boards.
> 
> Based on work by Laurent Pinchart for the r8a7790 and r8a7791 SoCs.
> 
> Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

I wonder if patches 2-4 shouldn't be squashed? I think it would make
reviewing/finding typos easier.


[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 836 bytes --]

[PATCH v3 04/20] ARM: shmobile: r8a7779: Add clocks

[Wolfram Sang]

On Wed, Feb 26, 2014 at 04:33:20PM +0900, Simon Horman wrote:
> Declare all core and MSTP clocks currently used by r8a7779-based boards.
> 
> Based on work by Laurent Pinchart for the r8a7790 and r8a7791 SoCs.
> 
> Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

I wonder if patches 2-4 shouldn't be squashed? I think it would make
reviewing/finding typos easier.

-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: Digital signature
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20140301/8772ffa3/attachment-0001.sig>

Re: [PATCH v3 01/20] clk: shmobile: r8a7779: Add clocks support

[Geert Uytterhoeven]

On Sat, Mar 1, 2014 at 2:50 PM, Wolfram Sang <wsa@the-dreams.de> wrote:
>> --- a/include/linux/clk/shmobile.h
>> +++ b/include/linux/clk/shmobile.h
>> @@ -1,7 +1,9 @@
>>  /*
>>   * Copyright 2013 Ideas On Board SPRL
>> + * Copyright 2013 Horms Solutions Ltd.
>>   *
>>   * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
>> + * Contact: Simon Horman <horms@verge.net.au>
>>   *
>>   * This program is free software; you can redistribute it and/or modify
>>   * it under the terms of the GNU General Public License as published by
>> @@ -14,6 +16,7 @@
>>
>>  #include <linux/types.h>
>>
>> +void r8a7779_clocks_init(u32 mode);
>>  void rcar_gen2_clocks_init(u32 mode);
>
> Shouldn't the init functions be protected by #ifdef CONFIG_ARCH...?

Not in header files.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH v3 01/20] clk: shmobile: r8a7779: Add clocks support

[Geert Uytterhoeven]

On Sat, Mar 1, 2014 at 2:50 PM, Wolfram Sang <wsa@the-dreams.de> wrote:
>> --- a/include/linux/clk/shmobile.h
>> +++ b/include/linux/clk/shmobile.h
>> @@ -1,7 +1,9 @@
>>  /*
>>   * Copyright 2013 Ideas On Board SPRL
>> + * Copyright 2013 Horms Solutions Ltd.
>>   *
>>   * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
>> + * Contact: Simon Horman <horms@verge.net.au>
>>   *
>>   * This program is free software; you can redistribute it and/or modify
>>   * it under the terms of the GNU General Public License as published by
>> @@ -14,6 +16,7 @@
>>
>>  #include <linux/types.h>
>>
>> +void r8a7779_clocks_init(u32 mode);
>>  void rcar_gen2_clocks_init(u32 mode);
>
> Shouldn't the init functions be protected by #ifdef CONFIG_ARCH...?

Not in header files.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v3 01/20] clk: shmobile: r8a7779: Add clocks support

[Laurent Pinchart]

[-- Attachment #1: Type: text/plain, Size: 1181 bytes --]

Hi Wolfram,

On Saturday 01 March 2014 14:50:03 Wolfram Sang wrote:
> > +	cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
> > +	clks = kzalloc(CPG_NUM_CLOCKS * sizeof(*clks), GFP_KERNEL);
> > +	if (cpg == NULL || clks == NULL) {
> > +		/* We're leaking memory on purpose, there's no point in cleaning
> > +		 * up as the system won't boot anyway.
> > +		 */
> > +		pr_err("%s: failed to allocate cpg\n", __func__);
> > +		return;
> > +	}
> 
> I have problems with this sloppiness. Writing the comment took probably
> the same time as writing the proper exit path :) On the drawback side,
> static code checkers will keep reporting this.

Then static code checkers should be fixed :-) or at least provide an override. 
Given that the system won't boot if this fails I don't see a point in adding 
useless code to the kernel that would just result in a larger binary size.

> > +	cpg->reg = of_iomap(np, 0);
> > +	if (WARN_ON(cpg->reg == NULL))
> > +		return;
> 
> if (WARN(!cpg->reg, "can't ioremap CPG\n"))
> 
> ?

We can probably remove this altogether given that the driver doesn't make use 
of the ioremap'ed memory.

-- 
Regards,

Laurent Pinchart

[-- Attachment #2: This is a digitally signed message part. --]
[-- Type: application/pgp-signature, Size: 490 bytes --]

[PATCH v3 01/20] clk: shmobile: r8a7779: Add clocks support

[Laurent Pinchart]

Hi Wolfram,

On Saturday 01 March 2014 14:50:03 Wolfram Sang wrote:
> > +	cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
> > +	clks = kzalloc(CPG_NUM_CLOCKS * sizeof(*clks), GFP_KERNEL);
> > +	if (cpg == NULL || clks == NULL) {
> > +		/* We're leaking memory on purpose, there's no point in cleaning
> > +		 * up as the system won't boot anyway.
> > +		 */
> > +		pr_err("%s: failed to allocate cpg\n", __func__);
> > +		return;
> > +	}
> 
> I have problems with this sloppiness. Writing the comment took probably
> the same time as writing the proper exit path :) On the drawback side,
> static code checkers will keep reporting this.

Then static code checkers should be fixed :-) or at least provide an override. 
Given that the system won't boot if this fails I don't see a point in adding 
useless code to the kernel that would just result in a larger binary size.

> > +	cpg->reg = of_iomap(np, 0);
> > +	if (WARN_ON(cpg->reg == NULL))
> > +		return;
> 
> if (WARN(!cpg->reg, "can't ioremap CPG\n"))
> 
> ?

We can probably remove this altogether given that the driver doesn't make use 
of the ioremap'ed memory.

-- 
Regards,

Laurent Pinchart
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 490 bytes
Desc: This is a digitally signed message part.
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20140302/e9607627/attachment.sig>

Re: [PATCH v3 01/20] clk: shmobile: r8a7779: Add clocks support

[Geert Uytterhoeven]

On Sun, Mar 2, 2014 at 12:35 PM, Laurent Pinchart
<laurent.pinchart@ideasonboard.com> wrote:
> On Saturday 01 March 2014 14:50:03 Wolfram Sang wrote:
>> > +   cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
>> > +   clks = kzalloc(CPG_NUM_CLOCKS * sizeof(*clks), GFP_KERNEL);
>> > +   if (cpg = NULL || clks = NULL) {
>> > +           /* We're leaking memory on purpose, there's no point in cleaning
>> > +            * up as the system won't boot anyway.
>> > +            */
>> > +           pr_err("%s: failed to allocate cpg\n", __func__);
>> > +           return;
>> > +   }
>>
>> I have problems with this sloppiness. Writing the comment took probably
>> the same time as writing the proper exit path :) On the drawback side,
>> static code checkers will keep reporting this.
>
> Then static code checkers should be fixed :-) or at least provide an override.
> Given that the system won't boot if this fails I don't see a point in adding
> useless code to the kernel that would just result in a larger binary size.

If binary size is what matters, I think you can remove the pr_err(), too,
as the kzalloc() above will scream, won't it?

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH v3 01/20] clk: shmobile: r8a7779: Add clocks support

[Geert Uytterhoeven]

On Sun, Mar 2, 2014 at 12:35 PM, Laurent Pinchart
<laurent.pinchart@ideasonboard.com> wrote:
> On Saturday 01 March 2014 14:50:03 Wolfram Sang wrote:
>> > +   cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
>> > +   clks = kzalloc(CPG_NUM_CLOCKS * sizeof(*clks), GFP_KERNEL);
>> > +   if (cpg == NULL || clks == NULL) {
>> > +           /* We're leaking memory on purpose, there's no point in cleaning
>> > +            * up as the system won't boot anyway.
>> > +            */
>> > +           pr_err("%s: failed to allocate cpg\n", __func__);
>> > +           return;
>> > +   }
>>
>> I have problems with this sloppiness. Writing the comment took probably
>> the same time as writing the proper exit path :) On the drawback side,
>> static code checkers will keep reporting this.
>
> Then static code checkers should be fixed :-) or at least provide an override.
> Given that the system won't boot if this fails I don't see a point in adding
> useless code to the kernel that would just result in a larger binary size.

If binary size is what matters, I think you can remove the pr_err(), too,
as the kzalloc() above will scream, won't it?

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v3 01/20] clk: shmobile: r8a7779: Add clocks support

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 1316 bytes --]

On Sun, Mar 02, 2014 at 12:35:50PM +0100, Laurent Pinchart wrote:
> Hi Wolfram,
> 
> On Saturday 01 March 2014 14:50:03 Wolfram Sang wrote:
> > > +	cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
> > > +	clks = kzalloc(CPG_NUM_CLOCKS * sizeof(*clks), GFP_KERNEL);
> > > +	if (cpg == NULL || clks == NULL) {
> > > +		/* We're leaking memory on purpose, there's no point in cleaning
> > > +		 * up as the system won't boot anyway.
> > > +		 */
> > > +		pr_err("%s: failed to allocate cpg\n", __func__);
> > > +		return;
> > > +	}
> > 
> > I have problems with this sloppiness. Writing the comment took probably
> > the same time as writing the proper exit path :) On the drawback side,
> > static code checkers will keep reporting this.
> 
> Then static code checkers should be fixed :-)

How should they know if you 'return'? :) They will know if you BUG().
Which might be the better (read: more descriptive) option which would
save the comment, too.

> > > +	cpg->reg = of_iomap(np, 0);
> > > +	if (WARN_ON(cpg->reg == NULL))
> > > +		return;
> > 
> > if (WARN(!cpg->reg, "can't ioremap CPG\n"))
> > 
> > ?
> 
> We can probably remove this altogether given that the driver doesn't make use 
> of the ioremap'ed memory.

Okay. Was still a good place to advertise WARN() over WARN_ON ;)


[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 836 bytes --]

[PATCH v3 01/20] clk: shmobile: r8a7779: Add clocks support

[Wolfram Sang]

On Sun, Mar 02, 2014 at 12:35:50PM +0100, Laurent Pinchart wrote:
> Hi Wolfram,
> 
> On Saturday 01 March 2014 14:50:03 Wolfram Sang wrote:
> > > +	cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
> > > +	clks = kzalloc(CPG_NUM_CLOCKS * sizeof(*clks), GFP_KERNEL);
> > > +	if (cpg == NULL || clks == NULL) {
> > > +		/* We're leaking memory on purpose, there's no point in cleaning
> > > +		 * up as the system won't boot anyway.
> > > +		 */
> > > +		pr_err("%s: failed to allocate cpg\n", __func__);
> > > +		return;
> > > +	}
> > 
> > I have problems with this sloppiness. Writing the comment took probably
> > the same time as writing the proper exit path :) On the drawback side,
> > static code checkers will keep reporting this.
> 
> Then static code checkers should be fixed :-)

How should they know if you 'return'? :) They will know if you BUG().
Which might be the better (read: more descriptive) option which would
save the comment, too.

> > > +	cpg->reg = of_iomap(np, 0);
> > > +	if (WARN_ON(cpg->reg == NULL))
> > > +		return;
> > 
> > if (WARN(!cpg->reg, "can't ioremap CPG\n"))
> > 
> > ?
> 
> We can probably remove this altogether given that the driver doesn't make use 
> of the ioremap'ed memory.

Okay. Was still a good place to advertise WARN() over WARN_ON ;)

-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: Digital signature
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20140302/0a181b53/attachment.sig>

Re: [PATCH v3 01/20] clk: shmobile: r8a7779: Add clocks support

[Simon Horman]

On Wed, Feb 26, 2014 at 02:02:37PM +0100, Laurent Pinchart wrote:
> Hi Simon,
> 
> Two more small comments.
> 
> On Wednesday 26 February 2014 13:53:17 Laurent Pinchart wrote:
> > On Wednesday 26 February 2014 16:33:17 Simon Horman wrote:
> > > The R8A7779 SoC has several clocks that are too custom to be supported in
> > > a generic driver. Those clocks can be divided in two categories:
> > > 
> > > - Fixed rate clocks with multiplier and divisor set according to boot
> > >   mode configuration
> > > 
> > > - Custom divider clocks with SoC-specific divider values
> > > 
> > > This driver supports both.
> > 
> > Looking at the R8A7779 datasheet it looks like we only have fixed rate
> > clocks, without any configurable divider clock. Did I miss something ?

Sorry, its a cut-and past error on my part.
I will revise the changelog.

> > 
> > > Based on work for R-Car Gen2 SoCs by Laurent Pinchart.
> > > 
> > > Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> > > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> > > 
> > > ---
> > > v3
> > > * As suggested by Laurent Pinchart
> > > 
> > >   - Added external clock input
> > >   - Use PLLA ratio set bu MD11 and MD12
> > >   - Add _div suffixes of fields of struct cpt_clk_config
> > >   - Register PLLA as a fixed factor clock
> > >   - Use sizeof() instead of sizeof
> > >   - Use num_clks instead of CPG_NUM_CLOCKS in r8a7779_cpg_clocks_init()
> > >   
> > >   - I kept this as r8a7779 binding rather than moving to a R-Car Gen1
> > >   
> > >     binding which could be shared with other SoCs as I do not believe that
> > >     the SoCs is are sufficiently similar.
> > 
> > I had a look at the M1 datasheet and I still find its CPG very similar with
> > the H1 CPG. The PLLA multiplier and divider are different, but if you look
> > closely, they're both exactly twice the value compared to H1, so there's no
> > difference in practice.
> > 
> > What differences do you see that would make it impractical to share a single
> > driver for both ?

Thanks for pointing that out. Looking over the M1 datasheet again I agree
with you that there does seem to be rather a lot of similarities with the
H1. And I agree that it is likely that the driver could be shared.

However, I'd like to leave that as future work at this time.

The reason for this is that on the one hand I believe such work sould be
done in conjunctin with integrating the driver on the bockw board.
And that seems to be non-trivial to me.

> > 
> > > ---
> > > 
> > >  .../bindings/clock/renesas,r8a7779-cpg-clocks.txt  |  26 +++
> > >  drivers/clk/shmobile/Makefile                      |   1 +
> > >  drivers/clk/shmobile/clk-r8a7779.c                 | 191
> > >  ++++++++++++++++++
> > >  include/linux/clk/shmobile.h                       |   3 +
> > >  4 files changed, 221 insertions(+)
> > >  create mode 100644
> > > 
> > > Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
> > > create mode 100644 drivers/clk/shmobile/clk-r8a7779.c
> > > 
> > > diff --git
> > > a/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
> > > b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
> > > new file mode 100644
> > > index 0000000..1461323
> > > --- /dev/null
> > > +++
> > > b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
> > > @@ -0,0 +1,26 @@
> > > +* Renesas R8A7779 Clock Pulse Generator (CPG)
> > > +
> > > +The CPG generates core clocks for the R8A7779. It includes one PLL and
> > > +and several fixed ratio dividers
> > > +
> > > +Required Properties:
> > > +
> > > +  - compatible: Must be "renesas,r8a7779-cpg-clocks"
> > > +  - reg: Base address and length of the memory resource used by the CPG
> > > +
> > > +  - clocks: Reference to the parent clock
> > > +  - #clock-cells: Must be 1
> > > +  - clock-output-names: The names of the clocks. Supported clocks are
> > > "plla",
> > > +    "z", "zs", "s", "s1", "p", "out".
> > 
> > What about clki, clks3, clks4, clkb and clkg ? Should pllb be exposed as
> > well ?
> 
> I spoke too fast, clki, clks3, clks4 and clkg are fixed factor clocks 
> expressed in DT, my bad. What about clkb though ?

Thanks. I missed clkb. I'll add it.

> 
> > 
> > > +Example
> > > +-------
> > > +
> > > +	cpg_clocks: cpg_clocks@ffc80000 {
> > > +		compatible = "renesas,r8a7779-cpg-clocks";
> > > +		reg = <0 0xffc80000 0 0x80>;
> > 
> > Shouldn't the range be restricted not to include the MSTP registers ? 0x30
> > should be enough.

Thanks, I will fix that.

> > 
> > > +		clocks = <&extal_clk>;
> > > +		#clock-cells = <1>;
> > > +		clock-output-names = "plla", "z", "zs", "s", "s1", "p", "out";
> > > +	};
> > > diff --git a/drivers/clk/shmobile/Makefile b/drivers/clk/shmobile/Makefile
> > > index 9ecef14..2121ba0 100644
> > > --- a/drivers/clk/shmobile/Makefile
> > > +++ b/drivers/clk/shmobile/Makefile
> > > @@ -1,4 +1,5 @@
> > > 
> > >  obj-$(CONFIG_ARCH_EMEV2)		+= clk-emev2.o
> > > 
> > > +obj-$(CONFIG_ARCH_R8A7779)		+= clk-r8a7779.o
> > > 
> > >  obj-$(CONFIG_ARCH_R8A7790)		+= clk-rcar-gen2.o
> > >  obj-$(CONFIG_ARCH_R8A7791)		+= clk-rcar-gen2.o
> > >  obj-$(CONFIG_ARCH_SHMOBILE_MULTI)	+= clk-div6.o
> > > 
> > > diff --git a/drivers/clk/shmobile/clk-r8a7779.c
> > > b/drivers/clk/shmobile/clk-r8a7779.c new file mode 100644
> > > index 0000000..2ca2d67
> > > --- /dev/null
> > > +++ b/drivers/clk/shmobile/clk-r8a7779.c
> > > @@ -0,0 +1,191 @@
> > > +/*
> > > + * r8a7779 Core CPG Clocks
> > > + *
> > > + * Copyright (C) 2013, 2014 Horms Solutions Ltd.
> > > + *
> > > + * Contact: Simon Horman <horms@verge.net.au>
> > > + *
> > > + * This program is free software; you can redistribute it and/or modify
> > > + * it under the terms of the GNU General Public License as published by
> > > + * the Free Software Foundation; version 2 of the License.
> > > + */
> > > +
> > > +#include <linux/clk-provider.h>
> > > +#include <linux/clkdev.h>
> > > +#include <linux/clk/shmobile.h>
> > > +#include <linux/init.h>
> > > +#include <linux/kernel.h>
> > > +#include <linux/of.h>
> > > +#include <linux/of_address.h>
> > > +#include <linux/spinlock.h>
> > > +
> > > +#include <dt-bindings/clock/r8a7779-clock.h>
> > > +
> > > +#define CPG_NUM_CLOCKS			(R8A7779_CLK_OUT + 1)
> > > +
> > > +struct r8a7779_cpg {
> > > +	struct clk_onecell_data data;
> > > +	spinlock_t lock;
> > > +	void __iomem *reg;
> > > +};
> > > +
> > > +/*
> > > --------------------------------------------------------------------------
> > > -
> > > -- + * CPG Clock Data
> > > + */
> > > +
> > > +/*
> > > + *		MD1 = 1			MD1 = 0
> > > + *		(PLLA = 1500)		(PLLA = 1600)
> > > + *		(MHz)			(MHz)
> > > + *------------------------------------------------+--------------------
> > > + * clkz		1000   (2/3)		800   (1/2)
> > > + * clkzs	 250   (1/6)		200   (1/8)
> > > + * clki		 750   (1/2)		800   (1/2)
> > > + * clks		 250   (1/6)		200   (1/8)
> > > + * clks1	 125   (1/12)		100   (1/16)
> > > + * clks3	 187.5 (1/8)		200   (1/8)
> > > + * clks4	  93.7 (1/16)		100   (1/16)
> > > + * clkp		  62.5 (1/24)		 50   (1/32)
> > > + * clkg		  62.5 (1/24)		 66.6 (1/24)
> > > + * clkb, CLKOUT
> > > + * (MD2 = 0)	  62.5 (1/24)		 66.6 (1/24)
> > > + * (MD2 = 1)	  41.6 (1/36)		 50   (1/32)
> > > + */
> > > +
> > > +#define CPG_CLK_CONFIG_INDEX(md)	(((md) & (BIT(1)|BIT(2))) >> 1)
> > > +
> > > +struct cpg_clk_config {
> > > +	unsigned int z_mult;
> > > +	unsigned int z_div;
> > > +	unsigned int zs_and_s_div;
> > > +	unsigned int s1_div;
> > > +	unsigned int p_div;
> > > +	unsigned int out_div;
> > > +};
> > > +
> > > +static const struct cpg_clk_config cpg_clk_configs[4] __initconst = {
> > > +	{ 1, 2, 8, 16, 32, 24 },
> > > +	{ 1, 2, 8, 16, 32, 24 },
> > > +	{ 2, 3, 6, 12, 24, 36 },
> > > +	{ 2, 3, 6, 12, 24, 32 },
> > > +};
> > > +
> > > +/*
> > > + *   MD		PLLA Ratio
> > > + * 12 11
> > > + *------------------------
> > > + * 0  0		x42
> > > + * 0  1		x48
> > > + * 1  0		x56
> > > + * 1  1		x64
> > > + */
> > > +#define CPG_PLL_CONFIG_INDEX(md)	((((md) & BIT(14)) >> 12) | \
> > > +					 (((md) & BIT(13)) >> 12) | \
> > > +					 (((md) & BIT(19)) >> 19))
> > > +struct cpg_pll_config {
> > > +	unsigned int extal_div;
> > > +	unsigned int pll1_mult;
> > > +	unsigned int pll3_mult;
> > > +};
> > > +
> > > +#define CPG_PLLA_MULT_INDEX(md)	(((md) & (BIT(12)|BIT(11))) >> 11)
> > > +
> > > +static const unsigned int cpg_plla_mult[4] __initconst = { 42, 48, 56, 64
> > > };
> > > +
> > > +/*
> > > ------------------------------------------------------------------------
> > > + * Initialization
> > > + */
> > > +
> > > +static u32 cpg_mode __initdata;
> > > +
> > > +static struct clk * __init
> > > +r8a7779_cpg_register_clock(struct device_node *np, struct r8a7779_cpg
> > > *cpg, +			   const struct cpg_clk_config *config,
> > > +			   unsigned int plla_mult, const char *name)
> > > +{
> > > +	const char *parent_name = "plla";
> > > +	unsigned int mult = 1;
> > > +	unsigned int div = 1;
> > > +
> > > +	if (!strcmp(name, "plla")) {
> > > +		parent_name = of_clk_get_parent_name(np, 0);
> > > +		mult = plla_mult;
> > > +	} else if (!strcmp(name, "z")) {
> > > +		div = config->z_div;
> > > +		mult = config->z_mult;
> > > +	} else if (!strcmp(name, "zs") || !strcmp(name, "s")) {
> > > +		div = config->zs_and_s_div;
> > > +	} else if (!strcmp(name, "s1")) {
> > > +		div = config->s1_div;
> > > +	} else if (!strcmp(name, "p")) {
> > > +		div = config->p_div;
> > > +	} else if (!strcmp(name, "out")) {
> > > +		div = config->out_div;
> > > +	}
> > 
> > You're missing an
> > 
> > 	else {
> > 		return ERR_PTR5-EINVAL);
> > 	}

Thanks, added.

> > I was tempted to say that it would make sense to read the div values from
> > the FRQMR register instead and remove the need to pass the boot mode bits
> > to the driver, but we need them for the PLLA multiplier anyway :-/
> > 
> > > +
> > > +	return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, 
> div);
> > > +}
> > > +
> > > +static void __init r8a7779_cpg_clocks_init(struct device_node *np)
> > > +{
> > > +	const struct cpg_clk_config *config;
> > > +	struct r8a7779_cpg *cpg;
> > > +	struct clk **clks;
> > > +	unsigned int i, plla_mult;
> > > +	int num_clks;
> > > +
> > > +	num_clks = of_property_count_strings(np, "clock-output-names");
> > > +	if (num_clks < 0) {
> > > +		pr_err("%s: failed to count clocks\n", __func__);
> > > +		return;
> > > +	}
> > > +
> > > +	cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
> > > +	clks = kzalloc(CPG_NUM_CLOCKS * sizeof(*clks), GFP_KERNEL);
> > > +	if (cpg = NULL || clks = NULL) {
> > > +		/* We're leaking memory on purpose, there's no point in cleaning
> > > +		 * up as the system won't boot anyway.
> > > +		 */
> > > +		pr_err("%s: failed to allocate cpg\n", __func__);
> > > +		return;
> > > +	}
> > > +
> > > +	spin_lock_init(&cpg->lock);
> > > +
> > > +	cpg->data.clks = clks;
> > > +	cpg->data.clk_num = num_clks;
> > > +
> > > +	cpg->reg = of_iomap(np, 0);
> > > +	if (WARN_ON(cpg->reg = NULL))
> > > +		return;
> 
> As the driver doesn't access any of the CPG registers this could even be 
> removed.

Thanks, I will remove the above 3 lines.

> > > +
> > > +	config = &cpg_clk_configs[CPG_CLK_CONFIG_INDEX(cpg_mode)];
> > > +	plla_mult = cpg_plla_mult[CPG_PLLA_MULT_INDEX(cpg_mode)];
> > 
> > Given that plla_mult is only used for a single clock, I would move that
> > inside the if (!strcmp(name, "plla")) { } above.
> > 
> > > +
> > > +	for (i = 0; i < num_clks; ++i) {
> > > +		const char *name;
> > > +		struct clk *clk;
> > > +
> > > +		of_property_read_string_index(np, "clock-output-names", i,
> > > +					      &name);
> > > +
> > > +		clk = r8a7779_cpg_register_clock(np, cpg, config,
> > > +						 plla_mult, name);
> > > +		if (IS_ERR(clk))
> > > +			pr_err("%s: failed to register %s %s clock (%ld)\n",
> > > +			       __func__, np->name, name, PTR_ERR(clk));
> > > +		else
> > > +			cpg->data.clks[i] = clk;
> > > +	}
> > > +
> > > +	of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
> > > +}
> > > +CLK_OF_DECLARE(r8a7779_cpg_clks, "renesas,r8a7779-cpg-clocks",
> > > +	       r8a7779_cpg_clocks_init);
> > > +
> > > +void __init r8a7779_clocks_init(u32 mode)
> > > +{
> > > +	cpg_mode = mode;
> > > +
> > > +	of_clk_init(NULL);
> > > +}
> > > diff --git a/include/linux/clk/shmobile.h b/include/linux/clk/shmobile.h
> > > index f9bf080..7667f49 100644
> > > --- a/include/linux/clk/shmobile.h
> > > +++ b/include/linux/clk/shmobile.h
> > > @@ -1,7 +1,9 @@
> > >  /*
> > >   * Copyright 2013 Ideas On Board SPRL
> > > + * Copyright 2013 Horms Solutions Ltd.
> > 
> > 2014 ?

I originally wrote and posted the code last year.
I'll update it to 2013, 2014.

> > 
> > >   *
> > >   * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> > > + * Contact: Simon Horman <horms@verge.net.au>
> > >   *
> > >   * This program is free software; you can redistribute it and/or modify
> > >   * it under the terms of the GNU General Public License as published by
> > > @@ -14,6 +16,7 @@
> > > 
> > >  #include <linux/types.h>
> > > 
> > > +void r8a7779_clocks_init(u32 mode);
> > >  void rcar_gen2_clocks_init(u32 mode);
> > >  
> > >  #endif
> 
> -- 
> Regards,
> 
> Laurent Pinchart
> 

[PATCH v3 01/20] clk: shmobile: r8a7779: Add clocks support

[Simon Horman]

On Wed, Feb 26, 2014 at 02:02:37PM +0100, Laurent Pinchart wrote:
> Hi Simon,
> 
> Two more small comments.
> 
> On Wednesday 26 February 2014 13:53:17 Laurent Pinchart wrote:
> > On Wednesday 26 February 2014 16:33:17 Simon Horman wrote:
> > > The R8A7779 SoC has several clocks that are too custom to be supported in
> > > a generic driver. Those clocks can be divided in two categories:
> > > 
> > > - Fixed rate clocks with multiplier and divisor set according to boot
> > >   mode configuration
> > > 
> > > - Custom divider clocks with SoC-specific divider values
> > > 
> > > This driver supports both.
> > 
> > Looking at the R8A7779 datasheet it looks like we only have fixed rate
> > clocks, without any configurable divider clock. Did I miss something ?

Sorry, its a cut-and past error on my part.
I will revise the changelog.

> > 
> > > Based on work for R-Car Gen2 SoCs by Laurent Pinchart.
> > > 
> > > Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> > > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> > > 
> > > ---
> > > v3
> > > * As suggested by Laurent Pinchart
> > > 
> > >   - Added external clock input
> > >   - Use PLLA ratio set bu MD11 and MD12
> > >   - Add _div suffixes of fields of struct cpt_clk_config
> > >   - Register PLLA as a fixed factor clock
> > >   - Use sizeof() instead of sizeof
> > >   - Use num_clks instead of CPG_NUM_CLOCKS in r8a7779_cpg_clocks_init()
> > >   
> > >   - I kept this as r8a7779 binding rather than moving to a R-Car Gen1
> > >   
> > >     binding which could be shared with other SoCs as I do not believe that
> > >     the SoCs is are sufficiently similar.
> > 
> > I had a look at the M1 datasheet and I still find its CPG very similar with
> > the H1 CPG. The PLLA multiplier and divider are different, but if you look
> > closely, they're both exactly twice the value compared to H1, so there's no
> > difference in practice.
> > 
> > What differences do you see that would make it impractical to share a single
> > driver for both ?

Thanks for pointing that out. Looking over the M1 datasheet again I agree
with you that there does seem to be rather a lot of similarities with the
H1. And I agree that it is likely that the driver could be shared.

However, I'd like to leave that as future work at this time.

The reason for this is that on the one hand I believe such work sould be
done in conjunctin with integrating the driver on the bockw board.
And that seems to be non-trivial to me.

> > 
> > > ---
> > > 
> > >  .../bindings/clock/renesas,r8a7779-cpg-clocks.txt  |  26 +++
> > >  drivers/clk/shmobile/Makefile                      |   1 +
> > >  drivers/clk/shmobile/clk-r8a7779.c                 | 191
> > >  ++++++++++++++++++
> > >  include/linux/clk/shmobile.h                       |   3 +
> > >  4 files changed, 221 insertions(+)
> > >  create mode 100644
> > > 
> > > Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
> > > create mode 100644 drivers/clk/shmobile/clk-r8a7779.c
> > > 
> > > diff --git
> > > a/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
> > > b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
> > > new file mode 100644
> > > index 0000000..1461323
> > > --- /dev/null
> > > +++
> > > b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
> > > @@ -0,0 +1,26 @@
> > > +* Renesas R8A7779 Clock Pulse Generator (CPG)
> > > +
> > > +The CPG generates core clocks for the R8A7779. It includes one PLL and
> > > +and several fixed ratio dividers
> > > +
> > > +Required Properties:
> > > +
> > > +  - compatible: Must be "renesas,r8a7779-cpg-clocks"
> > > +  - reg: Base address and length of the memory resource used by the CPG
> > > +
> > > +  - clocks: Reference to the parent clock
> > > +  - #clock-cells: Must be 1
> > > +  - clock-output-names: The names of the clocks. Supported clocks are
> > > "plla",
> > > +    "z", "zs", "s", "s1", "p", "out".
> > 
> > What about clki, clks3, clks4, clkb and clkg ? Should pllb be exposed as
> > well ?
> 
> I spoke too fast, clki, clks3, clks4 and clkg are fixed factor clocks 
> expressed in DT, my bad. What about clkb though ?

Thanks. I missed clkb. I'll add it.

> 
> > 
> > > +Example
> > > +-------
> > > +
> > > +	cpg_clocks: cpg_clocks at ffc80000 {
> > > +		compatible = "renesas,r8a7779-cpg-clocks";
> > > +		reg = <0 0xffc80000 0 0x80>;
> > 
> > Shouldn't the range be restricted not to include the MSTP registers ? 0x30
> > should be enough.

Thanks, I will fix that.

> > 
> > > +		clocks = <&extal_clk>;
> > > +		#clock-cells = <1>;
> > > +		clock-output-names = "plla", "z", "zs", "s", "s1", "p", "out";
> > > +	};
> > > diff --git a/drivers/clk/shmobile/Makefile b/drivers/clk/shmobile/Makefile
> > > index 9ecef14..2121ba0 100644
> > > --- a/drivers/clk/shmobile/Makefile
> > > +++ b/drivers/clk/shmobile/Makefile
> > > @@ -1,4 +1,5 @@
> > > 
> > >  obj-$(CONFIG_ARCH_EMEV2)		+= clk-emev2.o
> > > 
> > > +obj-$(CONFIG_ARCH_R8A7779)		+= clk-r8a7779.o
> > > 
> > >  obj-$(CONFIG_ARCH_R8A7790)		+= clk-rcar-gen2.o
> > >  obj-$(CONFIG_ARCH_R8A7791)		+= clk-rcar-gen2.o
> > >  obj-$(CONFIG_ARCH_SHMOBILE_MULTI)	+= clk-div6.o
> > > 
> > > diff --git a/drivers/clk/shmobile/clk-r8a7779.c
> > > b/drivers/clk/shmobile/clk-r8a7779.c new file mode 100644
> > > index 0000000..2ca2d67
> > > --- /dev/null
> > > +++ b/drivers/clk/shmobile/clk-r8a7779.c
> > > @@ -0,0 +1,191 @@
> > > +/*
> > > + * r8a7779 Core CPG Clocks
> > > + *
> > > + * Copyright (C) 2013, 2014 Horms Solutions Ltd.
> > > + *
> > > + * Contact: Simon Horman <horms@verge.net.au>
> > > + *
> > > + * This program is free software; you can redistribute it and/or modify
> > > + * it under the terms of the GNU General Public License as published by
> > > + * the Free Software Foundation; version 2 of the License.
> > > + */
> > > +
> > > +#include <linux/clk-provider.h>
> > > +#include <linux/clkdev.h>
> > > +#include <linux/clk/shmobile.h>
> > > +#include <linux/init.h>
> > > +#include <linux/kernel.h>
> > > +#include <linux/of.h>
> > > +#include <linux/of_address.h>
> > > +#include <linux/spinlock.h>
> > > +
> > > +#include <dt-bindings/clock/r8a7779-clock.h>
> > > +
> > > +#define CPG_NUM_CLOCKS			(R8A7779_CLK_OUT + 1)
> > > +
> > > +struct r8a7779_cpg {
> > > +	struct clk_onecell_data data;
> > > +	spinlock_t lock;
> > > +	void __iomem *reg;
> > > +};
> > > +
> > > +/*
> > > --------------------------------------------------------------------------
> > > -
> > > -- + * CPG Clock Data
> > > + */
> > > +
> > > +/*
> > > + *		MD1 = 1			MD1 = 0
> > > + *		(PLLA = 1500)		(PLLA = 1600)
> > > + *		(MHz)			(MHz)
> > > + *------------------------------------------------+--------------------
> > > + * clkz		1000   (2/3)		800   (1/2)
> > > + * clkzs	 250   (1/6)		200   (1/8)
> > > + * clki		 750   (1/2)		800   (1/2)
> > > + * clks		 250   (1/6)		200   (1/8)
> > > + * clks1	 125   (1/12)		100   (1/16)
> > > + * clks3	 187.5 (1/8)		200   (1/8)
> > > + * clks4	  93.7 (1/16)		100   (1/16)
> > > + * clkp		  62.5 (1/24)		 50   (1/32)
> > > + * clkg		  62.5 (1/24)		 66.6 (1/24)
> > > + * clkb, CLKOUT
> > > + * (MD2 = 0)	  62.5 (1/24)		 66.6 (1/24)
> > > + * (MD2 = 1)	  41.6 (1/36)		 50   (1/32)
> > > + */
> > > +
> > > +#define CPG_CLK_CONFIG_INDEX(md)	(((md) & (BIT(1)|BIT(2))) >> 1)
> > > +
> > > +struct cpg_clk_config {
> > > +	unsigned int z_mult;
> > > +	unsigned int z_div;
> > > +	unsigned int zs_and_s_div;
> > > +	unsigned int s1_div;
> > > +	unsigned int p_div;
> > > +	unsigned int out_div;
> > > +};
> > > +
> > > +static const struct cpg_clk_config cpg_clk_configs[4] __initconst = {
> > > +	{ 1, 2, 8, 16, 32, 24 },
> > > +	{ 1, 2, 8, 16, 32, 24 },
> > > +	{ 2, 3, 6, 12, 24, 36 },
> > > +	{ 2, 3, 6, 12, 24, 32 },
> > > +};
> > > +
> > > +/*
> > > + *   MD		PLLA Ratio
> > > + * 12 11
> > > + *------------------------
> > > + * 0  0		x42
> > > + * 0  1		x48
> > > + * 1  0		x56
> > > + * 1  1		x64
> > > + */
> > > +#define CPG_PLL_CONFIG_INDEX(md)	((((md) & BIT(14)) >> 12) | \
> > > +					 (((md) & BIT(13)) >> 12) | \
> > > +					 (((md) & BIT(19)) >> 19))
> > > +struct cpg_pll_config {
> > > +	unsigned int extal_div;
> > > +	unsigned int pll1_mult;
> > > +	unsigned int pll3_mult;
> > > +};
> > > +
> > > +#define CPG_PLLA_MULT_INDEX(md)	(((md) & (BIT(12)|BIT(11))) >> 11)
> > > +
> > > +static const unsigned int cpg_plla_mult[4] __initconst = { 42, 48, 56, 64
> > > };
> > > +
> > > +/*
> > > ------------------------------------------------------------------------
> > > + * Initialization
> > > + */
> > > +
> > > +static u32 cpg_mode __initdata;
> > > +
> > > +static struct clk * __init
> > > +r8a7779_cpg_register_clock(struct device_node *np, struct r8a7779_cpg
> > > *cpg, +			   const struct cpg_clk_config *config,
> > > +			   unsigned int plla_mult, const char *name)
> > > +{
> > > +	const char *parent_name = "plla";
> > > +	unsigned int mult = 1;
> > > +	unsigned int div = 1;
> > > +
> > > +	if (!strcmp(name, "plla")) {
> > > +		parent_name = of_clk_get_parent_name(np, 0);
> > > +		mult = plla_mult;
> > > +	} else if (!strcmp(name, "z")) {
> > > +		div = config->z_div;
> > > +		mult = config->z_mult;
> > > +	} else if (!strcmp(name, "zs") || !strcmp(name, "s")) {
> > > +		div = config->zs_and_s_div;
> > > +	} else if (!strcmp(name, "s1")) {
> > > +		div = config->s1_div;
> > > +	} else if (!strcmp(name, "p")) {
> > > +		div = config->p_div;
> > > +	} else if (!strcmp(name, "out")) {
> > > +		div = config->out_div;
> > > +	}
> > 
> > You're missing an
> > 
> > 	else {
> > 		return ERR_PTR5-EINVAL);
> > 	}

Thanks, added.

> > I was tempted to say that it would make sense to read the div values from
> > the FRQMR register instead and remove the need to pass the boot mode bits
> > to the driver, but we need them for the PLLA multiplier anyway :-/
> > 
> > > +
> > > +	return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, 
> div);
> > > +}
> > > +
> > > +static void __init r8a7779_cpg_clocks_init(struct device_node *np)
> > > +{
> > > +	const struct cpg_clk_config *config;
> > > +	struct r8a7779_cpg *cpg;
> > > +	struct clk **clks;
> > > +	unsigned int i, plla_mult;
> > > +	int num_clks;
> > > +
> > > +	num_clks = of_property_count_strings(np, "clock-output-names");
> > > +	if (num_clks < 0) {
> > > +		pr_err("%s: failed to count clocks\n", __func__);
> > > +		return;
> > > +	}
> > > +
> > > +	cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
> > > +	clks = kzalloc(CPG_NUM_CLOCKS * sizeof(*clks), GFP_KERNEL);
> > > +	if (cpg == NULL || clks == NULL) {
> > > +		/* We're leaking memory on purpose, there's no point in cleaning
> > > +		 * up as the system won't boot anyway.
> > > +		 */
> > > +		pr_err("%s: failed to allocate cpg\n", __func__);
> > > +		return;
> > > +	}
> > > +
> > > +	spin_lock_init(&cpg->lock);
> > > +
> > > +	cpg->data.clks = clks;
> > > +	cpg->data.clk_num = num_clks;
> > > +
> > > +	cpg->reg = of_iomap(np, 0);
> > > +	if (WARN_ON(cpg->reg == NULL))
> > > +		return;
> 
> As the driver doesn't access any of the CPG registers this could even be 
> removed.

Thanks, I will remove the above 3 lines.

> > > +
> > > +	config = &cpg_clk_configs[CPG_CLK_CONFIG_INDEX(cpg_mode)];
> > > +	plla_mult = cpg_plla_mult[CPG_PLLA_MULT_INDEX(cpg_mode)];
> > 
> > Given that plla_mult is only used for a single clock, I would move that
> > inside the if (!strcmp(name, "plla")) { } above.
> > 
> > > +
> > > +	for (i = 0; i < num_clks; ++i) {
> > > +		const char *name;
> > > +		struct clk *clk;
> > > +
> > > +		of_property_read_string_index(np, "clock-output-names", i,
> > > +					      &name);
> > > +
> > > +		clk = r8a7779_cpg_register_clock(np, cpg, config,
> > > +						 plla_mult, name);
> > > +		if (IS_ERR(clk))
> > > +			pr_err("%s: failed to register %s %s clock (%ld)\n",
> > > +			       __func__, np->name, name, PTR_ERR(clk));
> > > +		else
> > > +			cpg->data.clks[i] = clk;
> > > +	}
> > > +
> > > +	of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
> > > +}
> > > +CLK_OF_DECLARE(r8a7779_cpg_clks, "renesas,r8a7779-cpg-clocks",
> > > +	       r8a7779_cpg_clocks_init);
> > > +
> > > +void __init r8a7779_clocks_init(u32 mode)
> > > +{
> > > +	cpg_mode = mode;
> > > +
> > > +	of_clk_init(NULL);
> > > +}
> > > diff --git a/include/linux/clk/shmobile.h b/include/linux/clk/shmobile.h
> > > index f9bf080..7667f49 100644
> > > --- a/include/linux/clk/shmobile.h
> > > +++ b/include/linux/clk/shmobile.h
> > > @@ -1,7 +1,9 @@
> > >  /*
> > >   * Copyright 2013 Ideas On Board SPRL
> > > + * Copyright 2013 Horms Solutions Ltd.
> > 
> > 2014 ?

I originally wrote and posted the code last year.
I'll update it to 2013, 2014.

> > 
> > >   *
> > >   * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> > > + * Contact: Simon Horman <horms@verge.net.au>
> > >   *
> > >   * This program is free software; you can redistribute it and/or modify
> > >   * it under the terms of the GNU General Public License as published by
> > > @@ -14,6 +16,7 @@
> > > 
> > >  #include <linux/types.h>
> > > 
> > > +void r8a7779_clocks_init(u32 mode);
> > >  void rcar_gen2_clocks_init(u32 mode);
> > >  
> > >  #endif
> 
> -- 
> Regards,
> 
> Laurent Pinchart
> 

Re: [PATCH v3 04/20] ARM: shmobile: r8a7779: Add clocks

[Simon Horman]

On Wed, Feb 26, 2014 at 02:15:14PM +0100, Laurent Pinchart wrote:
> Hi Simon,
> 
> Thank you for the patch.

Thanks, I will address these problems.

> 
> On Wednesday 26 February 2014 16:33:20 Simon Horman wrote:
> > Declare all core and MSTP clocks currently used by r8a7779-based boards.
> > 
> > Based on work by Laurent Pinchart for the r8a7790 and r8a7791 SoCs.
> > 
> > Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> > 
> > ---
> > v3
> > * As suggested by Laurent Pinchart
> >   - Add and use extal_clk
> >   - Fix bogus status register use for MSTP clocks
> >   - Fix bogus mstp3_cls to use its own entries rather than
> >     that of mstp1_clks
> > 
> > * Update to use "main" in cpg_clocks as per updated
> >   binding in previous patch
> > * Update for new, consolidated and renamed index macros
> >   - R8A7779_CLK_ETHER
> >   - R8A7779_CLK_HSCIF
> >   - R8A7779_CLK_HSPI
> >   - R8A7779_CLK_MMC0,1
> >   - R8A7779_CLK_PCIE
> >   - R8A7779_CLK_USB01,2
> > ---
> >  arch/arm/boot/dts/r8a7779.dtsi | 129 ++++++++++++++++++++++++++++++++++++++
> >  1 file changed, 129 insertions(+)
> > 
> > diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
> > index d0561d4..240a03e 100644
> > --- a/arch/arm/boot/dts/r8a7779.dtsi
> > +++ b/arch/arm/boot/dts/r8a7779.dtsi
> > @@ -11,6 +11,7 @@
> > 
> >  /include/ "skeleton.dtsi"
> > 
> > +#include <dt-bindings/clock/r8a7779-clock.h>
> >  #include <dt-bindings/interrupt-controller/irq.h>
> > 
> >  / {
> > @@ -278,4 +279,132 @@
> >  		interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
> >  		status = "disabled";
> >  	};
> > +
> > +	clocks {
> > +		#address-cells = <2>;
> > +		#size-cells = <2>;
> > +		ranges;
> > +
> > +		/* External root clock */
> > +		extal_clk: extal_clk {
> > +			compatible = "fixed-clock";
> > +			#clock-cells = <0>;
> > +			/* This value must be overriden by the board. */
> > +			clock-frequency = <0>;
> > +			clock-output-names = "extal";
> > +		};
> > +
> > +		/* Special CPG clocks */
> > +		cpg_clocks: cpg_clocks@0xe6150000 {
> > +			compatible = "renesas,r8a7779-cpg-clocks";
> > +			reg = <0 0xe6150000 0 0x1000>;
> > +			clocks = <&extal_clk>;
> > +			#clock-cells = <1>;
> > +			clock-output-names = "plla", "z", "zs", "s",
> > +					     "s1", "p", "out";
> > +		};
> > +
> > +		/* Fixed factor clocks */
> > +		i_clk: i_clk {
> > +			compatible = "fixed-factor-clock";
> > +			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
> > +			#clock-cells = <0>;
> > +			clock-div = <2>;
> > +			clock-mult = <1>;
> > +			clock-output-names = "i";
> > +		};
> > +		s3_clk: s3_clk {
> > +			compatible = "fixed-factor-clock";
> > +			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
> > +			#clock-cells = <0>;
> > +			clock-div = <8>;
> > +			clock-mult = <1>;
> > +			clock-output-names = "s3";
> > +		};
> > +		s4_clk: s4_clk {
> > +			compatible = "fixed-factor-clock";
> > +			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
> > +			#clock-cells = <0>;
> > +			clock-div = <16>;
> > +			clock-mult = <1>;
> > +			clock-output-names = "s4";
> > +		};
> > +		g_clk: g_clk {
> > +			compatible = "fixed-factor-clock";
> > +			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
> > +			#clock-cells = <0>;
> > +			clock-div = <24>;
> > +			clock-mult = <1>;
> > +			clock-output-names = "g";
> > +		};
> > +
> > +		/* Gate clocks */
> > +		mstp0_clks: mstp0_clks {
> > +			compatible = "renesas,r8a7779-mstp-clocks", "renesas,cpg-mstp-
> clocks";
> > +			reg = <0 0xffc80030 0 4>;
> > +			clocks = <&cpg_clocks R8A7779_CLK_P>,
> > <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> > +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> > <&cpg_clocks R8A7779_CLK_P>,
> > +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> > <&cpg_clocks R8A7779_CLK_P>,
> > +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> > <&cpg_clocks R8A7779_CLK_P>,
> > +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> > <&cpg_clocks R8A7779_CLK_P>,
> > +				 <&cpg_clocks R8A7779_CLK_P>;
> 
> Aren't the HSPI and HSCIF parent clocks clks ? Aren't the SCIF parent clocks 
> clks1 ?
> 
> > +			#clock-cells = <1>;
> > +			renesas,clock-indices = <
> > +				R8A7779_CLK_HSPI R8A7779_CLK_TMU0 R8A7779_CLK_TMU0
> > +				R8A7779_CLK_TMU0 R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
> > +				R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2 R8A7779_CLK_SCIF1
> > +				R8A7779_CLK_SCIF0 R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
> > +				R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
> > +			>;
> > +			clock-output-names > > +				"hspi", "tmu00", "tmu01",
> > +				"tmu02", "scif5", "scif4",
> 
> The clock names should be tmu0, tmu1 and tmu2, not tmu00, tmu01 and tmu02.
> 
> > +				"scif3", "scif2", "scif1",
> > +				"scif0", "i2c3", "i2c2",
> > +				"i2c1", "i2c0";
> > +		};
> > +		mstp1_clks: mstp1_clks {
> > +			compatible = "renesas,r8a7779-mstp-clocks", "renesas,cpg-mstp-
> clocks";
> > +			reg = <0 0xffc80034 0 4>, <0 0xffc80044 0 4>;
> > +			clocks = <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks 
> R8A7779_CLK_P>,
> > +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> > +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> > +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> > +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> > +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>;
> 
> Please verify the clock parents here as well.
> 
> > +			#clock-cells = <1>;
> > +			renesas,clock-indices = <
> > +				R8A7779_CLK_USB01 R8A7779_CLK_USB01
> > +				R8A7779_CLK_USB2 R8A7779_CLK_USB2
> > +				R8A7779_CLK_DU R8A7779_CLK_VIN2
> > +				R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
> > +				R8A7779_CLK_ETHER R8A7779_CLK_SATA
> > +				R8A7779_CLK_PCIE R8A7779_CLK_VIN3
> > +			>;
> > +			clock-output-names > > +				"ehci0", "ohci0",
> > +				"ehci1", "ohci1",
> > +				"du", "vin2",
> > +				"vin1", "vin0",
> > +				"ether", "sata",
> > +				"pcie", "vin3";
> > +		};
> > +		mstp3_clks: mstp3_clks {
> > +			compatible = "renesas,r8a7779-mstp-clocks", "renesas,cpg-mstp-
> clocks";
> > +			reg = <0 0xffc8003c 0 4>;
> > +			clocks = <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks 
> R8A7779_CLK_P>,
> > +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> > +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>;
> 
> Aren't the MMC and SDHI parent clocks clks4 ?
> 
> > +			#clock-cells = <1>;
> > +			renesas,clock-indices = <
> > +				R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
> > +				R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
> > +				R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
> > +			>;
> > +			clock-output-names > > +				"sdhi3", "sdhi2",
> > +				"sdhi1", "sdhi0",
> > +				"mmc1", "mmc0";
> > +		};
> > +	};
> >  };
> 
> -- 
> Regards,
> 
> Laurent Pinchart
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-sh" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 

[PATCH v3 04/20] ARM: shmobile: r8a7779: Add clocks

[Simon Horman]

On Wed, Feb 26, 2014 at 02:15:14PM +0100, Laurent Pinchart wrote:
> Hi Simon,
> 
> Thank you for the patch.

Thanks, I will address these problems.

> 
> On Wednesday 26 February 2014 16:33:20 Simon Horman wrote:
> > Declare all core and MSTP clocks currently used by r8a7779-based boards.
> > 
> > Based on work by Laurent Pinchart for the r8a7790 and r8a7791 SoCs.
> > 
> > Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> > 
> > ---
> > v3
> > * As suggested by Laurent Pinchart
> >   - Add and use extal_clk
> >   - Fix bogus status register use for MSTP clocks
> >   - Fix bogus mstp3_cls to use its own entries rather than
> >     that of mstp1_clks
> > 
> > * Update to use "main" in cpg_clocks as per updated
> >   binding in previous patch
> > * Update for new, consolidated and renamed index macros
> >   - R8A7779_CLK_ETHER
> >   - R8A7779_CLK_HSCIF
> >   - R8A7779_CLK_HSPI
> >   - R8A7779_CLK_MMC0,1
> >   - R8A7779_CLK_PCIE
> >   - R8A7779_CLK_USB01,2
> > ---
> >  arch/arm/boot/dts/r8a7779.dtsi | 129 ++++++++++++++++++++++++++++++++++++++
> >  1 file changed, 129 insertions(+)
> > 
> > diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
> > index d0561d4..240a03e 100644
> > --- a/arch/arm/boot/dts/r8a7779.dtsi
> > +++ b/arch/arm/boot/dts/r8a7779.dtsi
> > @@ -11,6 +11,7 @@
> > 
> >  /include/ "skeleton.dtsi"
> > 
> > +#include <dt-bindings/clock/r8a7779-clock.h>
> >  #include <dt-bindings/interrupt-controller/irq.h>
> > 
> >  / {
> > @@ -278,4 +279,132 @@
> >  		interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
> >  		status = "disabled";
> >  	};
> > +
> > +	clocks {
> > +		#address-cells = <2>;
> > +		#size-cells = <2>;
> > +		ranges;
> > +
> > +		/* External root clock */
> > +		extal_clk: extal_clk {
> > +			compatible = "fixed-clock";
> > +			#clock-cells = <0>;
> > +			/* This value must be overriden by the board. */
> > +			clock-frequency = <0>;
> > +			clock-output-names = "extal";
> > +		};
> > +
> > +		/* Special CPG clocks */
> > +		cpg_clocks: cpg_clocks at 0xe6150000 {
> > +			compatible = "renesas,r8a7779-cpg-clocks";
> > +			reg = <0 0xe6150000 0 0x1000>;
> > +			clocks = <&extal_clk>;
> > +			#clock-cells = <1>;
> > +			clock-output-names = "plla", "z", "zs", "s",
> > +					     "s1", "p", "out";
> > +		};
> > +
> > +		/* Fixed factor clocks */
> > +		i_clk: i_clk {
> > +			compatible = "fixed-factor-clock";
> > +			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
> > +			#clock-cells = <0>;
> > +			clock-div = <2>;
> > +			clock-mult = <1>;
> > +			clock-output-names = "i";
> > +		};
> > +		s3_clk: s3_clk {
> > +			compatible = "fixed-factor-clock";
> > +			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
> > +			#clock-cells = <0>;
> > +			clock-div = <8>;
> > +			clock-mult = <1>;
> > +			clock-output-names = "s3";
> > +		};
> > +		s4_clk: s4_clk {
> > +			compatible = "fixed-factor-clock";
> > +			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
> > +			#clock-cells = <0>;
> > +			clock-div = <16>;
> > +			clock-mult = <1>;
> > +			clock-output-names = "s4";
> > +		};
> > +		g_clk: g_clk {
> > +			compatible = "fixed-factor-clock";
> > +			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
> > +			#clock-cells = <0>;
> > +			clock-div = <24>;
> > +			clock-mult = <1>;
> > +			clock-output-names = "g";
> > +		};
> > +
> > +		/* Gate clocks */
> > +		mstp0_clks: mstp0_clks {
> > +			compatible = "renesas,r8a7779-mstp-clocks", "renesas,cpg-mstp-
> clocks";
> > +			reg = <0 0xffc80030 0 4>;
> > +			clocks = <&cpg_clocks R8A7779_CLK_P>,
> > <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> > +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> > <&cpg_clocks R8A7779_CLK_P>,
> > +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> > <&cpg_clocks R8A7779_CLK_P>,
> > +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> > <&cpg_clocks R8A7779_CLK_P>,
> > +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> > <&cpg_clocks R8A7779_CLK_P>,
> > +				 <&cpg_clocks R8A7779_CLK_P>;
> 
> Aren't the HSPI and HSCIF parent clocks clks ? Aren't the SCIF parent clocks 
> clks1 ?
> 
> > +			#clock-cells = <1>;
> > +			renesas,clock-indices = <
> > +				R8A7779_CLK_HSPI R8A7779_CLK_TMU0 R8A7779_CLK_TMU0
> > +				R8A7779_CLK_TMU0 R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
> > +				R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2 R8A7779_CLK_SCIF1
> > +				R8A7779_CLK_SCIF0 R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
> > +				R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
> > +			>;
> > +			clock-output-names =
> > +				"hspi", "tmu00", "tmu01",
> > +				"tmu02", "scif5", "scif4",
> 
> The clock names should be tmu0, tmu1 and tmu2, not tmu00, tmu01 and tmu02.
> 
> > +				"scif3", "scif2", "scif1",
> > +				"scif0", "i2c3", "i2c2",
> > +				"i2c1", "i2c0";
> > +		};
> > +		mstp1_clks: mstp1_clks {
> > +			compatible = "renesas,r8a7779-mstp-clocks", "renesas,cpg-mstp-
> clocks";
> > +			reg = <0 0xffc80034 0 4>, <0 0xffc80044 0 4>;
> > +			clocks = <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks 
> R8A7779_CLK_P>,
> > +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> > +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> > +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> > +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> > +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>;
> 
> Please verify the clock parents here as well.
> 
> > +			#clock-cells = <1>;
> > +			renesas,clock-indices = <
> > +				R8A7779_CLK_USB01 R8A7779_CLK_USB01
> > +				R8A7779_CLK_USB2 R8A7779_CLK_USB2
> > +				R8A7779_CLK_DU R8A7779_CLK_VIN2
> > +				R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
> > +				R8A7779_CLK_ETHER R8A7779_CLK_SATA
> > +				R8A7779_CLK_PCIE R8A7779_CLK_VIN3
> > +			>;
> > +			clock-output-names =
> > +				"ehci0", "ohci0",
> > +				"ehci1", "ohci1",
> > +				"du", "vin2",
> > +				"vin1", "vin0",
> > +				"ether", "sata",
> > +				"pcie", "vin3";
> > +		};
> > +		mstp3_clks: mstp3_clks {
> > +			compatible = "renesas,r8a7779-mstp-clocks", "renesas,cpg-mstp-
> clocks";
> > +			reg = <0 0xffc8003c 0 4>;
> > +			clocks = <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks 
> R8A7779_CLK_P>,
> > +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> > +				 <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>;
> 
> Aren't the MMC and SDHI parent clocks clks4 ?
> 
> > +			#clock-cells = <1>;
> > +			renesas,clock-indices = <
> > +				R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
> > +				R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
> > +				R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
> > +			>;
> > +			clock-output-names =
> > +				"sdhi3", "sdhi2",
> > +				"sdhi1", "sdhi0",
> > +				"mmc1", "mmc0";
> > +		};
> > +	};
> >  };
> 
> -- 
> Regards,
> 
> Laurent Pinchart
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-sh" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 

Re: [PATCH v3 04/20] ARM: shmobile: r8a7779: Add clocks

[Simon Horman]

On Wed, Feb 26, 2014 at 03:45:03PM +0100, Laurent Pinchart wrote:
> Hi Simon,
> 
> One more comment.
> 
> On Wednesday 26 February 2014 16:33:20 Simon Horman wrote:
> > Declare all core and MSTP clocks currently used by r8a7779-based boards.
> > 
> > Based on work by Laurent Pinchart for the r8a7790 and r8a7791 SoCs.
> > 
> > Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> > 
> > ---
> > v3
> > * As suggested by Laurent Pinchart
> >   - Add and use extal_clk
> >   - Fix bogus status register use for MSTP clocks
> >   - Fix bogus mstp3_cls to use its own entries rather than
> >     that of mstp1_clks
> > 
> > * Update to use "main" in cpg_clocks as per updated
> >   binding in previous patch
> > * Update for new, consolidated and renamed index macros
> >   - R8A7779_CLK_ETHER
> >   - R8A7779_CLK_HSCIF
> >   - R8A7779_CLK_HSPI
> >   - R8A7779_CLK_MMC0,1
> >   - R8A7779_CLK_PCIE
> >   - R8A7779_CLK_USB01,2
> > ---
> >  arch/arm/boot/dts/r8a7779.dtsi | 129 ++++++++++++++++++++++++++++++++++++++
> >  1 file changed, 129 insertions(+)
> > 
> > diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
> > index d0561d4..240a03e 100644
> > --- a/arch/arm/boot/dts/r8a7779.dtsi
> > +++ b/arch/arm/boot/dts/r8a7779.dtsi
> > @@ -11,6 +11,7 @@
> > 
> >  /include/ "skeleton.dtsi"
> > 
> > +#include <dt-bindings/clock/r8a7779-clock.h>
> >  #include <dt-bindings/interrupt-controller/irq.h>
> > 
> >  / {
> > @@ -278,4 +279,132 @@
> >  		interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
> >  		status = "disabled";
> >  	};
> > +
> > +	clocks {
> > +		#address-cells = <2>;
> > +		#size-cells = <2>;
> > +		ranges;
> > +
> > +		/* External root clock */
> > +		extal_clk: extal_clk {
> > +			compatible = "fixed-clock";
> > +			#clock-cells = <0>;
> > +			/* This value must be overriden by the board. */
> > +			clock-frequency = <0>;
> > +			clock-output-names = "extal";
> > +		};
> > +
> > +		/* Special CPG clocks */
> > +		cpg_clocks: cpg_clocks@0xe6150000 {
> > +			compatible = "renesas,r8a7779-cpg-clocks";
> > +			reg = <0 0xe6150000 0 0x1000>;
> 
> Copied from H2 ? :-) This should probably be

Thanks :)

[PATCH v3 04/20] ARM: shmobile: r8a7779: Add clocks

[Simon Horman]

On Wed, Feb 26, 2014 at 03:45:03PM +0100, Laurent Pinchart wrote:
> Hi Simon,
> 
> One more comment.
> 
> On Wednesday 26 February 2014 16:33:20 Simon Horman wrote:
> > Declare all core and MSTP clocks currently used by r8a7779-based boards.
> > 
> > Based on work by Laurent Pinchart for the r8a7790 and r8a7791 SoCs.
> > 
> > Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> > 
> > ---
> > v3
> > * As suggested by Laurent Pinchart
> >   - Add and use extal_clk
> >   - Fix bogus status register use for MSTP clocks
> >   - Fix bogus mstp3_cls to use its own entries rather than
> >     that of mstp1_clks
> > 
> > * Update to use "main" in cpg_clocks as per updated
> >   binding in previous patch
> > * Update for new, consolidated and renamed index macros
> >   - R8A7779_CLK_ETHER
> >   - R8A7779_CLK_HSCIF
> >   - R8A7779_CLK_HSPI
> >   - R8A7779_CLK_MMC0,1
> >   - R8A7779_CLK_PCIE
> >   - R8A7779_CLK_USB01,2
> > ---
> >  arch/arm/boot/dts/r8a7779.dtsi | 129 ++++++++++++++++++++++++++++++++++++++
> >  1 file changed, 129 insertions(+)
> > 
> > diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
> > index d0561d4..240a03e 100644
> > --- a/arch/arm/boot/dts/r8a7779.dtsi
> > +++ b/arch/arm/boot/dts/r8a7779.dtsi
> > @@ -11,6 +11,7 @@
> > 
> >  /include/ "skeleton.dtsi"
> > 
> > +#include <dt-bindings/clock/r8a7779-clock.h>
> >  #include <dt-bindings/interrupt-controller/irq.h>
> > 
> >  / {
> > @@ -278,4 +279,132 @@
> >  		interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
> >  		status = "disabled";
> >  	};
> > +
> > +	clocks {
> > +		#address-cells = <2>;
> > +		#size-cells = <2>;
> > +		ranges;
> > +
> > +		/* External root clock */
> > +		extal_clk: extal_clk {
> > +			compatible = "fixed-clock";
> > +			#clock-cells = <0>;
> > +			/* This value must be overriden by the board. */
> > +			clock-frequency = <0>;
> > +			clock-output-names = "extal";
> > +		};
> > +
> > +		/* Special CPG clocks */
> > +		cpg_clocks: cpg_clocks at 0xe6150000 {
> > +			compatible = "renesas,r8a7779-cpg-clocks";
> > +			reg = <0 0xe6150000 0 0x1000>;
> 
> Copied from H2 ? :-) This should probably be

Thanks :)

Re: [PATCH v3 01/20] clk: shmobile: r8a7779: Add clocks support

[Laurent Pinchart]

Hi Simon,

On Wednesday 12 March 2014 16:55:23 Simon Horman wrote:
> On Wed, Feb 26, 2014 at 02:02:37PM +0100, Laurent Pinchart wrote:
 > On Wednesday 26 February 2014 13:53:17 Laurent Pinchart wrote:
> > > On Wednesday 26 February 2014 16:33:17 Simon Horman wrote:
> > > > The R8A7779 SoC has several clocks that are too custom to be supported
> > > > in a generic driver. Those clocks can be divided in two categories:
> > > > 
> > > > - Fixed rate clocks with multiplier and divisor set according to boot
> > > >   mode configuration
> > > > 
> > > > - Custom divider clocks with SoC-specific divider values
> > > > 
> > > > This driver supports both.
> > > 
> > > Looking at the R8A7779 datasheet it looks like we only have fixed rate
> > > clocks, without any configurable divider clock. Did I miss something ?
> 
> Sorry, its a cut-and past error on my part.
> I will revise the changelog.
> 
> > > > Based on work for R-Car Gen2 SoCs by Laurent Pinchart.
> > > > 
> > > > Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> > > > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> > > > 
> > > > ---
> > > > v3
> > > > * As suggested by Laurent Pinchart
> > > > 
> > > >   - Added external clock input
> > > >   - Use PLLA ratio set bu MD11 and MD12
> > > >   - Add _div suffixes of fields of struct cpt_clk_config
> > > >   - Register PLLA as a fixed factor clock
> > > >   - Use sizeof() instead of sizeof
> > > >   - Use num_clks instead of CPG_NUM_CLOCKS in
> > > >   r8a7779_cpg_clocks_init()
> > > >   
> > > >   - I kept this as r8a7779 binding rather than moving to a R-Car Gen1
> > > >     binding which could be shared with other SoCs as I do not believe
> > > >     that the SoCs is are sufficiently similar.
> > > 
> > > I had a look at the M1 datasheet and I still find its CPG very similar
> > > with the H1 CPG. The PLLA multiplier and divider are different, but if
> > > you look closely, they're both exactly twice the value compared to H1,
> > > so there's no difference in practice.
> > > 
> > > What differences do you see that would make it impractical to share a
> > > single driver for both ?
> 
> Thanks for pointing that out. Looking over the M1 datasheet again I agree
> with you that there does seem to be rather a lot of similarities with the
> H1. And I agree that it is likely that the driver could be shared.
> 
> However, I'd like to leave that as future work at this time.
> 
> The reason for this is that on the one hand I believe such work sould be
> done in conjunctin with integrating the driver on the bockw board.
> And that seems to be non-trivial to me.

We can always rename the driver later, that's not a big issue, but we can't 
change compatibility strings. I would thus like to see "renesas,rcar-gen1-cpg-
clocks" listed in the DT bindings.

-- 
Regards,

Laurent Pinchart

[PATCH v3 01/20] clk: shmobile: r8a7779: Add clocks support

[Laurent Pinchart]

Hi Simon,

On Wednesday 12 March 2014 16:55:23 Simon Horman wrote:
> On Wed, Feb 26, 2014 at 02:02:37PM +0100, Laurent Pinchart wrote:
 > On Wednesday 26 February 2014 13:53:17 Laurent Pinchart wrote:
> > > On Wednesday 26 February 2014 16:33:17 Simon Horman wrote:
> > > > The R8A7779 SoC has several clocks that are too custom to be supported
> > > > in a generic driver. Those clocks can be divided in two categories:
> > > > 
> > > > - Fixed rate clocks with multiplier and divisor set according to boot
> > > >   mode configuration
> > > > 
> > > > - Custom divider clocks with SoC-specific divider values
> > > > 
> > > > This driver supports both.
> > > 
> > > Looking at the R8A7779 datasheet it looks like we only have fixed rate
> > > clocks, without any configurable divider clock. Did I miss something ?
> 
> Sorry, its a cut-and past error on my part.
> I will revise the changelog.
> 
> > > > Based on work for R-Car Gen2 SoCs by Laurent Pinchart.
> > > > 
> > > > Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> > > > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> > > > 
> > > > ---
> > > > v3
> > > > * As suggested by Laurent Pinchart
> > > > 
> > > >   - Added external clock input
> > > >   - Use PLLA ratio set bu MD11 and MD12
> > > >   - Add _div suffixes of fields of struct cpt_clk_config
> > > >   - Register PLLA as a fixed factor clock
> > > >   - Use sizeof() instead of sizeof
> > > >   - Use num_clks instead of CPG_NUM_CLOCKS in
> > > >   r8a7779_cpg_clocks_init()
> > > >   
> > > >   - I kept this as r8a7779 binding rather than moving to a R-Car Gen1
> > > >     binding which could be shared with other SoCs as I do not believe
> > > >     that the SoCs is are sufficiently similar.
> > > 
> > > I had a look at the M1 datasheet and I still find its CPG very similar
> > > with the H1 CPG. The PLLA multiplier and divider are different, but if
> > > you look closely, they're both exactly twice the value compared to H1,
> > > so there's no difference in practice.
> > > 
> > > What differences do you see that would make it impractical to share a
> > > single driver for both ?
> 
> Thanks for pointing that out. Looking over the M1 datasheet again I agree
> with you that there does seem to be rather a lot of similarities with the
> H1. And I agree that it is likely that the driver could be shared.
> 
> However, I'd like to leave that as future work at this time.
> 
> The reason for this is that on the one hand I believe such work sould be
> done in conjunctin with integrating the driver on the bockw board.
> And that seems to be non-trivial to me.

We can always rename the driver later, that's not a big issue, but we can't 
change compatibility strings. I would thus like to see "renesas,rcar-gen1-cpg-
clocks" listed in the DT bindings.

-- 
Regards,

Laurent Pinchart

Re: [PATCH v3 15/20] ARM: shmobile: marzen-reference: Instantiate clkdevs for SCIF and TMU

[Simon Horman]

On Wed, Feb 26, 2014 at 02:24:01PM +0100, Laurent Pinchart wrote:
> Hi Simon,
> 
> Thank you for the patch.
> 
> On Wednesday 26 February 2014 16:33:31 Simon Horman wrote:
> > Now that the common clock framework is supported, the clock lookup
> > entries in clock-r8a7779.c are not registered anymore. Devices must
> > instead reference their clocks in the device tree. However, SCIF and CMT
> > devices are still instantiated through platform code, and thus need a
> > clock lookup entry.
> > 
> > Retrieve the SCIF and CMT clock entries by name and register clkdevs for
> > the corresponding devices. This will be removed when the SCIF and CMT
> > devices will be instantiated from the device tree.
> > 
> > Based on work for the Koelsch board by Laurent Pinchart.
> > 
> > Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> > 
> > ---
> > v3
> > * Initialise TMU clocks instead of CMT clocks
> >   - It is TMU that Marzen uses as a clocksource
> > * Refactor clock initialisation hack as per more recent mainline
> >   code for Koelsch
> > * Use IS_ERR to check the return value of clk_get()
> > ---
> >  arch/arm/mach-shmobile/board-marzen-reference.c | 31 +++++++++++++++++++++-
> > 1 file changed, 30 insertions(+), 1 deletion(-)
> > 
> > diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c
> > b/arch/arm/mach-shmobile/board-marzen-reference.c index e261431..a5974d2
> > 100644
> > --- a/arch/arm/mach-shmobile/board-marzen-reference.c
> > +++ b/arch/arm/mach-shmobile/board-marzen-reference.c
> > @@ -19,7 +19,9 @@
> >   * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 
> > USA */
> > 
> > +#include <linux/clk.h>
> >  #include <linux/clk/shmobile.h>
> > +#include <linux/clkdev.h>
> >  #include <linux/clocksource.h>
> >  #include <linux/of_platform.h>
> >  #include <mach/r8a7779.h>
> > @@ -38,7 +40,34 @@ static void __init marzen_init_timer(void)
> > 
> >  static void __init marzen_init(void)
> >  {
> > -#ifndef CONFIG_COMMON_CLK
> > +#ifdef CONFIG_COMMON_CLK
> > +	static const struct clk_name {
> > +		const char *clk;
> > +		const char *con_id;
> > +		const char *dev_id;
> > +	} clk_names[] = {
> > +		{ "scif0", NULL, "sh-sci.0" },
> > +		{ "scif1", NULL, "sh-sci.1" },
> > +		{ "scif2", NULL, "sh-sci.2" },
> > +		{ "scif3", NULL, "sh-sci.3" },
> > +		{ "scif4", NULL, "sh-sci.4" },
> > +		{ "scif5", NULL, "sh-sci.5" },
> 
> Any chance to switch the board the DT-based SCIF instead ? ;-)

As is typical for me, I'd like to handle that as a follow-up
rather than a pre-requisite.

> 
> > +		{ "tmu00", NULL, "sh_tmu.0" },
> > +		{ "tmu01", NULL, "sh_tmu.1" },
> > +		{ "tmu02", NULL, "sh_tmu.2" },
> 
> Those clocks should be tmu0, tmu1 and tmu2.

Thanks, I have fixed that.

> 
> > +	};
> > +	struct clk *clk;
> > +	unsigned int i;
> > +
> > +	for (i = 0; i < ARRAY_SIZE(clk_names); ++i) {
> > +		clk = clk_get(NULL, clk_names[i].clk);
> > +		if (!IS_ERR(clk)) {
> > +			clk_register_clkdev(clk, clk_names[i].con_id,
> > +					    clk_names[i].dev_id);
> > +			clk_put(clk);
> > +		}
> > +	}
> > +#else
> >  	r8a7779_clock_init();
> >  #endif
> >  	r8a7779_add_standard_devices_dt();
> 
> -- 
> Regards,
> 
> Laurent Pinchart
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-sh" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 

[PATCH v3 15/20] ARM: shmobile: marzen-reference: Instantiate clkdevs for SCIF and TMU

[Simon Horman]

On Wed, Feb 26, 2014 at 02:24:01PM +0100, Laurent Pinchart wrote:
> Hi Simon,
> 
> Thank you for the patch.
> 
> On Wednesday 26 February 2014 16:33:31 Simon Horman wrote:
> > Now that the common clock framework is supported, the clock lookup
> > entries in clock-r8a7779.c are not registered anymore. Devices must
> > instead reference their clocks in the device tree. However, SCIF and CMT
> > devices are still instantiated through platform code, and thus need a
> > clock lookup entry.
> > 
> > Retrieve the SCIF and CMT clock entries by name and register clkdevs for
> > the corresponding devices. This will be removed when the SCIF and CMT
> > devices will be instantiated from the device tree.
> > 
> > Based on work for the Koelsch board by Laurent Pinchart.
> > 
> > Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> > 
> > ---
> > v3
> > * Initialise TMU clocks instead of CMT clocks
> >   - It is TMU that Marzen uses as a clocksource
> > * Refactor clock initialisation hack as per more recent mainline
> >   code for Koelsch
> > * Use IS_ERR to check the return value of clk_get()
> > ---
> >  arch/arm/mach-shmobile/board-marzen-reference.c | 31 +++++++++++++++++++++-
> > 1 file changed, 30 insertions(+), 1 deletion(-)
> > 
> > diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c
> > b/arch/arm/mach-shmobile/board-marzen-reference.c index e261431..a5974d2
> > 100644
> > --- a/arch/arm/mach-shmobile/board-marzen-reference.c
> > +++ b/arch/arm/mach-shmobile/board-marzen-reference.c
> > @@ -19,7 +19,9 @@
> >   * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 
> > USA */
> > 
> > +#include <linux/clk.h>
> >  #include <linux/clk/shmobile.h>
> > +#include <linux/clkdev.h>
> >  #include <linux/clocksource.h>
> >  #include <linux/of_platform.h>
> >  #include <mach/r8a7779.h>
> > @@ -38,7 +40,34 @@ static void __init marzen_init_timer(void)
> > 
> >  static void __init marzen_init(void)
> >  {
> > -#ifndef CONFIG_COMMON_CLK
> > +#ifdef CONFIG_COMMON_CLK
> > +	static const struct clk_name {
> > +		const char *clk;
> > +		const char *con_id;
> > +		const char *dev_id;
> > +	} clk_names[] = {
> > +		{ "scif0", NULL, "sh-sci.0" },
> > +		{ "scif1", NULL, "sh-sci.1" },
> > +		{ "scif2", NULL, "sh-sci.2" },
> > +		{ "scif3", NULL, "sh-sci.3" },
> > +		{ "scif4", NULL, "sh-sci.4" },
> > +		{ "scif5", NULL, "sh-sci.5" },
> 
> Any chance to switch the board the DT-based SCIF instead ? ;-)

As is typical for me, I'd like to handle that as a follow-up
rather than a pre-requisite.

> 
> > +		{ "tmu00", NULL, "sh_tmu.0" },
> > +		{ "tmu01", NULL, "sh_tmu.1" },
> > +		{ "tmu02", NULL, "sh_tmu.2" },
> 
> Those clocks should be tmu0, tmu1 and tmu2.

Thanks, I have fixed that.

> 
> > +	};
> > +	struct clk *clk;
> > +	unsigned int i;
> > +
> > +	for (i = 0; i < ARRAY_SIZE(clk_names); ++i) {
> > +		clk = clk_get(NULL, clk_names[i].clk);
> > +		if (!IS_ERR(clk)) {
> > +			clk_register_clkdev(clk, clk_names[i].con_id,
> > +					    clk_names[i].dev_id);
> > +			clk_put(clk);
> > +		}
> > +	}
> > +#else
> >  	r8a7779_clock_init();
> >  #endif
> >  	r8a7779_add_standard_devices_dt();
> 
> -- 
> Regards,
> 
> Laurent Pinchart
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-sh" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 

Re: [PATCH v3 07/20] ARM: shmobile: marzen: Reference clocks

[Simon Horman]

On Wed, Feb 26, 2014 at 06:23:15PM +0300, Sergei Shtylyov wrote:
> Hello.
> 
> On 02/26/2014 10:33 AM, Simon Horman wrote:
> 
> >Reference clocks using a "clocks" property in all nodes corresponding to
> >devices that require a clock: that is, the lan0 node.
> 
>    Simon, "lan0" (should be "ethernet" BTW) is the SMC chip, it
> can't use Ether clock.

Thanks, I will drop this patch.

[PATCH v3 07/20] ARM: shmobile: marzen: Reference clocks

[Simon Horman]

On Wed, Feb 26, 2014 at 06:23:15PM +0300, Sergei Shtylyov wrote:
> Hello.
> 
> On 02/26/2014 10:33 AM, Simon Horman wrote:
> 
> >Reference clocks using a "clocks" property in all nodes corresponding to
> >devices that require a clock: that is, the lan0 node.
> 
>    Simon, "lan0" (should be "ethernet" BTW) is the SMC chip, it
> can't use Ether clock.

Thanks, I will drop this patch.

Re: [PATCH v3 01/20] clk: shmobile: r8a7779: Add clocks support

[Simon Horman]

On Wed, Mar 12, 2014 at 11:12:02AM +0100, Laurent Pinchart wrote:
> Hi Simon,
> 
> On Wednesday 12 March 2014 16:55:23 Simon Horman wrote:
> > On Wed, Feb 26, 2014 at 02:02:37PM +0100, Laurent Pinchart wrote:
>  > On Wednesday 26 February 2014 13:53:17 Laurent Pinchart wrote:
> > > > On Wednesday 26 February 2014 16:33:17 Simon Horman wrote:
> > > > > The R8A7779 SoC has several clocks that are too custom to be supported
> > > > > in a generic driver. Those clocks can be divided in two categories:
> > > > > 
> > > > > - Fixed rate clocks with multiplier and divisor set according to boot
> > > > >   mode configuration
> > > > > 
> > > > > - Custom divider clocks with SoC-specific divider values
> > > > > 
> > > > > This driver supports both.
> > > > 
> > > > Looking at the R8A7779 datasheet it looks like we only have fixed rate
> > > > clocks, without any configurable divider clock. Did I miss something ?
> > 
> > Sorry, its a cut-and past error on my part.
> > I will revise the changelog.
> > 
> > > > > Based on work for R-Car Gen2 SoCs by Laurent Pinchart.
> > > > > 
> > > > > Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> > > > > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> > > > > 
> > > > > ---
> > > > > v3
> > > > > * As suggested by Laurent Pinchart
> > > > > 
> > > > >   - Added external clock input
> > > > >   - Use PLLA ratio set bu MD11 and MD12
> > > > >   - Add _div suffixes of fields of struct cpt_clk_config
> > > > >   - Register PLLA as a fixed factor clock
> > > > >   - Use sizeof() instead of sizeof
> > > > >   - Use num_clks instead of CPG_NUM_CLOCKS in
> > > > >   r8a7779_cpg_clocks_init()
> > > > >   
> > > > >   - I kept this as r8a7779 binding rather than moving to a R-Car Gen1
> > > > >     binding which could be shared with other SoCs as I do not believe
> > > > >     that the SoCs is are sufficiently similar.
> > > > 
> > > > I had a look at the M1 datasheet and I still find its CPG very similar
> > > > with the H1 CPG. The PLLA multiplier and divider are different, but if
> > > > you look closely, they're both exactly twice the value compared to H1,
> > > > so there's no difference in practice.
> > > > 
> > > > What differences do you see that would make it impractical to share a
> > > > single driver for both ?
> > 
> > Thanks for pointing that out. Looking over the M1 datasheet again I agree
> > with you that there does seem to be rather a lot of similarities with the
> > H1. And I agree that it is likely that the driver could be shared.
> > 
> > However, I'd like to leave that as future work at this time.
> > 
> > The reason for this is that on the one hand I believe such work sould be
> > done in conjunctin with integrating the driver on the bockw board.
> > And that seems to be non-trivial to me.
> 
> We can always rename the driver later, that's not a big issue, but we can't 
> change compatibility strings. I would thus like to see "renesas,rcar-gen1-cpg-
> clocks" listed in the DT bindings.

I know that we have done such things in the past but these days I feel that
it is a bit contentious as it is a binding for a software abstraction
rather than the hardware. And as far as I know bindings are supposed to
describe the hardware.

[PATCH v3 01/20] clk: shmobile: r8a7779: Add clocks support

[Simon Horman]

On Wed, Mar 12, 2014 at 11:12:02AM +0100, Laurent Pinchart wrote:
> Hi Simon,
> 
> On Wednesday 12 March 2014 16:55:23 Simon Horman wrote:
> > On Wed, Feb 26, 2014 at 02:02:37PM +0100, Laurent Pinchart wrote:
>  > On Wednesday 26 February 2014 13:53:17 Laurent Pinchart wrote:
> > > > On Wednesday 26 February 2014 16:33:17 Simon Horman wrote:
> > > > > The R8A7779 SoC has several clocks that are too custom to be supported
> > > > > in a generic driver. Those clocks can be divided in two categories:
> > > > > 
> > > > > - Fixed rate clocks with multiplier and divisor set according to boot
> > > > >   mode configuration
> > > > > 
> > > > > - Custom divider clocks with SoC-specific divider values
> > > > > 
> > > > > This driver supports both.
> > > > 
> > > > Looking at the R8A7779 datasheet it looks like we only have fixed rate
> > > > clocks, without any configurable divider clock. Did I miss something ?
> > 
> > Sorry, its a cut-and past error on my part.
> > I will revise the changelog.
> > 
> > > > > Based on work for R-Car Gen2 SoCs by Laurent Pinchart.
> > > > > 
> > > > > Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> > > > > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> > > > > 
> > > > > ---
> > > > > v3
> > > > > * As suggested by Laurent Pinchart
> > > > > 
> > > > >   - Added external clock input
> > > > >   - Use PLLA ratio set bu MD11 and MD12
> > > > >   - Add _div suffixes of fields of struct cpt_clk_config
> > > > >   - Register PLLA as a fixed factor clock
> > > > >   - Use sizeof() instead of sizeof
> > > > >   - Use num_clks instead of CPG_NUM_CLOCKS in
> > > > >   r8a7779_cpg_clocks_init()
> > > > >   
> > > > >   - I kept this as r8a7779 binding rather than moving to a R-Car Gen1
> > > > >     binding which could be shared with other SoCs as I do not believe
> > > > >     that the SoCs is are sufficiently similar.
> > > > 
> > > > I had a look at the M1 datasheet and I still find its CPG very similar
> > > > with the H1 CPG. The PLLA multiplier and divider are different, but if
> > > > you look closely, they're both exactly twice the value compared to H1,
> > > > so there's no difference in practice.
> > > > 
> > > > What differences do you see that would make it impractical to share a
> > > > single driver for both ?
> > 
> > Thanks for pointing that out. Looking over the M1 datasheet again I agree
> > with you that there does seem to be rather a lot of similarities with the
> > H1. And I agree that it is likely that the driver could be shared.
> > 
> > However, I'd like to leave that as future work at this time.
> > 
> > The reason for this is that on the one hand I believe such work sould be
> > done in conjunctin with integrating the driver on the bockw board.
> > And that seems to be non-trivial to me.
> 
> We can always rename the driver later, that's not a big issue, but we can't 
> change compatibility strings. I would thus like to see "renesas,rcar-gen1-cpg-
> clocks" listed in the DT bindings.

I know that we have done such things in the past but these days I feel that
it is a bit contentious as it is a binding for a software abstraction
rather than the hardware. And as far as I know bindings are supposed to
describe the hardware.

Re: [PATCH v3 01/20] clk: shmobile: r8a7779: Add clocks support

[Laurent Pinchart]

Hi Simon,

On Thursday 13 March 2014 11:22:47 Simon Horman wrote:
> On Wed, Mar 12, 2014 at 11:12:02AM +0100, Laurent Pinchart wrote:
> > On Wednesday 12 March 2014 16:55:23 Simon Horman wrote:
> > > On Wed, Feb 26, 2014 at 02:02:37PM +0100, Laurent Pinchart wrote:
> >  > On Wednesday 26 February 2014 13:53:17 Laurent Pinchart wrote:
> > > > > On Wednesday 26 February 2014 16:33:17 Simon Horman wrote:
> > > > > > The R8A7779 SoC has several clocks that are too custom to be
> > > > > > supported in a generic driver. Those clocks can be divided in two
> > > > > > categories:
> > > > > > 
> > > > > > - Fixed rate clocks with multiplier and divisor set according to
> > > > > >   boot mode configuration
> > > > > > 
> > > > > > - Custom divider clocks with SoC-specific divider values
> > > > > > 
> > > > > > This driver supports both.
> > > > > 
> > > > > Looking at the R8A7779 datasheet it looks like we only have fixed
> > > > > rate clocks, without any configurable divider clock. Did I miss
> > > > > something ?
> > > 
> > > Sorry, its a cut-and past error on my part.
> > > I will revise the changelog.
> > > 
> > > > > > Based on work for R-Car Gen2 SoCs by Laurent Pinchart.
> > > > > > 
> > > > > > Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> > > > > > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> > > > > > 
> > > > > > ---
> > > > > > v3
> > > > > > * As suggested by Laurent Pinchart
> > > > > > 
> > > > > >   - Added external clock input
> > > > > >   - Use PLLA ratio set bu MD11 and MD12
> > > > > >   - Add _div suffixes of fields of struct cpt_clk_config
> > > > > >   - Register PLLA as a fixed factor clock
> > > > > >   - Use sizeof() instead of sizeof
> > > > > >   - Use num_clks instead of CPG_NUM_CLOCKS in
> > > > > >   r8a7779_cpg_clocks_init()
> > > > > >   
> > > > > >   - I kept this as r8a7779 binding rather than moving to a R-Car
> > > > > >   Gen1 binding which could be shared with other SoCs as I do not
> > > > > >   believe that the SoCs is are sufficiently similar.
> > > > > 
> > > > > I had a look at the M1 datasheet and I still find its CPG very
> > > > > similar with the H1 CPG. The PLLA multiplier and divider are
> > > > > different, but if you look closely, they're both exactly twice the
> > > > > value compared to H1, so there's no difference in practice.
> > > > > 
> > > > > What differences do you see that would make it impractical to share
> > > > > a single driver for both ?
> > > 
> > > Thanks for pointing that out. Looking over the M1 datasheet again I
> > > agree with you that there does seem to be rather a lot of similarities
> > > with the H1. And I agree that it is likely that the driver could be
> > > shared.
> > > 
> > > However, I'd like to leave that as future work at this time.
> > > 
> > > The reason for this is that on the one hand I believe such work sould be
> > > done in conjunctin with integrating the driver on the bockw board.
> > > And that seems to be non-trivial to me.
> > 
> > We can always rename the driver later, that's not a big issue, but we
> > can't change compatibility strings. I would thus like to see
> > "renesas,rcar-gen1-cpg-clocks" listed in the DT bindings.
> 
> I know that we have done such things in the past but these days I feel that
> it is a bit contentious as it is a binding for a software abstraction
> rather than the hardware. And as far as I know bindings are supposed to
> describe the hardware.

Sure, and I consider rcar-gen1-cpf is a hardware description. We have two 
generations of SoCs in the R-Car series so far, the first generation (H1 and 
M1) and the second generation (H2 and M2). The second generation is even 
explictly named as such in the M2 datasheet. SoCs within a generation share 
hardware characteristics, and it makes sense to reflect that in compatible 
strings.

-- 
Regards,

Laurent Pinchart

[PATCH v3 01/20] clk: shmobile: r8a7779: Add clocks support

[Laurent Pinchart]

Hi Simon,

On Thursday 13 March 2014 11:22:47 Simon Horman wrote:
> On Wed, Mar 12, 2014 at 11:12:02AM +0100, Laurent Pinchart wrote:
> > On Wednesday 12 March 2014 16:55:23 Simon Horman wrote:
> > > On Wed, Feb 26, 2014 at 02:02:37PM +0100, Laurent Pinchart wrote:
> >  > On Wednesday 26 February 2014 13:53:17 Laurent Pinchart wrote:
> > > > > On Wednesday 26 February 2014 16:33:17 Simon Horman wrote:
> > > > > > The R8A7779 SoC has several clocks that are too custom to be
> > > > > > supported in a generic driver. Those clocks can be divided in two
> > > > > > categories:
> > > > > > 
> > > > > > - Fixed rate clocks with multiplier and divisor set according to
> > > > > >   boot mode configuration
> > > > > > 
> > > > > > - Custom divider clocks with SoC-specific divider values
> > > > > > 
> > > > > > This driver supports both.
> > > > > 
> > > > > Looking at the R8A7779 datasheet it looks like we only have fixed
> > > > > rate clocks, without any configurable divider clock. Did I miss
> > > > > something ?
> > > 
> > > Sorry, its a cut-and past error on my part.
> > > I will revise the changelog.
> > > 
> > > > > > Based on work for R-Car Gen2 SoCs by Laurent Pinchart.
> > > > > > 
> > > > > > Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> > > > > > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> > > > > > 
> > > > > > ---
> > > > > > v3
> > > > > > * As suggested by Laurent Pinchart
> > > > > > 
> > > > > >   - Added external clock input
> > > > > >   - Use PLLA ratio set bu MD11 and MD12
> > > > > >   - Add _div suffixes of fields of struct cpt_clk_config
> > > > > >   - Register PLLA as a fixed factor clock
> > > > > >   - Use sizeof() instead of sizeof
> > > > > >   - Use num_clks instead of CPG_NUM_CLOCKS in
> > > > > >   r8a7779_cpg_clocks_init()
> > > > > >   
> > > > > >   - I kept this as r8a7779 binding rather than moving to a R-Car
> > > > > >   Gen1 binding which could be shared with other SoCs as I do not
> > > > > >   believe that the SoCs is are sufficiently similar.
> > > > > 
> > > > > I had a look at the M1 datasheet and I still find its CPG very
> > > > > similar with the H1 CPG. The PLLA multiplier and divider are
> > > > > different, but if you look closely, they're both exactly twice the
> > > > > value compared to H1, so there's no difference in practice.
> > > > > 
> > > > > What differences do you see that would make it impractical to share
> > > > > a single driver for both ?
> > > 
> > > Thanks for pointing that out. Looking over the M1 datasheet again I
> > > agree with you that there does seem to be rather a lot of similarities
> > > with the H1. And I agree that it is likely that the driver could be
> > > shared.
> > > 
> > > However, I'd like to leave that as future work at this time.
> > > 
> > > The reason for this is that on the one hand I believe such work sould be
> > > done in conjunctin with integrating the driver on the bockw board.
> > > And that seems to be non-trivial to me.
> > 
> > We can always rename the driver later, that's not a big issue, but we
> > can't change compatibility strings. I would thus like to see
> > "renesas,rcar-gen1-cpg-clocks" listed in the DT bindings.
> 
> I know that we have done such things in the past but these days I feel that
> it is a bit contentious as it is a binding for a software abstraction
> rather than the hardware. And as far as I know bindings are supposed to
> describe the hardware.

Sure, and I consider rcar-gen1-cpf is a hardware description. We have two 
generations of SoCs in the R-Car series so far, the first generation (H1 and 
M1) and the second generation (H2 and M2). The second generation is even 
explictly named as such in the M2 datasheet. SoCs within a generation share 
hardware characteristics, and it makes sense to reflect that in compatible 
strings.

-- 
Regards,

Laurent Pinchart

Re: [PATCH v3 01/20] clk: shmobile: r8a7779: Add clocks support

[Simon Horman]

On Thu, Mar 13, 2014 at 10:07:45AM +0100, Laurent Pinchart wrote:
> Hi Simon,
> 
> On Thursday 13 March 2014 11:22:47 Simon Horman wrote:
> > On Wed, Mar 12, 2014 at 11:12:02AM +0100, Laurent Pinchart wrote:
> > > On Wednesday 12 March 2014 16:55:23 Simon Horman wrote:
> > > > On Wed, Feb 26, 2014 at 02:02:37PM +0100, Laurent Pinchart wrote:
> > >  > On Wednesday 26 February 2014 13:53:17 Laurent Pinchart wrote:
> > > > > > On Wednesday 26 February 2014 16:33:17 Simon Horman wrote:
> > > > > > > The R8A7779 SoC has several clocks that are too custom to be
> > > > > > > supported in a generic driver. Those clocks can be divided in two
> > > > > > > categories:
> > > > > > > 
> > > > > > > - Fixed rate clocks with multiplier and divisor set according to
> > > > > > >   boot mode configuration
> > > > > > > 
> > > > > > > - Custom divider clocks with SoC-specific divider values
> > > > > > > 
> > > > > > > This driver supports both.
> > > > > > 
> > > > > > Looking at the R8A7779 datasheet it looks like we only have fixed
> > > > > > rate clocks, without any configurable divider clock. Did I miss
> > > > > > something ?
> > > > 
> > > > Sorry, its a cut-and past error on my part.
> > > > I will revise the changelog.
> > > > 
> > > > > > > Based on work for R-Car Gen2 SoCs by Laurent Pinchart.
> > > > > > > 
> > > > > > > Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> > > > > > > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> > > > > > > 
> > > > > > > ---
> > > > > > > v3
> > > > > > > * As suggested by Laurent Pinchart
> > > > > > > 
> > > > > > >   - Added external clock input
> > > > > > >   - Use PLLA ratio set bu MD11 and MD12
> > > > > > >   - Add _div suffixes of fields of struct cpt_clk_config
> > > > > > >   - Register PLLA as a fixed factor clock
> > > > > > >   - Use sizeof() instead of sizeof
> > > > > > >   - Use num_clks instead of CPG_NUM_CLOCKS in
> > > > > > >   r8a7779_cpg_clocks_init()
> > > > > > >   
> > > > > > >   - I kept this as r8a7779 binding rather than moving to a R-Car
> > > > > > >   Gen1 binding which could be shared with other SoCs as I do not
> > > > > > >   believe that the SoCs is are sufficiently similar.
> > > > > > 
> > > > > > I had a look at the M1 datasheet and I still find its CPG very
> > > > > > similar with the H1 CPG. The PLLA multiplier and divider are
> > > > > > different, but if you look closely, they're both exactly twice the
> > > > > > value compared to H1, so there's no difference in practice.
> > > > > > 
> > > > > > What differences do you see that would make it impractical to share
> > > > > > a single driver for both ?
> > > > 
> > > > Thanks for pointing that out. Looking over the M1 datasheet again I
> > > > agree with you that there does seem to be rather a lot of similarities
> > > > with the H1. And I agree that it is likely that the driver could be
> > > > shared.
> > > > 
> > > > However, I'd like to leave that as future work at this time.
> > > > 
> > > > The reason for this is that on the one hand I believe such work sould be
> > > > done in conjunctin with integrating the driver on the bockw board.
> > > > And that seems to be non-trivial to me.
> > > 
> > > We can always rename the driver later, that's not a big issue, but we
> > > can't change compatibility strings. I would thus like to see
> > > "renesas,rcar-gen1-cpg-clocks" listed in the DT bindings.
> > 
> > I know that we have done such things in the past but these days I feel that
> > it is a bit contentious as it is a binding for a software abstraction
> > rather than the hardware. And as far as I know bindings are supposed to
> > describe the hardware.
> 
> Sure, and I consider rcar-gen1-cpf is a hardware description. We have two 
> generations of SoCs in the R-Car series so far, the first generation (H1 and 
> M1) and the second generation (H2 and M2). The second generation is even 
> explictly named as such in the M2 datasheet. SoCs within a generation share 
> hardware characteristics, and it makes sense to reflect that in compatible 
> strings.

I think that if it is documented, as it is for R-Car Gen 2, then
this is entirely reasonable and I agree that it describes the hardware.

However, if it is not documented I don't think that we can make assumptions
and thus I don't think it is appropriate for R-Car Gen 1.

[PATCH v3 01/20] clk: shmobile: r8a7779: Add clocks support

[Simon Horman]

On Thu, Mar 13, 2014 at 10:07:45AM +0100, Laurent Pinchart wrote:
> Hi Simon,
> 
> On Thursday 13 March 2014 11:22:47 Simon Horman wrote:
> > On Wed, Mar 12, 2014 at 11:12:02AM +0100, Laurent Pinchart wrote:
> > > On Wednesday 12 March 2014 16:55:23 Simon Horman wrote:
> > > > On Wed, Feb 26, 2014 at 02:02:37PM +0100, Laurent Pinchart wrote:
> > >  > On Wednesday 26 February 2014 13:53:17 Laurent Pinchart wrote:
> > > > > > On Wednesday 26 February 2014 16:33:17 Simon Horman wrote:
> > > > > > > The R8A7779 SoC has several clocks that are too custom to be
> > > > > > > supported in a generic driver. Those clocks can be divided in two
> > > > > > > categories:
> > > > > > > 
> > > > > > > - Fixed rate clocks with multiplier and divisor set according to
> > > > > > >   boot mode configuration
> > > > > > > 
> > > > > > > - Custom divider clocks with SoC-specific divider values
> > > > > > > 
> > > > > > > This driver supports both.
> > > > > > 
> > > > > > Looking at the R8A7779 datasheet it looks like we only have fixed
> > > > > > rate clocks, without any configurable divider clock. Did I miss
> > > > > > something ?
> > > > 
> > > > Sorry, its a cut-and past error on my part.
> > > > I will revise the changelog.
> > > > 
> > > > > > > Based on work for R-Car Gen2 SoCs by Laurent Pinchart.
> > > > > > > 
> > > > > > > Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> > > > > > > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> > > > > > > 
> > > > > > > ---
> > > > > > > v3
> > > > > > > * As suggested by Laurent Pinchart
> > > > > > > 
> > > > > > >   - Added external clock input
> > > > > > >   - Use PLLA ratio set bu MD11 and MD12
> > > > > > >   - Add _div suffixes of fields of struct cpt_clk_config
> > > > > > >   - Register PLLA as a fixed factor clock
> > > > > > >   - Use sizeof() instead of sizeof
> > > > > > >   - Use num_clks instead of CPG_NUM_CLOCKS in
> > > > > > >   r8a7779_cpg_clocks_init()
> > > > > > >   
> > > > > > >   - I kept this as r8a7779 binding rather than moving to a R-Car
> > > > > > >   Gen1 binding which could be shared with other SoCs as I do not
> > > > > > >   believe that the SoCs is are sufficiently similar.
> > > > > > 
> > > > > > I had a look at the M1 datasheet and I still find its CPG very
> > > > > > similar with the H1 CPG. The PLLA multiplier and divider are
> > > > > > different, but if you look closely, they're both exactly twice the
> > > > > > value compared to H1, so there's no difference in practice.
> > > > > > 
> > > > > > What differences do you see that would make it impractical to share
> > > > > > a single driver for both ?
> > > > 
> > > > Thanks for pointing that out. Looking over the M1 datasheet again I
> > > > agree with you that there does seem to be rather a lot of similarities
> > > > with the H1. And I agree that it is likely that the driver could be
> > > > shared.
> > > > 
> > > > However, I'd like to leave that as future work at this time.
> > > > 
> > > > The reason for this is that on the one hand I believe such work sould be
> > > > done in conjunctin with integrating the driver on the bockw board.
> > > > And that seems to be non-trivial to me.
> > > 
> > > We can always rename the driver later, that's not a big issue, but we
> > > can't change compatibility strings. I would thus like to see
> > > "renesas,rcar-gen1-cpg-clocks" listed in the DT bindings.
> > 
> > I know that we have done such things in the past but these days I feel that
> > it is a bit contentious as it is a binding for a software abstraction
> > rather than the hardware. And as far as I know bindings are supposed to
> > describe the hardware.
> 
> Sure, and I consider rcar-gen1-cpf is a hardware description. We have two 
> generations of SoCs in the R-Car series so far, the first generation (H1 and 
> M1) and the second generation (H2 and M2). The second generation is even 
> explictly named as such in the M2 datasheet. SoCs within a generation share 
> hardware characteristics, and it makes sense to reflect that in compatible 
> strings.

I think that if it is documented, as it is for R-Car Gen 2, then
this is entirely reasonable and I agree that it describes the hardware.

However, if it is not documented I don't think that we can make assumptions
and thus I don't think it is appropriate for R-Car Gen 1.