[PATCH 00/15] drm/i915: Fix 830M/ns2501 for real, well almost

[PATCH 00/15] drm/i915: Fix 830M/ns2501 for real, well almost

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Since the 830M dragon popped up again, I figured I'd dig out my old patches
that try to fix it.

I ended up reworking the primary plane code a bit also to eliminate the
DSPCNTR/DSPADDR RMW accesses since those are dangerous on 830M. But I think
the end result is more in line where we want to go anyway with the primary
planes anyway.

This has been tested on my Lifebook S6010 and this is the first time two
displays work reliably on this thing. Additionally we still need the minimum
watermark fix, for now I just used a hack (didn't include it here).
The only thing that doesn't work is suspend to ram. It suspends but won't
wake up, but that happens w/o i915 also so I can't take the blame for that.

I pushed the lot to [1] and the watermark hack is included there as well.

[1] git://gitorious.org/vsyrjala/linux.git alm_fixes4

Ville Syrjälä (15):
  drm/i915: Use named initializers for gmch wm params
  drm/i915: Fix gen2 planes B and C max watermark value
  drm/i915: Don't get hw state from DVO chip unless DVO is enabled
  drm/i915: ns2501 is on DVOB
  drm/i915: Enable DVO between mode_set and dpms hooks
  drm/i915: Don't call DVO mode_set hook on DPMS changes
  drm/i915: Kill useless ns2501_dump_regs
  drm/i915: Rewrite ns2501 driver a bit
  drm/i915: Ignore VBT int_crt_support on 830M
  drm/i915: Fix DVO 2x clock enable on 830M
  Revert "drm/i915: Nuke pipe A quirk on i830M"
  drm/i915: Add pipe B force quirk for 830M
  drm/i915: Eliminate rmw from .update_primary_plane()
  drm/i915: Call .update_primary_plane in
    intel_{enable,disable}_primary_hw_plane()
  drm/i915: Check pixel clock in ns2501 mode_valid hook

 drivers/gpu/drm/i915/dvo_ns2501.c    | 552 +++++++++++++++++++++--------------
 drivers/gpu/drm/i915/i915_drv.h      |   4 +
 drivers/gpu/drm/i915/intel_display.c | 310 ++++++++++----------
 drivers/gpu/drm/i915/intel_dvo.c     |  19 +-
 drivers/gpu/drm/i915/intel_pm.c      | 154 +++++-----
 5 files changed, 580 insertions(+), 459 deletions(-)

-- 
1.8.5.5

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[PATCH 01/15] drm/i915: Use named initializers for gmch wm params

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Using names initializers when filling out the watermark structs
saves you from having go look up the struct definition every
single time.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 130 ++++++++++++++++++++--------------------
 1 file changed, 65 insertions(+), 65 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ee27d74..f83d1ff 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -865,95 +865,95 @@ static int i845_get_fifo_size(struct drm_device *dev, int plane)
 
 /* Pineview has different values for various configs */
 static const struct intel_watermark_params pineview_display_wm = {
-	PINEVIEW_DISPLAY_FIFO,
-	PINEVIEW_MAX_WM,
-	PINEVIEW_DFT_WM,
-	PINEVIEW_GUARD_WM,
-	PINEVIEW_FIFO_LINE_SIZE
+	.fifo_size = PINEVIEW_DISPLAY_FIFO,
+	.max_wm = PINEVIEW_MAX_WM,
+	.default_wm = PINEVIEW_DFT_WM,
+	.guard_size = PINEVIEW_GUARD_WM,
+	.cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 };
 static const struct intel_watermark_params pineview_display_hplloff_wm = {
-	PINEVIEW_DISPLAY_FIFO,
-	PINEVIEW_MAX_WM,
-	PINEVIEW_DFT_HPLLOFF_WM,
-	PINEVIEW_GUARD_WM,
-	PINEVIEW_FIFO_LINE_SIZE
+	.fifo_size = PINEVIEW_DISPLAY_FIFO,
+	.max_wm = PINEVIEW_MAX_WM,
+	.default_wm = PINEVIEW_DFT_HPLLOFF_WM,
+	.guard_size = PINEVIEW_GUARD_WM,
+	.cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 };
 static const struct intel_watermark_params pineview_cursor_wm = {
-	PINEVIEW_CURSOR_FIFO,
-	PINEVIEW_CURSOR_MAX_WM,
-	PINEVIEW_CURSOR_DFT_WM,
-	PINEVIEW_CURSOR_GUARD_WM,
-	PINEVIEW_FIFO_LINE_SIZE,
+	.fifo_size = PINEVIEW_CURSOR_FIFO,
+	.max_wm = PINEVIEW_CURSOR_MAX_WM,
+	.default_wm = PINEVIEW_CURSOR_DFT_WM,
+	.guard_size = PINEVIEW_CURSOR_GUARD_WM,
+	.cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 };
 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
-	PINEVIEW_CURSOR_FIFO,
-	PINEVIEW_CURSOR_MAX_WM,
-	PINEVIEW_CURSOR_DFT_WM,
-	PINEVIEW_CURSOR_GUARD_WM,
-	PINEVIEW_FIFO_LINE_SIZE
+	.fifo_size = PINEVIEW_CURSOR_FIFO,
+	.max_wm = PINEVIEW_CURSOR_MAX_WM,
+	.default_wm = PINEVIEW_CURSOR_DFT_WM,
+	.guard_size = PINEVIEW_CURSOR_GUARD_WM,
+	.cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 };
 static const struct intel_watermark_params g4x_wm_info = {
-	G4X_FIFO_SIZE,
-	G4X_MAX_WM,
-	G4X_MAX_WM,
-	2,
-	G4X_FIFO_LINE_SIZE,
+	.fifo_size = G4X_FIFO_SIZE,
+	.max_wm = G4X_MAX_WM,
+	.default_wm = G4X_MAX_WM,
+	.guard_size = 2,
+	.cacheline_size = G4X_FIFO_LINE_SIZE,
 };
 static const struct intel_watermark_params g4x_cursor_wm_info = {
-	I965_CURSOR_FIFO,
-	I965_CURSOR_MAX_WM,
-	I965_CURSOR_DFT_WM,
-	2,
-	G4X_FIFO_LINE_SIZE,
+	.fifo_size = I965_CURSOR_FIFO,
+	.max_wm = I965_CURSOR_MAX_WM,
+	.default_wm = I965_CURSOR_DFT_WM,
+	.guard_size = 2,
+	.cacheline_size = G4X_FIFO_LINE_SIZE,
 };
 static const struct intel_watermark_params valleyview_wm_info = {
-	VALLEYVIEW_FIFO_SIZE,
-	VALLEYVIEW_MAX_WM,
-	VALLEYVIEW_MAX_WM,
-	2,
-	G4X_FIFO_LINE_SIZE,
+	.fifo_size = VALLEYVIEW_FIFO_SIZE,
+	.max_wm = VALLEYVIEW_MAX_WM,
+	.default_wm = VALLEYVIEW_MAX_WM,
+	.guard_size = 2,
+	.cacheline_size = G4X_FIFO_LINE_SIZE,
 };
 static const struct intel_watermark_params valleyview_cursor_wm_info = {
-	I965_CURSOR_FIFO,
-	VALLEYVIEW_CURSOR_MAX_WM,
-	I965_CURSOR_DFT_WM,
-	2,
-	G4X_FIFO_LINE_SIZE,
+	.fifo_size = I965_CURSOR_FIFO,
+	.max_wm = VALLEYVIEW_CURSOR_MAX_WM,
+	.default_wm = I965_CURSOR_DFT_WM,
+	.guard_size = 2,
+	.cacheline_size = G4X_FIFO_LINE_SIZE,
 };
 static const struct intel_watermark_params i965_cursor_wm_info = {
-	I965_CURSOR_FIFO,
-	I965_CURSOR_MAX_WM,
-	I965_CURSOR_DFT_WM,
-	2,
-	I915_FIFO_LINE_SIZE,
+	.fifo_size = I965_CURSOR_FIFO,
+	.max_wm = I965_CURSOR_MAX_WM,
+	.default_wm = I965_CURSOR_DFT_WM,
+	.guard_size = 2,
+	.cacheline_size = I915_FIFO_LINE_SIZE,
 };
 static const struct intel_watermark_params i945_wm_info = {
-	I945_FIFO_SIZE,
-	I915_MAX_WM,
-	1,
-	2,
-	I915_FIFO_LINE_SIZE
+	.fifo_size = I945_FIFO_SIZE,
+	.max_wm = I915_MAX_WM,
+	.default_wm = 1,
+	.guard_size = 2,
+	.cacheline_size = I915_FIFO_LINE_SIZE,
 };
 static const struct intel_watermark_params i915_wm_info = {
-	I915_FIFO_SIZE,
-	I915_MAX_WM,
-	1,
-	2,
-	I915_FIFO_LINE_SIZE
+	.fifo_size = I915_FIFO_SIZE,
+	.max_wm = I915_MAX_WM,
+	.default_wm = 1,
+	.guard_size = 2,
+	.cacheline_size = I915_FIFO_LINE_SIZE,
 };
 static const struct intel_watermark_params i830_wm_info = {
-	I855GM_FIFO_SIZE,
-	I915_MAX_WM,
-	1,
-	2,
-	I830_FIFO_LINE_SIZE
+	.fifo_size = I855GM_FIFO_SIZE,
+	.max_wm = I915_MAX_WM,
+	.default_wm = 1,
+	.guard_size = 2,
+	.cacheline_size = I830_FIFO_LINE_SIZE,
 };
 static const struct intel_watermark_params i845_wm_info = {
-	I830_FIFO_SIZE,
-	I915_MAX_WM,
-	1,
-	2,
-	I830_FIFO_LINE_SIZE
+	.fifo_size = I830_FIFO_SIZE,
+	.max_wm = I915_MAX_WM,
+	.default_wm = 1,
+	.guard_size = 2,
+	.cacheline_size = I830_FIFO_LINE_SIZE,
 };
 
 /**
-- 
1.8.5.5

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Re: [PATCH 01/15] drm/i915: Use named initializers for gmch wm params

[Chris Wilson]

On Thu, Jun 05, 2014 at 07:15:50PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Using names initializers when filling out the watermark structs
> saves you from having go look up the struct definition every
> single time.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Thank you,
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

Re: [PATCH 01/15] drm/i915: Use named initializers for gmch wm params

[Thomas Richter]

Am 05.06.2014 22:43, schrieb Chris Wilson:
> On Thu, Jun 05, 2014 at 07:15:50PM +0300, ville.syrjala@linux.intel.com wrote:
>> From: Ville Syrjälä<ville.syrjala@linux.intel.com>
>>
>> Using names initializers when filling out the watermark structs
>> saves you from having go look up the struct definition every
>> single time.
>>
>> Signed-off-by: Ville Syrjälä<ville.syrjala@linux.intel.com>
>
> Thank you,
> Reviewed-by: Chris Wilson<chris@chris-wilson.co.uk>

Thanks for the patch and for all the work, unfortunately it does not 
quite work as presented. I applied the patch correctly to 
drm-intel-nightly, and it compiles fine.

However, the following issues exist:

*) If you boot with the kernel parameter vga=792 (i.e. the same console 
resolutions as initiated by KMS) the system just hangs with a black 
screen. Booting aborts, nothing happens.

*) Watermark settings are *still* not correct. *SIGH*, *sigh*

intel_reg_read 0x20d8
0x20D8 : 0x11F0104

This is a watermark level of 4. As I said multiple times, the watermark 
register needs to be *AT LEAST* eight (in numbers, 8) to have a stable 
display. It is stable between 8 and 32.

To reproduce, use a panning display with xrandr:

xrandr --output DVI1 --mode 1024x768 --panning 2048x1536

then scroll, and see the display flicker.

Folks, I really appreciate all your effort, but I would be really happy 
if my comments on the wrong watermarks wouldn't be continuously ignored. 
I submitted patches, twice, thrice... all went into the trash.

Greetings,
	Thomas

Bug reports on 830MG patches (thanks, but more trouble)

[Thomas Richter]

Update on the 830MG Updates:

As Ville already said, resume from "suspend-to-ram" is broken. No 
surprise, old broken bios. However, there is a big difference between 
the kernel with the pipe-A quirk disabled, and the one with pipe-a and 
pipe-b quirks enabled: If resumed without the quirk, the display is 
dead, but you can at least re-initiate it with vbetool post, then 
restart the X server. So at least, the kernel is working.

With the pipe A quirk enabled, something dies immediately when 
attempting to resume from suspend. The machine is completely 
unresponsive, also not reachable over the network. The kernel dies away. 
This is *probably* related to the dying kernel when booting with vga=792 
(or vga=791 or vga=790, all cause the same problem, no working machine.)

----

Thanks for the patch and for all the work, unfortunately it does not 
quite work as presented. I applied the patch correctly to 
drm-intel-nightly, and it compiles fine.

However, the following issues exist:

*) If you boot with the kernel parameter vga=792 (i.e. the same console 
resolutions as initiated by KMS) the system just hangs with a black 
screen. Booting aborts, nothing happens.

*) Watermark settings are *still* not correct. *SIGH*, *sigh*

intel_reg_read 0x20d8
0x20D8 : 0x11F0104

This is a watermark level of 4. As I said multiple times, the watermark 
register needs to be *AT LEAST* eight (in numbers, 8) to have a stable 
display. It is stable between 8 and 32.

To reproduce, use a panning display with xrandr:

xrandr --output DVI1 --mode 1024x768 --panning 2048x1536

then scroll, and see the display flicker.

Folks, I really appreciate all your effort, but I would be really happy 
if my comments on the wrong watermarks wouldn't be continuously ignored. 
I submitted patches, twice, thrice... all went into the trash.

Greetings,
     Thomas

Re: Bug reports on 830MG patches (thanks, but more trouble)

[Ville Syrjälä]

On Thu, Jun 05, 2014 at 11:33:55PM +0200, Thomas Richter wrote:
> Update on the 830MG Updates:
> 
> As Ville already said, resume from "suspend-to-ram" is broken. No 
> surprise, old broken bios. However, there is a big difference between 
> the kernel with the pipe-A quirk disabled, and the one with pipe-a and 
> pipe-b quirks enabled: If resumed without the quirk, the display is 
> dead, but you can at least re-initiate it with vbetool post, then 
> restart the X server. So at least, the kernel is working.
> 
> With the pipe A quirk enabled, something dies immediately when 
> attempting to resume from suspend. The machine is completely 
> unresponsive, also not reachable over the network. The kernel dies away. 

For me resume gets stuck even w/o i915. So something is different
clearly between our machines. Might be some driver, or might the BIOS.
Do you have the latest BIOS on that thing?

> This is *probably* related to the dying kernel when booting with vga=792 
> (or vga=791 or vga=790, all cause the same problem, no working machine.)

I must admit I didn't try the vga= options. I'll give them a go and see
what happens.

> 
> ----
> 
> Thanks for the patch and for all the work, unfortunately it does not 
> quite work as presented. I applied the patch correctly to 
> drm-intel-nightly, and it compiles fine.

You applied all 15 patches, right?

> 
> However, the following issues exist:
> 
> *) If you boot with the kernel parameter vga=792 (i.e. the same console 
> resolutions as initiated by KMS) the system just hangs with a black 
> screen. Booting aborts, nothing happens.
> 
> *) Watermark settings are *still* not correct. *SIGH*, *sigh*
> 
> intel_reg_read 0x20d8
> 0x20D8 : 0x11F0104

I did warn you. If you'd just taken my branch you would have gotten the
hack to avoid that.

> 
> This is a watermark level of 4. As I said multiple times, the watermark 
> register needs to be *AT LEAST* eight (in numbers, 8) to have a stable 
> display. It is stable between 8 and 32.
> 
> To reproduce, use a panning display with xrandr:
> 
> xrandr --output DVI1 --mode 1024x768 --panning 2048x1536
> 
> then scroll, and see the display flicker.
> 
> Folks, I really appreciate all your effort, but I would be really happy 
> if my comments on the wrong watermarks wouldn't be continuously ignored. 
> I submitted patches, twice, thrice... all went into the trash.
> 
> Greetings,
>      Thomas

-- 
Ville Syrjälä
Intel OTC

Re: Bug reports on 830MG patches (thanks, but more trouble)

[Thomas Richter]

Hi Ville, hi others,

>> As Ville already said, resume from "suspend-to-ram" is broken. No
>> surprise, old broken bios. However, there is a big difference between
>> the kernel with the pipe-A quirk disabled, and the one with pipe-a and
>> pipe-b quirks enabled: If resumed without the quirk, the display is
>> dead, but you can at least re-initiate it with vbetool post, then
>> restart the X server. So at least, the kernel is working.
>>
>> With the pipe A quirk enabled, something dies immediately when
>> attempting to resume from suspend. The machine is completely
>> unresponsive, also not reachable over the network. The kernel dies away.
>
> For me resume gets stuck even w/o i915. So something is different
> clearly between our machines. Might be some driver, or might the BIOS.
> Do you have the latest BIOS on that thing?

Yup, I flashed the bios last week with version 1.07, the latest I could 
find on the Fujitsu pages. It was 1.06 before, though I did not observe 
any difference between 1.06 and 1.07 with respect to the broken resume 
operation.

There is a difference between "freeze" and "freeze". Yes, w/o the pipe-A 
quirk, the screen goes black, but you can reach it over the network, and 
you can even type into the console and submit the video restart from 
there. So, it's not frozen, only the display is "off", though it looks 
the same for the untrained eye.

Maybe the bios configuration between yours and mine is different?

>> This is *probably* related to the dying kernel when booting with vga=792
>> (or vga=791 or vga=790, all cause the same problem, no working machine.)
>
> I must admit I didn't try the vga= options. I'll give them a go and see
> what happens.

Please do. I have narrowed it down to the case where text mode vs. 
graphics mode makes a difference. That is, a frame buffer console alone 
is sufficient for the machine to get stuck when loading i915.

>> ----
>>
>> Thanks for the patch and for all the work, unfortunately it does not
>> quite work as presented. I applied the patch correctly to
>> drm-intel-nightly, and it compiles fine.
>
> You applied all 15 patches, right?

Exactly, all 15 of them.

>>
>> However, the following issues exist:
>>
>> *) If you boot with the kernel parameter vga=792 (i.e. the same console
>> resolutions as initiated by KMS) the system just hangs with a black
>> screen. Booting aborts, nothing happens.
>>
>> *) Watermark settings are *still* not correct. *SIGH*, *sigh*
>>
>> intel_reg_read 0x20d8
>> 0x20D8 : 0x11F0104
>
> I did warn you. If you'd just taken my branch you would have gotten the
> hack to avoid that.

Ok, I'll try tonite to clone from your repository instead of 
intel-drm-nightly and report back. But if you have a patch concerning 
the watermark that works and is *accepted* into intel-drm-next, I would 
be thankful indeed. This is really annoying...

(It's not that it is hard to work around the watermark issue....)

So long,
	Thomas

Re: Bug reports on 830MG patches (thanks, but more trouble)

[Ville Syrjälä]

On Fri, Jun 06, 2014 at 07:24:02PM +0200, Thomas Richter wrote:
> Hi Ville, hi others,
> 
> >> As Ville already said, resume from "suspend-to-ram" is broken. No
> >> surprise, old broken bios. However, there is a big difference between
> >> the kernel with the pipe-A quirk disabled, and the one with pipe-a and
> >> pipe-b quirks enabled: If resumed without the quirk, the display is
> >> dead, but you can at least re-initiate it with vbetool post, then
> >> restart the X server. So at least, the kernel is working.
> >>
> >> With the pipe A quirk enabled, something dies immediately when
> >> attempting to resume from suspend. The machine is completely
> >> unresponsive, also not reachable over the network. The kernel dies away.
> >
> > For me resume gets stuck even w/o i915. So something is different
> > clearly between our machines. Might be some driver, or might the BIOS.
> > Do you have the latest BIOS on that thing?
> 
> Yup, I flashed the bios last week with version 1.07, the latest I could 
> find on the Fujitsu pages. It was 1.06 before, though I did not observe 
> any difference between 1.06 and 1.07 with respect to the broken resume 
> operation.

1.07 is what have as well.

> 
> There is a difference between "freeze" and "freeze". Yes, w/o the pipe-A 
> quirk, the screen goes black, but you can reach it over the network, and 
> you can even type into the console and submit the video restart from 
> there. So, it's not frozen, only the display is "off", though it looks 
> the same for the untrained eye.

My eye is well trained, sir.

> 
> Maybe the bios configuration between yours and mine is different?

I tried disabling everything extra from the BIOS. No dice.

> 
> >> This is *probably* related to the dying kernel when booting with vga=792
> >> (or vga=791 or vga=790, all cause the same problem, no working machine.)
> >
> > I must admit I didn't try the vga= options. I'll give them a go and see
> > what happens.
> 
> Please do. I have narrowed it down to the case where text mode vs. 
> graphics mode makes a difference. That is, a frame buffer console alone 
> is sufficient for the machine to get stuck when loading i915.

OK, so I posted a few revised patches, and three new ones. With these my
S6010 can resume from S3 if and only if:
1. pass acpi_sleep=s3_bios to the kernel command line
2. unload i915 before suspending

1. I guess is expected since you also had to use vbetool to post the
GPU. Having the kernel do it is better since then you can't clobber the
state while i915 is already doing stuff.

2. is more strange. I assume there must be some magic difference between
our suspend vs. unload and/or resume vs. init codepaths that cause problems.
Although the fact that you don't need to do it makes it even stranger. I
tried to use the pm_trace facility a bit bit didn't really get anywhere.
So given that this thing is a dinosaur I think I'll now leave it and either
let someone else figure it out or come back to it when I'm really bored.
Otherwise the machine works pretty decently for me now.

I think the reason why killing the pipe A quirk might have made a 
difference for you was the fact that i915 no longer registered the VGA
port and so the DVO port always stayed assigned to pipe A. But if you'd
just applied the "ignore VBT" patch and gotten the VGA port back, things
would have failed again rather nicely especially when trying to use both
pipes.

I pushed the new patches to [1] and I still included the watermark hack,
and there's an additional locking fix you'll want as well.

[1] git://gitorious.org/vsyrjala/linux.git alm_fixes5

So apart from the remaining S3 resume mystery the minimum watermark
problem is still to be solved. I think Chris's idea of converting
the .default_wm parameter to a minimum watermark level is sane. But in
order to do that I think we should do these things:
- s/.default_wm/.min_wm/
- Replace the current .default_wm values with "burst size" (maybe with +1)
  Some of the current .default_wm values make absolutely no sense as a
  minimum value (pnv at least has 0x3f there!)
- Someone should maybe figure out why we use a larger burst size on
  845/865 than on the other platforms

-- 
Ville Syrjälä
Intel OTC

Re: Bug reports on 830MG patches (thanks, but more trouble)

[Thomas Richter]

Am 06.06.2014 22:08, schrieb Ville Syrjälä:

>> Yup, I flashed the bios last week with version 1.07, the latest I could
>> find on the Fujitsu pages. It was 1.06 before, though I did not observe
>> any difference between 1.06 and 1.07 with respect to the broken resume
>> operation.
>
> 1.07 is what have as well.

Ok, great.

>> Maybe the bios configuration between yours and mine is different?
>
> I tried disabling everything extra from the BIOS. No dice.

As said, only with the pipe a quirk removed... I had "plug & play os" 
enabled, and the "security screen on resume" disabled.

> OK, so I posted a few revised patches, and three new ones. With these my
> S6010 can resume from S3 if and only if:
> 1. pass acpi_sleep=s3_bios to the kernel command line
> 2. unload i915 before suspending

This is as good as I had it without the pipe A quirk as well. Unloading 
i915 worked as well: I had to post the GPU, then either reload i915 or 
restart X.

> 1. I guess is expected since you also had to use vbetool to post the
> GPU. Having the kernel do it is better since then you can't clobber the
> state while i915 is already doing stuff.

Yes.

> 2. is more strange. I assume there must be some magic difference between
> our suspend vs. unload and/or resume vs. init codepaths that cause problems.

Likely.

> Although the fact that you don't need to do it makes it even stranger.

Not exactly, see above. Reloading i915 works as well, but otherwise you 
had to stop X, then restart X, then re-set the resolution to ensure that 
everything is configured correctly.

> I tried to use the pm_trace facility a bit bit didn't really get anywhere.
> So given that this thing is a dinosaur I think I'll now leave it and either
> let someone else figure it out or come back to it when I'm really bored.

resume from suspend is not really much an issue. suspend to disk works 
fine, and there is likely a bios problem.

Did you notice that intel_reg_snapshot just dies when you try? Also, if 
you check the bootlogs, some I/O regions seem to overlay. Probably 
resume tries to reload the same I/O addresses intel_reg_snapshot tries 
to save? vbetool vbestate save also hangs the machine...

> Otherwise the machine works pretty decently for me now.

Yes, with the watermark settings in place - from your repository - 
everything is as good as it gets.

Could you please create a patch for intel_calculate_wm() that adjusts 
wm_size, probably depending on GEN2?


> I think the reason why killing the pipe A quirk might have made a
> difference for you was the fact that i915 no longer registered the VGA
> port and so the DVO port always stayed assigned to pipe A. But if you'd
> just applied the "ignore VBT" patch and gotten the VGA port back, things
> would have failed again rather nicely especially when trying to use both
> pipes.
>
> I pushed the new patches to [1] and I still included the watermark hack,
> and there's an additional locking fix you'll want as well.
>
> [1] git://gitorious.org/vsyrjala/linux.git alm_fixes5

That is what I pulled probably two hours ago. It still has the issue 
with dying with vga=792 as boot parameter. When did you submit?


> So apart from the remaining S3 resume mystery the minimum watermark
> problem is still to be solved. I think Chris's idea of converting
> the .default_wm parameter to a minimum watermark level is sane. But in
> order to do that I think we should do these things:
> - s/.default_wm/.min_wm/
> - Replace the current .default_wm values with "burst size" (maybe with +1)
>    Some of the current .default_wm values make absolutely no sense as a
>    minimum value (pnv at least has 0x3f there!)
> - Someone should maybe figure out why we use a larger burst size on
>    845/865 than on the other platforms

I guess I do have a couple of additional intel based machines here if 
that is of help. A 945 based board is here, and some later machines.

Thanks!

Greetings,
	Thomas

Re: Bug reports on 830MG patches (thanks, but more trouble)

[Ville Syrjälä]

On Fri, Jun 06, 2014 at 11:09:53PM +0200, Thomas Richter wrote:
> Am 06.06.2014 22:08, schrieb Ville Syrjälä:
> >> Maybe the bios configuration between yours and mine is different?
> >
> > I tried disabling everything extra from the BIOS. No dice.
> 
> As said, only with the pipe a quirk removed... I had "plug & play os" 
> enabled, and the "security screen on resume" disabled.

Hmm. I don't think I tried the pnp os option. I'll give it a go next
week in case it has some effect.

> 
> > OK, so I posted a few revised patches, and three new ones. With these my
> > S6010 can resume from S3 if and only if:
> > 1. pass acpi_sleep=s3_bios to the kernel command line
> > 2. unload i915 before suspending
> 
> This is as good as I had it without the pipe A quirk as well. Unloading 
> i915 worked as well: I had to post the GPU, then either reload i915 or 
> restart X.

Just restarting X has some risk in case the vbetool POST clobbered some
state that i915 only sets up at init or resume.

> Did you notice that intel_reg_snapshot just dies when you try?

No, in fact never tried that tool.

> Also, if 
> you check the bootlogs, some I/O regions seem to overlay. Probably 
> resume tries to reload the same I/O addresses intel_reg_snapshot tries 
> to save? vbetool vbestate save also hangs the machine...
> 
> > Otherwise the machine works pretty decently for me now.
> 
> Yes, with the watermark settings in place - from your repository - 
> everything is as good as it gets.

Oh, great.

> 
> Could you please create a patch for intel_calculate_wm() that adjusts 
> wm_size, probably depending on GEN2?

Daniel was threatening to resurrect his watermark branch. But I don't
really see a problem with going with a temporary fix in the meantime
maybe even only for 830.

> > I think the reason why killing the pipe A quirk might have made a
> > difference for you was the fact that i915 no longer registered the VGA
> > port and so the DVO port always stayed assigned to pipe A. But if you'd
> > just applied the "ignore VBT" patch and gotten the VGA port back, things
> > would have failed again rather nicely especially when trying to use both
> > pipes.
> >
> > I pushed the new patches to [1] and I still included the watermark hack,
> > and there's an additional locking fix you'll want as well.
> >
> > [1] git://gitorious.org/vsyrjala/linux.git alm_fixes5
> 
> That is what I pulled probably two hours ago. It still has the issue 
> with dying with vga=792 as boot parameter. When did you submit?

I pushed just before sending the email. I think what you have is
alm_fixes4, which indeed did blow up with vga= for me as well.
alm_fixes5 should fare better.

-- 
Ville Syrjälä
Intel OTC

[PATCH] Check for a min level when computing the watermark.

[Thomas Richter]

[-- Attachment #1: Type: text/plain, Size: 635 bytes --]

Dear intel experts,

the attached patch is a minimally invasive modification of the watermark 
computation for the 830GM chipset graphics. It adds a minimum watermark 
level to test against. The minimum value is zero for all other families 
of the intel chipset graphics, thus causing no change there.

What is still strange is that the default watermark level is only used 
if the watermark level computation returns a value below zero, though 
values *below* the default value are acceptable as long as the are above 
or equal to zero. Anyhow, I keep it like this for the time being to 
avoid breaking anything.

Greetings,
	Thomas


[-- Attachment #2: 0001-Added-a-min-watermark-level.patch --]
[-- Type: text/x-patch, Size: 5544 bytes --]

>From 4ff44b36c3ca8ac0255700aaa8999e75efbf9598 Mon Sep 17 00:00:00 2001
From: thor <thor@math.tu-berlin.de>
Date: Sat, 7 Jun 2014 22:23:16 +0200
Subject: [PATCH] Added a min watermark level.

Signed-off-by: thor <thor@math.tu-berlin.de>
---
 drivers/gpu/drm/i915/i915_reg.h  |    1 +
 drivers/gpu/drm/i915/intel_drv.h |    1 +
 drivers/gpu/drm/i915/intel_pm.c  |   16 ++++++++++++++++
 3 files changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 286f05c..442240b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3897,6 +3897,7 @@ enum punit_power_well {
 #define I915_FIFO_SIZE		95
 #define I855GM_FIFO_SIZE	127 /* In cachelines */
 #define I830_FIFO_SIZE		95
+#define I830_MIN_WM		8
 
 #define VALLEYVIEW_MAX_WM	0xff
 #define G4X_MAX_WM		0x3f
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 78d4124..16d2f68 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -458,6 +458,7 @@ struct intel_plane {
 
 struct intel_watermark_params {
 	unsigned long fifo_size;
+	unsigned long min_wm;
 	unsigned long max_wm;
 	unsigned long default_wm;
 	unsigned long guard_size;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f83d1ff..ac8a832 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -866,6 +866,7 @@ static int i845_get_fifo_size(struct drm_device *dev, int plane)
 /* Pineview has different values for various configs */
 static const struct intel_watermark_params pineview_display_wm = {
 	.fifo_size = PINEVIEW_DISPLAY_FIFO,
+	.min_wm = 0,
 	.max_wm = PINEVIEW_MAX_WM,
 	.default_wm = PINEVIEW_DFT_WM,
 	.guard_size = PINEVIEW_GUARD_WM,
@@ -873,6 +874,7 @@ static const struct intel_watermark_params pineview_display_wm = {
 };
 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 	.fifo_size = PINEVIEW_DISPLAY_FIFO,
+	.min_wm = 0,
 	.max_wm = PINEVIEW_MAX_WM,
 	.default_wm = PINEVIEW_DFT_HPLLOFF_WM,
 	.guard_size = PINEVIEW_GUARD_WM,
@@ -880,6 +882,7 @@ static const struct intel_watermark_params pineview_display_hplloff_wm = {
 };
 static const struct intel_watermark_params pineview_cursor_wm = {
 	.fifo_size = PINEVIEW_CURSOR_FIFO,
+	.min_wm = 0,
 	.max_wm = PINEVIEW_CURSOR_MAX_WM,
 	.default_wm = PINEVIEW_CURSOR_DFT_WM,
 	.guard_size = PINEVIEW_CURSOR_GUARD_WM,
@@ -887,6 +890,7 @@ static const struct intel_watermark_params pineview_cursor_wm = {
 };
 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 	.fifo_size = PINEVIEW_CURSOR_FIFO,
+	.min_wm = 0,
 	.max_wm = PINEVIEW_CURSOR_MAX_WM,
 	.default_wm = PINEVIEW_CURSOR_DFT_WM,
 	.guard_size = PINEVIEW_CURSOR_GUARD_WM,
@@ -894,6 +898,7 @@ static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 };
 static const struct intel_watermark_params g4x_wm_info = {
 	.fifo_size = G4X_FIFO_SIZE,
+	.min_wm = 0,
 	.max_wm = G4X_MAX_WM,
 	.default_wm = G4X_MAX_WM,
 	.guard_size = 2,
@@ -901,6 +906,7 @@ static const struct intel_watermark_params g4x_wm_info = {
 };
 static const struct intel_watermark_params g4x_cursor_wm_info = {
 	.fifo_size = I965_CURSOR_FIFO,
+	.min_wm = 0,
 	.max_wm = I965_CURSOR_MAX_WM,
 	.default_wm = I965_CURSOR_DFT_WM,
 	.guard_size = 2,
@@ -908,6 +914,7 @@ static const struct intel_watermark_params g4x_cursor_wm_info = {
 };
 static const struct intel_watermark_params valleyview_wm_info = {
 	.fifo_size = VALLEYVIEW_FIFO_SIZE,
+	.min_wm = 0,
 	.max_wm = VALLEYVIEW_MAX_WM,
 	.default_wm = VALLEYVIEW_MAX_WM,
 	.guard_size = 2,
@@ -915,6 +922,7 @@ static const struct intel_watermark_params valleyview_wm_info = {
 };
 static const struct intel_watermark_params valleyview_cursor_wm_info = {
 	.fifo_size = I965_CURSOR_FIFO,
+	.min_wm = 0,
 	.max_wm = VALLEYVIEW_CURSOR_MAX_WM,
 	.default_wm = I965_CURSOR_DFT_WM,
 	.guard_size = 2,
@@ -922,6 +930,7 @@ static const struct intel_watermark_params valleyview_cursor_wm_info = {
 };
 static const struct intel_watermark_params i965_cursor_wm_info = {
 	.fifo_size = I965_CURSOR_FIFO,
+	.min_wm = 0,
 	.max_wm = I965_CURSOR_MAX_WM,
 	.default_wm = I965_CURSOR_DFT_WM,
 	.guard_size = 2,
@@ -929,6 +938,7 @@ static const struct intel_watermark_params i965_cursor_wm_info = {
 };
 static const struct intel_watermark_params i945_wm_info = {
 	.fifo_size = I945_FIFO_SIZE,
+	.min_wm = 0,
 	.max_wm = I915_MAX_WM,
 	.default_wm = 1,
 	.guard_size = 2,
@@ -936,6 +946,7 @@ static const struct intel_watermark_params i945_wm_info = {
 };
 static const struct intel_watermark_params i915_wm_info = {
 	.fifo_size = I915_FIFO_SIZE,
+	.min_wm = 0,
 	.max_wm = I915_MAX_WM,
 	.default_wm = 1,
 	.guard_size = 2,
@@ -943,6 +954,7 @@ static const struct intel_watermark_params i915_wm_info = {
 };
 static const struct intel_watermark_params i830_wm_info = {
 	.fifo_size = I855GM_FIFO_SIZE,
+	.min_wm = I830_MIN_WM,
 	.max_wm = I915_MAX_WM,
 	.default_wm = 1,
 	.guard_size = 2,
@@ -950,6 +962,7 @@ static const struct intel_watermark_params i830_wm_info = {
 };
 static const struct intel_watermark_params i845_wm_info = {
 	.fifo_size = I830_FIFO_SIZE,
+	.min_wm = I830_MIN_WM,
 	.max_wm = I915_MAX_WM,
 	.default_wm = 1,
 	.guard_size = 2,
@@ -1003,6 +1016,9 @@ static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 		wm_size = wm->max_wm;
 	if (wm_size <= 0)
 		wm_size = wm->default_wm;
+	if (wm_size < (long)wm->min_wm)
+		wm_size = wm->min_wm;
+
 	return wm_size;
 }
 
-- 
1.7.10.4


[-- Attachment #3: Type: text/plain, Size: 159 bytes --]

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Re: [PATCH 01/15] drm/i915: Use named initializers for gmch wm params

[Daniel Vetter]

On Thu, Jun 05, 2014 at 09:43:12PM +0100, Chris Wilson wrote:
> On Thu, Jun 05, 2014 at 07:15:50PM +0300, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Using names initializers when filling out the watermark structs
> > saves you from having go look up the struct definition every
> > single time.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Thank you,
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

My rusty "fix watermarks for gen2/3" wip branch had this too.
Queued for -next, thanks for the patch.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

[PATCH 02/15] drm/i915: Fix gen2 planes B and C max watermark value

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The max watermark value for gen2 planes B and C is 0x1f, instead of
the 0x3f that plane A uses.

Also check against the max even if the pipe is disabled since the
FIFO size exceeds the plane B and C max watermark value.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 24 ++++++++++++++++++++----
 1 file changed, 20 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f83d1ff..03904de 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -941,13 +941,20 @@ static const struct intel_watermark_params i915_wm_info = {
 	.guard_size = 2,
 	.cacheline_size = I915_FIFO_LINE_SIZE,
 };
-static const struct intel_watermark_params i830_wm_info = {
+static const struct intel_watermark_params i830_a_wm_info = {
 	.fifo_size = I855GM_FIFO_SIZE,
 	.max_wm = I915_MAX_WM,
 	.default_wm = 1,
 	.guard_size = 2,
 	.cacheline_size = I830_FIFO_LINE_SIZE,
 };
+static const struct intel_watermark_params i830_bc_wm_info = {
+	.fifo_size = I855GM_FIFO_SIZE,
+	.max_wm = I915_MAX_WM/2,
+	.default_wm = 1,
+	.guard_size = 2,
+	.cacheline_size = I830_FIFO_LINE_SIZE,
+};
 static const struct intel_watermark_params i845_wm_info = {
 	.fifo_size = I830_FIFO_SIZE,
 	.max_wm = I915_MAX_WM,
@@ -1506,7 +1513,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
 	else if (!IS_GEN2(dev))
 		wm_info = &i915_wm_info;
 	else
-		wm_info = &i830_wm_info;
+		wm_info = &i830_a_wm_info;
 
 	fifo_size = dev_priv->display.get_fifo_size(dev, 0);
 	crtc = intel_get_crtc_for_plane(dev, 0);
@@ -1521,8 +1528,14 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
 					       wm_info, fifo_size, cpp,
 					       latency_ns);
 		enabled = crtc;
-	} else
+	} else {
 		planea_wm = fifo_size - wm_info->guard_size;
+		if (planea_wm > (long)wm_info->max_wm)
+			planea_wm = wm_info->max_wm;
+	}
+
+	if (IS_GEN2(dev))
+		wm_info = &i830_bc_wm_info;
 
 	fifo_size = dev_priv->display.get_fifo_size(dev, 1);
 	crtc = intel_get_crtc_for_plane(dev, 1);
@@ -1540,8 +1553,11 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
 			enabled = crtc;
 		else
 			enabled = NULL;
-	} else
+	} else {
 		planeb_wm = fifo_size - wm_info->guard_size;
+		if (planeb_wm > (long)wm_info->max_wm)
+			planeb_wm = wm_info->max_wm;
+	}
 
 	DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
 
-- 
1.8.5.5

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[PATCH 03/15] drm/i915: Don't get hw state from DVO chip unless DVO is enabled

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Certain DVO chips (ns2501 for example) don't like to be accessed unless
the PLL is running. Simply skip the DVO get_hw_state if the DVO port
is disabled.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dvo.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c
index a3631c0..5d7d975 100644
--- a/drivers/gpu/drm/i915/intel_dvo.c
+++ b/drivers/gpu/drm/i915/intel_dvo.c
@@ -112,7 +112,15 @@ static struct intel_dvo *intel_attached_dvo(struct drm_connector *connector)
 
 static bool intel_dvo_connector_get_hw_state(struct intel_connector *connector)
 {
+	struct drm_device *dev = connector->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_dvo *intel_dvo = intel_attached_dvo(&connector->base);
+	u32 tmp;
+
+	tmp = I915_READ(intel_dvo->dev.dvo_reg);
+
+	if (!(tmp & DVO_ENABLE))
+		return false;
 
 	return intel_dvo->dev.dev_ops->get_hw_state(&intel_dvo->dev);
 }
-- 
1.8.5.5

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Re: [PATCH 03/15] drm/i915: Don't get hw state from DVO chip unless DVO is enabled

[Daniel Vetter]

On Thu, Jun 05, 2014 at 07:15:52PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Certain DVO chips (ns2501 for example) don't like to be accessed unless
> the PLL is running. Simply skip the DVO get_hw_state if the DVO port
> is disabled.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Definitely makes sense independent of the other patches. Queued for -next,
thanks for the patch.
-Daniel

> ---
>  drivers/gpu/drm/i915/intel_dvo.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c
> index a3631c0..5d7d975 100644
> --- a/drivers/gpu/drm/i915/intel_dvo.c
> +++ b/drivers/gpu/drm/i915/intel_dvo.c
> @@ -112,7 +112,15 @@ static struct intel_dvo *intel_attached_dvo(struct drm_connector *connector)
>  
>  static bool intel_dvo_connector_get_hw_state(struct intel_connector *connector)
>  {
> +	struct drm_device *dev = connector->base.dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct intel_dvo *intel_dvo = intel_attached_dvo(&connector->base);
> +	u32 tmp;
> +
> +	tmp = I915_READ(intel_dvo->dev.dvo_reg);
> +
> +	if (!(tmp & DVO_ENABLE))
> +		return false;
>  
>  	return intel_dvo->dev.dev_ops->get_hw_state(&intel_dvo->dev);
>  }
> -- 
> 1.8.5.5
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

[PATCH 04/15] drm/i915: ns2501 is on DVOB

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

On Fujitsu-Siememens S6010 the ns2501 chip is hooked up to DVOB instead
of DVOC.

FIXME: Maybe need to dig out the correct DVO port from VBT

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dvo.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c
index 5d7d975..be560bb 100644
--- a/drivers/gpu/drm/i915/intel_dvo.c
+++ b/drivers/gpu/drm/i915/intel_dvo.c
@@ -85,7 +85,7 @@ static const struct intel_dvo_device intel_dvo_devices[] = {
 	{
 	        .type = INTEL_DVO_CHIP_TMDS,
 		.name = "ns2501",
-		.dvo_reg = DVOC,
+		.dvo_reg = DVOB,
 		.slave_addr = NS2501_ADDR,
 		.dev_ops = &ns2501_ops,
        }
-- 
1.8.5.5

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Re: [PATCH 04/15] drm/i915: ns2501 is on DVOB

[Daniel Vetter]

On Thu, Jun 05, 2014 at 07:15:53PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> On Fujitsu-Siememens S6010 the ns2501 chip is hooked up to DVOB instead
> of DVOC.
> 
> FIXME: Maybe need to dig out the correct DVO port from VBT

Well we could have 2 match structs for dvoc and dvob. I guess on Thomas'
X30 it is actually on dvob, otherwise he wouldn't have picked that one ...
-Daniel

> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dvo.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c
> index 5d7d975..be560bb 100644
> --- a/drivers/gpu/drm/i915/intel_dvo.c
> +++ b/drivers/gpu/drm/i915/intel_dvo.c
> @@ -85,7 +85,7 @@ static const struct intel_dvo_device intel_dvo_devices[] = {
>  	{
>  	        .type = INTEL_DVO_CHIP_TMDS,
>  		.name = "ns2501",
> -		.dvo_reg = DVOC,
> +		.dvo_reg = DVOB,
>  		.slave_addr = NS2501_ADDR,
>  		.dev_ops = &ns2501_ops,
>         }
> -- 
> 1.8.5.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 04/15] drm/i915: ns2501 is on DVOB

[Ville Syrjälä]

On Fri, Jun 06, 2014 at 06:57:43PM +0200, Daniel Vetter wrote:
> On Thu, Jun 05, 2014 at 07:15:53PM +0300, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > On Fujitsu-Siememens S6010 the ns2501 chip is hooked up to DVOB instead
> > of DVOC.
> > 
> > FIXME: Maybe need to dig out the correct DVO port from VBT
> 
> Well we could have 2 match structs for dvoc and dvob. I guess on Thomas'
> X30 it is actually on dvob, otherwise he wouldn't have picked that one ...

Sure, but we can't probe the DVO port so we need to use VBT/DMI/something
to figure out which one to pick. In theory VBT should have information.

> -Daniel
> 
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_dvo.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c
> > index 5d7d975..be560bb 100644
> > --- a/drivers/gpu/drm/i915/intel_dvo.c
> > +++ b/drivers/gpu/drm/i915/intel_dvo.c
> > @@ -85,7 +85,7 @@ static const struct intel_dvo_device intel_dvo_devices[] = {
> >  	{
> >  	        .type = INTEL_DVO_CHIP_TMDS,
> >  		.name = "ns2501",
> > -		.dvo_reg = DVOC,
> > +		.dvo_reg = DVOB,
> >  		.slave_addr = NS2501_ADDR,
> >  		.dev_ops = &ns2501_ops,
> >         }
> > -- 
> > 1.8.5.5
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch

-- 
Ville Syrjälä
Intel OTC

[PATCH 05/15] drm/i915: Enable DVO between mode_set and dpms hooks

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

To more closely match the IEGD ns2501 driver behaviour, call the
mode_set hook while the DVO port is still disabled, then enable the DVO
port, and finally call the dpms hook.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dvo.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c
index be560bb..463cd40 100644
--- a/drivers/gpu/drm/i915/intel_dvo.c
+++ b/drivers/gpu/drm/i915/intel_dvo.c
@@ -185,12 +185,13 @@ static void intel_enable_dvo(struct intel_encoder *encoder)
 	u32 dvo_reg = intel_dvo->dev.dvo_reg;
 	u32 temp = I915_READ(dvo_reg);
 
-	I915_WRITE(dvo_reg, temp | DVO_ENABLE);
-	I915_READ(dvo_reg);
 	intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev,
 					 &crtc->config.requested_mode,
 					 &crtc->config.adjusted_mode);
 
+	I915_WRITE(dvo_reg, temp | DVO_ENABLE);
+	I915_READ(dvo_reg);
+
 	intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true);
 }
 
-- 
1.8.5.5

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 06/15] drm/i915: Don't call DVO mode_set hook on DPMS changes

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Calling the mode_set hook on DPMS changes doesn't seem to be necessary
for ns2501. Just drop it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dvo.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c
index 463cd40..ad01c3f 100644
--- a/drivers/gpu/drm/i915/intel_dvo.c
+++ b/drivers/gpu/drm/i915/intel_dvo.c
@@ -227,10 +227,6 @@ static void intel_dvo_dpms(struct drm_connector *connector, int mode)
 
 		intel_crtc_update_dpms(crtc);
 
-		intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev,
-						 &config->requested_mode,
-						 &config->adjusted_mode);
-
 		intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true);
 	} else {
 		intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false);
-- 
1.8.5.5

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 07/15] drm/i915: Kill useless ns2501_dump_regs

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/dvo_ns2501.c | 17 -----------------
 1 file changed, 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/dvo_ns2501.c b/drivers/gpu/drm/i915/dvo_ns2501.c
index 74f2af7..85030d4 100644
--- a/drivers/gpu/drm/i915/dvo_ns2501.c
+++ b/drivers/gpu/drm/i915/dvo_ns2501.c
@@ -479,22 +479,6 @@ static void ns2501_dpms(struct intel_dvo_device *dvo, bool enable)
 	}
 }
 
-static void ns2501_dump_regs(struct intel_dvo_device *dvo)
-{
-	uint8_t val;
-
-	ns2501_readb(dvo, NS2501_FREQ_LO, &val);
-	DRM_DEBUG_KMS("NS2501_FREQ_LO: 0x%02x\n", val);
-	ns2501_readb(dvo, NS2501_FREQ_HI, &val);
-	DRM_DEBUG_KMS("NS2501_FREQ_HI: 0x%02x\n", val);
-	ns2501_readb(dvo, NS2501_REG8, &val);
-	DRM_DEBUG_KMS("NS2501_REG8: 0x%02x\n", val);
-	ns2501_readb(dvo, NS2501_REG9, &val);
-	DRM_DEBUG_KMS("NS2501_REG9: 0x%02x\n", val);
-	ns2501_readb(dvo, NS2501_REGC, &val);
-	DRM_DEBUG_KMS("NS2501_REGC: 0x%02x\n", val);
-}
-
 static void ns2501_destroy(struct intel_dvo_device *dvo)
 {
 	struct ns2501_priv *ns = dvo->dev_priv;
@@ -512,6 +496,5 @@ struct intel_dvo_dev_ops ns2501_ops = {
 	.mode_set = ns2501_mode_set,
 	.dpms = ns2501_dpms,
 	.get_hw_state = ns2501_get_hw_state,
-	.dump_regs = ns2501_dump_regs,
 	.destroy = ns2501_destroy,
 };
-- 
1.8.5.5

_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 08/15] drm/i915: Rewrite ns2501 driver a bit

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Try to use the same programming sequence as used by the IEGD driver.

Also shovel the magic register values into a big static const array.

The register values are actually the based on what the BIOS programs
on the Fujitsu-Siemens Lifebook S6010. IEGD seemed to have hardcoded
register values (which also enabled the scaler for 1024x768 mode).
However those didn't actually work so well on the S6010. Possibly the
pipe timings that got used didn't match the ns2501 configuration.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/dvo_ns2501.c | 529 +++++++++++++++++++++++---------------
 1 file changed, 325 insertions(+), 204 deletions(-)

diff --git a/drivers/gpu/drm/i915/dvo_ns2501.c b/drivers/gpu/drm/i915/dvo_ns2501.c
index 85030d4..b278571 100644
--- a/drivers/gpu/drm/i915/dvo_ns2501.c
+++ b/drivers/gpu/drm/i915/dvo_ns2501.c
@@ -60,16 +60,291 @@
 
 #define NS2501_REGC 0x0c
 
+enum {
+	MODE_640x480,
+	MODE_800x600,
+	MODE_1024x768,
+};
+
+struct ns2501_reg {
+	 uint8_t offset;
+	 uint8_t value;
+};
+
+/*
+ * Magic values based on what the BIOS on
+ * Fujitsu-Siemens Lifebook S6010 programs (1024x768 panel).
+ */
+static const struct ns2501_reg regs_1024x768[][86] = {
+	[MODE_640x480] = {
+		[0] = { .offset = 0x0a, .value = 0x81, },
+		[1] = { .offset = 0x18, .value = 0x07, },
+		[2] = { .offset = 0x19, .value = 0x00, },
+		[3] = { .offset = 0x1a, .value = 0x00, },
+		[4] = { .offset = 0x1b, .value = 0x11, },
+		[5] = { .offset = 0x1c, .value = 0x54, },
+		[6] = { .offset = 0x1d, .value = 0x03, },
+		[7] = { .offset = 0x1e, .value = 0x02, },
+		[8] = { .offset = 0xf3, .value = 0x90, },
+		[9] = { .offset = 0xf9, .value = 0x00, },
+		[10] = { .offset = 0xc1, .value = 0x90, },
+		[11] = { .offset = 0xc2, .value = 0x00, },
+		[12] = { .offset = 0xc3, .value = 0x0f, },
+		[13] = { .offset = 0xc4, .value = 0x03, },
+		[14] = { .offset = 0xc5, .value = 0x16, },
+		[15] = { .offset = 0xc6, .value = 0x00, },
+		[16] = { .offset = 0xc7, .value = 0x02, },
+		[17] = { .offset = 0xc8, .value = 0x02, },
+		[18] = { .offset = 0xf4, .value = 0x00, },
+		[19] = { .offset = 0x80, .value = 0xff, },
+		[20] = { .offset = 0x81, .value = 0x07, },
+		[21] = { .offset = 0x82, .value = 0x3d, },
+		[22] = { .offset = 0x83, .value = 0x05, },
+		[23] = { .offset = 0x94, .value = 0x00, },
+		[24] = { .offset = 0x95, .value = 0x00, },
+		[25] = { .offset = 0x96, .value = 0x05, },
+		[26] = { .offset = 0x97, .value = 0x00, },
+		[27] = { .offset = 0x9a, .value = 0x88, },
+		[28] = { .offset = 0x9b, .value = 0x00, },
+		[29] = { .offset = 0x98, .value = 0x00, },
+		[30] = { .offset = 0x99, .value = 0x00, },
+		[31] = { .offset = 0xf7, .value = 0x88, },
+		[32] = { .offset = 0xf8, .value = 0x0a, },
+		[33] = { .offset = 0x9c, .value = 0x24, },
+		[34] = { .offset = 0x9d, .value = 0x00, },
+		[35] = { .offset = 0x9e, .value = 0x25, },
+		[36] = { .offset = 0x9f, .value = 0x03, },
+		[37] = { .offset = 0xa0, .value = 0x28, },
+		[38] = { .offset = 0xa1, .value = 0x01, },
+		[39] = { .offset = 0xa2, .value = 0x28, },
+		[40] = { .offset = 0xa3, .value = 0x05, },
+		[41] = { .offset = 0xb6, .value = 0x09, },
+		[42] = { .offset = 0xb8, .value = 0x00, },
+		[43] = { .offset = 0xb9, .value = 0xa0, },
+		[44] = { .offset = 0xba, .value = 0x00, },
+		[45] = { .offset = 0xbb, .value = 0x20, },
+		[46] = { .offset = 0x10, .value = 0x00, },
+		[47] = { .offset = 0x11, .value = 0xa0, },
+		[48] = { .offset = 0x12, .value = 0x02, },
+		[49] = { .offset = 0x20, .value = 0x00, },
+		[50] = { .offset = 0x22, .value = 0x00, },
+		[51] = { .offset = 0x23, .value = 0x00, },
+		[52] = { .offset = 0x24, .value = 0x00, },
+		[53] = { .offset = 0x25, .value = 0x00, },
+		[54] = { .offset = 0x8c, .value = 0x10, },
+		[55] = { .offset = 0x8d, .value = 0x02, },
+		[56] = { .offset = 0x8e, .value = 0x10, },
+		[57] = { .offset = 0x8f, .value = 0x00, },
+		[58] = { .offset = 0x90, .value = 0xff, },
+		[59] = { .offset = 0x91, .value = 0x07, },
+		[60] = { .offset = 0x92, .value = 0xa0, },
+		[61] = { .offset = 0x93, .value = 0x02, },
+		[62] = { .offset = 0xa5, .value = 0x00, },
+		[63] = { .offset = 0xa6, .value = 0x00, },
+		[64] = { .offset = 0xa7, .value = 0x00, },
+		[65] = { .offset = 0xa8, .value = 0x00, },
+		[66] = { .offset = 0xa9, .value = 0x04, },
+		[67] = { .offset = 0xaa, .value = 0x70, },
+		[68] = { .offset = 0xab, .value = 0x4f, },
+		[69] = { .offset = 0xac, .value = 0x00, },
+		[70] = { .offset = 0xa4, .value = 0x84, },
+		[71] = { .offset = 0x7e, .value = 0x18, },
+		[72] = { .offset = 0x84, .value = 0x00, },
+		[73] = { .offset = 0x85, .value = 0x00, },
+		[74] = { .offset = 0x86, .value = 0x00, },
+		[75] = { .offset = 0x87, .value = 0x00, },
+		[76] = { .offset = 0x88, .value = 0x00, },
+		[77] = { .offset = 0x89, .value = 0x00, },
+		[78] = { .offset = 0x8a, .value = 0x00, },
+		[79] = { .offset = 0x8b, .value = 0x00, },
+		[80] = { .offset = 0x26, .value = 0x00, },
+		[81] = { .offset = 0x27, .value = 0x00, },
+		[82] = { .offset = 0xad, .value = 0x00, },
+		[83] = { .offset = 0x08, .value = 0x30, }, /* 0x31 */
+		[84] = { .offset = 0x41, .value = 0x00, },
+		[85] = { .offset = 0xc0, .value = 0x05, },
+	},
+	[MODE_800x600] = {
+		[0] = { .offset = 0x0a, .value = 0x81, },
+		[1] = { .offset = 0x18, .value = 0x07, },
+		[2] = { .offset = 0x19, .value = 0x00, },
+		[3] = { .offset = 0x1a, .value = 0x00, },
+		[4] = { .offset = 0x1b, .value = 0x19, },
+		[5] = { .offset = 0x1c, .value = 0x64, },
+		[6] = { .offset = 0x1d, .value = 0x02, },
+		[7] = { .offset = 0x1e, .value = 0x02, },
+		[8] = { .offset = 0xf3, .value = 0x90, },
+		[9] = { .offset = 0xf9, .value = 0x00, },
+		[10] = { .offset = 0xc1, .value = 0xd7, },
+		[11] = { .offset = 0xc2, .value = 0x00, },
+		[12] = { .offset = 0xc3, .value = 0xf8, },
+		[13] = { .offset = 0xc4, .value = 0x03, },
+		[14] = { .offset = 0xc5, .value = 0x1a, },
+		[15] = { .offset = 0xc6, .value = 0x00, },
+		[16] = { .offset = 0xc7, .value = 0x73, },
+		[17] = { .offset = 0xc8, .value = 0x02, },
+		[18] = { .offset = 0xf4, .value = 0x00, },
+		[19] = { .offset = 0x80, .value = 0x27, },
+		[20] = { .offset = 0x81, .value = 0x03, },
+		[21] = { .offset = 0x82, .value = 0x41, },
+		[22] = { .offset = 0x83, .value = 0x05, },
+		[23] = { .offset = 0x94, .value = 0x00, },
+		[24] = { .offset = 0x95, .value = 0x00, },
+		[25] = { .offset = 0x96, .value = 0x05, },
+		[26] = { .offset = 0x97, .value = 0x00, },
+		[27] = { .offset = 0x9a, .value = 0x88, },
+		[28] = { .offset = 0x9b, .value = 0x00, },
+		[29] = { .offset = 0x98, .value = 0x00, },
+		[30] = { .offset = 0x99, .value = 0x00, },
+		[31] = { .offset = 0xf7, .value = 0x88, },
+		[32] = { .offset = 0xf8, .value = 0x06, },
+		[33] = { .offset = 0x9c, .value = 0x23, },
+		[34] = { .offset = 0x9d, .value = 0x00, },
+		[35] = { .offset = 0x9e, .value = 0x25, },
+		[36] = { .offset = 0x9f, .value = 0x03, },
+		[37] = { .offset = 0xa0, .value = 0x28, },
+		[38] = { .offset = 0xa1, .value = 0x01, },
+		[39] = { .offset = 0xa2, .value = 0x28, },
+		[40] = { .offset = 0xa3, .value = 0x05, },
+		[41] = { .offset = 0xb6, .value = 0x09, },
+		[42] = { .offset = 0xb8, .value = 0x30, },
+		[43] = { .offset = 0xb9, .value = 0xc8, },
+		[44] = { .offset = 0xba, .value = 0x00, },
+		[45] = { .offset = 0xbb, .value = 0x20, },
+		[46] = { .offset = 0x10, .value = 0x20, },
+		[47] = { .offset = 0x11, .value = 0xc8, },
+		[48] = { .offset = 0x12, .value = 0x02, },
+		[49] = { .offset = 0x20, .value = 0x00, },
+		[50] = { .offset = 0x22, .value = 0x00, },
+		[51] = { .offset = 0x23, .value = 0x00, },
+		[52] = { .offset = 0x24, .value = 0x00, },
+		[53] = { .offset = 0x25, .value = 0x00, },
+		[54] = { .offset = 0x8c, .value = 0x10, },
+		[55] = { .offset = 0x8d, .value = 0x02, },
+		[56] = { .offset = 0x8e, .value = 0x04, },
+		[57] = { .offset = 0x8f, .value = 0x00, },
+		[58] = { .offset = 0x90, .value = 0xff, },
+		[59] = { .offset = 0x91, .value = 0x07, },
+		[60] = { .offset = 0x92, .value = 0xa0, },
+		[61] = { .offset = 0x93, .value = 0x02, },
+		[62] = { .offset = 0xa5, .value = 0x00, },
+		[63] = { .offset = 0xa6, .value = 0x00, },
+		[64] = { .offset = 0xa7, .value = 0x00, },
+		[65] = { .offset = 0xa8, .value = 0x00, },
+		[66] = { .offset = 0xa9, .value = 0x83, },
+		[67] = { .offset = 0xaa, .value = 0x40, },
+		[68] = { .offset = 0xab, .value = 0x32, },
+		[69] = { .offset = 0xac, .value = 0x00, },
+		[70] = { .offset = 0xa4, .value = 0x80, },
+		[71] = { .offset = 0x7e, .value = 0x18, },
+		[72] = { .offset = 0x84, .value = 0x00, },
+		[73] = { .offset = 0x85, .value = 0x00, },
+		[74] = { .offset = 0x86, .value = 0x00, },
+		[75] = { .offset = 0x87, .value = 0x00, },
+		[76] = { .offset = 0x88, .value = 0x00, },
+		[77] = { .offset = 0x89, .value = 0x00, },
+		[78] = { .offset = 0x8a, .value = 0x00, },
+		[79] = { .offset = 0x8b, .value = 0x00, },
+		[80] = { .offset = 0x26, .value = 0x00, },
+		[81] = { .offset = 0x27, .value = 0x00, },
+		[82] = { .offset = 0xad, .value = 0x00, },
+		[83] = { .offset = 0x08, .value = 0x30, }, /* 0x31 */
+		[84] = { .offset = 0x41, .value = 0x00, },
+		[85] = { .offset = 0xc0, .value = 0x07, },
+	},
+	[MODE_1024x768] = {
+		[0] = { .offset = 0x0a, .value = 0x81, },
+		[1] = { .offset = 0x18, .value = 0x07, },
+		[2] = { .offset = 0x19, .value = 0x00, },
+		[3] = { .offset = 0x1a, .value = 0x00, },
+		[4] = { .offset = 0x1b, .value = 0x11, },
+		[5] = { .offset = 0x1c, .value = 0x54, },
+		[6] = { .offset = 0x1d, .value = 0x03, },
+		[7] = { .offset = 0x1e, .value = 0x02, },
+		[8] = { .offset = 0xf3, .value = 0x90, },
+		[9] = { .offset = 0xf9, .value = 0x00, },
+		[10] = { .offset = 0xc1, .value = 0x90, },
+		[11] = { .offset = 0xc2, .value = 0x00, },
+		[12] = { .offset = 0xc3, .value = 0x0f, },
+		[13] = { .offset = 0xc4, .value = 0x03, },
+		[14] = { .offset = 0xc5, .value = 0x16, },
+		[15] = { .offset = 0xc6, .value = 0x00, },
+		[16] = { .offset = 0xc7, .value = 0x02, },
+		[17] = { .offset = 0xc8, .value = 0x02, },
+		[18] = { .offset = 0xf4, .value = 0x00, },
+		[19] = { .offset = 0x80, .value = 0xff, },
+		[20] = { .offset = 0x81, .value = 0x07, },
+		[21] = { .offset = 0x82, .value = 0x3d, },
+		[22] = { .offset = 0x83, .value = 0x05, },
+		[23] = { .offset = 0x94, .value = 0x00, },
+		[24] = { .offset = 0x95, .value = 0x00, },
+		[25] = { .offset = 0x96, .value = 0x05, },
+		[26] = { .offset = 0x97, .value = 0x00, },
+		[27] = { .offset = 0x9a, .value = 0x88, },
+		[28] = { .offset = 0x9b, .value = 0x00, },
+		[29] = { .offset = 0x98, .value = 0x00, },
+		[30] = { .offset = 0x99, .value = 0x00, },
+		[31] = { .offset = 0xf7, .value = 0x88, },
+		[32] = { .offset = 0xf8, .value = 0x0a, },
+		[33] = { .offset = 0x9c, .value = 0x24, },
+		[34] = { .offset = 0x9d, .value = 0x00, },
+		[35] = { .offset = 0x9e, .value = 0x25, },
+		[36] = { .offset = 0x9f, .value = 0x03, },
+		[37] = { .offset = 0xa0, .value = 0x28, },
+		[38] = { .offset = 0xa1, .value = 0x01, },
+		[39] = { .offset = 0xa2, .value = 0x28, },
+		[40] = { .offset = 0xa3, .value = 0x05, },
+		[41] = { .offset = 0xb6, .value = 0x09, },
+		[42] = { .offset = 0xb8, .value = 0x00, },
+		[43] = { .offset = 0xb9, .value = 0xa0, },
+		[44] = { .offset = 0xba, .value = 0x00, },
+		[45] = { .offset = 0xbb, .value = 0x20, },
+		[46] = { .offset = 0x10, .value = 0x00, },
+		[47] = { .offset = 0x11, .value = 0xa0, },
+		[48] = { .offset = 0x12, .value = 0x02, },
+		[49] = { .offset = 0x20, .value = 0x00, },
+		[50] = { .offset = 0x22, .value = 0x00, },
+		[51] = { .offset = 0x23, .value = 0x00, },
+		[52] = { .offset = 0x24, .value = 0x00, },
+		[53] = { .offset = 0x25, .value = 0x00, },
+		[54] = { .offset = 0x8c, .value = 0x10, },
+		[55] = { .offset = 0x8d, .value = 0x02, },
+		[56] = { .offset = 0x8e, .value = 0x10, },
+		[57] = { .offset = 0x8f, .value = 0x00, },
+		[58] = { .offset = 0x90, .value = 0xff, },
+		[59] = { .offset = 0x91, .value = 0x07, },
+		[60] = { .offset = 0x92, .value = 0xa0, },
+		[61] = { .offset = 0x93, .value = 0x02, },
+		[62] = { .offset = 0xa5, .value = 0x00, },
+		[63] = { .offset = 0xa6, .value = 0x00, },
+		[64] = { .offset = 0xa7, .value = 0x00, },
+		[65] = { .offset = 0xa8, .value = 0x00, },
+		[66] = { .offset = 0xa9, .value = 0x04, },
+		[67] = { .offset = 0xaa, .value = 0x70, },
+		[68] = { .offset = 0xab, .value = 0x4f, },
+		[69] = { .offset = 0xac, .value = 0x00, },
+		[70] = { .offset = 0xa4, .value = 0x84, },
+		[71] = { .offset = 0x7e, .value = 0x18, },
+		[72] = { .offset = 0x84, .value = 0x00, },
+		[73] = { .offset = 0x85, .value = 0x00, },
+		[74] = { .offset = 0x86, .value = 0x00, },
+		[75] = { .offset = 0x87, .value = 0x00, },
+		[76] = { .offset = 0x88, .value = 0x00, },
+		[77] = { .offset = 0x89, .value = 0x00, },
+		[78] = { .offset = 0x8a, .value = 0x00, },
+		[79] = { .offset = 0x8b, .value = 0x00, },
+		[80] = { .offset = 0x26, .value = 0x00, },
+		[81] = { .offset = 0x27, .value = 0x00, },
+		[82] = { .offset = 0xad, .value = 0x00, },
+		[83] = { .offset = 0x08, .value = 0x34, }, /* 0x35 */
+		[84] = { .offset = 0x41, .value = 0x00, },
+		[85] = { .offset = 0xc0, .value = 0x01, },
+	},
+};
+
 struct ns2501_priv {
-	//I2CDevRec d;
 	bool quiet;
-	int reg_8_shadow;
-	int reg_8_set;
-	// Shadow registers for i915
-	int dvoc;
-	int pll_a;
-	int srcdim;
-	int fw_blc;
+	const struct ns2501_reg *regs;
 };
 
 #define NSPTR(d) ((NS2501Ptr)(d->DriverPrivate.ptr))
@@ -205,11 +480,9 @@ static bool ns2501_init(struct intel_dvo_device *dvo,
 		goto out;
 	}
 	ns->quiet = false;
-	ns->reg_8_set = 0;
-	ns->reg_8_shadow =
-	    NS2501_8_PD | NS2501_8_BPAS | NS2501_8_VEN | NS2501_8_HEN;
 
 	DRM_DEBUG_KMS("init ns2501 dvo controller successfully!\n");
+
 	return true;
 
 out:
@@ -255,180 +528,26 @@ static void ns2501_mode_set(struct intel_dvo_device *dvo,
 			    struct drm_display_mode *mode,
 			    struct drm_display_mode *adjusted_mode)
 {
-	bool ok;
-	int retries = 10;
 	struct ns2501_priv *ns = (struct ns2501_priv *)(dvo->dev_priv);
+	int mode_idx, i;
 
 	DRM_DEBUG_KMS
 	    ("set mode (hdisplay=%d,htotal=%d,vdisplay=%d,vtotal=%d).\n",
 	     mode->hdisplay, mode->htotal, mode->vdisplay, mode->vtotal);
 
-	/*
-	 * Where do I find the native resolution for which scaling is not required???
-	 *
-	 * First trigger the DVO on as otherwise the chip does not appear on the i2c
-	 * bus.
-	 */
-	do {
-		ok = true;
-
-		if (mode->hdisplay == 800 && mode->vdisplay == 600) {
-			/* mode 277 */
-			ns->reg_8_shadow &= ~NS2501_8_BPAS;
-			DRM_DEBUG_KMS("switching to 800x600\n");
-
-			/*
-			 * No, I do not know where this data comes from.
-			 * It is just what the video bios left in the DVO, so
-			 * I'm just copying it here over.
-			 * This also means that I cannot support any other modes
-			 * except the ones supported by the bios.
-			 */
-			ok &= ns2501_writeb(dvo, 0x11, 0xc8);	// 0xc7 also works.
-			ok &= ns2501_writeb(dvo, 0x1b, 0x19);
-			ok &= ns2501_writeb(dvo, 0x1c, 0x62);	// VBIOS left 0x64 here, but 0x62 works nicer
-			ok &= ns2501_writeb(dvo, 0x1d, 0x02);
-
-			ok &= ns2501_writeb(dvo, 0x34, 0x03);
-			ok &= ns2501_writeb(dvo, 0x35, 0xff);
-
-			ok &= ns2501_writeb(dvo, 0x80, 0x27);
-			ok &= ns2501_writeb(dvo, 0x81, 0x03);
-			ok &= ns2501_writeb(dvo, 0x82, 0x41);
-			ok &= ns2501_writeb(dvo, 0x83, 0x05);
+	if (mode->hdisplay == 640 && mode->vdisplay == 480)
+		mode_idx = MODE_640x480;
+	else if (mode->hdisplay == 800 && mode->vdisplay == 600)
+		mode_idx = MODE_800x600;
+	else if (mode->hdisplay == 1024 && mode->vdisplay == 768)
+		mode_idx = MODE_1024x768;
+	else
+		return;
 
-			ok &= ns2501_writeb(dvo, 0x8d, 0x02);
-			ok &= ns2501_writeb(dvo, 0x8e, 0x04);
-			ok &= ns2501_writeb(dvo, 0x8f, 0x00);
+	ns->regs = regs_1024x768[mode_idx];
 
-			ok &= ns2501_writeb(dvo, 0x90, 0xfe);	/* vertical. VBIOS left 0xff here, but 0xfe works better */
-			ok &= ns2501_writeb(dvo, 0x91, 0x07);
-			ok &= ns2501_writeb(dvo, 0x94, 0x00);
-			ok &= ns2501_writeb(dvo, 0x95, 0x00);
-
-			ok &= ns2501_writeb(dvo, 0x96, 0x00);
-
-			ok &= ns2501_writeb(dvo, 0x99, 0x00);
-			ok &= ns2501_writeb(dvo, 0x9a, 0x88);
-
-			ok &= ns2501_writeb(dvo, 0x9c, 0x23);	/* Looks like first and last line of the image. */
-			ok &= ns2501_writeb(dvo, 0x9d, 0x00);
-			ok &= ns2501_writeb(dvo, 0x9e, 0x25);
-			ok &= ns2501_writeb(dvo, 0x9f, 0x03);
-
-			ok &= ns2501_writeb(dvo, 0xa4, 0x80);
-
-			ok &= ns2501_writeb(dvo, 0xb6, 0x00);
-
-			ok &= ns2501_writeb(dvo, 0xb9, 0xc8);	/* horizontal? */
-			ok &= ns2501_writeb(dvo, 0xba, 0x00);	/* horizontal? */
-
-			ok &= ns2501_writeb(dvo, 0xc0, 0x05);	/* horizontal? */
-			ok &= ns2501_writeb(dvo, 0xc1, 0xd7);
-
-			ok &= ns2501_writeb(dvo, 0xc2, 0x00);
-			ok &= ns2501_writeb(dvo, 0xc3, 0xf8);
-
-			ok &= ns2501_writeb(dvo, 0xc4, 0x03);
-			ok &= ns2501_writeb(dvo, 0xc5, 0x1a);
-
-			ok &= ns2501_writeb(dvo, 0xc6, 0x00);
-			ok &= ns2501_writeb(dvo, 0xc7, 0x73);
-			ok &= ns2501_writeb(dvo, 0xc8, 0x02);
-
-		} else if (mode->hdisplay == 640 && mode->vdisplay == 480) {
-			/* mode 274 */
-			DRM_DEBUG_KMS("switching to 640x480\n");
-			/*
-			 * No, I do not know where this data comes from.
-			 * It is just what the video bios left in the DVO, so
-			 * I'm just copying it here over.
-			 * This also means that I cannot support any other modes
-			 * except the ones supported by the bios.
-			 */
-			ns->reg_8_shadow &= ~NS2501_8_BPAS;
-
-			ok &= ns2501_writeb(dvo, 0x11, 0xa0);
-			ok &= ns2501_writeb(dvo, 0x1b, 0x11);
-			ok &= ns2501_writeb(dvo, 0x1c, 0x54);
-			ok &= ns2501_writeb(dvo, 0x1d, 0x03);
-
-			ok &= ns2501_writeb(dvo, 0x34, 0x03);
-			ok &= ns2501_writeb(dvo, 0x35, 0xff);
-
-			ok &= ns2501_writeb(dvo, 0x80, 0xff);
-			ok &= ns2501_writeb(dvo, 0x81, 0x07);
-			ok &= ns2501_writeb(dvo, 0x82, 0x3d);
-			ok &= ns2501_writeb(dvo, 0x83, 0x05);
-
-			ok &= ns2501_writeb(dvo, 0x8d, 0x02);
-			ok &= ns2501_writeb(dvo, 0x8e, 0x10);
-			ok &= ns2501_writeb(dvo, 0x8f, 0x00);
-
-			ok &= ns2501_writeb(dvo, 0x90, 0xff);	/* vertical */
-			ok &= ns2501_writeb(dvo, 0x91, 0x07);
-			ok &= ns2501_writeb(dvo, 0x94, 0x00);
-			ok &= ns2501_writeb(dvo, 0x95, 0x00);
-
-			ok &= ns2501_writeb(dvo, 0x96, 0x05);
-
-			ok &= ns2501_writeb(dvo, 0x99, 0x00);
-			ok &= ns2501_writeb(dvo, 0x9a, 0x88);
-
-			ok &= ns2501_writeb(dvo, 0x9c, 0x24);
-			ok &= ns2501_writeb(dvo, 0x9d, 0x00);
-			ok &= ns2501_writeb(dvo, 0x9e, 0x25);
-			ok &= ns2501_writeb(dvo, 0x9f, 0x03);
-
-			ok &= ns2501_writeb(dvo, 0xa4, 0x84);
-
-			ok &= ns2501_writeb(dvo, 0xb6, 0x09);
-
-			ok &= ns2501_writeb(dvo, 0xb9, 0xa0);	/* horizontal? */
-			ok &= ns2501_writeb(dvo, 0xba, 0x00);	/* horizontal? */
-
-			ok &= ns2501_writeb(dvo, 0xc0, 0x05);	/* horizontal? */
-			ok &= ns2501_writeb(dvo, 0xc1, 0x90);
-
-			ok &= ns2501_writeb(dvo, 0xc2, 0x00);
-			ok &= ns2501_writeb(dvo, 0xc3, 0x0f);
-
-			ok &= ns2501_writeb(dvo, 0xc4, 0x03);
-			ok &= ns2501_writeb(dvo, 0xc5, 0x16);
-
-			ok &= ns2501_writeb(dvo, 0xc6, 0x00);
-			ok &= ns2501_writeb(dvo, 0xc7, 0x02);
-			ok &= ns2501_writeb(dvo, 0xc8, 0x02);
-
-		} else if (mode->hdisplay == 1024 && mode->vdisplay == 768) {
-			/* mode 280 */
-			DRM_DEBUG_KMS("switching to 1024x768\n");
-			/*
-			 * This might or might not work, actually. I'm silently
-			 * assuming here that the native panel resolution is
-			 * 1024x768. If not, then this leaves the scaler disabled
-			 * generating a picture that is likely not the expected.
-			 *
-			 * Problem is that I do not know where to take the panel
-			 * dimensions from.
-			 *
-			 * Enable the bypass, scaling not required.
-			 *
-			 * The scaler registers are irrelevant here....
-			 *
-			 */
-			ns->reg_8_shadow |= NS2501_8_BPAS;
-			ok &= ns2501_writeb(dvo, 0x37, 0x44);
-		} else {
-			/*
-			 * Data not known. Bummer!
-			 * Hopefully, the code should not go here
-			 * as mode_OK delivered no other modes.
-			 */
-			ns->reg_8_shadow |= NS2501_8_BPAS;
-		}
-		ok &= ns2501_writeb(dvo, NS2501_REG8, ns->reg_8_shadow);
-	} while (!ok && retries--);
+	for (i = 0; i < 84; i++)
+		ns2501_writeb(dvo, ns->regs[i].offset, ns->regs[i].value);
 }
 
 /* set the NS2501 power state */
@@ -439,43 +558,45 @@ static bool ns2501_get_hw_state(struct intel_dvo_device *dvo)
 	if (!ns2501_readb(dvo, NS2501_REG8, &ch))
 		return false;
 
-	if (ch & NS2501_8_PD)
-		return true;
-	else
-		return false;
+	return ch & NS2501_8_PD;
 }
 
 /* set the NS2501 power state */
 static void ns2501_dpms(struct intel_dvo_device *dvo, bool enable)
 {
-	bool ok;
-	int retries = 10;
 	struct ns2501_priv *ns = (struct ns2501_priv *)(dvo->dev_priv);
-	unsigned char ch;
 
 	DRM_DEBUG_KMS("Trying set the dpms of the DVO to %i\n", enable);
 
-	ch = ns->reg_8_shadow;
+	if (enable) {
+		if (WARN_ON(ns->regs[83].offset != 0x08 ||
+			    ns->regs[84].offset != 0x41 ||
+			    ns->regs[85].offset != 0xc0))
+			return;
 
-	if (enable)
-		ch |= NS2501_8_PD;
-	else
-		ch &= ~NS2501_8_PD;
-
-	if (ns->reg_8_set == 0 || ns->reg_8_shadow != ch) {
-		ns->reg_8_set = 1;
-		ns->reg_8_shadow = ch;
-
-		do {
-			ok = true;
-			ok &= ns2501_writeb(dvo, NS2501_REG8, ch);
-			ok &=
-			    ns2501_writeb(dvo, 0x34,
-					  enable ? 0x03 : 0x00);
-			ok &=
-			    ns2501_writeb(dvo, 0x35,
-					  enable ? 0xff : 0x00);
-		} while (!ok && retries--);
+		ns2501_writeb(dvo, 0xc0, ns->regs[85].value | 0x08);
+
+		ns2501_writeb(dvo, 0x41, ns->regs[84].value);
+
+		ns2501_writeb(dvo, 0x34, 0x01);
+		msleep(15);
+
+		ns2501_writeb(dvo, 0x08, 0x35);
+		if (!(ns->regs[83].value & NS2501_8_BPAS))
+			ns2501_writeb(dvo, 0x08, 0x31);
+		msleep(200);
+
+		ns2501_writeb(dvo, 0x34, 0x03);
+
+		ns2501_writeb(dvo, 0xc0, ns->regs[85].value);
+	} else {
+		ns2501_writeb(dvo, 0x34, 0x01);
+		msleep(200);
+
+		ns2501_writeb(dvo, 0x08, 0x34);
+		msleep(15);
+
+		ns2501_writeb(dvo, 0x34, 0x00);
 	}
 }
 
-- 
1.8.5.5

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[PATCH 09/15] drm/i915: Ignore VBT int_crt_support on 830M

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

My Fujitsu-Siemens Lifebook S6010 definitely has a VGA connector, but
the VBT says different. Ignore the VBT for 830M since it seems such
old machines would generally have a VGA connector.

This is a regression caused by:
 commit 9c2a03c2a194c086949f25d332937ac8dc4d9f7e
 Author: Jesse Barnes <jbarnes@virtuousgeek.org>
 Date:   Fri Apr 4 16:12:07 2014 -0700

    drm/i915: use VBT to determine whether to enumerate the VGA port

While at it refactor the code a bit to be more pleasing to the eye.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b5cbb28..3d51ceb 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11368,6 +11368,21 @@ const char *intel_output_name(int output)
 	return names[output];
 }
 
+static bool intel_crt_support(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	/* no hardware support whatsoever */
+	if (IS_ULT(dev) || IS_CHERRYVIEW(dev))
+		return false;
+
+	/* Fujitsu-Siemens Lifebook S6010 VBT lies */
+	if (IS_I830(dev))
+		return true;
+
+	return dev_priv->vbt.int_crt_support;
+}
+
 static void intel_setup_outputs(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -11376,7 +11391,7 @@ static void intel_setup_outputs(struct drm_device *dev)
 
 	intel_lvds_init(dev);
 
-	if (!IS_ULT(dev) && !IS_CHERRYVIEW(dev) && dev_priv->vbt.int_crt_support)
+	if (intel_crt_support(dev))
 		intel_crt_init(dev);
 
 	if (HAS_DDI(dev)) {
-- 
1.8.5.5

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Re: [PATCH 09/15] drm/i915: Ignore VBT int_crt_support on 830M

[Daniel Vetter]

On Thu, Jun 05, 2014 at 07:15:58PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> My Fujitsu-Siemens Lifebook S6010 definitely has a VGA connector, but
> the VBT says different. Ignore the VBT for 830M since it seems such
> old machines would generally have a VGA connector.
> 
> This is a regression caused by:
>  commit 9c2a03c2a194c086949f25d332937ac8dc4d9f7e
>  Author: Jesse Barnes <jbarnes@virtuousgeek.org>
>  Date:   Fri Apr 4 16:12:07 2014 -0700
> 
>     drm/i915: use VBT to determine whether to enumerate the VGA port
> 
> While at it refactor the code a bit to be more pleasing to the eye.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Well I think now's the time to move those checks into intel_crt_init. We
don't care at all whether we have a vga port, and imo that way it's
cleaner. eDP/mipi dsi and similar checks are also done in the _init
functions.
-Daniel

> ---
>  drivers/gpu/drm/i915/intel_display.c | 17 ++++++++++++++++-
>  1 file changed, 16 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index b5cbb28..3d51ceb 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -11368,6 +11368,21 @@ const char *intel_output_name(int output)
>  	return names[output];
>  }
>  
> +static bool intel_crt_support(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +
> +	/* no hardware support whatsoever */
> +	if (IS_ULT(dev) || IS_CHERRYVIEW(dev))
> +		return false;
> +
> +	/* Fujitsu-Siemens Lifebook S6010 VBT lies */
> +	if (IS_I830(dev))
> +		return true;
> +
> +	return dev_priv->vbt.int_crt_support;
> +}
> +
>  static void intel_setup_outputs(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -11376,7 +11391,7 @@ static void intel_setup_outputs(struct drm_device *dev)
>  
>  	intel_lvds_init(dev);
>  
> -	if (!IS_ULT(dev) && !IS_CHERRYVIEW(dev) && dev_priv->vbt.int_crt_support)
> +	if (intel_crt_support(dev))
>  		intel_crt_init(dev);
>  
>  	if (HAS_DDI(dev)) {
> -- 
> 1.8.5.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

[PATCH v2 09/15] drm/i915: Ignore VBT int_crt_support on 830M

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

My Fujitsu-Siemens Lifebook S6010 definitely has a VGA connector, but
the VBT says different. Ignore the VBT for 830M since it seems such
old machines would generally have a VGA connector.

This is a regression caused by:
 commit 9c2a03c2a194c086949f25d332937ac8dc4d9f7e
 Author: Jesse Barnes <jbarnes@virtuousgeek.org>
 Date:   Fri Apr 4 16:12:07 2014 -0700

    drm/i915: use VBT to determine whether to enumerate the VGA port

While at it refactor the code a bit to be more pleasing to the eye.

v2: Move the check into intel_crt_init() (Daniel)

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_crt.c     | 22 ++++++++++++++++++++--
 drivers/gpu/drm/i915/intel_display.c |  3 +--
 2 files changed, 21 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 5a045d3..5104e9f 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -801,6 +801,25 @@ static const struct dmi_system_id intel_no_crt[] = {
 	{ }
 };
 
+static bool has_crt_support(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	/* no hardware support whatsoever */
+	if (IS_ULT(dev) || IS_CHERRYVIEW(dev))
+		return false;
+
+	/* Skip machines without VGA that falsely report hotplug events */
+	if (dmi_check_system(intel_no_crt))
+		return false;
+
+	/* Fujitsu-Siemens Lifebook S6010 VBT lies */
+	if (IS_I830(dev))
+		return true;
+
+	return dev_priv->vbt.int_crt_support;
+}
+
 void intel_crt_init(struct drm_device *dev)
 {
 	struct drm_connector *connector;
@@ -808,8 +827,7 @@ void intel_crt_init(struct drm_device *dev)
 	struct intel_connector *intel_connector;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
-	/* Skip machines without VGA that falsely report hotplug events */
-	if (dmi_check_system(intel_no_crt))
+	if (!has_crt_support(dev))
 		return;
 
 	crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b5cbb28..1060caa 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11376,8 +11376,7 @@ static void intel_setup_outputs(struct drm_device *dev)
 
 	intel_lvds_init(dev);
 
-	if (!IS_ULT(dev) && !IS_CHERRYVIEW(dev) && dev_priv->vbt.int_crt_support)
-		intel_crt_init(dev);
+	intel_crt_init(dev);
 
 	if (HAS_DDI(dev)) {
 		int found;
-- 
1.8.5.5

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v2 09/15] drm/i915: Ignore VBT int_crt_support on 830M

[Daniel Vetter]

On Fri, Jun 06, 2014 at 10:44:12PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> My Fujitsu-Siemens Lifebook S6010 definitely has a VGA connector, but
> the VBT says different. Ignore the VBT for 830M since it seems such
> old machines would generally have a VGA connector.
> 
> This is a regression caused by:
>  commit 9c2a03c2a194c086949f25d332937ac8dc4d9f7e
>  Author: Jesse Barnes <jbarnes@virtuousgeek.org>
>  Date:   Fri Apr 4 16:12:07 2014 -0700
> 
>     drm/i915: use VBT to determine whether to enumerate the VGA port
> 
> While at it refactor the code a bit to be more pleasing to the eye.
> 
> v2: Move the check into intel_crt_init() (Daniel)
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>

We'll probably get more of these ...
-Daniel

> ---
>  drivers/gpu/drm/i915/intel_crt.c     | 22 ++++++++++++++++++++--
>  drivers/gpu/drm/i915/intel_display.c |  3 +--
>  2 files changed, 21 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
> index 5a045d3..5104e9f 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -801,6 +801,25 @@ static const struct dmi_system_id intel_no_crt[] = {
>  	{ }
>  };
>  
> +static bool has_crt_support(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +
> +	/* no hardware support whatsoever */
> +	if (IS_ULT(dev) || IS_CHERRYVIEW(dev))
> +		return false;
> +
> +	/* Skip machines without VGA that falsely report hotplug events */
> +	if (dmi_check_system(intel_no_crt))
> +		return false;
> +
> +	/* Fujitsu-Siemens Lifebook S6010 VBT lies */
> +	if (IS_I830(dev))
> +		return true;
> +
> +	return dev_priv->vbt.int_crt_support;
> +}
> +
>  void intel_crt_init(struct drm_device *dev)
>  {
>  	struct drm_connector *connector;
> @@ -808,8 +827,7 @@ void intel_crt_init(struct drm_device *dev)
>  	struct intel_connector *intel_connector;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  
> -	/* Skip machines without VGA that falsely report hotplug events */
> -	if (dmi_check_system(intel_no_crt))
> +	if (!has_crt_support(dev))
>  		return;
>  
>  	crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index b5cbb28..1060caa 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -11376,8 +11376,7 @@ static void intel_setup_outputs(struct drm_device *dev)
>  
>  	intel_lvds_init(dev);
>  
> -	if (!IS_ULT(dev) && !IS_CHERRYVIEW(dev) && dev_priv->vbt.int_crt_support)
> -		intel_crt_init(dev);
> +	intel_crt_init(dev);
>  
>  	if (HAS_DDI(dev)) {
>  		int found;
> -- 
> 1.8.5.5
> 

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

[Patch] Add minimum watermark level for I830

[Thomas Richter]

[-- Attachment #1: Type: text/plain, Size: 661 bytes --]

Dear Daniel, dear intel experts,

please find a minimally-invasive patch to add a minimum watermark level 
to the current watermark logic. This fixes the flickering and video 
overlay crashes on 830M(G) chipsets. Note that this patch does not alter 
the watermark algorithm on any other family of the intel chipsets.

Greetings,
	Thomas

PS: What I do not understand about the current logic is that there is a 
"default watermark" level if the computed watermark is below zero, 
though computed watermarks can well drop below this default. The 
appended patch still allows that to be backwards compatible, though this 
construction sounds pretty weird to me.



[-- Attachment #2: 0001-Added-a-min-watermark-level.patch --]
[-- Type: text/x-patch, Size: 5544 bytes --]

>From 4ff44b36c3ca8ac0255700aaa8999e75efbf9598 Mon Sep 17 00:00:00 2001
From: thor <thor@math.tu-berlin.de>
Date: Sat, 7 Jun 2014 22:23:16 +0200
Subject: [PATCH] Added a min watermark level.

Signed-off-by: thor <thor@math.tu-berlin.de>
---
 drivers/gpu/drm/i915/i915_reg.h  |    1 +
 drivers/gpu/drm/i915/intel_drv.h |    1 +
 drivers/gpu/drm/i915/intel_pm.c  |   16 ++++++++++++++++
 3 files changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 286f05c..442240b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3897,6 +3897,7 @@ enum punit_power_well {
 #define I915_FIFO_SIZE		95
 #define I855GM_FIFO_SIZE	127 /* In cachelines */
 #define I830_FIFO_SIZE		95
+#define I830_MIN_WM		8
 
 #define VALLEYVIEW_MAX_WM	0xff
 #define G4X_MAX_WM		0x3f
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 78d4124..16d2f68 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -458,6 +458,7 @@ struct intel_plane {
 
 struct intel_watermark_params {
 	unsigned long fifo_size;
+	unsigned long min_wm;
 	unsigned long max_wm;
 	unsigned long default_wm;
 	unsigned long guard_size;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f83d1ff..ac8a832 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -866,6 +866,7 @@ static int i845_get_fifo_size(struct drm_device *dev, int plane)
 /* Pineview has different values for various configs */
 static const struct intel_watermark_params pineview_display_wm = {
 	.fifo_size = PINEVIEW_DISPLAY_FIFO,
+	.min_wm = 0,
 	.max_wm = PINEVIEW_MAX_WM,
 	.default_wm = PINEVIEW_DFT_WM,
 	.guard_size = PINEVIEW_GUARD_WM,
@@ -873,6 +874,7 @@ static const struct intel_watermark_params pineview_display_wm = {
 };
 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 	.fifo_size = PINEVIEW_DISPLAY_FIFO,
+	.min_wm = 0,
 	.max_wm = PINEVIEW_MAX_WM,
 	.default_wm = PINEVIEW_DFT_HPLLOFF_WM,
 	.guard_size = PINEVIEW_GUARD_WM,
@@ -880,6 +882,7 @@ static const struct intel_watermark_params pineview_display_hplloff_wm = {
 };
 static const struct intel_watermark_params pineview_cursor_wm = {
 	.fifo_size = PINEVIEW_CURSOR_FIFO,
+	.min_wm = 0,
 	.max_wm = PINEVIEW_CURSOR_MAX_WM,
 	.default_wm = PINEVIEW_CURSOR_DFT_WM,
 	.guard_size = PINEVIEW_CURSOR_GUARD_WM,
@@ -887,6 +890,7 @@ static const struct intel_watermark_params pineview_cursor_wm = {
 };
 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 	.fifo_size = PINEVIEW_CURSOR_FIFO,
+	.min_wm = 0,
 	.max_wm = PINEVIEW_CURSOR_MAX_WM,
 	.default_wm = PINEVIEW_CURSOR_DFT_WM,
 	.guard_size = PINEVIEW_CURSOR_GUARD_WM,
@@ -894,6 +898,7 @@ static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 };
 static const struct intel_watermark_params g4x_wm_info = {
 	.fifo_size = G4X_FIFO_SIZE,
+	.min_wm = 0,
 	.max_wm = G4X_MAX_WM,
 	.default_wm = G4X_MAX_WM,
 	.guard_size = 2,
@@ -901,6 +906,7 @@ static const struct intel_watermark_params g4x_wm_info = {
 };
 static const struct intel_watermark_params g4x_cursor_wm_info = {
 	.fifo_size = I965_CURSOR_FIFO,
+	.min_wm = 0,
 	.max_wm = I965_CURSOR_MAX_WM,
 	.default_wm = I965_CURSOR_DFT_WM,
 	.guard_size = 2,
@@ -908,6 +914,7 @@ static const struct intel_watermark_params g4x_cursor_wm_info = {
 };
 static const struct intel_watermark_params valleyview_wm_info = {
 	.fifo_size = VALLEYVIEW_FIFO_SIZE,
+	.min_wm = 0,
 	.max_wm = VALLEYVIEW_MAX_WM,
 	.default_wm = VALLEYVIEW_MAX_WM,
 	.guard_size = 2,
@@ -915,6 +922,7 @@ static const struct intel_watermark_params valleyview_wm_info = {
 };
 static const struct intel_watermark_params valleyview_cursor_wm_info = {
 	.fifo_size = I965_CURSOR_FIFO,
+	.min_wm = 0,
 	.max_wm = VALLEYVIEW_CURSOR_MAX_WM,
 	.default_wm = I965_CURSOR_DFT_WM,
 	.guard_size = 2,
@@ -922,6 +930,7 @@ static const struct intel_watermark_params valleyview_cursor_wm_info = {
 };
 static const struct intel_watermark_params i965_cursor_wm_info = {
 	.fifo_size = I965_CURSOR_FIFO,
+	.min_wm = 0,
 	.max_wm = I965_CURSOR_MAX_WM,
 	.default_wm = I965_CURSOR_DFT_WM,
 	.guard_size = 2,
@@ -929,6 +938,7 @@ static const struct intel_watermark_params i965_cursor_wm_info = {
 };
 static const struct intel_watermark_params i945_wm_info = {
 	.fifo_size = I945_FIFO_SIZE,
+	.min_wm = 0,
 	.max_wm = I915_MAX_WM,
 	.default_wm = 1,
 	.guard_size = 2,
@@ -936,6 +946,7 @@ static const struct intel_watermark_params i945_wm_info = {
 };
 static const struct intel_watermark_params i915_wm_info = {
 	.fifo_size = I915_FIFO_SIZE,
+	.min_wm = 0,
 	.max_wm = I915_MAX_WM,
 	.default_wm = 1,
 	.guard_size = 2,
@@ -943,6 +954,7 @@ static const struct intel_watermark_params i915_wm_info = {
 };
 static const struct intel_watermark_params i830_wm_info = {
 	.fifo_size = I855GM_FIFO_SIZE,
+	.min_wm = I830_MIN_WM,
 	.max_wm = I915_MAX_WM,
 	.default_wm = 1,
 	.guard_size = 2,
@@ -950,6 +962,7 @@ static const struct intel_watermark_params i830_wm_info = {
 };
 static const struct intel_watermark_params i845_wm_info = {
 	.fifo_size = I830_FIFO_SIZE,
+	.min_wm = I830_MIN_WM,
 	.max_wm = I915_MAX_WM,
 	.default_wm = 1,
 	.guard_size = 2,
@@ -1003,6 +1016,9 @@ static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 		wm_size = wm->max_wm;
 	if (wm_size <= 0)
 		wm_size = wm->default_wm;
+	if (wm_size < (long)wm->min_wm)
+		wm_size = wm->min_wm;
+
 	return wm_size;
 }
 
-- 
1.7.10.4


[-- Attachment #3: Type: text/plain, Size: 159 bytes --]

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Re: [PATCH v2 09/15] drm/i915: Ignore VBT int_crt_support on 830M

[Bob Paauwe]

On Fri, 6 Jun 2014 22:44:12 +0300
<ville.syrjala@linux.intel.com> wrote:

> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> My Fujitsu-Siemens Lifebook S6010 definitely has a VGA connector, but
> the VBT says different. Ignore the VBT for 830M since it seems such
> old machines would generally have a VGA connector.
> 
> This is a regression caused by:
>  commit 9c2a03c2a194c086949f25d332937ac8dc4d9f7e
>  Author: Jesse Barnes <jbarnes@virtuousgeek.org>
>  Date:   Fri Apr 4 16:12:07 2014 -0700
> 
>     drm/i915: use VBT to determine whether to enumerate the VGA port
> 
> While at it refactor the code a bit to be more pleasing to the eye.
> 
> v2: Move the check into intel_crt_init() (Daniel)
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_crt.c     | 22 ++++++++++++++++++++--
>  drivers/gpu/drm/i915/intel_display.c |  3 +--
>  2 files changed, 21 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
> index 5a045d3..5104e9f 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -801,6 +801,25 @@ static const struct dmi_system_id intel_no_crt[] = {
>  	{ }
>  };
>  
> +static bool has_crt_support(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +
> +	/* no hardware support whatsoever */
> +	if (IS_ULT(dev) || IS_CHERRYVIEW(dev))
> +		return false;
> +
> +	/* Skip machines without VGA that falsely report hotplug events */
> +	if (dmi_check_system(intel_no_crt))
> +		return false;
> +
> +	/* Fujitsu-Siemens Lifebook S6010 VBT lies */
> +	if (IS_I830(dev))
> +		return true;

My old D945GNT board with a 945G and really old BIOS also has a VBT
that lies about this.

> +
> +	return dev_priv->vbt.int_crt_support;
> +}
> +
>  void intel_crt_init(struct drm_device *dev)
>  {
>  	struct drm_connector *connector;
> @@ -808,8 +827,7 @@ void intel_crt_init(struct drm_device *dev)
>  	struct intel_connector *intel_connector;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  
> -	/* Skip machines without VGA that falsely report hotplug events */
> -	if (dmi_check_system(intel_no_crt))
> +	if (!has_crt_support(dev))
>  		return;
>  
>  	crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index b5cbb28..1060caa 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -11376,8 +11376,7 @@ static void intel_setup_outputs(struct drm_device *dev)
>  
>  	intel_lvds_init(dev);
>  
> -	if (!IS_ULT(dev) && !IS_CHERRYVIEW(dev) && dev_priv->vbt.int_crt_support)
> -		intel_crt_init(dev);
> +	intel_crt_init(dev);
>  
>  	if (HAS_DDI(dev)) {
>  		int found;

Re: [PATCH v2 09/15] drm/i915: Ignore VBT int_crt_support on 830M

[Daniel Vetter]

On Fri, Jun 6, 2014 at 11:15 PM, Bob Paauwe <bob.j.paauwe@intel.com> wrote:
>> +     /* Fujitsu-Siemens Lifebook S6010 VBT lies */
>> +     if (IS_I830(dev))
>> +             return true;
>
> My old D945GNT board with a 945G and really old BIOS also has a VBT
> that lies about this.

I guess someone needs to dig out vbt docs then and figure out what
we've missed. Could be that the vga option is fairly new.

Jesse/Ben can you please look into that?
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH v2 09/15] drm/i915: Ignore VBT int_crt_support on 830M

[Jesse Barnes]

On Sat, 7 Jun 2014 00:23:08 +0200
Daniel Vetter <daniel@ffwll.ch> wrote:

> On Fri, Jun 6, 2014 at 11:15 PM, Bob Paauwe <bob.j.paauwe@intel.com> wrote:
> >> +     /* Fujitsu-Siemens Lifebook S6010 VBT lies */
> >> +     if (IS_I830(dev))
> >> +             return true;
> >
> > My old D945GNT board with a 945G and really old BIOS also has a VBT
> > that lies about this.
> 
> I guess someone needs to dig out vbt docs then and figure out what
> we've missed. Could be that the vga option is fairly new.
> 
> Jesse/Ben can you please look into that?

Yeah the meaning has changed over time, I'm trying to get the info from
ancient times.

-- 
Jesse Barnes, Intel Open Source Technology Center

Re: [PATCH v2 09/15] drm/i915: Ignore VBT int_crt_support on 830M

[Thomas Richter]

Am 07.06.2014 00:23, schrieb Daniel Vetter:
> On Fri, Jun 6, 2014 at 11:15 PM, Bob Paauwe<bob.j.paauwe@intel.com>  wrote:
>>> +     /* Fujitsu-Siemens Lifebook S6010 VBT lies */
>>> +     if (IS_I830(dev))
>>> +             return true;
>> My old D945GNT board with a 945G and really old BIOS also has a VBT
>> that lies about this.
> I guess someone needs to dig out vbt docs then and figure out what
> we've missed. Could be that the vga option is fairly new.

Positive feedback on this one: WIth this patch, I can finally set VGA 
and internal display (DVI) to independent resolutions.

Thanks!

Greetings,
     Thomas

Re: [PATCH v2 09/15] drm/i915: Ignore VBT int_crt_support on 830M

[Jani Nikula]

On Fri, 06 Jun 2014, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> My Fujitsu-Siemens Lifebook S6010 definitely has a VGA connector, but
> the VBT says different. Ignore the VBT for 830M since it seems such
> old machines would generally have a VGA connector.
>
> This is a regression caused by:
>  commit 9c2a03c2a194c086949f25d332937ac8dc4d9f7e
>  Author: Jesse Barnes <jbarnes@virtuousgeek.org>
>  Date:   Fri Apr 4 16:12:07 2014 -0700
>
>     drm/i915: use VBT to determine whether to enumerate the VGA port
>
> While at it refactor the code a bit to be more pleasing to the eye.

Going through some old patches I spotted this one. It no longer applies,
and the crt presence check has been changes. Do those changes fix the
issue here as well?

Jani.


>
> v2: Move the check into intel_crt_init() (Daniel)
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_crt.c     | 22 ++++++++++++++++++++--
>  drivers/gpu/drm/i915/intel_display.c |  3 +--
>  2 files changed, 21 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
> index 5a045d3..5104e9f 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -801,6 +801,25 @@ static const struct dmi_system_id intel_no_crt[] = {
>  	{ }
>  };
>  
> +static bool has_crt_support(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +
> +	/* no hardware support whatsoever */
> +	if (IS_ULT(dev) || IS_CHERRYVIEW(dev))
> +		return false;
> +
> +	/* Skip machines without VGA that falsely report hotplug events */
> +	if (dmi_check_system(intel_no_crt))
> +		return false;
> +
> +	/* Fujitsu-Siemens Lifebook S6010 VBT lies */
> +	if (IS_I830(dev))
> +		return true;
> +
> +	return dev_priv->vbt.int_crt_support;
> +}
> +
>  void intel_crt_init(struct drm_device *dev)
>  {
>  	struct drm_connector *connector;
> @@ -808,8 +827,7 @@ void intel_crt_init(struct drm_device *dev)
>  	struct intel_connector *intel_connector;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  
> -	/* Skip machines without VGA that falsely report hotplug events */
> -	if (dmi_check_system(intel_no_crt))
> +	if (!has_crt_support(dev))
>  		return;
>  
>  	crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index b5cbb28..1060caa 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -11376,8 +11376,7 @@ static void intel_setup_outputs(struct drm_device *dev)
>  
>  	intel_lvds_init(dev);
>  
> -	if (!IS_ULT(dev) && !IS_CHERRYVIEW(dev) && dev_priv->vbt.int_crt_support)
> -		intel_crt_init(dev);
> +	intel_crt_init(dev);
>  
>  	if (HAS_DDI(dev)) {
>  		int found;
> -- 
> 1.8.5.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
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Re: [PATCH v2 09/15] drm/i915: Ignore VBT int_crt_support on 830M

[Ville Syrjälä]

On Fri, Oct 24, 2014 at 04:23:22PM +0300, Jani Nikula wrote:
> On Fri, 06 Jun 2014, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > My Fujitsu-Siemens Lifebook S6010 definitely has a VGA connector, but
> > the VBT says different. Ignore the VBT for 830M since it seems such
> > old machines would generally have a VGA connector.
> >
> > This is a regression caused by:
> >  commit 9c2a03c2a194c086949f25d332937ac8dc4d9f7e
> >  Author: Jesse Barnes <jbarnes@virtuousgeek.org>
> >  Date:   Fri Apr 4 16:12:07 2014 -0700
> >
> >     drm/i915: use VBT to determine whether to enumerate the VGA port
> >
> > While at it refactor the code a bit to be more pleasing to the eye.
> 
> Going through some old patches I spotted this one. It no longer applies,
> and the crt presence check has been changes. Do those changes fix the
> issue here as well?

This was fixed in:

commit 84b4e042c4707bd1bf05094a51111403d680dc39
Author: Jesse Barnes <jbarnes@virtuousgeek.org>
Date:   Wed Jun 25 08:24:29 2014 -0700

    drm/i915: only apply crt_present check on VLV

> 
> Jani.
> 
> 
> >
> > v2: Move the check into intel_crt_init() (Daniel)
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_crt.c     | 22 ++++++++++++++++++++--
> >  drivers/gpu/drm/i915/intel_display.c |  3 +--
> >  2 files changed, 21 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
> > index 5a045d3..5104e9f 100644
> > --- a/drivers/gpu/drm/i915/intel_crt.c
> > +++ b/drivers/gpu/drm/i915/intel_crt.c
> > @@ -801,6 +801,25 @@ static const struct dmi_system_id intel_no_crt[] = {
> >  	{ }
> >  };
> >  
> > +static bool has_crt_support(struct drm_device *dev)
> > +{
> > +	struct drm_i915_private *dev_priv = dev->dev_private;
> > +
> > +	/* no hardware support whatsoever */
> > +	if (IS_ULT(dev) || IS_CHERRYVIEW(dev))
> > +		return false;
> > +
> > +	/* Skip machines without VGA that falsely report hotplug events */
> > +	if (dmi_check_system(intel_no_crt))
> > +		return false;
> > +
> > +	/* Fujitsu-Siemens Lifebook S6010 VBT lies */
> > +	if (IS_I830(dev))
> > +		return true;
> > +
> > +	return dev_priv->vbt.int_crt_support;
> > +}
> > +
> >  void intel_crt_init(struct drm_device *dev)
> >  {
> >  	struct drm_connector *connector;
> > @@ -808,8 +827,7 @@ void intel_crt_init(struct drm_device *dev)
> >  	struct intel_connector *intel_connector;
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> >  
> > -	/* Skip machines without VGA that falsely report hotplug events */
> > -	if (dmi_check_system(intel_no_crt))
> > +	if (!has_crt_support(dev))
> >  		return;
> >  
> >  	crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index b5cbb28..1060caa 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -11376,8 +11376,7 @@ static void intel_setup_outputs(struct drm_device *dev)
> >  
> >  	intel_lvds_init(dev);
> >  
> > -	if (!IS_ULT(dev) && !IS_CHERRYVIEW(dev) && dev_priv->vbt.int_crt_support)
> > -		intel_crt_init(dev);
> > +	intel_crt_init(dev);
> >  
> >  	if (HAS_DDI(dev)) {
> >  		int found;
> > -- 
> > 1.8.5.5
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Jani Nikula, Intel Open Source Technology Center

-- 
Ville Syrjälä
Intel OTC

[PATCH 10/15] drm/i915: Fix DVO 2x clock enable on 830M

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The spec says:
"For the correct operation of the muxed DVO pins (GDEVSELB/ I2Cdata,
GIRDBY/I2CClk) and (GFRAMEB/DVI_Data, GTRDYB/DVI_Clk): Bit 31
(DPLL VCO Enable) and Bit 30 (2X Clock Enable) must be set to “1” in
both the DPLL A Control Register (06014h-06017h) and DPLL B Control
Register (06018h-0601Bh)."

The pipe A and B force quirks take care of DPLL_VCO_ENABLE, so we
just need a bit of special care to handle DPLL_DVO_2X_MODE.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h      |  3 +++
 drivers/gpu/drm/i915/intel_display.c | 47 +++++++++++++++++++++++++++++++++---
 2 files changed, 46 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8631fb3..559f098 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1537,6 +1537,9 @@ struct drm_i915_private {
 
 	struct i915_runtime_pm pm;
 
+	/* used to control DVO 2x clock enable on 830M */
+	uint8_t dvo_pipes;
+
 	/* Old dri1 support infrastructure, beware the dragons ya fools entering
 	 * here! */
 	struct i915_dri1_state dri1;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3d51ceb..af944be 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1635,6 +1635,7 @@ static void i9xx_enable_pll(struct intel_crtc *crtc)
 {
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
+	enum pipe pipe = crtc->pipe;
 	int reg = DPLL(crtc->pipe);
 	u32 dpll = crtc->config.dpll_hw_state.dpll;
 
@@ -1647,7 +1648,16 @@ static void i9xx_enable_pll(struct intel_crtc *crtc)
 	if (IS_MOBILE(dev) && !IS_I830(dev))
 		assert_panel_unlocked(dev_priv, crtc->pipe);
 
-	I915_WRITE(reg, dpll);
+	/* enable DVO 2x clock on both PLLs if necessary */
+	if (IS_I830(dev)) {
+		if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
+			dev_priv->dvo_pipes |= 1 << pipe;
+
+		if (dev_priv->dvo_pipes) {
+			dpll |= DPLL_DVO_2X_MODE;
+			I915_WRITE(DPLL(!pipe), I915_READ(DPLL(!pipe)) | DPLL_DVO_2X_MODE);
+		}
+	}
 
 	/* Wait for the clocks to stabilize. */
 	POSTING_READ(reg);
@@ -1686,8 +1696,23 @@ static void i9xx_enable_pll(struct intel_crtc *crtc)
  *
  * Note!  This is for pre-ILK only.
  */
-static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
+static void i9xx_disable_pll(struct intel_crtc *crtc)
 {
+	struct drm_device *dev = crtc->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	enum pipe pipe = crtc->pipe;
+
+	/* disable DVO 2x clock on both PLLs if necessary */
+	if (IS_I830(dev)) {
+		if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
+			dev_priv->dvo_pipes &= ~(1 << pipe);
+
+		if (!dev_priv->dvo_pipes) {
+			I915_WRITE(DPLL(pipe), I915_READ(DPLL(pipe)) & ~DPLL_DVO_2X_MODE);
+			I915_WRITE(DPLL(!pipe), I915_READ(DPLL(!pipe)) & ~DPLL_DVO_2X_MODE);
+		}
+	}
+
 	/* Don't disable pipe A or pipe A PLLs if needed */
 	if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
 		return;
@@ -4820,7 +4845,7 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
 		else if (IS_VALLEYVIEW(dev))
 			vlv_disable_pll(dev_priv, pipe);
 		else
-			i9xx_disable_pll(dev_priv, pipe);
+			i9xx_disable_pll(intel_crtc);
 	}
 
 	if (!IS_GEN2(dev))
@@ -5781,7 +5806,7 @@ static void i8xx_update_pll(struct intel_crtc *crtc,
 			dpll |= PLL_P2_DIVIDE_BY_4;
 	}
 
-	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
+	if (!IS_I830(dev) && intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
 		dpll |= DPLL_DVO_2X_MODE;
 
 	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
@@ -6283,6 +6308,9 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
 	}
 	pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
 	if (!IS_VALLEYVIEW(dev)) {
+		if (IS_I830(dev))
+			pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
+
 		pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
 		pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
 	} else {
@@ -12443,6 +12471,17 @@ void intel_modeset_setup_hw_state(struct drm_device *dev,
 		}
 	}
 
+	/* update dvo_pipes */
+	if (IS_I830(dev)) {
+		dev_priv->dvo_pipes = 0;
+
+		for_each_intel_crtc(dev, crtc) {
+			if (crtc->active &&
+			    intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
+				dev_priv->dvo_pipes |= 1 << crtc->pipe;
+		}
+	}
+
 	/* HW state is read out, now we need to sanitize this mess. */
 	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
 			    base.head) {
-- 
1.8.5.5

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[PATCH 11/15] Revert "drm/i915: Nuke pipe A quirk on i830M"

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

This reverts commit ac6696d3236bd61503f89a1a99680fd7894d5d53.
---
 drivers/gpu/drm/i915/intel_display.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index af944be..3b6eccd 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11934,6 +11934,9 @@ static struct intel_quirk intel_quirks[] = {
 	/* ThinkPad T60 needs pipe A force quirk (bug #16494) */
 	{ 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
 
+	/* 830 needs to leave pipe A & dpll A up */
+	{ 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
+
 	/* Lenovo U160 cannot use SSC on LVDS */
 	{ 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
 
-- 
1.8.5.5

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[PATCH 12/15] drm/i915: Add pipe B force quirk for 830M

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

830M has problems when some of the pipes are disabled. Namely if a
plane, DVO port etc. is currently assigned to a disabled pipe, it
can't moved to the other pipe until the current pipe is also enabled.
To keep things simple just leave both pipes running all the time.

Ideally I think should turn the pipes off if neither is active, and
when either becomes active we enable both. But that would reuquire
proper atomic modeset support, and probably a bit of extra care in
the order things get enabled.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h      |  1 +
 drivers/gpu/drm/i915/intel_display.c | 41 ++++++++++++++++++++++++------------
 2 files changed, 29 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 559f098..10e9f68 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -655,6 +655,7 @@ enum intel_sbi_destination {
 #define QUIRK_PIPEA_FORCE (1<<0)
 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
+#define QUIRK_PIPEB_FORCE (1<<3)
 
 struct intel_fbdev;
 struct intel_fbc_work;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3b6eccd..4f02464 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1236,8 +1236,9 @@ void assert_pipe(struct drm_i915_private *dev_priv,
 	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 								      pipe);
 
-	/* if we need the pipe A quirk it must be always on */
-	if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
+	/* if we need the pipe quirk it must be always on */
+	if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
+	    (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
 		state = true;
 
 	if (!intel_display_power_enabled(dev_priv,
@@ -1713,8 +1714,9 @@ static void i9xx_disable_pll(struct intel_crtc *crtc)
 		}
 	}
 
-	/* Don't disable pipe A or pipe A PLLs if needed */
-	if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
+	/* Don't disable pipe or pipe PLLs if needed */
+	if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
+	    (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
 		return;
 
 	/* Make sure the pipe isn't still relying on us */
@@ -2078,8 +2080,8 @@ static void intel_enable_pipe(struct intel_crtc *crtc)
 	reg = PIPECONF(cpu_transcoder);
 	val = I915_READ(reg);
 	if (val & PIPECONF_ENABLE) {
-		WARN_ON(!(pipe == PIPE_A &&
-			  dev_priv->quirks & QUIRK_PIPEA_FORCE));
+		WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
+			  (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
 		return;
 	}
 
@@ -2115,8 +2117,9 @@ static void intel_disable_pipe(struct drm_i915_private *dev_priv,
 	assert_cursor_disabled(dev_priv, pipe);
 	assert_sprites_disabled(dev_priv, pipe);
 
-	/* Don't disable pipe A or pipe A PLLs if needed */
-	if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
+	/* Don't disable pipe or pipe PLLs if needed */
+	if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
+	    (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
 		return;
 
 	reg = PIPECONF(cpu_transcoder);
@@ -5957,9 +5960,9 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
 
 	pipeconf = 0;
 
-	if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
-	    I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
-		pipeconf |= PIPECONF_ENABLE;
+	if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
+	    (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
+		pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
 
 	if (intel_crtc->config.double_wide)
 		pipeconf |= PIPECONF_DOUBLE_WIDE;
@@ -10232,8 +10235,9 @@ check_crtc_state(struct drm_device *dev)
 		active = dev_priv->display.get_pipe_config(crtc,
 							   &pipe_config);
 
-		/* hw state is inconsistent with the pipe A quirk */
-		if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
+		/* hw state is inconsistent with the pipe quirk */
+		if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
+		    (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
 			active = crtc->active;
 
 		list_for_each_entry(encoder, &dev->mode_config.encoder_list,
@@ -11868,6 +11872,14 @@ static void quirk_pipea_force(struct drm_device *dev)
 	DRM_INFO("applying pipe a force quirk\n");
 }
 
+static void quirk_pipeb_force(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	dev_priv->quirks |= QUIRK_PIPEB_FORCE;
+	DRM_INFO("applying pipe b force quirk\n");
+}
+
 /*
  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
  */
@@ -11937,6 +11949,9 @@ static struct intel_quirk intel_quirks[] = {
 	/* 830 needs to leave pipe A & dpll A up */
 	{ 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
 
+	/* 830 needs to leave pipe B & dpll B up */
+	{ 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
+
 	/* Lenovo U160 cannot use SSC on LVDS */
 	{ 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
 
-- 
1.8.5.5

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[PATCH 13/15] drm/i915: Eliminate rmw from .update_primary_plane()

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Move the entire DSPCNTR register setup into the .update_primary_plane()
functions. That's where it belongs anyway and it'll also help 830M which
has the extra problem that plane registers reads will return the value
latched at the last vblank, not the value that was last written.

Also move DSPPOS and DSPSIZE setup there.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 110 +++++++++++------------------------
 1 file changed, 34 insertions(+), 76 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 4f02464..74bbab9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2431,20 +2431,31 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	struct intel_framebuffer *intel_fb;
-	struct drm_i915_gem_object *obj;
+	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
+	struct drm_i915_gem_object *obj = intel_fb->obj;
 	int plane = intel_crtc->plane;
 	unsigned long linear_offset;
 	u32 dspcntr;
-	u32 reg;
+	u32 reg = DSPCNTR(plane);
 
-	intel_fb = to_intel_framebuffer(fb);
-	obj = intel_fb->obj;
+	dspcntr = DISPPLANE_GAMMA_ENABLE;
+
+	if (intel_crtc->primary_enabled)
+		dspcntr |= DISPLAY_PLANE_ENABLE;
+
+	if (INTEL_INFO(dev)->gen < 4) {
+		if (intel_crtc->pipe == PIPE_B)
+			dspcntr |= DISPPLANE_SEL_PIPE_B;
+
+		/* pipesrc and dspsize control the size that is scaled from,
+		 * which should always be the user's requested size.
+		 */
+		I915_WRITE(DSPSIZE(plane),
+			   ((intel_crtc->config.pipe_src_h - 1) << 16) |
+			   (intel_crtc->config.pipe_src_w - 1));
+		I915_WRITE(DSPPOS(plane), 0);
+	}
 
-	reg = DSPCNTR(plane);
-	dspcntr = I915_READ(reg);
-	/* Mask out pixel format bits in case we change it */
-	dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
 	switch (fb->pixel_format) {
 	case DRM_FORMAT_C8:
 		dspcntr |= DISPPLANE_8BPP;
@@ -2476,12 +2487,9 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
 		BUG();
 	}
 
-	if (INTEL_INFO(dev)->gen >= 4) {
-		if (obj->tiling_mode != I915_TILING_NONE)
-			dspcntr |= DISPPLANE_TILED;
-		else
-			dspcntr &= ~DISPPLANE_TILED;
-	}
+	if (INTEL_INFO(dev)->gen >= 4 &&
+	    obj->tiling_mode != I915_TILING_NONE)
+		dspcntr |= DISPPLANE_TILED;
 
 	if (IS_G4X(dev))
 		dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
@@ -2521,20 +2529,21 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	struct intel_framebuffer *intel_fb;
-	struct drm_i915_gem_object *obj;
+	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
+	struct drm_i915_gem_object *obj = intel_fb->obj;
 	int plane = intel_crtc->plane;
 	unsigned long linear_offset;
 	u32 dspcntr;
-	u32 reg;
+	u32 reg = DSPCNTR(plane);
 
-	intel_fb = to_intel_framebuffer(fb);
-	obj = intel_fb->obj;
+	dspcntr = DISPPLANE_GAMMA_ENABLE;
+
+	if (intel_crtc->primary_enabled)
+		dspcntr |= DISPLAY_PLANE_ENABLE;
+
+	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
+		dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
 
-	reg = DSPCNTR(plane);
-	dspcntr = I915_READ(reg);
-	/* Mask out pixel format bits in case we change it */
-	dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
 	switch (fb->pixel_format) {
 	case DRM_FORMAT_C8:
 		dspcntr |= DISPPLANE_8BPP;
@@ -2564,12 +2573,8 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
 
 	if (obj->tiling_mode != I915_TILING_NONE)
 		dspcntr |= DISPPLANE_TILED;
-	else
-		dspcntr &= ~DISPPLANE_TILED;
 
-	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
-		dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
-	else
+	if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
 		dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
 
 	I915_WRITE(reg, dspcntr);
@@ -4000,7 +4005,6 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	struct intel_encoder *encoder;
 	int pipe = intel_crtc->pipe;
-	enum plane plane = intel_crtc->plane;
 
 	WARN_ON(!crtc->enabled);
 
@@ -4022,10 +4026,6 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
 
 	ironlake_set_pipeconf(crtc);
 
-	/* Set up the display plane register */
-	I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
-	POSTING_READ(DSPCNTR(plane));
-
 	dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
 					       crtc->x, crtc->y);
 
@@ -4113,7 +4113,6 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	struct intel_encoder *encoder;
 	int pipe = intel_crtc->pipe;
-	enum plane plane = intel_crtc->plane;
 
 	WARN_ON(!crtc->enabled);
 
@@ -4134,10 +4133,6 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
 
 	intel_set_pipe_csc(crtc);
 
-	/* Set up the display plane register */
-	I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
-	POSTING_READ(DSPCNTR(plane));
-
 	dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
 					       crtc->x, crtc->y);
 
@@ -4623,9 +4618,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	struct intel_encoder *encoder;
 	int pipe = intel_crtc->pipe;
-	int plane = intel_crtc->plane;
 	bool is_dsi;
-	u32 dspcntr;
 
 	WARN_ON(!crtc->enabled);
 
@@ -4634,27 +4627,13 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
 
 	vlv_prepare_pll(intel_crtc);
 
-	/* Set up the display plane register */
-	dspcntr = DISPPLANE_GAMMA_ENABLE;
-
 	if (intel_crtc->config.has_dp_encoder)
 		intel_dp_set_m_n(intel_crtc);
 
 	intel_set_pipe_timings(intel_crtc);
 
-	/* pipesrc and dspsize control the size that is scaled from,
-	 * which should always be the user's requested size.
-	 */
-	I915_WRITE(DSPSIZE(plane),
-		   ((intel_crtc->config.pipe_src_h - 1) << 16) |
-		   (intel_crtc->config.pipe_src_w - 1));
-	I915_WRITE(DSPPOS(plane), 0);
-
 	i9xx_set_pipeconf(intel_crtc);
 
-	I915_WRITE(DSPCNTR(plane), dspcntr);
-	POSTING_READ(DSPCNTR(plane));
-
 	dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
 					       crtc->x, crtc->y);
 
@@ -4711,8 +4690,6 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	struct intel_encoder *encoder;
 	int pipe = intel_crtc->pipe;
-	int plane = intel_crtc->plane;
-	u32 dspcntr;
 
 	WARN_ON(!crtc->enabled);
 
@@ -4721,32 +4698,13 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
 
 	i9xx_set_pll_dividers(intel_crtc);
 
-	/* Set up the display plane register */
-	dspcntr = DISPPLANE_GAMMA_ENABLE;
-
-	if (pipe == 0)
-		dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
-	else
-		dspcntr |= DISPPLANE_SEL_PIPE_B;
-
 	if (intel_crtc->config.has_dp_encoder)
 		intel_dp_set_m_n(intel_crtc);
 
 	intel_set_pipe_timings(intel_crtc);
 
-	/* pipesrc and dspsize control the size that is scaled from,
-	 * which should always be the user's requested size.
-	 */
-	I915_WRITE(DSPSIZE(plane),
-		   ((intel_crtc->config.pipe_src_h - 1) << 16) |
-		   (intel_crtc->config.pipe_src_w - 1));
-	I915_WRITE(DSPPOS(plane), 0);
-
 	i9xx_set_pipeconf(intel_crtc);
 
-	I915_WRITE(DSPCNTR(plane), dspcntr);
-	POSTING_READ(DSPCNTR(plane));
-
 	dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
 					       crtc->x, crtc->y);
 
-- 
1.8.5.5

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 13/15] drm/i915: Eliminate rmw from .update_primary_plane()

[Matt Roper]

On Thu, Jun 05, 2014 at 07:16:02PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Move the entire DSPCNTR register setup into the .update_primary_plane()
> functions. That's where it belongs anyway and it'll also help 830M which
> has the extra problem that plane registers reads will return the value
> latched at the last vblank, not the value that was last written.
> 
> Also move DSPPOS and DSPSIZE setup there.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

The code changes here look good to me.  You may want to reword/clarify
in the commit message exactly what "move entire register setup" means
since I didn't really know what you meant by that phrase until I looked
at the code and realized you were talking about starting to build the
new value for DSPCNTR which had previously started in *_crtc_enable().  

Looking at these *_update_primary_plane() functions makes me wonder
whether it might help future review if we were to add another patch for
these functions that reorders the bit setting to match the order they
appear in the docs.  Maybe also drop in a code comment in for each of
the bits that are described in the PRM, but that we're purposely just
leaving to a default value of 0 (180 rotation, async update, etc.) so
that it's clear to the reader that we expect the implicit assignment of
0 rather than overlooking overlooking we should have been programming.

Anyway, the code changes here look good, so with or without my
suggestions this is
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>


> ---
>  drivers/gpu/drm/i915/intel_display.c | 110 +++++++++++------------------------
>  1 file changed, 34 insertions(+), 76 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 4f02464..74bbab9 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2431,20 +2431,31 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
>  	struct drm_device *dev = crtc->dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> -	struct intel_framebuffer *intel_fb;
> -	struct drm_i915_gem_object *obj;
> +	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
> +	struct drm_i915_gem_object *obj = intel_fb->obj;
>  	int plane = intel_crtc->plane;
>  	unsigned long linear_offset;
>  	u32 dspcntr;
> -	u32 reg;
> +	u32 reg = DSPCNTR(plane);
>  
> -	intel_fb = to_intel_framebuffer(fb);
> -	obj = intel_fb->obj;
> +	dspcntr = DISPPLANE_GAMMA_ENABLE;
> +
> +	if (intel_crtc->primary_enabled)
> +		dspcntr |= DISPLAY_PLANE_ENABLE;
> +
> +	if (INTEL_INFO(dev)->gen < 4) {
> +		if (intel_crtc->pipe == PIPE_B)
> +			dspcntr |= DISPPLANE_SEL_PIPE_B;
> +
> +		/* pipesrc and dspsize control the size that is scaled from,
> +		 * which should always be the user's requested size.
> +		 */
> +		I915_WRITE(DSPSIZE(plane),
> +			   ((intel_crtc->config.pipe_src_h - 1) << 16) |
> +			   (intel_crtc->config.pipe_src_w - 1));
> +		I915_WRITE(DSPPOS(plane), 0);
> +	}
>  
> -	reg = DSPCNTR(plane);
> -	dspcntr = I915_READ(reg);
> -	/* Mask out pixel format bits in case we change it */
> -	dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
>  	switch (fb->pixel_format) {
>  	case DRM_FORMAT_C8:
>  		dspcntr |= DISPPLANE_8BPP;
> @@ -2476,12 +2487,9 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
>  		BUG();
>  	}
>  
> -	if (INTEL_INFO(dev)->gen >= 4) {
> -		if (obj->tiling_mode != I915_TILING_NONE)
> -			dspcntr |= DISPPLANE_TILED;
> -		else
> -			dspcntr &= ~DISPPLANE_TILED;
> -	}
> +	if (INTEL_INFO(dev)->gen >= 4 &&
> +	    obj->tiling_mode != I915_TILING_NONE)
> +		dspcntr |= DISPPLANE_TILED;
>  
>  	if (IS_G4X(dev))
>  		dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
> @@ -2521,20 +2529,21 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
>  	struct drm_device *dev = crtc->dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> -	struct intel_framebuffer *intel_fb;
> -	struct drm_i915_gem_object *obj;
> +	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
> +	struct drm_i915_gem_object *obj = intel_fb->obj;
>  	int plane = intel_crtc->plane;
>  	unsigned long linear_offset;
>  	u32 dspcntr;
> -	u32 reg;
> +	u32 reg = DSPCNTR(plane);
>  
> -	intel_fb = to_intel_framebuffer(fb);
> -	obj = intel_fb->obj;
> +	dspcntr = DISPPLANE_GAMMA_ENABLE;
> +
> +	if (intel_crtc->primary_enabled)
> +		dspcntr |= DISPLAY_PLANE_ENABLE;
> +
> +	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> +		dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
>  
> -	reg = DSPCNTR(plane);
> -	dspcntr = I915_READ(reg);
> -	/* Mask out pixel format bits in case we change it */
> -	dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
>  	switch (fb->pixel_format) {
>  	case DRM_FORMAT_C8:
>  		dspcntr |= DISPPLANE_8BPP;
> @@ -2564,12 +2573,8 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
>  
>  	if (obj->tiling_mode != I915_TILING_NONE)
>  		dspcntr |= DISPPLANE_TILED;
> -	else
> -		dspcntr &= ~DISPPLANE_TILED;
>  
> -	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> -		dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
> -	else
> +	if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
>  		dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
>  
>  	I915_WRITE(reg, dspcntr);
> @@ -4000,7 +4005,6 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>  	struct intel_encoder *encoder;
>  	int pipe = intel_crtc->pipe;
> -	enum plane plane = intel_crtc->plane;
>  
>  	WARN_ON(!crtc->enabled);
>  
> @@ -4022,10 +4026,6 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
>  
>  	ironlake_set_pipeconf(crtc);
>  
> -	/* Set up the display plane register */
> -	I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
> -	POSTING_READ(DSPCNTR(plane));
> -
>  	dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
>  					       crtc->x, crtc->y);
>  
> @@ -4113,7 +4113,6 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>  	struct intel_encoder *encoder;
>  	int pipe = intel_crtc->pipe;
> -	enum plane plane = intel_crtc->plane;
>  
>  	WARN_ON(!crtc->enabled);
>  
> @@ -4134,10 +4133,6 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
>  
>  	intel_set_pipe_csc(crtc);
>  
> -	/* Set up the display plane register */
> -	I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
> -	POSTING_READ(DSPCNTR(plane));
> -
>  	dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
>  					       crtc->x, crtc->y);
>  
> @@ -4623,9 +4618,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>  	struct intel_encoder *encoder;
>  	int pipe = intel_crtc->pipe;
> -	int plane = intel_crtc->plane;
>  	bool is_dsi;
> -	u32 dspcntr;
>  
>  	WARN_ON(!crtc->enabled);
>  
> @@ -4634,27 +4627,13 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
>  
>  	vlv_prepare_pll(intel_crtc);
>  
> -	/* Set up the display plane register */
> -	dspcntr = DISPPLANE_GAMMA_ENABLE;
> -
>  	if (intel_crtc->config.has_dp_encoder)
>  		intel_dp_set_m_n(intel_crtc);
>  
>  	intel_set_pipe_timings(intel_crtc);
>  
> -	/* pipesrc and dspsize control the size that is scaled from,
> -	 * which should always be the user's requested size.
> -	 */
> -	I915_WRITE(DSPSIZE(plane),
> -		   ((intel_crtc->config.pipe_src_h - 1) << 16) |
> -		   (intel_crtc->config.pipe_src_w - 1));
> -	I915_WRITE(DSPPOS(plane), 0);
> -
>  	i9xx_set_pipeconf(intel_crtc);
>  
> -	I915_WRITE(DSPCNTR(plane), dspcntr);
> -	POSTING_READ(DSPCNTR(plane));
> -
>  	dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
>  					       crtc->x, crtc->y);
>  
> @@ -4711,8 +4690,6 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>  	struct intel_encoder *encoder;
>  	int pipe = intel_crtc->pipe;
> -	int plane = intel_crtc->plane;
> -	u32 dspcntr;
>  
>  	WARN_ON(!crtc->enabled);
>  
> @@ -4721,32 +4698,13 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
>  
>  	i9xx_set_pll_dividers(intel_crtc);
>  
> -	/* Set up the display plane register */
> -	dspcntr = DISPPLANE_GAMMA_ENABLE;
> -
> -	if (pipe == 0)
> -		dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
> -	else
> -		dspcntr |= DISPPLANE_SEL_PIPE_B;
> -
>  	if (intel_crtc->config.has_dp_encoder)
>  		intel_dp_set_m_n(intel_crtc);
>  
>  	intel_set_pipe_timings(intel_crtc);
>  
> -	/* pipesrc and dspsize control the size that is scaled from,
> -	 * which should always be the user's requested size.
> -	 */
> -	I915_WRITE(DSPSIZE(plane),
> -		   ((intel_crtc->config.pipe_src_h - 1) << 16) |
> -		   (intel_crtc->config.pipe_src_w - 1));
> -	I915_WRITE(DSPPOS(plane), 0);
> -
>  	i9xx_set_pipeconf(intel_crtc);
>  
> -	I915_WRITE(DSPCNTR(plane), dspcntr);
> -	POSTING_READ(DSPCNTR(plane));
> -
>  	dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
>  					       crtc->x, crtc->y);
>  
> -- 
> 1.8.5.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795

[PATCH v2 13/15] drm/i915: Eliminate rmw from .update_primary_plane()

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Move the entire DSPCNTR register setup into the .update_primary_plane()
functions. That's where it belongs anyway and it'll also help 830M which
has the extra problem that plane registers reads will return the value
latched at the last vblank, not the value that was last written.

Also move DSPPOS and DSPSIZE setup there.

v2: Don't move variable initialization to avoid churn later

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 100 +++++++++++------------------------
 1 file changed, 32 insertions(+), 68 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 1c7ffe2..c048e31 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2436,15 +2436,29 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
 	int plane = intel_crtc->plane;
 	unsigned long linear_offset;
 	u32 dspcntr;
-	u32 reg;
+	u32 reg = DSPCNTR(plane);
 
 	intel_fb = to_intel_framebuffer(fb);
 	obj = intel_fb->obj;
 
-	reg = DSPCNTR(plane);
-	dspcntr = I915_READ(reg);
-	/* Mask out pixel format bits in case we change it */
-	dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
+	dspcntr = DISPPLANE_GAMMA_ENABLE;
+
+	if (intel_crtc->primary_enabled)
+		dspcntr |= DISPLAY_PLANE_ENABLE;
+
+	if (INTEL_INFO(dev)->gen < 4) {
+		if (intel_crtc->pipe == PIPE_B)
+			dspcntr |= DISPPLANE_SEL_PIPE_B;
+
+		/* pipesrc and dspsize control the size that is scaled from,
+		 * which should always be the user's requested size.
+		 */
+		I915_WRITE(DSPSIZE(plane),
+			   ((intel_crtc->config.pipe_src_h - 1) << 16) |
+			   (intel_crtc->config.pipe_src_w - 1));
+		I915_WRITE(DSPPOS(plane), 0);
+	}
+
 	switch (fb->pixel_format) {
 	case DRM_FORMAT_C8:
 		dspcntr |= DISPPLANE_8BPP;
@@ -2476,12 +2490,9 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
 		BUG();
 	}
 
-	if (INTEL_INFO(dev)->gen >= 4) {
-		if (obj->tiling_mode != I915_TILING_NONE)
-			dspcntr |= DISPPLANE_TILED;
-		else
-			dspcntr &= ~DISPPLANE_TILED;
-	}
+	if (INTEL_INFO(dev)->gen >= 4 &&
+	    obj->tiling_mode != I915_TILING_NONE)
+		dspcntr |= DISPPLANE_TILED;
 
 	if (IS_G4X(dev))
 		dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
@@ -2526,15 +2537,19 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
 	int plane = intel_crtc->plane;
 	unsigned long linear_offset;
 	u32 dspcntr;
-	u32 reg;
+	u32 reg = DSPCNTR(plane);
 
 	intel_fb = to_intel_framebuffer(fb);
 	obj = intel_fb->obj;
 
-	reg = DSPCNTR(plane);
-	dspcntr = I915_READ(reg);
-	/* Mask out pixel format bits in case we change it */
-	dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
+	dspcntr = DISPPLANE_GAMMA_ENABLE;
+
+	if (intel_crtc->primary_enabled)
+		dspcntr |= DISPLAY_PLANE_ENABLE;
+
+	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
+		dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
+
 	switch (fb->pixel_format) {
 	case DRM_FORMAT_C8:
 		dspcntr |= DISPPLANE_8BPP;
@@ -2564,12 +2579,8 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
 
 	if (obj->tiling_mode != I915_TILING_NONE)
 		dspcntr |= DISPPLANE_TILED;
-	else
-		dspcntr &= ~DISPPLANE_TILED;
 
-	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
-		dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
-	else
+	if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
 		dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
 
 	I915_WRITE(reg, dspcntr);
@@ -4000,7 +4011,6 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	struct intel_encoder *encoder;
 	int pipe = intel_crtc->pipe;
-	enum plane plane = intel_crtc->plane;
 
 	WARN_ON(!crtc->enabled);
 
@@ -4022,10 +4032,6 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
 
 	ironlake_set_pipeconf(crtc);
 
-	/* Set up the display plane register */
-	I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
-	POSTING_READ(DSPCNTR(plane));
-
 	dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
 					       crtc->x, crtc->y);
 
@@ -4113,7 +4119,6 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	struct intel_encoder *encoder;
 	int pipe = intel_crtc->pipe;
-	enum plane plane = intel_crtc->plane;
 
 	WARN_ON(!crtc->enabled);
 
@@ -4134,10 +4139,6 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
 
 	intel_set_pipe_csc(crtc);
 
-	/* Set up the display plane register */
-	I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
-	POSTING_READ(DSPCNTR(plane));
-
 	dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
 					       crtc->x, crtc->y);
 
@@ -4623,9 +4624,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	struct intel_encoder *encoder;
 	int pipe = intel_crtc->pipe;
-	int plane = intel_crtc->plane;
 	bool is_dsi;
-	u32 dspcntr;
 
 	WARN_ON(!crtc->enabled);
 
@@ -4634,27 +4633,13 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
 
 	vlv_prepare_pll(intel_crtc);
 
-	/* Set up the display plane register */
-	dspcntr = DISPPLANE_GAMMA_ENABLE;
-
 	if (intel_crtc->config.has_dp_encoder)
 		intel_dp_set_m_n(intel_crtc);
 
 	intel_set_pipe_timings(intel_crtc);
 
-	/* pipesrc and dspsize control the size that is scaled from,
-	 * which should always be the user's requested size.
-	 */
-	I915_WRITE(DSPSIZE(plane),
-		   ((intel_crtc->config.pipe_src_h - 1) << 16) |
-		   (intel_crtc->config.pipe_src_w - 1));
-	I915_WRITE(DSPPOS(plane), 0);
-
 	i9xx_set_pipeconf(intel_crtc);
 
-	I915_WRITE(DSPCNTR(plane), dspcntr);
-	POSTING_READ(DSPCNTR(plane));
-
 	dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
 					       crtc->x, crtc->y);
 
@@ -4711,8 +4696,6 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	struct intel_encoder *encoder;
 	int pipe = intel_crtc->pipe;
-	int plane = intel_crtc->plane;
-	u32 dspcntr;
 
 	WARN_ON(!crtc->enabled);
 
@@ -4721,32 +4704,13 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
 
 	i9xx_set_pll_dividers(intel_crtc);
 
-	/* Set up the display plane register */
-	dspcntr = DISPPLANE_GAMMA_ENABLE;
-
-	if (pipe == 0)
-		dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
-	else
-		dspcntr |= DISPPLANE_SEL_PIPE_B;
-
 	if (intel_crtc->config.has_dp_encoder)
 		intel_dp_set_m_n(intel_crtc);
 
 	intel_set_pipe_timings(intel_crtc);
 
-	/* pipesrc and dspsize control the size that is scaled from,
-	 * which should always be the user's requested size.
-	 */
-	I915_WRITE(DSPSIZE(plane),
-		   ((intel_crtc->config.pipe_src_h - 1) << 16) |
-		   (intel_crtc->config.pipe_src_w - 1));
-	I915_WRITE(DSPPOS(plane), 0);
-
 	i9xx_set_pipeconf(intel_crtc);
 
-	I915_WRITE(DSPCNTR(plane), dspcntr);
-	POSTING_READ(DSPCNTR(plane));
-
 	dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
 					       crtc->x, crtc->y);
 
-- 
1.8.5.5

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[PATCH 14/15] drm/i915: Call .update_primary_plane in intel_{enable, disable}_primary_hw_plane()

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Make the intel_{enable,disable}_primary_hw_plane() simply call
.update_primary_plane(), thus eliminating the rmw from these functions
which should help the poor old 830M.

Now we can also remove the .update_primary_plane() from the
.crtc_enable() hooks.

This also has the nice benefit of making primary planes a bit closer to
the way we handle sprite planes during modesets.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 92 +++++++++++-------------------------
 1 file changed, 27 insertions(+), 65 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 74bbab9..098017a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2147,63 +2147,51 @@ void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
 
 /**
  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
- * @dev_priv: i915 private structure
- * @plane: plane to enable
- * @pipe: pipe being fed
+ * @plane:  plane to be enabled
+ * @crtc: crtc for the plane
  *
- * Enable @plane on @pipe, making sure that @pipe is running first.
+ * Enable @plane on @crtc, making sure that the pipe is running first.
  */
-static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
-					  enum plane plane, enum pipe pipe)
+static void intel_enable_primary_hw_plane(struct drm_plane *plane,
+					  struct drm_crtc *crtc)
 {
-	struct intel_crtc *intel_crtc =
-		to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
-	int reg;
-	u32 val;
+	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 
 	/* If the pipe isn't enabled, we can't pump pixels and may hang */
-	assert_pipe_enabled(dev_priv, pipe);
+	assert_pipe_enabled(dev_priv, intel_crtc->pipe);
 
 	if (intel_crtc->primary_enabled)
 		return;
 
 	intel_crtc->primary_enabled = true;
 
-	reg = DSPCNTR(plane);
-	val = I915_READ(reg);
-	WARN_ON(val & DISPLAY_PLANE_ENABLE);
-
-	I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
-	intel_flush_primary_plane(dev_priv, plane);
+	dev_priv->display.update_primary_plane(crtc, plane->fb,
+					       crtc->x, crtc->y);
 }
 
 /**
  * intel_disable_primary_hw_plane - disable the primary hardware plane
- * @dev_priv: i915 private structure
- * @plane: plane to disable
- * @pipe: pipe consuming the data
+ * @plane: plane to be disabled
+ * @crtc: crtc for the plane
  *
- * Disable @plane; should be an independent operation.
+ * Disable @plane on @crtc, making sure that the pipe is running first.
  */
-static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv,
-					   enum plane plane, enum pipe pipe)
+static void intel_disable_primary_hw_plane(struct drm_plane *plane,
+					   struct drm_crtc *crtc)
 {
-	struct intel_crtc *intel_crtc =
-		to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
-	int reg;
-	u32 val;
+	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+
+	assert_pipe_enabled(dev_priv, intel_crtc->pipe);
 
 	if (!intel_crtc->primary_enabled)
 		return;
 
 	intel_crtc->primary_enabled = false;
 
-	reg = DSPCNTR(plane);
-	val = I915_READ(reg);
-	WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0);
-
-	I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
-	intel_flush_primary_plane(dev_priv, plane);
+	dev_priv->display.update_primary_plane(crtc, plane->fb,
+					       crtc->x, crtc->y);
 }
 
 static bool need_vtd_wa(struct drm_device *dev)
@@ -3955,11 +3943,10 @@ static void intel_crtc_enable_planes(struct drm_crtc *crtc)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	int pipe = intel_crtc->pipe;
-	int plane = intel_crtc->plane;
 
 	drm_vblank_on(dev, pipe);
 
-	intel_enable_primary_hw_plane(dev_priv, plane, pipe);
+	intel_enable_primary_hw_plane(crtc->primary, crtc);
 	intel_enable_planes(crtc);
 	/* The fixup needs to happen before cursor is enabled */
 	if (IS_G4X(dev))
@@ -3993,7 +3980,7 @@ static void intel_crtc_disable_planes(struct drm_crtc *crtc)
 	intel_crtc_dpms_overlay(intel_crtc, false);
 	intel_crtc_update_cursor(crtc, false);
 	intel_disable_planes(crtc);
-	intel_disable_primary_hw_plane(dev_priv, plane, pipe);
+	intel_disable_primary_hw_plane(crtc->primary, crtc);
 
 	drm_vblank_off(dev, pipe);
 }
@@ -4026,9 +4013,6 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
 
 	ironlake_set_pipeconf(crtc);
 
-	dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
-					       crtc->x, crtc->y);
-
 	intel_crtc->active = true;
 
 	intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
@@ -4133,9 +4117,6 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
 
 	intel_set_pipe_csc(crtc);
 
-	dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
-					       crtc->x, crtc->y);
-
 	intel_crtc->active = true;
 
 	intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
@@ -4614,7 +4595,6 @@ static void valleyview_modeset_global_resources(struct drm_device *dev)
 static void valleyview_crtc_enable(struct drm_crtc *crtc)
 {
 	struct drm_device *dev = crtc->dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	struct intel_encoder *encoder;
 	int pipe = intel_crtc->pipe;
@@ -4634,9 +4614,6 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
 
 	i9xx_set_pipeconf(intel_crtc);
 
-	dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
-					       crtc->x, crtc->y);
-
 	intel_crtc->active = true;
 
 	intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
@@ -4686,7 +4663,6 @@ static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
 static void i9xx_crtc_enable(struct drm_crtc *crtc)
 {
 	struct drm_device *dev = crtc->dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	struct intel_encoder *encoder;
 	int pipe = intel_crtc->pipe;
@@ -4705,9 +4681,6 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
 
 	i9xx_set_pipeconf(intel_crtc);
 
-	dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
-					       crtc->x, crtc->y);
-
 	intel_crtc->active = true;
 
 	if (!IS_GEN2(dev))
@@ -10854,7 +10827,6 @@ static int intel_crtc_set_config(struct drm_mode_set *set)
 		ret = intel_set_mode(set->crtc, set->mode,
 				     set->x, set->y, set->fb);
 	} else if (config->fb_changed) {
-		struct drm_i915_private *dev_priv = dev->dev_private;
 		struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
 
 		intel_crtc_wait_for_pending_flips(set->crtc);
@@ -10868,8 +10840,7 @@ static int intel_crtc_set_config(struct drm_mode_set *set)
 		 */
 		if (!intel_crtc->primary_enabled && ret == 0) {
 			WARN_ON(!intel_crtc->active);
-			intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane,
-						      intel_crtc->pipe);
+			intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
 		}
 
 		/*
@@ -11024,9 +10995,6 @@ static void intel_shared_dpll_init(struct drm_device *dev)
 static int
 intel_primary_plane_disable(struct drm_plane *plane)
 {
-	struct drm_device *dev = plane->dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_plane *intel_plane = to_intel_plane(plane);
 	struct intel_crtc *intel_crtc;
 
 	if (!plane->fb)
@@ -11049,8 +11017,7 @@ intel_primary_plane_disable(struct drm_plane *plane)
 		goto disable_unpin;
 
 	intel_crtc_wait_for_pending_flips(plane->crtc);
-	intel_disable_primary_hw_plane(dev_priv, intel_plane->plane,
-				       intel_plane->pipe);
+	intel_disable_primary_hw_plane(plane, plane->crtc);
 
 disable_unpin:
 	intel_unpin_fb_obj(to_intel_framebuffer(plane->fb)->obj);
@@ -11067,9 +11034,7 @@ intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
 			     uint32_t src_w, uint32_t src_h)
 {
 	struct drm_device *dev = crtc->dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	struct intel_plane *intel_plane = to_intel_plane(plane);
 	struct drm_rect dest = {
 		/* integer pixels */
 		.x1 = crtc_x,
@@ -11143,9 +11108,7 @@ intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
 		}
 
 		if (intel_crtc->primary_enabled)
-			intel_disable_primary_hw_plane(dev_priv,
-						       intel_plane->plane,
-						       intel_plane->pipe);
+			intel_disable_primary_hw_plane(plane, crtc);
 
 
 		if (plane->fb != fb)
@@ -11160,8 +11123,7 @@ intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
 		return ret;
 
 	if (!intel_crtc->primary_enabled)
-		intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane,
-					      intel_crtc->pipe);
+		intel_enable_primary_hw_plane(plane, crtc);
 
 	return 0;
 }
-- 
1.8.5.5

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Re: [PATCH 14/15] drm/i915: Call .update_primary_plane in intel_{enable, disable}_primary_hw_plane()

[Matt Roper]

On Thu, Jun 05, 2014 at 07:16:03PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Make the intel_{enable,disable}_primary_hw_plane() simply call
> .update_primary_plane(), thus eliminating the rmw from these functions
> which should help the poor old 830M.
> 
> Now we can also remove the .update_primary_plane() from the
> .crtc_enable() hooks.

This is because intel_crtc_enable_planes() ->
intel_enable_primary_hw_plane() takes care of it for us, right?  Can you
clarify that in the message?  That wasn't immediately obvious from the
context visible in the diff.

> This also has the nice benefit of making primary planes a bit closer to
> the way we handle sprite planes during modesets.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

On a somewhat related note, is there any reason not to call
.update_primary_plane() at the end of the various sprite update
functions in intel_sprite.c instead of calling
intel_update_primary_plane() and intel_flush_primary_plane()?  I find
the name similarity between intel_update_primary_plane() and
.update_primary_plane() confusing and it looks like we might be able to
consolidate a bit there unless I'm overlooking something.


Matt

> ---
>  drivers/gpu/drm/i915/intel_display.c | 92 +++++++++++-------------------------
>  1 file changed, 27 insertions(+), 65 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 74bbab9..098017a 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2147,63 +2147,51 @@ void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
>  
>  /**
>   * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
> - * @dev_priv: i915 private structure
> - * @plane: plane to enable
> - * @pipe: pipe being fed
> + * @plane:  plane to be enabled
> + * @crtc: crtc for the plane
>   *
> - * Enable @plane on @pipe, making sure that @pipe is running first.
> + * Enable @plane on @crtc, making sure that the pipe is running first.
>   */
> -static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
> -					  enum plane plane, enum pipe pipe)
> +static void intel_enable_primary_hw_plane(struct drm_plane *plane,
> +					  struct drm_crtc *crtc)
>  {
> -	struct intel_crtc *intel_crtc =
> -		to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
> -	int reg;
> -	u32 val;
> +	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
> +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>  
>  	/* If the pipe isn't enabled, we can't pump pixels and may hang */
> -	assert_pipe_enabled(dev_priv, pipe);
> +	assert_pipe_enabled(dev_priv, intel_crtc->pipe);
>  
>  	if (intel_crtc->primary_enabled)
>  		return;
>  
>  	intel_crtc->primary_enabled = true;
>  
> -	reg = DSPCNTR(plane);
> -	val = I915_READ(reg);
> -	WARN_ON(val & DISPLAY_PLANE_ENABLE);
> -
> -	I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
> -	intel_flush_primary_plane(dev_priv, plane);
> +	dev_priv->display.update_primary_plane(crtc, plane->fb,
> +					       crtc->x, crtc->y);
>  }
>  
>  /**
>   * intel_disable_primary_hw_plane - disable the primary hardware plane
> - * @dev_priv: i915 private structure
> - * @plane: plane to disable
> - * @pipe: pipe consuming the data
> + * @plane: plane to be disabled
> + * @crtc: crtc for the plane
>   *
> - * Disable @plane; should be an independent operation.
> + * Disable @plane on @crtc, making sure that the pipe is running first.
>   */
> -static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv,
> -					   enum plane plane, enum pipe pipe)
> +static void intel_disable_primary_hw_plane(struct drm_plane *plane,
> +					   struct drm_crtc *crtc)
>  {
> -	struct intel_crtc *intel_crtc =
> -		to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
> -	int reg;
> -	u32 val;
> +	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
> +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> +
> +	assert_pipe_enabled(dev_priv, intel_crtc->pipe);
>  
>  	if (!intel_crtc->primary_enabled)
>  		return;
>  
>  	intel_crtc->primary_enabled = false;
>  
> -	reg = DSPCNTR(plane);
> -	val = I915_READ(reg);
> -	WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0);
> -
> -	I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
> -	intel_flush_primary_plane(dev_priv, plane);
> +	dev_priv->display.update_primary_plane(crtc, plane->fb,
> +					       crtc->x, crtc->y);
>  }
>  
>  static bool need_vtd_wa(struct drm_device *dev)
> @@ -3955,11 +3943,10 @@ static void intel_crtc_enable_planes(struct drm_crtc *crtc)
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>  	int pipe = intel_crtc->pipe;
> -	int plane = intel_crtc->plane;
>  
>  	drm_vblank_on(dev, pipe);
>  
> -	intel_enable_primary_hw_plane(dev_priv, plane, pipe);
> +	intel_enable_primary_hw_plane(crtc->primary, crtc);
>  	intel_enable_planes(crtc);
>  	/* The fixup needs to happen before cursor is enabled */
>  	if (IS_G4X(dev))
> @@ -3993,7 +3980,7 @@ static void intel_crtc_disable_planes(struct drm_crtc *crtc)
>  	intel_crtc_dpms_overlay(intel_crtc, false);
>  	intel_crtc_update_cursor(crtc, false);
>  	intel_disable_planes(crtc);
> -	intel_disable_primary_hw_plane(dev_priv, plane, pipe);
> +	intel_disable_primary_hw_plane(crtc->primary, crtc);
>  
>  	drm_vblank_off(dev, pipe);
>  }
> @@ -4026,9 +4013,6 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
>  
>  	ironlake_set_pipeconf(crtc);
>  
> -	dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
> -					       crtc->x, crtc->y);
> -
>  	intel_crtc->active = true;
>  
>  	intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
> @@ -4133,9 +4117,6 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
>  
>  	intel_set_pipe_csc(crtc);
>  
> -	dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
> -					       crtc->x, crtc->y);
> -
>  	intel_crtc->active = true;
>  
>  	intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
> @@ -4614,7 +4595,6 @@ static void valleyview_modeset_global_resources(struct drm_device *dev)
>  static void valleyview_crtc_enable(struct drm_crtc *crtc)
>  {
>  	struct drm_device *dev = crtc->dev;
> -	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>  	struct intel_encoder *encoder;
>  	int pipe = intel_crtc->pipe;
> @@ -4634,9 +4614,6 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
>  
>  	i9xx_set_pipeconf(intel_crtc);
>  
> -	dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
> -					       crtc->x, crtc->y);
> -
>  	intel_crtc->active = true;
>  
>  	intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
> @@ -4686,7 +4663,6 @@ static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
>  static void i9xx_crtc_enable(struct drm_crtc *crtc)
>  {
>  	struct drm_device *dev = crtc->dev;
> -	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>  	struct intel_encoder *encoder;
>  	int pipe = intel_crtc->pipe;
> @@ -4705,9 +4681,6 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
>  
>  	i9xx_set_pipeconf(intel_crtc);
>  
> -	dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
> -					       crtc->x, crtc->y);
> -
>  	intel_crtc->active = true;
>  
>  	if (!IS_GEN2(dev))
> @@ -10854,7 +10827,6 @@ static int intel_crtc_set_config(struct drm_mode_set *set)
>  		ret = intel_set_mode(set->crtc, set->mode,
>  				     set->x, set->y, set->fb);
>  	} else if (config->fb_changed) {
> -		struct drm_i915_private *dev_priv = dev->dev_private;
>  		struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
>  
>  		intel_crtc_wait_for_pending_flips(set->crtc);
> @@ -10868,8 +10840,7 @@ static int intel_crtc_set_config(struct drm_mode_set *set)
>  		 */
>  		if (!intel_crtc->primary_enabled && ret == 0) {
>  			WARN_ON(!intel_crtc->active);
> -			intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane,
> -						      intel_crtc->pipe);
> +			intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
>  		}
>  
>  		/*
> @@ -11024,9 +10995,6 @@ static void intel_shared_dpll_init(struct drm_device *dev)
>  static int
>  intel_primary_plane_disable(struct drm_plane *plane)
>  {
> -	struct drm_device *dev = plane->dev;
> -	struct drm_i915_private *dev_priv = dev->dev_private;
> -	struct intel_plane *intel_plane = to_intel_plane(plane);
>  	struct intel_crtc *intel_crtc;
>  
>  	if (!plane->fb)
> @@ -11049,8 +11017,7 @@ intel_primary_plane_disable(struct drm_plane *plane)
>  		goto disable_unpin;
>  
>  	intel_crtc_wait_for_pending_flips(plane->crtc);
> -	intel_disable_primary_hw_plane(dev_priv, intel_plane->plane,
> -				       intel_plane->pipe);
> +	intel_disable_primary_hw_plane(plane, plane->crtc);
>  
>  disable_unpin:
>  	intel_unpin_fb_obj(to_intel_framebuffer(plane->fb)->obj);
> @@ -11067,9 +11034,7 @@ intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
>  			     uint32_t src_w, uint32_t src_h)
>  {
>  	struct drm_device *dev = crtc->dev;
> -	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> -	struct intel_plane *intel_plane = to_intel_plane(plane);
>  	struct drm_rect dest = {
>  		/* integer pixels */
>  		.x1 = crtc_x,
> @@ -11143,9 +11108,7 @@ intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
>  		}
>  
>  		if (intel_crtc->primary_enabled)
> -			intel_disable_primary_hw_plane(dev_priv,
> -						       intel_plane->plane,
> -						       intel_plane->pipe);
> +			intel_disable_primary_hw_plane(plane, crtc);
>  
>  
>  		if (plane->fb != fb)
> @@ -11160,8 +11123,7 @@ intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
>  		return ret;
>  
>  	if (!intel_crtc->primary_enabled)
> -		intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane,
> -					      intel_crtc->pipe);
> +		intel_enable_primary_hw_plane(plane, crtc);
>  
>  	return 0;
>  }
> -- 
> 1.8.5.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795

Re: [PATCH 14/15] drm/i915: Call .update_primary_plane in intel_{enable, disable}_primary_hw_plane()

[Ville Syrjälä]

On Thu, Jun 05, 2014 at 05:02:31PM -0700, Matt Roper wrote:
> On Thu, Jun 05, 2014 at 07:16:03PM +0300, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Make the intel_{enable,disable}_primary_hw_plane() simply call
> > .update_primary_plane(), thus eliminating the rmw from these functions
> > which should help the poor old 830M.
> > 
> > Now we can also remove the .update_primary_plane() from the
> > .crtc_enable() hooks.
> 
> This is because intel_crtc_enable_planes() ->
> intel_enable_primary_hw_plane() takes care of it for us, right?

Yes.

> Can you
> clarify that in the message?  That wasn't immediately obvious from the
> context visible in the diff.

Can do.

> 
> > This also has the nice benefit of making primary planes a bit closer to
> > the way we handle sprite planes during modesets.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> 
> On a somewhat related note, is there any reason not to call
> .update_primary_plane() at the end of the various sprite update
> functions in intel_sprite.c instead of calling
> intel_update_primary_plane() and intel_flush_primary_plane()?  I find
> the name similarity between intel_update_primary_plane() and
> .update_primary_plane() confusing and it looks like we might be able to
> consolidate a bit there unless I'm overlooking something.

I simply decided to leave the sprite code alone for now. Should probably
just call the .update_primary_plane hook there as well. It doesn't seem
too heavy to really compromise the atomic vblank evade thing. Though
at some point we should really start building up the plane_config thing
and then we should be able to minimize the amont of stuff we do in
that section.

> 
> 
> Matt
> 
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 92 +++++++++++-------------------------
> >  1 file changed, 27 insertions(+), 65 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 74bbab9..098017a 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -2147,63 +2147,51 @@ void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
> >  
> >  /**
> >   * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
> > - * @dev_priv: i915 private structure
> > - * @plane: plane to enable
> > - * @pipe: pipe being fed
> > + * @plane:  plane to be enabled
> > + * @crtc: crtc for the plane
> >   *
> > - * Enable @plane on @pipe, making sure that @pipe is running first.
> > + * Enable @plane on @crtc, making sure that the pipe is running first.
> >   */
> > -static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
> > -					  enum plane plane, enum pipe pipe)
> > +static void intel_enable_primary_hw_plane(struct drm_plane *plane,
> > +					  struct drm_crtc *crtc)
> >  {
> > -	struct intel_crtc *intel_crtc =
> > -		to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
> > -	int reg;
> > -	u32 val;
> > +	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
> > +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> >  
> >  	/* If the pipe isn't enabled, we can't pump pixels and may hang */
> > -	assert_pipe_enabled(dev_priv, pipe);
> > +	assert_pipe_enabled(dev_priv, intel_crtc->pipe);
> >  
> >  	if (intel_crtc->primary_enabled)
> >  		return;
> >  
> >  	intel_crtc->primary_enabled = true;
> >  
> > -	reg = DSPCNTR(plane);
> > -	val = I915_READ(reg);
> > -	WARN_ON(val & DISPLAY_PLANE_ENABLE);
> > -
> > -	I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
> > -	intel_flush_primary_plane(dev_priv, plane);
> > +	dev_priv->display.update_primary_plane(crtc, plane->fb,
> > +					       crtc->x, crtc->y);
> >  }
> >  
> >  /**
> >   * intel_disable_primary_hw_plane - disable the primary hardware plane
> > - * @dev_priv: i915 private structure
> > - * @plane: plane to disable
> > - * @pipe: pipe consuming the data
> > + * @plane: plane to be disabled
> > + * @crtc: crtc for the plane
> >   *
> > - * Disable @plane; should be an independent operation.
> > + * Disable @plane on @crtc, making sure that the pipe is running first.
> >   */
> > -static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv,
> > -					   enum plane plane, enum pipe pipe)
> > +static void intel_disable_primary_hw_plane(struct drm_plane *plane,
> > +					   struct drm_crtc *crtc)
> >  {
> > -	struct intel_crtc *intel_crtc =
> > -		to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
> > -	int reg;
> > -	u32 val;
> > +	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
> > +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > +
> > +	assert_pipe_enabled(dev_priv, intel_crtc->pipe);
> >  
> >  	if (!intel_crtc->primary_enabled)
> >  		return;
> >  
> >  	intel_crtc->primary_enabled = false;
> >  
> > -	reg = DSPCNTR(plane);
> > -	val = I915_READ(reg);
> > -	WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0);
> > -
> > -	I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
> > -	intel_flush_primary_plane(dev_priv, plane);
> > +	dev_priv->display.update_primary_plane(crtc, plane->fb,
> > +					       crtc->x, crtc->y);
> >  }
> >  
> >  static bool need_vtd_wa(struct drm_device *dev)
> > @@ -3955,11 +3943,10 @@ static void intel_crtc_enable_planes(struct drm_crtc *crtc)
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> >  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> >  	int pipe = intel_crtc->pipe;
> > -	int plane = intel_crtc->plane;
> >  
> >  	drm_vblank_on(dev, pipe);
> >  
> > -	intel_enable_primary_hw_plane(dev_priv, plane, pipe);
> > +	intel_enable_primary_hw_plane(crtc->primary, crtc);
> >  	intel_enable_planes(crtc);
> >  	/* The fixup needs to happen before cursor is enabled */
> >  	if (IS_G4X(dev))
> > @@ -3993,7 +3980,7 @@ static void intel_crtc_disable_planes(struct drm_crtc *crtc)
> >  	intel_crtc_dpms_overlay(intel_crtc, false);
> >  	intel_crtc_update_cursor(crtc, false);
> >  	intel_disable_planes(crtc);
> > -	intel_disable_primary_hw_plane(dev_priv, plane, pipe);
> > +	intel_disable_primary_hw_plane(crtc->primary, crtc);
> >  
> >  	drm_vblank_off(dev, pipe);
> >  }
> > @@ -4026,9 +4013,6 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
> >  
> >  	ironlake_set_pipeconf(crtc);
> >  
> > -	dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
> > -					       crtc->x, crtc->y);
> > -
> >  	intel_crtc->active = true;
> >  
> >  	intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
> > @@ -4133,9 +4117,6 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
> >  
> >  	intel_set_pipe_csc(crtc);
> >  
> > -	dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
> > -					       crtc->x, crtc->y);
> > -
> >  	intel_crtc->active = true;
> >  
> >  	intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
> > @@ -4614,7 +4595,6 @@ static void valleyview_modeset_global_resources(struct drm_device *dev)
> >  static void valleyview_crtc_enable(struct drm_crtc *crtc)
> >  {
> >  	struct drm_device *dev = crtc->dev;
> > -	struct drm_i915_private *dev_priv = dev->dev_private;
> >  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> >  	struct intel_encoder *encoder;
> >  	int pipe = intel_crtc->pipe;
> > @@ -4634,9 +4614,6 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
> >  
> >  	i9xx_set_pipeconf(intel_crtc);
> >  
> > -	dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
> > -					       crtc->x, crtc->y);
> > -
> >  	intel_crtc->active = true;
> >  
> >  	intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
> > @@ -4686,7 +4663,6 @@ static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
> >  static void i9xx_crtc_enable(struct drm_crtc *crtc)
> >  {
> >  	struct drm_device *dev = crtc->dev;
> > -	struct drm_i915_private *dev_priv = dev->dev_private;
> >  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> >  	struct intel_encoder *encoder;
> >  	int pipe = intel_crtc->pipe;
> > @@ -4705,9 +4681,6 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
> >  
> >  	i9xx_set_pipeconf(intel_crtc);
> >  
> > -	dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
> > -					       crtc->x, crtc->y);
> > -
> >  	intel_crtc->active = true;
> >  
> >  	if (!IS_GEN2(dev))
> > @@ -10854,7 +10827,6 @@ static int intel_crtc_set_config(struct drm_mode_set *set)
> >  		ret = intel_set_mode(set->crtc, set->mode,
> >  				     set->x, set->y, set->fb);
> >  	} else if (config->fb_changed) {
> > -		struct drm_i915_private *dev_priv = dev->dev_private;
> >  		struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
> >  
> >  		intel_crtc_wait_for_pending_flips(set->crtc);
> > @@ -10868,8 +10840,7 @@ static int intel_crtc_set_config(struct drm_mode_set *set)
> >  		 */
> >  		if (!intel_crtc->primary_enabled && ret == 0) {
> >  			WARN_ON(!intel_crtc->active);
> > -			intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane,
> > -						      intel_crtc->pipe);
> > +			intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
> >  		}
> >  
> >  		/*
> > @@ -11024,9 +10995,6 @@ static void intel_shared_dpll_init(struct drm_device *dev)
> >  static int
> >  intel_primary_plane_disable(struct drm_plane *plane)
> >  {
> > -	struct drm_device *dev = plane->dev;
> > -	struct drm_i915_private *dev_priv = dev->dev_private;
> > -	struct intel_plane *intel_plane = to_intel_plane(plane);
> >  	struct intel_crtc *intel_crtc;
> >  
> >  	if (!plane->fb)
> > @@ -11049,8 +11017,7 @@ intel_primary_plane_disable(struct drm_plane *plane)
> >  		goto disable_unpin;
> >  
> >  	intel_crtc_wait_for_pending_flips(plane->crtc);
> > -	intel_disable_primary_hw_plane(dev_priv, intel_plane->plane,
> > -				       intel_plane->pipe);
> > +	intel_disable_primary_hw_plane(plane, plane->crtc);
> >  
> >  disable_unpin:
> >  	intel_unpin_fb_obj(to_intel_framebuffer(plane->fb)->obj);
> > @@ -11067,9 +11034,7 @@ intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
> >  			     uint32_t src_w, uint32_t src_h)
> >  {
> >  	struct drm_device *dev = crtc->dev;
> > -	struct drm_i915_private *dev_priv = dev->dev_private;
> >  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > -	struct intel_plane *intel_plane = to_intel_plane(plane);
> >  	struct drm_rect dest = {
> >  		/* integer pixels */
> >  		.x1 = crtc_x,
> > @@ -11143,9 +11108,7 @@ intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
> >  		}
> >  
> >  		if (intel_crtc->primary_enabled)
> > -			intel_disable_primary_hw_plane(dev_priv,
> > -						       intel_plane->plane,
> > -						       intel_plane->pipe);
> > +			intel_disable_primary_hw_plane(plane, crtc);
> >  
> >  
> >  		if (plane->fb != fb)
> > @@ -11160,8 +11123,7 @@ intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
> >  		return ret;
> >  
> >  	if (!intel_crtc->primary_enabled)
> > -		intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane,
> > -					      intel_crtc->pipe);
> > +		intel_enable_primary_hw_plane(plane, crtc);
> >  
> >  	return 0;
> >  }
> > -- 
> > 1.8.5.5
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Matt Roper
> Graphics Software Engineer
> IoTG Platform Enabling & Development
> Intel Corporation
> (916) 356-2795

-- 
Ville Syrjälä
Intel OTC

[PATCH v2 14/15] drm/i915: Call .update_primary_plane in intel_{enable, disable}_primary_hw_plane()

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Make the intel_{enable,disable}_primary_hw_plane() simply call
.update_primary_plane(), thus eliminating the rmw from these functions
which should help the poor old 830M.

Now we can also remove the .update_primary_plane() from the
.crtc_enable() hooks because we end up calling it via
intel_crtc_enable_planes()->intel_enable_primary_hw_plane().

This also has the nice benefit of making primary planes a bit closer to
the way we handle sprite planes during modesets.

v2: Just write 0 to DSPCNTR and DSPSURF/DSPADDR if the plane is (to be)
    disabled. Quicker, and more importantly avoids an oops when fb==NULL
    due to BIOS fb takeover failure.
    Pimp the commit message a bit (Matt)

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 107 ++++++++++++++---------------------
 1 file changed, 42 insertions(+), 65 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e14e71b..5d652da 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2147,63 +2147,51 @@ void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
 
 /**
  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
- * @dev_priv: i915 private structure
- * @plane: plane to enable
- * @pipe: pipe being fed
+ * @plane:  plane to be enabled
+ * @crtc: crtc for the plane
  *
- * Enable @plane on @pipe, making sure that @pipe is running first.
+ * Enable @plane on @crtc, making sure that the pipe is running first.
  */
-static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
-					  enum plane plane, enum pipe pipe)
+static void intel_enable_primary_hw_plane(struct drm_plane *plane,
+					  struct drm_crtc *crtc)
 {
-	struct intel_crtc *intel_crtc =
-		to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
-	int reg;
-	u32 val;
+	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 
 	/* If the pipe isn't enabled, we can't pump pixels and may hang */
-	assert_pipe_enabled(dev_priv, pipe);
+	assert_pipe_enabled(dev_priv, intel_crtc->pipe);
 
 	if (intel_crtc->primary_enabled)
 		return;
 
 	intel_crtc->primary_enabled = true;
 
-	reg = DSPCNTR(plane);
-	val = I915_READ(reg);
-	WARN_ON(val & DISPLAY_PLANE_ENABLE);
-
-	I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
-	intel_flush_primary_plane(dev_priv, plane);
+	dev_priv->display.update_primary_plane(crtc, plane->fb,
+					       crtc->x, crtc->y);
 }
 
 /**
  * intel_disable_primary_hw_plane - disable the primary hardware plane
- * @dev_priv: i915 private structure
- * @plane: plane to disable
- * @pipe: pipe consuming the data
+ * @plane: plane to be disabled
+ * @crtc: crtc for the plane
  *
- * Disable @plane; should be an independent operation.
+ * Disable @plane on @crtc, making sure that the pipe is running first.
  */
-static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv,
-					   enum plane plane, enum pipe pipe)
+static void intel_disable_primary_hw_plane(struct drm_plane *plane,
+					   struct drm_crtc *crtc)
 {
-	struct intel_crtc *intel_crtc =
-		to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
-	int reg;
-	u32 val;
+	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+
+	assert_pipe_enabled(dev_priv, intel_crtc->pipe);
 
 	if (!intel_crtc->primary_enabled)
 		return;
 
 	intel_crtc->primary_enabled = false;
 
-	reg = DSPCNTR(plane);
-	val = I915_READ(reg);
-	WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0);
-
-	I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
-	intel_flush_primary_plane(dev_priv, plane);
+	dev_priv->display.update_primary_plane(crtc, plane->fb,
+					       crtc->x, crtc->y);
 }
 
 static bool need_vtd_wa(struct drm_device *dev)
@@ -2438,6 +2426,15 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
 	u32 dspcntr;
 	u32 reg = DSPCNTR(plane);
 
+	if (!intel_crtc->primary_enabled) {
+		I915_WRITE(reg, 0);
+		if (INTEL_INFO(dev)->gen >= 4)
+			I915_WRITE(DSPSURF(plane), 0);
+		else
+			I915_WRITE(DSPADDR(plane), 0);
+		return;
+	}
+
 	intel_fb = to_intel_framebuffer(fb);
 	obj = intel_fb->obj;
 
@@ -2539,6 +2536,12 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
 	u32 dspcntr;
 	u32 reg = DSPCNTR(plane);
 
+	if (!intel_crtc->primary_enabled) {
+		I915_WRITE(reg, 0);
+		I915_WRITE(DSPSURF(plane), 0);
+		return;
+	}
+
 	intel_fb = to_intel_framebuffer(fb);
 	obj = intel_fb->obj;
 
@@ -3961,11 +3964,10 @@ static void intel_crtc_enable_planes(struct drm_crtc *crtc)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	int pipe = intel_crtc->pipe;
-	int plane = intel_crtc->plane;
 
 	drm_vblank_on(dev, pipe);
 
-	intel_enable_primary_hw_plane(dev_priv, plane, pipe);
+	intel_enable_primary_hw_plane(crtc->primary, crtc);
 	intel_enable_planes(crtc);
 	/* The fixup needs to happen before cursor is enabled */
 	if (IS_G4X(dev))
@@ -3999,7 +4001,7 @@ static void intel_crtc_disable_planes(struct drm_crtc *crtc)
 	intel_crtc_dpms_overlay(intel_crtc, false);
 	intel_crtc_update_cursor(crtc, false);
 	intel_disable_planes(crtc);
-	intel_disable_primary_hw_plane(dev_priv, plane, pipe);
+	intel_disable_primary_hw_plane(crtc->primary, crtc);
 
 	drm_vblank_off(dev, pipe);
 }
@@ -4032,9 +4034,6 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
 
 	ironlake_set_pipeconf(crtc);
 
-	dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
-					       crtc->x, crtc->y);
-
 	intel_crtc->active = true;
 
 	intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
@@ -4139,9 +4138,6 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
 
 	intel_set_pipe_csc(crtc);
 
-	dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
-					       crtc->x, crtc->y);
-
 	intel_crtc->active = true;
 
 	intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
@@ -4620,7 +4616,6 @@ static void valleyview_modeset_global_resources(struct drm_device *dev)
 static void valleyview_crtc_enable(struct drm_crtc *crtc)
 {
 	struct drm_device *dev = crtc->dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	struct intel_encoder *encoder;
 	int pipe = intel_crtc->pipe;
@@ -4640,9 +4635,6 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
 
 	i9xx_set_pipeconf(intel_crtc);
 
-	dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
-					       crtc->x, crtc->y);
-
 	intel_crtc->active = true;
 
 	intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
@@ -4692,7 +4684,6 @@ static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
 static void i9xx_crtc_enable(struct drm_crtc *crtc)
 {
 	struct drm_device *dev = crtc->dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	struct intel_encoder *encoder;
 	int pipe = intel_crtc->pipe;
@@ -4711,9 +4702,6 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
 
 	i9xx_set_pipeconf(intel_crtc);
 
-	dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
-					       crtc->x, crtc->y);
-
 	intel_crtc->active = true;
 
 	if (!IS_GEN2(dev))
@@ -10860,7 +10848,6 @@ static int intel_crtc_set_config(struct drm_mode_set *set)
 		ret = intel_set_mode(set->crtc, set->mode,
 				     set->x, set->y, set->fb);
 	} else if (config->fb_changed) {
-		struct drm_i915_private *dev_priv = dev->dev_private;
 		struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
 
 		intel_crtc_wait_for_pending_flips(set->crtc);
@@ -10874,8 +10861,7 @@ static int intel_crtc_set_config(struct drm_mode_set *set)
 		 */
 		if (!intel_crtc->primary_enabled && ret == 0) {
 			WARN_ON(!intel_crtc->active);
-			intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane,
-						      intel_crtc->pipe);
+			intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
 		}
 
 		/*
@@ -11030,9 +11016,6 @@ static void intel_shared_dpll_init(struct drm_device *dev)
 static int
 intel_primary_plane_disable(struct drm_plane *plane)
 {
-	struct drm_device *dev = plane->dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_plane *intel_plane = to_intel_plane(plane);
 	struct intel_crtc *intel_crtc;
 
 	if (!plane->fb)
@@ -11055,8 +11038,7 @@ intel_primary_plane_disable(struct drm_plane *plane)
 		goto disable_unpin;
 
 	intel_crtc_wait_for_pending_flips(plane->crtc);
-	intel_disable_primary_hw_plane(dev_priv, intel_plane->plane,
-				       intel_plane->pipe);
+	intel_disable_primary_hw_plane(plane, plane->crtc);
 
 disable_unpin:
 	intel_unpin_fb_obj(to_intel_framebuffer(plane->fb)->obj);
@@ -11073,9 +11055,7 @@ intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
 			     uint32_t src_w, uint32_t src_h)
 {
 	struct drm_device *dev = crtc->dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	struct intel_plane *intel_plane = to_intel_plane(plane);
 	struct drm_rect dest = {
 		/* integer pixels */
 		.x1 = crtc_x,
@@ -11149,9 +11129,7 @@ intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
 		}
 
 		if (intel_crtc->primary_enabled)
-			intel_disable_primary_hw_plane(dev_priv,
-						       intel_plane->plane,
-						       intel_plane->pipe);
+			intel_disable_primary_hw_plane(plane, crtc);
 
 
 		if (plane->fb != fb)
@@ -11166,8 +11144,7 @@ intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
 		return ret;
 
 	if (!intel_crtc->primary_enabled)
-		intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane,
-					      intel_crtc->pipe);
+		intel_enable_primary_hw_plane(plane, crtc);
 
 	return 0;
 }
-- 
1.8.5.5

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[PATCH 15/15] drm/i915: Check pixel clock in ns2501 mode_valid hook

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The vbt on my Fujitsu-Siemens Lifebook S6010 provides two 800x600 modes,
60Hz and 56Hz. The magic register values we have correspond to the 60Hz
mode, and as I don't know how one would trick the VGA BIOS to set up
the 56Hz mode we can't get the magic values for the orther mode. So
when checking whether a mode is valid also check the pixel clock so that
we filter out the 56Hz variant.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/dvo_ns2501.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/dvo_ns2501.c b/drivers/gpu/drm/i915/dvo_ns2501.c
index b278571..64103cb 100644
--- a/drivers/gpu/drm/i915/dvo_ns2501.c
+++ b/drivers/gpu/drm/i915/dvo_ns2501.c
@@ -515,9 +515,9 @@ static enum drm_mode_status ns2501_mode_valid(struct intel_dvo_device *dvo,
 	 * of the panel in here so we could always accept it
 	 * by disabling the scaler.
 	 */
-	if ((mode->hdisplay == 800 && mode->vdisplay == 600) ||
-	    (mode->hdisplay == 640 && mode->vdisplay == 480) ||
-	    (mode->hdisplay == 1024 && mode->vdisplay == 768)) {
+	if ((mode->hdisplay == 640 && mode->vdisplay == 480 && mode->clock == 25175) ||
+	    (mode->hdisplay == 800 && mode->vdisplay == 600 && mode->clock == 40000) ||
+	    (mode->hdisplay == 1024 && mode->vdisplay == 768 && mode->clock == 65000)) {
 		return MODE_OK;
 	} else {
 		return MODE_ONE_SIZE;	/* Is this a reasonable error? */
-- 
1.8.5.5

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[PATCH 16/15] drm/i915: Pass intel_crtc to intel_disable_pipe() and intel_wait_for_pipe_off()

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Just pass the intel_crtc around instead of dev_priv+pipe.

Also make intel_wait_for_pipe_off() static since it's only used in
intel_display.c.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 37 +++++++++++++++++-------------------
 drivers/gpu/drm/i915/intel_drv.h     |  1 -
 2 files changed, 17 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 246e21e..fdda2cf 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -950,8 +950,7 @@ static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 
 /*
  * intel_wait_for_pipe_off - wait for pipe to turn off
- * @dev: drm device
- * @pipe: pipe to wait for
+ * @crtc: crtc whose pipe to wait for
  *
  * After disabling a pipe, we can't wait for vblank in the usual way,
  * spinning on the vblank interrupt status bit, since we won't actually
@@ -965,11 +964,12 @@ static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
  *   ends up stopping at the start of the next frame).
  *
  */
-void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
+static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
 {
+	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
-								      pipe);
+	enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
+	enum pipe pipe = crtc->pipe;
 
 	if (INTEL_INFO(dev)->gen >= 4) {
 		int reg = PIPECONF(cpu_transcoder);
@@ -2091,21 +2091,19 @@ static void intel_enable_pipe(struct intel_crtc *crtc)
 
 /**
  * intel_disable_pipe - disable a pipe, asserting requirements
- * @dev_priv: i915 private structure
- * @pipe: pipe to disable
+ * @crtc: crtc whose pipes is to be disabled
  *
- * Disable @pipe, making sure that various hardware specific requirements
- * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
- *
- * @pipe should be %PIPE_A or %PIPE_B.
+ * Disable the pipe of @crtc, making sure that various hardware
+ * specific requirements are met, if applicable, e.g. plane
+ * disabled, panel fitter off, etc.
  *
  * Will wait until the pipe has shut down before returning.
  */
-static void intel_disable_pipe(struct drm_i915_private *dev_priv,
-			       enum pipe pipe)
+static void intel_disable_pipe(struct intel_crtc *crtc)
 {
-	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
-								      pipe);
+	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
+	enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
+	enum pipe pipe = crtc->pipe;
 	int reg;
 	u32 val;
 
@@ -2128,7 +2126,7 @@ static void intel_disable_pipe(struct drm_i915_private *dev_priv,
 		return;
 
 	I915_WRITE(reg, val & ~PIPECONF_ENABLE);
-	intel_wait_for_pipe_off(dev_priv->dev, pipe);
+	intel_wait_for_pipe_off(crtc);
 }
 
 /*
@@ -4216,7 +4214,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
 	if (intel_crtc->config.has_pch_encoder)
 		intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
 
-	intel_disable_pipe(dev_priv, pipe);
+	intel_disable_pipe(intel_crtc);
 
 	ironlake_pfit_disable(intel_crtc);
 
@@ -4266,7 +4264,6 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	struct intel_encoder *encoder;
-	int pipe = intel_crtc->pipe;
 	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
 
 	if (!intel_crtc->active)
@@ -4281,7 +4278,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
 
 	if (intel_crtc->config.has_pch_encoder)
 		intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
-	intel_disable_pipe(dev_priv, pipe);
+	intel_disable_pipe(intel_crtc);
 
 	intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
 
@@ -4786,7 +4783,7 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
 	if (IS_GEN2(dev))
 		intel_wait_for_vblank(dev, pipe);
 
-	intel_disable_pipe(dev_priv, pipe);
+	intel_disable_pipe(intel_crtc);
 
 	i9xx_pfit_disable(intel_crtc);
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 78d4124..24bb131 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -741,7 +741,6 @@ int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 					     enum pipe pipe);
 void intel_wait_for_vblank(struct drm_device *dev, int pipe);
-void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
 			 struct intel_digital_port *dport);
-- 
1.8.5.5

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[PATCH 17/15] drm/i915: Disable double wide even when leaving the pipe on

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Disable double wide even if the pipe quirk compels us to leave the
pipe running. Double wide has certain implications for the plane
assignments so best keep it off.

Also helps resuming from S3 on the Fujitsu-Siemens Lifebook S6010
when double wide was enabled prior to suspend.

We do leave the pixel clock ticking at the original rate which would
require double wide to be enabled. But since the planes are all disabled
I'm hoping that the overly fast clock won't cause any problems. Seems
to be fine so far.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index fdda2cf..4004605 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2115,12 +2115,22 @@ static void intel_disable_pipe(struct intel_crtc *crtc)
 	assert_cursor_disabled(dev_priv, pipe);
 	assert_sprites_disabled(dev_priv, pipe);
 
+	reg = PIPECONF(cpu_transcoder);
+
 	/* Don't disable pipe or pipe PLLs if needed */
 	if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
-	    (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
+	    (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) {
+		/*
+		 * Double wide has implications for planes
+		 * so best keep it disabled when not needed.
+		 */
+		if (crtc->config.double_wide) {
+			I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_DOUBLE_WIDE);
+			POSTING_READ(reg);
+		}
 		return;
+	}
 
-	reg = PIPECONF(cpu_transcoder);
 	val = I915_READ(reg);
 	if ((val & PIPECONF_ENABLE) == 0)
 		return;
-- 
1.8.5.5

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[PATCH v2 17/15] drm/i915: Disable double wide even when leaving the pipe on

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Disable double wide even if the pipe quirk compels us to leave the
pipe running. Double wide has certain implications for the plane
assignments so best keep it off.

Also helps resuming from S3 on the Fujitsu-Siemens Lifebook S6010
when double wide was enabled prior to suspend.

We do leave the pixel clock ticking at the original rate which would
require double wide to be enabled. But since the planes are all disabled
I'm hoping that the overly fast clock won't cause any problems. Seems
to be fine so far.

v2: Disable double wide also when turning the pipe off

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 22 +++++++++++++++-------
 1 file changed, 15 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 1353744..034f7ce 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2115,18 +2115,26 @@ static void intel_disable_pipe(struct intel_crtc *crtc)
 	assert_cursor_disabled(dev_priv, pipe);
 	assert_sprites_disabled(dev_priv, pipe);
 
-	/* Don't disable pipe or pipe PLLs if needed */
-	if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
-	    (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
-		return;
-
 	reg = PIPECONF(cpu_transcoder);
 	val = I915_READ(reg);
 	if ((val & PIPECONF_ENABLE) == 0)
 		return;
 
-	I915_WRITE(reg, val & ~PIPECONF_ENABLE);
-	intel_wait_for_pipe_off(crtc);
+	/*
+	 * Double wide has implications for planes
+	 * so best keep it disabled when not needed.
+	 */
+	if (crtc->config.double_wide)
+		val &= ~PIPECONF_DOUBLE_WIDE;
+
+	/* Don't disable pipe or pipe PLLs if needed */
+	if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
+	    !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
+		val &= ~PIPECONF_ENABLE;
+
+	I915_WRITE(reg, val);
+	if ((val & PIPECONF_ENABLE) == 0)
+		intel_wait_for_pipe_off(crtc);
 }
 
 /*
-- 
1.8.5.5

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Deadlock in intel_enable_pipe_a()

[Thomas Richter]

Hi Ville, hi Daniel, dear intel experts,

just went through the problem I send around, and I guess I understand 
now what happens here. The reason *why* resume fails is that there is a 
deadlock situation in intel_display.c:

*) loading the module calls intel_modeset_init()
*) intel_modeset_init() calls intel_modeset_setup_hw_state(), but 
protects access to it with a global lock.
*) intel_modeset_setup_hw_state() calls intel_sanitize_crtc()
*) intel_sanitize_crtc() finds that the pipe-a quirk is enabled and 
calls intel_enable_pipe_a()
*) intel_enable_pipe_a() calls intel_release_load_detect_pipe(), however 
not using the same mutex context as the caller (intel_modeset_init()).
*) intel_release_load_detect_pipe() again gets the mutex of the crtc.

Unfortunately, at this time, the caller (intel_modeset_init()) had 
already everything locked.

Needless to say, this deadlocks and blocks the kernel completely, 
causing the problem I found above.

To verify my hypothesis, I removed the locks in 
intel_release_load_detect_pipe(), (obviously risking race conditions, 
but never mind for the test).

The result is that the machine is responsive after the resume. It still 
does not show a display (apparently, intel_sanitize_crtc() is 
insufficient and does not sanitize enough), but at least one can 
force-enable it again.

Thus, two bugs:

1) attempting to lock the same lock twice, nested, causing a deadlock. 
The pipe A quirk is not working correctly by requiring a call into a 
method that requires a lock that is already held.

2) not sanitizing the chipset sufficiently, still keeping the display 
black. (This, being, of course a side effect of the buggy bios).

Hope this helps!

Thomas

[PATCH] drm/i915: Avoid double mutex lock applying pipe A quirk during sanitize_crtc()

[Chris Wilson]

Thomas found that his machine would deadlock reloading the i915.ko
module after resume. He identified that this was caused by the
reacquisition of the connection mutex inside intel_enable_pipe_a()
during the CRTC sanitization routine. This will only affect machines
that quirk PIPE A, i.e. the original 830m chipsets.

This patch move the locking into a wrapper function so that
intel_enable_pipe_a() can bypass the locking knowing that it already
holds the correct locks.

Reported-by: Thomas Richter <richter@rus.uni-stuttgart.de>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Thomas Richter <richter@rus.uni-stuttgart.de>
Cc: Daniel Vetter <daniel@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |   54 ++++++++++++++++++++++------------
 1 file changed, 35 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c1f79a1..26d3424 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8387,9 +8387,10 @@ mode_fits_in_fbdev(struct drm_device *dev,
 #endif
 }
 
-bool intel_get_load_detect_pipe(struct drm_connector *connector,
-				struct drm_display_mode *mode,
-				struct intel_load_detect_pipe *old)
+static bool
+__intel_get_load_detect_pipe(struct drm_connector *connector,
+			     struct drm_display_mode *mode,
+			     struct intel_load_detect_pipe *old)
 {
 	struct intel_crtc *intel_crtc;
 	struct intel_encoder *intel_encoder =
@@ -8405,7 +8406,7 @@ bool intel_get_load_detect_pipe(struct drm_connector *connector,
 		      connector->base.id, connector->name,
 		      encoder->base.id, encoder->name);
 
-	mutex_lock(&dev->mode_config.connection_mutex);
+	lockdep_assert_held(&dev->mode_config.connection_mutex);
 
 	/*
 	 * Algorithm gets a little messy:
@@ -8449,7 +8450,7 @@ bool intel_get_load_detect_pipe(struct drm_connector *connector,
 	 */
 	if (!crtc) {
 		DRM_DEBUG_KMS("no pipe available for load-detect\n");
-		goto fail_unlock_connector;
+		return false;
 	}
 
 	mutex_lock(&crtc->mutex);
@@ -8503,14 +8504,13 @@ bool intel_get_load_detect_pipe(struct drm_connector *connector,
 	else
 		intel_crtc->new_config = NULL;
 	mutex_unlock(&crtc->mutex);
-fail_unlock_connector:
-	mutex_unlock(&dev->mode_config.connection_mutex);
 
 	return false;
 }
 
-void intel_release_load_detect_pipe(struct drm_connector *connector,
-				    struct intel_load_detect_pipe *old)
+static void
+__intel_release_load_detect_pipe(struct drm_connector *connector,
+				 struct intel_load_detect_pipe *old)
 {
 	struct intel_encoder *intel_encoder =
 		intel_attached_encoder(connector);
@@ -8518,6 +8518,8 @@ void intel_release_load_detect_pipe(struct drm_connector *connector,
 	struct drm_crtc *crtc = encoder->crtc;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 
+	lockdep_assert_held(&connector->dev->mode_config.connection_mutex);
+
 	DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
 		      connector->base.id, connector->name,
 		      encoder->base.id, encoder->name);
@@ -8533,17 +8535,32 @@ void intel_release_load_detect_pipe(struct drm_connector *connector,
 			drm_framebuffer_unregister_private(old->release_fb);
 			drm_framebuffer_unreference(old->release_fb);
 		}
+	} else {
+		/* Switch crtc and encoder back off if necessary */
+		if (old->dpms_mode != DRM_MODE_DPMS_ON)
+			connector->funcs->dpms(connector, old->dpms_mode);
+	}
+	mutex_unlock(&crtc->mutex);
+}
 
-		mutex_unlock(&crtc->mutex);
+bool intel_get_load_detect_pipe(struct drm_connector *connector,
+				struct drm_display_mode *mode,
+				struct intel_load_detect_pipe *old)
+{
+	mutex_lock(&connector->dev->mode_config.connection_mutex);
+	if (!__intel_get_load_detect_pipe(connector, mode, old)) {
 		mutex_unlock(&connector->dev->mode_config.connection_mutex);
-		return;
+		return false;
 	}
 
-	/* Switch crtc and encoder back off if necessary */
-	if (old->dpms_mode != DRM_MODE_DPMS_ON)
-		connector->funcs->dpms(connector, old->dpms_mode);
+	/* lock will be released by intel_release_load_detect_pipe() */
+	return true;
+}
 
-	mutex_unlock(&crtc->mutex);
+void intel_release_load_detect_pipe(struct drm_connector *connector,
+				    struct intel_load_detect_pipe *old)
+{
+	__intel_release_load_detect_pipe(connector, old);
 	mutex_unlock(&connector->dev->mode_config.connection_mutex);
 }
 
@@ -12354,10 +12371,9 @@ static void intel_enable_pipe_a(struct drm_device *dev)
 	if (!crt)
 		return;
 
-	if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
-		intel_release_load_detect_pipe(crt, &load_detect_temp);
-
-
+	lockdep_assert_held(&dev->mode_config.connection_mutex);
+	if (__intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
+		__intel_release_load_detect_pipe(crt, &load_detect_temp);
 }
 
 static bool
-- 
1.7.9.5

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Re: [PATCH] drm/i915: Avoid double mutex lock applying pipe A quirk during sanitize_crtc()

[Ville Syrjälä]

On Mon, Jun 09, 2014 at 07:47:10AM +0100, Chris Wilson wrote:
> Thomas found that his machine would deadlock reloading the i915.ko
> module after resume. He identified that this was caused by the
> reacquisition of the connection mutex inside intel_enable_pipe_a()
> during the CRTC sanitization routine. This will only affect machines
> that quirk PIPE A, i.e. the original 830m chipsets.
> 
> This patch move the locking into a wrapper function so that
> intel_enable_pipe_a() can bypass the locking knowing that it already
> holds the correct locks.

It can still try to grab crtc->mutex twice. Looks like Danial undid my
fix to not take all the modeset locks around
intel_modeset_setup_hw_state().

> 
> Reported-by: Thomas Richter <richter@rus.uni-stuttgart.de>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Thomas Richter <richter@rus.uni-stuttgart.de>
> Cc: Daniel Vetter <daniel@ffwll.ch>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c |   54 ++++++++++++++++++++++------------
>  1 file changed, 35 insertions(+), 19 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index c1f79a1..26d3424 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -8387,9 +8387,10 @@ mode_fits_in_fbdev(struct drm_device *dev,
>  #endif
>  }
>  
> -bool intel_get_load_detect_pipe(struct drm_connector *connector,
> -				struct drm_display_mode *mode,
> -				struct intel_load_detect_pipe *old)
> +static bool
> +__intel_get_load_detect_pipe(struct drm_connector *connector,
> +			     struct drm_display_mode *mode,
> +			     struct intel_load_detect_pipe *old)
>  {
>  	struct intel_crtc *intel_crtc;
>  	struct intel_encoder *intel_encoder =
> @@ -8405,7 +8406,7 @@ bool intel_get_load_detect_pipe(struct drm_connector *connector,
>  		      connector->base.id, connector->name,
>  		      encoder->base.id, encoder->name);
>  
> -	mutex_lock(&dev->mode_config.connection_mutex);
> +	lockdep_assert_held(&dev->mode_config.connection_mutex);
>  
>  	/*
>  	 * Algorithm gets a little messy:
> @@ -8449,7 +8450,7 @@ bool intel_get_load_detect_pipe(struct drm_connector *connector,
>  	 */
>  	if (!crtc) {
>  		DRM_DEBUG_KMS("no pipe available for load-detect\n");
> -		goto fail_unlock_connector;
> +		return false;
>  	}
>  
>  	mutex_lock(&crtc->mutex);
> @@ -8503,14 +8504,13 @@ bool intel_get_load_detect_pipe(struct drm_connector *connector,
>  	else
>  		intel_crtc->new_config = NULL;
>  	mutex_unlock(&crtc->mutex);
> -fail_unlock_connector:
> -	mutex_unlock(&dev->mode_config.connection_mutex);
>  
>  	return false;
>  }
>  
> -void intel_release_load_detect_pipe(struct drm_connector *connector,
> -				    struct intel_load_detect_pipe *old)
> +static void
> +__intel_release_load_detect_pipe(struct drm_connector *connector,
> +				 struct intel_load_detect_pipe *old)
>  {
>  	struct intel_encoder *intel_encoder =
>  		intel_attached_encoder(connector);
> @@ -8518,6 +8518,8 @@ void intel_release_load_detect_pipe(struct drm_connector *connector,
>  	struct drm_crtc *crtc = encoder->crtc;
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>  
> +	lockdep_assert_held(&connector->dev->mode_config.connection_mutex);
> +
>  	DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
>  		      connector->base.id, connector->name,
>  		      encoder->base.id, encoder->name);
> @@ -8533,17 +8535,32 @@ void intel_release_load_detect_pipe(struct drm_connector *connector,
>  			drm_framebuffer_unregister_private(old->release_fb);
>  			drm_framebuffer_unreference(old->release_fb);
>  		}
> +	} else {
> +		/* Switch crtc and encoder back off if necessary */
> +		if (old->dpms_mode != DRM_MODE_DPMS_ON)
> +			connector->funcs->dpms(connector, old->dpms_mode);
> +	}
> +	mutex_unlock(&crtc->mutex);
> +}
>  
> -		mutex_unlock(&crtc->mutex);
> +bool intel_get_load_detect_pipe(struct drm_connector *connector,
> +				struct drm_display_mode *mode,
> +				struct intel_load_detect_pipe *old)
> +{
> +	mutex_lock(&connector->dev->mode_config.connection_mutex);
> +	if (!__intel_get_load_detect_pipe(connector, mode, old)) {
>  		mutex_unlock(&connector->dev->mode_config.connection_mutex);
> -		return;
> +		return false;
>  	}
>  
> -	/* Switch crtc and encoder back off if necessary */
> -	if (old->dpms_mode != DRM_MODE_DPMS_ON)
> -		connector->funcs->dpms(connector, old->dpms_mode);
> +	/* lock will be released by intel_release_load_detect_pipe() */
> +	return true;
> +}
>  
> -	mutex_unlock(&crtc->mutex);
> +void intel_release_load_detect_pipe(struct drm_connector *connector,
> +				    struct intel_load_detect_pipe *old)
> +{
> +	__intel_release_load_detect_pipe(connector, old);
>  	mutex_unlock(&connector->dev->mode_config.connection_mutex);
>  }
>  
> @@ -12354,10 +12371,9 @@ static void intel_enable_pipe_a(struct drm_device *dev)
>  	if (!crt)
>  		return;
>  
> -	if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
> -		intel_release_load_detect_pipe(crt, &load_detect_temp);
> -
> -
> +	lockdep_assert_held(&dev->mode_config.connection_mutex);
> +	if (__intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
> +		__intel_release_load_detect_pipe(crt, &load_detect_temp);
>  }
>  
>  static bool
> -- 
> 1.7.9.5

-- 
Ville Syrjälä
Intel OTC

Re: [PATCH] drm/i915: Avoid double mutex lock applying pipe A quirk during sanitize_crtc()

[Chris Wilson]

On Mon, Jun 09, 2014 at 11:30:26AM +0300, Ville Syrjälä wrote:
> On Mon, Jun 09, 2014 at 07:47:10AM +0100, Chris Wilson wrote:
> > Thomas found that his machine would deadlock reloading the i915.ko
> > module after resume. He identified that this was caused by the
> > reacquisition of the connection mutex inside intel_enable_pipe_a()
> > during the CRTC sanitization routine. This will only affect machines
> > that quirk PIPE A, i.e. the original 830m chipsets.
> > 
> > This patch move the locking into a wrapper function so that
> > intel_enable_pipe_a() can bypass the locking knowing that it already
> > holds the correct locks.
> 
> It can still try to grab crtc->mutex twice. Looks like Danial undid my
> fix to not take all the modeset locks around
> intel_modeset_setup_hw_state().

Oh well, I only considered the santize_crtc path as I thought we would
have caught the modeset sequence deadlocking earlier.

Anyway, the locking is in flux due to the conversion to ww_mutex.
Have fun ;-)
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

Partial success - Fixing resume from s2ram on S6010

[Thomas Richter]

[-- Attachment #1: Type: text/plain, Size: 1908 bytes --]

Hi Ville, dear intel experts,

without the deadlock in i915, I had at least a partial success in 
restoring the video on the Fujitsu S6010.
Apparently, the bios does not re-initialize the 830MG registers, nor the 
registers of the ns2501 DVO.
Instead, the 830MG is configured in a 640x480 mode (no matter what the 
suspend mode was) and
the DVO is configured in a DPMS off state (no matter what the mode was 
before the suspend).

The attached script, to be placed in /etc/pm/sleep.d/99video will force 
correct values back into the registers
and thus restore the display. Partially. Trouble still is that the 
restored screen has some type of "hick-up" by
moving left or right by a couple of pixels (probably exactly by one 
tile, I did not measure). Interestingly,
a dump of the DVO and 830MG registers did not reveal any significant 
difference before and after the restore,
so it is still unclear why that hick-up appears.

Anyhow - it seems that $OTHER_OS has a completely different strategy for 
resume than Linux. $OTHER_OS seems
to simply re-load the video registers for the currently active mode, 
ignoring the current state of the hardware.
The i915 kernel module instead seems to try to interpret the current 
register set to a video mode, and then
restores its state from the state of the hardware. It seems to me that 
this is a less than ideal approach, and
it would be better keep a copy of the registers how they should be 
during suspend, and restore them in
the kernel module to the correct video mode on resume, ignoring whatever 
the bios left there.

Do kernel modules like the i915 or the dvo_ns2501 offer some kind of 
hook that is called by the kernel when
the machine is suspended and resumed? If so, this would be extremely 
helpful and would allow a much safer
suspend/resume operation than currently possible with the mode-detect 
guess i915 attempts to do.

Thanks,
     Thomas


[-- Attachment #2: 99video --]
[-- Type: text/plain, Size: 1846 bytes --]

#!/bin/sh
#
PATH="/root/bin/:$PATH"

suspend_video()
{	
    chvt 1
    sleep 0.5
}

restore_video()
{
intel_reg_write 0x2120 0
intel_reg_write 0x61140 0x90004084
intel_reg_write 0x61100 0xC18
intel_reg_write 0x70180 0xd8000000
intel_reg_write 0x70188 0x2000
intel_reg_write 0x70190 0x02ff03ff
intel_reg_write 0x6001c 0x03ff02ff
intel_reg_write 0x70024 0x10000207
intel_reg_write 0x06040 0x0004150d
intel_reg_write 0x06044 0x0004150d
intel_reg_write 0x6014 0xd0820000
intel_reg_write 0x60000 0x053f03ff
intel_reg_write 0x60004 0x053f03ff
intel_reg_write 0x60008 0x049f0417
intel_reg_write 0x6000c 0x032502ff
intel_reg_write 0x60010 0x032502ff
intel_reg_write 0x60014 0x03080302
intel_reg_write 0x71180 0x01000000
intel_reg_write 0x71008 0x80000000
intel_reg_write 0x6101c 0x027f01df
intel_reg_write 0x71024 0x90000206
intel_reg_write 0x06018 0xc08b0000
intel_reg_write 0x61000 0x031f027f
intel_reg_write 0x61004 0x03170287
intel_reg_write 0x61008 0x02ef028f
intel_reg_write 0x6100c 0x020c01df
intel_reg_write 0x61010 0x020401e7
intel_reg_write 0x61014 0x01eb01e9
intel_reg_write 0x2000 0x00400131
intel_reg_write 0x2004 0x05000561
intel_reg_write 0x200c 0x02000561
intel_reg_write 0x2010 0x0

modprobe i2c-hid
modprobe i2c-algo-bit
modprobe i2c-dev
modprobe i2c-scmi
modprobe i2c-i801
modprobe i2c-ismt
modprobe i2c-gpio
modprobe i2c-piix4
modprobe i2c-isch
modprobe i2c-mux
modprobe i2c-core

i2cset -y 5 0x38 8 0x35
i2cset -y 5 0x38 0x34 0x03
i2cset -y 5 0x38 0x35 0xff
i2cset -y 5 0x38 0x37 0x44
i2cset -y 5 0x38 0x40 0x80
i2cset -y 5 0x38 0x41 0x00
i2cset -y 5 0x38 0xb7 0x03
i2cset -y 5 0x38 0xc0 0x01
i2cset -y 5 0x38 0xf0 0xca
i2cset -y 5 0x38 0xf1 0x00
i2cset -y 5 0x38 0xf2 0x11

chvt 7
}

case "$1" in
        suspend) suspend_video;;
        hibernate) suspend_video;;
        resume) restore_video;;
        thaw) restore_video;;
esac

[-- Attachment #3: Type: text/plain, Size: 159 bytes --]

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Re: Partial success - Fixing resume from s2ram on S6010

[Ville Syrjälä]

On Mon, Jun 09, 2014 at 12:57:46PM +0200, Thomas Richter wrote:
> Hi Ville, dear intel experts,
> 
> without the deadlock in i915, I had at least a partial success in 
> restoring the video on the Fujitsu S6010.
> Apparently, the bios does not re-initialize the 830MG registers, nor the 
> registers of the ns2501 DVO.
> Instead, the 830MG is configured in a 640x480 mode (no matter what the 
> suspend mode was) and
> the DVO is configured in a DPMS off state (no matter what the mode was 
> before the suspend).
> 
> The attached script, to be placed in /etc/pm/sleep.d/99video will force 
> correct values back into the registers
> and thus restore the display. Partially. Trouble still is that the 
> restored screen has some type of "hick-up" by
> moving left or right by a couple of pixels (probably exactly by one 
> tile, I did not measure). Interestingly,
> a dump of the DVO and 830MG registers did not reveal any significant 
> difference before and after the restore,
> so it is still unclear why that hick-up appears.
> 
> Anyhow - it seems that $OTHER_OS has a completely different strategy for 
> resume than Linux. $OTHER_OS seems
> to simply re-load the video registers for the currently active mode, 
> ignoring the current state of the hardware.
> The i915 kernel module instead seems to try to interpret the current 
> register set to a video mode, and then
> restores its state from the state of the hardware.

No, we do restore the mode you were using before suspend.

Are you still using vbetool? That would explain why things go bad since
vbetool will clobber whatever i915 already did.

-- 
Ville Syrjälä
Intel OTC

Re: Partial success - Fixing resume from s2ram on S6010

[Thomas Richter]

Am 09.06.2014 13:08, schrieb Ville Syrjälä
> No, we do restore the mode you were using before suspend.
>
> Are you still using vbetool? That would explain why things go bad since
> vbetool will clobber whatever i915 already did.

No, vbetool is out of the equation (see the script attached to the 
previous post). However, I dumped the 830MG register set
and the ns2501 DVO set before and after the suspend, and they are pretty 
different. As said, the 830 is configured
to use a 640x480 mode (instead of the 1024x786 mode) and the DVO is off.

Maybe the kernel tries to mode-detect the connected monitor, and this 
fails because the PLLs are not yet
configured correctly? Note that the ns2501 requires a correctly 
configured DVO to be able to respond on
the i2c bus. If so, mode-detection requires configuring the PLLs to 
*some* useful mode before attempting
to detect anything, otherwise the DVO just plays "dead".

Greetings,
     Thomas

Re: Partial success - Fixing resume from s2ram on S6010

[Ville Syrjälä]

On Mon, Jun 09, 2014 at 01:19:46PM +0200, Thomas Richter wrote:
> Am 09.06.2014 13:08, schrieb Ville Syrjälä
> > No, we do restore the mode you were using before suspend.
> >
> > Are you still using vbetool? That would explain why things go bad since
> > vbetool will clobber whatever i915 already did.
> 
> No, vbetool is out of the equation (see the script attached to the 
> previous post).

So now you're using acpi_sleep=s3_bios, or nothing?

> However, I dumped the 830MG register set
> and the ns2501 DVO set before and after the suspend, and they are pretty 
> different. As said, the 830 is configured
> to use a 640x480 mode (instead of the 1024x786 mode) and the DVO is off.
> 
> Maybe the kernel tries to mode-detect the connected monitor, and this 
> fails because the PLLs are not yet
> configured correctly? Note that the ns2501 requires a correctly 
> configured DVO to be able to respond on
> the i2c bus. If so, mode-detection requires configuring the PLLs to 
> *some* useful mode before attempting
> to detect anything, otherwise the DVO just plays "dead".

Boot with drm.debug=0xe grab the dmesg after the resume and let's see
if there is something fishy happening.

-- 
Ville Syrjälä
Intel OTC

Re: Partial success - Fixing resume from s2ram on S6010

[Thomas Richter]

Am 09.06.2014 13:31, schrieb Ville Syrjälä:
> So now you're using acpi_sleep=s3_bios, or nothing?

Tried with acpi_sleep=s3 and nothing, makes no difference.

> Boot with drm.debug=0xe grab the dmesg after the resume and let's see
> if there is something fishy happening.
>
Ok, here we go:

Note that the kernel finds that all outputs are disabled, then loads a 
640x480 mode. All pipes and crtcs are disabled, too.

Greetings,
     Thomas


[  162.972995] PM: noirq resume of devices complete after 15.796 msecs
Jun  9 14:20:23 tyleet kernel: [  162.974050] PM: early resume of 
devices complete after 0.353 msecs
Jun  9 14:20:23 tyleet kernel: [  163.019288] uhci_hcd 0000:00:1d.0: 
enabling bus mastering
Jun  9 14:20:23 tyleet kernel: [  163.019322] usb usb1: root hub lost 
power or was reset
Jun  9 14:20:23 tyleet kernel: [  163.019403] uhci_hcd 0000:00:1d.1: 
enabling bus mastering
Jun  9 14:20:23 tyleet kernel: [  163.019428] usb usb2: root hub lost 
power or was reset
Jun  9 14:20:23 tyleet kernel: [  163.019597] snd_intel8x0 0000:00:1f.5: 
enabling bus mastering
Jun  9 14:20:23 tyleet kernel: [  163.019645] 8139too 0000:01:09.0 eth0: 
link down
Jun  9 14:20:23 tyleet kernel: [  163.069296] sd 0:0:0:0: [sda] Starting 
disk
Jun  9 14:20:23 tyleet kernel: [  163.069428] 
[drm:i915_redisable_vga_power_on] Something enabled VGA plane, disabling it
Jun  9 14:20:23 tyleet kernel: [  163.069742] [drm:intel_opregion_setup] 
graphic opregion physical addr: 0x0
Jun  9 14:20:23 tyleet kernel: [  163.069745] [drm:intel_opregion_setup] 
ACPI OpRegion not supported!
Jun  9 14:20:23 tyleet kernel: [  163.070172] 
[drm:intel_modeset_readout_hw_state] [CRTC:5] hw state readout: disabled
Jun  9 14:20:23 tyleet kernel: [  163.070179] 
[drm:intel_modeset_readout_hw_state] [CRTC:7] hw state readout: disabled
Jun  9 14:20:23 tyleet kernel: [  163.070187] 
[drm:intel_modeset_readout_hw_state] [ENCODER:9:DAC-9] hw state readout: 
disabled, pipe A
Jun  9 14:20:23 tyleet kernel: [  163.070192] 
[drm:intel_modeset_readout_hw_state] [ENCODER:10:None-10] hw state 
readout: disabled, pipe A
Jun  9 14:20:23 tyleet kernel: [  163.070197] 
[drm:intel_modeset_readout_hw_state] [CONNECTOR:8:VGA-1] hw state 
readout: disabled
Jun  9 14:20:23 tyleet kernel: [  163.070202] 
[drm:intel_modeset_readout_hw_state] [CONNECTOR:11:DVI-I-1] hw state 
readout: disabled
Jun  9 14:20:23 tyleet kernel: [  163.070211] 
[drm:i915_get_vblank_timestamp] crtc 0 is disabled
Jun  9 14:20:23 tyleet kernel: [  163.070221] 
[drm:intel_get_load_detect_pipe] [CONNECTOR:8:VGA-1], [ENCODER:9:DAC-9]
Jun  9 14:20:23 tyleet kernel: [  163.070226] 
[drm:intel_get_load_detect_pipe] reusing fbdev for load-detection 
framebuffer
Jun  9 14:20:23 tyleet kernel: [  163.070233] 
[drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, 
prepare: 1, disable: 0
Jun  9 14:20:23 tyleet kernel: [  163.070242] 
[drm:connected_sink_compute_bpp] [CONNECTOR:8:VGA-1] checking for sink 
bpp constrains
Jun  9 14:20:23 tyleet kernel: [  163.070245] 
[drm:connected_sink_compute_bpp] [CONNECTOR:11:DVI-I-1] checking for 
sink bpp constrains
Jun  9 14:20:23 tyleet kernel: [  163.070254] 
[drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
Jun  9 14:20:23 tyleet kernel: [  163.070259] 
[drm:intel_dump_pipe_config] [CRTC:5][modeset] config for pipe A
Jun  9 14:20:23 tyleet kernel: [  163.070261] 
[drm:intel_dump_pipe_config] cpu_transcoder: A
Jun  9 14:20:23 tyleet kernel: [  163.070265] 
[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
Jun  9 14:20:23 tyleet kernel: [  163.070270] 
[drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, 
link_m: 0, link_n: 0, tu: 0
Jun  9 14:20:23 tyleet kernel: [  163.070275] 
[drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, 
link_n: 0, tu: 0
Jun  9 14:20:23 tyleet kernel: [  163.070277] 
[drm:intel_dump_pipe_config] requested mode:
Jun  9 14:20:23 tyleet kernel: [  163.070287] 
[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 31500 640 664 
704 832 480 489 491 520 0x10 0xa
Jun  9 14:20:23 tyleet kernel: [  163.070289] 
[drm:intel_dump_pipe_config] adjusted mode:
Jun  9 14:20:23 tyleet kernel: [  163.070298] 
[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 31500 640 664 
704 832 480 489 491 520 0x10 0xa
Jun  9 14:20:23 tyleet kernel: [  163.070305] 
[drm:intel_dump_crtc_timings] crtc timings: 31500 640 664 704 832 480 
489 491 520, type: 0x10 flags: 0xa
Jun  9 14:20:23 tyleet kernel: [  163.070308] 
[drm:intel_dump_pipe_config] port clock: 31500
Jun  9 14:20:23 tyleet kernel: [  163.070311] 
[drm:intel_dump_pipe_config] pipe src size: 640x480
Jun  9 14:20:23 tyleet kernel: [  163.070316] 
[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 
0x00000000, lvds border: 0x00000000
Jun  9 14:20:23 tyleet kernel: [  163.070320] 
[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 
0x00000000, disabled
Jun  9 14:20:23 tyleet kernel: [  163.070323] 
[drm:intel_dump_pipe_config] ips: 0
Jun  9 14:20:23 tyleet kernel: [  163.070325] 
[drm:intel_dump_pipe_config] double wide: 0
Jun  9 14:20:23 tyleet kernel: [  163.079041] ------------[ cut here 
]------------
Jun  9 14:20:23 tyleet kernel: [  163.079158] WARNING: CPU: 0 PID: 2976 
at drivers/gpu/drm/i915/intel_display.c:1255 assert_pipe+0xec/0x100 [i915]()
Jun  9 14:20:23 tyleet kernel: [  163.079161] pipe A assertion failure 
(expected on, current off)
Jun  9 14:20:23 tyleet kernel: [  163.079246] Modules linked in: 
michael_mic arc4 ecb lib80211_crypt_tkip lib80211_crypt_ccmp binfmt_misc 
fuse netconsole loop firewire_sbp2 hid_generic usbhid hid ipw2100 
snd_intel8x0 snd_ac97_codec sg libipw ac97_bus sr_mod cfg80211 snd_pcm 
mousedev cdrom snd_seq snd_seq_device snd_timer pcmcia uhci_hcd irda 
usbcore i915 rfkill yenta_socket snd firewire_ohci lpc_ich pcmcia_rsrc 
firewire_core apanel 8139too input_polldev evdev psmouse 8139cp mfd_core 
mii soundcore crc_itu_t lib80211 i2c_i801 i2c_algo_bit drm_kms_helper 
8250 drm pcspkr crc_ccitt pcmcia_core serial_core fujitsu_laptop 
i2c_core video intel_agp intel_gtt led_class usb_common agpgart ac 
battery button
Jun  9 14:20:23 tyleet kernel: [  163.079254] CPU: 0 PID: 2976 Comm: 
kworker/u2:11 Not tainted 3.15.0-rc7+ #8
Jun  9 14:20:23 tyleet kernel: [  163.079257] Hardware name: FUJITSU 
SIEMENS LIFEBOOK S Series/FJNB159, BIOS Version 1.07  10/28/2002
Jun  9 14:20:23 tyleet kernel: [  163.079275] Workqueue: events_unbound 
async_run_entry_fn
Jun  9 14:20:23 tyleet kernel: [  163.079287]  c131831e c103451f 
f8a6cb28 efb6dca0 00000ba0 f8a6b228 000004e7 f8a1d36c
Jun  9 14:20:23 tyleet kernel: [  163.079296]  f8a1d36c c0148001 
f5b78000 00000041 00070000 c10345e3 00000009 efb6dc88
Jun  9 14:20:23 tyleet kernel: [  163.079305]  f8a6cb28 efb6dca0 
f8a1d36c f8a6b228 000004e7 f8a6cb28 00000041 f8a74230
Jun  9 14:20:23 tyleet kernel: [  163.079307] Call Trace:
Jun  9 14:20:23 tyleet kernel: [  163.079318]  [<c131831e>] ? 
dump_stack+0xa/0x13
Jun  9 14:20:23 tyleet kernel: [  163.079328]  [<c103451f>] ? 
warn_slowpath_common+0x7f/0xb0
Jun  9 14:20:23 tyleet kernel: [  163.079376]  [<f8a1d36c>] ? 
assert_pipe+0xec/0x100 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.079420]  [<f8a1d36c>] ? 
assert_pipe+0xec/0x100 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.079428]  [<c10345e3>] ? 
warn_slowpath_fmt+0x33/0x40
Jun  9 14:20:23 tyleet kernel: [  163.079473]  [<f8a1d36c>] ? 
assert_pipe+0xec/0x100 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.079522]  [<f8a1f79e>] ? 
i9xx_crtc_enable+0x14e/0x490 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.079567]  [<f8a240cb>] ? 
__intel_set_mode+0x7cb/0x14d0 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.079581]  [<c10662d2>] ? 
console_trylock+0x42/0x50
Jun  9 14:20:23 tyleet kernel: [  163.079596]  [<c1317020>] ? 
printk+0x37/0x3b
Jun  9 14:20:23 tyleet kernel: [  163.079641]  [<f8a273b3>] ? 
intel_set_mode+0x23/0x40 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.079685]  [<f8a276a7>] ? 
intel_get_load_detect_pipe+0x1d7/0x410 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.079733]  [<f8a29316>] ? 
intel_modeset_setup_hw_state+0xab6/0xd40 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.079775]  [<f8a055d5>] ? 
i915_enable_pipestat+0x95/0x100 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.079817]  [<f8a0da90>] ? 
gen4_write64+0x50/0x50 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.079846]  [<f89d8227>] ? 
__i915_drm_thaw+0xf7/0x170 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.079875]  [<f89d8b03>] ? 
i915_resume+0x23/0x40 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.079886]  [<c119d7d4>] ? 
pci_pm_resume+0x54/0xc0
Jun  9 14:20:23 tyleet kernel: [  163.079892]  [<c119d780>] ? 
pci_pm_restore+0xe0/0xe0
Jun  9 14:20:23 tyleet kernel: [  163.079904]  [<c12305fa>] ? 
dpm_run_callback.isra.8+0x2a/0x70
Jun  9 14:20:23 tyleet kernel: [  163.079911]  [<c1230c40>] ? 
device_resume+0xb0/0x170
Jun  9 14:20:23 tyleet kernel: [  163.079917]  [<c1230d16>] ? 
async_resume+0x16/0x40
Jun  9 14:20:23 tyleet kernel: [  163.079925]  [<c10502ba>] ? 
async_run_entry_fn+0x3a/0x130
Jun  9 14:20:23 tyleet kernel: [  163.079931]  [<c1051e7e>] ? 
check_preempt_curr+0x7e/0x90
Jun  9 14:20:23 tyleet kernel: [  163.079940]  [<c1045f41>] ? 
process_one_work+0xd1/0x300
Jun  9 14:20:23 tyleet kernel: [  163.079947]  [<c1046aa7>] ? 
manage_workers.isra.33+0x1a7/0x250
Jun  9 14:20:23 tyleet kernel: [  163.079954]  [<c1046c38>] ? 
worker_thread+0xe8/0x2f0
Jun  9 14:20:23 tyleet kernel: [  163.079960]  [<c1046b50>] ? 
manage_workers.isra.33+0x250/0x250
Jun  9 14:20:23 tyleet kernel: [  163.079971]  [<c104b313>] ? 
kthread+0x93/0xb0
Jun  9 14:20:23 tyleet kernel: [  163.079984]  [<c131bba0>] ? 
ret_from_kernel_thread+0x20/0x30
Jun  9 14:20:23 tyleet kernel: [  163.079991]  [<c104b280>] ? 
flush_kthread_worker+0x80/0x80
Jun  9 14:20:23 tyleet kernel: [  163.079995] ---[ end trace 
8f4827d64b0098be ]---
Jun  9 14:20:23 tyleet kernel: [  163.080695] [drm:i830_get_fifo_size] 
FIFO size - (0x00017e5f) A: 47
Jun  9 14:20:23 tyleet kernel: [  163.080700] [drm:intel_calculate_wm] 
FIFO entries required for mode: 20
Jun  9 14:20:23 tyleet kernel: [  163.080703] [drm:intel_calculate_wm] 
FIFO watermark level: 25
Jun  9 14:20:23 tyleet kernel: [  163.080707] [drm:i830_get_fifo_size] 
FIFO size - (0x00017e5f) B: 48
Jun  9 14:20:23 tyleet kernel: [  163.080711] [drm:i9xx_update_wm] FIFO 
watermarks - A: 25, B: 31
Jun  9 14:20:23 tyleet kernel: [  163.080716] [drm:i9xx_update_wm] 
Setting FIFO watermarks - A: 25, B: 31, C: 2, SR 1
Jun  9 14:20:23 tyleet kernel: [  163.080729] [drm:ns2501_mode_set] set 
mode (hdisplay=640,htotal=832,vdisplay=480,vtotal=520).
Jun  9 14:20:23 tyleet kernel: [  163.137445] [drm:ns2501_dpms] Trying 
set the dpms of the DVO to 1
Jun  9 14:20:23 tyleet kernel: [  163.224337] ata2.00: ACPI cmd 
ef/03:0c:00:00:00:a0 (unknown) filtered out
Jun  9 14:20:23 tyleet kernel: [  163.224344] ata2.00: ACPI cmd 
ef/03:42:00:00:00:a0 (unknown) filtered out
Jun  9 14:20:23 tyleet kernel: [  163.224464] ata2.00: ACPI cmd 
00/00:00:00:00:00:a0 (unknown) rejected by device (Stat=0x51 Err=0x04)
Jun  9 14:20:23 tyleet kernel: [  163.232261] ata2.00: configured for 
UDMA/33
Jun  9 14:20:23 tyleet kernel: [  163.361378] 
[drm:i9xx_update_primary_plane] Writing base 00060000 00000000 0 0 4096
Jun  9 14:20:23 tyleet kernel: [  163.361396] 
[drm:intel_connector_check_state] [CONNECTOR:8:VGA-1]
Jun  9 14:20:23 tyleet kernel: [  163.362295] 
[drm:intel_connector_check_state] [CONNECTOR:11:DVI-I-1]
Jun  9 14:20:23 tyleet kernel: [  163.362299] [drm:check_encoder_state] 
[ENCODER:9:DAC-9]
Jun  9 14:20:23 tyleet kernel: [  163.362303] [drm:check_encoder_state] 
[ENCODER:10:None-10]
Jun  9 14:20:23 tyleet kernel: [  163.362308] [drm:check_crtc_state] 
[CRTC:5]
Jun  9 14:20:23 tyleet kernel: [  163.362327] [drm:check_crtc_state] 
[CRTC:7]
Jun  9 14:20:23 tyleet kernel: [  163.376049] 
[drm:intel_release_load_detect_pipe] [CONNECTOR:8:VGA-1], [ENCODER:9:DAC-9]
Jun  9 14:20:23 tyleet kernel: [  163.376056] 
[drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, 
prepare: 0, disable: 1
Jun  9 14:20:23 tyleet kernel: [  163.376062] 
[drm:i9xx_set_fifo_underrun_reporting] *ERROR* pipe A underrun
Jun  9 14:20:23 tyleet kernel: [  163.376083] [drm:ns2501_dpms] Trying 
set the dpms of the DVO to 0
Jun  9 14:20:23 tyleet kernel: [  163.536088] usb 1-2: reset low-speed 
USB device number 3 using uhci_hcd
Jun  9 14:20:23 tyleet kernel: [  163.576094] firewire_core 
0000:01:0c.0: rediscovered device fw0
Jun  9 14:20:23 tyleet kernel: [  163.608054] [drm:i830_get_fifo_size] 
FIFO size - (0x00017e5f) A: 47
Jun  9 14:20:23 tyleet kernel: [  163.608059] [drm:i830_get_fifo_size] 
FIFO size - (0x00017e5f) B: 48
Jun  9 14:20:23 tyleet kernel: [  163.608062] [drm:i9xx_update_wm] FIFO 
watermarks - A: 45, B: 31
Jun  9 14:20:23 tyleet kernel: [  163.608066] [drm:i9xx_update_wm] 
Setting FIFO watermarks - A: 45, B: 31, C: 2, SR 1
Jun  9 14:20:23 tyleet kernel: [  163.608076] ------------[ cut here 
]------------
Jun  9 14:20:23 tyleet kernel: [  163.608165] WARNING: CPU: 0 PID: 2976 
at drivers/gpu/drm/i915/intel_display.c:9881 
__intel_set_mode+0x1363/0x14d0 [i915]()
Jun  9 14:20:23 tyleet kernel: [  163.608247] Modules linked in: 
michael_mic arc4 ecb lib80211_crypt_tkip lib80211_crypt_ccmp binfmt_misc 
fuse netconsole loop firewire_sbp2 hid_generic usbhid hid ipw2100 
snd_intel8x0 snd_ac97_codec sg libipw ac97_bus sr_mod cfg80211 snd_pcm 
mousedev cdrom snd_seq snd_seq_device snd_timer pcmcia uhci_hcd irda 
usbcore i915 rfkill yenta_socket snd firewire_ohci lpc_ich pcmcia_rsrc 
firewire_core apanel 8139too input_polldev evdev psmouse 8139cp mfd_core 
mii soundcore crc_itu_t lib80211 i2c_i801 i2c_algo_bit drm_kms_helper 
8250 drm pcspkr crc_ccitt pcmcia_core serial_core fujitsu_laptop 
i2c_core video intel_agp intel_gtt led_class usb_common agpgart ac 
battery button
Jun  9 14:20:23 tyleet kernel: [  163.608255] CPU: 0 PID: 2976 Comm: 
kworker/u2:11 Tainted: G        W     3.15.0-rc7+ #8
Jun  9 14:20:23 tyleet kernel: [  163.608258] Hardware name: FUJITSU 
SIEMENS LIFEBOOK S Series/FJNB159, BIOS Version 1.07  10/28/2002
Jun  9 14:20:23 tyleet kernel: [  163.608273] Workqueue: events_unbound 
async_run_entry_fn
Jun  9 14:20:23 tyleet kernel: [  163.608284]  c131831e c103451f 
c13ab9b0 00000000 00000ba0 f8a6b228 00002699 f8a24c63
Jun  9 14:20:23 tyleet kernel: [  163.608293]  f8a24c63 c0148000 
f6beb594 f6beb560 f6beb578 c1034569 00000009 00000000
Jun  9 14:20:23 tyleet kernel: [  163.608302]  f8a24c63 f8a5e6f0 
f8a6cf10 00000000 00000000 00000001 c10662d2 00000001
Jun  9 14:20:23 tyleet kernel: [  163.608304] Call Trace:
Jun  9 14:20:23 tyleet kernel: [  163.608313]  [<c131831e>] ? 
dump_stack+0xa/0x13
Jun  9 14:20:23 tyleet kernel: [  163.608321]  [<c103451f>] ? 
warn_slowpath_common+0x7f/0xb0
Jun  9 14:20:23 tyleet kernel: [  163.608368]  [<f8a24c63>] ? 
__intel_set_mode+0x1363/0x14d0 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.608413]  [<f8a24c63>] ? 
__intel_set_mode+0x1363/0x14d0 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.608420]  [<c1034569>] ? 
warn_slowpath_null+0x19/0x20
Jun  9 14:20:23 tyleet kernel: [  163.608465]  [<f8a24c63>] ? 
__intel_set_mode+0x1363/0x14d0 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.608479]  [<c10662d2>] ? 
console_trylock+0x42/0x50
Jun  9 14:20:23 tyleet kernel: [  163.608491]  [<c1317020>] ? 
printk+0x37/0x3b
Jun  9 14:20:23 tyleet kernel: [  163.608536]  [<f8a273b3>] ? 
intel_set_mode+0x23/0x40 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.608580]  [<f8a27476>] ? 
intel_release_load_detect_pipe+0xa6/0x100 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.608626]  [<f8a2932d>] ? 
intel_modeset_setup_hw_state+0xacd/0xd40 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.608669]  [<f8a055d5>] ? 
i915_enable_pipestat+0x95/0x100 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.608710]  [<f8a0da90>] ? 
gen4_write64+0x50/0x50 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.608740]  [<f89d8227>] ? 
__i915_drm_thaw+0xf7/0x170 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.608768]  [<f89d8b03>] ? 
i915_resume+0x23/0x40 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.608778]  [<c119d7d4>] ? 
pci_pm_resume+0x54/0xc0
Jun  9 14:20:23 tyleet kernel: [  163.608784]  [<c119d780>] ? 
pci_pm_restore+0xe0/0xe0
Jun  9 14:20:23 tyleet kernel: [  163.608795]  [<c12305fa>] ? 
dpm_run_callback.isra.8+0x2a/0x70
Jun  9 14:20:23 tyleet kernel: [  163.608802]  [<c1230c40>] ? 
device_resume+0xb0/0x170
Jun  9 14:20:23 tyleet kernel: [  163.608809]  [<c1230d16>] ? 
async_resume+0x16/0x40
Jun  9 14:20:23 tyleet kernel: [  163.608816]  [<c10502ba>] ? 
async_run_entry_fn+0x3a/0x130
Jun  9 14:20:23 tyleet kernel: [  163.608822]  [<c1051e7e>] ? 
check_preempt_curr+0x7e/0x90
Jun  9 14:20:23 tyleet kernel: [  163.608831]  [<c1045f41>] ? 
process_one_work+0xd1/0x300
Jun  9 14:20:23 tyleet kernel: [  163.608837]  [<c1046aa7>] ? 
manage_workers.isra.33+0x1a7/0x250
Jun  9 14:20:23 tyleet kernel: [  163.608844]  [<c1046c38>] ? 
worker_thread+0xe8/0x2f0
Jun  9 14:20:23 tyleet kernel: [  163.608851]  [<c1046b50>] ? 
manage_workers.isra.33+0x250/0x250
Jun  9 14:20:23 tyleet kernel: [  163.608860]  [<c104b313>] ? 
kthread+0x93/0xb0
Jun  9 14:20:23 tyleet kernel: [  163.608871]  [<c131bba0>] ? 
ret_from_kernel_thread+0x20/0x30
Jun  9 14:20:23 tyleet kernel: [  163.608878]  [<c104b280>] ? 
flush_kthread_worker+0x80/0x80
Jun  9 14:20:23 tyleet kernel: [  163.608883] ---[ end trace 
8f4827d64b0098bf ]---
Jun  9 14:20:23 tyleet kernel: [  163.608891] [drm:check_encoder_state] 
[ENCODER:9:DAC-9]
Jun  9 14:20:23 tyleet kernel: [  163.608895] [drm:check_encoder_state] 
[ENCODER:10:None-10]
Jun  9 14:20:23 tyleet kernel: [  163.608898] [drm:check_crtc_state] 
[CRTC:5]
Jun  9 14:20:23 tyleet kernel: [  163.608900] ------------[ cut here 
]------------
Jun  9 14:20:23 tyleet kernel: [  163.608945] WARNING: CPU: 0 PID: 2976 
at drivers/gpu/drm/i915/intel_display.c:10190 
check_crtc_state+0xaa3/0xf10 [i915]()
Jun  9 14:20:23 tyleet kernel: [  163.608948] crtc's computed enabled 
state doesn't match tracked enabled state (expected 1, found 0)
Jun  9 14:20:23 tyleet kernel: [  163.609023] Modules linked in: 
michael_mic arc4 ecb lib80211_crypt_tkip lib80211_crypt_ccmp binfmt_misc 
fuse netconsole loop firewire_sbp2 hid_generic usbhid hid ipw2100 
snd_intel8x0 snd_ac97_codec sg libipw ac97_bus sr_mod cfg80211 snd_pcm 
mousedev cdrom snd_seq snd_seq_device snd_timer pcmcia uhci_hcd irda 
usbcore i915 rfkill yenta_socket snd firewire_ohci lpc_ich pcmcia_rsrc 
firewire_core apanel 8139too input_polldev evdev psmouse 8139cp mfd_core 
mii soundcore crc_itu_t lib80211 i2c_i801 i2c_algo_bit drm_kms_helper 
8250 drm pcspkr crc_ccitt pcmcia_core serial_core fujitsu_laptop 
i2c_core video intel_agp intel_gtt led_class usb_common agpgart ac 
battery button
Jun  9 14:20:23 tyleet kernel: [  163.609028] CPU: 0 PID: 2976 Comm: 
kworker/u2:11 Tainted: G        W     3.15.0-rc7+ #8
Jun  9 14:20:23 tyleet kernel: [  163.609031] Hardware name: FUJITSU 
SIEMENS LIFEBOOK S Series/FJNB159, BIOS Version 1.07  10/28/2002
Jun  9 14:20:23 tyleet kernel: [  163.609039] Workqueue: events_unbound 
async_run_entry_fn
Jun  9 14:20:23 tyleet kernel: [  163.609049]  c131831e c103451f 
f8a6b9ac efb6db00 00000ba0 f8a6b228 000027ce f8a184b3
Jun  9 14:20:23 tyleet kernel: [  163.609058]  f8a184b3 c0148000 
f6beb574 f8a6b9ac f6beb578 c10345e3 00000009 efb6dae8
Jun  9 14:20:23 tyleet kernel: [  163.609067]  f8a6b9ac efb6db00 
f8a184b3 f8a6b228 000027ce f8a6b9ac 00000001 00000000
Jun  9 14:20:23 tyleet kernel: [  163.609068] Call Trace:
Jun  9 14:20:23 tyleet kernel: [  163.609075]  [<c131831e>] ? 
dump_stack+0xa/0x13
Jun  9 14:20:23 tyleet kernel: [  163.609081]  [<c103451f>] ? 
warn_slowpath_common+0x7f/0xb0
Jun  9 14:20:23 tyleet kernel: [  163.609128]  [<f8a184b3>] ? 
check_crtc_state+0xaa3/0xf10 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.609172]  [<f8a184b3>] ? 
check_crtc_state+0xaa3/0xf10 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.609180]  [<c10345e3>] ? 
warn_slowpath_fmt+0x33/0x40
Jun  9 14:20:23 tyleet kernel: [  163.609225]  [<f8a184b3>] ? 
check_crtc_state+0xaa3/0xf10 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.609280]  [<f8a26ddc>] ? 
intel_modeset_check_state+0x21c/0x7d0 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.609290]  [<c1317020>] ? 
printk+0x37/0x3b
Jun  9 14:20:23 tyleet kernel: [  163.609334]  [<f8a273c0>] ? 
intel_set_mode+0x30/0x40 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.609379]  [<f8a27476>] ? 
intel_release_load_detect_pipe+0xa6/0x100 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.609423]  [<f8a2932d>] ? 
intel_modeset_setup_hw_state+0xacd/0xd40 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.609466]  [<f8a055d5>] ? 
i915_enable_pipestat+0x95/0x100 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.609508]  [<f8a0da90>] ? 
gen4_write64+0x50/0x50 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.609537]  [<f89d8227>] ? 
__i915_drm_thaw+0xf7/0x170 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.609566]  [<f89d8b03>] ? 
i915_resume+0x23/0x40 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.609573]  [<c119d7d4>] ? 
pci_pm_resume+0x54/0xc0
Jun  9 14:20:23 tyleet kernel: [  163.609579]  [<c119d780>] ? 
pci_pm_restore+0xe0/0xe0
Jun  9 14:20:23 tyleet kernel: [  163.609587]  [<c12305fa>] ? 
dpm_run_callback.isra.8+0x2a/0x70
Jun  9 14:20:23 tyleet kernel: [  163.609593]  [<c1230c40>] ? 
device_resume+0xb0/0x170
Jun  9 14:20:23 tyleet kernel: [  163.609600]  [<c1230d16>] ? 
async_resume+0x16/0x40
Jun  9 14:20:23 tyleet kernel: [  163.609607]  [<c10502ba>] ? 
async_run_entry_fn+0x3a/0x130
Jun  9 14:20:23 tyleet kernel: [  163.609613]  [<c1051e7e>] ? 
check_preempt_curr+0x7e/0x90
Jun  9 14:20:23 tyleet kernel: [  163.609620]  [<c1045f41>] ? 
process_one_work+0xd1/0x300
Jun  9 14:20:23 tyleet kernel: [  163.609626]  [<c1046aa7>] ? 
manage_workers.isra.33+0x1a7/0x250
Jun  9 14:20:23 tyleet kernel: [  163.609633]  [<c1046c38>] ? 
worker_thread+0xe8/0x2f0
Jun  9 14:20:23 tyleet kernel: [  163.609639]  [<c1046b50>] ? 
manage_workers.isra.33+0x250/0x250
Jun  9 14:20:23 tyleet kernel: [  163.609647]  [<c104b313>] ? 
kthread+0x93/0xb0
Jun  9 14:20:23 tyleet kernel: [  163.609655]  [<c131bba0>] ? 
ret_from_kernel_thread+0x20/0x30
Jun  9 14:20:23 tyleet kernel: [  163.609662]  [<c104b280>] ? 
flush_kthread_worker+0x80/0x80
Jun  9 14:20:23 tyleet kernel: [  163.609666] ---[ end trace 
8f4827d64b0098c0 ]---
Jun  9 14:20:23 tyleet kernel: [  163.609676] [drm:check_crtc_state] 
[CRTC:7]
Jun  9 14:20:23 tyleet kernel: [  163.609685] 
[drm:intel_dump_pipe_config] [CRTC:5][setup_hw_state] config for pipe A
Jun  9 14:20:23 tyleet kernel: [  163.609687] 
[drm:intel_dump_pipe_config] cpu_transcoder: A
Jun  9 14:20:23 tyleet kernel: [  163.609690] 
[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
Jun  9 14:20:23 tyleet kernel: [  163.609696] 
[drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, 
link_m: 0, link_n: 0, tu: 0
Jun  9 14:20:23 tyleet kernel: [  163.609701] 
[drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, 
link_n: 0, tu: 0
Jun  9 14:20:23 tyleet kernel: [  163.609703] 
[drm:intel_dump_pipe_config] requested mode:
Jun  9 14:20:23 tyleet kernel: [  163.609712] 
[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 31500 640 664 
704 832 480 489 491 520 0x10 0xa
Jun  9 14:20:23 tyleet kernel: [  163.609715] 
[drm:intel_dump_pipe_config] adjusted mode:
Jun  9 14:20:23 tyleet kernel: [  163.609723] 
[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 31500 640 664 
704 832 480 489 491 520 0x10 0xa
Jun  9 14:20:23 tyleet kernel: [  163.609730] 
[drm:intel_dump_crtc_timings] crtc timings: 31500 640 664 704 832 480 
489 491 520, type: 0x10 flags: 0xa
Jun  9 14:20:23 tyleet kernel: [  163.609733] 
[drm:intel_dump_pipe_config] port clock: 31500
Jun  9 14:20:23 tyleet kernel: [  163.609736] 
[drm:intel_dump_pipe_config] pipe src size: 640x480
Jun  9 14:20:23 tyleet kernel: [  163.609741] 
[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 
0x00000000, lvds border: 0x00000000
Jun  9 14:20:23 tyleet kernel: [  163.609744] 
[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 
0x00000000, disabled
Jun  9 14:20:23 tyleet kernel: [  163.609747] 
[drm:intel_dump_pipe_config] ips: 0
Jun  9 14:20:23 tyleet kernel: [  163.609750] 
[drm:intel_dump_pipe_config] double wide: 0
Jun  9 14:20:23 tyleet kernel: [  163.609755] 
[drm:i915_get_vblank_timestamp] crtc 1 is disabled
Jun  9 14:20:23 tyleet kernel: [  163.609762] 
[drm:intel_dump_pipe_config] [CRTC:7][setup_hw_state] config for pipe B
Jun  9 14:20:23 tyleet kernel: [  163.609765] 
[drm:intel_dump_pipe_config] cpu_transcoder: B
Jun  9 14:20:23 tyleet kernel: [  163.609768] 
[drm:intel_dump_pipe_config] pipe bpp: 0, dithering: 0
Jun  9 14:20:23 tyleet kernel: [  163.609773] 
[drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, 
link_m: 0, link_n: 0, tu: 0
Jun  9 14:20:23 tyleet kernel: [  163.609778] 
[drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, 
link_n: 0, tu: 0
Jun  9 14:20:23 tyleet kernel: [  163.609780] 
[drm:intel_dump_pipe_config] requested mode:
Jun  9 14:20:23 tyleet kernel: [  163.609787] 
[drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
Jun  9 14:20:23 tyleet kernel: [  163.609790] 
[drm:intel_dump_pipe_config] adjusted mode:
Jun  9 14:20:23 tyleet kernel: [  163.609797] 
[drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
Jun  9 14:20:23 tyleet kernel: [  163.609803] 
[drm:intel_dump_crtc_timings] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 
flags: 0x0
Jun  9 14:20:23 tyleet kernel: [  163.609805] 
[drm:intel_dump_pipe_config] port clock: 0
Jun  9 14:20:23 tyleet kernel: [  163.609808] 
[drm:intel_dump_pipe_config] pipe src size: 0x0
Jun  9 14:20:23 tyleet kernel: [  163.609813] 
[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 
0x00000000, lvds border: 0x00000000
Jun  9 14:20:23 tyleet kernel: [  163.609816] 
[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 
0x00000000, disabled
Jun  9 14:20:23 tyleet kernel: [  163.609819] 
[drm:intel_dump_pipe_config] ips: 0
Jun  9 14:20:23 tyleet kernel: [  163.609821] 
[drm:intel_dump_pipe_config] double wide: 0
Jun  9 14:20:23 tyleet kernel: [  163.609827] 
[drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, 
prepare: 0, disable: 0
Jun  9 14:20:23 tyleet kernel: [  163.609829] ------------[ cut here 
]------------
Jun  9 14:20:23 tyleet kernel: [  163.609875] WARNING: CPU: 0 PID: 2976 
at drivers/gpu/drm/i915/intel_display.c:9881 
__intel_set_mode+0x1363/0x14d0 [i915]()
Jun  9 14:20:23 tyleet kernel: [  163.609949] Modules linked in: 
michael_mic arc4 ecb lib80211_crypt_tkip lib80211_crypt_ccmp binfmt_misc 
fuse netconsole loop firewire_sbp2 hid_generic usbhid hid ipw2100 
snd_intel8x0 snd_ac97_codec sg libipw ac97_bus sr_mod cfg80211 snd_pcm 
mousedev cdrom snd_seq snd_seq_device snd_timer pcmcia uhci_hcd irda 
usbcore i915 rfkill yenta_socket snd firewire_ohci lpc_ich pcmcia_rsrc 
firewire_core apanel 8139too input_polldev evdev psmouse 8139cp mfd_core 
mii soundcore crc_itu_t lib80211 i2c_i801 i2c_algo_bit drm_kms_helper 
8250 drm pcspkr crc_ccitt pcmcia_core serial_core fujitsu_laptop 
i2c_core video intel_agp intel_gtt led_class usb_common agpgart ac 
battery button
Jun  9 14:20:23 tyleet kernel: [  163.609955] CPU: 0 PID: 2976 Comm: 
kworker/u2:11 Tainted: G        W     3.15.0-rc7+ #8
Jun  9 14:20:23 tyleet kernel: [  163.609957] Hardware name: FUJITSU 
SIEMENS LIFEBOOK S Series/FJNB159, BIOS Version 1.07  10/28/2002
Jun  9 14:20:23 tyleet kernel: [  163.609965] Workqueue: events_unbound 
async_run_entry_fn
Jun  9 14:20:23 tyleet kernel: [  163.609975]  c131831e c103451f 
c13ab9b0 00000000 00000ba0 f8a6b228 00002699 f8a24c63
Jun  9 14:20:23 tyleet kernel: [  163.609984]  f8a24c63 c0148000 
f6beb594 f6beb560 f6beb578 c1034569 00000009 00000000
Jun  9 14:20:23 tyleet kernel: [  163.609992]  f8a24c63 f8a5e6f0 
f8a6cf10 00000000 00000000 00000000 00000000 00000000
Jun  9 14:20:23 tyleet kernel: [  163.609994] Call Trace:
Jun  9 14:20:23 tyleet kernel: [  163.610000]  [<c131831e>] ? 
dump_stack+0xa/0x13
Jun  9 14:20:23 tyleet kernel: [  163.610007]  [<c103451f>] ? 
warn_slowpath_common+0x7f/0xb0
Jun  9 14:20:23 tyleet kernel: [  163.610053]  [<f8a24c63>] ? 
__intel_set_mode+0x1363/0x14d0 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.610098]  [<f8a24c63>] ? 
__intel_set_mode+0x1363/0x14d0 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.610105]  [<c1034569>] ? 
warn_slowpath_null+0x19/0x20
Jun  9 14:20:23 tyleet kernel: [  163.610149]  [<f8a24c63>] ? 
__intel_set_mode+0x1363/0x14d0 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.610160]  [<c131a468>] ? 
mutex_lock+0x8/0x15
Jun  9 14:20:23 tyleet kernel: [  163.610204]  [<f8a287df>] ? 
i915_redisable_vga_power_on+0x3f/0x90 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.610248]  [<f8a28fe4>] ? 
intel_modeset_setup_hw_state+0x784/0xd40 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.610290]  [<f8a055d5>] ? 
i915_enable_pipestat+0x95/0x100 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.610332]  [<f8a0da90>] ? 
gen4_write64+0x50/0x50 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.610361]  [<f89d8227>] ? 
__i915_drm_thaw+0xf7/0x170 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.610390]  [<f89d8b03>] ? 
i915_resume+0x23/0x40 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.610398]  [<c119d7d4>] ? 
pci_pm_resume+0x54/0xc0
Jun  9 14:20:23 tyleet kernel: [  163.610404]  [<c119d780>] ? 
pci_pm_restore+0xe0/0xe0
Jun  9 14:20:23 tyleet kernel: [  163.610411]  [<c12305fa>] ? 
dpm_run_callback.isra.8+0x2a/0x70
Jun  9 14:20:23 tyleet kernel: [  163.610418]  [<c1230c40>] ? 
device_resume+0xb0/0x170
Jun  9 14:20:23 tyleet kernel: [  163.610424]  [<c1230d16>] ? 
async_resume+0x16/0x40
Jun  9 14:20:23 tyleet kernel: [  163.610432]  [<c10502ba>] ? 
async_run_entry_fn+0x3a/0x130
Jun  9 14:20:23 tyleet kernel: [  163.610437]  [<c1051e7e>] ? 
check_preempt_curr+0x7e/0x90
Jun  9 14:20:23 tyleet kernel: [  163.610444]  [<c1045f41>] ? 
process_one_work+0xd1/0x300
Jun  9 14:20:23 tyleet kernel: [  163.610451]  [<c1046aa7>] ? 
manage_workers.isra.33+0x1a7/0x250
Jun  9 14:20:23 tyleet kernel: [  163.610457]  [<c1046c38>] ? 
worker_thread+0xe8/0x2f0
Jun  9 14:20:23 tyleet kernel: [  163.610464]  [<c1046b50>] ? 
manage_workers.isra.33+0x250/0x250
Jun  9 14:20:23 tyleet kernel: [  163.610471]  [<c104b313>] ? 
kthread+0x93/0xb0
Jun  9 14:20:23 tyleet kernel: [  163.610479]  [<c131bba0>] ? 
ret_from_kernel_thread+0x20/0x30
Jun  9 14:20:23 tyleet kernel: [  163.610486]  [<c104b280>] ? 
flush_kthread_worker+0x80/0x80
Jun  9 14:20:23 tyleet kernel: [  163.610490] ---[ end trace 
8f4827d64b0098c1 ]---
Jun  9 14:20:23 tyleet kernel: [  163.610496] 
[drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, 
prepare: 0, disable: 0
Jun  9 14:20:23 tyleet kernel: [  163.610499] ------------[ cut here 
]------------
Jun  9 14:20:23 tyleet kernel: [  163.610544] WARNING: CPU: 0 PID: 2976 
at drivers/gpu/drm/i915/intel_display.c:9881 
__intel_set_mode+0x1363/0x14d0 [i915]()
Jun  9 14:20:23 tyleet kernel: [  163.610618] Modules linked in: 
michael_mic arc4 ecb lib80211_crypt_tkip lib80211_crypt_ccmp binfmt_misc 
fuse netconsole loop firewire_sbp2 hid_generic usbhid hid ipw2100 
snd_intel8x0 snd_ac97_codec sg libipw ac97_bus sr_mod cfg80211 snd_pcm 
mousedev cdrom snd_seq snd_seq_device snd_timer pcmcia uhci_hcd irda 
usbcore i915 rfkill yenta_socket snd firewire_ohci lpc_ich pcmcia_rsrc 
firewire_core apanel 8139too input_polldev evdev psmouse 8139cp mfd_core 
mii soundcore crc_itu_t lib80211 i2c_i801 i2c_algo_bit drm_kms_helper 
8250 drm pcspkr crc_ccitt pcmcia_core serial_core fujitsu_laptop 
i2c_core video intel_agp intel_gtt led_class usb_common agpgart ac 
battery button
Jun  9 14:20:23 tyleet kernel: [  163.610623] CPU: 0 PID: 2976 Comm: 
kworker/u2:11 Tainted: G        W     3.15.0-rc7+ #8
Jun  9 14:20:23 tyleet kernel: [  163.610626] Hardware name: FUJITSU 
SIEMENS LIFEBOOK S Series/FJNB159, BIOS Version 1.07  10/28/2002
Jun  9 14:20:23 tyleet kernel: [  163.610633] Workqueue: events_unbound 
async_run_entry_fn
Jun  9 14:20:23 tyleet kernel: [  163.610643]  c131831e c103451f 
c13ab9b0 00000000 00000ba0 f8a6b228 00002699 f8a24c63
Jun  9 14:20:23 tyleet kernel: [  163.610652]  f8a24c63 c0148000 
f6beb594 f6beb560 f6beb578 c1034569 00000009 00000000
Jun  9 14:20:23 tyleet kernel: [  163.610661]  f8a24c63 f8a5e6f0 
f8a6cf10 00000000 00000000 00000000 00000000 00000000
Jun  9 14:20:23 tyleet kernel: [  163.610662] Call Trace:
Jun  9 14:20:23 tyleet kernel: [  163.610668]  [<c131831e>] ? 
dump_stack+0xa/0x13
Jun  9 14:20:23 tyleet kernel: [  163.610675]  [<c103451f>] ? 
warn_slowpath_common+0x7f/0xb0
Jun  9 14:20:23 tyleet kernel: [  163.610721]  [<f8a24c63>] ? 
__intel_set_mode+0x1363/0x14d0 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.610765]  [<f8a24c63>] ? 
__intel_set_mode+0x1363/0x14d0 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.610772]  [<c1034569>] ? 
warn_slowpath_null+0x19/0x20
Jun  9 14:20:23 tyleet kernel: [  163.610817]  [<f8a24c63>] ? 
__intel_set_mode+0x1363/0x14d0 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.610827]  [<c131a468>] ? 
mutex_lock+0x8/0x15
Jun  9 14:20:23 tyleet kernel: [  163.610871]  [<f8a287df>] ? 
i915_redisable_vga_power_on+0x3f/0x90 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.610916]  [<f8a28fe4>] ? 
intel_modeset_setup_hw_state+0x784/0xd40 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.610957]  [<f8a055d5>] ? 
i915_enable_pipestat+0x95/0x100 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.610999]  [<f8a0da90>] ? 
gen4_write64+0x50/0x50 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.611028]  [<f89d8227>] ? 
__i915_drm_thaw+0xf7/0x170 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.611057]  [<f89d8b03>] ? 
i915_resume+0x23/0x40 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.611065]  [<c119d7d4>] ? 
pci_pm_resume+0x54/0xc0
Jun  9 14:20:23 tyleet kernel: [  163.611071]  [<c119d780>] ? 
pci_pm_restore+0xe0/0xe0
Jun  9 14:20:23 tyleet kernel: [  163.611078]  [<c12305fa>] ? 
dpm_run_callback.isra.8+0x2a/0x70
Jun  9 14:20:23 tyleet kernel: [  163.611085]  [<c1230c40>] ? 
device_resume+0xb0/0x170
Jun  9 14:20:23 tyleet kernel: [  163.611091]  [<c1230d16>] ? 
async_resume+0x16/0x40
Jun  9 14:20:23 tyleet kernel: [  163.611098]  [<c10502ba>] ? 
async_run_entry_fn+0x3a/0x130
Jun  9 14:20:23 tyleet kernel: [  163.611104]  [<c1051e7e>] ? 
check_preempt_curr+0x7e/0x90
Jun  9 14:20:23 tyleet kernel: [  163.611111]  [<c1045f41>] ? 
process_one_work+0xd1/0x300
Jun  9 14:20:23 tyleet kernel: [  163.611117]  [<c1046aa7>] ? 
manage_workers.isra.33+0x1a7/0x250
Jun  9 14:20:23 tyleet kernel: [  163.611124]  [<c1046c38>] ? 
worker_thread+0xe8/0x2f0
Jun  9 14:20:23 tyleet kernel: [  163.611131]  [<c1046b50>] ? 
manage_workers.isra.33+0x250/0x250
Jun  9 14:20:23 tyleet kernel: [  163.611138]  [<c104b313>] ? 
kthread+0x93/0xb0
Jun  9 14:20:23 tyleet kernel: [  163.611146]  [<c131bba0>] ? 
ret_from_kernel_thread+0x20/0x30
Jun  9 14:20:23 tyleet kernel: [  163.611153]  [<c104b280>] ? 
flush_kthread_worker+0x80/0x80
Jun  9 14:20:23 tyleet kernel: [  163.611157] ---[ end trace 
8f4827d64b0098c2 ]---
Jun  9 14:20:23 tyleet kernel: [  163.611163] [drm:check_encoder_state] 
[ENCODER:9:DAC-9]
Jun  9 14:20:23 tyleet kernel: [  163.611167] [drm:check_encoder_state] 
[ENCODER:10:None-10]
Jun  9 14:20:23 tyleet kernel: [  163.611171] [drm:check_crtc_state] 
[CRTC:5]
Jun  9 14:20:23 tyleet kernel: [  163.611172] ------------[ cut here 
]------------
Jun  9 14:20:23 tyleet kernel: [  163.611217] WARNING: CPU: 0 PID: 2976 
at drivers/gpu/drm/i915/intel_display.c:10190 
check_crtc_state+0xaa3/0xf10 [i915]()
Jun  9 14:20:23 tyleet kernel: [  163.611219] crtc's computed enabled 
state doesn't match tracked enabled state (expected 1, found 0)
Jun  9 14:20:23 tyleet kernel: [  163.611293] Modules linked in: 
michael_mic arc4 ecb lib80211_crypt_tkip lib80211_crypt_ccmp binfmt_misc 
fuse netconsole loop firewire_sbp2 hid_generic usbhid hid ipw2100 
snd_intel8x0 snd_ac97_codec sg libipw ac97_bus sr_mod cfg80211 snd_pcm 
mousedev cdrom snd_seq snd_seq_device snd_timer pcmcia uhci_hcd irda 
usbcore i915 rfkill yenta_socket snd firewire_ohci lpc_ich pcmcia_rsrc 
firewire_core apanel 8139too input_polldev evdev psmouse 8139cp mfd_core 
mii soundcore crc_itu_t lib80211 i2c_i801 i2c_algo_bit drm_kms_helper 
8250 drm pcspkr crc_ccitt pcmcia_core serial_core fujitsu_laptop 
i2c_core video intel_agp intel_gtt led_class usb_common agpgart ac 
battery button
Jun  9 14:20:23 tyleet kernel: [  163.611299] CPU: 0 PID: 2976 Comm: 
kworker/u2:11 Tainted: G        W     3.15.0-rc7+ #8
Jun  9 14:20:23 tyleet kernel: [  163.611301] Hardware name: FUJITSU 
SIEMENS LIFEBOOK S Series/FJNB159, BIOS Version 1.07  10/28/2002
Jun  9 14:20:23 tyleet kernel: [  163.611309] Workqueue: events_unbound 
async_run_entry_fn
Jun  9 14:20:23 tyleet kernel: [  163.611319]  c131831e c103451f 
f8a6b9ac efb6db44 00000ba0 f8a6b228 000027ce f8a184b3
Jun  9 14:20:23 tyleet kernel: [  163.611328]  f8a184b3 c0148000 
f6beb574 f8a6b9ac f6beb578 c10345e3 00000009 efb6db2c
Jun  9 14:20:23 tyleet kernel: [  163.611337]  f8a6b9ac efb6db44 
f8a184b3 f8a6b228 000027ce f8a6b9ac 00000001 00000000
Jun  9 14:20:23 tyleet kernel: [  163.611338] Call Trace:
Jun  9 14:20:23 tyleet kernel: [  163.611345]  [<c131831e>] ? 
dump_stack+0xa/0x13
Jun  9 14:20:23 tyleet kernel: [  163.611351]  [<c103451f>] ? 
warn_slowpath_common+0x7f/0xb0
Jun  9 14:20:23 tyleet kernel: [  163.611398]  [<f8a184b3>] ? 
check_crtc_state+0xaa3/0xf10 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.611442]  [<f8a184b3>] ? 
check_crtc_state+0xaa3/0xf10 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.611450]  [<c10345e3>] ? 
warn_slowpath_fmt+0x33/0x40
Jun  9 14:20:23 tyleet kernel: [  163.611495]  [<f8a184b3>] ? 
check_crtc_state+0xaa3/0xf10 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.611549]  [<f8a26ddc>] ? 
intel_modeset_check_state+0x21c/0x7d0 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.611558]  [<c131a468>] ? 
mutex_lock+0x8/0x15
Jun  9 14:20:23 tyleet kernel: [  163.611602]  [<f8a287df>] ? 
i915_redisable_vga_power_on+0x3f/0x90 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.611646]  [<f8a28ffb>] ? 
intel_modeset_setup_hw_state+0x79b/0xd40 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.611688]  [<f8a055d5>] ? 
i915_enable_pipestat+0x95/0x100 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.611730]  [<f8a0da90>] ? 
gen4_write64+0x50/0x50 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.611759]  [<f89d8227>] ? 
__i915_drm_thaw+0xf7/0x170 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.611788]  [<f89d8b03>] ? 
i915_resume+0x23/0x40 [i915]
Jun  9 14:20:23 tyleet kernel: [  163.611795]  [<c119d7d4>] ? 
pci_pm_resume+0x54/0xc0
Jun  9 14:20:23 tyleet kernel: [  163.611801]  [<c119d780>] ? 
pci_pm_restore+0xe0/0xe0
Jun  9 14:20:23 tyleet kernel: [  163.611809]  [<c12305fa>] ? 
dpm_run_callback.isra.8+0x2a/0x70
Jun  9 14:20:23 tyleet kernel: [  163.611815]  [<c1230c40>] ? 
device_resume+0xb0/0x170
Jun  9 14:20:23 tyleet kernel: [  163.611822]  [<c1230d16>] ? 
async_resume+0x16/0x40
Jun  9 14:20:23 tyleet kernel: [  163.611829]  [<c10502ba>] ? 
async_run_entry_fn+0x3a/0x130
Jun  9 14:20:23 tyleet kernel: [  163.611835]  [<c1051e7e>] ? 
check_preempt_curr+0x7e/0x90
Jun  9 14:20:23 tyleet kernel: [  163.611842]  [<c1045f41>] ? 
process_one_work+0xd1/0x300
Jun  9 14:20:23 tyleet kernel: [  163.611848]  [<c1046aa7>] ? 
manage_workers.isra.33+0x1a7/0x250
Jun  9 14:20:23 tyleet kernel: [  163.611855]  [<c1046c38>] ? 
worker_thread+0xe8/0x2f0
Jun  9 14:20:23 tyleet kernel: [  163.611861]  [<c1046b50>] ? 
manage_workers.isra.33+0x250/0x250
Jun  9 14:20:23 tyleet kernel: [  163.611868]  [<c104b313>] ? 
kthread+0x93/0xb0
Jun  9 14:20:23 tyleet kernel: [  163.611877]  [<c131bba0>] ? 
ret_from_kernel_thread+0x20/0x30
Jun  9 14:20:23 tyleet kernel: [  163.611884]  [<c104b280>] ? 
flush_kthread_worker+0x80/0x80
Jun  9 14:20:23 tyleet kernel: [  163.611888] ---[ end trace 
8f4827d64b0098c3 ]---
Jun  9 14:20:23 tyleet kernel: [  163.611898] [drm:check_crtc_state] 
[CRTC:7]
Jun  9 14:20:23 tyleet kernel: [  163.611955] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:15] #connectors=1 (x y) (0 0)
Jun  9 14:20:23 tyleet kernel: [  163.611963] 
[drm:intel_set_config_compute_mode_changes] modes are different, full 
mode set
Jun  9 14:20:23 tyleet kernel: [  163.611972] 
[drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 0 31500 640 664 
704 832 480 489 491 520 0x10 0xa
Jun  9 14:20:23 tyleet kernel: [  163.611981] 
[drm:drm_mode_debug_printmodeline] Modeline 13:"1024x768" 60 65000 1024 
1048 1184 1344 768 771 777 806 0x40 0xa
Jun  9 14:20:23 tyleet kernel: [  163.611984] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=1, fb_changed=0
Jun  9 14:20:23 tyleet kernel: [  163.611990] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:23 tyleet kernel: [  163.611994] 
[drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
Jun  9 14:20:23 tyleet kernel: [  163.611999] 
[drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, 
prepare: 1, disable: 0
Jun  9 14:20:23 tyleet kernel: [  163.612028] 
[drm:connected_sink_compute_bpp] [CONNECTOR:11:DVI-I-1] checking for 
sink bpp constrains
Jun  9 14:20:23 tyleet kernel: [  163.612036] 
[drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
Jun  9 14:20:23 tyleet kernel: [  163.612040] 
[drm:intel_dump_pipe_config] [CRTC:5][modeset] config for pipe A
Jun  9 14:20:23 tyleet kernel: [  163.612042] 
[drm:intel_dump_pipe_config] cpu_transcoder: A
Jun  9 14:20:23 tyleet kernel: [  163.612045] 
[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
Jun  9 14:20:23 tyleet kernel: [  163.612051] 
[drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, 
link_m: 0, link_n: 0, tu: 0
Jun  9 14:20:23 tyleet kernel: [  163.612055] 
[drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, 
link_n: 0, tu: 0
Jun  9 14:20:23 tyleet kernel: [  163.612057] 
[drm:intel_dump_pipe_config] requested mode:
Jun  9 14:20:23 tyleet kernel: [  163.612066] 
[drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 
1048 1184 1344 768 771 777 806 0x40 0xa
Jun  9 14:20:23 tyleet kernel: [  163.612068] 
[drm:intel_dump_pipe_config] adjusted mode:
Jun  9 14:20:23 tyleet kernel: [  163.612076] 
[drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 
1048 1184 1344 768 771 777 806 0x40 0xa
Jun  9 14:20:23 tyleet kernel: [  163.612083] 
[drm:intel_dump_crtc_timings] crtc timings: 65000 1024 1048 1184 1344 
768 771 777 806, type: 0x40 flags: 0xa
Jun  9 14:20:23 tyleet kernel: [  163.612086] 
[drm:intel_dump_pipe_config] port clock: 65000
Jun  9 14:20:23 tyleet kernel: [  163.612089] 
[drm:intel_dump_pipe_config] pipe src size: 1024x768
Jun  9 14:20:23 tyleet kernel: [  163.612093] 
[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 
0x00000000, lvds border: 0x00000000
Jun  9 14:20:23 tyleet kernel: [  163.612097] 
[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 
0x00000000, disabled
Jun  9 14:20:23 tyleet kernel: [  163.612099] 
[drm:intel_dump_pipe_config] ips: 0
Jun  9 14:20:23 tyleet kernel: [  163.612102] 
[drm:intel_dump_pipe_config] double wide: 0
Jun  9 14:20:23 tyleet kernel: [  163.621356] [drm:i830_get_fifo_size] 
FIFO size - (0x00017e5f) A: 47
Jun  9 14:20:23 tyleet kernel: [  163.621361] [drm:intel_calculate_wm] 
FIFO entries required for mode: 41
Jun  9 14:20:23 tyleet kernel: [  163.621363] [drm:intel_calculate_wm] 
FIFO watermark level: 4
Jun  9 14:20:23 tyleet kernel: [  163.621367] [drm:i830_get_fifo_size] 
FIFO size - (0x00017e5f) B: 48
Jun  9 14:20:23 tyleet kernel: [  163.621371] [drm:i9xx_update_wm] FIFO 
watermarks - A: 9, B: 31
Jun  9 14:20:23 tyleet kernel: [  163.621375] [drm:i9xx_update_wm] 
Setting FIFO watermarks - A: 9, B: 31, C: 2, SR 1
Jun  9 14:20:23 tyleet kernel: [  163.621384] [drm:ns2501_mode_set] set 
mode (hdisplay=1024,htotal=1344,vdisplay=768,vtotal=806).
Jun  9 14:20:23 tyleet kernel: [  163.677295] [drm:ns2501_dpms] Trying 
set the dpms of the DVO to 1
Jun  9 14:20:23 tyleet kernel: [  163.900116] PM: resume of devices 
complete after 926.057 msecs
Jun  9 14:20:23 tyleet kernel: [  163.901688] 
[drm:i9xx_update_primary_plane] Writing base 00060000 00000000 0 0 4096
Jun  9 14:20:23 tyleet kernel: [  163.902595] 
[drm:intel_connector_check_state] [CONNECTOR:11:DVI-I-1]
Jun  9 14:20:23 tyleet kernel: [  163.902599] [drm:check_encoder_state] 
[ENCODER:9:DAC-9]
Jun  9 14:20:23 tyleet kernel: [  163.902603] [drm:check_encoder_state] 
[ENCODER:10:None-10]
Jun  9 14:20:23 tyleet kernel: [  163.902607] [drm:check_crtc_state] 
[CRTC:5]
Jun  9 14:20:23 tyleet kernel: [  163.902620] [drm:check_crtc_state] 
[CRTC:7]
Jun  9 14:20:23 tyleet kernel: [  163.915750] PM: Finishing wakeup.
Jun  9 14:20:23 tyleet kernel: [  163.915756] Restarting tasks ... done.
Jun  9 14:20:23 tyleet kernel: [  163.932558] video LNXVIDEO:00: 
Restoring backlight state
Jun  9 14:20:23 tyleet kernel: [  163.974170] [drm:i8xx_irq_handler] 
*ERROR* pipe A underrun
Jun  9 14:20:23 tyleet kernel: [  164.344336] ata1.00: ACPI cmd 
ef/03:0c:00:00:00:a0 (unknown) filtered out
Jun  9 14:20:23 tyleet kernel: [  164.344354] ata1.00: ACPI cmd 
ef/03:45:00:00:00:a0 (unknown) filtered out
Jun  9 14:20:23 tyleet kernel: [  164.344365] ata1.00: ACPI cmd 
f5/00:00:00:00:00:a0 (unknown) filtered out
Jun  9 14:20:23 tyleet kernel: [  164.360367] ata1.00: configured for 
UDMA/100
Jun  9 14:20:24 tyleet kernel: [  164.985747] i2c /dev entries driver
Jun  9 14:20:24 tyleet kernel: [  165.240365] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:24 tyleet kernel: [  165.240393] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:24 tyleet kernel: [  165.240405] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (0 0)
Jun  9 14:20:24 tyleet kernel: [  165.240420] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:24 tyleet kernel: [  165.240431] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:24 tyleet kernel: [  165.240456] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00000000 0 0 8192
Jun  9 14:20:24 tyleet kernel: [  165.256313] 
[drm:drm_mode_getconnector] [CONNECTOR:8:?]
Jun  9 14:20:24 tyleet kernel: [  165.256332] 
[drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:8:VGA-1]
Jun  9 14:20:24 tyleet kernel: [  165.256342] [drm:intel_crt_detect] 
[CONNECTOR:8:VGA-1] force=1
Jun  9 14:20:24 tyleet kernel: [  165.256632] 
[drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 
gmbus vga
Jun  9 14:20:24 tyleet kernel: [  165.256640] [drm:intel_crt_detect_ddc] 
CRT not detected via DDC:0x50 [no valid EDID found]
Jun  9 14:20:24 tyleet kernel: [  165.256649] 
[drm:intel_get_load_detect_pipe] [CONNECTOR:8:VGA-1], [ENCODER:9:DAC-9]
Jun  9 14:20:24 tyleet kernel: [  165.256656] 
[drm:intel_get_load_detect_pipe] no pipe available for load-detect
Jun  9 14:20:24 tyleet kernel: [  165.256929] 
[drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 
gmbus vga
Jun  9 14:20:24 tyleet kernel: [  165.256943] 
[drm:drm_mode_getconnector] [CONNECTOR:8:?]
Jun  9 14:20:24 tyleet kernel: [  165.256951] 
[drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:8:VGA-1]
Jun  9 14:20:24 tyleet kernel: [  165.256958] [drm:intel_crt_detect] 
[CONNECTOR:8:VGA-1] force=1
Jun  9 14:20:24 tyleet kernel: [  165.257229] 
[drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 
gmbus vga
Jun  9 14:20:24 tyleet kernel: [  165.257235] [drm:intel_crt_detect_ddc] 
CRT not detected via DDC:0x50 [no valid EDID found]
Jun  9 14:20:24 tyleet kernel: [  165.257243] 
[drm:intel_get_load_detect_pipe] [CONNECTOR:8:VGA-1], [ENCODER:9:DAC-9]
Jun  9 14:20:24 tyleet kernel: [  165.257249] 
[drm:intel_get_load_detect_pipe] no pipe available for load-detect
Jun  9 14:20:24 tyleet kernel: [  165.257520] 
[drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 
gmbus vga
Jun  9 14:20:24 tyleet kernel: [  165.258248] 
[drm:drm_mode_getconnector] [CONNECTOR:11:?]
Jun  9 14:20:24 tyleet kernel: [  165.258259] 
[drm:drm_helper_probe_single_connector_modes_merge_bits] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:24 tyleet kernel: [  165.258267] [drm:intel_dvo_detect] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:24 tyleet kernel: [  165.258535] 
[drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 
gmbus dpc
Jun  9 14:20:24 tyleet kernel: [  165.258579] [drm:ns2501_mode_valid] is 
mode valid (hdisplay=1024,htotal=1344,vdisplay=768,vtotal=806)
Jun  9 14:20:24 tyleet kernel: [  165.258588] [drm:ns2501_mode_valid] is 
mode valid (hdisplay=800,htotal=1056,vdisplay=600,vtotal=628)
Jun  9 14:20:24 tyleet kernel: [  165.258596] [drm:ns2501_mode_valid] is 
mode valid (hdisplay=640,htotal=800,vdisplay=480,vtotal=525)
Jun  9 14:20:24 tyleet kernel: [  165.258604] [drm:ns2501_mode_valid] is 
mode valid (hdisplay=800,htotal=1024,vdisplay=600,vtotal=625)
Jun  9 14:20:24 tyleet kernel: [  165.258612] [drm:ns2501_mode_valid] is 
mode valid (hdisplay=848,htotal=1088,vdisplay=480,vtotal=517)
Jun  9 14:20:24 tyleet kernel: [  165.258625] 
[drm:drm_mode_debug_printmodeline] Modeline 19:"800x600" 0 36000 800 824 
896 1024 600 601 603 625 0x40 0x5
Jun  9 14:20:24 tyleet kernel: [  165.258633] 
[drm:drm_mode_prune_invalid] Not using 800x600 mode 33
Jun  9 14:20:24 tyleet kernel: [  165.258645] 
[drm:drm_mode_debug_printmodeline] Modeline 21:"848x480" 0 33750 848 864 
976 1088 480 486 494 517 0x40 0x5
Jun  9 14:20:24 tyleet kernel: [  165.258651] 
[drm:drm_mode_prune_invalid] Not using 848x480 mode 33
Jun  9 14:20:24 tyleet kernel: [  165.258661] 
[drm:drm_helper_probe_single_connector_modes_merge_bits] 
[CONNECTOR:11:DVI-I-1] probed modes :
Jun  9 14:20:24 tyleet kernel: [  165.258675] 
[drm:drm_mode_debug_printmodeline] Modeline 16:"1024x768" 60 65000 1024 
1048 1184 1344 768 771 777 806 0x40 0xa
Jun  9 14:20:24 tyleet kernel: [  165.258687] 
[drm:drm_mode_debug_printmodeline] Modeline 14:"800x600" 60 40000 800 
840 968 1056 600 601 605 628 0x40 0x5
Jun  9 14:20:24 tyleet kernel: [  165.258699] 
[drm:drm_mode_debug_printmodeline] Modeline 12:"640x480" 60 25175 640 
656 752 800 480 489 492 525 0x40 0xa
Jun  9 14:20:24 tyleet kernel: [  165.258713] 
[drm:drm_mode_getconnector] [CONNECTOR:11:?]
Jun  9 14:20:24 tyleet kernel: [  165.288983] [drm:i830_get_fifo_size] 
FIFO size - (0x00017e5f) A: 47
Jun  9 14:20:24 tyleet kernel: [  165.289005] [drm:intel_calculate_wm] 
FIFO entries required for mode: 41
Jun  9 14:20:24 tyleet kernel: [  165.289012] [drm:intel_calculate_wm] 
FIFO watermark level: 4
Jun  9 14:20:24 tyleet kernel: [  165.289019] [drm:i830_get_fifo_size] 
FIFO size - (0x00017e5f) B: 48
Jun  9 14:20:24 tyleet kernel: [  165.289027] [drm:i9xx_update_wm] FIFO 
watermarks - A: 9, B: 31
Jun  9 14:20:24 tyleet kernel: [  165.289035] [drm:i9xx_update_wm] 
Setting FIFO watermarks - A: 9, B: 31, C: 2, SR 1
Jun  9 14:20:27 tyleet kernel: [  168.716299] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:27 tyleet kernel: [  168.716324] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:27 tyleet kernel: [  168.716335] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (1 0)
Jun  9 14:20:27 tyleet kernel: [  168.716348] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:27 tyleet kernel: [  168.716357] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:27 tyleet kernel: [  168.716378] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00000004 1 0 8192
Jun  9 14:20:27 tyleet kernel: [  168.717010] 
[drm:intel_crtc_cursor_set] cursor off
Jun  9 14:20:27 tyleet kernel: [  168.724474] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:27 tyleet kernel: [  168.724497] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:27 tyleet kernel: [  168.724508] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (52 0)
Jun  9 14:20:27 tyleet kernel: [  168.724520] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:27 tyleet kernel: [  168.724530] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:27 tyleet kernel: [  168.724558] 
[drm:i9xx_update_primary_plane] Writing base 02000000 000000D0 52 0 8192
Jun  9 14:20:27 tyleet kernel: [  168.733153] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:27 tyleet kernel: [  168.733182] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:27 tyleet kernel: [  168.733193] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (95 0)
Jun  9 14:20:27 tyleet kernel: [  168.733205] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:27 tyleet kernel: [  168.733215] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:27 tyleet kernel: [  168.733241] 
[drm:i9xx_update_primary_plane] Writing base 02000000 0000017C 95 0 8192
Jun  9 14:20:27 tyleet kernel: [  168.741241] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:27 tyleet kernel: [  168.741270] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:27 tyleet kernel: [  168.741281] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (136 0)
Jun  9 14:20:27 tyleet kernel: [  168.741295] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:27 tyleet kernel: [  168.741305] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:27 tyleet kernel: [  168.741333] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00000220 136 0 8192
Jun  9 14:20:27 tyleet kernel: [  168.748466] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:27 tyleet kernel: [  168.748489] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:27 tyleet kernel: [  168.748500] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (173 0)
Jun  9 14:20:27 tyleet kernel: [  168.748513] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:27 tyleet kernel: [  168.748522] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:27 tyleet kernel: [  168.748548] 
[drm:i9xx_update_primary_plane] Writing base 02000000 000002B4 173 0 8192
Jun  9 14:20:27 tyleet kernel: [  168.756477] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:27 tyleet kernel: [  168.756502] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:27 tyleet kernel: [  168.756513] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (202 0)
Jun  9 14:20:27 tyleet kernel: [  168.756525] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:27 tyleet kernel: [  168.756536] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:27 tyleet kernel: [  168.756562] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00000328 202 0 8192
Jun  9 14:20:27 tyleet kernel: [  168.764452] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:27 tyleet kernel: [  168.764475] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:27 tyleet kernel: [  168.764486] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (231 0)
Jun  9 14:20:27 tyleet kernel: [  168.764499] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:27 tyleet kernel: [  168.764509] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:27 tyleet kernel: [  168.764534] 
[drm:i9xx_update_primary_plane] Writing base 02000000 0000039C 231 0 8192
Jun  9 14:20:27 tyleet kernel: [  168.772471] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:27 tyleet kernel: [  168.772494] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:27 tyleet kernel: [  168.772505] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (254 0)
Jun  9 14:20:27 tyleet kernel: [  168.772519] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:27 tyleet kernel: [  168.772528] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:27 tyleet kernel: [  168.772555] 
[drm:i9xx_update_primary_plane] Writing base 02000000 000003F8 254 0 8192
Jun  9 14:20:27 tyleet kernel: [  168.780449] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:27 tyleet kernel: [  168.780472] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:27 tyleet kernel: [  168.780483] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (273 0)
Jun  9 14:20:27 tyleet kernel: [  168.780496] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:27 tyleet kernel: [  168.780506] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:27 tyleet kernel: [  168.780532] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00000444 273 0 8192
Jun  9 14:20:27 tyleet kernel: [  168.788473] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:27 tyleet kernel: [  168.788497] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:27 tyleet kernel: [  168.788509] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (290 0)
Jun  9 14:20:27 tyleet kernel: [  168.788522] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:27 tyleet kernel: [  168.788532] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:27 tyleet kernel: [  168.788558] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00000488 290 0 8192
Jun  9 14:20:27 tyleet kernel: [  168.796447] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:27 tyleet kernel: [  168.796470] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:27 tyleet kernel: [  168.796482] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (307 0)
Jun  9 14:20:27 tyleet kernel: [  168.796493] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:27 tyleet kernel: [  168.796503] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:27 tyleet kernel: [  168.796530] 
[drm:i9xx_update_primary_plane] Writing base 02000000 000004CC 307 0 8192
Jun  9 14:20:27 tyleet kernel: [  168.804482] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:27 tyleet kernel: [  168.804508] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:27 tyleet kernel: [  168.804519] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (318 0)
Jun  9 14:20:27 tyleet kernel: [  168.804532] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:27 tyleet kernel: [  168.804542] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:27 tyleet kernel: [  168.804563] 
[drm:i9xx_update_primary_plane] Writing base 02000000 000004F8 318 0 8192
Jun  9 14:20:27 tyleet kernel: [  168.812447] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:27 tyleet kernel: [  168.812470] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:27 tyleet kernel: [  168.812481] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (329 0)
Jun  9 14:20:27 tyleet kernel: [  168.812493] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:27 tyleet kernel: [  168.812503] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:27 tyleet kernel: [  168.812530] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00000524 329 0 8192
Jun  9 14:20:27 tyleet kernel: [  168.820497] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:27 tyleet kernel: [  168.820520] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:27 tyleet kernel: [  168.820532] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (342 0)
Jun  9 14:20:27 tyleet kernel: [  168.820546] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:27 tyleet kernel: [  168.820555] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:27 tyleet kernel: [  168.820583] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00000558 342 0 8192
Jun  9 14:20:27 tyleet kernel: [  168.828444] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:27 tyleet kernel: [  168.828469] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:27 tyleet kernel: [  168.828480] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (357 0)
Jun  9 14:20:27 tyleet kernel: [  168.828493] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:27 tyleet kernel: [  168.828502] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:27 tyleet kernel: [  168.828529] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00000594 357 0 8192
Jun  9 14:20:27 tyleet kernel: [  168.836472] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:27 tyleet kernel: [  168.836496] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:27 tyleet kernel: [  168.836507] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (372 0)
Jun  9 14:20:27 tyleet kernel: [  168.836519] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:27 tyleet kernel: [  168.836529] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:27 tyleet kernel: [  168.836557] 
[drm:i9xx_update_primary_plane] Writing base 02000000 000005D0 372 0 8192
Jun  9 14:20:27 tyleet kernel: [  168.844453] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:27 tyleet kernel: [  168.844477] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:27 tyleet kernel: [  168.844488] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (387 0)
Jun  9 14:20:27 tyleet kernel: [  168.844500] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:27 tyleet kernel: [  168.844510] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:27 tyleet kernel: [  168.844537] 
[drm:i9xx_update_primary_plane] Writing base 02000000 0000060C 387 0 8192
Jun  9 14:20:27 tyleet kernel: [  168.852468] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:27 tyleet kernel: [  168.852493] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:27 tyleet kernel: [  168.852504] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (406 0)
Jun  9 14:20:27 tyleet kernel: [  168.852517] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:27 tyleet kernel: [  168.852528] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:27 tyleet kernel: [  168.852554] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00000658 406 0 8192
Jun  9 14:20:27 tyleet kernel: [  168.860448] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:27 tyleet kernel: [  168.860471] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:27 tyleet kernel: [  168.860482] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (427 0)
Jun  9 14:20:27 tyleet kernel: [  168.860495] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:27 tyleet kernel: [  168.860505] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:27 tyleet kernel: [  168.860530] 
[drm:i9xx_update_primary_plane] Writing base 02000000 000006AC 427 0 8192
Jun  9 14:20:27 tyleet kernel: [  168.868462] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:27 tyleet kernel: [  168.868485] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:27 tyleet kernel: [  168.868497] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (452 0)
Jun  9 14:20:27 tyleet kernel: [  168.868510] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:27 tyleet kernel: [  168.868520] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:27 tyleet kernel: [  168.868547] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00000710 452 0 8192
Jun  9 14:20:27 tyleet kernel: [  168.876442] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:27 tyleet kernel: [  168.876466] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:27 tyleet kernel: [  168.876477] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (477 0)
Jun  9 14:20:27 tyleet kernel: [  168.876489] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:27 tyleet kernel: [  168.876499] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:27 tyleet kernel: [  168.876525] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00000774 477 0 8192
Jun  9 14:20:27 tyleet kernel: [  168.884452] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:27 tyleet kernel: [  168.884477] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:27 tyleet kernel: [  168.884488] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (502 0)
Jun  9 14:20:27 tyleet kernel: [  168.884501] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:27 tyleet kernel: [  168.884511] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:27 tyleet kernel: [  168.884538] 
[drm:i9xx_update_primary_plane] Writing base 02000000 000007D8 502 0 8192
Jun  9 14:20:27 tyleet kernel: [  168.892465] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:27 tyleet kernel: [  168.892489] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:27 tyleet kernel: [  168.892500] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (525 0)
Jun  9 14:20:27 tyleet kernel: [  168.892513] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:27 tyleet kernel: [  168.892523] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:27 tyleet kernel: [  168.892550] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00000834 525 0 8192
Jun  9 14:20:28 tyleet kernel: [  168.900411] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:28 tyleet kernel: [  168.900434] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:28 tyleet kernel: [  168.900445] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (548 0)
Jun  9 14:20:28 tyleet kernel: [  168.900456] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:28 tyleet kernel: [  168.900466] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:28 tyleet kernel: [  168.900486] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00000890 548 0 8192
Jun  9 14:20:28 tyleet kernel: [  168.908456] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:28 tyleet kernel: [  168.908480] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:28 tyleet kernel: [  168.908491] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (565 0)
Jun  9 14:20:28 tyleet kernel: [  168.908504] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:28 tyleet kernel: [  168.908514] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:28 tyleet kernel: [  168.908541] 
[drm:i9xx_update_primary_plane] Writing base 02000000 000008D4 565 0 8192
Jun  9 14:20:28 tyleet kernel: [  168.916438] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:28 tyleet kernel: [  168.916461] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:28 tyleet kernel: [  168.916473] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (578 0)
Jun  9 14:20:28 tyleet kernel: [  168.916485] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:28 tyleet kernel: [  168.916495] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:28 tyleet kernel: [  168.916521] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00000908 578 0 8192
Jun  9 14:20:28 tyleet kernel: [  168.924448] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:28 tyleet kernel: [  168.924471] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:28 tyleet kernel: [  168.924482] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (589 0)
Jun  9 14:20:28 tyleet kernel: [  168.924496] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:28 tyleet kernel: [  168.924506] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:28 tyleet kernel: [  168.924535] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00000934 589 0 8192
Jun  9 14:20:28 tyleet kernel: [  168.932434] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:28 tyleet kernel: [  168.932457] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:28 tyleet kernel: [  168.932468] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (600 0)
Jun  9 14:20:28 tyleet kernel: [  168.932481] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:28 tyleet kernel: [  168.932491] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:28 tyleet kernel: [  168.932516] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00000960 600 0 8192
Jun  9 14:20:28 tyleet kernel: [  168.940452] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:28 tyleet kernel: [  168.940475] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:28 tyleet kernel: [  168.940487] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (611 0)
Jun  9 14:20:28 tyleet kernel: [  168.940500] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:28 tyleet kernel: [  168.940510] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:28 tyleet kernel: [  168.940537] 
[drm:i9xx_update_primary_plane] Writing base 02000000 0000098C 611 0 8192
Jun  9 14:20:28 tyleet kernel: [  168.948457] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:28 tyleet kernel: [  168.948481] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:28 tyleet kernel: [  168.948492] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (618 0)
Jun  9 14:20:28 tyleet kernel: [  168.948505] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:28 tyleet kernel: [  168.948514] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:28 tyleet kernel: [  168.948540] 
[drm:i9xx_update_primary_plane] Writing base 02000000 000009A8 618 0 8192
Jun  9 14:20:28 tyleet kernel: [  168.949196] 
[drm:intel_crtc_cursor_set] cursor off
Jun  9 14:20:28 tyleet kernel: [  168.956467] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:28 tyleet kernel: [  168.956491] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:28 tyleet kernel: [  168.956502] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (622 0)
Jun  9 14:20:28 tyleet kernel: [  168.956514] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:28 tyleet kernel: [  168.956524] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:28 tyleet kernel: [  168.956550] 
[drm:i9xx_update_primary_plane] Writing base 02000000 000009B8 622 0 8192
Jun  9 14:20:28 tyleet kernel: [  168.957202] 
[drm:intel_crtc_cursor_set] cursor off
Jun  9 14:20:28 tyleet kernel: [  168.964446] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:28 tyleet kernel: [  168.964469] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:28 tyleet kernel: [  168.964480] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (623 0)
Jun  9 14:20:28 tyleet kernel: [  168.964492] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:28 tyleet kernel: [  168.964502] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:28 tyleet kernel: [  168.964527] 
[drm:i9xx_update_primary_plane] Writing base 02000000 000009BC 623 0 8192
Jun  9 14:20:28 tyleet kernel: [  168.965180] 
[drm:intel_crtc_cursor_set] cursor off
Jun  9 14:20:29 tyleet kernel: [  169.940196] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  169.940222] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:29 tyleet kernel: [  169.940233] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (617 0)
Jun  9 14:20:29 tyleet kernel: [  169.940246] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:29 tyleet kernel: [  169.940255] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  169.940279] 
[drm:i9xx_update_primary_plane] Writing base 02000000 000009A4 617 0 8192
Jun  9 14:20:29 tyleet kernel: [  169.948367] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  169.948390] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:29 tyleet kernel: [  169.948401] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (600 0)
Jun  9 14:20:29 tyleet kernel: [  169.948413] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:29 tyleet kernel: [  169.948423] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  169.948448] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00000960 600 0 8192
Jun  9 14:20:29 tyleet kernel: [  169.956468] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  169.956501] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:29 tyleet kernel: [  169.956513] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (583 0)
Jun  9 14:20:29 tyleet kernel: [  169.956526] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:29 tyleet kernel: [  169.956538] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  169.956655] 
[drm:i9xx_update_primary_plane] Writing base 02000000 0000091C 583 0 8192
Jun  9 14:20:29 tyleet kernel: [  169.964375] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  169.964399] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:29 tyleet kernel: [  169.964411] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (562 0)
Jun  9 14:20:29 tyleet kernel: [  169.964422] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:29 tyleet kernel: [  169.964432] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  169.964454] 
[drm:i9xx_update_primary_plane] Writing base 02000000 000008C8 562 0 8192
Jun  9 14:20:29 tyleet kernel: [  169.972376] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  169.972401] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:29 tyleet kernel: [  169.972412] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (545 0)
Jun  9 14:20:29 tyleet kernel: [  169.972425] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:29 tyleet kernel: [  169.972434] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  169.972462] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00000884 545 0 8192
Jun  9 14:20:29 tyleet kernel: [  169.980358] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  169.980381] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:29 tyleet kernel: [  169.980392] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (528 0)
Jun  9 14:20:29 tyleet kernel: [  169.980404] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:29 tyleet kernel: [  169.980414] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  169.980440] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00000840 528 0 8192
Jun  9 14:20:29 tyleet kernel: [  169.988393] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  169.988418] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:29 tyleet kernel: [  169.988429] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (507 0)
Jun  9 14:20:29 tyleet kernel: [  169.988442] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:29 tyleet kernel: [  169.988452] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  169.988479] 
[drm:i9xx_update_primary_plane] Writing base 02000000 000007EC 507 0 8192
Jun  9 14:20:29 tyleet kernel: [  169.996350] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  169.996373] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:29 tyleet kernel: [  169.996383] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (484 0)
Jun  9 14:20:29 tyleet kernel: [  169.996396] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:29 tyleet kernel: [  169.996406] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  169.996431] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00000790 484 0 8192
Jun  9 14:20:29 tyleet kernel: [  170.006782] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  170.006810] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:29 tyleet kernel: [  170.006821] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (463 0)
Jun  9 14:20:29 tyleet kernel: [  170.006834] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:29 tyleet kernel: [  170.006844] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  170.006873] 
[drm:i9xx_update_primary_plane] Writing base 02000000 0000073C 463 0 8192
Jun  9 14:20:29 tyleet kernel: [  170.012353] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  170.012378] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:29 tyleet kernel: [  170.012389] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (442 0)
Jun  9 14:20:29 tyleet kernel: [  170.012401] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:29 tyleet kernel: [  170.012411] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  170.012432] 
[drm:i9xx_update_primary_plane] Writing base 02000000 000006E8 442 0 8192
Jun  9 14:20:29 tyleet kernel: [  170.020363] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  170.020387] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:29 tyleet kernel: [  170.020398] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (419 0)
Jun  9 14:20:29 tyleet kernel: [  170.020410] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:29 tyleet kernel: [  170.020420] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  170.020445] 
[drm:i9xx_update_primary_plane] Writing base 02000000 0000068C 419 0 8192
Jun  9 14:20:29 tyleet kernel: [  170.028339] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  170.028361] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:29 tyleet kernel: [  170.028372] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (396 0)
Jun  9 14:20:29 tyleet kernel: [  170.028385] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:29 tyleet kernel: [  170.028395] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  170.028419] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00000630 396 0 8192
Jun  9 14:20:29 tyleet kernel: [  170.036352] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  170.036374] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:29 tyleet kernel: [  170.036384] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (369 0)
Jun  9 14:20:29 tyleet kernel: [  170.036396] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:29 tyleet kernel: [  170.036406] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  170.036433] 
[drm:i9xx_update_primary_plane] Writing base 02000000 000005C4 369 0 8192
Jun  9 14:20:29 tyleet kernel: [  170.044336] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  170.044358] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:29 tyleet kernel: [  170.044369] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (342 0)
Jun  9 14:20:29 tyleet kernel: [  170.044381] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:29 tyleet kernel: [  170.044391] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  170.044415] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00000558 342 0 8192
Jun  9 14:20:29 tyleet kernel: [  170.052371] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  170.052395] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:29 tyleet kernel: [  170.052406] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (315 0)
Jun  9 14:20:29 tyleet kernel: [  170.052418] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:29 tyleet kernel: [  170.052428] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  170.052450] 
[drm:i9xx_update_primary_plane] Writing base 02000000 000004EC 315 0 8192
Jun  9 14:20:29 tyleet kernel: [  170.060388] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  170.060412] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:29 tyleet kernel: [  170.060423] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (288 0)
Jun  9 14:20:29 tyleet kernel: [  170.060435] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:29 tyleet kernel: [  170.060445] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  170.060467] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00000480 288 0 8192
Jun  9 14:20:29 tyleet kernel: [  170.068503] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  170.068525] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:29 tyleet kernel: [  170.068537] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (261 0)
Jun  9 14:20:29 tyleet kernel: [  170.068550] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:29 tyleet kernel: [  170.068560] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  170.068584] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00000414 261 0 8192
Jun  9 14:20:29 tyleet kernel: [  170.076339] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  170.076362] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:29 tyleet kernel: [  170.076373] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (236 0)
Jun  9 14:20:29 tyleet kernel: [  170.076385] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:29 tyleet kernel: [  170.076395] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  170.076418] 
[drm:i9xx_update_primary_plane] Writing base 02000000 000003B0 236 0 8192
Jun  9 14:20:29 tyleet kernel: [  170.084350] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  170.084373] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:29 tyleet kernel: [  170.084384] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (213 0)
Jun  9 14:20:29 tyleet kernel: [  170.084396] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:29 tyleet kernel: [  170.084407] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  170.084428] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00000354 213 0 8192
Jun  9 14:20:29 tyleet kernel: [  170.092348] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  170.092370] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:29 tyleet kernel: [  170.092381] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (194 0)
Jun  9 14:20:29 tyleet kernel: [  170.092394] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:29 tyleet kernel: [  170.092403] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  170.092427] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00000308 194 0 8192
Jun  9 14:20:29 tyleet kernel: [  170.100301] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  170.100321] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:29 tyleet kernel: [  170.100332] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (175 0)
Jun  9 14:20:29 tyleet kernel: [  170.100343] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:29 tyleet kernel: [  170.100353] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  170.100374] 
[drm:i9xx_update_primary_plane] Writing base 02000000 000002BC 175 0 8192
Jun  9 14:20:29 tyleet kernel: [  170.108353] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  170.108376] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:29 tyleet kernel: [  170.108387] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (158 0)
Jun  9 14:20:29 tyleet kernel: [  170.108400] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:29 tyleet kernel: [  170.108410] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  170.108431] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00000278 158 0 8192
Jun  9 14:20:29 tyleet kernel: [  170.116332] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  170.116354] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:29 tyleet kernel: [  170.116365] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (141 0)
Jun  9 14:20:29 tyleet kernel: [  170.116377] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:29 tyleet kernel: [  170.116387] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  170.116409] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00000234 141 0 8192
Jun  9 14:20:29 tyleet kernel: [  170.124356] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  170.124379] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:29 tyleet kernel: [  170.124389] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (124 0)
Jun  9 14:20:29 tyleet kernel: [  170.124402] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:29 tyleet kernel: [  170.124412] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  170.124435] 
[drm:i9xx_update_primary_plane] Writing base 02000000 000001F0 124 0 8192
Jun  9 14:20:29 tyleet kernel: [  170.133085] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  170.133113] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:29 tyleet kernel: [  170.133123] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (105 0)
Jun  9 14:20:29 tyleet kernel: [  170.133136] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:29 tyleet kernel: [  170.133145] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  170.133166] 
[drm:i9xx_update_primary_plane] Writing base 02000000 000001A4 105 0 8192
Jun  9 14:20:29 tyleet kernel: [  170.140415] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  170.140438] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:29 tyleet kernel: [  170.140449] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (88 0)
Jun  9 14:20:29 tyleet kernel: [  170.140462] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:29 tyleet kernel: [  170.140471] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  170.140495] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00000160 88 0 8192
Jun  9 14:20:29 tyleet kernel: [  170.148788] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  170.148814] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:29 tyleet kernel: [  170.148825] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (73 0)
Jun  9 14:20:29 tyleet kernel: [  170.148838] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:29 tyleet kernel: [  170.148849] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  170.148962] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00000124 73 0 8192
Jun  9 14:20:29 tyleet kernel: [  170.156533] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  170.156563] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:29 tyleet kernel: [  170.156574] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (58 0)
Jun  9 14:20:29 tyleet kernel: [  170.156587] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:29 tyleet kernel: [  170.156596] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  170.156618] 
[drm:i9xx_update_primary_plane] Writing base 02000000 000000E8 58 0 8192
Jun  9 14:20:29 tyleet kernel: [  170.164428] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  170.164454] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:29 tyleet kernel: [  170.164466] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (45 0)
Jun  9 14:20:29 tyleet kernel: [  170.164477] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:29 tyleet kernel: [  170.164487] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  170.164512] 
[drm:i9xx_update_primary_plane] Writing base 02000000 000000B4 45 0 8192
Jun  9 14:20:29 tyleet kernel: [  170.172366] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  170.172390] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:29 tyleet kernel: [  170.172401] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (34 0)
Jun  9 14:20:29 tyleet kernel: [  170.172413] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:29 tyleet kernel: [  170.172424] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  170.172443] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00000088 34 0 8192
Jun  9 14:20:29 tyleet kernel: [  170.180342] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  170.180365] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:29 tyleet kernel: [  170.180376] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (27 0)
Jun  9 14:20:29 tyleet kernel: [  170.180389] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:29 tyleet kernel: [  170.180398] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  170.180421] 
[drm:i9xx_update_primary_plane] Writing base 02000000 0000006C 27 0 8192
Jun  9 14:20:29 tyleet kernel: [  170.188367] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  170.188392] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:29 tyleet kernel: [  170.188403] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (21 0)
Jun  9 14:20:29 tyleet kernel: [  170.188415] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:29 tyleet kernel: [  170.188425] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  170.188449] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00000054 21 0 8192
Jun  9 14:20:29 tyleet kernel: [  170.196353] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  170.196377] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:29 tyleet kernel: [  170.196388] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (12 0)
Jun  9 14:20:29 tyleet kernel: [  170.196399] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:29 tyleet kernel: [  170.196409] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  170.196434] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00000030 12 0 8192
Jun  9 14:20:29 tyleet kernel: [  170.204361] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  170.204384] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:29 tyleet kernel: [  170.204395] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (3 0)
Jun  9 14:20:29 tyleet kernel: [  170.204407] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:29 tyleet kernel: [  170.204417] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  170.204441] 
[drm:i9xx_update_primary_plane] Writing base 02000000 0000000C 3 0 8192
Jun  9 14:20:29 tyleet kernel: [  170.212340] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  170.212362] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:29 tyleet kernel: [  170.212373] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (0 0)
Jun  9 14:20:29 tyleet kernel: [  170.212386] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:29 tyleet kernel: [  170.212395] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:29 tyleet kernel: [  170.212419] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00000000 0 0 8192
Jun  9 14:20:32 tyleet kernel: [  173.632089] [drm:intel_crt_detect] 
[CONNECTOR:8:VGA-1] force=0
Jun  9 14:20:32 tyleet kernel: [  173.632387] 
[drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 
gmbus vga
Jun  9 14:20:32 tyleet kernel: [  173.632396] [drm:intel_crt_detect_ddc] 
CRT not detected via DDC:0x50 [no valid EDID found]
Jun  9 14:20:33 tyleet kernel: [  173.972816] ipw2100: exit - failed to 
send CARD_DISABLE command
Jun  9 14:20:35 tyleet kernel: [  176.531532] 
[drm:intel_crtc_cursor_set] cursor off
Jun  9 14:20:35 tyleet kernel: [  176.531775] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:35 tyleet kernel: [  176.531793] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:35 tyleet kernel: [  176.531804] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (0 19)
Jun  9 14:20:35 tyleet kernel: [  176.531815] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:35 tyleet kernel: [  176.531825] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:35 tyleet kernel: [  176.531848] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00026000 0 19 8192
Jun  9 14:20:35 tyleet kernel: [  176.539770] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:35 tyleet kernel: [  176.539795] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:35 tyleet kernel: [  176.539806] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (0 44)
Jun  9 14:20:35 tyleet kernel: [  176.539819] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:35 tyleet kernel: [  176.539829] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:35 tyleet kernel: [  176.539853] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00058000 0 44 8192
Jun  9 14:20:35 tyleet kernel: [  176.547727] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:35 tyleet kernel: [  176.547752] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:35 tyleet kernel: [  176.547763] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (0 71)
Jun  9 14:20:35 tyleet kernel: [  176.547775] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:35 tyleet kernel: [  176.547785] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:35 tyleet kernel: [  176.547807] 
[drm:i9xx_update_primary_plane] Writing base 02000000 0008E000 0 71 8192
Jun  9 14:20:35 tyleet kernel: [  176.555772] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:35 tyleet kernel: [  176.555797] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:35 tyleet kernel: [  176.555808] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (0 102)
Jun  9 14:20:35 tyleet kernel: [  176.555821] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:35 tyleet kernel: [  176.555831] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:35 tyleet kernel: [  176.555855] 
[drm:i9xx_update_primary_plane] Writing base 02000000 000CC000 0 102 8192
Jun  9 14:20:35 tyleet kernel: [  176.563753] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:35 tyleet kernel: [  176.563778] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:35 tyleet kernel: [  176.563788] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (0 135)
Jun  9 14:20:35 tyleet kernel: [  176.563800] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:35 tyleet kernel: [  176.563811] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:35 tyleet kernel: [  176.563833] 
[drm:i9xx_update_primary_plane] Writing base 02000000 0010E000 0 135 8192
Jun  9 14:20:35 tyleet kernel: [  176.571793] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:35 tyleet kernel: [  176.571818] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:35 tyleet kernel: [  176.571830] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (0 170)
Jun  9 14:20:35 tyleet kernel: [  176.571842] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:35 tyleet kernel: [  176.571853] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:35 tyleet kernel: [  176.571876] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00154000 0 170 8192
Jun  9 14:20:35 tyleet kernel: [  176.579734] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:35 tyleet kernel: [  176.579758] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:35 tyleet kernel: [  176.579769] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (0 213)
Jun  9 14:20:35 tyleet kernel: [  176.579781] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:35 tyleet kernel: [  176.579791] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:35 tyleet kernel: [  176.579813] 
[drm:i9xx_update_primary_plane] Writing base 02000000 001AA000 0 213 8192
Jun  9 14:20:35 tyleet kernel: [  176.587735] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:35 tyleet kernel: [  176.587761] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:35 tyleet kernel: [  176.587771] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (0 258)
Jun  9 14:20:35 tyleet kernel: [  176.587783] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:35 tyleet kernel: [  176.587793] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:35 tyleet kernel: [  176.587813] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00204000 0 258 8192
Jun  9 14:20:35 tyleet kernel: [  176.595748] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:35 tyleet kernel: [  176.595774] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:35 tyleet kernel: [  176.595784] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (0 303)
Jun  9 14:20:35 tyleet kernel: [  176.595797] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:35 tyleet kernel: [  176.595807] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:35 tyleet kernel: [  176.595829] 
[drm:i9xx_update_primary_plane] Writing base 02000000 0025E000 0 303 8192
Jun  9 14:20:35 tyleet kernel: [  176.603747] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:35 tyleet kernel: [  176.603772] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:35 tyleet kernel: [  176.603783] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (0 348)
Jun  9 14:20:35 tyleet kernel: [  176.603795] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:35 tyleet kernel: [  176.603805] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:35 tyleet kernel: [  176.603827] 
[drm:i9xx_update_primary_plane] Writing base 02000000 002B8000 0 348 8192
Jun  9 14:20:35 tyleet kernel: [  176.611750] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:35 tyleet kernel: [  176.611775] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:35 tyleet kernel: [  176.611785] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (0 393)
Jun  9 14:20:35 tyleet kernel: [  176.611798] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:35 tyleet kernel: [  176.611807] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:35 tyleet kernel: [  176.611830] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00312000 0 393 8192
Jun  9 14:20:35 tyleet kernel: [  176.619729] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:35 tyleet kernel: [  176.619754] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:35 tyleet kernel: [  176.619765] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (0 434)
Jun  9 14:20:35 tyleet kernel: [  176.619778] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:35 tyleet kernel: [  176.619787] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:35 tyleet kernel: [  176.619809] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00364000 0 434 8192
Jun  9 14:20:35 tyleet kernel: [  176.627720] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:35 tyleet kernel: [  176.627745] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:35 tyleet kernel: [  176.627756] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (0 475)
Jun  9 14:20:35 tyleet kernel: [  176.627768] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:35 tyleet kernel: [  176.627777] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:35 tyleet kernel: [  176.627798] 
[drm:i9xx_update_primary_plane] Writing base 02000000 003B6000 0 475 8192
Jun  9 14:20:35 tyleet kernel: [  176.635750] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:35 tyleet kernel: [  176.635775] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:35 tyleet kernel: [  176.635786] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (0 516)
Jun  9 14:20:35 tyleet kernel: [  176.635798] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:35 tyleet kernel: [  176.635808] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:35 tyleet kernel: [  176.635831] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00408000 0 516 8192
Jun  9 14:20:35 tyleet kernel: [  176.643744] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:35 tyleet kernel: [  176.643769] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:35 tyleet kernel: [  176.643780] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (0 551)
Jun  9 14:20:35 tyleet kernel: [  176.643792] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:35 tyleet kernel: [  176.643802] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:35 tyleet kernel: [  176.643824] 
[drm:i9xx_update_primary_plane] Writing base 02000000 0044E000 0 551 8192
Jun  9 14:20:35 tyleet kernel: [  176.651744] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:35 tyleet kernel: [  176.651769] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:35 tyleet kernel: [  176.651780] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (0 586)
Jun  9 14:20:35 tyleet kernel: [  176.651791] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:35 tyleet kernel: [  176.651801] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:35 tyleet kernel: [  176.651824] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00494000 0 586 8192
Jun  9 14:20:35 tyleet kernel: [  176.659723] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:35 tyleet kernel: [  176.659748] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:35 tyleet kernel: [  176.659759] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (0 621)
Jun  9 14:20:35 tyleet kernel: [  176.659771] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:35 tyleet kernel: [  176.659781] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:35 tyleet kernel: [  176.659803] 
[drm:i9xx_update_primary_plane] Writing base 02000000 004DA000 0 621 8192
Jun  9 14:20:35 tyleet kernel: [  176.667742] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:35 tyleet kernel: [  176.667767] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:35 tyleet kernel: [  176.667778] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (0 656)
Jun  9 14:20:35 tyleet kernel: [  176.667790] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:35 tyleet kernel: [  176.667800] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:35 tyleet kernel: [  176.667822] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00520000 0 656 8192
Jun  9 14:20:35 tyleet kernel: [  176.675742] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:35 tyleet kernel: [  176.675768] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:35 tyleet kernel: [  176.675779] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (0 687)
Jun  9 14:20:35 tyleet kernel: [  176.675791] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:35 tyleet kernel: [  176.675801] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:35 tyleet kernel: [  176.675822] 
[drm:i9xx_update_primary_plane] Writing base 02000000 0055E000 0 687 8192
Jun  9 14:20:35 tyleet kernel: [  176.683732] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:35 tyleet kernel: [  176.683757] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:35 tyleet kernel: [  176.683768] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (0 716)
Jun  9 14:20:35 tyleet kernel: [  176.683780] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:35 tyleet kernel: [  176.683790] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:35 tyleet kernel: [  176.683811] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00598000 0 716 8192
Jun  9 14:20:35 tyleet kernel: [  176.691799] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:35 tyleet kernel: [  176.691824] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:35 tyleet kernel: [  176.691835] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (0 745)
Jun  9 14:20:35 tyleet kernel: [  176.691847] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:35 tyleet kernel: [  176.691857] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:35 tyleet kernel: [  176.691880] 
[drm:i9xx_update_primary_plane] Writing base 02000000 005D2000 0 745 8192
Jun  9 14:20:35 tyleet kernel: [  176.699760] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:35 tyleet kernel: [  176.699786] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:35 tyleet kernel: [  176.699797] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (0 768)
Jun  9 14:20:35 tyleet kernel: [  176.699810] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:35 tyleet kernel: [  176.699819] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:35 tyleet kernel: [  176.699840] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00600000 0 768 8192
Jun  9 14:20:36 tyleet kernel: [  177.163460] 
[drm:intel_crtc_cursor_set] cursor off
Jun  9 14:20:36 tyleet kernel: [  177.164811] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:36 tyleet kernel: [  177.164835] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:36 tyleet kernel: [  177.164846] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (0 704)
Jun  9 14:20:36 tyleet kernel: [  177.164860] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:36 tyleet kernel: [  177.164870] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:36 tyleet kernel: [  177.164891] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00580000 0 704 8192
Jun  9 14:20:36 tyleet kernel: [  177.171484] 
[drm:intel_crtc_cursor_set] cursor off
Jun  9 14:20:36 tyleet kernel: [  177.171750] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:36 tyleet kernel: [  177.171769] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:36 tyleet kernel: [  177.171781] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (0 629)
Jun  9 14:20:36 tyleet kernel: [  177.171793] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:36 tyleet kernel: [  177.171803] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:36 tyleet kernel: [  177.171826] 
[drm:i9xx_update_primary_plane] Writing base 02000000 004EA000 0 629 8192
Jun  9 14:20:36 tyleet kernel: [  177.179474] 
[drm:intel_crtc_cursor_set] cursor off
Jun  9 14:20:36 tyleet kernel: [  177.180767] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:36 tyleet kernel: [  177.180791] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:36 tyleet kernel: [  177.180803] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (0 564)
Jun  9 14:20:36 tyleet kernel: [  177.180816] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:36 tyleet kernel: [  177.180826] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:36 tyleet kernel: [  177.180848] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00468000 0 564 8192
Jun  9 14:20:36 tyleet kernel: [  177.187452] 
[drm:intel_crtc_cursor_set] cursor off
Jun  9 14:20:36 tyleet kernel: [  177.187705] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:36 tyleet kernel: [  177.187725] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:36 tyleet kernel: [  177.187736] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (0 495)
Jun  9 14:20:36 tyleet kernel: [  177.187748] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:36 tyleet kernel: [  177.187758] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:36 tyleet kernel: [  177.187780] 
[drm:i9xx_update_primary_plane] Writing base 02000000 003DE000 0 495 8192
Jun  9 14:20:36 tyleet kernel: [  177.195467] 
[drm:intel_crtc_cursor_set] cursor off
Jun  9 14:20:36 tyleet kernel: [  177.195716] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:36 tyleet kernel: [  177.195733] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:36 tyleet kernel: [  177.195745] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (0 442)
Jun  9 14:20:36 tyleet kernel: [  177.195757] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:36 tyleet kernel: [  177.195767] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:36 tyleet kernel: [  177.195789] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00374000 0 442 8192
Jun  9 14:20:36 tyleet kernel: [  177.203471] 
[drm:intel_crtc_cursor_set] cursor off
Jun  9 14:20:36 tyleet kernel: [  177.203723] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:36 tyleet kernel: [  177.203742] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:36 tyleet kernel: [  177.203752] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (0 389)
Jun  9 14:20:36 tyleet kernel: [  177.203765] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:36 tyleet kernel: [  177.203774] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:36 tyleet kernel: [  177.203796] 
[drm:i9xx_update_primary_plane] Writing base 02000000 0030A000 0 389 8192
Jun  9 14:20:36 tyleet kernel: [  177.211704] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:36 tyleet kernel: [  177.211728] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:36 tyleet kernel: [  177.211739] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (0 342)
Jun  9 14:20:36 tyleet kernel: [  177.211752] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:36 tyleet kernel: [  177.211761] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:36 tyleet kernel: [  177.211783] 
[drm:i9xx_update_primary_plane] Writing base 02000000 002AC000 0 342 8192
Jun  9 14:20:36 tyleet kernel: [  177.219683] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:36 tyleet kernel: [  177.219708] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:36 tyleet kernel: [  177.219719] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (0 295)
Jun  9 14:20:36 tyleet kernel: [  177.219731] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:36 tyleet kernel: [  177.219741] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:36 tyleet kernel: [  177.219762] 
[drm:i9xx_update_primary_plane] Writing base 02000000 0024E000 0 295 8192
Jun  9 14:20:36 tyleet kernel: [  177.227439] 
[drm:intel_crtc_cursor_set] cursor off
Jun  9 14:20:36 tyleet kernel: [  177.227692] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:36 tyleet kernel: [  177.227711] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:36 tyleet kernel: [  177.227722] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (0 246)
Jun  9 14:20:36 tyleet kernel: [  177.227734] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:36 tyleet kernel: [  177.227744] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:36 tyleet kernel: [  177.227767] 
[drm:i9xx_update_primary_plane] Writing base 02000000 001EC000 0 246 8192
Jun  9 14:20:36 tyleet kernel: [  177.235479] 
[drm:intel_crtc_cursor_set] cursor off
Jun  9 14:20:36 tyleet kernel: [  177.235738] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:36 tyleet kernel: [  177.235757] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:36 tyleet kernel: [  177.235768] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (0 197)
Jun  9 14:20:36 tyleet kernel: [  177.235780] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:36 tyleet kernel: [  177.235790] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:36 tyleet kernel: [  177.235812] 
[drm:i9xx_update_primary_plane] Writing base 02000000 0018A000 0 197 8192
Jun  9 14:20:36 tyleet kernel: [  177.243700] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:36 tyleet kernel: [  177.243725] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:36 tyleet kernel: [  177.243736] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (0 150)
Jun  9 14:20:36 tyleet kernel: [  177.243749] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:36 tyleet kernel: [  177.243758] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:36 tyleet kernel: [  177.243780] 
[drm:i9xx_update_primary_plane] Writing base 02000000 0012C000 0 150 8192
Jun  9 14:20:36 tyleet kernel: [  177.251729] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:36 tyleet kernel: [  177.251755] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:36 tyleet kernel: [  177.251766] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (0 107)
Jun  9 14:20:36 tyleet kernel: [  177.251778] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:36 tyleet kernel: [  177.251788] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:36 tyleet kernel: [  177.251810] 
[drm:i9xx_update_primary_plane] Writing base 02000000 000D6000 0 107 8192
Jun  9 14:20:36 tyleet kernel: [  177.260413] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:36 tyleet kernel: [  177.260440] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:36 tyleet kernel: [  177.260451] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (0 70)
Jun  9 14:20:36 tyleet kernel: [  177.260464] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:36 tyleet kernel: [  177.260474] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:36 tyleet kernel: [  177.260496] 
[drm:i9xx_update_primary_plane] Writing base 02000000 0008C000 0 70 8192
Jun  9 14:20:36 tyleet kernel: [  177.268472] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:36 tyleet kernel: [  177.268500] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:36 tyleet kernel: [  177.268511] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (0 45)
Jun  9 14:20:36 tyleet kernel: [  177.268524] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:36 tyleet kernel: [  177.268534] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:36 tyleet kernel: [  177.268557] 
[drm:i9xx_update_primary_plane] Writing base 02000000 0005A000 0 45 8192
Jun  9 14:20:36 tyleet kernel: [  177.275734] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:36 tyleet kernel: [  177.275758] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:36 tyleet kernel: [  177.275769] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (0 20)
Jun  9 14:20:36 tyleet kernel: [  177.275782] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:36 tyleet kernel: [  177.275791] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:36 tyleet kernel: [  177.275813] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00028000 0 20 8192
Jun  9 14:20:36 tyleet kernel: [  177.283822] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:36 tyleet kernel: [  177.283848] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:36 tyleet kernel: [  177.283858] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (0 0)
Jun  9 14:20:36 tyleet kernel: [  177.283870] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:36 tyleet kernel: [  177.283880] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:36 tyleet kernel: [  177.283899] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00000000 0 0 8192
Jun  9 14:20:42 tyleet kernel: [  183.648061] [drm:intel_crt_detect] 
[CONNECTOR:8:VGA-1] force=0
Jun  9 14:20:42 tyleet kernel: [  183.648351] 
[drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 
gmbus vga
Jun  9 14:20:42 tyleet kernel: [  183.648358] [drm:intel_crt_detect_ddc] 
CRT not detected via DDC:0x50 [no valid EDID found]
Jun  9 14:20:44 tyleet kernel: [  185.562591] 
[drm:intel_crtc_cursor_set] cursor off
Jun  9 14:20:44 tyleet kernel: [  185.563574] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:44 tyleet kernel: [  185.563603] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:44 tyleet kernel: [  185.563615] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (58 0)
Jun  9 14:20:44 tyleet kernel: [  185.563627] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:44 tyleet kernel: [  185.563637] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:44 tyleet kernel: [  185.563659] 
[drm:i9xx_update_primary_plane] Writing base 02000000 000000E8 58 0 8192
Jun  9 14:20:44 tyleet kernel: [  185.570938] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:44 tyleet kernel: [  185.570964] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:44 tyleet kernel: [  185.570975] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (151 0)
Jun  9 14:20:44 tyleet kernel: [  185.570987] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:44 tyleet kernel: [  185.570997] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:44 tyleet kernel: [  185.571017] 
[drm:i9xx_update_primary_plane] Writing base 02000000 0000025C 151 0 8192
Jun  9 14:20:44 tyleet kernel: [  185.578944] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:44 tyleet kernel: [  185.578967] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:44 tyleet kernel: [  185.578978] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (252 0)
Jun  9 14:20:44 tyleet kernel: [  185.578990] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:44 tyleet kernel: [  185.579000] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:44 tyleet kernel: [  185.579023] 
[drm:i9xx_update_primary_plane] Writing base 02000000 000003F0 252 0 8192
Jun  9 14:20:44 tyleet kernel: [  185.586960] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:44 tyleet kernel: [  185.586984] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:44 tyleet kernel: [  185.586995] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (353 0)
Jun  9 14:20:44 tyleet kernel: [  185.587008] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:44 tyleet kernel: [  185.587018] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:44 tyleet kernel: [  185.587040] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00000584 353 0 8192
Jun  9 14:20:44 tyleet kernel: [  185.594950] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:44 tyleet kernel: [  185.594973] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:44 tyleet kernel: [  185.594984] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (434 0)
Jun  9 14:20:44 tyleet kernel: [  185.594997] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:44 tyleet kernel: [  185.595007] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:44 tyleet kernel: [  185.595030] 
[drm:i9xx_update_primary_plane] Writing base 02000000 000006C8 434 0 8192
Jun  9 14:20:44 tyleet kernel: [  185.602956] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:44 tyleet kernel: [  185.602981] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:44 tyleet kernel: [  185.602992] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (505 0)
Jun  9 14:20:44 tyleet kernel: [  185.603005] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:44 tyleet kernel: [  185.603015] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:44 tyleet kernel: [  185.603039] 
[drm:i9xx_update_primary_plane] Writing base 02000000 000007E4 505 0 8192
Jun  9 14:20:44 tyleet kernel: [  185.610946] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:44 tyleet kernel: [  185.610969] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:44 tyleet kernel: [  185.610980] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (562 0)
Jun  9 14:20:44 tyleet kernel: [  185.610993] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:44 tyleet kernel: [  185.611003] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:44 tyleet kernel: [  185.611025] 
[drm:i9xx_update_primary_plane] Writing base 02000000 000008C8 562 0 8192
Jun  9 14:20:44 tyleet kernel: [  185.618961] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:44 tyleet kernel: [  185.618984] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:44 tyleet kernel: [  185.618995] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (597 0)
Jun  9 14:20:44 tyleet kernel: [  185.619008] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:44 tyleet kernel: [  185.619018] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:44 tyleet kernel: [  185.619041] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00000954 597 0 8192
Jun  9 14:20:44 tyleet kernel: [  185.626946] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:44 tyleet kernel: [  185.626969] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:44 tyleet kernel: [  185.626979] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (620 0)
Jun  9 14:20:44 tyleet kernel: [  185.626992] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:44 tyleet kernel: [  185.627002] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:44 tyleet kernel: [  185.627025] 
[drm:i9xx_update_primary_plane] Writing base 02000000 000009B0 620 0 8192
Jun  9 14:20:44 tyleet kernel: [  185.634939] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:44 tyleet kernel: [  185.634962] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:44 tyleet kernel: [  185.634973] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (631 0)
Jun  9 14:20:44 tyleet kernel: [  185.634987] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:44 tyleet kernel: [  185.634997] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:44 tyleet kernel: [  185.635021] 
[drm:i9xx_update_primary_plane] Writing base 02000000 000009DC 631 0 8192
Jun  9 14:20:44 tyleet kernel: [  185.642954] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:44 tyleet kernel: [  185.642976] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:44 tyleet kernel: [  185.642987] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (636 0)
Jun  9 14:20:44 tyleet kernel: [  185.643000] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:44 tyleet kernel: [  185.643009] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:44 tyleet kernel: [  185.643032] 
[drm:i9xx_update_primary_plane] Writing base 02000000 000009F0 636 0 8192
Jun  9 14:20:44 tyleet kernel: [  185.643673] 
[drm:intel_crtc_cursor_set] cursor off
Jun  9 14:20:44 tyleet kernel: [  185.650975] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:44 tyleet kernel: [  185.650999] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:44 tyleet kernel: [  185.651010] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (637 0)
Jun  9 14:20:44 tyleet kernel: [  185.651022] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:44 tyleet kernel: [  185.651032] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:44 tyleet kernel: [  185.651055] 
[drm:i9xx_update_primary_plane] Writing base 02000000 000009F4 637 0 8192
Jun  9 14:20:44 tyleet kernel: [  185.651708] 
[drm:intel_crtc_cursor_set] cursor off
Jun  9 14:20:44 tyleet kernel: [  185.658925] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:44 tyleet kernel: [  185.658947] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:44 tyleet kernel: [  185.658958] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (638 0)
Jun  9 14:20:44 tyleet kernel: [  185.658971] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:44 tyleet kernel: [  185.658981] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:44 tyleet kernel: [  185.659004] 
[drm:i9xx_update_primary_plane] Writing base 02000000 000009F8 638 0 8192
Jun  9 14:20:44 tyleet kernel: [  185.659643] 
[drm:intel_crtc_cursor_set] cursor off
Jun  9 14:20:45 tyleet kernel: [  185.938738] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:45 tyleet kernel: [  185.938763] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:45 tyleet kernel: [  185.938774] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (592 0)
Jun  9 14:20:45 tyleet kernel: [  185.938787] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:45 tyleet kernel: [  185.938797] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:45 tyleet kernel: [  185.938820] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00000940 592 0 8192
Jun  9 14:20:45 tyleet kernel: [  185.946697] 
[drm:intel_crtc_cursor_set] cursor off
Jun  9 14:20:45 tyleet kernel: [  185.946956] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:45 tyleet kernel: [  185.946976] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:45 tyleet kernel: [  185.946986] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (537 0)
Jun  9 14:20:45 tyleet kernel: [  185.946999] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:45 tyleet kernel: [  185.947009] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:45 tyleet kernel: [  185.947031] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00000864 537 0 8192
Jun  9 14:20:45 tyleet kernel: [  185.954636] 
[drm:intel_crtc_cursor_set] cursor off
Jun  9 14:20:45 tyleet kernel: [  185.955019] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:45 tyleet kernel: [  185.955040] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:45 tyleet kernel: [  185.955051] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (482 0)
Jun  9 14:20:45 tyleet kernel: [  185.955064] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:45 tyleet kernel: [  185.955074] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:45 tyleet kernel: [  185.955094] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00000788 482 0 8192
Jun  9 14:20:45 tyleet kernel: [  185.962918] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:45 tyleet kernel: [  185.962943] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:45 tyleet kernel: [  185.962953] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (435 0)
Jun  9 14:20:45 tyleet kernel: [  185.962966] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:45 tyleet kernel: [  185.962976] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:45 tyleet kernel: [  185.962995] 
[drm:i9xx_update_primary_plane] Writing base 02000000 000006CC 435 0 8192
Jun  9 14:20:45 tyleet kernel: [  185.970934] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:45 tyleet kernel: [  185.970958] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:45 tyleet kernel: [  185.970968] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (394 0)
Jun  9 14:20:45 tyleet kernel: [  185.970981] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:45 tyleet kernel: [  185.970991] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:45 tyleet kernel: [  185.971014] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00000628 394 0 8192
Jun  9 14:20:45 tyleet kernel: [  185.978898] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:45 tyleet kernel: [  185.978921] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:45 tyleet kernel: [  185.978932] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (367 0)
Jun  9 14:20:45 tyleet kernel: [  185.978944] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:45 tyleet kernel: [  185.978954] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:45 tyleet kernel: [  185.978975] 
[drm:i9xx_update_primary_plane] Writing base 02000000 000005BC 367 0 8192
Jun  9 14:20:45 tyleet kernel: [  185.986920] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:45 tyleet kernel: [  185.986945] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:45 tyleet kernel: [  185.986956] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (348 0)
Jun  9 14:20:45 tyleet kernel: [  185.986969] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:45 tyleet kernel: [  185.986980] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:45 tyleet kernel: [  185.987003] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00000570 348 0 8192
Jun  9 14:20:45 tyleet kernel: [  185.994924] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:45 tyleet kernel: [  185.994947] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:45 tyleet kernel: [  185.994958] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (339 0)
Jun  9 14:20:45 tyleet kernel: [  185.994970] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:45 tyleet kernel: [  185.994980] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:45 tyleet kernel: [  185.995002] 
[drm:i9xx_update_primary_plane] Writing base 02000000 0000054C 339 0 8192
Jun  9 14:20:45 tyleet kernel: [  186.106853] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:45 tyleet kernel: [  186.106879] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:45 tyleet kernel: [  186.106889] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (334 0)
Jun  9 14:20:45 tyleet kernel: [  186.106902] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:45 tyleet kernel: [  186.106912] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:45 tyleet kernel: [  186.106932] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00000538 334 0 8192
Jun  9 14:20:45 tyleet kernel: [  186.114852] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:45 tyleet kernel: [  186.114875] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:45 tyleet kernel: [  186.114886] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (303 0)
Jun  9 14:20:45 tyleet kernel: [  186.114899] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:45 tyleet kernel: [  186.114909] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:45 tyleet kernel: [  186.114932] 
[drm:i9xx_update_primary_plane] Writing base 02000000 000004BC 303 0 8192
Jun  9 14:20:45 tyleet kernel: [  186.122899] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:45 tyleet kernel: [  186.122923] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:45 tyleet kernel: [  186.122934] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (270 0)
Jun  9 14:20:45 tyleet kernel: [  186.122947] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:45 tyleet kernel: [  186.122957] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:45 tyleet kernel: [  186.122979] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00000438 270 0 8192
Jun  9 14:20:45 tyleet kernel: [  186.130860] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:45 tyleet kernel: [  186.130880] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:45 tyleet kernel: [  186.130890] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (237 0)
Jun  9 14:20:45 tyleet kernel: [  186.130902] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:45 tyleet kernel: [  186.130912] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:45 tyleet kernel: [  186.130932] 
[drm:i9xx_update_primary_plane] Writing base 02000000 000003B4 237 0 8192
Jun  9 14:20:45 tyleet kernel: [  186.138892] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:45 tyleet kernel: [  186.140134] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:45 tyleet kernel: [  186.140148] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (204 0)
Jun  9 14:20:45 tyleet kernel: [  186.140161] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:45 tyleet kernel: [  186.140171] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:45 tyleet kernel: [  186.140195] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00000330 204 0 8192
Jun  9 14:20:45 tyleet kernel: [  186.146884] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:45 tyleet kernel: [  186.146907] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:45 tyleet kernel: [  186.146918] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (173 0)
Jun  9 14:20:45 tyleet kernel: [  186.146931] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:45 tyleet kernel: [  186.146941] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:45 tyleet kernel: [  186.146962] 
[drm:i9xx_update_primary_plane] Writing base 02000000 000002B4 173 0 8192
Jun  9 14:20:45 tyleet kernel: [  186.154951] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:45 tyleet kernel: [  186.154977] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:45 tyleet kernel: [  186.154989] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (142 0)
Jun  9 14:20:45 tyleet kernel: [  186.155001] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:45 tyleet kernel: [  186.155011] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:45 tyleet kernel: [  186.155037] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00000238 142 0 8192
Jun  9 14:20:45 tyleet kernel: [  186.162881] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:45 tyleet kernel: [  186.162903] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:45 tyleet kernel: [  186.162914] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (109 0)
Jun  9 14:20:45 tyleet kernel: [  186.162927] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:45 tyleet kernel: [  186.162936] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:45 tyleet kernel: [  186.162959] 
[drm:i9xx_update_primary_plane] Writing base 02000000 000001B4 109 0 8192
Jun  9 14:20:45 tyleet kernel: [  186.170909] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:45 tyleet kernel: [  186.170934] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:45 tyleet kernel: [  186.170945] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (76 0)
Jun  9 14:20:45 tyleet kernel: [  186.170957] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:45 tyleet kernel: [  186.170967] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:45 tyleet kernel: [  186.170990] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00000130 76 0 8192
Jun  9 14:20:45 tyleet kernel: [  186.178898] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:45 tyleet kernel: [  186.178921] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:45 tyleet kernel: [  186.178932] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (41 0)
Jun  9 14:20:45 tyleet kernel: [  186.178944] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:45 tyleet kernel: [  186.178954] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:45 tyleet kernel: [  186.178978] 
[drm:i9xx_update_primary_plane] Writing base 02000000 000000A4 41 0 8192
Jun  9 14:20:45 tyleet kernel: [  186.186913] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:45 tyleet kernel: [  186.186937] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:45 tyleet kernel: [  186.186948] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (6 0)
Jun  9 14:20:45 tyleet kernel: [  186.186960] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:45 tyleet kernel: [  186.186970] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:45 tyleet kernel: [  186.186991] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00000018 6 0 8192
Jun  9 14:20:45 tyleet kernel: [  186.195587] [drm:drm_mode_setcrtc] 
[CRTC:5]
Jun  9 14:20:45 tyleet kernel: [  186.195616] [drm:drm_mode_setcrtc] 
[CONNECTOR:11:DVI-I-1]
Jun  9 14:20:45 tyleet kernel: [  186.195627] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:18] #connectors=1 (x y) (0 0)
Jun  9 14:20:45 tyleet kernel: [  186.195640] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=1
Jun  9 14:20:45 tyleet kernel: [  186.195650] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:20:45 tyleet kernel: [  186.195671] 
[drm:i9xx_update_primary_plane] Writing base 02000000 00000000 0 0 8192
Jun  9 14:20:52 tyleet kernel: [  193.664064] [drm:intel_crt_detect] 
[CONNECTOR:8:VGA-1] force=0
Jun  9 14:20:52 tyleet kernel: [  193.664359] 
[drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 
gmbus vga
Jun  9 14:20:52 tyleet kernel: [  193.664367] [drm:intel_crt_detect_ddc] 
CRT not detected via DDC:0x50 [no valid EDID found]
Jun  9 14:21:02 tyleet kernel: [  203.680065] [drm:intel_crt_detect] 
[CONNECTOR:8:VGA-1] force=0
Jun  9 14:21:02 tyleet kernel: [  203.680358] 
[drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 
gmbus vga
Jun  9 14:21:02 tyleet kernel: [  203.680367] [drm:intel_crt_detect_ddc] 
CRT not detected via DDC:0x50 [no valid EDID found]
Jun  9 14:21:05 tyleet kernel: [  206.163158] 
[drm:intel_crtc_cursor_set] cursor off
Jun  9 14:21:05 tyleet kernel: [  206.197059] 
[drm:intel_crtc_set_config] [CRTC:5] [NOFB]
Jun  9 14:21:05 tyleet kernel: [  206.197086] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=1, fb_changed=0
Jun  9 14:21:05 tyleet kernel: [  206.197097] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [NOCRTC]
Jun  9 14:21:05 tyleet kernel: [  206.197103] 
[drm:intel_modeset_stage_output_state] encoder changed, full mode switch
Jun  9 14:21:05 tyleet kernel: [  206.197110] 
[drm:intel_modeset_stage_output_state] crtc changed, full mode switch
Jun  9 14:21:05 tyleet kernel: [  206.197118] 
[drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
Jun  9 14:21:05 tyleet kernel: [  206.197129] 
[drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, 
prepare: 0, disable: 1
Jun  9 14:21:05 tyleet kernel: [  206.238824] [drm:ns2501_dpms] Trying 
set the dpms of the DVO to 0
Jun  9 14:21:05 tyleet kernel: [  206.468055] [drm:i830_get_fifo_size] 
FIFO size - (0x00017e5f) A: 47
Jun  9 14:21:05 tyleet kernel: [  206.468067] [drm:i830_get_fifo_size] 
FIFO size - (0x00017e5f) B: 48
Jun  9 14:21:05 tyleet kernel: [  206.468075] [drm:i9xx_update_wm] FIFO 
watermarks - A: 45, B: 31
Jun  9 14:21:05 tyleet kernel: [  206.468083] [drm:i9xx_update_wm] 
Setting FIFO watermarks - A: 45, B: 31, C: 2, SR 1
Jun  9 14:21:05 tyleet kernel: [  206.468107] [drm:check_encoder_state] 
[ENCODER:9:DAC-9]
Jun  9 14:21:05 tyleet kernel: [  206.468114] [drm:check_encoder_state] 
[ENCODER:10:None-10]
Jun  9 14:21:05 tyleet kernel: [  206.468122] [drm:check_crtc_state] 
[CRTC:5]
Jun  9 14:21:05 tyleet kernel: [  206.468138] [drm:check_crtc_state] 
[CRTC:7]
Jun  9 14:21:05 tyleet kernel: [  206.475097] 
[drm:intel_crtc_cursor_set] cursor off
Jun  9 14:21:05 tyleet kernel: [  206.475112] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:15] #connectors=1 (x y) (0 0)
Jun  9 14:21:05 tyleet kernel: [  206.475122] 
[drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
Jun  9 14:21:05 tyleet kernel: [  206.475129] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=1, fb_changed=0
Jun  9 14:21:05 tyleet kernel: [  206.475133] 
[drm:intel_modeset_stage_output_state] encoder changed, full mode switch
Jun  9 14:21:05 tyleet kernel: [  206.475138] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:21:05 tyleet kernel: [  206.475141] 
[drm:intel_modeset_stage_output_state] crtc changed, full mode switch
Jun  9 14:21:05 tyleet kernel: [  206.475144] 
[drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
Jun  9 14:21:05 tyleet kernel: [  206.475152] 
[drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, 
prepare: 1, disable: 0
Jun  9 14:21:05 tyleet kernel: [  206.475161] 
[drm:connected_sink_compute_bpp] [CONNECTOR:11:DVI-I-1] checking for 
sink bpp constrains
Jun  9 14:21:05 tyleet kernel: [  206.475171] 
[drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
Jun  9 14:21:05 tyleet kernel: [  206.475176] 
[drm:intel_dump_pipe_config] [CRTC:5][modeset] config for pipe A
Jun  9 14:21:05 tyleet kernel: [  206.475179] 
[drm:intel_dump_pipe_config] cpu_transcoder: A
Jun  9 14:21:05 tyleet kernel: [  206.475182] 
[drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
Jun  9 14:21:05 tyleet kernel: [  206.475187] 
[drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, 
link_m: 0, link_n: 0, tu: 0
Jun  9 14:21:05 tyleet kernel: [  206.475192] 
[drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, 
link_n: 0, tu: 0
Jun  9 14:21:05 tyleet kernel: [  206.475194] 
[drm:intel_dump_pipe_config] requested mode:
Jun  9 14:21:05 tyleet kernel: [  206.475204] 
[drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 
1048 1184 1344 768 771 777 806 0x40 0xa
Jun  9 14:21:05 tyleet kernel: [  206.475207] 
[drm:intel_dump_pipe_config] adjusted mode:
Jun  9 14:21:05 tyleet kernel: [  206.475215] 
[drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 
1048 1184 1344 768 771 777 806 0x40 0xa
Jun  9 14:21:05 tyleet kernel: [  206.475222] 
[drm:intel_dump_crtc_timings] crtc timings: 65000 1024 1048 1184 1344 
768 771 777 806, type: 0x40 flags: 0xa
Jun  9 14:21:05 tyleet kernel: [  206.475225] 
[drm:intel_dump_pipe_config] port clock: 65000
Jun  9 14:21:05 tyleet kernel: [  206.475228] 
[drm:intel_dump_pipe_config] pipe src size: 1024x768
Jun  9 14:21:05 tyleet kernel: [  206.475233] 
[drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 
0x00000000, lvds border: 0x00000000
Jun  9 14:21:05 tyleet kernel: [  206.475237] 
[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 
0x00000000, disabled
Jun  9 14:21:05 tyleet kernel: [  206.475240] 
[drm:intel_dump_pipe_config] ips: 0
Jun  9 14:21:05 tyleet kernel: [  206.475242] 
[drm:intel_dump_pipe_config] double wide: 0
Jun  9 14:21:05 tyleet kernel: [  206.484537] [drm:i830_get_fifo_size] 
FIFO size - (0x00017e5f) A: 47
Jun  9 14:21:05 tyleet kernel: [  206.484542] [drm:intel_calculate_wm] 
FIFO entries required for mode: 41
Jun  9 14:21:05 tyleet kernel: [  206.484544] [drm:intel_calculate_wm] 
FIFO watermark level: 4
Jun  9 14:21:05 tyleet kernel: [  206.484549] [drm:i830_get_fifo_size] 
FIFO size - (0x00017e5f) B: 48
Jun  9 14:21:05 tyleet kernel: [  206.484553] [drm:i9xx_update_wm] FIFO 
watermarks - A: 9, B: 31
Jun  9 14:21:05 tyleet kernel: [  206.484557] [drm:i9xx_update_wm] 
Setting FIFO watermarks - A: 9, B: 31, C: 2, SR 1
Jun  9 14:21:05 tyleet kernel: [  206.484569] [drm:ns2501_mode_set] set 
mode (hdisplay=1024,htotal=1344,vdisplay=768,vtotal=806).
Jun  9 14:21:05 tyleet kernel: [  206.540432] [drm:ns2501_dpms] Trying 
set the dpms of the DVO to 1
Jun  9 14:21:05 tyleet kernel: [  206.765381] 
[drm:i9xx_update_primary_plane] Writing base 00060000 00000000 0 0 4096
Jun  9 14:21:05 tyleet kernel: [  206.766293] 
[drm:intel_connector_check_state] [CONNECTOR:11:DVI-I-1]
Jun  9 14:21:05 tyleet kernel: [  206.766297] [drm:check_encoder_state] 
[ENCODER:9:DAC-9]
Jun  9 14:21:05 tyleet kernel: [  206.766302] [drm:check_encoder_state] 
[ENCODER:10:None-10]
Jun  9 14:21:05 tyleet kernel: [  206.766306] [drm:check_crtc_state] 
[CRTC:5]
Jun  9 14:21:05 tyleet kernel: [  206.766324] [drm:check_crtc_state] 
[CRTC:7]
Jun  9 14:21:05 tyleet kernel: [  206.766336] 
[drm:intel_crtc_cursor_set] cursor off
Jun  9 14:21:05 tyleet kernel: [  206.766340] 
[drm:intel_crtc_set_config] [CRTC:7] [NOFB]
Jun  9 14:21:05 tyleet kernel: [  206.766347] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:7], mode_changed=0, fb_changed=0
Jun  9 14:21:05 tyleet kernel: [  206.766353] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:21:05 tyleet kernel: [  206.766367] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:15] #connectors=1 (x y) (0 0)
Jun  9 14:21:05 tyleet kernel: [  206.766374] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=0
Jun  9 14:21:05 tyleet kernel: [  206.766378] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:21:05 tyleet kernel: [  206.766424] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:15] #connectors=1 (x y) (0 0)
Jun  9 14:21:05 tyleet kernel: [  206.766430] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=0
Jun  9 14:21:05 tyleet kernel: [  206.766435] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:21:05 tyleet kernel: [  206.778556] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:15] #connectors=1 (x y) (0 0)
Jun  9 14:21:05 tyleet kernel: [  206.778563] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=0
Jun  9 14:21:05 tyleet kernel: [  206.778567] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:21:05 tyleet kernel: [  206.877563] 
[drm:intel_crtc_cursor_set] cursor off
Jun  9 14:21:05 tyleet kernel: [  206.877587] 
[drm:intel_crtc_set_config] [CRTC:5] [FB:15] #connectors=1 (x y) (0 0)
Jun  9 14:21:05 tyleet kernel: [  206.877601] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:5], mode_changed=0, fb_changed=0
Jun  9 14:21:05 tyleet kernel: [  206.877611] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:21:05 tyleet kernel: [  206.877619] 
[drm:intel_crtc_cursor_set] cursor off
Jun  9 14:21:05 tyleet kernel: [  206.877626] 
[drm:intel_crtc_set_config] [CRTC:7] [NOFB]
Jun  9 14:21:05 tyleet kernel: [  206.877635] 
[drm:intel_set_config_compute_mode_changes] computed changes for 
[CRTC:7], mode_changed=0, fb_changed=0
Jun  9 14:21:05 tyleet kernel: [  206.877643] 
[drm:intel_modeset_stage_output_state] [CONNECTOR:11:DVI-I-1] to [CRTC:5]
Jun  9 14:21:06 tyleet kernel: [  207.204617] fuse exit
Jun  9 14:21:06 tyleet kernel: [  207.536214] ipw2100: exit - failed to 
send CARD_DISABLE command

Re: Partial success - Fixing resume from s2ram on S6010

[Thomas Richter]

Am 09.06.2014 13:31, schrieb Ville Syrjälä:

>
> So now you're using acpi_sleep=s3_bios, or nothing?

Ok, tried now with acpi_sleep=s3. Unfortunately, this hangs the machine 
completely during resume, I cannot even ping it.

Then, I tried the same trick again, namely unloading the i915 module 
before the resume, reloading it after the resume. This worked 
flawlessly, display came back without requiring any quirks, even with 
the state the bios left the hardware in.

Note again that this is different for the resume from acpi_sleep=s3 or 
'nothing', where I can restore the display (though the result is a hick-up).

If there is another deadlock in i915 (not unlikely) I cannot debug it 
this way, unfortunately.

Unfortunately, the S6010 does not have a serial port to redirect the 
console to. I can only use the netconsole, though this reveals nothing. 
Probably the deadlock happens before the is enabled.

Greetings,
	Thomas

Re: Partial success - Fixing resume from s2ram on S6010

[Thomas Richter]

Hi Ville, dear Intel experts,

more on the partial resume from suspend for the S6010. It seems that the 
culprit is really the lack of a proper
initialization of the DVO. The minimum sequence to restore the display 
does not require to modify the 830 registers
directly, but rather needs to setup the DVO.

xrandr --output DVI1 --mode 640x480
# without this, access to the DVO is blocked, thus
# all the following fails. The above initializes the
# PLLs such that the DVO can be accessed.

modprobe i2c-hid
modprobe i2c-algo-bit
modprobe i2c-dev
modprobe i2c-scmi
modprobe i2c-i801
modprobe i2c-ismt
modprobe i2c-gpio
modprobe i2c-piix4
modprobe i2c-isch
modprobe i2c-mux
modprobe i2c-core

#
# Only the following two are required.
i2cset -y 5 0x38 0x34 0x02
i2cset -y 5 0x38 0x35 0x7f

# This restores the old resolution.
xrandr --output DVI1 --mode 1024x768

Thus, it really seems that the culprit is here that the resume operation 
does
not provide access to the DVO correctly.

Greetings,
     Thomas

[PATCH] drm/i915: Init important ns2501 registers

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

In my earlier rewrite I missed a few important registers. Thomas Richter
noticed that they're needed to make his machine resume correctly.

Looks like IEGD does a one time init of these three registers. We don't
have a good one time init place in the ns2501 driver, so let's just
stick them into the .mode_set() hook and see if that helps things along.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/dvo_ns2501.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/dvo_ns2501.c b/drivers/gpu/drm/i915/dvo_ns2501.c
index 64103cb..4416304 100644
--- a/drivers/gpu/drm/i915/dvo_ns2501.c
+++ b/drivers/gpu/drm/i915/dvo_ns2501.c
@@ -342,6 +342,12 @@ static const struct ns2501_reg regs_1024x768[][86] = {
 	},
 };
 
+static const struct ns2501_reg regs_init[] = {
+	[0] = { .offset = 0x35, .value = 0xff, },
+	[1] = { .offset = 0x34, .value = 0x00, },
+	[2] = { .offset = 0x08, .value = 0x30, },
+};
+
 struct ns2501_priv {
 	bool quiet;
 	const struct ns2501_reg *regs;
@@ -544,6 +550,10 @@ static void ns2501_mode_set(struct intel_dvo_device *dvo,
 	else
 		return;
 
+	/* Hopefully doing it every time won't hurt... */
+	for (i = 0; i < ARRAY_SIZE(regs_init); i++)
+		ns2501_writeb(dvo, regs_init[i].offset, regs_init[i].value);
+
 	ns->regs = regs_1024x768[mode_idx];
 
 	for (i = 0; i < 84; i++)
-- 
1.8.5.5

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Re: [PATCH] drm/i915: Init important ns2501 registers

[Thomas Richter]

Am 09.06.2014 21:46, schrieb ville.syrjala@linux.intel.com:
> From: Ville Syrjälä<ville.syrjala@linux.intel.com>
>
> In my earlier rewrite I missed a few important registers. Thomas Richter
> noticed that they're needed to make his machine resume correctly.
Thanks, this *almost* works, much better than before. Now I only need to 
switch the console
forth and back to get a display. However, I get a pretty unstable 
display on the console, and
a *sometimes* unstable display on the X display. From the way it looks, 
I would guess that
the synchronization between the display and the PLL is not quite right. 
Which is stunning since
the 830M seems to be configured correctly.

Greetings,
     Thomas

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Re: [PATCH] drm/i915: Init important ns2501 registers

[Thomas Richter]

[-- Attachment #1: Type: text/plain, Size: 421 bytes --]

Hi Ville,

thanks for the latest patch. As said, the screen did not come back quite 
correctly. I checked the register values
again, and I am sorry to say that I was wrong - register values do 
differ. Apparently, the code configures now
the wrong pipe to generate output to the DVO and thus the DVO does not 
seem to synchronize correctly
anymore. Please find the two register dumps attached.

Greetings,
     Thomas




[-- Attachment #2: reg.org --]
[-- Type: application/octet-stream, Size: 10383 bytes --]

[-- Attachment #3: reg.resume --]
[-- Type: text/plain, Size: 10310 bytes --]

                 DCC: 0x00000000 (`7v·ô‚ƒ¿bFx·ä‚ƒ¿ô‡r·Ø‚ƒ¿dŠy·)
           CHDECMISC: 0x00000000 (none, ch2 enh disabled, ch1 enh disabled, ch0 enh disabled, flex disabled, ep not present)
              C0DRB0: 0x00000000 (0x0000)
              C0DRB1: 0x00000000 (0x0000)
              C0DRB2: 0x00000000 (0x0000)
              C0DRB3: 0x00000000 (0x0000)
              C1DRB0: 0x00000000 (0x0000)
              C1DRB1: 0x00000000 (0x0000)
              C1DRB2: 0x00000000 (0x0000)
              C1DRB3: 0x00000000 (0x0000)
             C0DRA01: 0x00000000 (0x0000)
             C0DRA23: 0x00000000 (0x0000)
             C1DRA01: 0x00000000 (0x0000)
             C1DRA23: 0x00000000 (0x0000)
          PGETBL_CTL: 0x3ff60001
   VCLK_DIVISOR_VGA0: 0x00021207 (n = 2, m1 = 18, m2 = 7)
   VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
       VCLK_POST_DIV: 0x0000888b (vga0 p1 = 13, p2 = 4, vga1 p1 = 10, p2 = 4)
           DPLL_TEST: 0x00000000 (, DPLLA input buffer disabled, DPLLB input buffer disabled)
        CACHE_MODE_0: 0x001f0000
             D_STATE: 0x00000000
       DSPCLK_GATE_D: 0x00000008 (clock gates disabled: OVRUNIT)
      RENCLK_GATE_D1: 0x00000000
      RENCLK_GATE_D2: 0x00000000
               SDVOB: 0x90004084 (enabled, pipe A, stall disabled, detected)
               SDVOC: 0x00000000 (disabled, pipe A, stall disabled, not detected)
             SDVOUDI: 0x00000000
              DSPARB: 0x00017e5f
              DSPFW1: 0x00000000
              DSPFW2: 0x00000000
              DSPFW3: 0x00000000
                ADPA: 0x00000c00 (disabled, pipe A, -hsync, -vsync)
                LVDS: 0x00000000 (disabled, pipe A, 18 bit, 1 channel)
                DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
                DVOB: 0x90004084 (enabled, pipe A, stall, -hsync, -vsync)
                DVOC: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
         DVOA_SRCDIM: 0x00000000
         DVOB_SRCDIM: 0x00000000
         DVOC_SRCDIM: 0x00000000
          PP_CONTROL: 0x00000000 (power target: off)
           PP_STATUS: 0x00000000 (off, not ready, sequencing idle)
        PP_ON_DELAYS: 0x00000000
       PP_OFF_DELAYS: 0x00000000
          PP_DIVISOR: 0x00000000
        PFIT_CONTROL: 0x00000000
     PFIT_PGM_RATIOS: 0x00000000
     PORT_HOTPLUG_EN: 0x00000000
   PORT_HOTPLUG_STAT: 0x00000000
            DSPACNTR: 0xd8000000 (enabled, pipe A)
          DSPASTRIDE: 0x00002000 (8192 bytes)
             DSPAPOS: 0x00000000 (0, 0)
            DSPASIZE: 0x02ff03ff (1024, 768)
            DSPABASE: 0x02000000
            DSPASURF: 0x00000000
         DSPATILEOFF: 0x00000000
           PIPEACONF: 0x80000000 (enabled, single-wide)
            PIPEASRC: 0x03ff02ff (1024, 768)
           PIPEASTAT: 0x10000207 (status: CRC_DONE_ENABLE VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS)
   PIPEA_GMCH_DATA_M: 0x00000000
   PIPEA_GMCH_DATA_N: 0x00000000
     PIPEA_DP_LINK_M: 0x00000000
     PIPEA_DP_LINK_N: 0x00000000
       CURSOR_A_BASE: 0x3524c000
    CURSOR_A_CONTROL: 0x04000027
   CURSOR_A_POSITION: 0x00d50133
                FPA0: 0x0004150d (n = 4, m1 = 21, m2 = 13)
                FPA1: 0x0004150d (n = 4, m1 = 21, m2 = 13)
              DPLL_A: 0xd0820000 (enabled, dvo, default clock, DAC/serial mode, p1 = 4, p2 = 4)
           DPLL_A_MD: 0x00000000
            HTOTAL_A: 0x053f03ff (1024 active, 1344 total)
            HBLANK_A: 0x053f03ff (1024 start, 1344 end)
             HSYNC_A: 0x049f0417 (1048 start, 1184 end)
            VTOTAL_A: 0x032502ff (768 active, 806 total)
            VBLANK_A: 0x032502ff (768 start, 806 end)
             VSYNC_A: 0x03080302 (771 start, 777 end)
           BCLRPAT_A: 0x00000000
        VSYNCSHIFT_A: 0x00000000
            DSPBCNTR: 0x00000000 (disabled, pipe A)
          DSPBSTRIDE: 0x00000000 (0 bytes)
             DSPBPOS: 0x00000000 (0, 0)
            DSPBSIZE: 0x00000000 (1, 1)
            DSPBBASE: 0x00000000
            DSPBSURF: 0x00000000
         DSPBTILEOFF: 0x00000000
           PIPEBCONF: 0x00000000 (disabled, single-wide)
            PIPEBSRC: 0x00000000 (1, 1)
           PIPEBSTAT: 0x10000004 (status: CRC_DONE_ENABLE SVBLANK_INT_STATUS)
   PIPEB_GMCH_DATA_M: 0x00000000
   PIPEB_GMCH_DATA_N: 0x00000000
     PIPEB_DP_LINK_M: 0x00000000
     PIPEB_DP_LINK_N: 0x00000000
       CURSOR_B_BASE: 0x00000000
    CURSOR_B_CONTROL: 0x00000000
   CURSOR_B_POSITION: 0x00000000
                FPB0: 0x00021207 (n = 2, m1 = 18, m2 = 7)
                FPB1: 0x00021207 (n = 2, m1 = 18, m2 = 7)
              DPLL_B: 0x408b0000 (disabled, dvo, VGA, default clock, DAC/serial mode, p1 = 13, p2 = 4)
           DPLL_B_MD: 0x00000000
            HTOTAL_B: 0x00000000 (1 active, 1 total)
            HBLANK_B: 0x00000000 (1 start, 1 end)
             HSYNC_B: 0x00000000 (1 start, 1 end)
            VTOTAL_B: 0x00000000 (1 active, 1 total)
            VBLANK_B: 0x00000000 (1 start, 1 end)
             VSYNC_B: 0x00000000 (1 start, 1 end)
           BCLRPAT_B: 0x00000000
        VSYNCSHIFT_B: 0x00000000
   VCLK_DIVISOR_VGA0: 0x00021207
   VCLK_DIVISOR_VGA1: 0x00031406
       VCLK_POST_DIV: 0x0000888b
            VGACNTRL: 0x8124008e (disabled)
              TV_CTL: 0x00000000
              TV_DAC: 0x00000000
            TV_CSC_Y: 0x00000000
           TV_CSC_Y2: 0x00000000
            TV_CSC_U: 0x00000000
           TV_CSC_U2: 0x00000000
            TV_CSC_V: 0x00000000
           TV_CSC_V2: 0x00000000
        TV_CLR_KNOBS: 0x00000000
        TV_CLR_LEVEL: 0x00000000
          TV_H_CTL_1: 0x00000000
          TV_H_CTL_2: 0x00000000
          TV_H_CTL_3: 0x00000000
          TV_V_CTL_1: 0x00000000
          TV_V_CTL_2: 0x00000000
          TV_V_CTL_3: 0x00000000
          TV_V_CTL_4: 0x00000000
          TV_V_CTL_5: 0x00000000
          TV_V_CTL_6: 0x00000000
          TV_V_CTL_7: 0x00000000
         TV_SC_CTL_1: 0x00000000
         TV_SC_CTL_2: 0x00000000
         TV_SC_CTL_3: 0x00000000
          TV_WIN_POS: 0x00000000
         TV_WIN_SIZE: 0x00000000
     TV_FILTER_CTL_1: 0x00000000
     TV_FILTER_CTL_2: 0x00000000
     TV_FILTER_CTL_3: 0x00000000
       TV_CC_CONTROL: 0x00000000
          TV_CC_DATA: 0x00000000
         TV_H_LUMA_0: 0x00000000
        TV_H_LUMA_59: 0x00000000
       TV_H_CHROMA_0: 0x00000000
      TV_H_CHROMA_59: 0x00000000
        FBC_CFB_BASE: 0x00000000
         FBC_LL_BASE: 0x00000000
         FBC_CONTROL: 0x00000000
         FBC_COMMAND: 0x00000000
          FBC_STATUS: 0x00000000
        FBC_CONTROL2: 0x00000000
       FBC_FENCE_OFF: 0x00000000
         FBC_MOD_NUM: 0x00000000
             MI_MODE: 0x00000000
        MI_ARB_STATE: 0x00000000
      MI_RDRET_STATE: 0x00000000
             ECOSKPD: 0x00000307
                DP_B: 0x00000000
      DPB_AUX_CH_CTL: 0x00000000
    DPB_AUX_CH_DATA1: 0x00000000
    DPB_AUX_CH_DATA2: 0x00000000
    DPB_AUX_CH_DATA3: 0x00000000
    DPB_AUX_CH_DATA4: 0x00000000
    DPB_AUX_CH_DATA5: 0x00000000
                DP_C: 0x00000000
      DPC_AUX_CH_CTL: 0x00000000
    DPC_AUX_CH_DATA1: 0x00000000
    DPC_AUX_CH_DATA2: 0x00000000
    DPC_AUX_CH_DATA3: 0x00000000
    DPC_AUX_CH_DATA4: 0x00000000
    DPC_AUX_CH_DATA5: 0x00000000
                DP_D: 0x00000000
      DPD_AUX_CH_CTL: 0x00000000
    DPD_AUX_CH_DATA1: 0x00000000
    DPD_AUX_CH_DATA2: 0x00000000
    DPD_AUX_CH_DATA3: 0x00000000
    DPD_AUX_CH_DATA4: 0x00000000
    DPD_AUX_CH_DATA5: 0x00000000
          AUD_CONFIG: 0x00000000
    AUD_HDMIW_STATUS: 0x00000000
      AUD_CONV_CHCNT: 0x00000000
       VIDEO_DIP_CTL: 0x00000000
       AUD_PINW_CNTR: 0x00000000
         AUD_CNTL_ST: 0x00000000
         AUD_PIN_CAP: 0x00000000
        AUD_PINW_CAP: 0x00000000
  AUD_PINW_UNSOLRESP: 0x00000000
    AUD_OUT_DIG_CNVT: 0x00000000
       AUD_OUT_CWCAP: 0x00000000
         AUD_GRP_CAP: 0x00000000
            FENCE  0: 0x05000561 (enabled, X tiled, 32768 pitch, 0x05000000 - 0x07000000 (32768kb))
            FENCE  1: 0x03800351 (enabled, X tiled, 16384 pitch, 0x03800000 - 0x04000000 (8192kb))
            FENCE  2: 0x06000351 (enabled, X tiled, 16384 pitch, 0x06000000 - 0x06800000 (8192kb))
            FENCE  3: 0x00000000 (disabled)
            FENCE  4: 0x02000561 (enabled, X tiled, 32768 pitch, 0x02000000 - 0x04000000 (32768kb))
            FENCE  5: 0x00000000 (disabled)
            FENCE  6: 0x00600251 (enabled, X tiled, 16384 pitch, 0x00600000 - 0x00a00000 (4096kb))
            FENCE  7: 0x00000000 (disabled)
            FENCE  8: 0x00000000 (disabled)
            FENCE  9: 0x00000000 (disabled)
           FENCE  10: 0x00000000 (disabled)
           FENCE  11: 0x00000000 (disabled)
           FENCE  12: 0x00000048 (disabled)
           FENCE  13: 0x00000002 (disabled)
           FENCE  14: 0x00000000 (disabled)
           FENCE  15: 0x00000000 (disabled)
       FENCE START 0: 0x00000000 (disabled)
         FENCE END 0: 0x00000000 (disabled)
       FENCE START 1: 0x00000000 (disabled)
         FENCE END 1: 0x00000000 (disabled)
       FENCE START 2: 0x00000048 (disabled)
         FENCE END 2: 0x00000002 (disabled)
       FENCE START 3: 0x00000000 (disabled)
         FENCE END 3: 0x00000000 (disabled)
       FENCE START 4: 0x00000000 (disabled)
         FENCE END 4: 0x00000000 (disabled)
       FENCE START 5: 0x00000000 (disabled)
         FENCE END 5: 0x00000000 (disabled)
       FENCE START 6: 0x00000000 (disabled)
         FENCE END 6: 0x00000000 (disabled)
       FENCE START 7: 0x00000000 (disabled)
         FENCE END 7: 0x00000000 (disabled)
       FENCE START 8: 0x00000000 (disabled)
         FENCE END 8: 0x00000000 (disabled)
       FENCE START 9: 0x00000000 (disabled)
         FENCE END 9: 0x00000000 (disabled)
      FENCE START 10: 0x00000000 (disabled)
        FENCE END 10: 0x00000000 (disabled)
      FENCE START 11: 0x00000000 (disabled)
        FENCE END 11: 0x00000000 (disabled)
      FENCE START 12: 0x00000000 (disabled)
        FENCE END 12: 0x00000000 (disabled)
      FENCE START 13: 0x00000000 (disabled)
        FENCE END 13: 0x00000000 (disabled)
      FENCE START 14: 0x00000000 (disabled)
        FENCE END 14: 0x00000000 (disabled)
      FENCE START 15: 0x00000000 (disabled)
        FENCE END 15: 0x00000000 (disabled)
             INST_PM: 0x00000000
pipe A dot 65000 n 4 m1 21 m2 13 p1 4 p2 4
pipe B dot 25153 n 2 m1 18 m2 7 p1 13 p2 4

[-- Attachment #4: Type: text/plain, Size: 159 bytes --]

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Re: [PATCH] drm/i915: Init important ns2501 registers

[Ville Syrjälä]

On Tue, Jun 10, 2014 at 12:29:20AM +0200, Thomas Richter wrote:
> Hi Ville,
> 
> thanks for the latest patch. As said, the screen did not come back quite 
> correctly. I checked the register values
> again, and I am sorry to say that I was wrong - register values do 
> differ. Apparently, the code configures now
> the wrong pipe to generate output to the DVO and thus the DVO does not 
> seem to synchronize correctly
> anymore. Please find the two register dumps attached.

Either pipe can drive DVO just fine. Looks like it's using pipe A in
your register dump, and all the registers look fine to me. Well, DPLL B
VCO enable is off since we don't currently have a mechanism to kick pipe
B into action during resume/load. In theory that would need to be enabled
as well.

Can you see if a simple 'intel_reg_write 0x6018 0xc08b0000' fixes the
problem?

And if not, I'd like to see a diff of register dumps between working and
non working setups.

-- 
Ville Syrjälä
Intel OTC

Re: [PATCH] drm/i915: Init important ns2501 registers

[Thomas Richter]

Hi Ville,

> Either pipe can drive DVO just fine. Looks like it's using pipe A in
> your register dump, and all the registers look fine to me. Well, DPLL B
> VCO enable is off since we don't currently have a mechanism to kick pipe
> B into action during resume/load. In theory that would need to be enabled
> as well.
>
> Can you see if a simple 'intel_reg_write 0x6018 0xc08b0000' fixes the
> problem?

Nope. I created a little script that wrote the previous data back into 
the chipset, but that did not cure the problem. The only register I 
could not write to was CACHEMODE (IIRC, this was the name intel_reg_dump 
gave). The plane pointers and cursor pointers were different, too, but 
that should not be critical.

> And if not, I'd like to see a diff of register dumps between working and
> non working setups.

I afraid the S6010 is out of reach for the next three weeks, but I 
should have a complete register dump attached to my previous mail from 
yesterday night (or this morning, to be precise).

I can now try on the R31, but I don't remember having seen anything like 
it there. It does *not* look like the flickering of the misaligned 
watermark registers - on the console it really looks like bad HSYNC on a 
TV (tearing across horizontal lines, and massive misalignments of the 
very first lines of the screen). Within X, it causes the screen to jump 
to the right by about 64(?)128(?) pixels. The problem does not disappear 
by using a different resolution or restarting X. It remains permanent 
until the next boot.

Greetings,
	Thomas

i830GM on IBM R31 works with alm_fixes5 repository

[Thomas Richter]

Hi Ville,

thanks again for your alm_fixes5 branch. Just installed it on the old 
R31 - this seems to work fine. The external monitor works
(unlike with intel_drm_nightly, which is broken), and watermarks are 
also setup correctly. Booting works correctly, boot console
is setup correctly.

Suspend to RAM does not work, but this does not seem to be the fault of 
the i915 and drm modules. Even with almost all modules
unloaded, the machine hangs when trying to resume. The suspend2ram tests 
all work fine (i.e. freezing tasks, devices...), but as
soon as I use a real suspend (no testing), the machine does not wake up. 
The s3_sleep kernel parameter is not able to work around
this, i.e. there is no combination which makes this working. The BIOS is 
the latest version I could find (ancient, still) but no avail.

Machine remains completely unresponsive, no network, no mouse, no 
keyboard, no video, no sound. The pm-suspend rtc debugging
tricks do not reveal in which kernel module the machine hangs, nothing 
seems to match the recorded hash. The problem must appear
pretty early in the call-chain.

Anyhow, this is not i915 related as it seems, so nothing to fix here. 
I'll try to find out a bit more on this if I can.

Greetings,
     Thomas

Re: [PATCH] drm/i915: Avoid double mutex lock applying pipe A quirk during sanitize_crtc()

[Daniel Vetter]

On Mon, Jun 09, 2014 at 11:30:26AM +0300, Ville Syrjälä wrote:
> On Mon, Jun 09, 2014 at 07:47:10AM +0100, Chris Wilson wrote:
> > Thomas found that his machine would deadlock reloading the i915.ko
> > module after resume. He identified that this was caused by the
> > reacquisition of the connection mutex inside intel_enable_pipe_a()
> > during the CRTC sanitization routine. This will only affect machines
> > that quirk PIPE A, i.e. the original 830m chipsets.
> > 
> > This patch move the locking into a wrapper function so that
> > intel_enable_pipe_a() can bypass the locking knowing that it already
> > holds the correct locks.
> 
> It can still try to grab crtc->mutex twice. Looks like Danial undid my
> fix to not take all the modeset locks around
> intel_modeset_setup_hw_state().

Hm, I didn't find anything in git logs and we've had places where we used
modeset_lock_all since a long time. And I don't see how Chris' patch
wouldn't address this here. Can you please explain?

Thanks, Daniel

> 
> > 
> > Reported-by: Thomas Richter <richter@rus.uni-stuttgart.de>
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Thomas Richter <richter@rus.uni-stuttgart.de>
> > Cc: Daniel Vetter <daniel@ffwll.ch>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_display.c |   54 ++++++++++++++++++++++------------
> >  1 file changed, 35 insertions(+), 19 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index c1f79a1..26d3424 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -8387,9 +8387,10 @@ mode_fits_in_fbdev(struct drm_device *dev,
> >  #endif
> >  }
> >  
> > -bool intel_get_load_detect_pipe(struct drm_connector *connector,
> > -				struct drm_display_mode *mode,
> > -				struct intel_load_detect_pipe *old)
> > +static bool
> > +__intel_get_load_detect_pipe(struct drm_connector *connector,
> > +			     struct drm_display_mode *mode,
> > +			     struct intel_load_detect_pipe *old)
> >  {
> >  	struct intel_crtc *intel_crtc;
> >  	struct intel_encoder *intel_encoder =
> > @@ -8405,7 +8406,7 @@ bool intel_get_load_detect_pipe(struct drm_connector *connector,
> >  		      connector->base.id, connector->name,
> >  		      encoder->base.id, encoder->name);
> >  
> > -	mutex_lock(&dev->mode_config.connection_mutex);
> > +	lockdep_assert_held(&dev->mode_config.connection_mutex);
> >  
> >  	/*
> >  	 * Algorithm gets a little messy:
> > @@ -8449,7 +8450,7 @@ bool intel_get_load_detect_pipe(struct drm_connector *connector,
> >  	 */
> >  	if (!crtc) {
> >  		DRM_DEBUG_KMS("no pipe available for load-detect\n");
> > -		goto fail_unlock_connector;
> > +		return false;
> >  	}
> >  
> >  	mutex_lock(&crtc->mutex);
> > @@ -8503,14 +8504,13 @@ bool intel_get_load_detect_pipe(struct drm_connector *connector,
> >  	else
> >  		intel_crtc->new_config = NULL;
> >  	mutex_unlock(&crtc->mutex);
> > -fail_unlock_connector:
> > -	mutex_unlock(&dev->mode_config.connection_mutex);
> >  
> >  	return false;
> >  }
> >  
> > -void intel_release_load_detect_pipe(struct drm_connector *connector,
> > -				    struct intel_load_detect_pipe *old)
> > +static void
> > +__intel_release_load_detect_pipe(struct drm_connector *connector,
> > +				 struct intel_load_detect_pipe *old)
> >  {
> >  	struct intel_encoder *intel_encoder =
> >  		intel_attached_encoder(connector);
> > @@ -8518,6 +8518,8 @@ void intel_release_load_detect_pipe(struct drm_connector *connector,
> >  	struct drm_crtc *crtc = encoder->crtc;
> >  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> >  
> > +	lockdep_assert_held(&connector->dev->mode_config.connection_mutex);
> > +
> >  	DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
> >  		      connector->base.id, connector->name,
> >  		      encoder->base.id, encoder->name);
> > @@ -8533,17 +8535,32 @@ void intel_release_load_detect_pipe(struct drm_connector *connector,
> >  			drm_framebuffer_unregister_private(old->release_fb);
> >  			drm_framebuffer_unreference(old->release_fb);
> >  		}
> > +	} else {
> > +		/* Switch crtc and encoder back off if necessary */
> > +		if (old->dpms_mode != DRM_MODE_DPMS_ON)
> > +			connector->funcs->dpms(connector, old->dpms_mode);
> > +	}
> > +	mutex_unlock(&crtc->mutex);
> > +}
> >  
> > -		mutex_unlock(&crtc->mutex);
> > +bool intel_get_load_detect_pipe(struct drm_connector *connector,
> > +				struct drm_display_mode *mode,
> > +				struct intel_load_detect_pipe *old)
> > +{
> > +	mutex_lock(&connector->dev->mode_config.connection_mutex);
> > +	if (!__intel_get_load_detect_pipe(connector, mode, old)) {
> >  		mutex_unlock(&connector->dev->mode_config.connection_mutex);
> > -		return;
> > +		return false;
> >  	}
> >  
> > -	/* Switch crtc and encoder back off if necessary */
> > -	if (old->dpms_mode != DRM_MODE_DPMS_ON)
> > -		connector->funcs->dpms(connector, old->dpms_mode);
> > +	/* lock will be released by intel_release_load_detect_pipe() */
> > +	return true;
> > +}
> >  
> > -	mutex_unlock(&crtc->mutex);
> > +void intel_release_load_detect_pipe(struct drm_connector *connector,
> > +				    struct intel_load_detect_pipe *old)
> > +{
> > +	__intel_release_load_detect_pipe(connector, old);
> >  	mutex_unlock(&connector->dev->mode_config.connection_mutex);
> >  }
> >  
> > @@ -12354,10 +12371,9 @@ static void intel_enable_pipe_a(struct drm_device *dev)
> >  	if (!crt)
> >  		return;
> >  
> > -	if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
> > -		intel_release_load_detect_pipe(crt, &load_detect_temp);
> > -
> > -
> > +	lockdep_assert_held(&dev->mode_config.connection_mutex);
> > +	if (__intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
> > +		__intel_release_load_detect_pipe(crt, &load_detect_temp);
> >  }
> >  
> >  static bool
> > -- 
> > 1.7.9.5
> 
> -- 
> Ville Syrjälä
> Intel OTC

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH] drm/i915: Avoid double mutex lock applying pipe A quirk during sanitize_crtc()

[Ville Syrjälä]

On Tue, Jun 10, 2014 at 09:02:07AM +0200, Daniel Vetter wrote:
> On Mon, Jun 09, 2014 at 11:30:26AM +0300, Ville Syrjälä wrote:
> > On Mon, Jun 09, 2014 at 07:47:10AM +0100, Chris Wilson wrote:
> > > Thomas found that his machine would deadlock reloading the i915.ko
> > > module after resume. He identified that this was caused by the
> > > reacquisition of the connection mutex inside intel_enable_pipe_a()
> > > during the CRTC sanitization routine. This will only affect machines
> > > that quirk PIPE A, i.e. the original 830m chipsets.
> > > 
> > > This patch move the locking into a wrapper function so that
> > > intel_enable_pipe_a() can bypass the locking knowing that it already
> > > holds the correct locks.
> > 
> > It can still try to grab crtc->mutex twice. Looks like Danial undid my
> > fix to not take all the modeset locks around
> > intel_modeset_setup_hw_state().
> 
> Hm, I didn't find anything in git logs and we've had places where we used
> modeset_lock_all since a long time. And I don't see how Chris' patch
> wouldn't address this here. Can you please explain?

I added the modeset_all locking here:
 commit 027476642811f8559cbe00ef6cc54db230e48a20
 Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
 Date:   Mon Dec 2 11:08:06 2013 +0200

    drm/i915: Take modeset locks around intel_modeset_setup_hw_state()

and then had to reduce it to just the mode_config.mutex precisely due to
the pipe A quirk here:
 commit 7ad228b11ec26a820291c9f5a1168d6176580dc1
 Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
 Date:   Tue Jan 7 16:15:36 2014 +0200

    drm/i915: Don't grab crtc mutexes in intel_modeset_gem_init()

-- 
Ville Syrjälä
Intel OTC

Re: [PATCH] drm/i915: Avoid double mutex lock applying pipe A quirk during sanitize_crtc()

[Daniel Vetter]

On Tue, Jun 10, 2014 at 11:53:51AM +0300, Ville Syrjälä wrote:
> On Tue, Jun 10, 2014 at 09:02:07AM +0200, Daniel Vetter wrote:
> > On Mon, Jun 09, 2014 at 11:30:26AM +0300, Ville Syrjälä wrote:
> > > On Mon, Jun 09, 2014 at 07:47:10AM +0100, Chris Wilson wrote:
> > > > Thomas found that his machine would deadlock reloading the i915.ko
> > > > module after resume. He identified that this was caused by the
> > > > reacquisition of the connection mutex inside intel_enable_pipe_a()
> > > > during the CRTC sanitization routine. This will only affect machines
> > > > that quirk PIPE A, i.e. the original 830m chipsets.
> > > > 
> > > > This patch move the locking into a wrapper function so that
> > > > intel_enable_pipe_a() can bypass the locking knowing that it already
> > > > holds the correct locks.
> > > 
> > > It can still try to grab crtc->mutex twice. Looks like Danial undid my
> > > fix to not take all the modeset locks around
> > > intel_modeset_setup_hw_state().
> > 
> > Hm, I didn't find anything in git logs and we've had places where we used
> > modeset_lock_all since a long time. And I don't see how Chris' patch
> > wouldn't address this here. Can you please explain?
> 
> I added the modeset_all locking here:
>  commit 027476642811f8559cbe00ef6cc54db230e48a20
>  Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
>  Date:   Mon Dec 2 11:08:06 2013 +0200
> 
>     drm/i915: Take modeset locks around intel_modeset_setup_hw_state()
> 
> and then had to reduce it to just the mode_config.mutex precisely due to
> the pipe A quirk here:
>  commit 7ad228b11ec26a820291c9f5a1168d6176580dc1
>  Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
>  Date:   Tue Jan 7 16:15:36 2014 +0200
> 
>     drm/i915: Don't grab crtc mutexes in intel_modeset_gem_init()

Hm, indeed missed this since we have a bunch of other places that still do
the full modeset_lock_all, but probably not possible to hit the pipe A
quirk there. The ww mutex code makes this a bit more annoying so I guess
Chris' patch with having a lock-less pipe A quirk is the way to go.

But that one needs to be updated for latest drm-next/-nightly.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH] drm/i915: Avoid double mutex lock applying pipe A quirk during sanitize_crtc()

[Daniel Vetter]

On Mon, Jun 09, 2014 at 07:47:10AM +0100, Chris Wilson wrote:
> Thomas found that his machine would deadlock reloading the i915.ko
> module after resume. He identified that this was caused by the
> reacquisition of the connection mutex inside intel_enable_pipe_a()
> during the CRTC sanitization routine. This will only affect machines
> that quirk PIPE A, i.e. the original 830m chipsets.
> 
> This patch move the locking into a wrapper function so that
> intel_enable_pipe_a() can bypass the locking knowing that it already
> holds the correct locks.
> 
> Reported-by: Thomas Richter <richter@rus.uni-stuttgart.de>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Thomas Richter <richter@rus.uni-stuttgart.de>
> Cc: Daniel Vetter <daniel@ffwll.ch>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c |   54 ++++++++++++++++++++++------------
>  1 file changed, 35 insertions(+), 19 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index c1f79a1..26d3424 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -8387,9 +8387,10 @@ mode_fits_in_fbdev(struct drm_device *dev,
>  #endif
>  }
>  
> -bool intel_get_load_detect_pipe(struct drm_connector *connector,
> -				struct drm_display_mode *mode,
> -				struct intel_load_detect_pipe *old)
> +static bool
> +__intel_get_load_detect_pipe(struct drm_connector *connector,
> +			     struct drm_display_mode *mode,
> +			     struct intel_load_detect_pipe *old)
>  {
>  	struct intel_crtc *intel_crtc;
>  	struct intel_encoder *intel_encoder =
> @@ -8405,7 +8406,7 @@ bool intel_get_load_detect_pipe(struct drm_connector *connector,
>  		      connector->base.id, connector->name,
>  		      encoder->base.id, encoder->name);
>  
> -	mutex_lock(&dev->mode_config.connection_mutex);
> +	lockdep_assert_held(&dev->mode_config.connection_mutex);
>  
>  	/*
>  	 * Algorithm gets a little messy:
> @@ -8449,7 +8450,7 @@ bool intel_get_load_detect_pipe(struct drm_connector *connector,
>  	 */
>  	if (!crtc) {
>  		DRM_DEBUG_KMS("no pipe available for load-detect\n");
> -		goto fail_unlock_connector;
> +		return false;
>  	}
>  
>  	mutex_lock(&crtc->mutex);
> @@ -8503,14 +8504,13 @@ bool intel_get_load_detect_pipe(struct drm_connector *connector,
>  	else
>  		intel_crtc->new_config = NULL;
>  	mutex_unlock(&crtc->mutex);
> -fail_unlock_connector:
> -	mutex_unlock(&dev->mode_config.connection_mutex);
>  
>  	return false;
>  }
>  
> -void intel_release_load_detect_pipe(struct drm_connector *connector,
> -				    struct intel_load_detect_pipe *old)
> +static void
> +__intel_release_load_detect_pipe(struct drm_connector *connector,
> +				 struct intel_load_detect_pipe *old)
>  {
>  	struct intel_encoder *intel_encoder =
>  		intel_attached_encoder(connector);
> @@ -8518,6 +8518,8 @@ void intel_release_load_detect_pipe(struct drm_connector *connector,
>  	struct drm_crtc *crtc = encoder->crtc;
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>  
> +	lockdep_assert_held(&connector->dev->mode_config.connection_mutex);
> +
>  	DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
>  		      connector->base.id, connector->name,
>  		      encoder->base.id, encoder->name);
> @@ -8533,17 +8535,32 @@ void intel_release_load_detect_pipe(struct drm_connector *connector,
>  			drm_framebuffer_unregister_private(old->release_fb);
>  			drm_framebuffer_unreference(old->release_fb);
>  		}
> +	} else {
> +		/* Switch crtc and encoder back off if necessary */
> +		if (old->dpms_mode != DRM_MODE_DPMS_ON)
> +			connector->funcs->dpms(connector, old->dpms_mode);
> +	}

This part looks like an unrelated change?
-Daniel

> +	mutex_unlock(&crtc->mutex);
> +}
>  
> -		mutex_unlock(&crtc->mutex);
> +bool intel_get_load_detect_pipe(struct drm_connector *connector,
> +				struct drm_display_mode *mode,
> +				struct intel_load_detect_pipe *old)
> +{
> +	mutex_lock(&connector->dev->mode_config.connection_mutex);
> +	if (!__intel_get_load_detect_pipe(connector, mode, old)) {
>  		mutex_unlock(&connector->dev->mode_config.connection_mutex);
> -		return;
> +		return false;
>  	}
>  
> -	/* Switch crtc and encoder back off if necessary */
> -	if (old->dpms_mode != DRM_MODE_DPMS_ON)
> -		connector->funcs->dpms(connector, old->dpms_mode);
> +	/* lock will be released by intel_release_load_detect_pipe() */
> +	return true;
> +}
>  
> -	mutex_unlock(&crtc->mutex);
> +void intel_release_load_detect_pipe(struct drm_connector *connector,
> +				    struct intel_load_detect_pipe *old)
> +{
> +	__intel_release_load_detect_pipe(connector, old);
>  	mutex_unlock(&connector->dev->mode_config.connection_mutex);
>  }
>  
> @@ -12354,10 +12371,9 @@ static void intel_enable_pipe_a(struct drm_device *dev)
>  	if (!crt)
>  		return;
>  
> -	if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
> -		intel_release_load_detect_pipe(crt, &load_detect_temp);
> -
> -
> +	lockdep_assert_held(&dev->mode_config.connection_mutex);
> +	if (__intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
> +		__intel_release_load_detect_pipe(crt, &load_detect_temp);
>  }
>  
>  static bool
> -- 
> 1.7.9.5
> 

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH] drm/i915: Avoid double mutex lock applying pipe A quirk during sanitize_crtc()

[Chris Wilson]

On Tue, Jun 10, 2014 at 08:59:42AM +0200, Daniel Vetter wrote:
> On Mon, Jun 09, 2014 at 07:47:10AM +0100, Chris Wilson wrote:
> > +	} else {
> > +		/* Switch crtc and encoder back off if necessary */
> > +		if (old->dpms_mode != DRM_MODE_DPMS_ON)
> > +			connector->funcs->dpms(connector, old->dpms_mode);
> > +	}
> 
> This part looks like an unrelated change?

It's just diff. The change was to rejig the braces to remove the
duplicated unlock + return.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

[PATCH 18/15] drm/i915: Preserve VGACNTR bits from the BIOS

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

My Fujistsu-Siemens Lifebook S6010 doesn't like to resume from
S3 unless VGACNTR has been restore to the original value. The BIOS
value in this case was 0x0124008E. Setting the "VGA disable" bit
doesn't interfere with the S3 resume fortunately.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h      | 2 ++
 drivers/gpu/drm/i915/intel_display.c | 8 +++++++-
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 10e9f68..c1862c8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1541,6 +1541,8 @@ struct drm_i915_private {
 	/* used to control DVO 2x clock enable on 830M */
 	uint8_t dvo_pipes;
 
+	uint32_t bios_vgacntr;
+
 	/* Old dri1 support infrastructure, beware the dragons ya fools entering
 	 * here! */
 	struct i915_dri1_state dri1;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 4004605..12f7e8c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11946,7 +11946,11 @@ static void i915_disable_vga(struct drm_device *dev)
 	vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
 	udelay(300);
 
-	I915_WRITE(vga_reg, VGA_DISP_DISABLE);
+	/*
+	 * Fujitsu-Siemens Lifebook S6010 (830) has problems resuming
+	 * from S3 without preserving (some of?) the other bits.
+	 */
+	I915_WRITE(vga_reg, dev_priv->bios_vgacntr | VGA_DISP_DISABLE);
 	POSTING_READ(vga_reg);
 }
 
@@ -12033,6 +12037,8 @@ void intel_modeset_init(struct drm_device *dev)
 	intel_cpu_pll_init(dev);
 	intel_shared_dpll_init(dev);
 
+	/* save the BIOS value before clobbering it */
+	dev_priv->bios_vgacntr = I915_READ(i915_vgacntrl_reg(dev));
 	/* Just disable it once at startup */
 	i915_disable_vga(dev);
 	intel_setup_outputs(dev);
-- 
1.8.5.5

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