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From: Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: Joseph Lo <josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>,
	Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>,
	Paul Walmsley <pwalmsley-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
	Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>,
	Ian Campbell
	<ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>,
	Marc Zyngier <marc.zyngier-5wv7dgnIgG8@public.gmane.org>,
	Dave Martin <Dave.Martin-5wv7dgnIgG8@public.gmane.org>,
	Olav Haugan <ohaugan-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
	"devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
	<devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
	Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>,
	Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>,
	Grant Grundler <grundler-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>,
	Allen Martin <AMartin-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
	Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
	"linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
	<linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
	Cho KyongHo <pullip.cho-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>,
	"linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org"
	<linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>,
	"linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
	<linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
	"iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org"
	<iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org>,
	Kumar Gala <galak-sgV2jX0FEOJiIJoWrK/4GQ@public.gmane.org>
Subject: Re: [RFC 04/10] memory: Add Tegra124 memory controller support
Date: Fri, 27 Jun 2014 10:17:00 +0200	[thread overview]
Message-ID: <20140627081659.GA10794@ulmo> (raw)
In-Reply-To: <53AD2020.1050802-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>


[-- Attachment #1.1: Type: text/plain, Size: 1851 bytes --]

On Fri, Jun 27, 2014 at 03:41:20PM +0800, Joseph Lo wrote:
> Hi Thierry,
> 
> On 06/27/2014 04:49 AM, Thierry Reding wrote:
> [snip]
> >+
> >+#define MC_INTSTATUS 0x000
> >+#define  MC_INT_DECERR_MTS (1 << 16)
> >+#define  MC_INT_SECERR_SEC (1 << 13)
> >+#define  MC_INT_DECERR_VPR (1 << 12)
> >+#define  MC_INT_INVALID_APB_ASID_UPDATE (1 << 11)
> >+#define  MC_INT_INVALID_SMMU_PAGE (1 << 10)
> >+#define  MC_INT_ARBITRATION_EMEM (1 << 9)
> >+#define  MC_INT_SECURITY_VIOLATION (1 << 8)
> >+#define  MC_INT_DECERR_EMEM (1 << 6)
> >+#define MC_INTMASK 0x004
> >+#define MC_ERR_STATUS 0x08
> >+#define MC_ERR_ADR 0x0c
> >+
> [snip]
> >+
> >+#define SMMU_PDE_ATTR          (SMMU_PDE_READABLE | SMMU_PDE_WRITABLE | \
> >+                                SMMU_PDE_NONSECURE)
> >+#define SMMU_PTE_ATTR          (SMMU_PTE_READABLE | SMMU_PTE_WRITABLE | \
> >+                                SMMU_PTE_NONSECURE)
> >+
> >+#define SMMU_PDE_VACANT(n)     (((n) << 10) | SMMU_PDE_ATTR)
> >+#define SMMU_PTE_VACANT(n)     (((n) << 12) | SMMU_PTE_ATTR)
> 
> There is an ISR to catch the invalid SMMU translation. Do you want to modify
> the identity mapping with read/write attribute of the unused SMMU pages?

I'm not sure I understand what you mean by "identity mapping". None of
the public documentation seems to describe the exact layout of PDEs or
PTEs, so it's somewhat hard to tell what to set them to when pages are
unmapped.

> This can make sure we capture the invalid SMMU translation. And helps for
> driver to capture issues when using SMMU.

That certainly sounds like a useful thing to have. Like I said this is
an RFC and I'm not even sure if it's acceptable in the current form, so
I wanted to get feedback early on to avoid wasting effort on something
that turn out to be a wild-goose chase.

Thierry

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WARNING: multiple messages have this Message-ID (diff)
From: Thierry Reding <thierry.reding@gmail.com>
To: Joseph Lo <josephl@nvidia.com>
Cc: Rob Herring <robh+dt@kernel.org>, Pawel Moll <pawel.moll@arm.com>,
	Mark Rutland <mark.rutland@arm.com>,
	Ian Campbell <ijc+devicetree@hellion.org.uk>,
	Kumar Gala <galak@codeaurora.org>,
	Stephen Warren <swarren@wwwdotorg.org>,
	Arnd Bergmann <arnd@arndb.de>, Will Deacon <will.deacon@arm.com>,
	Joerg Roedel <joro@8bytes.org>,
	Cho KyongHo <pullip.cho@samsung.com>,
	Grant Grundler <grundler@chromium.org>,
	Dave Martin <Dave.Martin@arm.com>,
	Marc Zyngier <marc.zyngier@arm.com>,
	Hiroshi Doyu <hdoyu@nvidia.com>,
	Olav Haugan <ohaugan@codeaurora.org>,
	Paul Walmsley <pwalmsley@nvidia.com>,
	Rhyland Klein <rklein@nvidia.com>,
	Allen Martin <AMartin@nvidia.com>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"iommu@lists.linux-foundation.org"
	<iommu@lists.linux-foundation.org>,
	"linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>,
	"linux-tegra@vger.kernel.org" <linux-tegra@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [RFC 04/10] memory: Add Tegra124 memory controller support
Date: Fri, 27 Jun 2014 10:17:00 +0200	[thread overview]
Message-ID: <20140627081659.GA10794@ulmo> (raw)
In-Reply-To: <53AD2020.1050802@nvidia.com>

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On Fri, Jun 27, 2014 at 03:41:20PM +0800, Joseph Lo wrote:
> Hi Thierry,
> 
> On 06/27/2014 04:49 AM, Thierry Reding wrote:
> [snip]
> >+
> >+#define MC_INTSTATUS 0x000
> >+#define  MC_INT_DECERR_MTS (1 << 16)
> >+#define  MC_INT_SECERR_SEC (1 << 13)
> >+#define  MC_INT_DECERR_VPR (1 << 12)
> >+#define  MC_INT_INVALID_APB_ASID_UPDATE (1 << 11)
> >+#define  MC_INT_INVALID_SMMU_PAGE (1 << 10)
> >+#define  MC_INT_ARBITRATION_EMEM (1 << 9)
> >+#define  MC_INT_SECURITY_VIOLATION (1 << 8)
> >+#define  MC_INT_DECERR_EMEM (1 << 6)
> >+#define MC_INTMASK 0x004
> >+#define MC_ERR_STATUS 0x08
> >+#define MC_ERR_ADR 0x0c
> >+
> [snip]
> >+
> >+#define SMMU_PDE_ATTR          (SMMU_PDE_READABLE | SMMU_PDE_WRITABLE | \
> >+                                SMMU_PDE_NONSECURE)
> >+#define SMMU_PTE_ATTR          (SMMU_PTE_READABLE | SMMU_PTE_WRITABLE | \
> >+                                SMMU_PTE_NONSECURE)
> >+
> >+#define SMMU_PDE_VACANT(n)     (((n) << 10) | SMMU_PDE_ATTR)
> >+#define SMMU_PTE_VACANT(n)     (((n) << 12) | SMMU_PTE_ATTR)
> 
> There is an ISR to catch the invalid SMMU translation. Do you want to modify
> the identity mapping with read/write attribute of the unused SMMU pages?

I'm not sure I understand what you mean by "identity mapping". None of
the public documentation seems to describe the exact layout of PDEs or
PTEs, so it's somewhat hard to tell what to set them to when pages are
unmapped.

> This can make sure we capture the invalid SMMU translation. And helps for
> driver to capture issues when using SMMU.

That certainly sounds like a useful thing to have. Like I said this is
an RFC and I'm not even sure if it's acceptable in the current form, so
I wanted to get feedback early on to avoid wasting effort on something
that turn out to be a wild-goose chase.

Thierry

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WARNING: multiple messages have this Message-ID (diff)
From: thierry.reding@gmail.com (Thierry Reding)
To: linux-arm-kernel@lists.infradead.org
Subject: [RFC 04/10] memory: Add Tegra124 memory controller support
Date: Fri, 27 Jun 2014 10:17:00 +0200	[thread overview]
Message-ID: <20140627081659.GA10794@ulmo> (raw)
In-Reply-To: <53AD2020.1050802@nvidia.com>

On Fri, Jun 27, 2014 at 03:41:20PM +0800, Joseph Lo wrote:
> Hi Thierry,
> 
> On 06/27/2014 04:49 AM, Thierry Reding wrote:
> [snip]
> >+
> >+#define MC_INTSTATUS 0x000
> >+#define  MC_INT_DECERR_MTS (1 << 16)
> >+#define  MC_INT_SECERR_SEC (1 << 13)
> >+#define  MC_INT_DECERR_VPR (1 << 12)
> >+#define  MC_INT_INVALID_APB_ASID_UPDATE (1 << 11)
> >+#define  MC_INT_INVALID_SMMU_PAGE (1 << 10)
> >+#define  MC_INT_ARBITRATION_EMEM (1 << 9)
> >+#define  MC_INT_SECURITY_VIOLATION (1 << 8)
> >+#define  MC_INT_DECERR_EMEM (1 << 6)
> >+#define MC_INTMASK 0x004
> >+#define MC_ERR_STATUS 0x08
> >+#define MC_ERR_ADR 0x0c
> >+
> [snip]
> >+
> >+#define SMMU_PDE_ATTR          (SMMU_PDE_READABLE | SMMU_PDE_WRITABLE | \
> >+                                SMMU_PDE_NONSECURE)
> >+#define SMMU_PTE_ATTR          (SMMU_PTE_READABLE | SMMU_PTE_WRITABLE | \
> >+                                SMMU_PTE_NONSECURE)
> >+
> >+#define SMMU_PDE_VACANT(n)     (((n) << 10) | SMMU_PDE_ATTR)
> >+#define SMMU_PTE_VACANT(n)     (((n) << 12) | SMMU_PTE_ATTR)
> 
> There is an ISR to catch the invalid SMMU translation. Do you want to modify
> the identity mapping with read/write attribute of the unused SMMU pages?

I'm not sure I understand what you mean by "identity mapping". None of
the public documentation seems to describe the exact layout of PDEs or
PTEs, so it's somewhat hard to tell what to set them to when pages are
unmapped.

> This can make sure we capture the invalid SMMU translation. And helps for
> driver to capture issues when using SMMU.

That certainly sounds like a useful thing to have. Like I said this is
an RFC and I'm not even sure if it's acceptable in the current form, so
I wanted to get feedback early on to avoid wasting effort on something
that turn out to be a wild-goose chase.

Thierry
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  parent reply	other threads:[~2014-06-27  8:17 UTC|newest]

Thread overview: 133+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-06-26 20:49 [RFC 00/10] Add NVIDIA Tegra124 IOMMU support Thierry Reding
2014-06-26 20:49 ` Thierry Reding
2014-06-26 20:49 ` Thierry Reding
     [not found] ` <1403815790-8548-1-git-send-email-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2014-06-26 20:49   ` [RFC 01/10] iommu: Add IOMMU device registry Thierry Reding
2014-06-26 20:49     ` Thierry Reding
2014-06-26 20:49     ` Thierry Reding
     [not found]     ` <1403815790-8548-2-git-send-email-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2014-06-27  6:58       ` Thierry Reding
2014-06-27  6:58         ` Thierry Reding
2014-06-27  6:58         ` Thierry Reding
2014-07-03 10:37         ` Varun Sethi
2014-07-03 10:37           ` Varun Sethi
2014-07-03 10:37           ` Varun Sethi
2014-07-04 11:05       ` Joerg Roedel
2014-07-04 11:05         ` Joerg Roedel
2014-07-04 11:05         ` Joerg Roedel
     [not found]         ` <20140704110529.GF13434-zLv9SwRftAIdnm+yROfE0A@public.gmane.org>
2014-07-04 13:47           ` Thierry Reding
2014-07-04 13:47             ` Thierry Reding
2014-07-04 13:47             ` Thierry Reding
2014-07-04 13:49             ` Will Deacon
2014-07-04 13:49               ` Will Deacon
2014-07-04 13:49               ` Will Deacon
     [not found]               ` <20140704134928.GA25714-5wv7dgnIgG8@public.gmane.org>
2014-07-06 18:17                 ` Arnd Bergmann
2014-07-06 18:17                   ` Arnd Bergmann
2014-07-06 18:17                   ` Arnd Bergmann
     [not found]                   ` <201407062017.23049.arnd-r2nGTMty4D4@public.gmane.org>
2014-07-07 11:42                     ` Thierry Reding
2014-07-07 11:42                       ` Thierry Reding
2014-07-07 11:42                       ` Thierry Reding
2014-06-26 20:49   ` [PATCH v3 02/10] devicetree: Add generic IOMMU device tree bindings Thierry Reding
2014-06-26 20:49     ` Thierry Reding
2014-06-26 20:49     ` Thierry Reding
     [not found]     ` <1403815790-8548-3-git-send-email-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2014-06-27 13:55       ` Will Deacon
2014-06-27 13:55         ` Will Deacon
2014-06-27 13:55         ` Will Deacon
2014-06-30 22:24       ` Stephen Warren
2014-06-30 22:24         ` Stephen Warren
2014-06-30 22:24         ` Stephen Warren
2014-07-04  6:42       ` Varun Sethi
2014-07-04  6:42         ` Varun Sethi
2014-07-04  6:42         ` Varun Sethi
     [not found]         ` <9ffe3c3871ef4b60a955259bfa0bed6c-AZ66ij2kwaacCcN9WK45f+O6mTEJWrR4XA4E9RH9d+qIuWR1G4zioA@public.gmane.org>
2014-07-04  9:05           ` Arnd Bergmann
2014-07-04  9:05             ` Arnd Bergmann
2014-07-04  9:05             ` Arnd Bergmann
2014-06-26 20:49   ` [RFC 03/10] of: Add NVIDIA Tegra124 memory controller binding Thierry Reding
2014-06-26 20:49     ` Thierry Reding
2014-06-26 20:49     ` Thierry Reding
2014-06-26 20:49   ` [RFC 04/10] memory: Add Tegra124 memory controller support Thierry Reding
2014-06-26 20:49     ` Thierry Reding
2014-06-26 20:49     ` Thierry Reding
     [not found]     ` <1403815790-8548-5-git-send-email-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2014-06-27  7:41       ` Joseph Lo
2014-06-27  7:41         ` Joseph Lo
2014-06-27  7:41         ` Joseph Lo
     [not found]         ` <53AD2020.1050802-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2014-06-27  8:17           ` Thierry Reding [this message]
2014-06-27  8:17             ` Thierry Reding
2014-06-27  8:17             ` Thierry Reding
2014-06-27  8:24             ` Hiroshi Doyu
2014-06-27  8:24               ` Hiroshi Doyu
2014-06-27  9:46       ` Hiroshi DOyu
2014-06-27  9:46         ` Hiroshi DOyu
2014-06-27  9:46         ` Hiroshi DOyu
     [not found]         ` <20140627124638.7ec150cca163c89727b8953f-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2014-06-27 11:08           ` Thierry Reding
2014-06-27 11:08             ` Thierry Reding
2014-06-27 11:08             ` Thierry Reding
2014-06-27 21:33             ` Stephen Warren
2014-06-27 21:33               ` Stephen Warren
2014-06-27 21:33               ` Stephen Warren
2014-06-27 11:07       ` Arnd Bergmann
2014-06-27 11:07         ` Arnd Bergmann
2014-06-27 11:07         ` Arnd Bergmann
2014-06-27 11:15         ` Thierry Reding
2014-06-27 11:15           ` Thierry Reding
2014-06-27 11:15           ` Thierry Reding
2014-06-27 21:37           ` Stephen Warren
2014-06-27 21:37             ` Stephen Warren
2014-06-27 21:37             ` Stephen Warren
2014-06-30 22:43       ` Stephen Warren
2014-06-30 22:43         ` Stephen Warren
2014-06-30 22:43         ` Stephen Warren
2014-07-01 12:14       ` Hiroshi Doyu
2014-07-01 12:14         ` Hiroshi Doyu
2014-07-01 12:14         ` Hiroshi Doyu
2014-06-27 13:29     ` Mikko Perttunen
2014-06-27 13:29       ` Mikko Perttunen
2014-06-27 13:29       ` Mikko Perttunen
2014-06-26 20:49   ` [RFC 05/10] ARM: tegra: Add memory controller on Tegra124 Thierry Reding
2014-06-26 20:49     ` Thierry Reding
2014-06-26 20:49     ` Thierry Reding
2014-06-26 20:49   ` [RFC 06/10] ARM: tegra: tegra124: Enable IOMMU for display controllers Thierry Reding
2014-06-26 20:49     ` Thierry Reding
2014-06-26 20:49     ` Thierry Reding
2014-06-26 20:49   ` [RFC 07/10] ARM: tegra: tegra124: Enable IOMMU for SDMMC controllers Thierry Reding
2014-06-26 20:49     ` Thierry Reding
2014-06-26 20:49     ` Thierry Reding
2014-06-26 20:49   ` [RFC 08/10] ARM: tegra: Select ARM_DMA_USE_IOMMU Thierry Reding
2014-06-26 20:49     ` Thierry Reding
2014-06-26 20:49     ` Thierry Reding
2014-06-26 20:49   ` [RFC 09/10] drm/tegra: Add IOMMU support Thierry Reding
2014-06-26 20:49     ` Thierry Reding
2014-06-26 20:49     ` Thierry Reding
     [not found]     ` <1403815790-8548-10-git-send-email-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2014-06-27  9:46       ` Hiroshi DOyu
2014-06-27  9:46         ` Hiroshi DOyu
2014-06-27  9:46         ` Hiroshi DOyu
     [not found]         ` <20140627124614.050be2e406a4b9a02d9fe97c-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2014-06-27 10:54           ` Arnd Bergmann
2014-06-27 10:54             ` Arnd Bergmann
2014-06-27 10:54             ` Arnd Bergmann
2014-06-27 11:03             ` Hiroshi Doyu
2014-06-27 11:03               ` Hiroshi Doyu
2014-06-27 10:58           ` Thierry Reding
2014-06-27 10:58             ` Thierry Reding
2014-06-27 10:58             ` Thierry Reding
2014-09-30 18:48       ` Sean Paul
2014-09-30 18:48         ` Sean Paul
2014-09-30 18:48         ` Sean Paul
     [not found]         ` <CAOw6vbJy6oy7cibH4f332UM=kS56KUMcnYdUTG0pEYXyQkFDoQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2014-10-01 15:54           ` Sean Paul
2014-10-01 15:54             ` Sean Paul
2014-10-01 15:54             ` Sean Paul
     [not found]             ` <CAOw6vbLFLrqWYB-4N50G7oucgMD+xd+QtdcMSzX4z7xRiU-vPQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2014-10-02  8:39               ` Thierry Reding
2014-10-02  8:39                 ` Thierry Reding
2014-10-02  8:39                 ` Thierry Reding
2014-11-05  9:50               ` Thierry Reding
2014-11-05  9:50                 ` Thierry Reding
2014-11-05  9:50                 ` Thierry Reding
2014-11-05 10:26           ` Thierry Reding
2014-11-05 10:26             ` Thierry Reding
2014-11-05 10:26             ` Thierry Reding
2014-06-26 20:49   ` [RFC 10/10] mmc: sdhci-tegra: " Thierry Reding
2014-06-26 20:49     ` Thierry Reding
2014-06-26 20:49     ` Thierry Reding
     [not found]     ` <1403815790-8548-11-git-send-email-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2014-06-27  9:46       ` Hiroshi DOyu
2014-06-27  9:46         ` Hiroshi DOyu
2014-06-27  9:46         ` Hiroshi DOyu
     [not found]         ` <20140627124602.53d046dae5d7e269815e56a0-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2014-06-27 11:01           ` Thierry Reding
2014-06-27 11:01             ` Thierry Reding
2014-06-27 11:01             ` Thierry Reding

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