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From: Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>
To: Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
	Pawel Moll <Pawel.Moll-5wv7dgnIgG8@public.gmane.org>,
	Mark Rutland <Mark.Rutland-5wv7dgnIgG8@public.gmane.org>,
	Ian Campbell
	<ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>,
	Kumar Gala <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
	Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>,
	Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>,
	Joerg Roedel <joro-zLv9SwRftAIdnm+yROfE0A@public.gmane.org>,
	Cho KyongHo <pullip.cho-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>,
	Grant Grundler <grundler-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>,
	Dave P Martin <Dave.Martin-5wv7dgnIgG8@public.gmane.org>,
	Marc Zyngier <Marc.Zyngier-5wv7dgnIgG8@public.gmane.org>,
	Hiroshi Doyu <hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
	Olav Haugan <ohaugan-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
	Paul Walmsley <pwalmsley-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
	Rhyland Klein <rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
	Allen Martin <amartin-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
	"devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
	<devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
	"iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org"
	<iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org>,
	"linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org"
	<linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>,
	"linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
	<linux-tegra@vger.>
Subject: Re: [PATCH v3 02/10] devicetree: Add generic IOMMU device tree bindings
Date: Fri, 27 Jun 2014 14:55:38 +0100	[thread overview]
Message-ID: <20140627135537.GU26276@arm.com> (raw)
In-Reply-To: <1403815790-8548-3-git-send-email-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

Hi Thierry,

On Thu, Jun 26, 2014 at 09:49:42PM +0100, Thierry Reding wrote:
> From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> 
> This commit introduces a generic device tree binding for IOMMU devices.
> Only a very minimal subset is described here, but it is enough to cover
> the requirements of both the Exynos System MMU and Tegra SMMU as
> discussed here:
> 
>     https://lkml.org/lkml/2014/4/27/346
> 
> Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

[...]

> +Required properties:
> +--------------------
> +- #iommu-cells: The number of cells in an IOMMU specifier needed to encode an
> +  address.
> +
> +Typical values for the above include:
> +- #iommu-cells = <0>: Single master IOMMU devices are not configurable and
> +  therefore no additional information needs to be encoded in the specifier.
> +  This may also apply to multiple master IOMMU devices that do not allow the
> +  association of masters to be configured.

A multiple-master capable IOMMU could be built with a single master, but
we'd still need #iommu-cells > 0 here. I appreciate this is just an example,
but the wording sounds like it's enforced.

> +- #iommu-cells = <1>: Multiple master IOMMU devices may need to be configured
> +  in order to enable translation for a given master. In such cases the single
> +  address cell corresponds to the master device's ID.

Again, we will definitely need more than one cell in this case, as I fully
expect multiple StreamIDs for each master (e.g. Qualcomm mentioned on the
list the other day that they have a master emitting 43 unique IDs).

Anyway, the actual binding looks great, I just don't want people to think
they need to do something different because they don't fit your example
use-cases.

> +Multiple-master IOMMU:
> +----------------------
> +
> +	iommu {
> +		/* the specifier represents the ID of the master */
> +		#iommu-cells = <1>;
> +	};
> +
> +	master {
> +		/* device has master ID 42 in the IOMMU */
> +		iommus = <&/iommu 42>;
> +	};
> +
> +Multiple-master IOMMU with configurable DMA window:
> +---------------------------------------------------
> +
> +	/ {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +
> +		iommu {
> +			/* master ID, address and length of DMA window */
> +			#iommu-cells = <4>;
> +		};
> +
> +		master {
> +			/* master ID 42, 4 GiB DMA window starting at 0 */
> +			iommus = <&/iommu  42  0  0x1 0x0>;
> +		};
> +	};

Could you also please include an example of a master with multiple IDs?

Will

WARNING: multiple messages have this Message-ID (diff)
From: Will Deacon <will.deacon@arm.com>
To: Thierry Reding <thierry.reding@gmail.com>
Cc: Rob Herring <robh+dt@kernel.org>, Pawel Moll <Pawel.Moll@arm.com>,
	Mark Rutland <Mark.Rutland@arm.com>,
	Ian Campbell <ijc+devicetree@hellion.org.uk>,
	Kumar Gala <galak@codeaurora.org>,
	Stephen Warren <swarren@wwwdotorg.org>,
	Arnd Bergmann <arnd@arndb.de>, Joerg Roedel <joro@8bytes.org>,
	Cho KyongHo <pullip.cho@samsung.com>,
	Grant Grundler <grundler@chromium.org>,
	Dave P Martin <Dave.Martin@arm.com>,
	Marc Zyngier <Marc.Zyngier@arm.com>,
	Hiroshi Doyu <hdoyu@nvidia.com>,
	Olav Haugan <ohaugan@codeaurora.org>,
	Paul Walmsley <pwalmsley@nvidia.com>,
	Rhyland Klein <rklein@nvidia.com>,
	Allen Martin <amartin@nvidia.com>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"iommu@lists.linux-foundation.org"
	<iommu@lists.linux-foundation.org>,
	"linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>,
	"linux-tegra@vger.kernel.org" <linux-tegra@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v3 02/10] devicetree: Add generic IOMMU device tree bindings
Date: Fri, 27 Jun 2014 14:55:38 +0100	[thread overview]
Message-ID: <20140627135537.GU26276@arm.com> (raw)
In-Reply-To: <1403815790-8548-3-git-send-email-thierry.reding@gmail.com>

Hi Thierry,

On Thu, Jun 26, 2014 at 09:49:42PM +0100, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> This commit introduces a generic device tree binding for IOMMU devices.
> Only a very minimal subset is described here, but it is enough to cover
> the requirements of both the Exynos System MMU and Tegra SMMU as
> discussed here:
> 
>     https://lkml.org/lkml/2014/4/27/346
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>

[...]

> +Required properties:
> +--------------------
> +- #iommu-cells: The number of cells in an IOMMU specifier needed to encode an
> +  address.
> +
> +Typical values for the above include:
> +- #iommu-cells = <0>: Single master IOMMU devices are not configurable and
> +  therefore no additional information needs to be encoded in the specifier.
> +  This may also apply to multiple master IOMMU devices that do not allow the
> +  association of masters to be configured.

A multiple-master capable IOMMU could be built with a single master, but
we'd still need #iommu-cells > 0 here. I appreciate this is just an example,
but the wording sounds like it's enforced.

> +- #iommu-cells = <1>: Multiple master IOMMU devices may need to be configured
> +  in order to enable translation for a given master. In such cases the single
> +  address cell corresponds to the master device's ID.

Again, we will definitely need more than one cell in this case, as I fully
expect multiple StreamIDs for each master (e.g. Qualcomm mentioned on the
list the other day that they have a master emitting 43 unique IDs).

Anyway, the actual binding looks great, I just don't want people to think
they need to do something different because they don't fit your example
use-cases.

> +Multiple-master IOMMU:
> +----------------------
> +
> +	iommu {
> +		/* the specifier represents the ID of the master */
> +		#iommu-cells = <1>;
> +	};
> +
> +	master {
> +		/* device has master ID 42 in the IOMMU */
> +		iommus = <&/iommu 42>;
> +	};
> +
> +Multiple-master IOMMU with configurable DMA window:
> +---------------------------------------------------
> +
> +	/ {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +
> +		iommu {
> +			/* master ID, address and length of DMA window */
> +			#iommu-cells = <4>;
> +		};
> +
> +		master {
> +			/* master ID 42, 4 GiB DMA window starting at 0 */
> +			iommus = <&/iommu  42  0  0x1 0x0>;
> +		};
> +	};

Could you also please include an example of a master with multiple IDs?

Will

WARNING: multiple messages have this Message-ID (diff)
From: will.deacon@arm.com (Will Deacon)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 02/10] devicetree: Add generic IOMMU device tree bindings
Date: Fri, 27 Jun 2014 14:55:38 +0100	[thread overview]
Message-ID: <20140627135537.GU26276@arm.com> (raw)
In-Reply-To: <1403815790-8548-3-git-send-email-thierry.reding@gmail.com>

Hi Thierry,

On Thu, Jun 26, 2014 at 09:49:42PM +0100, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> This commit introduces a generic device tree binding for IOMMU devices.
> Only a very minimal subset is described here, but it is enough to cover
> the requirements of both the Exynos System MMU and Tegra SMMU as
> discussed here:
> 
>     https://lkml.org/lkml/2014/4/27/346
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>

[...]

> +Required properties:
> +--------------------
> +- #iommu-cells: The number of cells in an IOMMU specifier needed to encode an
> +  address.
> +
> +Typical values for the above include:
> +- #iommu-cells = <0>: Single master IOMMU devices are not configurable and
> +  therefore no additional information needs to be encoded in the specifier.
> +  This may also apply to multiple master IOMMU devices that do not allow the
> +  association of masters to be configured.

A multiple-master capable IOMMU could be built with a single master, but
we'd still need #iommu-cells > 0 here. I appreciate this is just an example,
but the wording sounds like it's enforced.

> +- #iommu-cells = <1>: Multiple master IOMMU devices may need to be configured
> +  in order to enable translation for a given master. In such cases the single
> +  address cell corresponds to the master device's ID.

Again, we will definitely need more than one cell in this case, as I fully
expect multiple StreamIDs for each master (e.g. Qualcomm mentioned on the
list the other day that they have a master emitting 43 unique IDs).

Anyway, the actual binding looks great, I just don't want people to think
they need to do something different because they don't fit your example
use-cases.

> +Multiple-master IOMMU:
> +----------------------
> +
> +	iommu {
> +		/* the specifier represents the ID of the master */
> +		#iommu-cells = <1>;
> +	};
> +
> +	master {
> +		/* device has master ID 42 in the IOMMU */
> +		iommus = <&/iommu 42>;
> +	};
> +
> +Multiple-master IOMMU with configurable DMA window:
> +---------------------------------------------------
> +
> +	/ {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +
> +		iommu {
> +			/* master ID, address and length of DMA window */
> +			#iommu-cells = <4>;
> +		};
> +
> +		master {
> +			/* master ID 42, 4 GiB DMA window starting at 0 */
> +			iommus = <&/iommu  42  0  0x1 0x0>;
> +		};
> +	};

Could you also please include an example of a master with multiple IDs?

Will

  parent reply	other threads:[~2014-06-27 13:55 UTC|newest]

Thread overview: 133+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-06-26 20:49 [RFC 00/10] Add NVIDIA Tegra124 IOMMU support Thierry Reding
2014-06-26 20:49 ` Thierry Reding
2014-06-26 20:49 ` Thierry Reding
     [not found] ` <1403815790-8548-1-git-send-email-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2014-06-26 20:49   ` [RFC 01/10] iommu: Add IOMMU device registry Thierry Reding
2014-06-26 20:49     ` Thierry Reding
2014-06-26 20:49     ` Thierry Reding
     [not found]     ` <1403815790-8548-2-git-send-email-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2014-06-27  6:58       ` Thierry Reding
2014-06-27  6:58         ` Thierry Reding
2014-06-27  6:58         ` Thierry Reding
2014-07-03 10:37         ` Varun Sethi
2014-07-03 10:37           ` Varun Sethi
2014-07-03 10:37           ` Varun Sethi
2014-07-04 11:05       ` Joerg Roedel
2014-07-04 11:05         ` Joerg Roedel
2014-07-04 11:05         ` Joerg Roedel
     [not found]         ` <20140704110529.GF13434-zLv9SwRftAIdnm+yROfE0A@public.gmane.org>
2014-07-04 13:47           ` Thierry Reding
2014-07-04 13:47             ` Thierry Reding
2014-07-04 13:47             ` Thierry Reding
2014-07-04 13:49             ` Will Deacon
2014-07-04 13:49               ` Will Deacon
2014-07-04 13:49               ` Will Deacon
     [not found]               ` <20140704134928.GA25714-5wv7dgnIgG8@public.gmane.org>
2014-07-06 18:17                 ` Arnd Bergmann
2014-07-06 18:17                   ` Arnd Bergmann
2014-07-06 18:17                   ` Arnd Bergmann
     [not found]                   ` <201407062017.23049.arnd-r2nGTMty4D4@public.gmane.org>
2014-07-07 11:42                     ` Thierry Reding
2014-07-07 11:42                       ` Thierry Reding
2014-07-07 11:42                       ` Thierry Reding
2014-06-26 20:49   ` [PATCH v3 02/10] devicetree: Add generic IOMMU device tree bindings Thierry Reding
2014-06-26 20:49     ` Thierry Reding
2014-06-26 20:49     ` Thierry Reding
     [not found]     ` <1403815790-8548-3-git-send-email-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2014-06-27 13:55       ` Will Deacon [this message]
2014-06-27 13:55         ` Will Deacon
2014-06-27 13:55         ` Will Deacon
2014-06-30 22:24       ` Stephen Warren
2014-06-30 22:24         ` Stephen Warren
2014-06-30 22:24         ` Stephen Warren
2014-07-04  6:42       ` Varun Sethi
2014-07-04  6:42         ` Varun Sethi
2014-07-04  6:42         ` Varun Sethi
     [not found]         ` <9ffe3c3871ef4b60a955259bfa0bed6c-AZ66ij2kwaacCcN9WK45f+O6mTEJWrR4XA4E9RH9d+qIuWR1G4zioA@public.gmane.org>
2014-07-04  9:05           ` Arnd Bergmann
2014-07-04  9:05             ` Arnd Bergmann
2014-07-04  9:05             ` Arnd Bergmann
2014-06-26 20:49   ` [RFC 03/10] of: Add NVIDIA Tegra124 memory controller binding Thierry Reding
2014-06-26 20:49     ` Thierry Reding
2014-06-26 20:49     ` Thierry Reding
2014-06-26 20:49   ` [RFC 04/10] memory: Add Tegra124 memory controller support Thierry Reding
2014-06-26 20:49     ` Thierry Reding
2014-06-26 20:49     ` Thierry Reding
     [not found]     ` <1403815790-8548-5-git-send-email-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2014-06-27  7:41       ` Joseph Lo
2014-06-27  7:41         ` Joseph Lo
2014-06-27  7:41         ` Joseph Lo
     [not found]         ` <53AD2020.1050802-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2014-06-27  8:17           ` Thierry Reding
2014-06-27  8:17             ` Thierry Reding
2014-06-27  8:17             ` Thierry Reding
2014-06-27  8:24             ` Hiroshi Doyu
2014-06-27  8:24               ` Hiroshi Doyu
2014-06-27  9:46       ` Hiroshi DOyu
2014-06-27  9:46         ` Hiroshi DOyu
2014-06-27  9:46         ` Hiroshi DOyu
     [not found]         ` <20140627124638.7ec150cca163c89727b8953f-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2014-06-27 11:08           ` Thierry Reding
2014-06-27 11:08             ` Thierry Reding
2014-06-27 11:08             ` Thierry Reding
2014-06-27 21:33             ` Stephen Warren
2014-06-27 21:33               ` Stephen Warren
2014-06-27 21:33               ` Stephen Warren
2014-06-27 11:07       ` Arnd Bergmann
2014-06-27 11:07         ` Arnd Bergmann
2014-06-27 11:07         ` Arnd Bergmann
2014-06-27 11:15         ` Thierry Reding
2014-06-27 11:15           ` Thierry Reding
2014-06-27 11:15           ` Thierry Reding
2014-06-27 21:37           ` Stephen Warren
2014-06-27 21:37             ` Stephen Warren
2014-06-27 21:37             ` Stephen Warren
2014-06-30 22:43       ` Stephen Warren
2014-06-30 22:43         ` Stephen Warren
2014-06-30 22:43         ` Stephen Warren
2014-07-01 12:14       ` Hiroshi Doyu
2014-07-01 12:14         ` Hiroshi Doyu
2014-07-01 12:14         ` Hiroshi Doyu
2014-06-27 13:29     ` Mikko Perttunen
2014-06-27 13:29       ` Mikko Perttunen
2014-06-27 13:29       ` Mikko Perttunen
2014-06-26 20:49   ` [RFC 05/10] ARM: tegra: Add memory controller on Tegra124 Thierry Reding
2014-06-26 20:49     ` Thierry Reding
2014-06-26 20:49     ` Thierry Reding
2014-06-26 20:49   ` [RFC 06/10] ARM: tegra: tegra124: Enable IOMMU for display controllers Thierry Reding
2014-06-26 20:49     ` Thierry Reding
2014-06-26 20:49     ` Thierry Reding
2014-06-26 20:49   ` [RFC 07/10] ARM: tegra: tegra124: Enable IOMMU for SDMMC controllers Thierry Reding
2014-06-26 20:49     ` Thierry Reding
2014-06-26 20:49     ` Thierry Reding
2014-06-26 20:49   ` [RFC 08/10] ARM: tegra: Select ARM_DMA_USE_IOMMU Thierry Reding
2014-06-26 20:49     ` Thierry Reding
2014-06-26 20:49     ` Thierry Reding
2014-06-26 20:49   ` [RFC 09/10] drm/tegra: Add IOMMU support Thierry Reding
2014-06-26 20:49     ` Thierry Reding
2014-06-26 20:49     ` Thierry Reding
     [not found]     ` <1403815790-8548-10-git-send-email-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2014-06-27  9:46       ` Hiroshi DOyu
2014-06-27  9:46         ` Hiroshi DOyu
2014-06-27  9:46         ` Hiroshi DOyu
     [not found]         ` <20140627124614.050be2e406a4b9a02d9fe97c-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2014-06-27 10:54           ` Arnd Bergmann
2014-06-27 10:54             ` Arnd Bergmann
2014-06-27 10:54             ` Arnd Bergmann
2014-06-27 11:03             ` Hiroshi Doyu
2014-06-27 11:03               ` Hiroshi Doyu
2014-06-27 10:58           ` Thierry Reding
2014-06-27 10:58             ` Thierry Reding
2014-06-27 10:58             ` Thierry Reding
2014-09-30 18:48       ` Sean Paul
2014-09-30 18:48         ` Sean Paul
2014-09-30 18:48         ` Sean Paul
     [not found]         ` <CAOw6vbJy6oy7cibH4f332UM=kS56KUMcnYdUTG0pEYXyQkFDoQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2014-10-01 15:54           ` Sean Paul
2014-10-01 15:54             ` Sean Paul
2014-10-01 15:54             ` Sean Paul
     [not found]             ` <CAOw6vbLFLrqWYB-4N50G7oucgMD+xd+QtdcMSzX4z7xRiU-vPQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2014-10-02  8:39               ` Thierry Reding
2014-10-02  8:39                 ` Thierry Reding
2014-10-02  8:39                 ` Thierry Reding
2014-11-05  9:50               ` Thierry Reding
2014-11-05  9:50                 ` Thierry Reding
2014-11-05  9:50                 ` Thierry Reding
2014-11-05 10:26           ` Thierry Reding
2014-11-05 10:26             ` Thierry Reding
2014-11-05 10:26             ` Thierry Reding
2014-06-26 20:49   ` [RFC 10/10] mmc: sdhci-tegra: " Thierry Reding
2014-06-26 20:49     ` Thierry Reding
2014-06-26 20:49     ` Thierry Reding
     [not found]     ` <1403815790-8548-11-git-send-email-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2014-06-27  9:46       ` Hiroshi DOyu
2014-06-27  9:46         ` Hiroshi DOyu
2014-06-27  9:46         ` Hiroshi DOyu
     [not found]         ` <20140627124602.53d046dae5d7e269815e56a0-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2014-06-27 11:01           ` Thierry Reding
2014-06-27 11:01             ` Thierry Reding
2014-06-27 11:01             ` Thierry Reding

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