From: Mark Rutland <mark.rutland@arm.com> To: "suravee.suthikulpanit@amd.com" <suravee.suthikulpanit@amd.com> Cc: Marc Zyngier <Marc.Zyngier@arm.com>, "jason@lakedaemon.net" <jason@lakedaemon.net>, Pawel Moll <Pawel.Moll@arm.com>, Catalin Marinas <Catalin.Marinas@arm.com>, Will Deacon <Will.Deacon@arm.com>, "tglx@linutronix.de" <tglx@linutronix.de>, "Harish.Kasiviswanathan@amd.com" <Harish.Kasiviswanathan@amd.com>, "linux-arm-kernel@lists.infradead.org" <linux-arm-kernel@lists.infradead.org>, "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, "linux-doc@vger.kernel.org" <linux-doc@vger.kernel.org>, "devicetree@vger.kernel.org" <devicetree@vger.kernel.org> Subject: Re: [PATCH 1/2 V4] irqchip: gic: Add supports for ARM GICv2m MSI(-X) Date: Thu, 14 Aug 2014 18:55:26 +0100 [thread overview] Message-ID: <20140814175525.GI24018@leverpostej> (raw) In-Reply-To: <1407942041-3291-2-git-send-email-suravee.suthikulpanit@amd.com> On Wed, Aug 13, 2014 at 04:00:40PM +0100, suravee.suthikulpanit@amd.com wrote: > From: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> > > ARM GICv2m specification extends GICv2 to support MSI(-X) with > a new set of register frame. This patch introduces support for > the non-secure GICv2m register frame. Currently, GICV2m is available > in certain version of GIC-400. > > The patch introduces a new property in ARM gic binding, the v2m subnode. > It is optional. > > Signed-off-by: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> > Cc: Mark Rutland <Mark.Rutland@arm.com> > Cc: Marc Zyngier <Marc.Zyngier@arm.com> > Cc: Jason Cooper <jason@lakedaemon.net> > Cc: Catalin Marinas <Catalin.Marinas@arm.com> > Cc: Will Deacon <Will.Deacon@arm.com> > --- > Documentation/devicetree/bindings/arm/gic.txt | 32 ++++ > drivers/irqchip/Kconfig | 7 + > drivers/irqchip/Makefile | 1 + > drivers/irqchip/irq-gic-v2m.c | 215 ++++++++++++++++++++++++++ > drivers/irqchip/irq-gic.c | 75 +++++---- > drivers/irqchip/irq-gic.h | 48 ++++++ > 6 files changed, 348 insertions(+), 30 deletions(-) > create mode 100644 drivers/irqchip/irq-gic-v2m.c > create mode 100644 drivers/irqchip/irq-gic.h > > diff --git a/Documentation/devicetree/bindings/arm/gic.txt b/Documentation/devicetree/bindings/arm/gic.txt > index 5573c08..8a64179 100644 > --- a/Documentation/devicetree/bindings/arm/gic.txt > +++ b/Documentation/devicetree/bindings/arm/gic.txt > @@ -95,3 +95,35 @@ Example: > <0x2c006000 0x2000>; > interrupts = <1 9 0xf04>; > }; > + > + > +* GICv2m extension for MSI/MSI-x support (Optional) > + > +Certain revision of GIC-400 supports MSI/MSI-x via V2M register frame. > +This is enabled by specifying v2m sub-node. > + > +Required properties: > + > +- msi-controller : Identifies the node as an MSI controller. > + > +- reg : GICv2m MSI interface register base and size > + > +Example: > + > + interrupt-controller@e1101000 { > + compatible = "arm,gic-400"; > + #interrupt-cells = <3>; > + #address-cells = <2>; > + #size-cells = <2>; > + interrupt-controller; > + interrupts = <1 8 0xf04>; > + ranges = <0 0 0 0xe1100000 0 0x100000>; > + reg = <0x0 0xe1110000 0 0x01000>, > + <0x0 0xe112f000 0 0x02000>, > + <0x0 0xe1140000 0 0x10000>, > + <0x0 0xe1160000 0 0x10000>; > + v2m { > + msi-controller; > + reg = <0x0 0x80000 0 0x1000>; > + }; > + }; [...] > @@ -1009,6 +1012,16 @@ gic_of_init(struct device_node *node, struct device_node *parent) > if (of_property_read_u32(node, "cpu-offset", &percpu_offset)) > percpu_offset = 0; > > + gic_data[gic_cnt].irq_chip = &gic_chip; > + > + /* Currently, we only support one v2m subnode. */ > + child = of_get_child_by_name(node, "v2m"); > + if (child) { > + ret = gicv2m_of_init(child, &gic_data[gic_cnt]); > + if (ret) > + return ret; > + } I can't see how you'd sanely expand this to multiple children, which was the main point of having a separate node for the M block. Give the M block a compatible string and look for children with that string. Thanks, Mark.
WARNING: multiple messages have this Message-ID (diff)
From: mark.rutland@arm.com (Mark Rutland) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/2 V4] irqchip: gic: Add supports for ARM GICv2m MSI(-X) Date: Thu, 14 Aug 2014 18:55:26 +0100 [thread overview] Message-ID: <20140814175525.GI24018@leverpostej> (raw) In-Reply-To: <1407942041-3291-2-git-send-email-suravee.suthikulpanit@amd.com> On Wed, Aug 13, 2014 at 04:00:40PM +0100, suravee.suthikulpanit at amd.com wrote: > From: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> > > ARM GICv2m specification extends GICv2 to support MSI(-X) with > a new set of register frame. This patch introduces support for > the non-secure GICv2m register frame. Currently, GICV2m is available > in certain version of GIC-400. > > The patch introduces a new property in ARM gic binding, the v2m subnode. > It is optional. > > Signed-off-by: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> > Cc: Mark Rutland <Mark.Rutland@arm.com> > Cc: Marc Zyngier <Marc.Zyngier@arm.com> > Cc: Jason Cooper <jason@lakedaemon.net> > Cc: Catalin Marinas <Catalin.Marinas@arm.com> > Cc: Will Deacon <Will.Deacon@arm.com> > --- > Documentation/devicetree/bindings/arm/gic.txt | 32 ++++ > drivers/irqchip/Kconfig | 7 + > drivers/irqchip/Makefile | 1 + > drivers/irqchip/irq-gic-v2m.c | 215 ++++++++++++++++++++++++++ > drivers/irqchip/irq-gic.c | 75 +++++---- > drivers/irqchip/irq-gic.h | 48 ++++++ > 6 files changed, 348 insertions(+), 30 deletions(-) > create mode 100644 drivers/irqchip/irq-gic-v2m.c > create mode 100644 drivers/irqchip/irq-gic.h > > diff --git a/Documentation/devicetree/bindings/arm/gic.txt b/Documentation/devicetree/bindings/arm/gic.txt > index 5573c08..8a64179 100644 > --- a/Documentation/devicetree/bindings/arm/gic.txt > +++ b/Documentation/devicetree/bindings/arm/gic.txt > @@ -95,3 +95,35 @@ Example: > <0x2c006000 0x2000>; > interrupts = <1 9 0xf04>; > }; > + > + > +* GICv2m extension for MSI/MSI-x support (Optional) > + > +Certain revision of GIC-400 supports MSI/MSI-x via V2M register frame. > +This is enabled by specifying v2m sub-node. > + > +Required properties: > + > +- msi-controller : Identifies the node as an MSI controller. > + > +- reg : GICv2m MSI interface register base and size > + > +Example: > + > + interrupt-controller at e1101000 { > + compatible = "arm,gic-400"; > + #interrupt-cells = <3>; > + #address-cells = <2>; > + #size-cells = <2>; > + interrupt-controller; > + interrupts = <1 8 0xf04>; > + ranges = <0 0 0 0xe1100000 0 0x100000>; > + reg = <0x0 0xe1110000 0 0x01000>, > + <0x0 0xe112f000 0 0x02000>, > + <0x0 0xe1140000 0 0x10000>, > + <0x0 0xe1160000 0 0x10000>; > + v2m { > + msi-controller; > + reg = <0x0 0x80000 0 0x1000>; > + }; > + }; [...] > @@ -1009,6 +1012,16 @@ gic_of_init(struct device_node *node, struct device_node *parent) > if (of_property_read_u32(node, "cpu-offset", &percpu_offset)) > percpu_offset = 0; > > + gic_data[gic_cnt].irq_chip = &gic_chip; > + > + /* Currently, we only support one v2m subnode. */ > + child = of_get_child_by_name(node, "v2m"); > + if (child) { > + ret = gicv2m_of_init(child, &gic_data[gic_cnt]); > + if (ret) > + return ret; > + } I can't see how you'd sanely expand this to multiple children, which was the main point of having a separate node for the M block. Give the M block a compatible string and look for children with that string. Thanks, Mark.
next prev parent reply other threads:[~2014-08-14 17:56 UTC|newest] Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top 2014-08-13 15:00 [PATCH 0/2 V4] irqchip: gic: Introduce ARM GICv2m MSI(-X) support suravee.suthikulpanit 2014-08-13 15:00 ` suravee.suthikulpanit at amd.com 2014-08-13 15:00 ` suravee.suthikulpanit-5C7GfCeVMHo 2014-08-13 15:00 ` [PATCH 1/2 V4] irqchip: gic: Add supports for ARM GICv2m MSI(-X) suravee.suthikulpanit 2014-08-13 15:00 ` suravee.suthikulpanit at amd.com 2014-08-13 15:00 ` suravee.suthikulpanit 2014-08-14 2:56 ` Jingoo Han 2014-08-14 2:56 ` Jingoo Han 2014-08-28 9:15 ` Suravee Suthikulpanit 2014-08-28 9:15 ` Suravee Suthikulpanit 2014-08-28 9:15 ` Suravee Suthikulpanit 2014-08-14 17:55 ` Mark Rutland [this message] 2014-08-14 17:55 ` Mark Rutland 2014-08-14 17:55 ` Mark Rutland 2014-08-28 9:03 ` Suravee Suthikulpanit 2014-08-28 9:03 ` Suravee Suthikulpanit 2014-08-28 9:03 ` Suravee Suthikulpanit 2014-09-08 23:05 ` Suravee Suthikulpanit 2014-09-08 23:05 ` Suravee Suthikulpanit 2014-09-08 23:05 ` Suravee Suthikulpanit 2014-09-08 23:05 ` Suravee Suthikulpanit 2014-09-09 11:03 ` Mark Rutland 2014-09-09 11:03 ` Mark Rutland 2014-09-09 11:03 ` Mark Rutland 2014-08-15 14:03 ` Marc Zyngier 2014-08-15 14:03 ` Marc Zyngier 2014-08-15 14:03 ` Marc Zyngier 2014-08-15 14:03 ` Marc Zyngier 2014-08-28 8:59 ` Suravee Suthikulpanit 2014-08-28 8:59 ` Suravee Suthikulpanit 2014-08-28 8:59 ` Suravee Suthikulpanit 2014-09-05 16:15 ` Marc Zyngier 2014-09-05 16:15 ` Marc Zyngier 2014-09-05 16:15 ` Marc Zyngier 2014-09-05 16:15 ` Marc Zyngier 2014-08-13 15:00 ` [PATCH 2/2 V4] irqchip: gicv2m: Add support for multiple MSI for ARM64 GICv2m suravee.suthikulpanit 2014-08-13 15:00 ` suravee.suthikulpanit at amd.com 2014-08-13 15:00 ` suravee.suthikulpanit 2014-08-15 13:31 ` Marc Zyngier 2014-08-15 13:31 ` Marc Zyngier 2014-08-15 13:31 ` Marc Zyngier 2014-08-15 13:31 ` Marc Zyngier 2014-08-15 14:53 ` Suravee Suthikulanit 2014-08-15 14:53 ` Suravee Suthikulanit 2014-08-15 14:53 ` Suravee Suthikulanit 2014-08-15 15:08 ` Marc Zyngier 2014-08-15 15:08 ` Marc Zyngier 2014-08-15 15:08 ` Marc Zyngier 2014-08-15 15:08 ` Marc Zyngier
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20140814175525.GI24018@leverpostej \ --to=mark.rutland@arm.com \ --cc=Catalin.Marinas@arm.com \ --cc=Harish.Kasiviswanathan@amd.com \ --cc=Marc.Zyngier@arm.com \ --cc=Pawel.Moll@arm.com \ --cc=Will.Deacon@arm.com \ --cc=devicetree@vger.kernel.org \ --cc=jason@lakedaemon.net \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-doc@vger.kernel.org \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-pci@vger.kernel.org \ --cc=suravee.suthikulpanit@amd.com \ --cc=tglx@linutronix.de \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.