From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
To: Jingoo Han <jg1.han@samsung.com>
Cc: <marc.zyngier@arm.com>, <mark.rutland@arm.com>,
<jason@lakedaemon.net>, <pawel.moll@arm.com>,
<Catalin.Marinas@arm.com>, <Will.Deacon@arm.com>,
<tglx@linutronix.de>, <Harish.Kasiviswanathan@amd.com>,
<linux-arm-kernel@lists.infradead.org>,
<linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-doc@vger.kernel.org>, <devicetree@vger.kernel.org>
Subject: Re: [PATCH 1/2 V4] irqchip: gic: Add supports for ARM GICv2m MSI(-X)
Date: Thu, 28 Aug 2014 04:15:17 -0500 [thread overview]
Message-ID: <53FEF325.20505@amd.com> (raw)
In-Reply-To: <003d01cfb76b$629b43c0$27d1cb40$%han@samsung.com>
On 08/13/2014 09:56 PM, Jingoo Han wrote:
> On Thursday, August 14, 2014 12:01 AM, Suravee Suthikulpanit wrote:
>>
>> From: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>
>>
>> ARM GICv2m specification extends GICv2 to support MSI(-X) with
>> a new set of register frame. This patch introduces support for
>> the non-secure GICv2m register frame. Currently, GICV2m is available
>> in certain version of GIC-400.
>>
>> The patch introduces a new property in ARM gic binding, the v2m subnode.
>> It is optional.
>
> Hi Suravee Suthikulpanit,
>
> I added some minor comments.
Thanks for the cleaning up comments.
Suravee
WARNING: multiple messages have this Message-ID (diff)
From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
To: Jingoo Han <jg1.han@samsung.com>
Cc: marc.zyngier@arm.com, mark.rutland@arm.com, jason@lakedaemon.net,
pawel.moll@arm.com, Catalin.Marinas@arm.com, Will.Deacon@arm.com,
tglx@linutronix.de, Harish.Kasiviswanathan@amd.com,
linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org,
devicetree@vger.kernel.org
Subject: Re: [PATCH 1/2 V4] irqchip: gic: Add supports for ARM GICv2m MSI(-X)
Date: Thu, 28 Aug 2014 04:15:17 -0500 [thread overview]
Message-ID: <53FEF325.20505@amd.com> (raw)
In-Reply-To: <003d01cfb76b$629b43c0$27d1cb40$%han@samsung.com>
On 08/13/2014 09:56 PM, Jingoo Han wrote:
> On Thursday, August 14, 2014 12:01 AM, Suravee Suthikulpanit wrote:
>>
>> From: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>
>>
>> ARM GICv2m specification extends GICv2 to support MSI(-X) with
>> a new set of register frame. This patch introduces support for
>> the non-secure GICv2m register frame. Currently, GICV2m is available
>> in certain version of GIC-400.
>>
>> The patch introduces a new property in ARM gic binding, the v2m subnode.
>> It is optional.
>
> Hi Suravee Suthikulpanit,
>
> I added some minor comments.
Thanks for the cleaning up comments.
Suravee
WARNING: multiple messages have this Message-ID (diff)
From: suravee.suthikulpanit@amd.com (Suravee Suthikulpanit)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 1/2 V4] irqchip: gic: Add supports for ARM GICv2m MSI(-X)
Date: Thu, 28 Aug 2014 04:15:17 -0500 [thread overview]
Message-ID: <53FEF325.20505@amd.com> (raw)
In-Reply-To: <003d01cfb76b$629b43c0$27d1cb40$%han@samsung.com>
On 08/13/2014 09:56 PM, Jingoo Han wrote:
> On Thursday, August 14, 2014 12:01 AM, Suravee Suthikulpanit wrote:
>>
>> From: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>
>>
>> ARM GICv2m specification extends GICv2 to support MSI(-X) with
>> a new set of register frame. This patch introduces support for
>> the non-secure GICv2m register frame. Currently, GICV2m is available
>> in certain version of GIC-400.
>>
>> The patch introduces a new property in ARM gic binding, the v2m subnode.
>> It is optional.
>
> Hi Suravee Suthikulpanit,
>
> I added some minor comments.
Thanks for the cleaning up comments.
Suravee
next prev parent reply other threads:[~2014-08-28 9:15 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-08-13 15:00 [PATCH 0/2 V4] irqchip: gic: Introduce ARM GICv2m MSI(-X) support suravee.suthikulpanit
2014-08-13 15:00 ` suravee.suthikulpanit at amd.com
2014-08-13 15:00 ` suravee.suthikulpanit-5C7GfCeVMHo
2014-08-13 15:00 ` [PATCH 1/2 V4] irqchip: gic: Add supports for ARM GICv2m MSI(-X) suravee.suthikulpanit
2014-08-13 15:00 ` suravee.suthikulpanit at amd.com
2014-08-13 15:00 ` suravee.suthikulpanit
2014-08-14 2:56 ` Jingoo Han
2014-08-14 2:56 ` Jingoo Han
2014-08-28 9:15 ` Suravee Suthikulpanit [this message]
2014-08-28 9:15 ` Suravee Suthikulpanit
2014-08-28 9:15 ` Suravee Suthikulpanit
2014-08-14 17:55 ` Mark Rutland
2014-08-14 17:55 ` Mark Rutland
2014-08-14 17:55 ` Mark Rutland
2014-08-28 9:03 ` Suravee Suthikulpanit
2014-08-28 9:03 ` Suravee Suthikulpanit
2014-08-28 9:03 ` Suravee Suthikulpanit
2014-09-08 23:05 ` Suravee Suthikulpanit
2014-09-08 23:05 ` Suravee Suthikulpanit
2014-09-08 23:05 ` Suravee Suthikulpanit
2014-09-08 23:05 ` Suravee Suthikulpanit
2014-09-09 11:03 ` Mark Rutland
2014-09-09 11:03 ` Mark Rutland
2014-09-09 11:03 ` Mark Rutland
2014-08-15 14:03 ` Marc Zyngier
2014-08-15 14:03 ` Marc Zyngier
2014-08-15 14:03 ` Marc Zyngier
2014-08-15 14:03 ` Marc Zyngier
2014-08-28 8:59 ` Suravee Suthikulpanit
2014-08-28 8:59 ` Suravee Suthikulpanit
2014-08-28 8:59 ` Suravee Suthikulpanit
2014-09-05 16:15 ` Marc Zyngier
2014-09-05 16:15 ` Marc Zyngier
2014-09-05 16:15 ` Marc Zyngier
2014-09-05 16:15 ` Marc Zyngier
2014-08-13 15:00 ` [PATCH 2/2 V4] irqchip: gicv2m: Add support for multiple MSI for ARM64 GICv2m suravee.suthikulpanit
2014-08-13 15:00 ` suravee.suthikulpanit at amd.com
2014-08-13 15:00 ` suravee.suthikulpanit
2014-08-15 13:31 ` Marc Zyngier
2014-08-15 13:31 ` Marc Zyngier
2014-08-15 13:31 ` Marc Zyngier
2014-08-15 13:31 ` Marc Zyngier
2014-08-15 14:53 ` Suravee Suthikulanit
2014-08-15 14:53 ` Suravee Suthikulanit
2014-08-15 14:53 ` Suravee Suthikulanit
2014-08-15 15:08 ` Marc Zyngier
2014-08-15 15:08 ` Marc Zyngier
2014-08-15 15:08 ` Marc Zyngier
2014-08-15 15:08 ` Marc Zyngier
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