[PATCH 00/13] net: can: Add can support for TI platforms

[PATCH 00/13] net: can: Add can support for TI platforms

[Roger Quadros]

Hi,

Some hardware (TI am43xx) has a buggy RAMINIT DONE mechanism and it might
not always set the DONE bit. This will result in a lockup in c_can_hw_raminit_wait_ti(),
so patch 1 adds a timeout mechanism there.

There is a non compliancy within TI platforms with respect to the
layout of the RAMINIT register. The patches 2 and 3 address this issue
and make a flexible but standard way of defining the RAMINIT hardware register
layout in the device tree. The RAMINIT register is accessed using the syscon
regmap framework.

The patches 4 to 13 add adaptation details for am43xx and dra7x Socs and
EVMs.

cheers,
-roger

---

Afzal Mohammed (1):
  arm: dts: am4372: Add dcan nodes

Dave Gerlach (1):
  ARM: dts: am437x-gp-evm: Add pinctrl sleep states for dcan pins

Mugunthan V N (1):
  arm: dts: am437x-gp: Add dcan support

Roger Quadros (10):
  can: c_can_platform: Fix c_can_hw_raminit_ti() and add timeout
  net: can: c_can: Add syscon/regmap RAMINIT mechanism
  net: can: c_can: Add support for START pulse in RAMINIT sequence
  ARM: dts: dra7: Add syscon regmap for CORE CONTROL area
  ARM: dts: DRA7: Add DCAN nodes
  ARM: dts: dra7-evm: Add CAN support
  ARM: dts: dra72-evm: Add CAN support
  ARM: dts: AM43xx: Add aliases to d_can nodes
  ARM: dts: am4372: Add control module syscon node
  ARM: dts: am4372: Add dcan raminit bits

 .../devicetree/bindings/net/can/c_can.txt          |  10 ++
 arch/arm/boot/dts/am4372.dtsi                      |  35 ++++++
 arch/arm/boot/dts/am437x-gp-evm.dts                |  42 ++++++++
 arch/arm/boot/dts/dra7-evm.dts                     |  21 ++++
 arch/arm/boot/dts/dra7.dtsi                        |  35 ++++++
 arch/arm/boot/dts/dra72-evm.dts                    |  23 ++++
 drivers/net/can/c_can/c_can.h                      |  12 ++-
 drivers/net/can/c_can/c_can_platform.c             | 120 ++++++++++++++++-----
 8 files changed, 270 insertions(+), 28 deletions(-)

-- 
1.8.3.2

[PATCH 00/13] net: can: Add can support for TI platforms

[Roger Quadros]

Hi,

Some hardware (TI am43xx) has a buggy RAMINIT DONE mechanism and it might
not always set the DONE bit. This will result in a lockup in c_can_hw_raminit_wait_ti(),
so patch 1 adds a timeout mechanism there.

There is a non compliancy within TI platforms with respect to the
layout of the RAMINIT register. The patches 2 and 3 address this issue
and make a flexible but standard way of defining the RAMINIT hardware register
layout in the device tree. The RAMINIT register is accessed using the syscon
regmap framework.

The patches 4 to 13 add adaptation details for am43xx and dra7x Socs and
EVMs.

cheers,
-roger

---

Afzal Mohammed (1):
  arm: dts: am4372: Add dcan nodes

Dave Gerlach (1):
  ARM: dts: am437x-gp-evm: Add pinctrl sleep states for dcan pins

Mugunthan V N (1):
  arm: dts: am437x-gp: Add dcan support

Roger Quadros (10):
  can: c_can_platform: Fix c_can_hw_raminit_ti() and add timeout
  net: can: c_can: Add syscon/regmap RAMINIT mechanism
  net: can: c_can: Add support for START pulse in RAMINIT sequence
  ARM: dts: dra7: Add syscon regmap for CORE CONTROL area
  ARM: dts: DRA7: Add DCAN nodes
  ARM: dts: dra7-evm: Add CAN support
  ARM: dts: dra72-evm: Add CAN support
  ARM: dts: AM43xx: Add aliases to d_can nodes
  ARM: dts: am4372: Add control module syscon node
  ARM: dts: am4372: Add dcan raminit bits

 .../devicetree/bindings/net/can/c_can.txt          |  10 ++
 arch/arm/boot/dts/am4372.dtsi                      |  35 ++++++
 arch/arm/boot/dts/am437x-gp-evm.dts                |  42 ++++++++
 arch/arm/boot/dts/dra7-evm.dts                     |  21 ++++
 arch/arm/boot/dts/dra7.dtsi                        |  35 ++++++
 arch/arm/boot/dts/dra72-evm.dts                    |  23 ++++
 drivers/net/can/c_can/c_can.h                      |  12 ++-
 drivers/net/can/c_can/c_can_platform.c             | 120 ++++++++++++++++-----
 8 files changed, 270 insertions(+), 28 deletions(-)

-- 
1.8.3.2

[PATCH 01/13] can: c_can_platform: Fix c_can_hw_raminit_ti() and add timeout

[Roger Quadros]

Pass the correct 'mask' and 'value' bits to c_can_hw_raminit_wait_ti().
They seem to have been swapped in the usage instances.

TI's RAMINIT DONE mechanism is buggy and may not always be
set after the START bit is set. So add a timeout mechanism to
c_can_hw_raminit_wait_ti().

Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 drivers/net/can/c_can/c_can_platform.c | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/net/can/c_can/c_can_platform.c b/drivers/net/can/c_can/c_can_platform.c
index 109cb44..b144e71 100644
--- a/drivers/net/can/c_can/c_can_platform.c
+++ b/drivers/net/can/c_can/c_can_platform.c
@@ -75,10 +75,18 @@ static void c_can_plat_write_reg_aligned_to_32bit(const struct c_can_priv *priv,
 static void c_can_hw_raminit_wait_ti(const struct c_can_priv *priv, u32 mask,
 				  u32 val)
 {
+	int timeout = 0;
 	/* We look only at the bits of our instance. */
 	val &= mask;
-	while ((readl(priv->raminit_ctrlreg) & mask) != val)
+	while ((readl(priv->raminit_ctrlreg) & mask) != val) {
 		udelay(1);
+		timeout++;
+
+		if (timeout == 1000) {
+			dev_err(&priv->dev->dev, "%s: time out\n", __func__);
+			break;
+		}
+	}
 }
 
 static void c_can_hw_raminit_ti(const struct c_can_priv *priv, bool enable)
@@ -97,14 +105,14 @@ static void c_can_hw_raminit_ti(const struct c_can_priv *priv, bool enable)
 	ctrl |= CAN_RAMINIT_DONE_MASK(priv->instance);
 	writel(ctrl, priv->raminit_ctrlreg);
 	ctrl &= ~CAN_RAMINIT_DONE_MASK(priv->instance);
-	c_can_hw_raminit_wait_ti(priv, ctrl, mask);
+	c_can_hw_raminit_wait_ti(priv, mask, ctrl);
 
 	if (enable) {
 		/* Set start bit and wait for the done bit. */
 		ctrl |= CAN_RAMINIT_START_MASK(priv->instance);
 		writel(ctrl, priv->raminit_ctrlreg);
 		ctrl |= CAN_RAMINIT_DONE_MASK(priv->instance);
-		c_can_hw_raminit_wait_ti(priv, ctrl, mask);
+		c_can_hw_raminit_wait_ti(priv, mask, ctrl);
 	}
 	spin_unlock(&raminit_lock);
 }
-- 
1.8.3.2

[PATCH 01/13] can: c_can_platform: Fix c_can_hw_raminit_ti() and add timeout

[Roger Quadros]

Pass the correct 'mask' and 'value' bits to c_can_hw_raminit_wait_ti().
They seem to have been swapped in the usage instances.

TI's RAMINIT DONE mechanism is buggy and may not always be
set after the START bit is set. So add a timeout mechanism to
c_can_hw_raminit_wait_ti().

Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 drivers/net/can/c_can/c_can_platform.c | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/net/can/c_can/c_can_platform.c b/drivers/net/can/c_can/c_can_platform.c
index 109cb44..b144e71 100644
--- a/drivers/net/can/c_can/c_can_platform.c
+++ b/drivers/net/can/c_can/c_can_platform.c
@@ -75,10 +75,18 @@ static void c_can_plat_write_reg_aligned_to_32bit(const struct c_can_priv *priv,
 static void c_can_hw_raminit_wait_ti(const struct c_can_priv *priv, u32 mask,
 				  u32 val)
 {
+	int timeout = 0;
 	/* We look only at the bits of our instance. */
 	val &= mask;
-	while ((readl(priv->raminit_ctrlreg) & mask) != val)
+	while ((readl(priv->raminit_ctrlreg) & mask) != val) {
 		udelay(1);
+		timeout++;
+
+		if (timeout == 1000) {
+			dev_err(&priv->dev->dev, "%s: time out\n", __func__);
+			break;
+		}
+	}
 }
 
 static void c_can_hw_raminit_ti(const struct c_can_priv *priv, bool enable)
@@ -97,14 +105,14 @@ static void c_can_hw_raminit_ti(const struct c_can_priv *priv, bool enable)
 	ctrl |= CAN_RAMINIT_DONE_MASK(priv->instance);
 	writel(ctrl, priv->raminit_ctrlreg);
 	ctrl &= ~CAN_RAMINIT_DONE_MASK(priv->instance);
-	c_can_hw_raminit_wait_ti(priv, ctrl, mask);
+	c_can_hw_raminit_wait_ti(priv, mask, ctrl);
 
 	if (enable) {
 		/* Set start bit and wait for the done bit. */
 		ctrl |= CAN_RAMINIT_START_MASK(priv->instance);
 		writel(ctrl, priv->raminit_ctrlreg);
 		ctrl |= CAN_RAMINIT_DONE_MASK(priv->instance);
-		c_can_hw_raminit_wait_ti(priv, ctrl, mask);
+		c_can_hw_raminit_wait_ti(priv, mask, ctrl);
 	}
 	spin_unlock(&raminit_lock);
 }
-- 
1.8.3.2

[PATCH 02/13] net: can: c_can: Add syscon/regmap RAMINIT mechanism

[Roger Quadros]

Some TI SoCs like DRA7 have a RAMINIT register specification
different from the other AMxx SoCs and as expected by the
existing driver.

To add more insanity, this register is shared with other
IPs like DSS, PCIe and PWM.

Provides a more generic mechanism to specify the RAMINIT
register location and START/DONE bit position and use the
syscon/regmap framework to access the register.

Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 .../devicetree/bindings/net/can/c_can.txt          |   7 ++
 drivers/net/can/c_can/c_can.h                      |  11 ++-
 drivers/net/can/c_can/c_can_platform.c             | 106 +++++++++++++++------
 3 files changed, 95 insertions(+), 29 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/can/c_can.txt b/Documentation/devicetree/bindings/net/can/c_can.txt
index 8f1ae81..0856209 100644
--- a/Documentation/devicetree/bindings/net/can/c_can.txt
+++ b/Documentation/devicetree/bindings/net/can/c_can.txt
@@ -13,6 +13,13 @@ Optional properties:
 - ti,hwmods		: Must be "d_can<n>" or "c_can<n>", n being the
 			  instance number
 
+- raminit-syscon	: Handle to system control region that contains the
+			  RAMINIT register. If specified, the second memory resource
+			  in the reg property must index into the RAMINIT
+			  register within the syscon region
+- raminit-start-bit	: Bit posistion of START bit in the RAMINIT register
+- raminit-done-bit	: Bit position of DONE bit in the RAMINIT register
+
 Note: "ti,hwmods" field is used to fetch the base address and irq
 resources from TI, omap hwmod data base during device registration.
 Future plan is to migrate hwmod data base contents into device tree
diff --git a/drivers/net/can/c_can/c_can.h b/drivers/net/can/c_can/c_can.h
index 99ad1aa..bf68822 100644
--- a/drivers/net/can/c_can/c_can.h
+++ b/drivers/net/can/c_can/c_can.h
@@ -169,6 +169,14 @@ enum c_can_dev_id {
 	BOSCH_D_CAN,
 };
 
+/* Out of band RAMINIT register access via syscon regmap */
+struct c_can_raminit {
+	struct regmap *syscon;	/* for raminit ctrl. reg. access */
+	unsigned int reg;	/* register index within syscon */
+	u8 start_bit;	/* START bit position in raminit reg. */
+	u8 done_bit;	/* DONE bit position in raminit reg. */
+};
+
 /* c_can private data structure */
 struct c_can_priv {
 	struct can_priv can;	/* must be the first member */
@@ -186,8 +194,7 @@ struct c_can_priv {
 	const u16 *regs;
 	void *priv;		/* for board-specific data */
 	enum c_can_dev_id type;
-	u32 __iomem *raminit_ctrlreg;
-	int instance;
+	struct c_can_raminit raminit_sys;	/* RAMINIT via syscon regmap */
 	void (*raminit) (const struct c_can_priv *priv, bool enable);
 	u32 comm_rcv_high;
 	u32 rxmasked;
diff --git a/drivers/net/can/c_can/c_can_platform.c b/drivers/net/can/c_can/c_can_platform.c
index b144e71..e7ec3b6 100644
--- a/drivers/net/can/c_can/c_can_platform.c
+++ b/drivers/net/can/c_can/c_can_platform.c
@@ -32,6 +32,8 @@
 #include <linux/clk.h>
 #include <linux/of.h>
 #include <linux/of_device.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
 
 #include <linux/can/dev.h>
 
@@ -72,48 +74,59 @@ static void c_can_plat_write_reg_aligned_to_32bit(const struct c_can_priv *priv,
 	writew(val, priv->base + 2 * priv->regs[index]);
 }
 
-static void c_can_hw_raminit_wait_ti(const struct c_can_priv *priv, u32 mask,
-				  u32 val)
+static void c_can_hw_raminit_wait_syscon(const struct c_can_priv *priv,
+					 u32 mask, u32 val)
 {
 	int timeout = 0;
+	const struct c_can_raminit *raminit = &priv->raminit_sys;
+	u32 ctrl;
+
 	/* We look only at the bits of our instance. */
 	val &= mask;
-	while ((readl(priv->raminit_ctrlreg) & mask) != val) {
+	do {
 		udelay(1);
 		timeout++;
 
+		regmap_read(raminit->syscon, raminit->reg, &ctrl);
 		if (timeout == 1000) {
 			dev_err(&priv->dev->dev, "%s: time out\n", __func__);
 			break;
 		}
-	}
+	} while ((ctrl & mask) != val);
 }
 
-static void c_can_hw_raminit_ti(const struct c_can_priv *priv, bool enable)
+static void c_can_hw_raminit_syscon(const struct c_can_priv *priv, bool enable)
 {
-	u32 mask = CAN_RAMINIT_ALL_MASK(priv->instance);
+	u32 mask;
 	u32 ctrl;
+	const struct c_can_raminit *raminit = &priv->raminit_sys;
 
 	spin_lock(&raminit_lock);
 
-	ctrl = readl(priv->raminit_ctrlreg);
+	mask = 1 << raminit->start_bit | 1 << raminit->done_bit;
+	regmap_read(raminit->syscon, raminit->reg, &ctrl);
+
 	/* We clear the done and start bit first. The start bit is
 	 * looking at the 0 -> transition, but is not self clearing;
 	 * And we clear the init done bit as well.
+	 * NOTE: DONE must be written with 1 to clear it.
 	 */
-	ctrl &= ~CAN_RAMINIT_START_MASK(priv->instance);
-	ctrl |= CAN_RAMINIT_DONE_MASK(priv->instance);
-	writel(ctrl, priv->raminit_ctrlreg);
-	ctrl &= ~CAN_RAMINIT_DONE_MASK(priv->instance);
-	c_can_hw_raminit_wait_ti(priv, mask, ctrl);
+	ctrl &= ~(1 << raminit->start_bit);
+	ctrl |= 1 << raminit->done_bit;
+	regmap_write(raminit->syscon, raminit->reg, ctrl);
+
+	ctrl &= ~(1 << raminit->done_bit);
+	c_can_hw_raminit_wait_syscon(priv, mask, ctrl);
 
 	if (enable) {
 		/* Set start bit and wait for the done bit. */
-		ctrl |= CAN_RAMINIT_START_MASK(priv->instance);
-		writel(ctrl, priv->raminit_ctrlreg);
-		ctrl |= CAN_RAMINIT_DONE_MASK(priv->instance);
-		c_can_hw_raminit_wait_ti(priv, mask, ctrl);
+		ctrl |= 1 << raminit->start_bit;
+		regmap_write(raminit->syscon, raminit->reg, ctrl);
+
+		ctrl |= 1 << raminit->done_bit;
+		c_can_hw_raminit_wait_syscon(priv, mask, ctrl);
 	}
+
 	spin_unlock(&raminit_lock);
 }
 
@@ -202,6 +215,8 @@ static int c_can_plat_probe(struct platform_device *pdev)
 	struct resource *mem, *res;
 	int irq;
 	struct clk *clk;
+	struct device_node *np = pdev->dev.of_node;
+	u32 val;
 
 	if (pdev->dev.of_node) {
 		match = of_match_device(c_can_of_table, &pdev->dev);
@@ -271,11 +286,6 @@ static int c_can_plat_probe(struct platform_device *pdev)
 		priv->read_reg32 = d_can_plat_read_reg32;
 		priv->write_reg32 = d_can_plat_write_reg32;
 
-		if (pdev->dev.of_node)
-			priv->instance = of_alias_get_id(pdev->dev.of_node, "d_can");
-		else
-			priv->instance = pdev->id;
-
 		res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 		/* Not all D_CAN modules have a separate register for the D_CAN
 		 * RAM initialization. Use default RAM init bit in D_CAN module
@@ -286,12 +296,54 @@ static int c_can_plat_probe(struct platform_device *pdev)
 			break;
 		}
 
-		priv->raminit_ctrlreg = devm_ioremap(&pdev->dev, res->start,
-						     resource_size(res));
-		if (!priv->raminit_ctrlreg || priv->instance < 0)
-			dev_info(&pdev->dev, "control memory is not used for raminit\n");
-		else
-			priv->raminit = c_can_hw_raminit_ti;
+		/* If separate RAMINIT register is specified access
+		 * it using syscon regmap. Mostly for TI platforms.
+		 */
+		ret = -EINVAL;
+		if (!np) {
+			dev_err(&pdev->dev,
+				"separate RAMINIT reg. not supported on non DT\n");
+			goto exit_free_device;
+		}
+
+		priv->raminit_sys.syscon = syscon_regmap_lookup_by_phandle(np,
+									   "raminit-syscon");
+		if (IS_ERR(priv->raminit_sys.syscon)) {
+			dev_err(&pdev->dev,
+				"couldn't get syscon regmap for RAMINIT reg.\n");
+			goto exit_free_device;
+		}
+
+		priv->raminit_sys.reg = res->start;
+		if (of_property_read_u32(np, "raminit-start-bit",
+					 &val)) {
+			dev_err(&pdev->dev,
+				"missing raminit-start-bit property\n");
+			goto exit_free_device;
+		}
+
+		if (val > 31) {
+			dev_err(&pdev->dev,
+				"invalid raminit-start-bit property\n");
+			goto exit_free_device;
+		}
+
+		priv->raminit_sys.start_bit = val;
+		if (of_property_read_u32(np, "raminit-done-bit",
+					 &val)) {
+			dev_err(&pdev->dev,
+				"missing raminit-done-bit property\n");
+			goto exit_free_device;
+		}
+
+		if (val > 31) {
+			dev_err(&pdev->dev,
+				"invalid raminit-done-bit property\n");
+			goto exit_free_device;
+		}
+
+		priv->raminit_sys.done_bit = val;
+		priv->raminit = c_can_hw_raminit_syscon;
 		break;
 	default:
 		ret = -EINVAL;
-- 
1.8.3.2

[PATCH 02/13] net: can: c_can: Add syscon/regmap RAMINIT mechanism

[Roger Quadros]

Some TI SoCs like DRA7 have a RAMINIT register specification
different from the other AMxx SoCs and as expected by the
existing driver.

To add more insanity, this register is shared with other
IPs like DSS, PCIe and PWM.

Provides a more generic mechanism to specify the RAMINIT
register location and START/DONE bit position and use the
syscon/regmap framework to access the register.

Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 .../devicetree/bindings/net/can/c_can.txt          |   7 ++
 drivers/net/can/c_can/c_can.h                      |  11 ++-
 drivers/net/can/c_can/c_can_platform.c             | 106 +++++++++++++++------
 3 files changed, 95 insertions(+), 29 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/can/c_can.txt b/Documentation/devicetree/bindings/net/can/c_can.txt
index 8f1ae81..0856209 100644
--- a/Documentation/devicetree/bindings/net/can/c_can.txt
+++ b/Documentation/devicetree/bindings/net/can/c_can.txt
@@ -13,6 +13,13 @@ Optional properties:
 - ti,hwmods		: Must be "d_can<n>" or "c_can<n>", n being the
 			  instance number
 
+- raminit-syscon	: Handle to system control region that contains the
+			  RAMINIT register. If specified, the second memory resource
+			  in the reg property must index into the RAMINIT
+			  register within the syscon region
+- raminit-start-bit	: Bit posistion of START bit in the RAMINIT register
+- raminit-done-bit	: Bit position of DONE bit in the RAMINIT register
+
 Note: "ti,hwmods" field is used to fetch the base address and irq
 resources from TI, omap hwmod data base during device registration.
 Future plan is to migrate hwmod data base contents into device tree
diff --git a/drivers/net/can/c_can/c_can.h b/drivers/net/can/c_can/c_can.h
index 99ad1aa..bf68822 100644
--- a/drivers/net/can/c_can/c_can.h
+++ b/drivers/net/can/c_can/c_can.h
@@ -169,6 +169,14 @@ enum c_can_dev_id {
 	BOSCH_D_CAN,
 };
 
+/* Out of band RAMINIT register access via syscon regmap */
+struct c_can_raminit {
+	struct regmap *syscon;	/* for raminit ctrl. reg. access */
+	unsigned int reg;	/* register index within syscon */
+	u8 start_bit;	/* START bit position in raminit reg. */
+	u8 done_bit;	/* DONE bit position in raminit reg. */
+};
+
 /* c_can private data structure */
 struct c_can_priv {
 	struct can_priv can;	/* must be the first member */
@@ -186,8 +194,7 @@ struct c_can_priv {
 	const u16 *regs;
 	void *priv;		/* for board-specific data */
 	enum c_can_dev_id type;
-	u32 __iomem *raminit_ctrlreg;
-	int instance;
+	struct c_can_raminit raminit_sys;	/* RAMINIT via syscon regmap */
 	void (*raminit) (const struct c_can_priv *priv, bool enable);
 	u32 comm_rcv_high;
 	u32 rxmasked;
diff --git a/drivers/net/can/c_can/c_can_platform.c b/drivers/net/can/c_can/c_can_platform.c
index b144e71..e7ec3b6 100644
--- a/drivers/net/can/c_can/c_can_platform.c
+++ b/drivers/net/can/c_can/c_can_platform.c
@@ -32,6 +32,8 @@
 #include <linux/clk.h>
 #include <linux/of.h>
 #include <linux/of_device.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
 
 #include <linux/can/dev.h>
 
@@ -72,48 +74,59 @@ static void c_can_plat_write_reg_aligned_to_32bit(const struct c_can_priv *priv,
 	writew(val, priv->base + 2 * priv->regs[index]);
 }
 
-static void c_can_hw_raminit_wait_ti(const struct c_can_priv *priv, u32 mask,
-				  u32 val)
+static void c_can_hw_raminit_wait_syscon(const struct c_can_priv *priv,
+					 u32 mask, u32 val)
 {
 	int timeout = 0;
+	const struct c_can_raminit *raminit = &priv->raminit_sys;
+	u32 ctrl;
+
 	/* We look only at the bits of our instance. */
 	val &= mask;
-	while ((readl(priv->raminit_ctrlreg) & mask) != val) {
+	do {
 		udelay(1);
 		timeout++;
 
+		regmap_read(raminit->syscon, raminit->reg, &ctrl);
 		if (timeout == 1000) {
 			dev_err(&priv->dev->dev, "%s: time out\n", __func__);
 			break;
 		}
-	}
+	} while ((ctrl & mask) != val);
 }
 
-static void c_can_hw_raminit_ti(const struct c_can_priv *priv, bool enable)
+static void c_can_hw_raminit_syscon(const struct c_can_priv *priv, bool enable)
 {
-	u32 mask = CAN_RAMINIT_ALL_MASK(priv->instance);
+	u32 mask;
 	u32 ctrl;
+	const struct c_can_raminit *raminit = &priv->raminit_sys;
 
 	spin_lock(&raminit_lock);
 
-	ctrl = readl(priv->raminit_ctrlreg);
+	mask = 1 << raminit->start_bit | 1 << raminit->done_bit;
+	regmap_read(raminit->syscon, raminit->reg, &ctrl);
+
 	/* We clear the done and start bit first. The start bit is
 	 * looking at the 0 -> transition, but is not self clearing;
 	 * And we clear the init done bit as well.
+	 * NOTE: DONE must be written with 1 to clear it.
 	 */
-	ctrl &= ~CAN_RAMINIT_START_MASK(priv->instance);
-	ctrl |= CAN_RAMINIT_DONE_MASK(priv->instance);
-	writel(ctrl, priv->raminit_ctrlreg);
-	ctrl &= ~CAN_RAMINIT_DONE_MASK(priv->instance);
-	c_can_hw_raminit_wait_ti(priv, mask, ctrl);
+	ctrl &= ~(1 << raminit->start_bit);
+	ctrl |= 1 << raminit->done_bit;
+	regmap_write(raminit->syscon, raminit->reg, ctrl);
+
+	ctrl &= ~(1 << raminit->done_bit);
+	c_can_hw_raminit_wait_syscon(priv, mask, ctrl);
 
 	if (enable) {
 		/* Set start bit and wait for the done bit. */
-		ctrl |= CAN_RAMINIT_START_MASK(priv->instance);
-		writel(ctrl, priv->raminit_ctrlreg);
-		ctrl |= CAN_RAMINIT_DONE_MASK(priv->instance);
-		c_can_hw_raminit_wait_ti(priv, mask, ctrl);
+		ctrl |= 1 << raminit->start_bit;
+		regmap_write(raminit->syscon, raminit->reg, ctrl);
+
+		ctrl |= 1 << raminit->done_bit;
+		c_can_hw_raminit_wait_syscon(priv, mask, ctrl);
 	}
+
 	spin_unlock(&raminit_lock);
 }
 
@@ -202,6 +215,8 @@ static int c_can_plat_probe(struct platform_device *pdev)
 	struct resource *mem, *res;
 	int irq;
 	struct clk *clk;
+	struct device_node *np = pdev->dev.of_node;
+	u32 val;
 
 	if (pdev->dev.of_node) {
 		match = of_match_device(c_can_of_table, &pdev->dev);
@@ -271,11 +286,6 @@ static int c_can_plat_probe(struct platform_device *pdev)
 		priv->read_reg32 = d_can_plat_read_reg32;
 		priv->write_reg32 = d_can_plat_write_reg32;
 
-		if (pdev->dev.of_node)
-			priv->instance = of_alias_get_id(pdev->dev.of_node, "d_can");
-		else
-			priv->instance = pdev->id;
-
 		res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 		/* Not all D_CAN modules have a separate register for the D_CAN
 		 * RAM initialization. Use default RAM init bit in D_CAN module
@@ -286,12 +296,54 @@ static int c_can_plat_probe(struct platform_device *pdev)
 			break;
 		}
 
-		priv->raminit_ctrlreg = devm_ioremap(&pdev->dev, res->start,
-						     resource_size(res));
-		if (!priv->raminit_ctrlreg || priv->instance < 0)
-			dev_info(&pdev->dev, "control memory is not used for raminit\n");
-		else
-			priv->raminit = c_can_hw_raminit_ti;
+		/* If separate RAMINIT register is specified access
+		 * it using syscon regmap. Mostly for TI platforms.
+		 */
+		ret = -EINVAL;
+		if (!np) {
+			dev_err(&pdev->dev,
+				"separate RAMINIT reg. not supported on non DT\n");
+			goto exit_free_device;
+		}
+
+		priv->raminit_sys.syscon = syscon_regmap_lookup_by_phandle(np,
+									   "raminit-syscon");
+		if (IS_ERR(priv->raminit_sys.syscon)) {
+			dev_err(&pdev->dev,
+				"couldn't get syscon regmap for RAMINIT reg.\n");
+			goto exit_free_device;
+		}
+
+		priv->raminit_sys.reg = res->start;
+		if (of_property_read_u32(np, "raminit-start-bit",
+					 &val)) {
+			dev_err(&pdev->dev,
+				"missing raminit-start-bit property\n");
+			goto exit_free_device;
+		}
+
+		if (val > 31) {
+			dev_err(&pdev->dev,
+				"invalid raminit-start-bit property\n");
+			goto exit_free_device;
+		}
+
+		priv->raminit_sys.start_bit = val;
+		if (of_property_read_u32(np, "raminit-done-bit",
+					 &val)) {
+			dev_err(&pdev->dev,
+				"missing raminit-done-bit property\n");
+			goto exit_free_device;
+		}
+
+		if (val > 31) {
+			dev_err(&pdev->dev,
+				"invalid raminit-done-bit property\n");
+			goto exit_free_device;
+		}
+
+		priv->raminit_sys.done_bit = val;
+		priv->raminit = c_can_hw_raminit_syscon;
 		break;
 	default:
 		ret = -EINVAL;
-- 
1.8.3.2

[PATCH 03/13] net: can: c_can: Add support for START pulse in RAMINIT sequence

[Roger Quadros]

Some SoCs e.g. (TI DRA7xx) need a START pulse to start the
RAMINIT sequence i.e. START bit must be set and cleared before
checking for the DONE bit status. Add a new DT property "raminit-pulse"
to specify if this mechanism must be used for RAMINIT.

Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 Documentation/devicetree/bindings/net/can/c_can.txt | 3 +++
 drivers/net/can/c_can/c_can.h                       | 1 +
 drivers/net/can/c_can/c_can_platform.c              | 8 ++++++++
 3 files changed, 12 insertions(+)

diff --git a/Documentation/devicetree/bindings/net/can/c_can.txt b/Documentation/devicetree/bindings/net/can/c_can.txt
index 0856209..2f0a6bb 100644
--- a/Documentation/devicetree/bindings/net/can/c_can.txt
+++ b/Documentation/devicetree/bindings/net/can/c_can.txt
@@ -19,6 +19,9 @@ Optional properties:
 			  register within the syscon region
 - raminit-start-bit	: Bit posistion of START bit in the RAMINIT register
 - raminit-done-bit	: Bit position of DONE bit in the RAMINIT register
+- raminit-pulse		: Property must exist if START pulse is needed for RAMINIT
+			  sequence i.e. START bit will be set and cleared before
+			  checking for DONE bit.
 
 Note: "ti,hwmods" field is used to fetch the base address and irq
 resources from TI, omap hwmod data base during device registration.
diff --git a/drivers/net/can/c_can/c_can.h b/drivers/net/can/c_can/c_can.h
index bf68822..85b5ad0 100644
--- a/drivers/net/can/c_can/c_can.h
+++ b/drivers/net/can/c_can/c_can.h
@@ -175,6 +175,7 @@ struct c_can_raminit {
 	unsigned int reg;	/* register index within syscon */
 	u8 start_bit;	/* START bit position in raminit reg. */
 	u8 done_bit;	/* DONE bit position in raminit reg. */
+	bool needs_pulse;	/* If set, sets and clears START bit (pulse) */
 };
 
 /* c_can private data structure */
diff --git a/drivers/net/can/c_can/c_can_platform.c b/drivers/net/can/c_can/c_can_platform.c
index e7ec3b6..bc09695 100644
--- a/drivers/net/can/c_can/c_can_platform.c
+++ b/drivers/net/can/c_can/c_can_platform.c
@@ -123,6 +123,12 @@ static void c_can_hw_raminit_syscon(const struct c_can_priv *priv, bool enable)
 		ctrl |= 1 << raminit->start_bit;
 		regmap_write(raminit->syscon, raminit->reg, ctrl);
 
+		/* clear START bit if start pulse is needed */
+		if (raminit->needs_pulse) {
+			ctrl &= ~(1 << raminit->start_bit);
+			regmap_write(raminit->syscon, raminit->reg, ctrl);
+		}
+
 		ctrl |= 1 << raminit->done_bit;
 		c_can_hw_raminit_wait_syscon(priv, mask, ctrl);
 	}
@@ -343,6 +349,8 @@ static int c_can_plat_probe(struct platform_device *pdev)
 		}
 
 		priv->raminit_sys.done_bit = val;
+		priv->raminit_sys.needs_pulse = of_property_read_bool(np,
+								      "raminit-pulse");
 		priv->raminit = c_can_hw_raminit_syscon;
 		break;
 	default:
-- 
1.8.3.2

[PATCH 03/13] net: can: c_can: Add support for START pulse in RAMINIT sequence

[Roger Quadros]

Some SoCs e.g. (TI DRA7xx) need a START pulse to start the
RAMINIT sequence i.e. START bit must be set and cleared before
checking for the DONE bit status. Add a new DT property "raminit-pulse"
to specify if this mechanism must be used for RAMINIT.

Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 Documentation/devicetree/bindings/net/can/c_can.txt | 3 +++
 drivers/net/can/c_can/c_can.h                       | 1 +
 drivers/net/can/c_can/c_can_platform.c              | 8 ++++++++
 3 files changed, 12 insertions(+)

diff --git a/Documentation/devicetree/bindings/net/can/c_can.txt b/Documentation/devicetree/bindings/net/can/c_can.txt
index 0856209..2f0a6bb 100644
--- a/Documentation/devicetree/bindings/net/can/c_can.txt
+++ b/Documentation/devicetree/bindings/net/can/c_can.txt
@@ -19,6 +19,9 @@ Optional properties:
 			  register within the syscon region
 - raminit-start-bit	: Bit posistion of START bit in the RAMINIT register
 - raminit-done-bit	: Bit position of DONE bit in the RAMINIT register
+- raminit-pulse		: Property must exist if START pulse is needed for RAMINIT
+			  sequence i.e. START bit will be set and cleared before
+			  checking for DONE bit.
 
 Note: "ti,hwmods" field is used to fetch the base address and irq
 resources from TI, omap hwmod data base during device registration.
diff --git a/drivers/net/can/c_can/c_can.h b/drivers/net/can/c_can/c_can.h
index bf68822..85b5ad0 100644
--- a/drivers/net/can/c_can/c_can.h
+++ b/drivers/net/can/c_can/c_can.h
@@ -175,6 +175,7 @@ struct c_can_raminit {
 	unsigned int reg;	/* register index within syscon */
 	u8 start_bit;	/* START bit position in raminit reg. */
 	u8 done_bit;	/* DONE bit position in raminit reg. */
+	bool needs_pulse;	/* If set, sets and clears START bit (pulse) */
 };
 
 /* c_can private data structure */
diff --git a/drivers/net/can/c_can/c_can_platform.c b/drivers/net/can/c_can/c_can_platform.c
index e7ec3b6..bc09695 100644
--- a/drivers/net/can/c_can/c_can_platform.c
+++ b/drivers/net/can/c_can/c_can_platform.c
@@ -123,6 +123,12 @@ static void c_can_hw_raminit_syscon(const struct c_can_priv *priv, bool enable)
 		ctrl |= 1 << raminit->start_bit;
 		regmap_write(raminit->syscon, raminit->reg, ctrl);
 
+		/* clear START bit if start pulse is needed */
+		if (raminit->needs_pulse) {
+			ctrl &= ~(1 << raminit->start_bit);
+			regmap_write(raminit->syscon, raminit->reg, ctrl);
+		}
+
 		ctrl |= 1 << raminit->done_bit;
 		c_can_hw_raminit_wait_syscon(priv, mask, ctrl);
 	}
@@ -343,6 +349,8 @@ static int c_can_plat_probe(struct platform_device *pdev)
 		}
 
 		priv->raminit_sys.done_bit = val;
+		priv->raminit_sys.needs_pulse = of_property_read_bool(np,
+								      "raminit-pulse");
 		priv->raminit = c_can_hw_raminit_syscon;
 		break;
 	default:
-- 
1.8.3.2

[PATCH 04/13] ARM: dts: dra7: Add syscon regmap for CORE CONTROL area

[Roger Quadros]

Display and DCAN drivers use syscon regmap to access some registers
in the CORE control area. Add the syscon regmap node for this
area.

Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: Nishanth Menon <nm@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 arch/arm/boot/dts/dra7.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index d678152..370009e 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -200,6 +200,11 @@
 			ti,hwmods = "counter_32k";
 		};
 
+		dra7_ctrl_core: ctrl_core@4a002000 {
+			compatible = "syscon";
+			reg = <0x4a002000 0x6d0>;
+		};
+
 		dra7_ctrl_general: tisyscon@4a002e00 {
 			compatible = "syscon";
 			reg = <0x4a002e00 0x7c>;
-- 
1.8.3.2

[PATCH 04/13] ARM: dts: dra7: Add syscon regmap for CORE CONTROL area

[Roger Quadros]

Display and DCAN drivers use syscon regmap to access some registers
in the CORE control area. Add the syscon regmap node for this
area.

Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: Nishanth Menon <nm@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 arch/arm/boot/dts/dra7.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index d678152..370009e 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -200,6 +200,11 @@
 			ti,hwmods = "counter_32k";
 		};
 
+		dra7_ctrl_core: ctrl_core@4a002000 {
+			compatible = "syscon";
+			reg = <0x4a002000 0x6d0>;
+		};
+
 		dra7_ctrl_general: tisyscon@4a002e00 {
 			compatible = "syscon";
 			reg = <0x4a002e00 0x7c>;
-- 
1.8.3.2

[PATCH 05/13] ARM: dts: DRA7: Add DCAN nodes

[Roger Quadros]

The SoC supports 2 DCAN nodes. Add them.

Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 arch/arm/boot/dts/dra7.dtsi | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 370009e..4ce1a4f 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -34,6 +34,8 @@
 		serial3 = &uart4;
 		serial4 = &uart5;
 		serial5 = &uart6;
+		d_can0 = &dcan1;
+		d_can1 = &dcan2;
 	};
 
 	timer {
@@ -1267,6 +1269,34 @@
 			ti,irqs-skip = <10 133 139 140>;
 			ti,irqs-safe-map = <0>;
 		};
+
+		dcan1: d_can@481cc000 {
+			compatible = "bosch,d_can";
+			ti,hwmods = "dcan1";
+			reg = <0x4ae3c000 0x2000>,
+			      <0x558 0x4>; /* index to RAMINIT reg within syscon */
+			raminit-syscon = <&dra7_ctrl_core>;
+			raminit-start-bit = <3>;
+			raminit-done-bit = <1>;
+			raminit-pulse;
+			interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&dcan1_sys_clk_mux>;
+			status = "disabled";
+		};
+
+		dcan2: d_can@481d0000 {
+			compatible = "bosch,d_can";
+			ti,hwmods = "dcan2";
+			reg = <0x48480000 0x2000>,
+			      <0x558 0x4>; /* index to RAMINIT reg within syscon */
+			raminit-syscon = <&dra7_ctrl_core>;
+			raminit-start-bit = <5>;
+			raminit-done-bit = <2>;
+			raminit-pulse;
+			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sys_clkin1>;
+			status = "disabled";
+		};
 	};
 };
 
-- 
1.8.3.2

[PATCH 05/13] ARM: dts: DRA7: Add DCAN nodes

[Roger Quadros]

The SoC supports 2 DCAN nodes. Add them.

Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 arch/arm/boot/dts/dra7.dtsi | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 370009e..4ce1a4f 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -34,6 +34,8 @@
 		serial3 = &uart4;
 		serial4 = &uart5;
 		serial5 = &uart6;
+		d_can0 = &dcan1;
+		d_can1 = &dcan2;
 	};
 
 	timer {
@@ -1267,6 +1269,34 @@
 			ti,irqs-skip = <10 133 139 140>;
 			ti,irqs-safe-map = <0>;
 		};
+
+		dcan1: d_can@481cc000 {
+			compatible = "bosch,d_can";
+			ti,hwmods = "dcan1";
+			reg = <0x4ae3c000 0x2000>,
+			      <0x558 0x4>; /* index to RAMINIT reg within syscon */
+			raminit-syscon = <&dra7_ctrl_core>;
+			raminit-start-bit = <3>;
+			raminit-done-bit = <1>;
+			raminit-pulse;
+			interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&dcan1_sys_clk_mux>;
+			status = "disabled";
+		};
+
+		dcan2: d_can@481d0000 {
+			compatible = "bosch,d_can";
+			ti,hwmods = "dcan2";
+			reg = <0x48480000 0x2000>,
+			      <0x558 0x4>; /* index to RAMINIT reg within syscon */
+			raminit-syscon = <&dra7_ctrl_core>;
+			raminit-start-bit = <5>;
+			raminit-done-bit = <2>;
+			raminit-pulse;
+			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sys_clkin1>;
+			status = "disabled";
+		};
 	};
 };
 
-- 
1.8.3.2

[PATCH 06/13] ARM: dts: dra7-evm: Add CAN support

[Roger Quadros]

The board has 2 CAN ports but only the first one can be used.
Enable the first CAN port.

The second one cannot be used without hardware modification
so we don't enable the second port.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Reviewed-by: Felipe Balbi <balbi@ti.com>
---
 arch/arm/boot/dts/dra7-evm.dts | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index e03fbf3..d6b9b27 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -171,6 +171,20 @@
 			0xd0	(PIN_OUTPUT | MUX_MODE0)	/* gpmc_be0n_cle */
 		>;
 	};
+
+	dcan1_pins_default: dcan1_pins_default {
+		pinctrl-single,pins = <
+			0x3d4	(PIN_INPUT | MUX_MODE0)		/* dcan1_tx */
+			0x3d8	(PIN_INPUT | MUX_MODE0)		/* dcan1_rx */
+		>;
+	};
+
+	dcan1_pins_sleep: dcan1_pins_sleep {
+		pinctrl-single,pins = <
+			0x3d4	(PIN_INPUT | MUX_MODE15)	/* dcan1_tx */
+			0x3d8	(PIN_INPUT | MUX_MODE15)	/* dcan1_rx */
+		>;
+	};
 };
 
 &i2c1 {
@@ -529,3 +543,10 @@
 	ti,no-reset-on-init;
 	ti,no-idle-on-init;
 };
+
+&dcan1 {
+	status = "ok";
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&dcan1_pins_default>;
+	pinctrl-1 = <&dcan1_pins_sleep>;
+};
-- 
1.8.3.2

[PATCH 06/13] ARM: dts: dra7-evm: Add CAN support

[Roger Quadros]

The board has 2 CAN ports but only the first one can be used.
Enable the first CAN port.

The second one cannot be used without hardware modification
so we don't enable the second port.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Reviewed-by: Felipe Balbi <balbi@ti.com>
---
 arch/arm/boot/dts/dra7-evm.dts | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index e03fbf3..d6b9b27 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -171,6 +171,20 @@
 			0xd0	(PIN_OUTPUT | MUX_MODE0)	/* gpmc_be0n_cle */
 		>;
 	};
+
+	dcan1_pins_default: dcan1_pins_default {
+		pinctrl-single,pins = <
+			0x3d4	(PIN_INPUT | MUX_MODE0)		/* dcan1_tx */
+			0x3d8	(PIN_INPUT | MUX_MODE0)		/* dcan1_rx */
+		>;
+	};
+
+	dcan1_pins_sleep: dcan1_pins_sleep {
+		pinctrl-single,pins = <
+			0x3d4	(PIN_INPUT | MUX_MODE15)	/* dcan1_tx */
+			0x3d8	(PIN_INPUT | MUX_MODE15)	/* dcan1_rx */
+		>;
+	};
 };
 
 &i2c1 {
@@ -529,3 +543,10 @@
 	ti,no-reset-on-init;
 	ti,no-idle-on-init;
 };
+
+&dcan1 {
+	status = "ok";
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&dcan1_pins_default>;
+	pinctrl-1 = <&dcan1_pins_sleep>;
+};
-- 
1.8.3.2

[PATCH 07/13] ARM: dts: dra72-evm: Add CAN support

[Roger Quadros]

The board has 2 CAN ports but only the first one can be used.
Enable the first CAN port.

The second one cannot be used without hardware modification
so we don't enable the second port.

Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 arch/arm/boot/dts/dra72-evm.dts | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts
index 5147023..e5b7172 100644
--- a/arch/arm/boot/dts/dra72-evm.dts
+++ b/arch/arm/boot/dts/dra72-evm.dts
@@ -19,6 +19,29 @@
 	};
 };
 
+&dra7_pmx_core {
+	dcan1_pins_default: dcan1_pins_default {
+		pinctrl-single,pins = <
+			0x3d4	(PIN_INPUT | MUX_MODE0)		/* dcan1_tx */
+			0x418	(PIN_INPUT | MUX_MODE1)		/* wakeup0.dcan1_rx */
+		>;
+	};
+
+	dcan1_pins_sleep: dcan1_pins_sleep {
+		pinctrl-single,pins = <
+			0x3d4	(PIN_INPUT | MUX_MODE15)	/* dcan1_tx.off */
+			0x418	(PIN_INPUT | MUX_MODE15)	/* wakeup0.off */
+		>;
+	};
+};
+
 &uart1 {
 	status = "okay";
 };
+
+&dcan1 {
+	status = "ok";
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&dcan1_pins_default>;
+	pinctrl-1 = <&dcan1_pins_sleep>;
+};
-- 
1.8.3.2

[PATCH 07/13] ARM: dts: dra72-evm: Add CAN support

[Roger Quadros]

The board has 2 CAN ports but only the first one can be used.
Enable the first CAN port.

The second one cannot be used without hardware modification
so we don't enable the second port.

Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 arch/arm/boot/dts/dra72-evm.dts | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts
index 5147023..e5b7172 100644
--- a/arch/arm/boot/dts/dra72-evm.dts
+++ b/arch/arm/boot/dts/dra72-evm.dts
@@ -19,6 +19,29 @@
 	};
 };
 
+&dra7_pmx_core {
+	dcan1_pins_default: dcan1_pins_default {
+		pinctrl-single,pins = <
+			0x3d4	(PIN_INPUT | MUX_MODE0)		/* dcan1_tx */
+			0x418	(PIN_INPUT | MUX_MODE1)		/* wakeup0.dcan1_rx */
+		>;
+	};
+
+	dcan1_pins_sleep: dcan1_pins_sleep {
+		pinctrl-single,pins = <
+			0x3d4	(PIN_INPUT | MUX_MODE15)	/* dcan1_tx.off */
+			0x418	(PIN_INPUT | MUX_MODE15)	/* wakeup0.off */
+		>;
+	};
+};
+
 &uart1 {
 	status = "okay";
 };
+
+&dcan1 {
+	status = "ok";
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&dcan1_pins_default>;
+	pinctrl-1 = <&dcan1_pins_sleep>;
+};
-- 
1.8.3.2

[PATCH 08/13] arm: dts: am4372: Add dcan nodes

[Roger Quadros]

From: Afzal Mohammed <afzal@ti.com>

Add dcan nodes.

Signed-off-by: Afzal Mohammed <afzal@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: George Cherian <george.cherian@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
---
 arch/arm/boot/dts/am4372.dtsi | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 8689949..3514d0a 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -885,6 +885,28 @@
 				clock-names = "fck";
 			};
 		};
+
+		dcan0: can@481cc000 {
+			compatible = "bosch,d_can";
+			ti,hwmods = "d_can0";
+			clocks = <&dcan0_fck>;
+			clock-names = "fck";
+			reg = <0x481cc000 0x2000
+				0x44e10644 0x4>;
+			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		dcan1: can@481d0000 {
+			compatible = "bosch,d_can";
+			ti,hwmods = "d_can1";
+			clocks = <&dcan1_fck>;
+			clock-names = "fck";
+			reg = <0x481d0000 0x2000
+				0x44e10644 0x4>;
+			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
 	};
 };
 
-- 
1.8.3.2

[PATCH 08/13] arm: dts: am4372: Add dcan nodes

[Roger Quadros]

From: Afzal Mohammed <afzal@ti.com>

Add dcan nodes.

Signed-off-by: Afzal Mohammed <afzal@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: George Cherian <george.cherian@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
---
 arch/arm/boot/dts/am4372.dtsi | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 8689949..3514d0a 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -885,6 +885,28 @@
 				clock-names = "fck";
 			};
 		};
+
+		dcan0: can@481cc000 {
+			compatible = "bosch,d_can";
+			ti,hwmods = "d_can0";
+			clocks = <&dcan0_fck>;
+			clock-names = "fck";
+			reg = <0x481cc000 0x2000
+				0x44e10644 0x4>;
+			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		dcan1: can@481d0000 {
+			compatible = "bosch,d_can";
+			ti,hwmods = "d_can1";
+			clocks = <&dcan1_fck>;
+			clock-names = "fck";
+			reg = <0x481d0000 0x2000
+				0x44e10644 0x4>;
+			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
 	};
 };
 
-- 
1.8.3.2

[PATCH 09/13] ARM: dts: AM43xx: Add aliases to d_can nodes

[Roger Quadros]

The d_can driver expects appropriately named aliases for
the d_can nodes for the RAMINIT control register access.

Provide those, otherwise RAMINIT register won't be configured.
Get's rid of the following messages during boot.

[   16.419354] c_can_platform 481cc000.can: control memory is not used for raminit
[   16.449142] c_can_platform 481d0000.can: control memory is not used for raminit

Signed-off-by: Roger Quadros <rogerq@ti.com>
Reviewed-by: Felipe Balbi <balbi@ti.com>
---
 arch/arm/boot/dts/am4372.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 3514d0a..a705e50 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -25,6 +25,8 @@
 		serial0 = &uart0;
 		ethernet0 = &cpsw_emac0;
 		ethernet1 = &cpsw_emac1;
+		d_can0 = &dcan0;
+		d_can1 = &dcan1;
 	};
 
 	cpus {
-- 
1.8.3.2

[PATCH 09/13] ARM: dts: AM43xx: Add aliases to d_can nodes

[Roger Quadros]

The d_can driver expects appropriately named aliases for
the d_can nodes for the RAMINIT control register access.

Provide those, otherwise RAMINIT register won't be configured.
Get's rid of the following messages during boot.

[   16.419354] c_can_platform 481cc000.can: control memory is not used for raminit
[   16.449142] c_can_platform 481d0000.can: control memory is not used for raminit

Signed-off-by: Roger Quadros <rogerq@ti.com>
Reviewed-by: Felipe Balbi <balbi@ti.com>
---
 arch/arm/boot/dts/am4372.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 3514d0a..a705e50 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -25,6 +25,8 @@
 		serial0 = &uart0;
 		ethernet0 = &cpsw_emac0;
 		ethernet1 = &cpsw_emac1;
+		d_can0 = &dcan0;
+		d_can1 = &dcan1;
 	};
 
 	cpus {
-- 
1.8.3.2

[PATCH 10/13] arm: dts: am437x-gp: Add dcan support

[Roger Quadros]

From: Mugunthan V N <mugunthanvnm@ti.com>

Add DCAN support for AM437x GP EVM with both DCAN instances.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: George Cherian <george.cherian@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
---
 arch/arm/boot/dts/am437x-gp-evm.dts | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts
index e7ac47f..6d03baa 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -254,6 +254,20 @@
 			0x238 (PIN_OUTPUT_PULLUP | MUX_MODE7)
 		>;
 	};
+
+	dcan0_default: dcan0_default_pins {
+		pinctrl-single,pins = <
+			0x178 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* uart1_ctsn.d_can0_tx */
+			0x17c (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_rtsn.d_can0_rx */
+		>;
+	};
+
+	dcan1_default: dcan1_default_pins {
+		pinctrl-single,pins = <
+			0x180 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* uart1_rxd.d_can1_tx */
+			0x184 (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_txd.d_can1_rx */
+		>;
+	};
 };
 
 &i2c0 {
@@ -511,3 +525,15 @@
 		};
 	};
 };
+
+&dcan0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&dcan0_default>;
+	status = "okay";
+};
+
+&dcan1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&dcan1_default>;
+	status = "okay";
+};
-- 
1.8.3.2

[PATCH 10/13] arm: dts: am437x-gp: Add dcan support

[Roger Quadros]

From: Mugunthan V N <mugunthanvnm@ti.com>

Add DCAN support for AM437x GP EVM with both DCAN instances.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: George Cherian <george.cherian@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
---
 arch/arm/boot/dts/am437x-gp-evm.dts | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts
index e7ac47f..6d03baa 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -254,6 +254,20 @@
 			0x238 (PIN_OUTPUT_PULLUP | MUX_MODE7)
 		>;
 	};
+
+	dcan0_default: dcan0_default_pins {
+		pinctrl-single,pins = <
+			0x178 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* uart1_ctsn.d_can0_tx */
+			0x17c (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_rtsn.d_can0_rx */
+		>;
+	};
+
+	dcan1_default: dcan1_default_pins {
+		pinctrl-single,pins = <
+			0x180 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* uart1_rxd.d_can1_tx */
+			0x184 (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_txd.d_can1_rx */
+		>;
+	};
 };
 
 &i2c0 {
@@ -511,3 +525,15 @@
 		};
 	};
 };
+
+&dcan0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&dcan0_default>;
+	status = "okay";
+};
+
+&dcan1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&dcan1_default>;
+	status = "okay";
+};
-- 
1.8.3.2

[PATCH 11/13] ARM: dts: am437x-gp-evm: Add pinctrl sleep states for dcan pins

[Roger Quadros]

From: Dave Gerlach <d-gerlach@ti.com>

Define pinctrl sleep states for both dcan0 and dcan1 to place pull downs
on the lines to optimize power savings during suspend.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
---
 arch/arm/boot/dts/am437x-gp-evm.dts | 20 ++++++++++++++++++--
 1 file changed, 18 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts
index 6d03baa..ca9e1ab 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -262,12 +262,26 @@
 		>;
 	};
 
+	dcan0_sleep: dcan0_sleep_pins {
+		pinctrl-single,pins = <
+			0x178 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x17c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+		>;
+	};
+
 	dcan1_default: dcan1_default_pins {
 		pinctrl-single,pins = <
 			0x180 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* uart1_rxd.d_can1_tx */
 			0x184 (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_txd.d_can1_rx */
 		>;
 	};
+
+	dcan1_sleep: dcan1_sleep_pins {
+		pinctrl-single,pins = <
+			0x180 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x184 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+		>;
+	};
 };
 
 &i2c0 {
@@ -527,13 +541,15 @@
 };
 
 &dcan0 {
-	pinctrl-names = "default";
+	pinctrl-names = "default", "sleep";
 	pinctrl-0 = <&dcan0_default>;
+	pinctrl-1 = <&dcan0_sleep>;
 	status = "okay";
 };
 
 &dcan1 {
-	pinctrl-names = "default";
+	pinctrl-names = "default", "sleep";
 	pinctrl-0 = <&dcan1_default>;
+	pinctrl-1 = <&dcan1_sleep>;
 	status = "okay";
 };
-- 
1.8.3.2

[PATCH 11/13] ARM: dts: am437x-gp-evm: Add pinctrl sleep states for dcan pins

[Roger Quadros]

From: Dave Gerlach <d-gerlach@ti.com>

Define pinctrl sleep states for both dcan0 and dcan1 to place pull downs
on the lines to optimize power savings during suspend.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
---
 arch/arm/boot/dts/am437x-gp-evm.dts | 20 ++++++++++++++++++--
 1 file changed, 18 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts
index 6d03baa..ca9e1ab 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -262,12 +262,26 @@
 		>;
 	};
 
+	dcan0_sleep: dcan0_sleep_pins {
+		pinctrl-single,pins = <
+			0x178 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x17c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+		>;
+	};
+
 	dcan1_default: dcan1_default_pins {
 		pinctrl-single,pins = <
 			0x180 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* uart1_rxd.d_can1_tx */
 			0x184 (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_txd.d_can1_rx */
 		>;
 	};
+
+	dcan1_sleep: dcan1_sleep_pins {
+		pinctrl-single,pins = <
+			0x180 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x184 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+		>;
+	};
 };
 
 &i2c0 {
@@ -527,13 +541,15 @@
 };
 
 &dcan0 {
-	pinctrl-names = "default";
+	pinctrl-names = "default", "sleep";
 	pinctrl-0 = <&dcan0_default>;
+	pinctrl-1 = <&dcan0_sleep>;
 	status = "okay";
 };
 
 &dcan1 {
-	pinctrl-names = "default";
+	pinctrl-names = "default", "sleep";
 	pinctrl-0 = <&dcan1_default>;
+	pinctrl-1 = <&dcan1_sleep>;
 	status = "okay";
 };
-- 
1.8.3.2

[PATCH 12/13] ARM: dts: am4372: Add control module syscon node

[Roger Quadros]

Use syscon regmap to expose the Control module register space.
This register space is shared between many users e.g. DCAN, USB, display, etc.

Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 arch/arm/boot/dts/am4372.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index a705e50..d38a0ed 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -59,6 +59,11 @@
 		cache-level = <2>;
 	};
 
+	am43xx_control_module: control_module@4a002000 {
+		compatible = "syscon";
+		reg = <0x44e10000 0x7f4>;
+	};
+
 	am43xx_pinmux: pinmux@44e10800 {
 		compatible = "pinctrl-single";
 		reg = <0x44e10800 0x31c>;
-- 
1.8.3.2

[PATCH 12/13] ARM: dts: am4372: Add control module syscon node

[Roger Quadros]

Use syscon regmap to expose the Control module register space.
This register space is shared between many users e.g. DCAN, USB, display, etc.

Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 arch/arm/boot/dts/am4372.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index a705e50..d38a0ed 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -59,6 +59,11 @@
 		cache-level = <2>;
 	};
 
+	am43xx_control_module: control_module@4a002000 {
+		compatible = "syscon";
+		reg = <0x44e10000 0x7f4>;
+	};
+
 	am43xx_pinmux: pinmux@44e10800 {
 		compatible = "pinctrl-single";
 		reg = <0x44e10800 0x31c>;
-- 
1.8.3.2

[PATCH 13/13] ARM: dts: am4372: Add dcan raminit bits

[Roger Quadros]

Add RAMINIT specific bits into the DCAN nodes.

Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 arch/arm/boot/dts/am4372.dtsi | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index d38a0ed..33d27cd 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -899,7 +899,10 @@
 			clocks = <&dcan0_fck>;
 			clock-names = "fck";
 			reg = <0x481cc000 0x2000
-				0x44e10644 0x4>;
+				0x644 0x4>; /* index to RAMINIT reg within syscon */
+			raminit-syscon = <&am43xx_control_module>;
+			raminit-start-bit = <0>;
+			raminit-done-bit = <8>;
 			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 			status = "disabled";
 		};
@@ -910,7 +913,10 @@
 			clocks = <&dcan1_fck>;
 			clock-names = "fck";
 			reg = <0x481d0000 0x2000
-				0x44e10644 0x4>;
+				0x644 0x4>; /* index to RAMINIT reg within syscon */
+			raminit-syscon = <&am43xx_control_module>;
+			raminit-start-bit = <1>;
+			raminit-done-bit = <9>;
 			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 			status = "disabled";
 		};
-- 
1.8.3.2

[PATCH 13/13] ARM: dts: am4372: Add dcan raminit bits

[Roger Quadros]

Add RAMINIT specific bits into the DCAN nodes.

Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 arch/arm/boot/dts/am4372.dtsi | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index d38a0ed..33d27cd 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -899,7 +899,10 @@
 			clocks = <&dcan0_fck>;
 			clock-names = "fck";
 			reg = <0x481cc000 0x2000
-				0x44e10644 0x4>;
+				0x644 0x4>; /* index to RAMINIT reg within syscon */
+			raminit-syscon = <&am43xx_control_module>;
+			raminit-start-bit = <0>;
+			raminit-done-bit = <8>;
 			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 			status = "disabled";
 		};
@@ -910,7 +913,10 @@
 			clocks = <&dcan1_fck>;
 			clock-names = "fck";
 			reg = <0x481d0000 0x2000
-				0x44e10644 0x4>;
+				0x644 0x4>; /* index to RAMINIT reg within syscon */
+			raminit-syscon = <&am43xx_control_module>;
+			raminit-start-bit = <1>;
+			raminit-done-bit = <9>;
 			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 			status = "disabled";
 		};
-- 
1.8.3.2

Re: [PATCH 05/13] ARM: dts: DRA7: Add DCAN nodes

[Sergei Shtylyov]

Hello.

On 9/8/2014 6:10 PM, Roger Quadros wrote:

> The SoC supports 2 DCAN nodes. Add them.

> Signed-off-by: Roger Quadros <rogerq@ti.com>
> ---
>   arch/arm/boot/dts/dra7.dtsi | 30 ++++++++++++++++++++++++++++++
>   1 file changed, 30 insertions(+)

> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
> index 370009e..4ce1a4f 100644
> --- a/arch/arm/boot/dts/dra7.dtsi
> +++ b/arch/arm/boot/dts/dra7.dtsi
[...]
> @@ -1267,6 +1269,34 @@
>   			ti,irqs-skip = <10 133 139 140>;
>   			ti,irqs-safe-map = <0>;
>   		};
> +
> +		dcan1: d_can@481cc000 {

    The ePAPR standard has something to say here:

 >>
The name of a node should be somewhat generic, reflecting the function of the 
device and not its precise programming model. If appropriate, the name should 
be one of the following choices:

	• can
 >>

> +			compatible = "bosch,d_can";
> +			ti,hwmods = "dcan1";
> +			reg = <0x4ae3c000 0x2000>,
> +			      <0x558 0x4>; /* index to RAMINIT reg within syscon */
> +			raminit-syscon = <&dra7_ctrl_core>;
> +			raminit-start-bit = <3>;
> +			raminit-done-bit = <1>;
> +			raminit-pulse;

    Hm, aren't the above 4 properties vendor specific? If so, they should 
start with a vendor prefix and comma.

> +			interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&dcan1_sys_clk_mux>;
> +			status = "disabled";
> +		};

WBR, Sergei

Re: [PATCH 05/13] ARM: dts: DRA7: Add DCAN nodes

[Sergei Shtylyov]

Hello.

On 9/8/2014 6:10 PM, Roger Quadros wrote:

> The SoC supports 2 DCAN nodes. Add them.

> Signed-off-by: Roger Quadros <rogerq@ti.com>
> ---
>   arch/arm/boot/dts/dra7.dtsi | 30 ++++++++++++++++++++++++++++++
>   1 file changed, 30 insertions(+)

> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
> index 370009e..4ce1a4f 100644
> --- a/arch/arm/boot/dts/dra7.dtsi
> +++ b/arch/arm/boot/dts/dra7.dtsi
[...]
> @@ -1267,6 +1269,34 @@
>   			ti,irqs-skip = <10 133 139 140>;
>   			ti,irqs-safe-map = <0>;
>   		};
> +
> +		dcan1: d_can@481cc000 {

    The ePAPR standard has something to say here:

 >>
The name of a node should be somewhat generic, reflecting the function of the 
device and not its precise programming model. If appropriate, the name should 
be one of the following choices:

	• can
 >>

> +			compatible = "bosch,d_can";
> +			ti,hwmods = "dcan1";
> +			reg = <0x4ae3c000 0x2000>,
> +			      <0x558 0x4>; /* index to RAMINIT reg within syscon */
> +			raminit-syscon = <&dra7_ctrl_core>;
> +			raminit-start-bit = <3>;
> +			raminit-done-bit = <1>;
> +			raminit-pulse;

    Hm, aren't the above 4 properties vendor specific? If so, they should 
start with a vendor prefix and comma.

> +			interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&dcan1_sys_clk_mux>;
> +			status = "disabled";
> +		};

WBR, Sergei

Re: [PATCH 04/13] ARM: dts: dra7: Add syscon regmap for CORE CONTROL area

[Tony Lindgren]

* Roger Quadros <rogerq@ti.com> [140908 07:11]:
> Display and DCAN drivers use syscon regmap to access some registers
> in the CORE control area. Add the syscon regmap node for this
> area.

Please repost the .dts changes in a separate series to avoid
conflicts.

Thanks,

Tony

Re: [PATCH 04/13] ARM: dts: dra7: Add syscon regmap for CORE CONTROL area

[Tony Lindgren]

* Roger Quadros <rogerq@ti.com> [140908 07:11]:
> Display and DCAN drivers use syscon regmap to access some registers
> in the CORE control area. Add the syscon regmap node for this
> area.

Please repost the .dts changes in a separate series to avoid
conflicts.

Thanks,

Tony

Re: [PATCH 05/13] ARM: dts: DRA7: Add DCAN nodes

[Roger Quadros]

Hi,

On 09/08/2014 07:40 PM, Sergei Shtylyov wrote:
> Hello.
> 
> On 9/8/2014 6:10 PM, Roger Quadros wrote:
> 
>> The SoC supports 2 DCAN nodes. Add them.
> 
>> Signed-off-by: Roger Quadros <rogerq@ti.com>
>> ---
>>   arch/arm/boot/dts/dra7.dtsi | 30 ++++++++++++++++++++++++++++++
>>   1 file changed, 30 insertions(+)
> 
>> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
>> index 370009e..4ce1a4f 100644
>> --- a/arch/arm/boot/dts/dra7.dtsi
>> +++ b/arch/arm/boot/dts/dra7.dtsi
> [...]
>> @@ -1267,6 +1269,34 @@
>>               ti,irqs-skip = <10 133 139 140>;
>>               ti,irqs-safe-map = <0>;
>>           };
>> +
>> +        dcan1: d_can@481cc000 {
> 
>    The ePAPR standard has something to say here:
> 
>>>
> The name of a node should be somewhat generic, reflecting the function of the device and not its precise programming model. If appropriate, the name should be one of the following choices:
> 
>     • can

Right. I'll fix it up.

>>>
> 
>> +            compatible = "bosch,d_can";
>> +            ti,hwmods = "dcan1";
>> +            reg = <0x4ae3c000 0x2000>,
>> +                  <0x558 0x4>; /* index to RAMINIT reg within syscon */
>> +            raminit-syscon = <&dra7_ctrl_core>;
>> +            raminit-start-bit = <3>;
>> +            raminit-done-bit = <1>;
>> +            raminit-pulse;
> 
>    Hm, aren't the above 4 properties vendor specific? If so, they should start with a vendor prefix and comma.

At least for now I don't know about any other platform other than TI using a RAMINIT register outside the
CAN register space. However the mechanism is generic enough and not limited to TI platforms.

I don't mind vendor prefix or not, but would like to hear the opinion of the CAN maintainers as to what they would prefer.

> 
>> +            interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
>> +            clocks = <&dcan1_sys_clk_mux>;
>> +            status = "disabled";
>> +        };
> 

cheers,
-roger

Re: [PATCH 05/13] ARM: dts: DRA7: Add DCAN nodes

[Roger Quadros]

Hi,

On 09/08/2014 07:40 PM, Sergei Shtylyov wrote:
> Hello.
> 
> On 9/8/2014 6:10 PM, Roger Quadros wrote:
> 
>> The SoC supports 2 DCAN nodes. Add them.
> 
>> Signed-off-by: Roger Quadros <rogerq@ti.com>
>> ---
>>   arch/arm/boot/dts/dra7.dtsi | 30 ++++++++++++++++++++++++++++++
>>   1 file changed, 30 insertions(+)
> 
>> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
>> index 370009e..4ce1a4f 100644
>> --- a/arch/arm/boot/dts/dra7.dtsi
>> +++ b/arch/arm/boot/dts/dra7.dtsi
> [...]
>> @@ -1267,6 +1269,34 @@
>>               ti,irqs-skip = <10 133 139 140>;
>>               ti,irqs-safe-map = <0>;
>>           };
>> +
>> +        dcan1: d_can@481cc000 {
> 
>    The ePAPR standard has something to say here:
> 
>>>
> The name of a node should be somewhat generic, reflecting the function of the device and not its precise programming model. If appropriate, the name should be one of the following choices:
> 
>     • can

Right. I'll fix it up.

>>>
> 
>> +            compatible = "bosch,d_can";
>> +            ti,hwmods = "dcan1";
>> +            reg = <0x4ae3c000 0x2000>,
>> +                  <0x558 0x4>; /* index to RAMINIT reg within syscon */
>> +            raminit-syscon = <&dra7_ctrl_core>;
>> +            raminit-start-bit = <3>;
>> +            raminit-done-bit = <1>;
>> +            raminit-pulse;
> 
>    Hm, aren't the above 4 properties vendor specific? If so, they should start with a vendor prefix and comma.

At least for now I don't know about any other platform other than TI using a RAMINIT register outside the
CAN register space. However the mechanism is generic enough and not limited to TI platforms.

I don't mind vendor prefix or not, but would like to hear the opinion of the CAN maintainers as to what they would prefer.

> 
>> +            interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
>> +            clocks = <&dcan1_sys_clk_mux>;
>> +            status = "disabled";
>> +        };
> 

cheers,
-roger

Re: [PATCH 05/13] ARM: dts: DRA7: Add DCAN nodes

[Marc Kleine-Budde]

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On 09/09/2014 10:30 AM, Roger Quadros wrote:
>>> +            compatible = "bosch,d_can";
>>> +            ti,hwmods = "dcan1";
>>> +            reg = <0x4ae3c000 0x2000>,
>>> +                  <0x558 0x4>; /* index to RAMINIT reg within syscon */
>>> +            raminit-syscon = <&dra7_ctrl_core>;
>>> +            raminit-start-bit = <3>;
>>> +            raminit-done-bit = <1>;
>>> +            raminit-pulse;
>>
>>    Hm, aren't the above 4 properties vendor specific? If so, they should start with a vendor prefix and comma.
> 
> At least for now I don't know about any other platform other than TI using a RAMINIT register outside the
> CAN register space. However the mechanism is generic enough and not limited to TI platforms.
> 
> I don't mind vendor prefix or not, but would like to hear the opinion of the CAN maintainers as to what they would prefer.

I don't know of any c_can/d_can implementation outside of TI that
implements the raminit outside of the register space. So a "ti," prefix
seems appropriate.

Marc

-- 
Pengutronix e.K.                  | Marc Kleine-Budde           |
Industrial Linux Solutions        | Phone: +49-231-2826-924     |
Vertretung West/Dortmund          | Fax:   +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686  | http://www.pengutronix.de   |


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Re: [PATCH 05/13] ARM: dts: DRA7: Add DCAN nodes

[Marc Kleine-Budde]

[-- Attachment #1: Type: text/plain, Size: 1331 bytes --]

On 09/09/2014 10:30 AM, Roger Quadros wrote:
>>> +            compatible = "bosch,d_can";
>>> +            ti,hwmods = "dcan1";
>>> +            reg = <0x4ae3c000 0x2000>,
>>> +                  <0x558 0x4>; /* index to RAMINIT reg within syscon */
>>> +            raminit-syscon = <&dra7_ctrl_core>;
>>> +            raminit-start-bit = <3>;
>>> +            raminit-done-bit = <1>;
>>> +            raminit-pulse;
>>
>>    Hm, aren't the above 4 properties vendor specific? If so, they should start with a vendor prefix and comma.
> 
> At least for now I don't know about any other platform other than TI using a RAMINIT register outside the
> CAN register space. However the mechanism is generic enough and not limited to TI platforms.
> 
> I don't mind vendor prefix or not, but would like to hear the opinion of the CAN maintainers as to what they would prefer.

I don't know of any c_can/d_can implementation outside of TI that
implements the raminit outside of the register space. So a "ti," prefix
seems appropriate.

Marc

-- 
Pengutronix e.K.                  | Marc Kleine-Budde           |
Industrial Linux Solutions        | Phone: +49-231-2826-924     |
Vertretung West/Dortmund          | Fax:   +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686  | http://www.pengutronix.de   |


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Re: [PATCH 05/13] ARM: dts: DRA7: Add DCAN nodes

[Roger Quadros]

Hi Marc,

On 09/09/2014 11:34 AM, Marc Kleine-Budde wrote:
> On 09/09/2014 10:30 AM, Roger Quadros wrote:
>>>> +            compatible = "bosch,d_can";
>>>> +            ti,hwmods = "dcan1";
>>>> +            reg = <0x4ae3c000 0x2000>,
>>>> +                  <0x558 0x4>; /* index to RAMINIT reg within syscon */
>>>> +            raminit-syscon = <&dra7_ctrl_core>;
>>>> +            raminit-start-bit = <3>;
>>>> +            raminit-done-bit = <1>;
>>>> +            raminit-pulse;
>>>
>>>    Hm, aren't the above 4 properties vendor specific? If so, they should start with a vendor prefix and comma.
>>
>> At least for now I don't know about any other platform other than TI using a RAMINIT register outside the
>> CAN register space. However the mechanism is generic enough and not limited to TI platforms.
>>
>> I don't mind vendor prefix or not, but would like to hear the opinion of the CAN maintainers as to what they would prefer.
> 
> I don't know of any c_can/d_can implementation outside of TI that
> implements the raminit outside of the register space. So a "ti," prefix
> seems appropriate.
> 

Fine, I'll re-spin this with the "ti," prefix. Thanks.

cheers,
-roger
 

Re: [PATCH 05/13] ARM: dts: DRA7: Add DCAN nodes

[Roger Quadros]

Hi Marc,

On 09/09/2014 11:34 AM, Marc Kleine-Budde wrote:
> On 09/09/2014 10:30 AM, Roger Quadros wrote:
>>>> +            compatible = "bosch,d_can";
>>>> +            ti,hwmods = "dcan1";
>>>> +            reg = <0x4ae3c000 0x2000>,
>>>> +                  <0x558 0x4>; /* index to RAMINIT reg within syscon */
>>>> +            raminit-syscon = <&dra7_ctrl_core>;
>>>> +            raminit-start-bit = <3>;
>>>> +            raminit-done-bit = <1>;
>>>> +            raminit-pulse;
>>>
>>>    Hm, aren't the above 4 properties vendor specific? If so, they should start with a vendor prefix and comma.
>>
>> At least for now I don't know about any other platform other than TI using a RAMINIT register outside the
>> CAN register space. However the mechanism is generic enough and not limited to TI platforms.
>>
>> I don't mind vendor prefix or not, but would like to hear the opinion of the CAN maintainers as to what they would prefer.
> 
> I don't know of any c_can/d_can implementation outside of TI that
> implements the raminit outside of the register space. So a "ti," prefix
> seems appropriate.
> 

Fine, I'll re-spin this with the "ti," prefix. Thanks.

cheers,
-roger