[PATCH v1 1/3] i2c: designware-pci: shrink dw_pci_controllers array

[PATCH v1 1/3] i2c: designware-pci: shrink dw_pci_controllers array

[Andy Shevchenko]

There is no need to duplicate same data for each controller. If we need
specific stuff for a certain controller in the future we may add it later. The
patch leaves one controller per platform.

Signed-off-by: Andy Shevchenko <andriy.shevchenko-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
---
 drivers/i2c/busses/i2c-designware-pcidrv.c | 96 ++++++------------------------
 1 file changed, 19 insertions(+), 77 deletions(-)

diff --git a/drivers/i2c/busses/i2c-designware-pcidrv.c b/drivers/i2c/busses/i2c-designware-pcidrv.c
index acb40f9..9237abb 100644
--- a/drivers/i2c/busses/i2c-designware-pcidrv.c
+++ b/drivers/i2c/busses/i2c-designware-pcidrv.c
@@ -40,17 +40,8 @@
 #define DRIVER_NAME "i2c-designware-pci"
 
 enum dw_pci_ctl_id_t {
-	moorestown_0,
-	moorestown_1,
-	moorestown_2,
-
-	medfield_0,
-	medfield_1,
-	medfield_2,
-	medfield_3,
-	medfield_4,
-	medfield_5,
-
+	moorestown,
+	medfield,
 	baytrail,
 	haswell,
 };
@@ -102,68 +93,19 @@ static struct dw_scl_sda_cfg hsw_config = {
 };
 
 static struct  dw_pci_controller  dw_pci_controllers[] = {
-	[moorestown_0] = {
-		.bus_num     = 0,
-		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
-		.tx_fifo_depth = 32,
-		.rx_fifo_depth = 32,
-		.clk_khz      = 25000,
-	},
-	[moorestown_1] = {
-		.bus_num     = 1,
-		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
-		.tx_fifo_depth = 32,
-		.rx_fifo_depth = 32,
-		.clk_khz      = 25000,
-	},
-	[moorestown_2] = {
-		.bus_num     = 2,
-		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
-		.tx_fifo_depth = 32,
-		.rx_fifo_depth = 32,
-		.clk_khz      = 25000,
-	},
-	[medfield_0] = {
-		.bus_num     = 0,
-		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
-		.tx_fifo_depth = 32,
-		.rx_fifo_depth = 32,
-		.clk_khz      = 25000,
-	},
-	[medfield_1] = {
-		.bus_num     = 1,
-		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
-		.tx_fifo_depth = 32,
-		.rx_fifo_depth = 32,
-		.clk_khz      = 25000,
-	},
-	[medfield_2] = {
-		.bus_num     = 2,
-		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
-		.tx_fifo_depth = 32,
-		.rx_fifo_depth = 32,
-		.clk_khz      = 25000,
-	},
-	[medfield_3] = {
-		.bus_num     = 3,
-		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_STD,
-		.tx_fifo_depth = 32,
-		.rx_fifo_depth = 32,
-		.clk_khz      = 25000,
-	},
-	[medfield_4] = {
-		.bus_num     = 4,
-		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
+	[moorestown] = {
+		.bus_num = -1,
+		.bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
 		.tx_fifo_depth = 32,
 		.rx_fifo_depth = 32,
-		.clk_khz      = 25000,
+		.clk_khz = 25000,
 	},
-	[medfield_5] = {
-		.bus_num     = 5,
-		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
+	[medfield] = {
+		.bus_num = -1,
+		.bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
 		.tx_fifo_depth = 32,
 		.rx_fifo_depth = 32,
-		.clk_khz      = 25000,
+		.clk_khz = 25000,
 	},
 	[baytrail] = {
 		.bus_num = -1,
@@ -326,16 +268,16 @@ MODULE_ALIAS("i2c_designware-pci");
 
 static const struct pci_device_id i2_designware_pci_ids[] = {
 	/* Moorestown */
-	{ PCI_VDEVICE(INTEL, 0x0802), moorestown_0 },
-	{ PCI_VDEVICE(INTEL, 0x0803), moorestown_1 },
-	{ PCI_VDEVICE(INTEL, 0x0804), moorestown_2 },
+	{ PCI_VDEVICE(INTEL, 0x0802), moorestown },
+	{ PCI_VDEVICE(INTEL, 0x0803), moorestown },
+	{ PCI_VDEVICE(INTEL, 0x0804), moorestown },
 	/* Medfield */
-	{ PCI_VDEVICE(INTEL, 0x0817), medfield_3,},
-	{ PCI_VDEVICE(INTEL, 0x0818), medfield_4 },
-	{ PCI_VDEVICE(INTEL, 0x0819), medfield_5 },
-	{ PCI_VDEVICE(INTEL, 0x082C), medfield_0 },
-	{ PCI_VDEVICE(INTEL, 0x082D), medfield_1 },
-	{ PCI_VDEVICE(INTEL, 0x082E), medfield_2 },
+	{ PCI_VDEVICE(INTEL, 0x0817), medfield },
+	{ PCI_VDEVICE(INTEL, 0x0818), medfield },
+	{ PCI_VDEVICE(INTEL, 0x0819), medfield },
+	{ PCI_VDEVICE(INTEL, 0x082c), medfield },
+	{ PCI_VDEVICE(INTEL, 0x082d), medfield },
+	{ PCI_VDEVICE(INTEL, 0x082e), medfield },
 	/* Baytrail */
 	{ PCI_VDEVICE(INTEL, 0x0F41), baytrail },
 	{ PCI_VDEVICE(INTEL, 0x0F42), baytrail },
-- 
2.1.4

[PATCH v1 2/3] i2c: designware-pci: update Intel copytight line

[Andy Shevchenko]

While here, fix few indentations issues across the code. There is no functional
change.

Signed-off-by: Andy Shevchenko <andriy.shevchenko-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
---
 drivers/i2c/busses/i2c-designware-pcidrv.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/i2c/busses/i2c-designware-pcidrv.c b/drivers/i2c/busses/i2c-designware-pcidrv.c
index 9237abb..2bbd2a7 100644
--- a/drivers/i2c/busses/i2c-designware-pcidrv.c
+++ b/drivers/i2c/busses/i2c-designware-pcidrv.c
@@ -6,7 +6,7 @@
  * Copyright (C) 2006 Texas Instruments.
  * Copyright (C) 2007 MontaVista Software Inc.
  * Copyright (C) 2009 Provigent Ltd.
- * Copyright (C) 2011 Intel corporation.
+ * Copyright (C) 2011,2015 Intel Corporation.
  *
  * ----------------------------------------------------------------------------
  *
@@ -92,7 +92,7 @@ static struct dw_scl_sda_cfg hsw_config = {
 	.sda_hold = 0x9,
 };
 
-static struct  dw_pci_controller  dw_pci_controllers[] = {
+static struct dw_pci_controller dw_pci_controllers[] = {
 	[moorestown] = {
 		.bus_num = -1,
 		.bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
@@ -201,7 +201,7 @@ static int i2c_dw_pci_probe(struct pci_dev *pdev,
 	dev->functionality = controller->functionality |
 				DW_DEFAULT_FUNCTIONALITY;
 
-	dev->master_cfg =  controller->bus_cfg;
+	dev->master_cfg = controller->bus_cfg;
 	if (controller->scl_sda_cfg) {
 		cfg = controller->scl_sda_cfg;
 		dev->ss_hcnt = cfg->ss_hcnt;
@@ -290,7 +290,7 @@ static const struct pci_device_id i2_designware_pci_ids[] = {
 	{ PCI_VDEVICE(INTEL, 0x9c61), haswell },
 	{ PCI_VDEVICE(INTEL, 0x9c62), haswell },
 	/* Braswell / Cherrytrail */
-	{ PCI_VDEVICE(INTEL, 0x22C1), baytrail,},
+	{ PCI_VDEVICE(INTEL, 0x22C1), baytrail },
 	{ PCI_VDEVICE(INTEL, 0x22C2), baytrail },
 	{ PCI_VDEVICE(INTEL, 0x22C3), baytrail },
 	{ PCI_VDEVICE(INTEL, 0x22C4), baytrail },
-- 
2.1.4

[PATCH v1 3/3] i2c: designware-pci: no need to provide clk_khz

[Andy Shevchenko]

The clk_khz field makes sense only if SS counters are not provided. Since we
provide them for Haswell and Baytrail explicitly we can omit the clk_khz
parameter.

Signed-off-by: Andy Shevchenko <andriy.shevchenko-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
---
 drivers/i2c/busses/i2c-designware-pcidrv.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/i2c/busses/i2c-designware-pcidrv.c b/drivers/i2c/busses/i2c-designware-pcidrv.c
index 2bbd2a7..506cbe8 100644
--- a/drivers/i2c/busses/i2c-designware-pcidrv.c
+++ b/drivers/i2c/busses/i2c-designware-pcidrv.c
@@ -112,7 +112,6 @@ static struct dw_pci_controller dw_pci_controllers[] = {
 		.bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
 		.tx_fifo_depth = 32,
 		.rx_fifo_depth = 32,
-		.clk_khz = 100000,
 		.functionality = I2C_FUNC_10BIT_ADDR,
 		.scl_sda_cfg = &byt_config,
 	},
@@ -121,7 +120,6 @@ static struct dw_pci_controller dw_pci_controllers[] = {
 		.bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
 		.tx_fifo_depth = 32,
 		.rx_fifo_depth = 32,
-		.clk_khz = 100000,
 		.functionality = I2C_FUNC_10BIT_ADDR,
 		.scl_sda_cfg = &hsw_config,
 	},
-- 
2.1.4

Re: [PATCH v1 1/3] i2c: designware-pci: shrink dw_pci_controllers array

[David Cohen]

Hi Andy,

On Thu, Jan 22, 2015 at 04:44:27PM +0200, Andy Shevchenko wrote:
> There is no need to duplicate same data for each controller. If we need
> specific stuff for a certain controller in the future we may add it later. The
> patch leaves one controller per platform.
> 
> Signed-off-by: Andy Shevchenko <andriy.shevchenko-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
> ---
>  drivers/i2c/busses/i2c-designware-pcidrv.c | 96 ++++++------------------------
>  1 file changed, 19 insertions(+), 77 deletions(-)
> 
> diff --git a/drivers/i2c/busses/i2c-designware-pcidrv.c b/drivers/i2c/busses/i2c-designware-pcidrv.c
> index acb40f9..9237abb 100644
> --- a/drivers/i2c/busses/i2c-designware-pcidrv.c
> +++ b/drivers/i2c/busses/i2c-designware-pcidrv.c
> @@ -40,17 +40,8 @@
>  #define DRIVER_NAME "i2c-designware-pci"
>  
>  enum dw_pci_ctl_id_t {
> -	moorestown_0,
> -	moorestown_1,
> -	moorestown_2,
> -
> -	medfield_0,
> -	medfield_1,
> -	medfield_2,
> -	medfield_3,
> -	medfield_4,
> -	medfield_5,
> -
> +	moorestown,

Since you're doing this rework, could you remove moorestown for good?
It's no longer supported as one of intel mid's platform anyway.

Br, David

Re: [PATCH v1 1/3] i2c: designware-pci: shrink dw_pci_controllers array

[Wolfram Sang]

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> Since you're doing this rework, could you remove moorestown for good?
> It's no longer supported as one of intel mid's platform anyway.

If support for that platform is not broken anyhow, I'd say let's keep
it. There still might be users out there...


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Re: [PATCH v1 1/3] i2c: designware-pci: shrink dw_pci_controllers array

[David Cohen]

On Thu, Jan 22, 2015 at 08:17:58PM +0100, Wolfram Sang wrote:
> 
> > Since you're doing this rework, could you remove moorestown for good?
> > It's no longer supported as one of intel mid's platform anyway.
> 
> If support for that platform is not broken anyhow, I'd say let's keep
> it. There still might be users out there...
> 

It actually is. When Medfield, Clover Trail and Merrifield support was
merged, Moorefield support became broken with no interest from anybody
to fix it. It's time now to remove all of its code :)

Br, David

Re: [PATCH v1 3/3] i2c: designware-pci: no need to provide clk_khz

[Jarkko Nikula]

On 01/22/2015 04:44 PM, Andy Shevchenko wrote:
> The clk_khz field makes sense only if SS counters are not provided. Since we
> provide them for Haswell and Baytrail explicitly we can omit the clk_khz
> parameter.
>
> Signed-off-by: Andy Shevchenko <andriy.shevchenko-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
> ---
>   drivers/i2c/busses/i2c-designware-pcidrv.c | 2 --
>   1 file changed, 2 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-designware-pcidrv.c b/drivers/i2c/busses/i2c-designware-pcidrv.c
> index 2bbd2a7..506cbe8 100644
> --- a/drivers/i2c/busses/i2c-designware-pcidrv.c
> +++ b/drivers/i2c/busses/i2c-designware-pcidrv.c
> @@ -112,7 +112,6 @@ static struct dw_pci_controller dw_pci_controllers[] = {
>   		.bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
>   		.tx_fifo_depth = 32,
>   		.rx_fifo_depth = 32,
> -		.clk_khz = 100000,
>   		.functionality = I2C_FUNC_10BIT_ADDR,
>   		.scl_sda_cfg = &byt_config,
>   	},
> @@ -121,7 +120,6 @@ static struct dw_pci_controller dw_pci_controllers[] = {
>   		.bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
>   		.tx_fifo_depth = 32,
>   		.rx_fifo_depth = 32,
> -		.clk_khz = 100000,
>   		.functionality = I2C_FUNC_10BIT_ADDR,
>   		.scl_sda_cfg = &hsw_config,
>   	},
>
Yes, there are no other use for the clock rate than calculate these SS 
counters in drivers/i2c/busses/i2c-designware-core.c, and which will get 
overwritten by provided values.

Reviewed-by: Jarkko Nikula <jarkko.nikula-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>

Re: [PATCH v1 1/3] i2c: designware-pci: shrink dw_pci_controllers array

[Andy Shevchenko]

On Thu, 2015-01-22 at 14:27 -0800, David Cohen wrote:
> On Thu, Jan 22, 2015 at 08:17:58PM +0100, Wolfram Sang wrote:
> > 
> > > Since you're doing this rework, could you remove moorestown for good?
> > > It's no longer supported as one of intel mid's platform anyway.
> > 
> > If support for that platform is not broken anyhow, I'd say let's keep
> > it. There still might be users out there...
> > 
> 
> It actually is. When Medfield, Clover Trail and Merrifield support was
> merged, Moorefield support became broken with no interest from anybody
> to fix it. It's time now to remove all of its code :)

You perhaps meant Moorestown.


-- 
Andy Shevchenko <andriy.shevchenko-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
Intel Finland Oy

Re: [PATCH v1 1/3] i2c: designware-pci: shrink dw_pci_controllers array

[David Cohen]

On Fri, Jan 23, 2015 at 01:57:29PM +0200, Andy Shevchenko wrote:
> On Thu, 2015-01-22 at 14:27 -0800, David Cohen wrote:
> > On Thu, Jan 22, 2015 at 08:17:58PM +0100, Wolfram Sang wrote:
> > > 
> > > > Since you're doing this rework, could you remove moorestown for good?
> > > > It's no longer supported as one of intel mid's platform anyway.
> > > 
> > > If support for that platform is not broken anyhow, I'd say let's keep
> > > it. There still might be users out there...
> > > 
> > 
> > It actually is. When Medfield, Clover Trail and Merrifield support was
> > merged, Moorefield support became broken with no interest from anybody
> > to fix it. It's time now to remove all of its code :)
> 
> You perhaps meant Moorestown.

Oops. Sorry for the typo. Yes, I meant Morrestown :)

Br, David

Re: [PATCH v1 1/3] i2c: designware-pci: shrink dw_pci_controllers array

[David Cohen]

On Fri, Jan 23, 2015 at 09:50:44AM -0800, David Cohen wrote:
> On Fri, Jan 23, 2015 at 01:57:29PM +0200, Andy Shevchenko wrote:
> > On Thu, 2015-01-22 at 14:27 -0800, David Cohen wrote:
> > > On Thu, Jan 22, 2015 at 08:17:58PM +0100, Wolfram Sang wrote:
> > > > 
> > > > > Since you're doing this rework, could you remove moorestown for good?
> > > > > It's no longer supported as one of intel mid's platform anyway.
> > > > 
> > > > If support for that platform is not broken anyhow, I'd say let's keep
> > > > it. There still might be users out there...
> > > > 
> > > 
> > > It actually is. When Medfield, Clover Trail and Merrifield support was
> > > merged, Moorefield support became broken with no interest from anybody
> > > to fix it. It's time now to remove all of its code :)
> > 
> > You perhaps meant Moorestown.
> 
> Oops. Sorry for the typo. Yes, I meant Morrestown :)

Grrr... Moorestown :)

> 
> Br, David