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* [PATCH 1/9] usb:fsl:otg: Add controller version based ULPI and UTMI phy
@ 2015-03-26 15:17 Ramneek Mehresh
  2015-03-26 15:17 ` [PATCH 2/9][v2]usb:fsl:otg: Add support to add/remove usb host driver Ramneek Mehresh
                   ` (8 more replies)
  0 siblings, 9 replies; 15+ messages in thread
From: Ramneek Mehresh @ 2015-03-26 15:17 UTC (permalink / raw)
  To: linux-kernel; +Cc: balbi, stern, gregkh, Ramneek Mehresh, Shengzhou Liu

Add controller version based ULPI and UTMI phy initialization for
otg driver

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
---
 drivers/usb/phy/phy-fsl-usb.c | 20 ++++++++++++++++++++
 drivers/usb/phy/phy-fsl-usb.h |  7 +++++++
 2 files changed, 27 insertions(+)

diff --git a/drivers/usb/phy/phy-fsl-usb.c b/drivers/usb/phy/phy-fsl-usb.c
index 94eb292..f90093a 100644
--- a/drivers/usb/phy/phy-fsl-usb.c
+++ b/drivers/usb/phy/phy-fsl-usb.c
@@ -923,12 +923,32 @@ int usb_otg_start(struct platform_device *pdev)
 	temp &= ~(PORTSC_PHY_TYPE_SEL | PORTSC_PTW);
 	switch (pdata->phy_mode) {
 	case FSL_USB2_PHY_ULPI:
+		if (pdata->controller_ver) {
+			/* controller version 1.6 or above */
+			setbits32(&p_otg->dr_mem_map->control,
+				USB_CTRL_ULPI_PHY_CLK_SEL);
+			/*
+			 * Due to controller issue of PHY_CLK_VALID in ULPI
+			 * mode, we set USB_CTRL_USB_EN before checking
+			 * PHY_CLK_VALID, otherwise PHY_CLK_VALID doesn't work.
+			 */
+			clrsetbits_be32(&p_otg->dr_mem_map->control,
+				 USB_CTRL_UTMI_PHY_EN, USB_CTRL_IOENB);
+		}
 		temp |= PORTSC_PTS_ULPI;
 		break;
 	case FSL_USB2_PHY_UTMI_WIDE:
 		temp |= PORTSC_PTW_16BIT;
 		/* fall through */
 	case FSL_USB2_PHY_UTMI:
+		if (pdata->controller_ver) {
+			/* controller version 1.6 or above */
+			setbits32(&p_otg->dr_mem_map->control,
+				 USB_CTRL_UTMI_PHY_EN);
+			/* Delay for UTMI PHY CLK to become stable - 10ms */
+			mdelay(FSL_UTMI_PHY_DLY);
+		}
+		setbits32(&p_otg->dr_mem_map->control, USB_CTRL_UTMI_PHY_EN);
 		temp |= PORTSC_PTS_UTMI;
 		/* fall through */
 	default:
diff --git a/drivers/usb/phy/phy-fsl-usb.h b/drivers/usb/phy/phy-fsl-usb.h
index 2314995..4a78fb3 100644
--- a/drivers/usb/phy/phy-fsl-usb.h
+++ b/drivers/usb/phy/phy-fsl-usb.h
@@ -199,6 +199,13 @@
 /* control Register Bit Masks */
 #define  USB_CTRL_IOENB			(0x1<<2)
 #define  USB_CTRL_ULPI_INT0EN		(0x1<<0)
+#define  USB_CTRL_WU_INT_EN		(0x1<<1)
+#define  USB_CTRL_LINE_STATE_FILTER__EN	(0x1<<3)
+#define  USB_CTRL_KEEP_OTG_ON		(0x1<<4)
+#define  USB_CTRL_OTG_PORT		(0x1<<5)
+#define  USB_CTRL_PLL_RESET		(0x1<<8)
+#define  USB_CTRL_UTMI_PHY_EN		(0x1<<9)
+#define  USB_CTRL_ULPI_PHY_CLK_SEL	(0x1<<10)
 
 /* BCSR5 */
 #define BCSR5_INT_USB			(0x02)
-- 
1.8.3.1


^ permalink raw reply related	[flat|nested] 15+ messages in thread
* [PATCH 1/9] usb:fsl:otg: Add controller version based ULPI and UTMI phy
@ 2015-04-07 11:58 Ramneek Mehresh
  0 siblings, 0 replies; 15+ messages in thread
From: Ramneek Mehresh @ 2015-04-07 11:58 UTC (permalink / raw)
  To: linux-kernel, linux-usb
  Cc: balbi, stern, gregkh, Ramneek Mehresh, Shengzhou Liu

Add controller version based ULPI and UTMI phy initialization for
otg driver

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
---
 drivers/usb/phy/phy-fsl-usb.c | 20 ++++++++++++++++++++
 drivers/usb/phy/phy-fsl-usb.h |  7 +++++++
 2 files changed, 27 insertions(+)

diff --git a/drivers/usb/phy/phy-fsl-usb.c b/drivers/usb/phy/phy-fsl-usb.c
index 94eb292..f90093a 100644
--- a/drivers/usb/phy/phy-fsl-usb.c
+++ b/drivers/usb/phy/phy-fsl-usb.c
@@ -923,12 +923,32 @@ int usb_otg_start(struct platform_device *pdev)
 	temp &= ~(PORTSC_PHY_TYPE_SEL | PORTSC_PTW);
 	switch (pdata->phy_mode) {
 	case FSL_USB2_PHY_ULPI:
+		if (pdata->controller_ver) {
+			/* controller version 1.6 or above */
+			setbits32(&p_otg->dr_mem_map->control,
+				USB_CTRL_ULPI_PHY_CLK_SEL);
+			/*
+			 * Due to controller issue of PHY_CLK_VALID in ULPI
+			 * mode, we set USB_CTRL_USB_EN before checking
+			 * PHY_CLK_VALID, otherwise PHY_CLK_VALID doesn't work.
+			 */
+			clrsetbits_be32(&p_otg->dr_mem_map->control,
+				 USB_CTRL_UTMI_PHY_EN, USB_CTRL_IOENB);
+		}
 		temp |= PORTSC_PTS_ULPI;
 		break;
 	case FSL_USB2_PHY_UTMI_WIDE:
 		temp |= PORTSC_PTW_16BIT;
 		/* fall through */
 	case FSL_USB2_PHY_UTMI:
+		if (pdata->controller_ver) {
+			/* controller version 1.6 or above */
+			setbits32(&p_otg->dr_mem_map->control,
+				 USB_CTRL_UTMI_PHY_EN);
+			/* Delay for UTMI PHY CLK to become stable - 10ms */
+			mdelay(FSL_UTMI_PHY_DLY);
+		}
+		setbits32(&p_otg->dr_mem_map->control, USB_CTRL_UTMI_PHY_EN);
 		temp |= PORTSC_PTS_UTMI;
 		/* fall through */
 	default:
diff --git a/drivers/usb/phy/phy-fsl-usb.h b/drivers/usb/phy/phy-fsl-usb.h
index 2314995..4a78fb3 100644
--- a/drivers/usb/phy/phy-fsl-usb.h
+++ b/drivers/usb/phy/phy-fsl-usb.h
@@ -199,6 +199,13 @@
 /* control Register Bit Masks */
 #define  USB_CTRL_IOENB			(0x1<<2)
 #define  USB_CTRL_ULPI_INT0EN		(0x1<<0)
+#define  USB_CTRL_WU_INT_EN		(0x1<<1)
+#define  USB_CTRL_LINE_STATE_FILTER__EN	(0x1<<3)
+#define  USB_CTRL_KEEP_OTG_ON		(0x1<<4)
+#define  USB_CTRL_OTG_PORT		(0x1<<5)
+#define  USB_CTRL_PLL_RESET		(0x1<<8)
+#define  USB_CTRL_UTMI_PHY_EN		(0x1<<9)
+#define  USB_CTRL_ULPI_PHY_CLK_SEL	(0x1<<10)
 
 /* BCSR5 */
 #define BCSR5_INT_USB			(0x02)
-- 
1.8.3.1


^ permalink raw reply related	[flat|nested] 15+ messages in thread
* [PATCH 1/9] usb:fsl:otg: Add controller version based ULPI and UTMI phy
@ 2015-05-05 12:43 Ramneek Mehresh
  2015-05-05 15:11 ` Felipe Balbi
  0 siblings, 1 reply; 15+ messages in thread
From: Ramneek Mehresh @ 2015-05-05 12:43 UTC (permalink / raw)
  To: linux-kernel; +Cc: balbi, stern, gregkh, Ramneek Mehresh, Shengzhou Liu

Add controller version based ULPI and UTMI phy initialization for
otg driver

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
---
 drivers/usb/phy/phy-fsl-usb.c | 20 ++++++++++++++++++++
 drivers/usb/phy/phy-fsl-usb.h |  7 +++++++
 2 files changed, 27 insertions(+)

diff --git a/drivers/usb/phy/phy-fsl-usb.c b/drivers/usb/phy/phy-fsl-usb.c
index 94eb292..f90093a 100644
--- a/drivers/usb/phy/phy-fsl-usb.c
+++ b/drivers/usb/phy/phy-fsl-usb.c
@@ -923,12 +923,32 @@ int usb_otg_start(struct platform_device *pdev)
 	temp &= ~(PORTSC_PHY_TYPE_SEL | PORTSC_PTW);
 	switch (pdata->phy_mode) {
 	case FSL_USB2_PHY_ULPI:
+		if (pdata->controller_ver) {
+			/* controller version 1.6 or above */
+			setbits32(&p_otg->dr_mem_map->control,
+				USB_CTRL_ULPI_PHY_CLK_SEL);
+			/*
+			 * Due to controller issue of PHY_CLK_VALID in ULPI
+			 * mode, we set USB_CTRL_USB_EN before checking
+			 * PHY_CLK_VALID, otherwise PHY_CLK_VALID doesn't work.
+			 */
+			clrsetbits_be32(&p_otg->dr_mem_map->control,
+				 USB_CTRL_UTMI_PHY_EN, USB_CTRL_IOENB);
+		}
 		temp |= PORTSC_PTS_ULPI;
 		break;
 	case FSL_USB2_PHY_UTMI_WIDE:
 		temp |= PORTSC_PTW_16BIT;
 		/* fall through */
 	case FSL_USB2_PHY_UTMI:
+		if (pdata->controller_ver) {
+			/* controller version 1.6 or above */
+			setbits32(&p_otg->dr_mem_map->control,
+				 USB_CTRL_UTMI_PHY_EN);
+			/* Delay for UTMI PHY CLK to become stable - 10ms */
+			mdelay(FSL_UTMI_PHY_DLY);
+		}
+		setbits32(&p_otg->dr_mem_map->control, USB_CTRL_UTMI_PHY_EN);
 		temp |= PORTSC_PTS_UTMI;
 		/* fall through */
 	default:
diff --git a/drivers/usb/phy/phy-fsl-usb.h b/drivers/usb/phy/phy-fsl-usb.h
index 2314995..4a78fb3 100644
--- a/drivers/usb/phy/phy-fsl-usb.h
+++ b/drivers/usb/phy/phy-fsl-usb.h
@@ -199,6 +199,13 @@
 /* control Register Bit Masks */
 #define  USB_CTRL_IOENB			(0x1<<2)
 #define  USB_CTRL_ULPI_INT0EN		(0x1<<0)
+#define  USB_CTRL_WU_INT_EN		(0x1<<1)
+#define  USB_CTRL_LINE_STATE_FILTER__EN	(0x1<<3)
+#define  USB_CTRL_KEEP_OTG_ON		(0x1<<4)
+#define  USB_CTRL_OTG_PORT		(0x1<<5)
+#define  USB_CTRL_PLL_RESET		(0x1<<8)
+#define  USB_CTRL_UTMI_PHY_EN		(0x1<<9)
+#define  USB_CTRL_ULPI_PHY_CLK_SEL	(0x1<<10)
 
 /* BCSR5 */
 #define BCSR5_INT_USB			(0x02)
-- 
1.8.3.1


^ permalink raw reply related	[flat|nested] 15+ messages in thread
* [PATCH 1/9] usb:fsl:otg: Add controller version based ULPI and UTMI phy
@ 2015-05-05 17:58 Ramneek Mehresh
  0 siblings, 0 replies; 15+ messages in thread
From: Ramneek Mehresh @ 2015-05-05 17:58 UTC (permalink / raw)
  To: linux-kernel
  Cc: balbi, linux-usb, stern, gregkh, Ramneek Mehresh, Shengzhou Liu

Add controller version based ULPI and UTMI phy initialization for
otg driver

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
---
 drivers/usb/phy/phy-fsl-usb.c | 20 ++++++++++++++++++++
 drivers/usb/phy/phy-fsl-usb.h |  7 +++++++
 2 files changed, 27 insertions(+)

diff --git a/drivers/usb/phy/phy-fsl-usb.c b/drivers/usb/phy/phy-fsl-usb.c
index 94eb292..f90093a 100644
--- a/drivers/usb/phy/phy-fsl-usb.c
+++ b/drivers/usb/phy/phy-fsl-usb.c
@@ -923,12 +923,32 @@ int usb_otg_start(struct platform_device *pdev)
 	temp &= ~(PORTSC_PHY_TYPE_SEL | PORTSC_PTW);
 	switch (pdata->phy_mode) {
 	case FSL_USB2_PHY_ULPI:
+		if (pdata->controller_ver) {
+			/* controller version 1.6 or above */
+			setbits32(&p_otg->dr_mem_map->control,
+				USB_CTRL_ULPI_PHY_CLK_SEL);
+			/*
+			 * Due to controller issue of PHY_CLK_VALID in ULPI
+			 * mode, we set USB_CTRL_USB_EN before checking
+			 * PHY_CLK_VALID, otherwise PHY_CLK_VALID doesn't work.
+			 */
+			clrsetbits_be32(&p_otg->dr_mem_map->control,
+				 USB_CTRL_UTMI_PHY_EN, USB_CTRL_IOENB);
+		}
 		temp |= PORTSC_PTS_ULPI;
 		break;
 	case FSL_USB2_PHY_UTMI_WIDE:
 		temp |= PORTSC_PTW_16BIT;
 		/* fall through */
 	case FSL_USB2_PHY_UTMI:
+		if (pdata->controller_ver) {
+			/* controller version 1.6 or above */
+			setbits32(&p_otg->dr_mem_map->control,
+				 USB_CTRL_UTMI_PHY_EN);
+			/* Delay for UTMI PHY CLK to become stable - 10ms */
+			mdelay(FSL_UTMI_PHY_DLY);
+		}
+		setbits32(&p_otg->dr_mem_map->control, USB_CTRL_UTMI_PHY_EN);
 		temp |= PORTSC_PTS_UTMI;
 		/* fall through */
 	default:
diff --git a/drivers/usb/phy/phy-fsl-usb.h b/drivers/usb/phy/phy-fsl-usb.h
index 2314995..4a78fb3 100644
--- a/drivers/usb/phy/phy-fsl-usb.h
+++ b/drivers/usb/phy/phy-fsl-usb.h
@@ -199,6 +199,13 @@
 /* control Register Bit Masks */
 #define  USB_CTRL_IOENB			(0x1<<2)
 #define  USB_CTRL_ULPI_INT0EN		(0x1<<0)
+#define  USB_CTRL_WU_INT_EN		(0x1<<1)
+#define  USB_CTRL_LINE_STATE_FILTER__EN	(0x1<<3)
+#define  USB_CTRL_KEEP_OTG_ON		(0x1<<4)
+#define  USB_CTRL_OTG_PORT		(0x1<<5)
+#define  USB_CTRL_PLL_RESET		(0x1<<8)
+#define  USB_CTRL_UTMI_PHY_EN		(0x1<<9)
+#define  USB_CTRL_ULPI_PHY_CLK_SEL	(0x1<<10)
 
 /* BCSR5 */
 #define BCSR5_INT_USB			(0x02)
-- 
1.8.3.1


^ permalink raw reply related	[flat|nested] 15+ messages in thread

end of thread, other threads:[~2015-05-05 17:48 UTC | newest]

Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-03-26 15:17 [PATCH 1/9] usb:fsl:otg: Add controller version based ULPI and UTMI phy Ramneek Mehresh
2015-03-26 15:17 ` [PATCH 2/9][v2]usb:fsl:otg: Add support to add/remove usb host driver Ramneek Mehresh
2015-03-26 15:17 ` [PATCH 3/9] usb:fsl:otg: Signal host drv when host is otg Ramneek Mehresh
2015-03-26 15:17 ` [PATCH 4/9] usb:fsl:otg: Modify otg_event to start host drv Ramneek Mehresh
2015-03-26 15:17 ` [PATCH 5/9] usb:fsl:otg: Combine host/gadget start/resume for ID change Ramneek Mehresh
2015-03-26 15:17 ` [PATCH 6/9] usb:fsl:otg: Remove host drv upon otg bring-up Ramneek Mehresh
2015-03-26 15:17 ` [PATCH 7/9] usb:fsl:otg: Add host-gadget drv sync delay Ramneek Mehresh
2015-03-26 15:17 ` [PATCH 8/9] usb:fsl:otg: Resolve OTG crash issue with another host Ramneek Mehresh
2015-03-26 15:17 ` [PATCH 9/9] usb:fsl:otg: Make fsl otg driver as tristate Ramneek Mehresh
2015-03-26 17:10 ` [PATCH 1/9] usb:fsl:otg: Add controller version based ULPI and UTMI phy Felipe Balbi
2015-04-07 11:58 Ramneek Mehresh
2015-05-05 12:43 Ramneek Mehresh
2015-05-05 15:11 ` Felipe Balbi
2015-05-05 17:48   ` Ramneek Mehresh
2015-05-05 17:58 Ramneek Mehresh

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