[PATCH] drm/i915: Pin tiled objects for L-shaped configs

[PATCH] drm/i915: Pin tiled objects for L-shaped configs

[Daniel Vetter]

Let's just throw in the towel on this one and take the cheap way out.

Based on a patch from Chris Wilson, but checking for a different bit.
Chris' patch checked for even bank layout, this one here for a magic
bit. Given the evidence we've gathered (not much) both work I think,
but checking for the magic bit might be more accurate.

Anyway, works on my gm45 here.

For paranoi restrict to gen4 (and mobile), since we've only ever seen
this on gm45 and i965gm.

Also add some debugfs output so that we can skip the tiled swapping
tests properly in these cases.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=28813
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=45092
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c    |  6 ++++++
 drivers/gpu/drm/i915/i915_drv.h        |  1 +
 drivers/gpu/drm/i915/i915_gem.c        | 14 ++++++++++++++
 drivers/gpu/drm/i915/i915_gem_tiling.c | 18 ++++++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h        |  2 ++
 5 files changed, 41 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 0a6981399642..a43124e4a77b 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1975,6 +1975,8 @@ static int i915_swizzle_info(struct seq_file *m, void *data)
 	if (IS_GEN3(dev) || IS_GEN4(dev)) {
 		seq_printf(m, "DDC = 0x%08x\n",
 			   I915_READ(DCC));
+		seq_printf(m, "DDC2 = 0x%08x\n",
+			   I915_READ(DCC2));
 		seq_printf(m, "C0DRB3 = 0x%04x\n",
 			   I915_READ16(C0DRB3));
 		seq_printf(m, "C1DRB3 = 0x%04x\n",
@@ -1997,6 +1999,10 @@ static int i915_swizzle_info(struct seq_file *m, void *data)
 		seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
 			   I915_READ(DISP_ARB_CTL));
 	}
+
+	if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
+		seq_puts(m, "L-shaped memory detected\n");
+
 	intel_runtime_pm_put(dev_priv);
 	mutex_unlock(&dev->struct_mutex);
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 54691bcf1822..d5accc481082 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -747,6 +747,7 @@ enum intel_sbi_destination {
 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
 #define QUIRK_PIPEB_FORCE (1<<4)
+#define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
 
 struct intel_fbdev;
 struct intel_fbc_work;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 1de94cc63517..196ebd07d118 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2120,6 +2120,10 @@ i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
 	if (i915_gem_object_needs_bit17_swizzle(obj))
 		i915_gem_object_do_bit_17_swizzle(obj);
 
+	if (obj->tiling_mode != I915_TILING_NONE &&
+	    dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
+		i915_gem_object_pin_pages(obj);
+
 	return 0;
 
 err_pages:
@@ -4300,6 +4304,7 @@ int
 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
 		       struct drm_file *file_priv)
 {
+	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_i915_gem_madvise *args = data;
 	struct drm_i915_gem_object *obj;
 	int ret;
@@ -4327,6 +4332,15 @@ i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
 		goto out;
 	}
 
+	if (obj->pages &&
+	    obj->tiling_mode != I915_TILING_NONE &&
+	    dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
+		if (obj->madv == I915_MADV_WILLNEED)
+			i915_gem_object_unpin_pages(obj);
+		if (args->madv == I915_MADV_WILLNEED)
+			i915_gem_object_pin_pages(obj);
+	}
+
 	if (obj->madv != __I915_MADV_PURGED)
 		obj->madv = args->madv;
 
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index 749ab485569e..03c675a4476e 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -178,6 +178,15 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
 			}
 			break;
 		}
+
+		/* check for L-shaped memory aka modified enhanced addressing */
+		if (IS_GEN4(dev)) {
+			uint32_t ddc2 = I915_READ(DCC2);
+
+			if (!(ddc2 & DCC2_MODIFIED_ENHANCED_DISABLE))
+				dev_priv->quirks |= QUIRK_PIN_SWIZZLED_PAGES;
+		}
+
 		if (dcc == 0xffffffff) {
 			DRM_ERROR("Couldn't read from MCHBAR.  "
 				  "Disabling tiling.\n");
@@ -393,6 +402,15 @@ i915_gem_set_tiling(struct drm_device *dev, void *data,
 		}
 
 		if (ret == 0) {
+			if (obj->pages &&
+			    obj->madv == I915_MADV_WILLNEED &&
+			    dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
+				if (args->tiling_mode == I915_TILING_NONE)
+					i915_gem_object_unpin_pages(obj);
+				if (obj->tiling_mode == I915_TILING_NONE)
+					i915_gem_object_pin_pages(obj);
+			}
+
 			obj->fence_dirty =
 				obj->last_fenced_seqno ||
 				obj->fence_reg != I915_FENCE_REG_NONE;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f32c624ba9f9..1f651d7487e1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2030,6 +2030,8 @@ enum punit_power_well {
 #define DCC_ADDRESSING_MODE_MASK			(3 << 0)
 #define DCC_CHANNEL_XOR_DISABLE				(1 << 10)
 #define DCC_CHANNEL_XOR_BIT_17				(1 << 9)
+#define DCC2			0x10204
+#define DCC2_MODIFIED_ENHANCED_DISABLE			(1 << 20)
 
 /* Pineview MCH register contains DDR3 setting */
 #define CSHRDDR3CTL            0x101a8
-- 
1.8.4.rc3

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Re: [PATCH] drm/i915: Pin tiled objects for L-shaped configs

[Chris Wilson]

On Tue, Nov 18, 2014 at 02:41:22PM +0100, Daniel Vetter wrote:
>  struct intel_fbdev;
>  struct intel_fbc_work;
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 1de94cc63517..196ebd07d118 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -2120,6 +2120,10 @@ i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
>  	if (i915_gem_object_needs_bit17_swizzle(obj))
>  		i915_gem_object_do_bit_17_swizzle(obj);
>  
> +	if (obj->tiling_mode != I915_TILING_NONE &&
> +	    dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
> +		i915_gem_object_pin_pages(obj);

Note that we have a WARN_ON(obj->pages_pin_count) in
i915_gem_free_object() now.

if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
  obj->pages_pin_count = 0;

or we could just throw away the WARN_ON().
-Chris

-- 
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Re: [PATCH] drm/i915: Pin tiled objects for L-shaped configs

[Daniel Vetter]

On Tue, Nov 18, 2014 at 02:01:37PM +0000, Chris Wilson wrote:
> On Tue, Nov 18, 2014 at 02:41:22PM +0100, Daniel Vetter wrote:
> >  struct intel_fbdev;
> >  struct intel_fbc_work;
> > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> > index 1de94cc63517..196ebd07d118 100644
> > --- a/drivers/gpu/drm/i915/i915_gem.c
> > +++ b/drivers/gpu/drm/i915/i915_gem.c
> > @@ -2120,6 +2120,10 @@ i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
> >  	if (i915_gem_object_needs_bit17_swizzle(obj))
> >  		i915_gem_object_do_bit_17_swizzle(obj);
> >  
> > +	if (obj->tiling_mode != I915_TILING_NONE &&
> > +	    dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
> > +		i915_gem_object_pin_pages(obj);
> 
> Note that we have a WARN_ON(obj->pages_pin_count) in
> i915_gem_free_object() now.
> 
> if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
>   obj->pages_pin_count = 0;
> 
> or we could just throw away the WARN_ON().

Shame on me for not noticing that. I think I'll just drop the pinning for
tiled objects manually, that way we can keep the WARN_ON. Given all the
tricks being pulled with pin refcounts I think that check is useful.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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[PATCH] drm/i915: Pin tiled objects for L-shaped configs

[Daniel Vetter]

Let's just throw in the towel on this one and take the cheap way out.

Based on a patch from Chris Wilson, but checking for a different bit.
Chris' patch checked for even bank layout, this one here for a magic
bit. Given the evidence we've gathered (not much) both work I think,
but checking for the magic bit might be more accurate.

Anyway, works on my gm45 here.

For paranoi restrict to gen4 (and mobile), since we've only ever seen
this on gm45 and i965gm.

Also add some debugfs output so that we can skip the tiled swapping
tests properly in these cases.

v2: Clean up the quirk'ed pin count in free_object to avoid upsetting
the WARN_ON. Spotted by Chris.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=28813
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=45092
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c    |  6 ++++++
 drivers/gpu/drm/i915/i915_drv.h        |  1 +
 drivers/gpu/drm/i915/i915_gem.c        | 19 +++++++++++++++++++
 drivers/gpu/drm/i915/i915_gem_tiling.c | 18 ++++++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h        |  2 ++
 5 files changed, 46 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 0a6981399642..a43124e4a77b 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1975,6 +1975,8 @@ static int i915_swizzle_info(struct seq_file *m, void *data)
 	if (IS_GEN3(dev) || IS_GEN4(dev)) {
 		seq_printf(m, "DDC = 0x%08x\n",
 			   I915_READ(DCC));
+		seq_printf(m, "DDC2 = 0x%08x\n",
+			   I915_READ(DCC2));
 		seq_printf(m, "C0DRB3 = 0x%04x\n",
 			   I915_READ16(C0DRB3));
 		seq_printf(m, "C1DRB3 = 0x%04x\n",
@@ -1997,6 +1999,10 @@ static int i915_swizzle_info(struct seq_file *m, void *data)
 		seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
 			   I915_READ(DISP_ARB_CTL));
 	}
+
+	if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
+		seq_puts(m, "L-shaped memory detected\n");
+
 	intel_runtime_pm_put(dev_priv);
 	mutex_unlock(&dev->struct_mutex);
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 54691bcf1822..d5accc481082 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -747,6 +747,7 @@ enum intel_sbi_destination {
 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
 #define QUIRK_PIPEB_FORCE (1<<4)
+#define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
 
 struct intel_fbdev;
 struct intel_fbc_work;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 1de94cc63517..8d04e0979d0a 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2120,6 +2120,10 @@ i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
 	if (i915_gem_object_needs_bit17_swizzle(obj))
 		i915_gem_object_do_bit_17_swizzle(obj);
 
+	if (obj->tiling_mode != I915_TILING_NONE &&
+	    dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
+		i915_gem_object_pin_pages(obj);
+
 	return 0;
 
 err_pages:
@@ -4300,6 +4304,7 @@ int
 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
 		       struct drm_file *file_priv)
 {
+	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_i915_gem_madvise *args = data;
 	struct drm_i915_gem_object *obj;
 	int ret;
@@ -4327,6 +4332,15 @@ i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
 		goto out;
 	}
 
+	if (obj->pages &&
+	    obj->tiling_mode != I915_TILING_NONE &&
+	    dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
+		if (obj->madv == I915_MADV_WILLNEED)
+			i915_gem_object_unpin_pages(obj);
+		if (args->madv == I915_MADV_WILLNEED)
+			i915_gem_object_pin_pages(obj);
+	}
+
 	if (obj->madv != __I915_MADV_PURGED)
 		obj->madv = args->madv;
 
@@ -4478,6 +4492,11 @@ void i915_gem_free_object(struct drm_gem_object *gem_obj)
 
 	WARN_ON(obj->frontbuffer_bits);
 
+	if (obj->pages && obj->madv == I915_MADV_WILLNEED &&
+	    dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES &&
+	    obj->tiling_mode != I915_TILING_NONE)
+		i915_gem_object_unpin_pages(obj);
+
 	if (WARN_ON(obj->pages_pin_count))
 		obj->pages_pin_count = 0;
 	if (discard_backing_storage(obj))
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index 749ab485569e..03c675a4476e 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -178,6 +178,15 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
 			}
 			break;
 		}
+
+		/* check for L-shaped memory aka modified enhanced addressing */
+		if (IS_GEN4(dev)) {
+			uint32_t ddc2 = I915_READ(DCC2);
+
+			if (!(ddc2 & DCC2_MODIFIED_ENHANCED_DISABLE))
+				dev_priv->quirks |= QUIRK_PIN_SWIZZLED_PAGES;
+		}
+
 		if (dcc == 0xffffffff) {
 			DRM_ERROR("Couldn't read from MCHBAR.  "
 				  "Disabling tiling.\n");
@@ -393,6 +402,15 @@ i915_gem_set_tiling(struct drm_device *dev, void *data,
 		}
 
 		if (ret == 0) {
+			if (obj->pages &&
+			    obj->madv == I915_MADV_WILLNEED &&
+			    dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
+				if (args->tiling_mode == I915_TILING_NONE)
+					i915_gem_object_unpin_pages(obj);
+				if (obj->tiling_mode == I915_TILING_NONE)
+					i915_gem_object_pin_pages(obj);
+			}
+
 			obj->fence_dirty =
 				obj->last_fenced_seqno ||
 				obj->fence_reg != I915_FENCE_REG_NONE;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f32c624ba9f9..1f651d7487e1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2030,6 +2030,8 @@ enum punit_power_well {
 #define DCC_ADDRESSING_MODE_MASK			(3 << 0)
 #define DCC_CHANNEL_XOR_DISABLE				(1 << 10)
 #define DCC_CHANNEL_XOR_BIT_17				(1 << 9)
+#define DCC2			0x10204
+#define DCC2_MODIFIED_ENHANCED_DISABLE			(1 << 20)
 
 /* Pineview MCH register contains DDR3 setting */
 #define CSHRDDR3CTL            0x101a8
-- 
1.8.4.rc3

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Re: [PATCH] drm/i915: Pin tiled objects for L-shaped configs

[Chris Wilson]

On Thu, Nov 20, 2014 at 09:26:30AM +0100, Daniel Vetter wrote:
> Let's just throw in the towel on this one and take the cheap way out.
> 
> Based on a patch from Chris Wilson, but checking for a different bit.
> Chris' patch checked for even bank layout, this one here for a magic
> bit. Given the evidence we've gathered (not much) both work I think,
> but checking for the magic bit might be more accurate.
> 
> Anyway, works on my gm45 here.
> 
> For paranoi restrict to gen4 (and mobile), since we've only ever seen
> this on gm45 and i965gm.
> 
> Also add some debugfs output so that we can skip the tiled swapping
> tests properly in these cases.
> 
> v2: Clean up the quirk'ed pin count in free_object to avoid upsetting
> the WARN_ON. Spotted by Chris.
> 
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=28813
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=45092
> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>

I want to complain about the nearly duplicated repeated checks, but I
failed to rewrite them compactly. :|

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

Oh, one more request: can I haz decoded quirks in the error state?
-Chris

-- 
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Re: [PATCH] drm/i915: Pin tiled objects for L-shaped configs

[Daniel Vetter]

On Thu, Nov 20, 2014 at 08:37:36AM +0000, Chris Wilson wrote:
> On Thu, Nov 20, 2014 at 09:26:30AM +0100, Daniel Vetter wrote:
> > Let's just throw in the towel on this one and take the cheap way out.
> > 
> > Based on a patch from Chris Wilson, but checking for a different bit.
> > Chris' patch checked for even bank layout, this one here for a magic
> > bit. Given the evidence we've gathered (not much) both work I think,
> > but checking for the magic bit might be more accurate.
> > 
> > Anyway, works on my gm45 here.
> > 
> > For paranoi restrict to gen4 (and mobile), since we've only ever seen
> > this on gm45 and i965gm.
> > 
> > Also add some debugfs output so that we can skip the tiled swapping
> > tests properly in these cases.
> > 
> > v2: Clean up the quirk'ed pin count in free_object to avoid upsetting
> > the WARN_ON. Spotted by Chris.
> > 
> > Cc: Chris Wilson <chris@chris-wilson.co.uk>
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=28813
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=45092
> > Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
> 
> I want to complain about the nearly duplicated repeated checks, but I
> failed to rewrite them compactly. :|
> 
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

Queued for -next, thanks for the review.

> Oh, one more request: can I haz decoded quirks in the error state?

Hm, I haven't ever yet wanted to see them. Not even sure whether this
might be useful here really ...
-Daniel
-- 
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Software Engineer, Intel Corporation
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Re: [PATCH] drm/i915: Pin tiled objects for L-shaped configs

[Chris Wilson]

On Thu, Nov 20, 2014 at 10:22:42AM +0100, Daniel Vetter wrote:
> On Thu, Nov 20, 2014 at 08:37:36AM +0000, Chris Wilson wrote:
> > Oh, one more request: can I haz decoded quirks in the error state?
> 
> Hm, I haven't ever yet wanted to see them. Not even sure whether this
> might be useful here really ...

Here, I think just logging obj->pages_pin_count would answer some
worries. At the moment our quirks concern interaction with the display
hardware (backlight, PIPEA, ssc), if we start adding more that are
focused on memory management or GPU interaction, then we will went to
see the quirk list.

Thinking of which, there are quite a few cache/execution mode registers
we should be dumping upon error.
-Chris

-- 
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Re: [PATCH] drm/i915: Pin tiled objects for L-shaped configs

[Chris Wilson]

On Thu, Nov 20, 2014 at 09:26:30AM +0100, Daniel Vetter wrote:
> diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
> index 749ab485569e..03c675a4476e 100644
> --- a/drivers/gpu/drm/i915/i915_gem_tiling.c
> +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
> @@ -178,6 +178,15 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
>  			}
>  			break;
>  		}
> +
> +		/* check for L-shaped memory aka modified enhanced addressing */
> +		if (IS_GEN4(dev)) {
> +			uint32_t ddc2 = I915_READ(DCC2);
> +
> +			if (!(ddc2 & DCC2_MODIFIED_ENHANCED_DISABLE))
> +				dev_priv->quirks |= QUIRK_PIN_SWIZZLED_PAGES;
> +		}
> +
>  		if (dcc == 0xffffffff) {
>  			DRM_ERROR("Couldn't read from MCHBAR.  "
>  				  "Disabling tiling.\n");

I resurrected my dual-channel evenly loaded gm45 and to my surprise
found it reporting a L-shaped memory layout.

Perhaps the if ((ddc2 & DISABLE) == 0) is inverted or is not the truly
magic bit?

ickle@x200s $ sudo cat /sys/kernel/debug/dri/0/i915_swizzle_info
bit6 swizzle for X-tiling = bit9/bit10/bit11
bit6 swizzle for Y-tiling = bit9/bit11
DDC = 0x000f0002
DDC2 = 0x00000010
C0DRB3 = 0x0000
C1DRB3 = 0x0000
L-shaped memory detected
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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Re: [PATCH] drm/i915: Pin tiled objects for L-shaped configs

[Daniel Vetter]

On Fri, Apr 03, 2015 at 10:43:29AM +0100, Chris Wilson wrote:
> On Thu, Nov 20, 2014 at 09:26:30AM +0100, Daniel Vetter wrote:
> > diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
> > index 749ab485569e..03c675a4476e 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_tiling.c
> > +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
> > @@ -178,6 +178,15 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
> >  			}
> >  			break;
> >  		}
> > +
> > +		/* check for L-shaped memory aka modified enhanced addressing */
> > +		if (IS_GEN4(dev)) {
> > +			uint32_t ddc2 = I915_READ(DCC2);
> > +
> > +			if (!(ddc2 & DCC2_MODIFIED_ENHANCED_DISABLE))
> > +				dev_priv->quirks |= QUIRK_PIN_SWIZZLED_PAGES;
> > +		}
> > +
> >  		if (dcc == 0xffffffff) {
> >  			DRM_ERROR("Couldn't read from MCHBAR.  "
> >  				  "Disabling tiling.\n");
> 
> I resurrected my dual-channel evenly loaded gm45 and to my surprise
> found it reporting a L-shaped memory layout.

Well my gm45 is also dual-channel and evenly loaded and still mangles
tiled buffers when going through swap. Is gem_tiled_swapping happy on your
box?

> Perhaps the if ((ddc2 & DISABLE) == 0) is inverted or is not the truly
> magic bit?

It was the best one I could find - given how old this all is now I think
some false positives are acceptable in the test. I did try a few other
things which did all fail.
-Daniel
 
> ickle@x200s $ sudo cat /sys/kernel/debug/dri/0/i915_swizzle_info
> bit6 swizzle for X-tiling = bit9/bit10/bit11
> bit6 swizzle for Y-tiling = bit9/bit11
> DDC = 0x000f0002
> DDC2 = 0x00000010
> C0DRB3 = 0x0000
> C1DRB3 = 0x0000
> L-shaped memory detected
> -Chris
> 
> -- 
> Chris Wilson, Intel Open Source Technology Centre

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH] drm/i915: Pin tiled objects for L-shaped configs

[Chris Wilson]

On Tue, Apr 07, 2015 at 10:05:39AM +0200, Daniel Vetter wrote:
> On Fri, Apr 03, 2015 at 10:43:29AM +0100, Chris Wilson wrote:
> > I resurrected my dual-channel evenly loaded gm45 and to my surprise
> > found it reporting a L-shaped memory layout.
> 
> Well my gm45 is also dual-channel and evenly loaded and still mangles
> tiled buffers when going through swap. Is gem_tiled_swapping happy on your
> box?

ickle@x200s ~/intel-gpu-tools/tests $ sudo ./gem_tiled_swapping 
IGT-Version: 1.10-ge809895 (x86_64) (Linux: 4.0.0-rc6+ x86_64)
Using 640 1MiB objects (available RAM: 343/3847, swap: 3989)
Subtest non-threaded: SUCCESS (23.344s)
Subtest threaded: SUCCESS (110.801s)

> > Perhaps the if ((ddc2 & DISABLE) == 0) is inverted or is not the truly
> > magic bit?
> 
> It was the best one I could find - given how old this all is now I think
> some false positives are acceptable in the test. I did try a few other
> things which did all fail.

It's the false-negative I worry about. I am just worried this is not the
bit we are looking for. Time will tell if we get a new bug report with
broken swizzling after swapping.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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