[U-Boot] [PATCH v4 00/24] spi: Use BIT and GENMASK

[U-Boot] [PATCH v4 00/24] spi: Use BIT and GENMASK

[Jagan Teki]

This series replaces numerical bit shitfts and mask values
with BIT and GENMASK macro's

Changes for v4:
- Patch split for individual drivers.
Changes for v3, v2:
- none

Jagan Teki (24):
  spi: zynq_[q]spi: Use BIT macro
  spi: zynq_[q]spi: Use GENMASK macro
  spi: altera_spi: Use BIT macro
  spi: atmel_spi: Use BIT macro
  spi: bfin_spi6xx: Use BIT macro
  spi: cadence_qspi_apb: Use BIT macro
  spi: designware_spi: Use BIT macro
  spi: exynos_spi: Use BIT macro
  spi: fsl: Use BIT macro
  spi: ich: Use BIT macro
  spi: mpc8xxx_spi: Use BIT macro
  spi: omap3_spi: Use BIT macro
  spi: sh_qspi: Use BIT macro
  spi: tegra: Use BIT macro
  spi: ti_qspi: Use BIT macro
  spi: xilinx_spi: Use BIT macro
  spi: atmel_spi: Use GENMASK
  spi: cadence_qspi_apb: Use GENMASK
  spi: designware_spi: Use GENMASK
  spi: fsl_qspi: Use GENMASK
  spi: mxs_spi: Use GENMASK
  spi: omap3_spi: Use GENMASK
  spi: tegra: Use GENMASK
  spi: xilinx_spi: Use GENMASK

 drivers/spi/altera_spi.c       | 26 +++++++--------
 drivers/spi/atmel_spi.h        | 54 +++++++++++++++---------------
 drivers/spi/bfin_spi6xx.c      |  8 ++---
 drivers/spi/cadence_qspi_apb.c | 76 +++++++++++++++++++++---------------------
 drivers/spi/designware_spi.c   | 16 ++++-----
 drivers/spi/exynos_spi.c       |  4 +--
 drivers/spi/fsl_dspi.c         |  2 +-
 drivers/spi/fsl_espi.c         | 20 +++++------
 drivers/spi/fsl_qspi.c         |  6 ++--
 drivers/spi/ich.c              |  4 +--
 drivers/spi/mpc8xxx_spi.c      |  2 +-
 drivers/spi/mxs_spi.c          |  2 +-
 drivers/spi/omap3_spi.h        | 64 +++++++++++++++++------------------
 drivers/spi/sh_qspi.c          | 16 ++++-----
 drivers/spi/tegra114_spi.c     | 76 +++++++++++++++++++++---------------------
 drivers/spi/tegra20_sflash.c   | 54 +++++++++++++++---------------
 drivers/spi/tegra20_slink.c    | 62 +++++++++++++++++-----------------
 drivers/spi/ti_qspi.c          | 10 +++---
 drivers/spi/xilinx_spi.c       | 46 ++++++++++++-------------
 drivers/spi/zynq_qspi.c        | 28 ++++++++--------
 drivers/spi/zynq_spi.c         | 22 ++++++------
 21 files changed, 299 insertions(+), 299 deletions(-)

-- 
1.9.1

[U-Boot] [PATCH v4 01/24] spi: zynq_[q]spi: Use BIT macro

[Jagan Teki]

Used BIT macro on zynq_spi.c and zynq_qspi.c

:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31

Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
---
 drivers/spi/zynq_qspi.c | 20 ++++++++++----------
 drivers/spi/zynq_spi.c  | 16 ++++++++--------
 2 files changed, 18 insertions(+), 18 deletions(-)

diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c
index 8aa61d7..dd530a1 100644
--- a/drivers/spi/zynq_qspi.c
+++ b/drivers/spi/zynq_qspi.c
@@ -16,20 +16,20 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /* zynq qspi register bit masks ZYNQ_QSPI_<REG>_<BIT>_MASK */
-#define ZYNQ_QSPI_CR_IFMODE_MASK	(1 << 31)	/* Flash intrface mode*/
-#define ZYNQ_QSPI_CR_MSA_MASK		(1 << 15)	/* Manual start enb */
-#define ZYNQ_QSPI_CR_MCS_MASK		(1 << 14)	/* Manual chip select */
-#define ZYNQ_QSPI_CR_PCS_MASK		(1 << 10)	/* Peri chip select */
+#define ZYNQ_QSPI_CR_IFMODE_MASK	BIT(31)	/* Flash intrface mode*/
+#define ZYNQ_QSPI_CR_MSA_MASK		BIT(15)	/* Manual start enb */
+#define ZYNQ_QSPI_CR_MCS_MASK		BIT(14)	/* Manual chip select */
+#define ZYNQ_QSPI_CR_PCS_MASK		BIT(10)	/* Peri chip select */
 #define ZYNQ_QSPI_CR_FW_MASK		(0x3 << 6)	/* FIFO width */
 #define ZYNQ_QSPI_CR_SS_MASK		(0xF << 10)	/* Slave Select */
 #define ZYNQ_QSPI_CR_BAUD_MASK		(0x7 << 3)	/* Baud rate div */
-#define ZYNQ_QSPI_CR_CPHA_MASK		(1 << 2)	/* Clock phase */
-#define ZYNQ_QSPI_CR_CPOL_MASK		(1 << 1)	/* Clock polarity */
-#define ZYNQ_QSPI_CR_MSTREN_MASK	(1 << 0)	/* Mode select */
-#define ZYNQ_QSPI_IXR_RXNEMPTY_MASK	(1 << 4)	/* RX_FIFO_not_empty */
-#define ZYNQ_QSPI_IXR_TXOW_MASK		(1 << 2)	/* TX_FIFO_not_full */
+#define ZYNQ_QSPI_CR_CPHA_MASK		BIT(2)	/* Clock phase */
+#define ZYNQ_QSPI_CR_CPOL_MASK		BIT(1)	/* Clock polarity */
+#define ZYNQ_QSPI_CR_MSTREN_MASK	BIT(0)	/* Mode select */
+#define ZYNQ_QSPI_IXR_RXNEMPTY_MASK	BIT(4)	/* RX_FIFO_not_empty */
+#define ZYNQ_QSPI_IXR_TXOW_MASK		BIT(2)	/* TX_FIFO_not_full */
 #define ZYNQ_QSPI_IXR_ALL_MASK		0x7F		/* All IXR bits */
-#define ZYNQ_QSPI_ENR_SPI_EN_MASK	(1 << 0)	/* SPI Enable */
+#define ZYNQ_QSPI_ENR_SPI_EN_MASK	BIT(0)	/* SPI Enable */
 
 /* zynq qspi Transmit Data Register */
 #define ZYNQ_QSPI_TXD_00_00_OFFSET	0x1C	/* Transmit 4-byte inst */
diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c
index 65a9633..92e5712 100644
--- a/drivers/spi/zynq_spi.c
+++ b/drivers/spi/zynq_spi.c
@@ -20,17 +20,17 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /* zynq spi register bit masks ZYNQ_SPI_<REG>_<BIT>_MASK */
-#define ZYNQ_SPI_CR_MSA_MASK		(1 << 15)	/* Manual start enb */
-#define ZYNQ_SPI_CR_MCS_MASK		(1 << 14)	/* Manual chip select */
+#define ZYNQ_SPI_CR_MSA_MASK		BIT(15)	/* Manual start enb */
+#define ZYNQ_SPI_CR_MCS_MASK		BIT(14)	/* Manual chip select */
 #define ZYNQ_SPI_CR_CS_MASK		(0xF << 10)	/* Chip select */
 #define ZYNQ_SPI_CR_BAUD_MASK		(0x7 << 3)	/* Baud rate div */
-#define ZYNQ_SPI_CR_CPHA_MASK		(1 << 2)	/* Clock phase */
-#define ZYNQ_SPI_CR_CPOL_MASK		(1 << 1)	/* Clock polarity */
-#define ZYNQ_SPI_CR_MSTREN_MASK		(1 << 0)	/* Mode select */
-#define ZYNQ_SPI_IXR_RXNEMPTY_MASK	(1 << 4)	/* RX_FIFO_not_empty */
-#define ZYNQ_SPI_IXR_TXOW_MASK		(1 << 2)	/* TX_FIFO_not_full */
+#define ZYNQ_SPI_CR_CPHA_MASK		BIT(2)	/* Clock phase */
+#define ZYNQ_SPI_CR_CPOL_MASK		BIT(1)	/* Clock polarity */
+#define ZYNQ_SPI_CR_MSTREN_MASK		BIT(0)	/* Mode select */
+#define ZYNQ_SPI_IXR_RXNEMPTY_MASK	BIT(4)	/* RX_FIFO_not_empty */
+#define ZYNQ_SPI_IXR_TXOW_MASK		BIT(2)	/* TX_FIFO_not_full */
 #define ZYNQ_SPI_IXR_ALL_MASK		0x7F		/* All IXR bits */
-#define ZYNQ_SPI_ENR_SPI_EN_MASK	(1 << 0)	/* SPI Enable */
+#define ZYNQ_SPI_ENR_SPI_EN_MASK	BIT(0)	/* SPI Enable */
 
 #define ZYNQ_SPI_CR_BAUD_MAX		8	/* Baud rate divisor max val */
 #define ZYNQ_SPI_CR_BAUD_SHIFT		3	/* Baud rate divisor shift */
-- 
1.9.1

[U-Boot] [PATCH v4 02/24] spi: zynq_[q]spi: Use GENMASK macro

[Jagan Teki]

GENMASK macro used on zynq_spi.c and zynq_qspi.c

GENMASK is used to create a contiguous bitmask([hi:lo]).
Ex: (0x7 << 3) => GENMASK(5, 3)

Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
---
 drivers/spi/zynq_qspi.c | 8 ++++----
 drivers/spi/zynq_spi.c  | 6 +++---
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c
index dd530a1..64b4eea 100644
--- a/drivers/spi/zynq_qspi.c
+++ b/drivers/spi/zynq_qspi.c
@@ -20,15 +20,15 @@ DECLARE_GLOBAL_DATA_PTR;
 #define ZYNQ_QSPI_CR_MSA_MASK		BIT(15)	/* Manual start enb */
 #define ZYNQ_QSPI_CR_MCS_MASK		BIT(14)	/* Manual chip select */
 #define ZYNQ_QSPI_CR_PCS_MASK		BIT(10)	/* Peri chip select */
-#define ZYNQ_QSPI_CR_FW_MASK		(0x3 << 6)	/* FIFO width */
-#define ZYNQ_QSPI_CR_SS_MASK		(0xF << 10)	/* Slave Select */
-#define ZYNQ_QSPI_CR_BAUD_MASK		(0x7 << 3)	/* Baud rate div */
+#define ZYNQ_QSPI_CR_FW_MASK		GENMASK(7, 6)	/* FIFO width */
+#define ZYNQ_QSPI_CR_SS_MASK		GENMASK(13, 10)	/* Slave Select */
+#define ZYNQ_QSPI_CR_BAUD_MASK		GENMASK(5, 3)	/* Baud rate div */
 #define ZYNQ_QSPI_CR_CPHA_MASK		BIT(2)	/* Clock phase */
 #define ZYNQ_QSPI_CR_CPOL_MASK		BIT(1)	/* Clock polarity */
 #define ZYNQ_QSPI_CR_MSTREN_MASK	BIT(0)	/* Mode select */
 #define ZYNQ_QSPI_IXR_RXNEMPTY_MASK	BIT(4)	/* RX_FIFO_not_empty */
 #define ZYNQ_QSPI_IXR_TXOW_MASK		BIT(2)	/* TX_FIFO_not_full */
-#define ZYNQ_QSPI_IXR_ALL_MASK		0x7F		/* All IXR bits */
+#define ZYNQ_QSPI_IXR_ALL_MASK		GENMASK(6, 0)	/* All IXR bits */
 #define ZYNQ_QSPI_ENR_SPI_EN_MASK	BIT(0)	/* SPI Enable */
 
 /* zynq qspi Transmit Data Register */
diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c
index 92e5712..9ede099 100644
--- a/drivers/spi/zynq_spi.c
+++ b/drivers/spi/zynq_spi.c
@@ -22,14 +22,14 @@ DECLARE_GLOBAL_DATA_PTR;
 /* zynq spi register bit masks ZYNQ_SPI_<REG>_<BIT>_MASK */
 #define ZYNQ_SPI_CR_MSA_MASK		BIT(15)	/* Manual start enb */
 #define ZYNQ_SPI_CR_MCS_MASK		BIT(14)	/* Manual chip select */
-#define ZYNQ_SPI_CR_CS_MASK		(0xF << 10)	/* Chip select */
-#define ZYNQ_SPI_CR_BAUD_MASK		(0x7 << 3)	/* Baud rate div */
+#define ZYNQ_SPI_CR_CS_MASK		GENMASK(13, 10)	/* Chip select */
+#define ZYNQ_SPI_CR_BAUD_MASK		GENMASK(5, 3)	/* Baud rate div */
 #define ZYNQ_SPI_CR_CPHA_MASK		BIT(2)	/* Clock phase */
 #define ZYNQ_SPI_CR_CPOL_MASK		BIT(1)	/* Clock polarity */
 #define ZYNQ_SPI_CR_MSTREN_MASK		BIT(0)	/* Mode select */
 #define ZYNQ_SPI_IXR_RXNEMPTY_MASK	BIT(4)	/* RX_FIFO_not_empty */
 #define ZYNQ_SPI_IXR_TXOW_MASK		BIT(2)	/* TX_FIFO_not_full */
-#define ZYNQ_SPI_IXR_ALL_MASK		0x7F		/* All IXR bits */
+#define ZYNQ_SPI_IXR_ALL_MASK		GENMASK(6, 0)	/* All IXR bits */
 #define ZYNQ_SPI_ENR_SPI_EN_MASK	BIT(0)	/* SPI Enable */
 
 #define ZYNQ_SPI_CR_BAUD_MAX		8	/* Baud rate divisor max val */
-- 
1.9.1

[U-Boot] [PATCH v4 03/24] spi: altera_spi: Use BIT macro

[Jagan Teki]

Replace numerical bit shift with BIT macro in altera_spi

:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31

Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Jagan Teki <jteki@openedev.com>
---
 drivers/spi/altera_spi.c | 26 +++++++++++++-------------
 1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/drivers/spi/altera_spi.c b/drivers/spi/altera_spi.c
index a4d03d9..2302117 100644
--- a/drivers/spi/altera_spi.c
+++ b/drivers/spi/altera_spi.c
@@ -29,19 +29,19 @@ struct altera_spi_regs {
 	u32	slave_sel;
 };
 
-#define ALTERA_SPI_STATUS_ROE_MSK	(1 << 3)
-#define ALTERA_SPI_STATUS_TOE_MSK	(1 << 4)
-#define ALTERA_SPI_STATUS_TMT_MSK	(1 << 5)
-#define ALTERA_SPI_STATUS_TRDY_MSK	(1 << 6)
-#define ALTERA_SPI_STATUS_RRDY_MSK	(1 << 7)
-#define ALTERA_SPI_STATUS_E_MSK		(1 << 8)
-
-#define ALTERA_SPI_CONTROL_IROE_MSK	(1 << 3)
-#define ALTERA_SPI_CONTROL_ITOE_MSK	(1 << 4)
-#define ALTERA_SPI_CONTROL_ITRDY_MSK	(1 << 6)
-#define ALTERA_SPI_CONTROL_IRRDY_MSK	(1 << 7)
-#define ALTERA_SPI_CONTROL_IE_MSK	(1 << 8)
-#define ALTERA_SPI_CONTROL_SSO_MSK	(1 << 10)
+#define ALTERA_SPI_STATUS_ROE_MSK	BIT(3)
+#define ALTERA_SPI_STATUS_TOE_MSK	BIT(4)
+#define ALTERA_SPI_STATUS_TMT_MSK	BIT(5)
+#define ALTERA_SPI_STATUS_TRDY_MSK	BIT(6)
+#define ALTERA_SPI_STATUS_RRDY_MSK	BIT(7)
+#define ALTERA_SPI_STATUS_E_MSK		BIT(8)
+
+#define ALTERA_SPI_CONTROL_IROE_MSK	BIT(3)
+#define ALTERA_SPI_CONTROL_ITOE_MSK	BIT(4)
+#define ALTERA_SPI_CONTROL_ITRDY_MSK	BIT(6)
+#define ALTERA_SPI_CONTROL_IRRDY_MSK	BIT(7)
+#define ALTERA_SPI_CONTROL_IE_MSK	BIT(8)
+#define ALTERA_SPI_CONTROL_SSO_MSK	BIT(10)
 
 static ulong altera_spi_base_list[] = CONFIG_SYS_ALTERA_SPI_LIST;
 
-- 
1.9.1

[U-Boot] [PATCH v4 04/24] spi: atmel_spi: Use BIT macro

[Jagan Teki]

Replace numerical bit shift with BIT macro in atmel_spi

:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31

Cc: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
---
 drivers/spi/atmel_spi.h | 52 ++++++++++++++++++++++++-------------------------
 1 file changed, 26 insertions(+), 26 deletions(-)

diff --git a/drivers/spi/atmel_spi.h b/drivers/spi/atmel_spi.h
index 1538a23..5b892d2 100644
--- a/drivers/spi/atmel_spi.h
+++ b/drivers/spi/atmel_spi.h
@@ -15,19 +15,19 @@
 #define ATMEL_SPI_VERSION		0x00fc
 
 /* Bits in CR */
-#define ATMEL_SPI_CR_SPIEN		(1 << 0)
-#define ATMEL_SPI_CR_SPIDIS		(1 << 1)
-#define ATMEL_SPI_CR_SWRST		(1 << 7)
-#define ATMEL_SPI_CR_LASTXFER		(1 << 24)
+#define ATMEL_SPI_CR_SPIEN		BIT(0)
+#define ATMEL_SPI_CR_SPIDIS		BIT(1)
+#define ATMEL_SPI_CR_SWRST		BIT(7)
+#define ATMEL_SPI_CR_LASTXFER		BIT(24)
 
 /* Bits in MR */
-#define ATMEL_SPI_MR_MSTR		(1 << 0)
-#define ATMEL_SPI_MR_PS			(1 << 1)
-#define ATMEL_SPI_MR_PCSDEC		(1 << 2)
-#define ATMEL_SPI_MR_FDIV		(1 << 3)
-#define ATMEL_SPI_MR_MODFDIS		(1 << 4)
-#define ATMEL_SPI_MR_WDRBT		(1 << 5)
-#define ATMEL_SPI_MR_LLB		(1 << 7)
+#define ATMEL_SPI_MR_MSTR		BIT(0)
+#define ATMEL_SPI_MR_PS			BIT(1)
+#define ATMEL_SPI_MR_PCSDEC		BIT(2)
+#define ATMEL_SPI_MR_FDIV		BIT(3)
+#define ATMEL_SPI_MR_MODFDIS		BIT(4)
+#define ATMEL_SPI_MR_WDRBT		BIT(5)
+#define ATMEL_SPI_MR_LLB		BIT(7)
 #define ATMEL_SPI_MR_PCS(x)		(((x) & 15) << 16)
 #define ATMEL_SPI_MR_DLYBCS(x)		((x) << 24)
 
@@ -38,25 +38,25 @@
 /* Bits in TDR */
 #define ATMEL_SPI_TDR_TD(x)		(x)
 #define ATMEL_SPI_TDR_PCS(x)		((x) << 16)
-#define ATMEL_SPI_TDR_LASTXFER		(1 << 24)
+#define ATMEL_SPI_TDR_LASTXFER		BIT(24)
 
 /* Bits in SR/IER/IDR/IMR */
-#define ATMEL_SPI_SR_RDRF		(1 << 0)
-#define ATMEL_SPI_SR_TDRE		(1 << 1)
-#define ATMEL_SPI_SR_MODF		(1 << 2)
-#define ATMEL_SPI_SR_OVRES		(1 << 3)
-#define ATMEL_SPI_SR_ENDRX		(1 << 4)
-#define ATMEL_SPI_SR_ENDTX		(1 << 5)
-#define ATMEL_SPI_SR_RXBUFF		(1 << 6)
-#define ATMEL_SPI_SR_TXBUFE		(1 << 7)
-#define ATMEL_SPI_SR_NSSR		(1 << 8)
-#define ATMEL_SPI_SR_TXEMPTY		(1 << 9)
-#define ATMEL_SPI_SR_SPIENS		(1 << 16)
+#define ATMEL_SPI_SR_RDRF		BIT(0)
+#define ATMEL_SPI_SR_TDRE		BIT(1)
+#define ATMEL_SPI_SR_MODF		BIT(2)
+#define ATMEL_SPI_SR_OVRES		BIT(3)
+#define ATMEL_SPI_SR_ENDRX		BIT(4)
+#define ATMEL_SPI_SR_ENDTX		BIT(5)
+#define ATMEL_SPI_SR_RXBUFF		BIT(6)
+#define ATMEL_SPI_SR_TXBUFE		BIT(7)
+#define ATMEL_SPI_SR_NSSR		BIT(8)
+#define ATMEL_SPI_SR_TXEMPTY		BIT(9)
+#define ATMEL_SPI_SR_SPIENS		BIT(16)
 
 /* Bits in CSRx */
-#define ATMEL_SPI_CSRx_CPOL		(1 << 0)
-#define ATMEL_SPI_CSRx_NCPHA		(1 << 1)
-#define ATMEL_SPI_CSRx_CSAAT		(1 << 3)
+#define ATMEL_SPI_CSRx_CPOL		BIT(0)
+#define ATMEL_SPI_CSRx_NCPHA		BIT(1)
+#define ATMEL_SPI_CSRx_CSAAT		BIT(3)
 #define ATMEL_SPI_CSRx_BITS(x)		((x) << 4)
 #define ATMEL_SPI_CSRx_SCBR(x)		((x) << 8)
 #define ATMEL_SPI_CSRx_SCBR_MAX		0xff
-- 
1.9.1

[U-Boot] [PATCH v4 05/24] spi: bfin_spi6xx: Use BIT macro

[Jagan Teki]

Replace numerical bit shift with BIT macro in bfin_spi6xx

:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31

Signed-off-by: Jagan Teki <jteki@openedev.com>
---
 drivers/spi/bfin_spi6xx.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/spi/bfin_spi6xx.c b/drivers/spi/bfin_spi6xx.c
index eba01d1..8359d76 100644
--- a/drivers/spi/bfin_spi6xx.c
+++ b/drivers/spi/bfin_spi6xx.c
@@ -63,9 +63,9 @@ void spi_cs_activate(struct spi_slave *slave)
 		ssel = bfin_read32(&bss->regs->ssel);
 		ssel |= 1 << slave->cs;
 		if (bss->cs_pol)
-			ssel |= (1 << 8) << slave->cs;
+			ssel |= BIT(8) << slave->cs;
 		else
-			ssel &= ~((1 << 8) << slave->cs);
+			ssel &= ~(BIT(8) << slave->cs);
 		bfin_write32(&bss->regs->ssel, ssel);
 	}
 
@@ -83,9 +83,9 @@ void spi_cs_deactivate(struct spi_slave *slave)
 		u32 ssel;
 		ssel = bfin_read32(&bss->regs->ssel);
 		if (bss->cs_pol)
-			ssel &= ~((1 << 8) << slave->cs);
+			ssel &= ~(BIT(8) << slave->cs);
 		else
-			ssel |= (1 << 8) << slave->cs;
+			ssel |= BIT(8) << slave->cs;
 		/* deassert cs */
 		bfin_write32(&bss->regs->ssel, ssel);
 		SSYNC();
-- 
1.9.1

[U-Boot] [PATCH v4 06/24] spi: cadence_qspi_apb: Use BIT macro

[Jagan Teki]

Replace numerical bit shift with BIT macro in cadence_qspi_apb

:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31

Cc: Stefan Roese <sr@denx.de>
Cc: Vikas Manocha <vikas.manocha@st.com>
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Jagan Teki <jteki@openedev.com>
---
 drivers/spi/cadence_qspi_apb.c | 28 ++++++++++++++--------------
 1 file changed, 14 insertions(+), 14 deletions(-)

diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index d053407..7786dd6 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -58,10 +58,10 @@
 #define	CQSPI_REG_CONFIG			0x00
 #define	CQSPI_REG_CONFIG_CLK_POL_LSB		1
 #define	CQSPI_REG_CONFIG_CLK_PHA_LSB		2
-#define	CQSPI_REG_CONFIG_ENABLE_MASK		(1 << 0)
-#define	CQSPI_REG_CONFIG_DIRECT_MASK		(1 << 7)
-#define	CQSPI_REG_CONFIG_DECODE_MASK		(1 << 9)
-#define	CQSPI_REG_CONFIG_XIP_IMM_MASK		(1 << 18)
+#define	CQSPI_REG_CONFIG_ENABLE_MASK		BIT(0)
+#define	CQSPI_REG_CONFIG_DIRECT_MASK		BIT(7)
+#define	CQSPI_REG_CONFIG_DECODE_MASK		BIT(9)
+#define	CQSPI_REG_CONFIG_XIP_IMM_MASK		BIT(18)
 #define	CQSPI_REG_CONFIG_CHIPSELECT_LSB		10
 #define	CQSPI_REG_CONFIG_BAUD_LSB		19
 #define	CQSPI_REG_CONFIG_IDLE_LSB		31
@@ -122,18 +122,18 @@
 #define	CQSPI_REG_IRQMASK			0x44
 
 #define	CQSPI_REG_INDIRECTRD			0x60
-#define	CQSPI_REG_INDIRECTRD_START_MASK		(1 << 0)
-#define	CQSPI_REG_INDIRECTRD_CANCEL_MASK	(1 << 1)
-#define	CQSPI_REG_INDIRECTRD_INPROGRESS_MASK	(1 << 2)
-#define	CQSPI_REG_INDIRECTRD_DONE_MASK		(1 << 5)
+#define	CQSPI_REG_INDIRECTRD_START_MASK		BIT(0)
+#define	CQSPI_REG_INDIRECTRD_CANCEL_MASK	BIT(1)
+#define	CQSPI_REG_INDIRECTRD_INPROGRESS_MASK	BIT(2)
+#define	CQSPI_REG_INDIRECTRD_DONE_MASK		BIT(5)
 
 #define	CQSPI_REG_INDIRECTRDWATERMARK		0x64
 #define	CQSPI_REG_INDIRECTRDSTARTADDR		0x68
 #define	CQSPI_REG_INDIRECTRDBYTES		0x6C
 
 #define	CQSPI_REG_CMDCTRL			0x90
-#define	CQSPI_REG_CMDCTRL_EXECUTE_MASK		(1 << 0)
-#define	CQSPI_REG_CMDCTRL_INPROGRESS_MASK	(1 << 1)
+#define	CQSPI_REG_CMDCTRL_EXECUTE_MASK		BIT(0)
+#define	CQSPI_REG_CMDCTRL_INPROGRESS_MASK	BIT(1)
 #define	CQSPI_REG_CMDCTRL_DUMMY_LSB		7
 #define	CQSPI_REG_CMDCTRL_WR_BYTES_LSB		12
 #define	CQSPI_REG_CMDCTRL_WR_EN_LSB		15
@@ -149,10 +149,10 @@
 #define	CQSPI_REG_CMDCTRL_OPCODE_MASK		0xFF
 
 #define	CQSPI_REG_INDIRECTWR			0x70
-#define	CQSPI_REG_INDIRECTWR_START_MASK		(1 << 0)
-#define	CQSPI_REG_INDIRECTWR_CANCEL_MASK	(1 << 1)
-#define	CQSPI_REG_INDIRECTWR_INPROGRESS_MASK	(1 << 2)
-#define	CQSPI_REG_INDIRECTWR_DONE_MASK		(1 << 5)
+#define	CQSPI_REG_INDIRECTWR_START_MASK		BIT(0)
+#define	CQSPI_REG_INDIRECTWR_CANCEL_MASK	BIT(1)
+#define	CQSPI_REG_INDIRECTWR_INPROGRESS_MASK	BIT(2)
+#define	CQSPI_REG_INDIRECTWR_DONE_MASK		BIT(5)
 
 #define	CQSPI_REG_INDIRECTWRWATERMARK		0x74
 #define	CQSPI_REG_INDIRECTWRSTARTADDR		0x78
-- 
1.9.1

[U-Boot] [PATCH v4 07/24] spi: designware_spi: Use BIT macro

[Jagan Teki]

Replace numerical bit shift with BIT macro in designware_spi

:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31

Cc: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Jagan Teki <jteki@openedev.com>
---
 drivers/spi/designware_spi.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index 86ee90f..7885e46 100644
--- a/drivers/spi/designware_spi.c
+++ b/drivers/spi/designware_spi.c
@@ -75,13 +75,13 @@ DECLARE_GLOBAL_DATA_PTR;
 
 /* Bit fields in SR, 7 bits */
 #define SR_MASK				0x7f		/* cover 7 bits */
-#define SR_BUSY				(1 << 0)
-#define SR_TF_NOT_FULL			(1 << 1)
-#define SR_TF_EMPT			(1 << 2)
-#define SR_RF_NOT_EMPT			(1 << 3)
-#define SR_RF_FULL			(1 << 4)
-#define SR_TX_ERR			(1 << 5)
-#define SR_DCOL				(1 << 6)
+#define SR_BUSY				BIT(0)
+#define SR_TF_NOT_FULL			BIT(1)
+#define SR_TF_EMPT			BIT(2)
+#define SR_RF_NOT_EMPT			BIT(3)
+#define SR_RF_FULL			BIT(4)
+#define SR_TX_ERR			BIT(5)
+#define SR_DCOL				BIT(6)
 
 #define RX_TIMEOUT			1000		/* timeout in ms */
 
-- 
1.9.1

[U-Boot] [PATCH v4 08/24] spi: exynos_spi: Use BIT macro

[Jagan Teki]

Replace numerical bit shift with BIT macro in exynos_spi

:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31

Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jteki@openedev.com>
---
 drivers/spi/exynos_spi.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/exynos_spi.c b/drivers/spi/exynos_spi.c
index 44948c3..ea3c51d 100644
--- a/drivers/spi/exynos_spi.c
+++ b/drivers/spi/exynos_spi.c
@@ -86,7 +86,7 @@ static void spi_request_bytes(struct exynos_spi *regs, int count, int step)
 		writel(0, &regs->swap_cfg);
 	}
 
-	assert(count && count < (1 << 16));
+	assert(count && count < BIT(16));
 	setbits_le32(&regs->ch_cfg, SPI_CH_RST);
 	clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
 
@@ -345,7 +345,7 @@ static int exynos_spi_xfer(struct udevice *dev, unsigned int bitlen,
 	 */
 	bytelen = bitlen / 8;
 	for (upto = 0; !ret && upto < bytelen; upto += todo) {
-		todo = min(bytelen - upto, (1 << 16) - 4);
+		todo = min(bytelen - upto, BIT(16) - 4);
 		ret = spi_rx_tx(priv, todo, &din, &dout, flags);
 		if (ret)
 			break;
-- 
1.9.1

[U-Boot] [PATCH v4 09/24] spi: fsl: Use BIT macro

[Jagan Teki]

Replace numerical bit shift with BIT macro in fsl_*spi.c

:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31

Cc: York Sun <yorksun@freescale.com>
Cc: Haikun Wang <Haikun.Wang@freescale.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
---
 drivers/spi/fsl_dspi.c |  2 +-
 drivers/spi/fsl_espi.c | 20 ++++++++++----------
 drivers/spi/fsl_qspi.c |  4 ++--
 3 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/drivers/spi/fsl_dspi.c b/drivers/spi/fsl_dspi.c
index 887edd8..c8dcb27 100644
--- a/drivers/spi/fsl_dspi.c
+++ b/drivers/spi/fsl_dspi.c
@@ -24,7 +24,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /* fsl_dspi_platdata flags */
-#define DSPI_FLAG_REGMAP_ENDIAN_BIG	(1 << 0)
+#define DSPI_FLAG_REGMAP_ENDIAN_BIG	BIT(0)
 
 /* idle data value */
 #define DSPI_IDLE_VAL			0x0
diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c
index 375dc07..b1586d1 100644
--- a/drivers/spi/fsl_espi.c
+++ b/drivers/spi/fsl_espi.c
@@ -32,26 +32,26 @@ struct fsl_spi_slave {
 #define ESPI_MAX_CS_NUM		4
 #define ESPI_FIFO_WIDTH_BIT	32
 
-#define ESPI_EV_RNE		(1 << 9)
-#define ESPI_EV_TNF		(1 << 8)
-#define ESPI_EV_DON		(1 << 14)
-#define ESPI_EV_TXE		(1 << 15)
+#define ESPI_EV_RNE		BIT(9)
+#define ESPI_EV_TNF		BIT(8)
+#define ESPI_EV_DON		BIT(14)
+#define ESPI_EV_TXE		BIT(15)
 #define ESPI_EV_RFCNT_SHIFT	24
 #define ESPI_EV_RFCNT_MASK	(0x3f << ESPI_EV_RFCNT_SHIFT)
 
-#define ESPI_MODE_EN		(1 << 31)	/* Enable interface */
+#define ESPI_MODE_EN		BIT(31)	/* Enable interface */
 #define ESPI_MODE_TXTHR(x)	((x) << 8)	/* Tx FIFO threshold */
 #define ESPI_MODE_RXTHR(x)	((x) << 0)	/* Rx FIFO threshold */
 
 #define ESPI_COM_CS(x)		((x) << 30)
 #define ESPI_COM_TRANLEN(x)	((x) << 0)
 
-#define ESPI_CSMODE_CI_INACTIVEHIGH	(1 << 31)
-#define ESPI_CSMODE_CP_BEGIN_EDGCLK	(1 << 30)
-#define ESPI_CSMODE_REV_MSB_FIRST	(1 << 29)
-#define ESPI_CSMODE_DIV16		(1 << 28)
+#define ESPI_CSMODE_CI_INACTIVEHIGH	BIT(31)
+#define ESPI_CSMODE_CP_BEGIN_EDGCLK	BIT(30)
+#define ESPI_CSMODE_REV_MSB_FIRST	BIT(29)
+#define ESPI_CSMODE_DIV16		BIT(28)
 #define ESPI_CSMODE_PM(x)		((x) << 24)
-#define ESPI_CSMODE_POL_ASSERTED_LOW	(1 << 20)
+#define ESPI_CSMODE_POL_ASSERTED_LOW	BIT(20)
 #define ESPI_CSMODE_LEN(x)		((x) << 16)
 #define ESPI_CSMODE_CSBEF(x)		((x) << 12)
 #define ESPI_CSMODE_CSAFT(x)		((x) << 8)
diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index 868df5f..e1a0ec9 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -68,7 +68,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define QSPI_CMD_SE_4B		0xdc    /* Sector erase (usually 64KiB) */
 
 /* fsl_qspi_platdata flags */
-#define QSPI_FLAG_REGMAP_ENDIAN_BIG	(1 << 0)
+#define QSPI_FLAG_REGMAP_ENDIAN_BIG	BIT(0)
 
 /* default SCK frequency, unit: HZ */
 #define FSL_QSPI_DEFAULT_SCK_FREQ	50000000
@@ -383,7 +383,7 @@ static void qspi_enable_ddr_mode(struct fsl_qspi_priv *priv)
 	/* Enable the module again (enable the DDR too) */
 	reg |= QSPI_MCR_DDR_EN_MASK;
 	/* Enable bit 29 for imx6sx */
-	reg |= (1 << 29);
+	reg |= BIT(29);
 
 	qspi_write32(priv->flags, &regs->mcr, reg);
 }
-- 
1.9.1

[U-Boot] [PATCH v4 10/24] spi: ich: Use BIT macro

[Jagan Teki]

Replace numerical bit shift with BIT macro in ich

:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31

Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jteki@openedev.com>
---
 drivers/spi/ich.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
index be4c0a3..af327c4 100644
--- a/drivers/spi/ich.c
+++ b/drivers/spi/ich.c
@@ -692,13 +692,13 @@ static int ich_spi_probe(struct udevice *bus)
 	 */
 	if (plat->use_sbase) {
 		bios_cntl = ich_readb(priv, priv->bcr);
-		bios_cntl &= ~(1 << 5);	/* clear Enable InSMM_STS (EISS) */
+		bios_cntl &= ~BIT(5);	/* clear Enable InSMM_STS (EISS) */
 		bios_cntl |= 1;		/* Write Protect Disable (WPD) */
 		ich_writeb(priv, bios_cntl, priv->bcr);
 	} else {
 		pci_read_config_byte(plat->dev, 0xdc, &bios_cntl);
 		if (plat->ich_version == 9)
-			bios_cntl &= ~(1 << 5);
+			bios_cntl &= ~BIT(5);
 		pci_write_config_byte(plat->dev, 0xdc, bios_cntl | 0x1);
 	}
 
-- 
1.9.1

[U-Boot] [PATCH v4 11/24] spi: mpc8xxx_spi: Use BIT macro

[Jagan Teki]

Replace numerical bit shift with BIT macro in mpc8xxx_spi

:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31

Signed-off-by: Jagan Teki <jteki@openedev.com>
---
 drivers/spi/mpc8xxx_spi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/spi/mpc8xxx_spi.c b/drivers/spi/mpc8xxx_spi.c
index 0d59c36..00cbcbf 100644
--- a/drivers/spi/mpc8xxx_spi.c
+++ b/drivers/spi/mpc8xxx_spi.c
@@ -55,7 +55,7 @@ void spi_init(void)
 	 * some registers
 	 */
 	spi->mode = SPI_MODE_REV | SPI_MODE_MS | SPI_MODE_EN;
-	spi->mode = (spi->mode & 0xfff0ffff) | (1 << 16); /* Use SYSCLK / 8
+	spi->mode = (spi->mode & 0xfff0ffff) | BIT(16); /* Use SYSCLK / 8
 							     (16.67MHz typ.) */
 	spi->event = 0xffffffff;	/* Clear all SPI events */
 	spi->mask = 0x00000000;	/* Mask  all SPI interrupts */
-- 
1.9.1

[U-Boot] [PATCH v4 12/24] spi: omap3_spi: Use BIT macro

[Jagan Teki]

Replace numerical bit shift with BIT macro in omap3_spi

:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31

Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Tom Rini <trini@konsulko.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
---
 drivers/spi/omap3_spi.h | 48 ++++++++++++++++++++++++------------------------
 1 file changed, 24 insertions(+), 24 deletions(-)

diff --git a/drivers/spi/omap3_spi.h b/drivers/spi/omap3_spi.h
index 4af22c1..fb02ea1 100644
--- a/drivers/spi/omap3_spi.h
+++ b/drivers/spi/omap3_spi.h
@@ -52,40 +52,40 @@ struct mcspi {
 
 /* per-register bitmasks */
 #define OMAP3_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3)
-#define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP (1 << 2)
-#define OMAP3_MCSPI_SYSCONFIG_AUTOIDLE	(1 << 0)
-#define OMAP3_MCSPI_SYSCONFIG_SOFTRESET (1 << 1)
+#define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2)
+#define OMAP3_MCSPI_SYSCONFIG_AUTOIDLE	BIT(0)
+#define OMAP3_MCSPI_SYSCONFIG_SOFTRESET BIT(1)
 
-#define OMAP3_MCSPI_SYSSTATUS_RESETDONE (1 << 0)
+#define OMAP3_MCSPI_SYSSTATUS_RESETDONE BIT(0)
 
-#define OMAP3_MCSPI_MODULCTRL_SINGLE	(1 << 0)
-#define OMAP3_MCSPI_MODULCTRL_MS	(1 << 2)
-#define OMAP3_MCSPI_MODULCTRL_STEST	(1 << 3)
+#define OMAP3_MCSPI_MODULCTRL_SINGLE	BIT(0)
+#define OMAP3_MCSPI_MODULCTRL_MS	BIT(2)
+#define OMAP3_MCSPI_MODULCTRL_STEST	BIT(3)
 
-#define OMAP3_MCSPI_CHCONF_PHA		(1 << 0)
-#define OMAP3_MCSPI_CHCONF_POL		(1 << 1)
+#define OMAP3_MCSPI_CHCONF_PHA		BIT(0)
+#define OMAP3_MCSPI_CHCONF_POL		BIT(1)
 #define OMAP3_MCSPI_CHCONF_CLKD_MASK	(0x0f << 2)
-#define OMAP3_MCSPI_CHCONF_EPOL		(1 << 6)
+#define OMAP3_MCSPI_CHCONF_EPOL		BIT(6)
 #define OMAP3_MCSPI_CHCONF_WL_MASK	(0x1f << 7)
 #define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY	(0x01 << 12)
 #define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY	(0x02 << 12)
 #define OMAP3_MCSPI_CHCONF_TRM_MASK	(0x03 << 12)
-#define OMAP3_MCSPI_CHCONF_DMAW		(1 << 14)
-#define OMAP3_MCSPI_CHCONF_DMAR		(1 << 15)
-#define OMAP3_MCSPI_CHCONF_DPE0		(1 << 16)
-#define OMAP3_MCSPI_CHCONF_DPE1		(1 << 17)
-#define OMAP3_MCSPI_CHCONF_IS		(1 << 18)
-#define OMAP3_MCSPI_CHCONF_TURBO	(1 << 19)
-#define OMAP3_MCSPI_CHCONF_FORCE	(1 << 20)
-
-#define OMAP3_MCSPI_CHSTAT_RXS		(1 << 0)
-#define OMAP3_MCSPI_CHSTAT_TXS		(1 << 1)
-#define OMAP3_MCSPI_CHSTAT_EOT		(1 << 2)
-
-#define OMAP3_MCSPI_CHCTRL_EN		(1 << 0)
+#define OMAP3_MCSPI_CHCONF_DMAW		BIT(14)
+#define OMAP3_MCSPI_CHCONF_DMAR		BIT(15)
+#define OMAP3_MCSPI_CHCONF_DPE0		BIT(16)
+#define OMAP3_MCSPI_CHCONF_DPE1		BIT(17)
+#define OMAP3_MCSPI_CHCONF_IS		BIT(18)
+#define OMAP3_MCSPI_CHCONF_TURBO	BIT(19)
+#define OMAP3_MCSPI_CHCONF_FORCE	BIT(20)
+
+#define OMAP3_MCSPI_CHSTAT_RXS		BIT(0)
+#define OMAP3_MCSPI_CHSTAT_TXS		BIT(1)
+#define OMAP3_MCSPI_CHSTAT_EOT		BIT(2)
+
+#define OMAP3_MCSPI_CHCTRL_EN		BIT(0)
 #define OMAP3_MCSPI_CHCTRL_DIS		(0 << 0)
 
-#define OMAP3_MCSPI_WAKEUPENABLE_WKEN	(1 << 0)
+#define OMAP3_MCSPI_WAKEUPENABLE_WKEN	BIT(0)
 
 struct omap3_spi_slave {
 	struct spi_slave slave;
-- 
1.9.1

[U-Boot] [PATCH v4 13/24] spi: sh_qspi: Use BIT macro

[Jagan Teki]

Replace numerical bit shift with BIT macro in sh_qspi

:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31

Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
---
 drivers/spi/sh_qspi.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/spi/sh_qspi.c b/drivers/spi/sh_qspi.c
index 77ede6b..7209e1d 100644
--- a/drivers/spi/sh_qspi.c
+++ b/drivers/spi/sh_qspi.c
@@ -21,19 +21,19 @@
 #define SPPCR_IO3FV	0x04
 #define SPPCR_IO2FV	0x02
 #define SPPCR_IO1FV	0x01
-#define SPBDCR_RXBC0	(1 << 0)
-#define SPCMD_SCKDEN	(1 << 15)
-#define SPCMD_SLNDEN	(1 << 14)
-#define SPCMD_SPNDEN	(1 << 13)
-#define SPCMD_SSLKP	(1 << 7)
-#define SPCMD_BRDV0	(1 << 2)
+#define SPBDCR_RXBC0	BIT(0)
+#define SPCMD_SCKDEN	BIT(15)
+#define SPCMD_SLNDEN	BIT(14)
+#define SPCMD_SPNDEN	BIT(13)
+#define SPCMD_SSLKP	BIT(7)
+#define SPCMD_BRDV0	BIT(2)
 #define SPCMD_INIT1	SPCMD_SCKDEN | SPCMD_SLNDEN | \
 			SPCMD_SPNDEN | SPCMD_SSLKP | \
 			SPCMD_BRDV0
 #define SPCMD_INIT2	SPCMD_SPNDEN | SPCMD_SSLKP | \
 			SPCMD_BRDV0
-#define SPBFCR_TXRST	(1 << 7)
-#define SPBFCR_RXRST	(1 << 6)
+#define SPBFCR_TXRST	BIT(7)
+#define SPBFCR_RXRST	BIT(6)
 
 /* SH QSPI register set */
 struct sh_qspi_regs {
-- 
1.9.1

[U-Boot] [PATCH v4 14/24] spi: tegra: Use BIT macro

[Jagan Teki]

Replace numerical bit shift with BIT macro in tegra*.c

:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31

Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Tom Warren <twarren@nvidia.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
---
 drivers/spi/tegra114_spi.c   | 64 ++++++++++++++++++++++----------------------
 drivers/spi/tegra20_sflash.c | 50 +++++++++++++++++-----------------
 drivers/spi/tegra20_slink.c  | 58 +++++++++++++++++++--------------------
 3 files changed, 86 insertions(+), 86 deletions(-)

diff --git a/drivers/spi/tegra114_spi.c b/drivers/spi/tegra114_spi.c
index a965f80..d9edd11 100644
--- a/drivers/spi/tegra114_spi.c
+++ b/drivers/spi/tegra114_spi.c
@@ -33,54 +33,54 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /* COMMAND1 */
-#define SPI_CMD1_GO			(1 << 31)
-#define SPI_CMD1_M_S			(1 << 30)
+#define SPI_CMD1_GO			BIT(31)
+#define SPI_CMD1_M_S			BIT(30)
 #define SPI_CMD1_MODE_MASK		0x3
 #define SPI_CMD1_MODE_SHIFT		28
 #define SPI_CMD1_CS_SEL_MASK		0x3
 #define SPI_CMD1_CS_SEL_SHIFT		26
-#define SPI_CMD1_CS_POL_INACTIVE3	(1 << 25)
-#define SPI_CMD1_CS_POL_INACTIVE2	(1 << 24)
-#define SPI_CMD1_CS_POL_INACTIVE1	(1 << 23)
-#define SPI_CMD1_CS_POL_INACTIVE0	(1 << 22)
-#define SPI_CMD1_CS_SW_HW		(1 << 21)
-#define SPI_CMD1_CS_SW_VAL		(1 << 20)
+#define SPI_CMD1_CS_POL_INACTIVE3	BIT(25)
+#define SPI_CMD1_CS_POL_INACTIVE2	BIT(24)
+#define SPI_CMD1_CS_POL_INACTIVE1	BIT(23)
+#define SPI_CMD1_CS_POL_INACTIVE0	BIT(22)
+#define SPI_CMD1_CS_SW_HW		BIT(21)
+#define SPI_CMD1_CS_SW_VAL		BIT(20)
 #define SPI_CMD1_IDLE_SDA_MASK		0x3
 #define SPI_CMD1_IDLE_SDA_SHIFT		18
-#define SPI_CMD1_BIDIR			(1 << 17)
-#define SPI_CMD1_LSBI_FE		(1 << 16)
-#define SPI_CMD1_LSBY_FE		(1 << 15)
-#define SPI_CMD1_BOTH_EN_BIT		(1 << 14)
-#define SPI_CMD1_BOTH_EN_BYTE		(1 << 13)
-#define SPI_CMD1_RX_EN			(1 << 12)
-#define SPI_CMD1_TX_EN			(1 << 11)
-#define SPI_CMD1_PACKED			(1 << 5)
+#define SPI_CMD1_BIDIR			BIT(17)
+#define SPI_CMD1_LSBI_FE		BIT(16)
+#define SPI_CMD1_LSBY_FE		BIT(15)
+#define SPI_CMD1_BOTH_EN_BIT		BIT(14)
+#define SPI_CMD1_BOTH_EN_BYTE		BIT(13)
+#define SPI_CMD1_RX_EN			BIT(12)
+#define SPI_CMD1_TX_EN			BIT(11)
+#define SPI_CMD1_PACKED			BIT(5)
 #define SPI_CMD1_BIT_LEN_MASK		0x1F
 #define SPI_CMD1_BIT_LEN_SHIFT		0
 
 /* COMMAND2 */
-#define SPI_CMD2_TX_CLK_TAP_DELAY	(1 << 6)
+#define SPI_CMD2_TX_CLK_TAP_DELAY	BIT(6)
 #define SPI_CMD2_TX_CLK_TAP_DELAY_MASK	(0x3F << 6)
-#define SPI_CMD2_RX_CLK_TAP_DELAY	(1 << 0)
+#define SPI_CMD2_RX_CLK_TAP_DELAY	BIT(0)
 #define SPI_CMD2_RX_CLK_TAP_DELAY_MASK	(0x3F << 0)
 
 /* TRANSFER STATUS */
-#define SPI_XFER_STS_RDY		(1 << 30)
+#define SPI_XFER_STS_RDY		BIT(30)
 
 /* FIFO STATUS */
-#define SPI_FIFO_STS_CS_INACTIVE	(1 << 31)
-#define SPI_FIFO_STS_FRAME_END		(1 << 30)
-#define SPI_FIFO_STS_RX_FIFO_FLUSH	(1 << 15)
-#define SPI_FIFO_STS_TX_FIFO_FLUSH	(1 << 14)
-#define SPI_FIFO_STS_ERR		(1 << 8)
-#define SPI_FIFO_STS_TX_FIFO_OVF	(1 << 7)
-#define SPI_FIFO_STS_TX_FIFO_UNR	(1 << 6)
-#define SPI_FIFO_STS_RX_FIFO_OVF	(1 << 5)
-#define SPI_FIFO_STS_RX_FIFO_UNR	(1 << 4)
-#define SPI_FIFO_STS_TX_FIFO_FULL	(1 << 3)
-#define SPI_FIFO_STS_TX_FIFO_EMPTY	(1 << 2)
-#define SPI_FIFO_STS_RX_FIFO_FULL	(1 << 1)
-#define SPI_FIFO_STS_RX_FIFO_EMPTY	(1 << 0)
+#define SPI_FIFO_STS_CS_INACTIVE	BIT(31)
+#define SPI_FIFO_STS_FRAME_END		BIT(30)
+#define SPI_FIFO_STS_RX_FIFO_FLUSH	BIT(15)
+#define SPI_FIFO_STS_TX_FIFO_FLUSH	BIT(14)
+#define SPI_FIFO_STS_ERR		BIT(8)
+#define SPI_FIFO_STS_TX_FIFO_OVF	BIT(7)
+#define SPI_FIFO_STS_TX_FIFO_UNR	BIT(6)
+#define SPI_FIFO_STS_RX_FIFO_OVF	BIT(5)
+#define SPI_FIFO_STS_RX_FIFO_UNR	BIT(4)
+#define SPI_FIFO_STS_TX_FIFO_FULL	BIT(3)
+#define SPI_FIFO_STS_TX_FIFO_EMPTY	BIT(2)
+#define SPI_FIFO_STS_RX_FIFO_FULL	BIT(1)
+#define SPI_FIFO_STS_RX_FIFO_EMPTY	BIT(0)
 
 #define SPI_TIMEOUT		1000
 #define TEGRA_SPI_MAX_FREQ	52000000
diff --git a/drivers/spi/tegra20_sflash.c b/drivers/spi/tegra20_sflash.c
index afa0848..5dc196b 100644
--- a/drivers/spi/tegra20_sflash.c
+++ b/drivers/spi/tegra20_sflash.c
@@ -20,37 +20,37 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define SPI_CMD_GO			(1 << 30)
+#define SPI_CMD_GO			BIT(30)
 #define SPI_CMD_ACTIVE_SCLK_SHIFT	26
 #define SPI_CMD_ACTIVE_SCLK_MASK	(3 << SPI_CMD_ACTIVE_SCLK_SHIFT)
-#define SPI_CMD_CK_SDA			(1 << 21)
+#define SPI_CMD_CK_SDA			BIT(21)
 #define SPI_CMD_ACTIVE_SDA_SHIFT	18
 #define SPI_CMD_ACTIVE_SDA_MASK		(3 << SPI_CMD_ACTIVE_SDA_SHIFT)
-#define SPI_CMD_CS_POL			(1 << 16)
-#define SPI_CMD_TXEN			(1 << 15)
-#define SPI_CMD_RXEN			(1 << 14)
-#define SPI_CMD_CS_VAL			(1 << 13)
-#define SPI_CMD_CS_SOFT			(1 << 12)
-#define SPI_CMD_CS_DELAY		(1 << 9)
-#define SPI_CMD_CS3_EN			(1 << 8)
-#define SPI_CMD_CS2_EN			(1 << 7)
-#define SPI_CMD_CS1_EN			(1 << 6)
-#define SPI_CMD_CS0_EN			(1 << 5)
-#define SPI_CMD_BIT_LENGTH		(1 << 4)
+#define SPI_CMD_CS_POL			BIT(16)
+#define SPI_CMD_TXEN			BIT(15)
+#define SPI_CMD_RXEN			BIT(14)
+#define SPI_CMD_CS_VAL			BIT(13)
+#define SPI_CMD_CS_SOFT			BIT(12)
+#define SPI_CMD_CS_DELAY		BIT(9)
+#define SPI_CMD_CS3_EN			BIT(8)
+#define SPI_CMD_CS2_EN			BIT(7)
+#define SPI_CMD_CS1_EN			BIT(6)
+#define SPI_CMD_CS0_EN			BIT(5)
+#define SPI_CMD_BIT_LENGTH		BIT(4)
 #define SPI_CMD_BIT_LENGTH_MASK		0x0000001F
 
-#define SPI_STAT_BSY			(1 << 31)
-#define SPI_STAT_RDY			(1 << 30)
-#define SPI_STAT_RXF_FLUSH		(1 << 29)
-#define SPI_STAT_TXF_FLUSH		(1 << 28)
-#define SPI_STAT_RXF_UNR		(1 << 27)
-#define SPI_STAT_TXF_OVF		(1 << 26)
-#define SPI_STAT_RXF_EMPTY		(1 << 25)
-#define SPI_STAT_RXF_FULL		(1 << 24)
-#define SPI_STAT_TXF_EMPTY		(1 << 23)
-#define SPI_STAT_TXF_FULL		(1 << 22)
-#define SPI_STAT_SEL_TXRX_N		(1 << 16)
-#define SPI_STAT_CUR_BLKCNT		(1 << 15)
+#define SPI_STAT_BSY			BIT(31)
+#define SPI_STAT_RDY			BIT(30)
+#define SPI_STAT_RXF_FLUSH		BIT(29)
+#define SPI_STAT_TXF_FLUSH		BIT(28)
+#define SPI_STAT_RXF_UNR		BIT(27)
+#define SPI_STAT_TXF_OVF		BIT(26)
+#define SPI_STAT_RXF_EMPTY		BIT(25)
+#define SPI_STAT_RXF_FULL		BIT(24)
+#define SPI_STAT_TXF_EMPTY		BIT(23)
+#define SPI_STAT_TXF_FULL		BIT(22)
+#define SPI_STAT_SEL_TXRX_N		BIT(16)
+#define SPI_STAT_CUR_BLKCNT		BIT(15)
 
 #define SPI_TIMEOUT		1000
 #define TEGRA_SPI_MAX_FREQ	52000000
diff --git a/drivers/spi/tegra20_slink.c b/drivers/spi/tegra20_slink.c
index 144716f..d1abac2 100644
--- a/drivers/spi/tegra20_slink.c
+++ b/drivers/spi/tegra20_slink.c
@@ -33,45 +33,45 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /* COMMAND */
-#define SLINK_CMD_ENB			(1 << 31)
-#define SLINK_CMD_GO			(1 << 30)
-#define SLINK_CMD_M_S			(1 << 28)
+#define SLINK_CMD_ENB			BIT(31)
+#define SLINK_CMD_GO			BIT(30)
+#define SLINK_CMD_M_S			BIT(28)
 #define SLINK_CMD_IDLE_SCLK_DRIVE_LOW	(0 << 24)
-#define SLINK_CMD_IDLE_SCLK_DRIVE_HIGH	(1 << 24)
+#define SLINK_CMD_IDLE_SCLK_DRIVE_HIGH	BIT(24)
 #define SLINK_CMD_IDLE_SCLK_PULL_LOW	(2 << 24)
 #define SLINK_CMD_IDLE_SCLK_PULL_HIGH	(3 << 24)
 #define SLINK_CMD_IDLE_SCLK_MASK	(3 << 24)
-#define SLINK_CMD_CK_SDA		(1 << 21)
-#define SLINK_CMD_CS_POL		(1 << 13)
-#define SLINK_CMD_CS_VAL		(1 << 12)
-#define SLINK_CMD_CS_SOFT		(1 << 11)
-#define SLINK_CMD_BIT_LENGTH		(1 << 4)
+#define SLINK_CMD_CK_SDA		BIT(21)
+#define SLINK_CMD_CS_POL		BIT(13)
+#define SLINK_CMD_CS_VAL		BIT(12)
+#define SLINK_CMD_CS_SOFT		BIT(11)
+#define SLINK_CMD_BIT_LENGTH		BIT(4)
 #define SLINK_CMD_BIT_LENGTH_MASK	0x0000001F
 /* COMMAND2 */
-#define SLINK_CMD2_TXEN			(1 << 30)
-#define SLINK_CMD2_RXEN			(1 << 31)
-#define SLINK_CMD2_SS_EN		(1 << 18)
+#define SLINK_CMD2_TXEN			BIT(30)
+#define SLINK_CMD2_RXEN			BIT(31)
+#define SLINK_CMD2_SS_EN		BIT(18)
 #define SLINK_CMD2_SS_EN_SHIFT		18
 #define SLINK_CMD2_SS_EN_MASK		0x000C0000
-#define SLINK_CMD2_CS_ACTIVE_BETWEEN	(1 << 17)
+#define SLINK_CMD2_CS_ACTIVE_BETWEEN	BIT(17)
 /* STATUS */
-#define SLINK_STAT_BSY			(1 << 31)
-#define SLINK_STAT_RDY			(1 << 30)
-#define SLINK_STAT_ERR			(1 << 29)
-#define SLINK_STAT_RXF_FLUSH		(1 << 27)
-#define SLINK_STAT_TXF_FLUSH		(1 << 26)
-#define SLINK_STAT_RXF_OVF		(1 << 25)
-#define SLINK_STAT_TXF_UNR		(1 << 24)
-#define SLINK_STAT_RXF_EMPTY		(1 << 23)
-#define SLINK_STAT_RXF_FULL		(1 << 22)
-#define SLINK_STAT_TXF_EMPTY		(1 << 21)
-#define SLINK_STAT_TXF_FULL		(1 << 20)
-#define SLINK_STAT_TXF_OVF		(1 << 19)
-#define SLINK_STAT_RXF_UNR		(1 << 18)
-#define SLINK_STAT_CUR_BLKCNT		(1 << 15)
+#define SLINK_STAT_BSY			BIT(31)
+#define SLINK_STAT_RDY			BIT(30)
+#define SLINK_STAT_ERR			BIT(29)
+#define SLINK_STAT_RXF_FLUSH		BIT(27)
+#define SLINK_STAT_TXF_FLUSH		BIT(26)
+#define SLINK_STAT_RXF_OVF		BIT(25)
+#define SLINK_STAT_TXF_UNR		BIT(24)
+#define SLINK_STAT_RXF_EMPTY		BIT(23)
+#define SLINK_STAT_RXF_FULL		BIT(22)
+#define SLINK_STAT_TXF_EMPTY		BIT(21)
+#define SLINK_STAT_TXF_FULL		BIT(20)
+#define SLINK_STAT_TXF_OVF		BIT(19)
+#define SLINK_STAT_RXF_UNR		BIT(18)
+#define SLINK_STAT_CUR_BLKCNT		BIT(15)
 /* STATUS2 */
-#define SLINK_STAT2_RXF_FULL_CNT	(1 << 16)
-#define SLINK_STAT2_TXF_FULL_CNT	(1 << 0)
+#define SLINK_STAT2_RXF_FULL_CNT	BIT(16)
+#define SLINK_STAT2_TXF_FULL_CNT	BIT(0)
 
 #define SPI_TIMEOUT		1000
 #define TEGRA_SPI_MAX_FREQ	52000000
-- 
1.9.1

[U-Boot] [PATCH v4 15/24] spi: ti_qspi: Use BIT macro

[Jagan Teki]

Replace numerical bit shift with BIT macro in ti_qspi

:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31

Cc: Tom Rini <trini@konsulko.com>
Cc: Vignesh R <vigneshr@ti.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
---
 drivers/spi/ti_qspi.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index bd63db8..ecd9d78 100644
--- a/drivers/spi/ti_qspi.c
+++ b/drivers/spi/ti_qspi.c
@@ -20,13 +20,13 @@
 #define QSPI_TIMEOUT                    2000000
 #define QSPI_FCLK                       192000000
 /* clock control */
-#define QSPI_CLK_EN                     (1 << 31)
+#define QSPI_CLK_EN                     BIT(31)
 #define QSPI_CLK_DIV_MAX                0xffff
 /* command */
 #define QSPI_EN_CS(n)                   (n << 28)
 #define QSPI_WLEN(n)                    ((n-1) << 19)
-#define QSPI_3_PIN                      (1 << 18)
-#define QSPI_RD_SNGL                    (1 << 16)
+#define QSPI_3_PIN                      BIT(18)
+#define QSPI_RD_SNGL                    BIT(16)
 #define QSPI_WR_SNGL                    (2 << 16)
 #define QSPI_INVAL                      (4 << 16)
 #define QSPI_RD_QUAD                    (7 << 16)
@@ -36,8 +36,8 @@
 #define QSPI_CSPOL(n)                   (1 << (1 + n*8))
 #define QSPI_CKPOL(n)                   (1 << (n*8))
 /* status */
-#define QSPI_WC                         (1 << 1)
-#define QSPI_BUSY                       (1 << 0)
+#define QSPI_WC                         BIT(1)
+#define QSPI_BUSY                       BIT(0)
 #define QSPI_WC_BUSY                    (QSPI_WC | QSPI_BUSY)
 #define QSPI_XFER_DONE                  QSPI_WC
 #define MM_SWITCH                       0x01
-- 
1.9.1

[U-Boot] [PATCH v4 16/24] spi: xilinx_spi: Use BIT macro

[Jagan Teki]

Replace numerical bit shift with BIT macro in xilinx_spi

:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31

Cc: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
---
 drivers/spi/xilinx_spi.c | 32 ++++++++++++++++----------------
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
index 8ccc578..7620163 100644
--- a/drivers/spi/xilinx_spi.c
+++ b/drivers/spi/xilinx_spi.c
@@ -32,24 +32,24 @@
  */
 
 /* SPI Control Register (spicr), [1] p9, [2] p8 */
-#define SPICR_LSB_FIRST		(1 << 9)
-#define SPICR_MASTER_INHIBIT	(1 << 8)
-#define SPICR_MANUAL_SS		(1 << 7)
-#define SPICR_RXFIFO_RESEST	(1 << 6)
-#define SPICR_TXFIFO_RESEST	(1 << 5)
-#define SPICR_CPHA		(1 << 4)
-#define SPICR_CPOL		(1 << 3)
-#define SPICR_MASTER_MODE	(1 << 2)
-#define SPICR_SPE		(1 << 1)
-#define SPICR_LOOP		(1 << 0)
+#define SPICR_LSB_FIRST		BIT(9)
+#define SPICR_MASTER_INHIBIT	BIT(8)
+#define SPICR_MANUAL_SS		BIT(7)
+#define SPICR_RXFIFO_RESEST	BIT(6)
+#define SPICR_TXFIFO_RESEST	BIT(5)
+#define SPICR_CPHA		BIT(4)
+#define SPICR_CPOL		BIT(3)
+#define SPICR_MASTER_MODE	BIT(2)
+#define SPICR_SPE		BIT(1)
+#define SPICR_LOOP		BIT(0)
 
 /* SPI Status Register (spisr), [1] p11, [2] p10 */
-#define SPISR_SLAVE_MODE_SELECT	(1 << 5)
-#define SPISR_MODF		(1 << 4)
-#define SPISR_TX_FULL		(1 << 3)
-#define SPISR_TX_EMPTY		(1 << 2)
-#define SPISR_RX_FULL		(1 << 1)
-#define SPISR_RX_EMPTY		(1 << 0)
+#define SPISR_SLAVE_MODE_SELECT	BIT(5)
+#define SPISR_MODF		BIT(4)
+#define SPISR_TX_FULL		BIT(3)
+#define SPISR_TX_EMPTY		BIT(2)
+#define SPISR_RX_FULL		BIT(1)
+#define SPISR_RX_EMPTY		BIT(0)
 
 /* SPI Data Transmit Register (spidtr), [1] p12, [2] p12 */
 #define SPIDTR_8BIT_MASK	(0xff << 0)
-- 
1.9.1

[U-Boot] [PATCH v4 17/24] spi: atmel_spi: Use GENMASK

[Jagan Teki]

Replace numeric mask hexcodes with GENMASK macro in atmel_spi

Cc: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
---
 drivers/spi/atmel_spi.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/spi/atmel_spi.h b/drivers/spi/atmel_spi.h
index 5b892d2..76b8556 100644
--- a/drivers/spi/atmel_spi.h
+++ b/drivers/spi/atmel_spi.h
@@ -59,7 +59,7 @@
 #define ATMEL_SPI_CSRx_CSAAT		BIT(3)
 #define ATMEL_SPI_CSRx_BITS(x)		((x) << 4)
 #define ATMEL_SPI_CSRx_SCBR(x)		((x) << 8)
-#define ATMEL_SPI_CSRx_SCBR_MAX		0xff
+#define ATMEL_SPI_CSRx_SCBR_MAX		GENMASK(7, 0)
 #define ATMEL_SPI_CSRx_DLYBS(x)		((x) << 16)
 #define ATMEL_SPI_CSRx_DLYBCT(x)	((x) << 24)
 
-- 
1.9.1

[U-Boot] [PATCH v4 18/24] spi: cadence_qspi_apb: Use GENMASK

[Jagan Teki]

Replace numeric mask hexcodes with GENMASK macro in cadence_qspi_apb

Cc: Stefan Roese <sr@denx.de>
Cc: Vikas Manocha <vikas.manocha@st.com>
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Jagan Teki <jteki@openedev.com>
---
 drivers/spi/cadence_qspi_apb.c | 48 +++++++++++++++++++++---------------------
 1 file changed, 24 insertions(+), 24 deletions(-)

diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index 7786dd6..31e14ee 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -44,7 +44,7 @@
 #define CQSPI_INST_TYPE_QUAD			(2)
 
 #define CQSPI_STIG_DATA_LEN_MAX			(8)
-#define CQSPI_INDIRECTTRIGGER_ADDR_MASK		(0xFFFFF)
+#define CQSPI_INDIRECTTRIGGER_ADDR_MASK		GENMASK(19, 0)
 
 #define CQSPI_DUMMY_CLKS_PER_BYTE		(8)
 #define CQSPI_DUMMY_BYTES_MAX			(4)
@@ -65,8 +65,8 @@
 #define	CQSPI_REG_CONFIG_CHIPSELECT_LSB		10
 #define	CQSPI_REG_CONFIG_BAUD_LSB		19
 #define	CQSPI_REG_CONFIG_IDLE_LSB		31
-#define	CQSPI_REG_CONFIG_CHIPSELECT_MASK	0xF
-#define	CQSPI_REG_CONFIG_BAUD_MASK		0xF
+#define	CQSPI_REG_CONFIG_CHIPSELECT_MASK	GENMASK(3, 0)
+#define	CQSPI_REG_CONFIG_BAUD_MASK		GENMASK(3, 0)
 
 #define	CQSPI_REG_RD_INSTR			0x04
 #define	CQSPI_REG_RD_INSTR_OPCODE_LSB		0
@@ -75,10 +75,10 @@
 #define	CQSPI_REG_RD_INSTR_TYPE_DATA_LSB	16
 #define	CQSPI_REG_RD_INSTR_MODE_EN_LSB		20
 #define	CQSPI_REG_RD_INSTR_DUMMY_LSB		24
-#define	CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK	0x3
-#define	CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK	0x3
-#define	CQSPI_REG_RD_INSTR_TYPE_DATA_MASK	0x3
-#define	CQSPI_REG_RD_INSTR_DUMMY_MASK		0x1F
+#define	CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK	GENMASK(1, 0)
+#define	CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK	GENMASK(1, 0)
+#define	CQSPI_REG_RD_INSTR_TYPE_DATA_MASK	GENMASK(1, 0)
+#define	CQSPI_REG_RD_INSTR_DUMMY_MASK		GENMASK(4, 0)
 
 #define	CQSPI_REG_WR_INSTR			0x08
 #define	CQSPI_REG_WR_INSTR_OPCODE_LSB		0
@@ -88,23 +88,23 @@
 #define	CQSPI_REG_DELAY_TCHSH_LSB		8
 #define	CQSPI_REG_DELAY_TSD2D_LSB		16
 #define	CQSPI_REG_DELAY_TSHSL_LSB		24
-#define	CQSPI_REG_DELAY_TSLCH_MASK		0xFF
-#define	CQSPI_REG_DELAY_TCHSH_MASK		0xFF
-#define	CQSPI_REG_DELAY_TSD2D_MASK		0xFF
-#define	CQSPI_REG_DELAY_TSHSL_MASK		0xFF
+#define	CQSPI_REG_DELAY_TSLCH_MASK		GENMASK(7, 0)
+#define	CQSPI_REG_DELAY_TCHSH_MASK		GENMASK(7, 0)
+#define	CQSPI_REG_DELAY_TSD2D_MASK		GENMASK(7, 0)
+#define	CQSPI_REG_DELAY_TSHSL_MASK		GENMASK(7, 0)
 
 #define	CQSPI_READLCAPTURE			0x10
 #define	CQSPI_READLCAPTURE_BYPASS_LSB		0
 #define	CQSPI_READLCAPTURE_DELAY_LSB		1
-#define	CQSPI_READLCAPTURE_DELAY_MASK		0xF
+#define	CQSPI_READLCAPTURE_DELAY_MASK		GENMASK(3, 0)
 
 #define	CQSPI_REG_SIZE				0x14
 #define	CQSPI_REG_SIZE_ADDRESS_LSB		0
 #define	CQSPI_REG_SIZE_PAGE_LSB			4
 #define	CQSPI_REG_SIZE_BLOCK_LSB		16
-#define	CQSPI_REG_SIZE_ADDRESS_MASK		0xF
-#define	CQSPI_REG_SIZE_PAGE_MASK		0xFFF
-#define	CQSPI_REG_SIZE_BLOCK_MASK		0x3F
+#define	CQSPI_REG_SIZE_ADDRESS_MASK		GENMASK(3, 0)
+#define	CQSPI_REG_SIZE_PAGE_MASK		GENMASK(11, 0)
+#define	CQSPI_REG_SIZE_BLOCK_MASK		GENMASK(5, 0)
 
 #define	CQSPI_REG_SRAMPARTITION			0x18
 #define	CQSPI_REG_INDIRECTTRIGGER		0x1C
@@ -115,8 +115,8 @@
 #define	CQSPI_REG_SDRAMLEVEL			0x2C
 #define	CQSPI_REG_SDRAMLEVEL_RD_LSB		0
 #define	CQSPI_REG_SDRAMLEVEL_WR_LSB		16
-#define	CQSPI_REG_SDRAMLEVEL_RD_MASK		0xFFFF
-#define	CQSPI_REG_SDRAMLEVEL_WR_MASK		0xFFFF
+#define	CQSPI_REG_SDRAMLEVEL_RD_MASK		GENMASK(15, 0)
+#define	CQSPI_REG_SDRAMLEVEL_WR_MASK		GENMASK(15, 0)
 
 #define	CQSPI_REG_IRQSTATUS			0x40
 #define	CQSPI_REG_IRQMASK			0x44
@@ -142,11 +142,11 @@
 #define	CQSPI_REG_CMDCTRL_RD_BYTES_LSB		20
 #define	CQSPI_REG_CMDCTRL_RD_EN_LSB		23
 #define	CQSPI_REG_CMDCTRL_OPCODE_LSB		24
-#define	CQSPI_REG_CMDCTRL_DUMMY_MASK		0x1F
-#define	CQSPI_REG_CMDCTRL_WR_BYTES_MASK		0x7
-#define	CQSPI_REG_CMDCTRL_ADD_BYTES_MASK	0x3
-#define	CQSPI_REG_CMDCTRL_RD_BYTES_MASK		0x7
-#define	CQSPI_REG_CMDCTRL_OPCODE_MASK		0xFF
+#define	CQSPI_REG_CMDCTRL_DUMMY_MASK		GENMASK(4, 0)
+#define	CQSPI_REG_CMDCTRL_WR_BYTES_MASK		GENMASK(2, 0)
+#define	CQSPI_REG_CMDCTRL_ADD_BYTES_MASK	GENMASK(1, 0)
+#define	CQSPI_REG_CMDCTRL_RD_BYTES_MASK		GENMASK(2, 0)
+#define	CQSPI_REG_CMDCTRL_OPCODE_MASK		GENMASK(7, 0)
 
 #define	CQSPI_REG_INDIRECTWR			0x70
 #define	CQSPI_REG_INDIRECTWR_START_MASK		BIT(0)
@@ -463,7 +463,7 @@ void cadence_qspi_apb_chipselect(void *reg_base,
 		 * CS2 to 4b'1011
 		 * CS3 to 4b'0111
 		 */
-		chip_select = 0xF & ~(1 << chip_select);
+		chip_select = GENMASK(3, 0) & ~(1 << chip_select);
 	}
 
 	reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
@@ -719,7 +719,7 @@ int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
 #if defined(CONFIG_SPL_SPI_XIP) && defined(CONFIG_SPL_BUILD)
 		writel(0x0, plat->regbase + CQSPI_REG_MODE_BIT);
 #else
-		writel(0xFF, plat->regbase + CQSPI_REG_MODE_BIT);
+		writel(GENMASK(7, 0), plat->regbase + CQSPI_REG_MODE_BIT);
 #endif
 
 		/* Convert to clock cycles. */
-- 
1.9.1

[U-Boot] [PATCH v4 19/24] spi: designware_spi: Use GENMASK

[Jagan Teki]

Replace numeric mask hexcodes with GENMASK macro in designware_spi

Cc: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Jagan Teki <jteki@openedev.com>
---
 drivers/spi/designware_spi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index 7885e46..24a6e98 100644
--- a/drivers/spi/designware_spi.c
+++ b/drivers/spi/designware_spi.c
@@ -74,7 +74,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define SPI_CFS_OFFSET			12
 
 /* Bit fields in SR, 7 bits */
-#define SR_MASK				0x7f		/* cover 7 bits */
+#define SR_MASK				GENMASK(6, 0)	/* cover 7 bits */
 #define SR_BUSY				BIT(0)
 #define SR_TF_NOT_FULL			BIT(1)
 #define SR_TF_EMPT			BIT(2)
-- 
1.9.1

[U-Boot] [PATCH v4 20/24] spi: fsl_qspi: Use GENMASK

[Jagan Teki]

Replace numeric mask hexcodes with GENMASK macro in fsl_qspi

Cc: York Sun <yorksun@freescale.com>
Cc: Haikun Wang <Haikun.Wang@freescale.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
---
 drivers/spi/fsl_qspi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index e1a0ec9..10733df 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -24,7 +24,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define TX_BUFFER_SIZE		0x40
 #endif
 
-#define OFFSET_BITS_MASK	0x00ffffff
+#define OFFSET_BITS_MASK	GENMASK(24, 0)
 
 #define FLASH_STATUS_WEL	0x02
 
-- 
1.9.1

[U-Boot] [PATCH v4 21/24] spi: mxs_spi: Use GENMASK

[Jagan Teki]

Replace numeric mask hexcodes with GENMASK macro in mxs_spi

Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Jagan Teki <jteki@openedev.com>
---
 drivers/spi/mxs_spi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c
index 627644b..459c603 100644
--- a/drivers/spi/mxs_spi.c
+++ b/drivers/spi/mxs_spi.c
@@ -23,7 +23,7 @@
 
 #define	MXS_SPI_MAX_TIMEOUT	1000000
 #define	MXS_SPI_PORT_OFFSET	0x2000
-#define MXS_SSP_CHIPSELECT_MASK		0x00300000
+#define MXS_SSP_CHIPSELECT_MASK		GENMASK(21, 20)
 #define MXS_SSP_CHIPSELECT_SHIFT	20
 
 #define MXSSSP_SMALL_TRANSFER	512
-- 
1.9.1

[U-Boot] [PATCH v4 22/24] spi: omap3_spi: Use GENMASK

[Jagan Teki]

Replace numeric mask hexcodes with GENMASK macro in omap3_spi

Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Tom Rini <trini@konsulko.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
---
 drivers/spi/omap3_spi.h | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/spi/omap3_spi.h b/drivers/spi/omap3_spi.h
index fb02ea1..6a07c6d 100644
--- a/drivers/spi/omap3_spi.h
+++ b/drivers/spi/omap3_spi.h
@@ -64,12 +64,12 @@ struct mcspi {
 
 #define OMAP3_MCSPI_CHCONF_PHA		BIT(0)
 #define OMAP3_MCSPI_CHCONF_POL		BIT(1)
-#define OMAP3_MCSPI_CHCONF_CLKD_MASK	(0x0f << 2)
+#define OMAP3_MCSPI_CHCONF_CLKD_MASK	GENMASK(5, 2)
 #define OMAP3_MCSPI_CHCONF_EPOL		BIT(6)
-#define OMAP3_MCSPI_CHCONF_WL_MASK	(0x1f << 7)
-#define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY	(0x01 << 12)
-#define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY	(0x02 << 12)
-#define OMAP3_MCSPI_CHCONF_TRM_MASK	(0x03 << 12)
+#define OMAP3_MCSPI_CHCONF_WL_MASK	GENMASK(11, 7)
+#define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY	BIT(12)
+#define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY	BIT(13)
+#define OMAP3_MCSPI_CHCONF_TRM_MASK	GENMASK(13, 12)
 #define OMAP3_MCSPI_CHCONF_DMAW		BIT(14)
 #define OMAP3_MCSPI_CHCONF_DMAR		BIT(15)
 #define OMAP3_MCSPI_CHCONF_DPE0		BIT(16)
-- 
1.9.1

[U-Boot] [PATCH v4 23/24] spi: tegra: Use GENMASK

[Jagan Teki]

Replace numeric mask hexcodes with GENMASK macro in tegra*.c

Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Tom Warren <twarren@nvidia.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
---
 drivers/spi/tegra114_spi.c   | 12 ++++++------
 drivers/spi/tegra20_sflash.c |  2 +-
 drivers/spi/tegra20_slink.c  |  4 ++--
 3 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/spi/tegra114_spi.c b/drivers/spi/tegra114_spi.c
index d9edd11..98a062c 100644
--- a/drivers/spi/tegra114_spi.c
+++ b/drivers/spi/tegra114_spi.c
@@ -35,9 +35,9 @@ DECLARE_GLOBAL_DATA_PTR;
 /* COMMAND1 */
 #define SPI_CMD1_GO			BIT(31)
 #define SPI_CMD1_M_S			BIT(30)
-#define SPI_CMD1_MODE_MASK		0x3
+#define SPI_CMD1_MODE_MASK		GENMASK(1, 0)
 #define SPI_CMD1_MODE_SHIFT		28
-#define SPI_CMD1_CS_SEL_MASK		0x3
+#define SPI_CMD1_CS_SEL_MASK		GENMASK(1, 0)
 #define SPI_CMD1_CS_SEL_SHIFT		26
 #define SPI_CMD1_CS_POL_INACTIVE3	BIT(25)
 #define SPI_CMD1_CS_POL_INACTIVE2	BIT(24)
@@ -45,7 +45,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define SPI_CMD1_CS_POL_INACTIVE0	BIT(22)
 #define SPI_CMD1_CS_SW_HW		BIT(21)
 #define SPI_CMD1_CS_SW_VAL		BIT(20)
-#define SPI_CMD1_IDLE_SDA_MASK		0x3
+#define SPI_CMD1_IDLE_SDA_MASK		GENMASK(1, 0)
 #define SPI_CMD1_IDLE_SDA_SHIFT		18
 #define SPI_CMD1_BIDIR			BIT(17)
 #define SPI_CMD1_LSBI_FE		BIT(16)
@@ -55,14 +55,14 @@ DECLARE_GLOBAL_DATA_PTR;
 #define SPI_CMD1_RX_EN			BIT(12)
 #define SPI_CMD1_TX_EN			BIT(11)
 #define SPI_CMD1_PACKED			BIT(5)
-#define SPI_CMD1_BIT_LEN_MASK		0x1F
+#define SPI_CMD1_BIT_LEN_MASK		GENMASK(4, 0)
 #define SPI_CMD1_BIT_LEN_SHIFT		0
 
 /* COMMAND2 */
 #define SPI_CMD2_TX_CLK_TAP_DELAY	BIT(6)
-#define SPI_CMD2_TX_CLK_TAP_DELAY_MASK	(0x3F << 6)
+#define SPI_CMD2_TX_CLK_TAP_DELAY_MASK	GENMASK(11, 6)
 #define SPI_CMD2_RX_CLK_TAP_DELAY	BIT(0)
-#define SPI_CMD2_RX_CLK_TAP_DELAY_MASK	(0x3F << 0)
+#define SPI_CMD2_RX_CLK_TAP_DELAY_MASK	GENMASK(5, 0)
 
 /* TRANSFER STATUS */
 #define SPI_XFER_STS_RDY		BIT(30)
diff --git a/drivers/spi/tegra20_sflash.c b/drivers/spi/tegra20_sflash.c
index 5dc196b..6888a96 100644
--- a/drivers/spi/tegra20_sflash.c
+++ b/drivers/spi/tegra20_sflash.c
@@ -37,7 +37,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define SPI_CMD_CS1_EN			BIT(6)
 #define SPI_CMD_CS0_EN			BIT(5)
 #define SPI_CMD_BIT_LENGTH		BIT(4)
-#define SPI_CMD_BIT_LENGTH_MASK		0x0000001F
+#define SPI_CMD_BIT_LENGTH_MASK		GENMASK(4, 0)
 
 #define SPI_STAT_BSY			BIT(31)
 #define SPI_STAT_RDY			BIT(30)
diff --git a/drivers/spi/tegra20_slink.c b/drivers/spi/tegra20_slink.c
index d1abac2..43054f1 100644
--- a/drivers/spi/tegra20_slink.c
+++ b/drivers/spi/tegra20_slink.c
@@ -46,13 +46,13 @@ DECLARE_GLOBAL_DATA_PTR;
 #define SLINK_CMD_CS_VAL		BIT(12)
 #define SLINK_CMD_CS_SOFT		BIT(11)
 #define SLINK_CMD_BIT_LENGTH		BIT(4)
-#define SLINK_CMD_BIT_LENGTH_MASK	0x0000001F
+#define SLINK_CMD_BIT_LENGTH_MASK	GENMASK(4, 0)
 /* COMMAND2 */
 #define SLINK_CMD2_TXEN			BIT(30)
 #define SLINK_CMD2_RXEN			BIT(31)
 #define SLINK_CMD2_SS_EN		BIT(18)
 #define SLINK_CMD2_SS_EN_SHIFT		18
-#define SLINK_CMD2_SS_EN_MASK		0x000C0000
+#define SLINK_CMD2_SS_EN_MASK		GENMASK(19, 18)
 #define SLINK_CMD2_CS_ACTIVE_BETWEEN	BIT(17)
 /* STATUS */
 #define SLINK_STAT_BSY			BIT(31)
-- 
1.9.1

[U-Boot] [PATCH v4 24/24] spi: xilinx_spi: Use GENMASK

[Jagan Teki]

Replace numeric mask hexcodes with GENMASK macro in xilinx_spi

Cc: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
---
 drivers/spi/xilinx_spi.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
index 7620163..0713714 100644
--- a/drivers/spi/xilinx_spi.c
+++ b/drivers/spi/xilinx_spi.c
@@ -52,14 +52,14 @@
 #define SPISR_RX_EMPTY		BIT(0)
 
 /* SPI Data Transmit Register (spidtr), [1] p12, [2] p12 */
-#define SPIDTR_8BIT_MASK	(0xff << 0)
-#define SPIDTR_16BIT_MASK	(0xffff << 0)
-#define SPIDTR_32BIT_MASK	(0xffffffff << 0)
+#define SPIDTR_8BIT_MASK	GENMASK(7, 0)
+#define SPIDTR_16BIT_MASK	GENMASK(15, 0)
+#define SPIDTR_32BIT_MASK	GENMASK(31, 0)
 
 /* SPI Data Receive Register (spidrr), [1] p12, [2] p12 */
-#define SPIDRR_8BIT_MASK	(0xff << 0)
-#define SPIDRR_16BIT_MASK	(0xffff << 0)
-#define SPIDRR_32BIT_MASK	(0xffffffff << 0)
+#define SPIDRR_8BIT_MASK	GENMASK(7, 0)
+#define SPIDRR_16BIT_MASK	GENMASK(15, 0)
+#define SPIDRR_32BIT_MASK	GENMASK(31, 0)
 
 /* SPI Slave Select Register (spissr), [1] p13, [2] p13 */
 #define SPISSR_MASK(cs)		(1 << (cs))
@@ -75,7 +75,7 @@
 #define XILSPI_SPICR_DFLT_OFF	(SPICR_MASTER_INHIBIT | SPICR_MANUAL_SS)
 
 #ifndef CONFIG_XILINX_SPI_IDLE_VAL
-#define CONFIG_XILINX_SPI_IDLE_VAL	0xff
+#define CONFIG_XILINX_SPI_IDLE_VAL	GENMASK(7, 0)
 #endif
 
 #ifndef CONFIG_SYS_XILINX_SPI_LIST
-- 
1.9.1

[U-Boot] [PATCH v4 21/24] spi: mxs_spi: Use GENMASK

[Fabio Estevam]

On Thu, Oct 22, 2015 at 6:50 PM, Jagan Teki <jteki@openedev.com> wrote:
> Replace numeric mask hexcodes with GENMASK macro in mxs_spi
>
> Cc: Marek Vasut <marex@denx.de>
> Signed-off-by: Jagan Teki <jteki@openedev.com>
> ---
>  drivers/spi/mxs_spi.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c
> index 627644b..459c603 100644
> --- a/drivers/spi/mxs_spi.c
> +++ b/drivers/spi/mxs_spi.c
> @@ -23,7 +23,7 @@
>
>  #define        MXS_SPI_MAX_TIMEOUT     1000000
>  #define        MXS_SPI_PORT_OFFSET     0x2000
> -#define MXS_SSP_CHIPSELECT_MASK                0x00300000
> +#define MXS_SSP_CHIPSELECT_MASK                GENMASK(21, 20)

Does this really improve the code?

Personally I prefer the original code as I don't need to go and look
at the definition of the GENMASK() macro.

[U-Boot] [PATCH v4 18/24] spi: cadence_qspi_apb: Use GENMASK

[Fabio Estevam]

On Thu, Oct 22, 2015 at 6:50 PM, Jagan Teki <jteki@openedev.com> wrote:

>         reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
> @@ -719,7 +719,7 @@ int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
>  #if defined(CONFIG_SPL_SPI_XIP) && defined(CONFIG_SPL_BUILD)
>                 writel(0x0, plat->regbase + CQSPI_REG_MODE_BIT);
>  #else
> -               writel(0xFF, plat->regbase + CQSPI_REG_MODE_BIT);
> +               writel(GENMASK(7, 0), plat->regbase + CQSPI_REG_MODE_BIT);

Is the 0xFF really a mask here? It seems it is just writing 0xFF to
the register directly without any masking operation.

[U-Boot] [PATCH v4 21/24] spi: mxs_spi: Use GENMASK

[Jagan Teki]

On 23 October 2015 at 02:38, Fabio Estevam <festevam@gmail.com> wrote:
> On Thu, Oct 22, 2015 at 6:50 PM, Jagan Teki <jteki@openedev.com> wrote:
>> Replace numeric mask hexcodes with GENMASK macro in mxs_spi
>>
>> Cc: Marek Vasut <marex@denx.de>
>> Signed-off-by: Jagan Teki <jteki@openedev.com>
>> ---
>>  drivers/spi/mxs_spi.c | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c
>> index 627644b..459c603 100644
>> --- a/drivers/spi/mxs_spi.c
>> +++ b/drivers/spi/mxs_spi.c
>> @@ -23,7 +23,7 @@
>>
>>  #define        MXS_SPI_MAX_TIMEOUT     1000000
>>  #define        MXS_SPI_PORT_OFFSET     0x2000
>> -#define MXS_SSP_CHIPSELECT_MASK                0x00300000
>> +#define MXS_SSP_CHIPSELECT_MASK                GENMASK(21, 20)
>
> Does this really improve the code?

GENMASK will simplificate the bit masking and most of drivers in Linux
start using this along with BIT for bit shifting.

>
> Personally I prefer the original code as I don't need to go and look
> at the definition of the GENMASK() macro.

-- 
Jagan | openedev.

[U-Boot] [PATCH v4 21/24] spi: mxs_spi: Use GENMASK

[Fabio Estevam]

On Thu, Oct 22, 2015 at 7:15 PM, Jagan Teki <jteki@openedev.com> wrote:

>>>  #define        MXS_SPI_MAX_TIMEOUT     1000000
>>>  #define        MXS_SPI_PORT_OFFSET     0x2000
>>> -#define MXS_SSP_CHIPSELECT_MASK                0x00300000
>>> +#define MXS_SSP_CHIPSELECT_MASK                GENMASK(21, 20)
>>
>> Does this really improve the code?
>
> GENMASK will simplificate the bit masking and most of drivers in Linux
> start using this along with BIT for bit shifting.

Most drivers?

In mainline kernel:

git grep GENMASK drivers/spi/ | wc -l
2

No, this is not most drivers ;-)

[U-Boot] [PATCH v4 01/24] spi: zynq_[q]spi: Use BIT macro

[Tom Rini]

On Fri, Oct 23, 2015 at 02:20:01AM +0530, Jagan Teki wrote:

> Used BIT macro on zynq_spi.c and zynq_qspi.c
> 
> :%s/(1 << nr)/BIT(nr)/g
> where nr = 0, 1, 2 .... 31
> 
> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
> Cc: Michal Simek <michal.simek@xilinx.com>
> Signed-off-by: Jagan Teki <jteki@openedev.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH v4 04/24] spi: atmel_spi: Use BIT macro

[Tom Rini]

On Fri, Oct 23, 2015 at 02:20:04AM +0530, Jagan Teki wrote:

> Replace numerical bit shift with BIT macro in atmel_spi
> 
> :%s/(1 << nr)/BIT(nr)/g
> where nr = 0, 1, 2 .... 31
> 
> Cc: Bo Shen <voice.shen@atmel.com>
> Signed-off-by: Jagan Teki <jteki@openedev.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH v4 03/24] spi: altera_spi: Use BIT macro

[Tom Rini]

On Fri, Oct 23, 2015 at 02:20:03AM +0530, Jagan Teki wrote:

> Replace numerical bit shift with BIT macro in altera_spi
> 
> :%s/(1 << nr)/BIT(nr)/g
> where nr = 0, 1, 2 .... 31
> 
> Cc: Marek Vasut <marex@denx.de>
> Signed-off-by: Jagan Teki <jteki@openedev.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH v4 05/24] spi: bfin_spi6xx: Use BIT macro

[Tom Rini]

On Fri, Oct 23, 2015 at 02:20:05AM +0530, Jagan Teki wrote:

> Replace numerical bit shift with BIT macro in bfin_spi6xx
> 
> :%s/(1 << nr)/BIT(nr)/g
> where nr = 0, 1, 2 .... 31
> 
> Signed-off-by: Jagan Teki <jteki@openedev.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH v4 06/24] spi: cadence_qspi_apb: Use BIT macro

[Tom Rini]

On Fri, Oct 23, 2015 at 02:20:06AM +0530, Jagan Teki wrote:

> Replace numerical bit shift with BIT macro in cadence_qspi_apb
> 
> :%s/(1 << nr)/BIT(nr)/g
> where nr = 0, 1, 2 .... 31
> 
> Cc: Stefan Roese <sr@denx.de>
> Cc: Vikas Manocha <vikas.manocha@st.com>
> Cc: Marek Vasut <marex@denx.de>
> Signed-off-by: Jagan Teki <jteki@openedev.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH v4 08/24] spi: exynos_spi: Use BIT macro

[Tom Rini]

On Fri, Oct 23, 2015 at 02:20:08AM +0530, Jagan Teki wrote:

> Replace numerical bit shift with BIT macro in exynos_spi
> 
> :%s/(1 << nr)/BIT(nr)/g
> where nr = 0, 1, 2 .... 31
> 
> Cc: Simon Glass <sjg@chromium.org>
> Signed-off-by: Jagan Teki <jteki@openedev.com>
> ---
>  drivers/spi/exynos_spi.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/spi/exynos_spi.c b/drivers/spi/exynos_spi.c
> index 44948c3..ea3c51d 100644
> --- a/drivers/spi/exynos_spi.c
> +++ b/drivers/spi/exynos_spi.c
> @@ -86,7 +86,7 @@ static void spi_request_bytes(struct exynos_spi *regs, int count, int step)
>  		writel(0, &regs->swap_cfg);
>  	}
>  
> -	assert(count && count < (1 << 16));
> +	assert(count && count < BIT(16));
>  	setbits_le32(&regs->ch_cfg, SPI_CH_RST);
>  	clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
>  
> @@ -345,7 +345,7 @@ static int exynos_spi_xfer(struct udevice *dev, unsigned int bitlen,
>  	 */
>  	bytelen = bitlen / 8;
>  	for (upto = 0; !ret && upto < bytelen; upto += todo) {
> -		todo = min(bytelen - upto, (1 << 16) - 4);
> +		todo = min(bytelen - upto, BIT(16) - 4);
>  		ret = spi_rx_tx(priv, todo, &din, &dout, flags);
>  		if (ret)
>  			break;

These look like (1 << 16) is a size, not a bit.  Can you read the
functions in context and confirm that it really is bit 16 here, rather
than 4KiB (0x10000) ?

> -- 
> 1.9.1
> 
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot

-- 
Tom
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[U-Boot] [PATCH v4 10/24] spi: ich: Use BIT macro

[Tom Rini]

On Fri, Oct 23, 2015 at 02:20:10AM +0530, Jagan Teki wrote:

> Replace numerical bit shift with BIT macro in ich
> 
> :%s/(1 << nr)/BIT(nr)/g
> where nr = 0, 1, 2 .... 31
> 
> Cc: Simon Glass <sjg@chromium.org>
> Signed-off-by: Jagan Teki <jteki@openedev.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH v4 09/24] spi: fsl: Use BIT macro

[Tom Rini]

On Fri, Oct 23, 2015 at 02:20:09AM +0530, Jagan Teki wrote:

> Replace numerical bit shift with BIT macro in fsl_*spi.c
> 
> :%s/(1 << nr)/BIT(nr)/g
> where nr = 0, 1, 2 .... 31
> 
> Cc: York Sun <yorksun@freescale.com>
> Cc: Haikun Wang <Haikun.Wang@freescale.com>
> Signed-off-by: Jagan Teki <jteki@openedev.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH v4 11/24] spi: mpc8xxx_spi: Use BIT macro

[Tom Rini]

On Fri, Oct 23, 2015 at 02:20:11AM +0530, Jagan Teki wrote:

> Replace numerical bit shift with BIT macro in mpc8xxx_spi
> 
> :%s/(1 << nr)/BIT(nr)/g
> where nr = 0, 1, 2 .... 31
> 
> Signed-off-by: Jagan Teki <jteki@openedev.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH v4 12/24] spi: omap3_spi: Use BIT macro

[Tom Rini]

On Fri, Oct 23, 2015 at 02:20:12AM +0530, Jagan Teki wrote:

> Replace numerical bit shift with BIT macro in omap3_spi
> 
> :%s/(1 << nr)/BIT(nr)/g
> where nr = 0, 1, 2 .... 31
> 
> Cc: Nikita Kiryanov <nikita@compulab.co.il>
> Cc: Tom Rini <trini@konsulko.com>
> Signed-off-by: Jagan Teki <jteki@openedev.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH v4 13/24] spi: sh_qspi: Use BIT macro

[Tom Rini]

On Fri, Oct 23, 2015 at 02:20:13AM +0530, Jagan Teki wrote:

> Replace numerical bit shift with BIT macro in sh_qspi
> 
> :%s/(1 << nr)/BIT(nr)/g
> where nr = 0, 1, 2 .... 31
> 
> Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
> Signed-off-by: Jagan Teki <jteki@openedev.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH v4 14/24] spi: tegra: Use BIT macro

[Tom Rini]

On Fri, Oct 23, 2015 at 02:20:14AM +0530, Jagan Teki wrote:

> Replace numerical bit shift with BIT macro in tegra*.c
> 
> :%s/(1 << nr)/BIT(nr)/g
> where nr = 0, 1, 2 .... 31
> 
> Cc: Stephen Warren <swarren@wwwdotorg.org>
> Cc: Tom Warren <twarren@nvidia.com>
> Signed-off-by: Jagan Teki <jteki@openedev.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH v4 15/24] spi: ti_qspi: Use BIT macro

[Tom Rini]

On Fri, Oct 23, 2015 at 02:20:15AM +0530, Jagan Teki wrote:

> Replace numerical bit shift with BIT macro in ti_qspi
> 
> :%s/(1 << nr)/BIT(nr)/g
> where nr = 0, 1, 2 .... 31
> 
> Cc: Tom Rini <trini@konsulko.com>
> Cc: Vignesh R <vigneshr@ti.com>
> Signed-off-by: Jagan Teki <jteki@openedev.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH v4 16/24] spi: xilinx_spi: Use BIT macro

[Tom Rini]

On Fri, Oct 23, 2015 at 02:20:16AM +0530, Jagan Teki wrote:

> Replace numerical bit shift with BIT macro in xilinx_spi
> 
> :%s/(1 << nr)/BIT(nr)/g
> where nr = 0, 1, 2 .... 31
> 
> Cc: Michal Simek <michal.simek@xilinx.com>
> Signed-off-by: Jagan Teki <jteki@openedev.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH v4 17/24] spi: atmel_spi: Use GENMASK

[Tom Rini]

On Fri, Oct 23, 2015 at 02:20:17AM +0530, Jagan Teki wrote:

> Replace numeric mask hexcodes with GENMASK macro in atmel_spi
> 
> Cc: Bo Shen <voice.shen@atmel.com>
> Signed-off-by: Jagan Teki <jteki@openedev.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH v4 19/24] spi: designware_spi: Use GENMASK

[Tom Rini]

On Fri, Oct 23, 2015 at 02:20:19AM +0530, Jagan Teki wrote:

> Replace numeric mask hexcodes with GENMASK macro in designware_spi
> 
> Cc: Stefan Roese <sr@denx.de>
> Cc: Marek Vasut <marex@denx.de>
> Signed-off-by: Jagan Teki <jteki@openedev.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH v4 22/24] spi: omap3_spi: Use GENMASK

[Tom Rini]

On Fri, Oct 23, 2015 at 02:20:22AM +0530, Jagan Teki wrote:

> Replace numeric mask hexcodes with GENMASK macro in omap3_spi
> 
> Cc: Nikita Kiryanov <nikita@compulab.co.il>
> Cc: Tom Rini <trini@konsulko.com>
> Signed-off-by: Jagan Teki <jteki@openedev.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH v4 21/24] spi: mxs_spi: Use GENMASK

[Tom Rini]

On Thu, Oct 22, 2015 at 07:08:32PM -0200, Fabio Estevam wrote:
> On Thu, Oct 22, 2015 at 6:50 PM, Jagan Teki <jteki@openedev.com> wrote:
> > Replace numeric mask hexcodes with GENMASK macro in mxs_spi
> >
> > Cc: Marek Vasut <marex@denx.de>
> > Signed-off-by: Jagan Teki <jteki@openedev.com>
> > ---
> >  drivers/spi/mxs_spi.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c
> > index 627644b..459c603 100644
> > --- a/drivers/spi/mxs_spi.c
> > +++ b/drivers/spi/mxs_spi.c
> > @@ -23,7 +23,7 @@
> >
> >  #define        MXS_SPI_MAX_TIMEOUT     1000000
> >  #define        MXS_SPI_PORT_OFFSET     0x2000
> > -#define MXS_SSP_CHIPSELECT_MASK                0x00300000
> > +#define MXS_SSP_CHIPSELECT_MASK                GENMASK(21, 20)
> 
> Does this really improve the code?
> 
> Personally I prefer the original code as I don't need to go and look
> at the definition of the GENMASK() macro.

Fair point.  This is a kernel helper macro but it's "new" and still
gaining traction.  I personally do find GENMASK(hi, lo) and BIT(x) more
readable.  Others don't.  That's fine.  The question I have here is, who
is spending the most time in these drivers?

-- 
Tom
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[U-Boot] [PATCH v4 18/24] spi: cadence_qspi_apb: Use GENMASK

[Tom Rini]

On Thu, Oct 22, 2015 at 07:10:17PM -0200, Fabio Estevam wrote:
> On Thu, Oct 22, 2015 at 6:50 PM, Jagan Teki <jteki@openedev.com> wrote:
> 
> >         reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
> > @@ -719,7 +719,7 @@ int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
> >  #if defined(CONFIG_SPL_SPI_XIP) && defined(CONFIG_SPL_BUILD)
> >                 writel(0x0, plat->regbase + CQSPI_REG_MODE_BIT);
> >  #else
> > -               writel(0xFF, plat->regbase + CQSPI_REG_MODE_BIT);
> > +               writel(GENMASK(7, 0), plat->regbase + CQSPI_REG_MODE_BIT);
> 
> Is the 0xFF really a mask here? It seems it is just writing 0xFF to
> the register directly without any masking operation.

Indeed, with context on the #else side it looks like an old fashioned
"clear everything with magic value" which I suppose might technically be
the bitmask but it's not helping with clarity in this case.

-- 
Tom
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[U-Boot] [PATCH v4 00/24] spi: Use BIT and GENMASK

[Tom Rini]

On Fri, Oct 23, 2015 at 02:20:00AM +0530, Jagan Teki wrote:

> This series replaces numerical bit shitfts and mask values
> with BIT and GENMASK macro's
> 
> Changes for v4:
> - Patch split for individual drivers.
> Changes for v3, v2:
> - none

For the GENMASK changes, how did you do the conversion?  I only
reviewed-by the OMAP ones since I pulled out printf and manually
confirmed each change.

-- 
Tom
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[U-Boot] [PATCH v4 21/24] spi: mxs_spi: Use GENMASK

[Marek Vasut]

On Thursday, October 22, 2015 at 11:15:26 PM, Jagan Teki wrote:
> On 23 October 2015 at 02:38, Fabio Estevam <festevam@gmail.com> wrote:
> > On Thu, Oct 22, 2015 at 6:50 PM, Jagan Teki <jteki@openedev.com> wrote:
> >> Replace numeric mask hexcodes with GENMASK macro in mxs_spi
> >> 
> >> Cc: Marek Vasut <marex@denx.de>
> >> Signed-off-by: Jagan Teki <jteki@openedev.com>
> >> ---
> >> 
> >>  drivers/spi/mxs_spi.c | 2 +-
> >>  1 file changed, 1 insertion(+), 1 deletion(-)
> >> 
> >> diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c
> >> index 627644b..459c603 100644
> >> --- a/drivers/spi/mxs_spi.c
> >> +++ b/drivers/spi/mxs_spi.c
> >> @@ -23,7 +23,7 @@
> >> 
> >>  #define        MXS_SPI_MAX_TIMEOUT     1000000
> >>  #define        MXS_SPI_PORT_OFFSET     0x2000
> >> 
> >> -#define MXS_SSP_CHIPSELECT_MASK                0x00300000
> >> +#define MXS_SSP_CHIPSELECT_MASK                GENMASK(21, 20)
> > 
> > Does this really improve the code?
> 
> GENMASK will simplificate

You mean [1] ? :-) In that case, I agree ...
"
simplificate

verb - the action of taking an answered that is simplified and extending the 
answer to the point of complete and utter obscurity, unreadable by anyone, yet 
still correct.

See also: BS 
"

[1] http://cs.urbandictionary.com/define.php?term=simplificate&defid=2897356

> the bit masking and most of drivers in Linux
> start using this along with BIT for bit shifting.
> 
> > Personally I prefer the original code as I don't need to go and look
> > at the definition of the GENMASK() macro.

Best regards,
Marek Vasut

[U-Boot] [PATCH v4 21/24] spi: mxs_spi: Use GENMASK

[Jagan Teki]

On 23 October 2015 at 02:48, Fabio Estevam <festevam@gmail.com> wrote:
> On Thu, Oct 22, 2015 at 7:15 PM, Jagan Teki <jteki@openedev.com> wrote:
>
>>>>  #define        MXS_SPI_MAX_TIMEOUT     1000000
>>>>  #define        MXS_SPI_PORT_OFFSET     0x2000
>>>> -#define MXS_SSP_CHIPSELECT_MASK                0x00300000
>>>> +#define MXS_SSP_CHIPSELECT_MASK                GENMASK(21, 20)
>>>
>>> Does this really improve the code?
>>
>> GENMASK will simplificate the bit masking and most of drivers in Linux
>> start using this along with BIT for bit shifting.
>
> Most drivers?

Most drivers will include all drivers in Linux not only spi drivers.

>
> In mainline kernel:
>
> git grep GENMASK drivers/spi/ | wc -l
> 2

# grep -R GENMASK drivers/ | wc -l
465

>
> No, this is not most drivers ;-)

-- 
Jagan | openedev.

[U-Boot] [PATCH v4 21/24] spi: mxs_spi: Use GENMASK

[Jagan Teki]

On 23 October 2015 at 03:00, Marek Vasut <marex@denx.de> wrote:
> On Thursday, October 22, 2015 at 11:15:26 PM, Jagan Teki wrote:
>> On 23 October 2015 at 02:38, Fabio Estevam <festevam@gmail.com> wrote:
>> > On Thu, Oct 22, 2015 at 6:50 PM, Jagan Teki <jteki@openedev.com> wrote:
>> >> Replace numeric mask hexcodes with GENMASK macro in mxs_spi
>> >>
>> >> Cc: Marek Vasut <marex@denx.de>
>> >> Signed-off-by: Jagan Teki <jteki@openedev.com>
>> >> ---
>> >>
>> >>  drivers/spi/mxs_spi.c | 2 +-
>> >>  1 file changed, 1 insertion(+), 1 deletion(-)
>> >>
>> >> diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c
>> >> index 627644b..459c603 100644
>> >> --- a/drivers/spi/mxs_spi.c
>> >> +++ b/drivers/spi/mxs_spi.c
>> >> @@ -23,7 +23,7 @@
>> >>
>> >>  #define        MXS_SPI_MAX_TIMEOUT     1000000
>> >>  #define        MXS_SPI_PORT_OFFSET     0x2000
>> >>
>> >> -#define MXS_SSP_CHIPSELECT_MASK                0x00300000
>> >> +#define MXS_SSP_CHIPSELECT_MASK                GENMASK(21, 20)
>> >
>> > Does this really improve the code?
>>
>> GENMASK will simplificate
>
> You mean [1] ? :-) In that case, I agree ...
> "
> simplificate

I just used simplificate as per the sentence formation which I would
it's reasonable. Look like simplificate similar to simplify [1]

[1] http://www.dictionarist.com/english-english/simplificate

>
> verb - the action of taking an answered that is simplified and extending the
> answer to the point of complete and utter obscurity, unreadable by anyone, yet
> still correct.
>
> See also: BS
> "
>
> [1] http://cs.urbandictionary.com/define.php?term=simplificate&defid=2897356
>
>> the bit masking and most of drivers in Linux
>> start using this along with BIT for bit shifting.
>>
>> > Personally I prefer the original code as I don't need to go and look
>> > at the definition of the GENMASK() macro.

-- 
Jagan | openedev.

[U-Boot] [PATCH v4 00/24] spi: Use BIT and GENMASK

[Jagan Teki]

On 23 October 2015 at 02:55, Tom Rini <trini@konsulko.com> wrote:
> On Fri, Oct 23, 2015 at 02:20:00AM +0530, Jagan Teki wrote:
>
>> This series replaces numerical bit shitfts and mask values
>> with BIT and GENMASK macro's
>>
>> Changes for v4:
>> - Patch split for individual drivers.
>> Changes for v3, v2:
>> - none
>
> For the GENMASK changes, how did you do the conversion?  I only
> reviewed-by the OMAP ones since I pulled out printf and manually
> confirmed each change.

Did it manually based on the bit masks' but these were verified on armv7 system.

--  Jagan | openedev.

[U-Boot] [PATCH v4 06/24] spi: cadence_qspi_apb: Use BIT macro

[Vikas MANOCHA]

Thanks Jagan for this patch.

Acked-by: vikas.manocha at st.com

Rgds,
Vikas

> -----Original Message-----
> From: Jagan Teki [mailto:jteki at openedev.com]
> Sent: Thursday, October 22, 2015 1:50 PM
> To: u-boot at lists.denx.de
> Cc: Jagan Teki; Stefan Roese; Vikas MANOCHA; Marek Vasut
> Subject: [PATCH v4 06/24] spi: cadence_qspi_apb: Use BIT macro
> 
> Replace numerical bit shift with BIT macro in cadence_qspi_apb
> 
> :%s/(1 << nr)/BIT(nr)/g
> where nr = 0, 1, 2 .... 31
> 
> Cc: Stefan Roese <sr@denx.de>
> Cc: Vikas Manocha <vikas.manocha@st.com>
> Cc: Marek Vasut <marex@denx.de>
> Signed-off-by: Jagan Teki <jteki@openedev.com>
> ---
>  drivers/spi/cadence_qspi_apb.c | 28 ++++++++++++++--------------
>  1 file changed, 14 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/spi/cadence_qspi_apb.c
> b/drivers/spi/cadence_qspi_apb.c index d053407..7786dd6 100644
> --- a/drivers/spi/cadence_qspi_apb.c
> +++ b/drivers/spi/cadence_qspi_apb.c
> @@ -58,10 +58,10 @@
>  #define	CQSPI_REG_CONFIG			0x00
>  #define	CQSPI_REG_CONFIG_CLK_POL_LSB		1
>  #define	CQSPI_REG_CONFIG_CLK_PHA_LSB		2
> -#define	CQSPI_REG_CONFIG_ENABLE_MASK		(1 << 0)
> -#define	CQSPI_REG_CONFIG_DIRECT_MASK		(1 << 7)
> -#define	CQSPI_REG_CONFIG_DECODE_MASK		(1 << 9)
> -#define	CQSPI_REG_CONFIG_XIP_IMM_MASK		(1 << 18)
> +#define	CQSPI_REG_CONFIG_ENABLE_MASK		BIT(0)
> +#define	CQSPI_REG_CONFIG_DIRECT_MASK		BIT(7)
> +#define	CQSPI_REG_CONFIG_DECODE_MASK		BIT(9)
> +#define	CQSPI_REG_CONFIG_XIP_IMM_MASK		BIT(18)
>  #define	CQSPI_REG_CONFIG_CHIPSELECT_LSB		10
>  #define	CQSPI_REG_CONFIG_BAUD_LSB		19
>  #define	CQSPI_REG_CONFIG_IDLE_LSB		31
> @@ -122,18 +122,18 @@
>  #define	CQSPI_REG_IRQMASK			0x44
> 
>  #define	CQSPI_REG_INDIRECTRD			0x60
> -#define	CQSPI_REG_INDIRECTRD_START_MASK		(1 <<
> 0)
> -#define	CQSPI_REG_INDIRECTRD_CANCEL_MASK	(1 << 1)
> -#define	CQSPI_REG_INDIRECTRD_INPROGRESS_MASK	(1 << 2)
> -#define	CQSPI_REG_INDIRECTRD_DONE_MASK		(1 <<
> 5)
> +#define	CQSPI_REG_INDIRECTRD_START_MASK		BIT(0)
> +#define	CQSPI_REG_INDIRECTRD_CANCEL_MASK	BIT(1)
> +#define	CQSPI_REG_INDIRECTRD_INPROGRESS_MASK	BIT(2)
> +#define	CQSPI_REG_INDIRECTRD_DONE_MASK		BIT(5)
> 
>  #define	CQSPI_REG_INDIRECTRDWATERMARK		0x64
>  #define	CQSPI_REG_INDIRECTRDSTARTADDR		0x68
>  #define	CQSPI_REG_INDIRECTRDBYTES		0x6C
> 
>  #define	CQSPI_REG_CMDCTRL			0x90
> -#define	CQSPI_REG_CMDCTRL_EXECUTE_MASK		(1 <<
> 0)
> -#define	CQSPI_REG_CMDCTRL_INPROGRESS_MASK	(1 << 1)
> +#define	CQSPI_REG_CMDCTRL_EXECUTE_MASK		BIT(0)
> +#define	CQSPI_REG_CMDCTRL_INPROGRESS_MASK	BIT(1)
>  #define	CQSPI_REG_CMDCTRL_DUMMY_LSB		7
>  #define	CQSPI_REG_CMDCTRL_WR_BYTES_LSB		12
>  #define	CQSPI_REG_CMDCTRL_WR_EN_LSB		15
> @@ -149,10 +149,10 @@
>  #define	CQSPI_REG_CMDCTRL_OPCODE_MASK		0xFF
> 
>  #define	CQSPI_REG_INDIRECTWR			0x70
> -#define	CQSPI_REG_INDIRECTWR_START_MASK		(1 <<
> 0)
> -#define	CQSPI_REG_INDIRECTWR_CANCEL_MASK	(1 << 1)
> -#define	CQSPI_REG_INDIRECTWR_INPROGRESS_MASK	(1 <<
> 2)
> -#define	CQSPI_REG_INDIRECTWR_DONE_MASK		(1 <<
> 5)
> +#define	CQSPI_REG_INDIRECTWR_START_MASK		BIT(0)
> +#define	CQSPI_REG_INDIRECTWR_CANCEL_MASK	BIT(1)
> +#define	CQSPI_REG_INDIRECTWR_INPROGRESS_MASK	BIT(2)
> +#define	CQSPI_REG_INDIRECTWR_DONE_MASK		BIT(5)
> 
>  #define	CQSPI_REG_INDIRECTWRWATERMARK		0x74
>  #define	CQSPI_REG_INDIRECTWRSTARTADDR		0x78
> --
> 1.9.1

[U-Boot] [PATCH v4 18/24] spi: cadence_qspi_apb: Use GENMASK

[Vikas MANOCHA]

Acked-by: vikas.manocha at st.com

Rgds,
Vikas

> -----Original Message-----
> From: Jagan Teki [mailto:jteki at openedev.com]
> Sent: Thursday, October 22, 2015 1:50 PM
> To: u-boot at lists.denx.de
> Cc: Jagan Teki; Stefan Roese; Vikas MANOCHA; Marek Vasut
> Subject: [PATCH v4 18/24] spi: cadence_qspi_apb: Use GENMASK
> 
> Replace numeric mask hexcodes with GENMASK macro in cadence_qspi_apb
> 
> Cc: Stefan Roese <sr@denx.de>
> Cc: Vikas Manocha <vikas.manocha@st.com>
> Cc: Marek Vasut <marex@denx.de>
> Signed-off-by: Jagan Teki <jteki@openedev.com>
> ---
>  drivers/spi/cadence_qspi_apb.c | 48 +++++++++++++++++++++--------------
> -------
>  1 file changed, 24 insertions(+), 24 deletions(-)
> 
> diff --git a/drivers/spi/cadence_qspi_apb.c
> b/drivers/spi/cadence_qspi_apb.c index 7786dd6..31e14ee 100644
> --- a/drivers/spi/cadence_qspi_apb.c
> +++ b/drivers/spi/cadence_qspi_apb.c
> @@ -44,7 +44,7 @@
>  #define CQSPI_INST_TYPE_QUAD			(2)
> 
>  #define CQSPI_STIG_DATA_LEN_MAX			(8)
> -#define CQSPI_INDIRECTTRIGGER_ADDR_MASK		(0xFFFFF)
> +#define CQSPI_INDIRECTTRIGGER_ADDR_MASK
> 	GENMASK(19, 0)
> 
>  #define CQSPI_DUMMY_CLKS_PER_BYTE		(8)
>  #define CQSPI_DUMMY_BYTES_MAX			(4)
> @@ -65,8 +65,8 @@
>  #define	CQSPI_REG_CONFIG_CHIPSELECT_LSB		10
>  #define	CQSPI_REG_CONFIG_BAUD_LSB		19
>  #define	CQSPI_REG_CONFIG_IDLE_LSB		31
> -#define	CQSPI_REG_CONFIG_CHIPSELECT_MASK	0xF
> -#define	CQSPI_REG_CONFIG_BAUD_MASK		0xF
> +#define	CQSPI_REG_CONFIG_CHIPSELECT_MASK	GENMASK(3,
> 0)
> +#define	CQSPI_REG_CONFIG_BAUD_MASK		GENMASK(3,
> 0)
> 
>  #define	CQSPI_REG_RD_INSTR			0x04
>  #define	CQSPI_REG_RD_INSTR_OPCODE_LSB		0
> @@ -75,10 +75,10 @@
>  #define	CQSPI_REG_RD_INSTR_TYPE_DATA_LSB	16
>  #define	CQSPI_REG_RD_INSTR_MODE_EN_LSB		20
>  #define	CQSPI_REG_RD_INSTR_DUMMY_LSB		24
> -#define	CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK	0x3
> -#define	CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK	0x3
> -#define	CQSPI_REG_RD_INSTR_TYPE_DATA_MASK	0x3
> -#define	CQSPI_REG_RD_INSTR_DUMMY_MASK		0x1F
> +#define	CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK	GENMASK(1,
> 0)
> +#define	CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK	GENMASK(1,
> 0)
> +#define	CQSPI_REG_RD_INSTR_TYPE_DATA_MASK	GENMASK(1,
> 0)
> +#define	CQSPI_REG_RD_INSTR_DUMMY_MASK
> 	GENMASK(4, 0)
> 
>  #define	CQSPI_REG_WR_INSTR			0x08
>  #define	CQSPI_REG_WR_INSTR_OPCODE_LSB		0
> @@ -88,23 +88,23 @@
>  #define	CQSPI_REG_DELAY_TCHSH_LSB		8
>  #define	CQSPI_REG_DELAY_TSD2D_LSB		16
>  #define	CQSPI_REG_DELAY_TSHSL_LSB		24
> -#define	CQSPI_REG_DELAY_TSLCH_MASK		0xFF
> -#define	CQSPI_REG_DELAY_TCHSH_MASK		0xFF
> -#define	CQSPI_REG_DELAY_TSD2D_MASK		0xFF
> -#define	CQSPI_REG_DELAY_TSHSL_MASK		0xFF
> +#define	CQSPI_REG_DELAY_TSLCH_MASK		GENMASK(7,
> 0)
> +#define	CQSPI_REG_DELAY_TCHSH_MASK		GENMASK(7,
> 0)
> +#define	CQSPI_REG_DELAY_TSD2D_MASK		GENMASK(7,
> 0)
> +#define	CQSPI_REG_DELAY_TSHSL_MASK		GENMASK(7,
> 0)
> 
>  #define	CQSPI_READLCAPTURE			0x10
>  #define	CQSPI_READLCAPTURE_BYPASS_LSB		0
>  #define	CQSPI_READLCAPTURE_DELAY_LSB		1
> -#define	CQSPI_READLCAPTURE_DELAY_MASK		0xF
> +#define	CQSPI_READLCAPTURE_DELAY_MASK		GENMASK(3,
> 0)
> 
>  #define	CQSPI_REG_SIZE				0x14
>  #define	CQSPI_REG_SIZE_ADDRESS_LSB		0
>  #define	CQSPI_REG_SIZE_PAGE_LSB			4
>  #define	CQSPI_REG_SIZE_BLOCK_LSB		16
> -#define	CQSPI_REG_SIZE_ADDRESS_MASK		0xF
> -#define	CQSPI_REG_SIZE_PAGE_MASK		0xFFF
> -#define	CQSPI_REG_SIZE_BLOCK_MASK		0x3F
> +#define	CQSPI_REG_SIZE_ADDRESS_MASK		GENMASK(3,
> 0)
> +#define	CQSPI_REG_SIZE_PAGE_MASK		GENMASK(11, 0)
> +#define	CQSPI_REG_SIZE_BLOCK_MASK		GENMASK(5,
> 0)
> 
>  #define	CQSPI_REG_SRAMPARTITION			0x18
>  #define	CQSPI_REG_INDIRECTTRIGGER		0x1C
> @@ -115,8 +115,8 @@
>  #define	CQSPI_REG_SDRAMLEVEL			0x2C
>  #define	CQSPI_REG_SDRAMLEVEL_RD_LSB		0
>  #define	CQSPI_REG_SDRAMLEVEL_WR_LSB		16
> -#define	CQSPI_REG_SDRAMLEVEL_RD_MASK		0xFFFF
> -#define	CQSPI_REG_SDRAMLEVEL_WR_MASK		0xFFFF
> +#define	CQSPI_REG_SDRAMLEVEL_RD_MASK
> 	GENMASK(15, 0)
> +#define	CQSPI_REG_SDRAMLEVEL_WR_MASK
> 	GENMASK(15, 0)
> 
>  #define	CQSPI_REG_IRQSTATUS			0x40
>  #define	CQSPI_REG_IRQMASK			0x44
> @@ -142,11 +142,11 @@
>  #define	CQSPI_REG_CMDCTRL_RD_BYTES_LSB		20
>  #define	CQSPI_REG_CMDCTRL_RD_EN_LSB		23
>  #define	CQSPI_REG_CMDCTRL_OPCODE_LSB		24
> -#define	CQSPI_REG_CMDCTRL_DUMMY_MASK		0x1F
> -#define	CQSPI_REG_CMDCTRL_WR_BYTES_MASK		0x7
> -#define	CQSPI_REG_CMDCTRL_ADD_BYTES_MASK	0x3
> -#define	CQSPI_REG_CMDCTRL_RD_BYTES_MASK		0x7
> -#define	CQSPI_REG_CMDCTRL_OPCODE_MASK		0xFF
> +#define	CQSPI_REG_CMDCTRL_DUMMY_MASK
> 	GENMASK(4, 0)
> +#define	CQSPI_REG_CMDCTRL_WR_BYTES_MASK
> 	GENMASK(2, 0)
> +#define	CQSPI_REG_CMDCTRL_ADD_BYTES_MASK	GENMASK(1,
> 0)
> +#define	CQSPI_REG_CMDCTRL_RD_BYTES_MASK
> 	GENMASK(2, 0)
> +#define	CQSPI_REG_CMDCTRL_OPCODE_MASK
> 	GENMASK(7, 0)
> 
>  #define	CQSPI_REG_INDIRECTWR			0x70
>  #define	CQSPI_REG_INDIRECTWR_START_MASK		BIT(0)
> @@ -463,7 +463,7 @@ void cadence_qspi_apb_chipselect(void *reg_base,
>  		 * CS2 to 4b'1011
>  		 * CS3 to 4b'0111
>  		 */
> -		chip_select = 0xF & ~(1 << chip_select);
> +		chip_select = GENMASK(3, 0) & ~(1 << chip_select);
>  	}
> 
>  	reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
> @@ -719,7 +719,7 @@ int cadence_qspi_apb_indirect_read_setup(struct
> cadence_spi_platdata *plat,  #if defined(CONFIG_SPL_SPI_XIP) &&
> defined(CONFIG_SPL_BUILD)
>  		writel(0x0, plat->regbase + CQSPI_REG_MODE_BIT);  #else
> -		writel(0xFF, plat->regbase + CQSPI_REG_MODE_BIT);
> +		writel(GENMASK(7, 0), plat->regbase +
> CQSPI_REG_MODE_BIT);
>  #endif
> 
>  		/* Convert to clock cycles. */
> --
> 1.9.1

[U-Boot] [PATCH v4 18/24] spi: cadence_qspi_apb: Use GENMASK

[Jagan Teki]

On 23 October 2015 at 02:55, Tom Rini <trini@konsulko.com> wrote:
> On Thu, Oct 22, 2015 at 07:10:17PM -0200, Fabio Estevam wrote:
>> On Thu, Oct 22, 2015 at 6:50 PM, Jagan Teki <jteki@openedev.com> wrote:
>>
>> >         reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
>> > @@ -719,7 +719,7 @@ int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
>> >  #if defined(CONFIG_SPL_SPI_XIP) && defined(CONFIG_SPL_BUILD)
>> >                 writel(0x0, plat->regbase + CQSPI_REG_MODE_BIT);
>> >  #else
>> > -               writel(0xFF, plat->regbase + CQSPI_REG_MODE_BIT);
>> > +               writel(GENMASK(7, 0), plat->regbase + CQSPI_REG_MODE_BIT);
>>
>> Is the 0xFF really a mask here? It seems it is just writing 0xFF to
>> the register directly without any masking operation.

As register got initialized to all 1's like masking all to set may be
we can add a macro like MODE_BIT_MASK and then will assign GENMASK to
that.

>
> Indeed, with context on the #else side it looks like an old fashioned
> "clear everything with magic value" which I suppose might technically be
> the bitmask but it's not helping with clarity in this case.

-- 
Jagan | openedev.

[U-Boot] [PATCH v4 18/24] spi: cadence_qspi_apb: Use GENMASK

[Marek Vasut]

On Friday, October 23, 2015 at 07:17:28 PM, Jagan Teki wrote:
> On 23 October 2015 at 02:55, Tom Rini <trini@konsulko.com> wrote:
> > On Thu, Oct 22, 2015 at 07:10:17PM -0200, Fabio Estevam wrote:
> >> On Thu, Oct 22, 2015 at 6:50 PM, Jagan Teki <jteki@openedev.com> wrote:
> >> >         reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
> >> > 
> >> > @@ -719,7 +719,7 @@ int cadence_qspi_apb_indirect_read_setup(struct
> >> > cadence_spi_platdata *plat,
> >> > 
> >> >  #if defined(CONFIG_SPL_SPI_XIP) && defined(CONFIG_SPL_BUILD)
> >> >  
> >> >                 writel(0x0, plat->regbase + CQSPI_REG_MODE_BIT);
> >> >  
> >> >  #else
> >> > 
> >> > -               writel(0xFF, plat->regbase + CQSPI_REG_MODE_BIT);
> >> > +               writel(GENMASK(7, 0), plat->regbase +
> >> > CQSPI_REG_MODE_BIT);
> >> 
> >> Is the 0xFF really a mask here? It seems it is just writing 0xFF to
> >> the register directly without any masking operation.
> 
> As register got initialized to all 1's like masking all to set may be
> we can add a macro like MODE_BIT_MASK and then will assign GENMASK to
> that.

Please keep the 0xff value, I agree with Fabio.

Best regards,
Marek Vasut

[U-Boot] [PATCH v4 18/24] spi: cadence_qspi_apb: Use GENMASK

[Marek Vasut]

On Thursday, October 22, 2015 at 10:50:18 PM, Jagan Teki wrote:
> Replace numeric mask hexcodes with GENMASK macro in cadence_qspi_apb
> 
> Cc: Stefan Roese <sr@denx.de>
> Cc: Vikas Manocha <vikas.manocha@st.com>
> Cc: Marek Vasut <marex@denx.de>
> Signed-off-by: Jagan Teki <jteki@openedev.com>
> ---
>  drivers/spi/cadence_qspi_apb.c | 48
> +++++++++++++++++++++--------------------- 1 file changed, 24
> insertions(+), 24 deletions(-)
> 
> diff --git a/drivers/spi/cadence_qspi_apb.c
> b/drivers/spi/cadence_qspi_apb.c index 7786dd6..31e14ee 100644
> --- a/drivers/spi/cadence_qspi_apb.c
> +++ b/drivers/spi/cadence_qspi_apb.c
> @@ -44,7 +44,7 @@
>  #define CQSPI_INST_TYPE_QUAD			(2)
> 
>  #define CQSPI_STIG_DATA_LEN_MAX			(8)
> -#define CQSPI_INDIRECTTRIGGER_ADDR_MASK		(0xFFFFF)
> +#define CQSPI_INDIRECTTRIGGER_ADDR_MASK		GENMASK(19, 0)
> 
>  #define CQSPI_DUMMY_CLKS_PER_BYTE		(8)
>  #define CQSPI_DUMMY_BYTES_MAX			(4)
> @@ -65,8 +65,8 @@
>  #define	CQSPI_REG_CONFIG_CHIPSELECT_LSB		10
>  #define	CQSPI_REG_CONFIG_BAUD_LSB		19
>  #define	CQSPI_REG_CONFIG_IDLE_LSB		31
> -#define	CQSPI_REG_CONFIG_CHIPSELECT_MASK	0xF
> -#define	CQSPI_REG_CONFIG_BAUD_MASK		0xF
> +#define	CQSPI_REG_CONFIG_CHIPSELECT_MASK	GENMASK(3, 0)
> +#define	CQSPI_REG_CONFIG_BAUD_MASK		GENMASK(3, 0)
> 
>  #define	CQSPI_REG_RD_INSTR			0x04
>  #define	CQSPI_REG_RD_INSTR_OPCODE_LSB		0
> @@ -75,10 +75,10 @@
>  #define	CQSPI_REG_RD_INSTR_TYPE_DATA_LSB	16
>  #define	CQSPI_REG_RD_INSTR_MODE_EN_LSB		20
>  #define	CQSPI_REG_RD_INSTR_DUMMY_LSB		24
> -#define	CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK	0x3
> -#define	CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK	0x3
> -#define	CQSPI_REG_RD_INSTR_TYPE_DATA_MASK	0x3
> -#define	CQSPI_REG_RD_INSTR_DUMMY_MASK		0x1F
> +#define	CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK	GENMASK(1, 0)
> +#define	CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK	GENMASK(1, 0)
> +#define	CQSPI_REG_RD_INSTR_TYPE_DATA_MASK	GENMASK(1, 0)
> +#define	CQSPI_REG_RD_INSTR_DUMMY_MASK		GENMASK(4, 0)
> 
>  #define	CQSPI_REG_WR_INSTR			0x08
>  #define	CQSPI_REG_WR_INSTR_OPCODE_LSB		0
> @@ -88,23 +88,23 @@
>  #define	CQSPI_REG_DELAY_TCHSH_LSB		8
>  #define	CQSPI_REG_DELAY_TSD2D_LSB		16
>  #define	CQSPI_REG_DELAY_TSHSL_LSB		24
> -#define	CQSPI_REG_DELAY_TSLCH_MASK		0xFF
> -#define	CQSPI_REG_DELAY_TCHSH_MASK		0xFF
> -#define	CQSPI_REG_DELAY_TSD2D_MASK		0xFF
> -#define	CQSPI_REG_DELAY_TSHSL_MASK		0xFF
> +#define	CQSPI_REG_DELAY_TSLCH_MASK		GENMASK(7, 0)
> +#define	CQSPI_REG_DELAY_TCHSH_MASK		GENMASK(7, 0)
> +#define	CQSPI_REG_DELAY_TSD2D_MASK		GENMASK(7, 0)
> +#define	CQSPI_REG_DELAY_TSHSL_MASK		GENMASK(7, 0)
> 
>  #define	CQSPI_READLCAPTURE			0x10
>  #define	CQSPI_READLCAPTURE_BYPASS_LSB		0
>  #define	CQSPI_READLCAPTURE_DELAY_LSB		1
> -#define	CQSPI_READLCAPTURE_DELAY_MASK		0xF
> +#define	CQSPI_READLCAPTURE_DELAY_MASK		GENMASK(3, 0)
> 
>  #define	CQSPI_REG_SIZE				0x14
>  #define	CQSPI_REG_SIZE_ADDRESS_LSB		0
>  #define	CQSPI_REG_SIZE_PAGE_LSB			4
>  #define	CQSPI_REG_SIZE_BLOCK_LSB		16
> -#define	CQSPI_REG_SIZE_ADDRESS_MASK		0xF
> -#define	CQSPI_REG_SIZE_PAGE_MASK		0xFFF
> -#define	CQSPI_REG_SIZE_BLOCK_MASK		0x3F
> +#define	CQSPI_REG_SIZE_ADDRESS_MASK		GENMASK(3, 0)
> +#define	CQSPI_REG_SIZE_PAGE_MASK		GENMASK(11, 0)
> +#define	CQSPI_REG_SIZE_BLOCK_MASK		GENMASK(5, 0)
> 
>  #define	CQSPI_REG_SRAMPARTITION			0x18
>  #define	CQSPI_REG_INDIRECTTRIGGER		0x1C
> @@ -115,8 +115,8 @@
>  #define	CQSPI_REG_SDRAMLEVEL			0x2C
>  #define	CQSPI_REG_SDRAMLEVEL_RD_LSB		0
>  #define	CQSPI_REG_SDRAMLEVEL_WR_LSB		16
> -#define	CQSPI_REG_SDRAMLEVEL_RD_MASK		0xFFFF
> -#define	CQSPI_REG_SDRAMLEVEL_WR_MASK		0xFFFF
> +#define	CQSPI_REG_SDRAMLEVEL_RD_MASK		GENMASK(15, 0)
> +#define	CQSPI_REG_SDRAMLEVEL_WR_MASK		GENMASK(15, 0)
> 
>  #define	CQSPI_REG_IRQSTATUS			0x40
>  #define	CQSPI_REG_IRQMASK			0x44
> @@ -142,11 +142,11 @@
>  #define	CQSPI_REG_CMDCTRL_RD_BYTES_LSB		20
>  #define	CQSPI_REG_CMDCTRL_RD_EN_LSB		23
>  #define	CQSPI_REG_CMDCTRL_OPCODE_LSB		24
> -#define	CQSPI_REG_CMDCTRL_DUMMY_MASK		0x1F
> -#define	CQSPI_REG_CMDCTRL_WR_BYTES_MASK		0x7
> -#define	CQSPI_REG_CMDCTRL_ADD_BYTES_MASK	0x3
> -#define	CQSPI_REG_CMDCTRL_RD_BYTES_MASK		0x7
> -#define	CQSPI_REG_CMDCTRL_OPCODE_MASK		0xFF
> +#define	CQSPI_REG_CMDCTRL_DUMMY_MASK		GENMASK(4, 0)
> +#define	CQSPI_REG_CMDCTRL_WR_BYTES_MASK		GENMASK(2, 0)
> +#define	CQSPI_REG_CMDCTRL_ADD_BYTES_MASK	GENMASK(1, 0)
> +#define	CQSPI_REG_CMDCTRL_RD_BYTES_MASK		GENMASK(2, 0)
> +#define	CQSPI_REG_CMDCTRL_OPCODE_MASK		GENMASK(7, 0)

Sorry, this just decreased the clarify of the code, so

NAK

[U-Boot] [PATCH v4 18/24] spi: cadence_qspi_apb: Use GENMASK

[Fabio Estevam]

Jagan,

On Fri, Oct 23, 2015 at 3:17 PM, Jagan Teki <jteki@openedev.com> wrote:
> On 23 October 2015 at 02:55, Tom Rini <trini@konsulko.com> wrote:
>> On Thu, Oct 22, 2015 at 07:10:17PM -0200, Fabio Estevam wrote:
>>> On Thu, Oct 22, 2015 at 6:50 PM, Jagan Teki <jteki@openedev.com> wrote:
>>>
>>> >         reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
>>> > @@ -719,7 +719,7 @@ int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
>>> >  #if defined(CONFIG_SPL_SPI_XIP) && defined(CONFIG_SPL_BUILD)
>>> >                 writel(0x0, plat->regbase + CQSPI_REG_MODE_BIT);
>>> >  #else
>>> > -               writel(0xFF, plat->regbase + CQSPI_REG_MODE_BIT);
>>> > +               writel(GENMASK(7, 0), plat->regbase + CQSPI_REG_MODE_BIT);
>>>
>>> Is the 0xFF really a mask here? It seems it is just writing 0xFF to
>>> the register directly without any masking operation.

Your quoting style is a bit odd.

You are replying to my message in Tom's reply. This is confusing.

> As register got initialized to all 1's like masking all to set may be
> we can add a macro like MODE_BIT_MASK and then will assign GENMASK to
> that.

Sorry, bu this sentence is hard to parse.

Anyway, this change is only making the code harder to read.

[U-Boot] [PATCH v4 18/24] spi: cadence_qspi_apb: Use GENMASK

[Tom Rini]

On Fri, Oct 23, 2015 at 10:47:28PM +0530, Jagan Teki wrote:
> On 23 October 2015 at 02:55, Tom Rini <trini@konsulko.com> wrote:
> > On Thu, Oct 22, 2015 at 07:10:17PM -0200, Fabio Estevam wrote:
> >> On Thu, Oct 22, 2015 at 6:50 PM, Jagan Teki <jteki@openedev.com> wrote:
> >>
> >> >         reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
> >> > @@ -719,7 +719,7 @@ int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
> >> >  #if defined(CONFIG_SPL_SPI_XIP) && defined(CONFIG_SPL_BUILD)
> >> >                 writel(0x0, plat->regbase + CQSPI_REG_MODE_BIT);
> >> >  #else
> >> > -               writel(0xFF, plat->regbase + CQSPI_REG_MODE_BIT);
> >> > +               writel(GENMASK(7, 0), plat->regbase + CQSPI_REG_MODE_BIT);
> >>
> >> Is the 0xFF really a mask here? It seems it is just writing 0xFF to
> >> the register directly without any masking operation.
> 
> As register got initialized to all 1's like masking all to set may be
> we can add a macro like MODE_BIT_MASK and then will assign GENMASK to
> that.

Lets just leave it to 0xFF as I bet when you read the datasheet it says
something along the lines of "write 0xFF first" or something like that.

-- 
Tom
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[U-Boot] [PATCH v4 08/24] spi: exynos_spi: Use BIT macro

[Jagan Teki]

On 23 October 2015 at 02:54, Tom Rini <trini@konsulko.com> wrote:
> On Fri, Oct 23, 2015 at 02:20:08AM +0530, Jagan Teki wrote:
>
>> Replace numerical bit shift with BIT macro in exynos_spi
>>
>> :%s/(1 << nr)/BIT(nr)/g
>> where nr = 0, 1, 2 .... 31
>>
>> Cc: Simon Glass <sjg@chromium.org>
>> Signed-off-by: Jagan Teki <jteki@openedev.com>
>> ---
>>  drivers/spi/exynos_spi.c | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/spi/exynos_spi.c b/drivers/spi/exynos_spi.c
>> index 44948c3..ea3c51d 100644
>> --- a/drivers/spi/exynos_spi.c
>> +++ b/drivers/spi/exynos_spi.c
>> @@ -86,7 +86,7 @@ static void spi_request_bytes(struct exynos_spi *regs, int count, int step)
>>               writel(0, &regs->swap_cfg);
>>       }
>>
>> -     assert(count && count < (1 << 16));
>> +     assert(count && count < BIT(16));
>>       setbits_le32(&regs->ch_cfg, SPI_CH_RST);
>>       clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
>>
>> @@ -345,7 +345,7 @@ static int exynos_spi_xfer(struct udevice *dev, unsigned int bitlen,
>>        */
>>       bytelen = bitlen / 8;
>>       for (upto = 0; !ret && upto < bytelen; upto += todo) {
>> -             todo = min(bytelen - upto, (1 << 16) - 4);
>> +             todo = min(bytelen - upto, BIT(16) - 4);
>>               ret = spi_rx_tx(priv, todo, &din, &dout, flags);
>>               if (ret)
>>                       break;
>
> These look like (1 << 16) is a size, not a bit.  Can you read the
> functions in context and confirm that it really is bit 16 here, rather
> than 4KiB (0x10000) ?

Ignoring this change this seems to be 65535 exynos SPI transfer limit,
not a bit.

-- 
Jagan | openedev