* [Qemu-devel] [PATCH] ppc: Add/Re-introduce MMU model definitions needed by PR KVM @ 2015-11-06 7:42 Bharata B Rao 2015-11-06 21:12 ` Benjamin Herrenschmidt 0 siblings, 1 reply; 6+ messages in thread From: Bharata B Rao @ 2015-11-06 7:42 UTC (permalink / raw) To: qemu-devel; +Cc: aik, qemu-ppc, aneesh.kumar, Bharata B Rao, david Commit aa4bb5875231 (ppc: Add mmu_model defines for arch 2.03 and 2.07) removed the mmu_model definition POWERPC_MMU_2_06a which is needed by PR KVM. Reintroduce it and also add POWERPC_MMU_2_07a. This fixes QEMU crash (qemu: fatal: Unknown MMU model) during booting of PR KVM guest. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> --- target-ppc/cpu.h | 6 ++++++ target-ppc/mmu_helper.c | 8 ++++++++ 2 files changed, 14 insertions(+) diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index b34aed6..31c6fee 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -122,9 +122,15 @@ enum powerpc_mmu_t { /* Architecture 2.06 variant */ POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG | POWERPC_MMU_AMR | 0x00000003, + /* Architecture 2.06 "degraded" (no 1T segments) */ + POWERPC_MMU_2_06a = POWERPC_MMU_64 | POWERPC_MMU_AMR + | 0x00000003, /* Architecture 2.07 variant */ POWERPC_MMU_2_07 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG | POWERPC_MMU_AMR | 0x00000004, + /* Architecture 2.07 "degraded" (no 1T segments) */ + POWERPC_MMU_2_07a = POWERPC_MMU_64 | POWERPC_MMU_AMR + | 0x00000004, #endif /* defined(TARGET_PPC64) */ }; diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c index e52d0e5..30298d8 100644 --- a/target-ppc/mmu_helper.c +++ b/target-ppc/mmu_helper.c @@ -1295,7 +1295,9 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env) case POWERPC_MMU_64B: case POWERPC_MMU_2_03: case POWERPC_MMU_2_06: + case POWERPC_MMU_2_06a: case POWERPC_MMU_2_07: + case POWERPC_MMU_2_07a: dump_slb(f, cpu_fprintf, env); break; #endif @@ -1435,7 +1437,9 @@ hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) case POWERPC_MMU_64B: case POWERPC_MMU_2_03: case POWERPC_MMU_2_06: + case POWERPC_MMU_2_06a: case POWERPC_MMU_2_07: + case POWERPC_MMU_2_07a: return ppc_hash64_get_phys_page_debug(env, addr); #endif @@ -1939,7 +1943,9 @@ void ppc_tlb_invalidate_all(CPUPPCState *env) case POWERPC_MMU_64B: case POWERPC_MMU_2_03: case POWERPC_MMU_2_06: + case POWERPC_MMU_2_06a: case POWERPC_MMU_2_07: + case POWERPC_MMU_2_07a: #endif /* defined(TARGET_PPC64) */ tlb_flush(CPU(cpu), 1); break; @@ -2013,7 +2019,9 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr) case POWERPC_MMU_64B: case POWERPC_MMU_2_03: case POWERPC_MMU_2_06: + case POWERPC_MMU_2_06a: case POWERPC_MMU_2_07: + case POWERPC_MMU_2_07a: /* tlbie invalidate TLBs for all segments */ /* XXX: given the fact that there are too many segments to invalidate, * and we still don't have a tlb_flush_mask(env, n, mask) in QEMU, -- 2.1.0 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] [PATCH] ppc: Add/Re-introduce MMU model definitions needed by PR KVM 2015-11-06 7:42 [Qemu-devel] [PATCH] ppc: Add/Re-introduce MMU model definitions needed by PR KVM Bharata B Rao @ 2015-11-06 21:12 ` Benjamin Herrenschmidt 2015-11-10 1:13 ` Alexey Kardashevskiy 0 siblings, 1 reply; 6+ messages in thread From: Benjamin Herrenschmidt @ 2015-11-06 21:12 UTC (permalink / raw) To: Bharata B Rao, qemu-devel; +Cc: aik, qemu-ppc, aneesh.kumar, david On Fri, 2015-11-06 at 13:12 +0530, Bharata B Rao wrote: > Commit aa4bb5875231 (ppc: Add mmu_model defines for arch 2.03 and > 2.07) > removed the mmu_model definition POWERPC_MMU_2_06a which is needed by > PR KVM. Reintroduce it and also add POWERPC_MMU_2_07a. > > This fixes QEMU crash (qemu: fatal: Unknown MMU model) during booting > of PR KVM guest. Hrm, I see... we clear the 1TSEG bit and that causes the switch/cases to no long work. Argh.... We should clean up that junk. We are mixing up bit masks and an actual model "number" in the same field. We should make that cleaner, using a mask to extract the actual version and switch/case on *that*... > Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> > Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> > --- > target-ppc/cpu.h | 6 ++++++ > target-ppc/mmu_helper.c | 8 ++++++++ > 2 files changed, 14 insertions(+) > > diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h > index b34aed6..31c6fee 100644 > --- a/target-ppc/cpu.h > +++ b/target-ppc/cpu.h > @@ -122,9 +122,15 @@ enum powerpc_mmu_t { > /* Architecture 2.06 variant */ > POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG > | POWERPC_MMU_AMR | 0x00000003, > + /* Architecture 2.06 "degraded" (no 1T segments) */ > + POWERPC_MMU_2_06a = POWERPC_MMU_64 | POWERPC_MMU_AMR > + | 0x00000003, > /* Architecture 2.07 variant */ > POWERPC_MMU_2_07 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG > | POWERPC_MMU_AMR | 0x00000004, > + /* Architecture 2.07 "degraded" (no 1T segments) */ > + POWERPC_MMU_2_07a = POWERPC_MMU_64 | POWERPC_MMU_AMR > + | 0x00000004, > #endif /* defined(TARGET_PPC64) */ > }; > > diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c > index e52d0e5..30298d8 100644 > --- a/target-ppc/mmu_helper.c > +++ b/target-ppc/mmu_helper.c > @@ -1295,7 +1295,9 @@ void dump_mmu(FILE *f, fprintf_function > cpu_fprintf, CPUPPCState *env) > case POWERPC_MMU_64B: > case POWERPC_MMU_2_03: > case POWERPC_MMU_2_06: > + case POWERPC_MMU_2_06a: > case POWERPC_MMU_2_07: > + case POWERPC_MMU_2_07a: > dump_slb(f, cpu_fprintf, env); > break; > #endif > @@ -1435,7 +1437,9 @@ hwaddr ppc_cpu_get_phys_page_debug(CPUState > *cs, vaddr addr) > case POWERPC_MMU_64B: > case POWERPC_MMU_2_03: > case POWERPC_MMU_2_06: > + case POWERPC_MMU_2_06a: > case POWERPC_MMU_2_07: > + case POWERPC_MMU_2_07a: > return ppc_hash64_get_phys_page_debug(env, addr); > #endif > > @@ -1939,7 +1943,9 @@ void ppc_tlb_invalidate_all(CPUPPCState *env) > case POWERPC_MMU_64B: > case POWERPC_MMU_2_03: > case POWERPC_MMU_2_06: > + case POWERPC_MMU_2_06a: > case POWERPC_MMU_2_07: > + case POWERPC_MMU_2_07a: > #endif /* defined(TARGET_PPC64) */ > tlb_flush(CPU(cpu), 1); > break; > @@ -2013,7 +2019,9 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, > target_ulong addr) > case POWERPC_MMU_64B: > case POWERPC_MMU_2_03: > case POWERPC_MMU_2_06: > + case POWERPC_MMU_2_06a: > case POWERPC_MMU_2_07: > + case POWERPC_MMU_2_07a: > /* tlbie invalidate TLBs for all segments */ > /* XXX: given the fact that there are too many segments to > invalidate, > * and we still don't have a tlb_flush_mask(env, n, > mask) in QEMU, ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] [PATCH] ppc: Add/Re-introduce MMU model definitions needed by PR KVM 2015-11-06 21:12 ` Benjamin Herrenschmidt @ 2015-11-10 1:13 ` Alexey Kardashevskiy 2015-11-10 5:29 ` Bharata B Rao 0 siblings, 1 reply; 6+ messages in thread From: Alexey Kardashevskiy @ 2015-11-10 1:13 UTC (permalink / raw) To: Benjamin Herrenschmidt, Bharata B Rao, qemu-devel Cc: qemu-ppc, aneesh.kumar, david On 11/07/2015 08:12 AM, Benjamin Herrenschmidt wrote: > On Fri, 2015-11-06 at 13:12 +0530, Bharata B Rao wrote: >> Commit aa4bb5875231 (ppc: Add mmu_model defines for arch 2.03 and >> 2.07) >> removed the mmu_model definition POWERPC_MMU_2_06a which is needed by >> PR KVM. Reintroduce it and also add POWERPC_MMU_2_07a. >> >> This fixes QEMU crash (qemu: fatal: Unknown MMU model) during booting >> of PR KVM guest. > > Hrm, I see... we clear the 1TSEG bit and that causes the switch/cases > to no long work. Argh.... > > We should clean up that junk. We are mixing up bit masks and an actual > model "number" in the same field. We should make that cleaner, using > a mask to extract the actual version and switch/case on *that*... I like this and I wonder if Bharata is going to do this, if not, I will, I just noticed this this patch made it to the dwg/spapr-next tree so we need to hurry... Bharata, got some time for this? Thanks. > >> Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> >> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> >> --- >> target-ppc/cpu.h | 6 ++++++ >> target-ppc/mmu_helper.c | 8 ++++++++ >> 2 files changed, 14 insertions(+) >> >> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h >> index b34aed6..31c6fee 100644 >> --- a/target-ppc/cpu.h >> +++ b/target-ppc/cpu.h >> @@ -122,9 +122,15 @@ enum powerpc_mmu_t { >> /* Architecture 2.06 variant */ >> POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG >> | POWERPC_MMU_AMR | 0x00000003, >> + /* Architecture 2.06 "degraded" (no 1T segments) */ >> + POWERPC_MMU_2_06a = POWERPC_MMU_64 | POWERPC_MMU_AMR >> + | 0x00000003, >> /* Architecture 2.07 variant */ >> POWERPC_MMU_2_07 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG >> | POWERPC_MMU_AMR | 0x00000004, >> + /* Architecture 2.07 "degraded" (no 1T segments) */ >> + POWERPC_MMU_2_07a = POWERPC_MMU_64 | POWERPC_MMU_AMR >> + | 0x00000004, >> #endif /* defined(TARGET_PPC64) */ >> }; >> >> diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c >> index e52d0e5..30298d8 100644 >> --- a/target-ppc/mmu_helper.c >> +++ b/target-ppc/mmu_helper.c >> @@ -1295,7 +1295,9 @@ void dump_mmu(FILE *f, fprintf_function >> cpu_fprintf, CPUPPCState *env) >> case POWERPC_MMU_64B: >> case POWERPC_MMU_2_03: >> case POWERPC_MMU_2_06: >> + case POWERPC_MMU_2_06a: >> case POWERPC_MMU_2_07: >> + case POWERPC_MMU_2_07a: >> dump_slb(f, cpu_fprintf, env); >> break; >> #endif >> @@ -1435,7 +1437,9 @@ hwaddr ppc_cpu_get_phys_page_debug(CPUState >> *cs, vaddr addr) >> case POWERPC_MMU_64B: >> case POWERPC_MMU_2_03: >> case POWERPC_MMU_2_06: >> + case POWERPC_MMU_2_06a: >> case POWERPC_MMU_2_07: >> + case POWERPC_MMU_2_07a: >> return ppc_hash64_get_phys_page_debug(env, addr); >> #endif >> >> @@ -1939,7 +1943,9 @@ void ppc_tlb_invalidate_all(CPUPPCState *env) >> case POWERPC_MMU_64B: >> case POWERPC_MMU_2_03: >> case POWERPC_MMU_2_06: >> + case POWERPC_MMU_2_06a: >> case POWERPC_MMU_2_07: >> + case POWERPC_MMU_2_07a: >> #endif /* defined(TARGET_PPC64) */ >> tlb_flush(CPU(cpu), 1); >> break; >> @@ -2013,7 +2019,9 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, >> target_ulong addr) >> case POWERPC_MMU_64B: >> case POWERPC_MMU_2_03: >> case POWERPC_MMU_2_06: >> + case POWERPC_MMU_2_06a: >> case POWERPC_MMU_2_07: >> + case POWERPC_MMU_2_07a: >> /* tlbie invalidate TLBs for all segments */ >> /* XXX: given the fact that there are too many segments to >> invalidate, >> * and we still don't have a tlb_flush_mask(env, n, >> mask) in QEMU, -- Alexey ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] [PATCH] ppc: Add/Re-introduce MMU model definitions needed by PR KVM 2015-11-10 1:13 ` Alexey Kardashevskiy @ 2015-11-10 5:29 ` Bharata B Rao 2015-11-11 0:43 ` Alexey Kardashevskiy 2015-11-11 0:46 ` David Gibson 0 siblings, 2 replies; 6+ messages in thread From: Bharata B Rao @ 2015-11-10 5:29 UTC (permalink / raw) To: Alexey Kardashevskiy; +Cc: aneesh.kumar, qemu-ppc, qemu-devel, david On Tue, Nov 10, 2015 at 12:13:50PM +1100, Alexey Kardashevskiy wrote: > On 11/07/2015 08:12 AM, Benjamin Herrenschmidt wrote: > >On Fri, 2015-11-06 at 13:12 +0530, Bharata B Rao wrote: > >>Commit aa4bb5875231 (ppc: Add mmu_model defines for arch 2.03 and > >>2.07) > >>removed the mmu_model definition POWERPC_MMU_2_06a which is needed by > >>PR KVM. Reintroduce it and also add POWERPC_MMU_2_07a. > >> > >>This fixes QEMU crash (qemu: fatal: Unknown MMU model) during booting > >>of PR KVM guest. > > > >Hrm, I see... we clear the 1TSEG bit and that causes the switch/cases > >to no long work. Argh.... > > > >We should clean up that junk. We are mixing up bit masks and an actual > >model "number" in the same field. We should make that cleaner, using > >a mask to extract the actual version and switch/case on *that*... > > > I like this and I wonder if Bharata is going to do this, if not, I will, I > just noticed this this patch made it to the dwg/spapr-next tree so we need > to hurry... > > Bharata, got some time for this? Thanks. I can only get to this tomorrow, so if it is urgent please feel free to work on this. Meanwhile I have gotten till this point, very lightly tested though and patch description needs update. Regards, Bharata. ppc: Add/Re-introduce MMU model definitions needed by PR KVM From: Bharata B Rao <bharata@linux.vnet.ibm.com> Commit aa4bb5875231 (ppc: Add mmu_model defines for arch 2.03 and 2.07) removed the mmu_model definition POWERPC_MMU_2_06a which is needed by PR KVM. Reintroduce it and also add POWERPC_MMU_2_07a. This fixes QEMU crash (qemu: fatal: Unknown MMU model) during booting of PR KVM guest. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> --- target-ppc/cpu.h | 25 +++++++++++++++---------- target-ppc/mmu_helper.c | 8 ++++---- target-ppc/translate_init.c | 11 +++++++---- 3 files changed, 26 insertions(+), 18 deletions(-) diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index b34aed6..2c4a10a 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -88,6 +88,17 @@ /*****************************************************************************/ /* MMU model */ + +#if defined(TARGET_PPC64) +#define POWERPC_MMU_64 0x00010000 +#define POWERPC_MMU_1TSEG 0x00020000 +#define POWERPC_MMU_AMR 0x00040000 +#define POWERPC_MMU_MASK ~(POWERPC_MMU_64 | POWERPC_MMU_1TSEG | \ + POWERPC_MMU_AMR) +#else +#define POWERPC_MMU_MASK ~0 +#endif + typedef enum powerpc_mmu_t powerpc_mmu_t; enum powerpc_mmu_t { POWERPC_MMU_UNKNOWN = 0x00000000, @@ -112,19 +123,13 @@ enum powerpc_mmu_t { /* PowerPC 601 MMU model (specific BATs format) */ POWERPC_MMU_601 = 0x0000000A, #if defined(TARGET_PPC64) -#define POWERPC_MMU_64 0x00010000 -#define POWERPC_MMU_1TSEG 0x00020000 -#define POWERPC_MMU_AMR 0x00040000 /* 64 bits PowerPC MMU */ - POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001, - /* Architecture 2.03 and later (has LPCR) */ - POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002, + POWERPC_MMU_64B = 0x0000000B, + POWERPC_MMU_2_03 = 0x0000000C, /* Architecture 2.06 variant */ - POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG - | POWERPC_MMU_AMR | 0x00000003, + POWERPC_MMU_2_06 = 0x0000000D, /* Architecture 2.07 variant */ - POWERPC_MMU_2_07 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG - | POWERPC_MMU_AMR | 0x00000004, + POWERPC_MMU_2_07 = 0x0000000E, #endif /* defined(TARGET_PPC64) */ }; diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c index e52d0e5..9dead4b 100644 --- a/target-ppc/mmu_helper.c +++ b/target-ppc/mmu_helper.c @@ -1280,7 +1280,7 @@ static void mmu6xx_dump_mmu(FILE *f, fprintf_function cpu_fprintf, void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env) { - switch (env->mmu_model) { + switch (env->mmu_model & POWERPC_MMU_MASK) { case POWERPC_MMU_BOOKE: mmubooke_dump_mmu(f, cpu_fprintf, env); break; @@ -1430,7 +1430,7 @@ hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) CPUPPCState *env = &cpu->env; mmu_ctx_t ctx; - switch (env->mmu_model) { + switch (env->mmu_model & POWERPC_MMU_MASK) { #if defined(TARGET_PPC64) case POWERPC_MMU_64B: case POWERPC_MMU_2_03: @@ -1911,7 +1911,7 @@ void ppc_tlb_invalidate_all(CPUPPCState *env) { PowerPCCPU *cpu = ppc_env_get_cpu(env); - switch (env->mmu_model) { + switch (env->mmu_model & POWERPC_MMU_MASK) { case POWERPC_MMU_SOFT_6xx: case POWERPC_MMU_SOFT_74xx: ppc6xx_tlb_invalidate_all(env); @@ -1957,7 +1957,7 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr) CPUState *cs; addr &= TARGET_PAGE_MASK; - switch (env->mmu_model) { + switch (env->mmu_model & POWERPC_MMU_MASK) { case POWERPC_MMU_SOFT_6xx: case POWERPC_MMU_SOFT_74xx: ppc6xx_tlb_invalidate_virt(env, addr, 0); diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 4934c80..a19aa32 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -7967,7 +7967,7 @@ POWERPC_FAMILY(970)(ObjectClass *oc, void *data) (1ull << MSR_DR) | (1ull << MSR_PMM) | (1ull << MSR_RI); - pcc->mmu_model = POWERPC_MMU_64B; + pcc->mmu_model = POWERPC_MMU_64B | POWERPC_MMU_64; #if defined(CONFIG_SOFTMMU) pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; #endif @@ -8020,7 +8020,8 @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) (1ull << MSR_DR) | (1ull << MSR_PMM) | (1ull << MSR_RI); - pcc->mmu_model = POWERPC_MMU_2_03; + /* Architecture 2.03 and later (has LPCR) */ + pcc->mmu_model = POWERPC_MMU_2_03 | POWERPC_MMU_64; #if defined(CONFIG_SOFTMMU) pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; #endif @@ -8164,7 +8165,8 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) (1ull << MSR_PMM) | (1ull << MSR_RI) | (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_2_06; + pcc->mmu_model = POWERPC_MMU_2_06 | POWERPC_MMU_64 | POWERPC_MMU_1TSEG | + POWERPC_MMU_AMR; #if defined(CONFIG_SOFTMMU) pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; #endif @@ -8244,7 +8246,8 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) (1ull << MSR_PMM) | (1ull << MSR_RI) | (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_2_07; + pcc->mmu_model = POWERPC_MMU_2_07 | POWERPC_MMU_64 | POWERPC_MMU_1TSEG | + POWERPC_MMU_AMR; #if defined(CONFIG_SOFTMMU) pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; #endif ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] [PATCH] ppc: Add/Re-introduce MMU model definitions needed by PR KVM 2015-11-10 5:29 ` Bharata B Rao @ 2015-11-11 0:43 ` Alexey Kardashevskiy 2015-11-11 0:46 ` David Gibson 1 sibling, 0 replies; 6+ messages in thread From: Alexey Kardashevskiy @ 2015-11-11 0:43 UTC (permalink / raw) To: bharata; +Cc: david, qemu-ppc, aneesh.kumar, qemu-devel On 11/10/2015 04:29 PM, Bharata B Rao wrote: > On Tue, Nov 10, 2015 at 12:13:50PM +1100, Alexey Kardashevskiy wrote: >> On 11/07/2015 08:12 AM, Benjamin Herrenschmidt wrote: >>> On Fri, 2015-11-06 at 13:12 +0530, Bharata B Rao wrote: >>>> Commit aa4bb5875231 (ppc: Add mmu_model defines for arch 2.03 and >>>> 2.07) >>>> removed the mmu_model definition POWERPC_MMU_2_06a which is needed by >>>> PR KVM. Reintroduce it and also add POWERPC_MMU_2_07a. >>>> >>>> This fixes QEMU crash (qemu: fatal: Unknown MMU model) during booting >>>> of PR KVM guest. >>> >>> Hrm, I see... we clear the 1TSEG bit and that causes the switch/cases >>> to no long work. Argh.... >>> >>> We should clean up that junk. We are mixing up bit masks and an actual >>> model "number" in the same field. We should make that cleaner, using >>> a mask to extract the actual version and switch/case on *that*... >> >> >> I like this and I wonder if Bharata is going to do this, if not, I will, I >> just noticed this this patch made it to the dwg/spapr-next tree so we need >> to hurry... >> >> Bharata, got some time for this? Thanks. > > I can only get to this tomorrow, so if it is urgent please feel free > to work on this. No, I am fine if you finish this :) > Meanwhile I have gotten till this point, very lightly tested though > and patch description needs update. imho this looks worse than just adding POWERPC_MMU_2_06a and POWERPC_MMU_2_07a back... I'd rather have "if (env->mmu_model & POWERPC_MMU_64){} else switch (env->mmu_model) {}" and remove POWERPC_MMU_64 cases from the switch'es. > > Regards, > Bharata. > > ppc: Add/Re-introduce MMU model definitions needed by PR KVM > > From: Bharata B Rao <bharata@linux.vnet.ibm.com> > > Commit aa4bb5875231 (ppc: Add mmu_model defines for arch 2.03 and 2.07) > removed the mmu_model definition POWERPC_MMU_2_06a which is needed by > PR KVM. Reintroduce it and also add POWERPC_MMU_2_07a. > > This fixes QEMU crash (qemu: fatal: Unknown MMU model) during booting > of PR KVM guest. > > Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> > Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> > --- > target-ppc/cpu.h | 25 +++++++++++++++---------- > target-ppc/mmu_helper.c | 8 ++++---- > target-ppc/translate_init.c | 11 +++++++---- > 3 files changed, 26 insertions(+), 18 deletions(-) > > diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h > index b34aed6..2c4a10a 100644 > --- a/target-ppc/cpu.h > +++ b/target-ppc/cpu.h > @@ -88,6 +88,17 @@ > > /*****************************************************************************/ > /* MMU model */ > + > +#if defined(TARGET_PPC64) > +#define POWERPC_MMU_64 0x00010000 > +#define POWERPC_MMU_1TSEG 0x00020000 > +#define POWERPC_MMU_AMR 0x00040000 > +#define POWERPC_MMU_MASK ~(POWERPC_MMU_64 | POWERPC_MMU_1TSEG | \ > + POWERPC_MMU_AMR) > +#else > +#define POWERPC_MMU_MASK ~0 > +#endif > + > typedef enum powerpc_mmu_t powerpc_mmu_t; > enum powerpc_mmu_t { > POWERPC_MMU_UNKNOWN = 0x00000000, > @@ -112,19 +123,13 @@ enum powerpc_mmu_t { > /* PowerPC 601 MMU model (specific BATs format) */ > POWERPC_MMU_601 = 0x0000000A, > #if defined(TARGET_PPC64) > -#define POWERPC_MMU_64 0x00010000 > -#define POWERPC_MMU_1TSEG 0x00020000 > -#define POWERPC_MMU_AMR 0x00040000 > /* 64 bits PowerPC MMU */ > - POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001, > - /* Architecture 2.03 and later (has LPCR) */ > - POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002, > + POWERPC_MMU_64B = 0x0000000B, > + POWERPC_MMU_2_03 = 0x0000000C, > /* Architecture 2.06 variant */ > - POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG > - | POWERPC_MMU_AMR | 0x00000003, > + POWERPC_MMU_2_06 = 0x0000000D, > /* Architecture 2.07 variant */ > - POWERPC_MMU_2_07 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG > - | POWERPC_MMU_AMR | 0x00000004, > + POWERPC_MMU_2_07 = 0x0000000E, > #endif /* defined(TARGET_PPC64) */ > }; > > diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c > index e52d0e5..9dead4b 100644 > --- a/target-ppc/mmu_helper.c > +++ b/target-ppc/mmu_helper.c > @@ -1280,7 +1280,7 @@ static void mmu6xx_dump_mmu(FILE *f, fprintf_function cpu_fprintf, > > void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env) > { > - switch (env->mmu_model) { > + switch (env->mmu_model & POWERPC_MMU_MASK) { > case POWERPC_MMU_BOOKE: > mmubooke_dump_mmu(f, cpu_fprintf, env); > break; > @@ -1430,7 +1430,7 @@ hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) > CPUPPCState *env = &cpu->env; > mmu_ctx_t ctx; > > - switch (env->mmu_model) { > + switch (env->mmu_model & POWERPC_MMU_MASK) { > #if defined(TARGET_PPC64) > case POWERPC_MMU_64B: > case POWERPC_MMU_2_03: > @@ -1911,7 +1911,7 @@ void ppc_tlb_invalidate_all(CPUPPCState *env) > { > PowerPCCPU *cpu = ppc_env_get_cpu(env); > > - switch (env->mmu_model) { > + switch (env->mmu_model & POWERPC_MMU_MASK) { > case POWERPC_MMU_SOFT_6xx: > case POWERPC_MMU_SOFT_74xx: > ppc6xx_tlb_invalidate_all(env); > @@ -1957,7 +1957,7 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr) > CPUState *cs; > > addr &= TARGET_PAGE_MASK; > - switch (env->mmu_model) { > + switch (env->mmu_model & POWERPC_MMU_MASK) { > case POWERPC_MMU_SOFT_6xx: > case POWERPC_MMU_SOFT_74xx: > ppc6xx_tlb_invalidate_virt(env, addr, 0); > diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c > index 4934c80..a19aa32 100644 > --- a/target-ppc/translate_init.c > +++ b/target-ppc/translate_init.c > @@ -7967,7 +7967,7 @@ POWERPC_FAMILY(970)(ObjectClass *oc, void *data) > (1ull << MSR_DR) | > (1ull << MSR_PMM) | > (1ull << MSR_RI); > - pcc->mmu_model = POWERPC_MMU_64B; > + pcc->mmu_model = POWERPC_MMU_64B | POWERPC_MMU_64; > #if defined(CONFIG_SOFTMMU) > pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; > #endif > @@ -8020,7 +8020,8 @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) > (1ull << MSR_DR) | > (1ull << MSR_PMM) | > (1ull << MSR_RI); > - pcc->mmu_model = POWERPC_MMU_2_03; > + /* Architecture 2.03 and later (has LPCR) */ > + pcc->mmu_model = POWERPC_MMU_2_03 | POWERPC_MMU_64; > #if defined(CONFIG_SOFTMMU) > pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; > #endif > @@ -8164,7 +8165,8 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) > (1ull << MSR_PMM) | > (1ull << MSR_RI) | > (1ull << MSR_LE); > - pcc->mmu_model = POWERPC_MMU_2_06; > + pcc->mmu_model = POWERPC_MMU_2_06 | POWERPC_MMU_64 | POWERPC_MMU_1TSEG | > + POWERPC_MMU_AMR; > #if defined(CONFIG_SOFTMMU) > pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; > #endif > @@ -8244,7 +8246,8 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) > (1ull << MSR_PMM) | > (1ull << MSR_RI) | > (1ull << MSR_LE); > - pcc->mmu_model = POWERPC_MMU_2_07; > + pcc->mmu_model = POWERPC_MMU_2_07 | POWERPC_MMU_64 | POWERPC_MMU_1TSEG | > + POWERPC_MMU_AMR; > #if defined(CONFIG_SOFTMMU) > pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; > #endif > > -- Alexey ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] [PATCH] ppc: Add/Re-introduce MMU model definitions needed by PR KVM 2015-11-10 5:29 ` Bharata B Rao 2015-11-11 0:43 ` Alexey Kardashevskiy @ 2015-11-11 0:46 ` David Gibson 1 sibling, 0 replies; 6+ messages in thread From: David Gibson @ 2015-11-11 0:46 UTC (permalink / raw) To: Bharata B Rao; +Cc: Alexey Kardashevskiy, qemu-ppc, qemu-devel, aneesh.kumar [-- Attachment #1: Type: text/plain, Size: 8222 bytes --] On Tue, Nov 10, 2015 at 10:59:45AM +0530, Bharata B Rao wrote: > On Tue, Nov 10, 2015 at 12:13:50PM +1100, Alexey Kardashevskiy wrote: > > On 11/07/2015 08:12 AM, Benjamin Herrenschmidt wrote: > > >On Fri, 2015-11-06 at 13:12 +0530, Bharata B Rao wrote: > > >>Commit aa4bb5875231 (ppc: Add mmu_model defines for arch 2.03 and > > >>2.07) > > >>removed the mmu_model definition POWERPC_MMU_2_06a which is needed by > > >>PR KVM. Reintroduce it and also add POWERPC_MMU_2_07a. > > >> > > >>This fixes QEMU crash (qemu: fatal: Unknown MMU model) during booting > > >>of PR KVM guest. > > > > > >Hrm, I see... we clear the 1TSEG bit and that causes the switch/cases > > >to no long work. Argh.... > > > > > >We should clean up that junk. We are mixing up bit masks and an actual > > >model "number" in the same field. We should make that cleaner, using > > >a mask to extract the actual version and switch/case on *that*... > > > > > > I like this and I wonder if Bharata is going to do this, if not, I will, I > > just noticed this this patch made it to the dwg/spapr-next tree so we need > > to hurry... > > > > Bharata, got some time for this? Thanks. > > I can only get to this tomorrow, so if it is urgent please feel free > to work on this. > > Meanwhile I have gotten till this point, very lightly tested though > and patch description needs update. This looks like a good start on a cleanup, but I'm disinclined to merge it now, right before the hard freeze. The mixing of model IDs and feature bits is ugly, but it's been there for a long while - we can cope with it for a bit longer. > > Regards, > Bharata. > > ppc: Add/Re-introduce MMU model definitions needed by PR KVM > > From: Bharata B Rao <bharata@linux.vnet.ibm.com> > > Commit aa4bb5875231 (ppc: Add mmu_model defines for arch 2.03 and 2.07) > removed the mmu_model definition POWERPC_MMU_2_06a which is needed by > PR KVM. Reintroduce it and also add POWERPC_MMU_2_07a. > > This fixes QEMU crash (qemu: fatal: Unknown MMU model) during booting > of PR KVM guest. > > Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> > Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> > --- > target-ppc/cpu.h | 25 +++++++++++++++---------- > target-ppc/mmu_helper.c | 8 ++++---- > target-ppc/translate_init.c | 11 +++++++---- > 3 files changed, 26 insertions(+), 18 deletions(-) > > diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h > index b34aed6..2c4a10a 100644 > --- a/target-ppc/cpu.h > +++ b/target-ppc/cpu.h > @@ -88,6 +88,17 @@ > > /*****************************************************************************/ > /* MMU model */ > + > +#if defined(TARGET_PPC64) > +#define POWERPC_MMU_64 0x00010000 > +#define POWERPC_MMU_1TSEG 0x00020000 > +#define POWERPC_MMU_AMR 0x00040000 > +#define POWERPC_MMU_MASK ~(POWERPC_MMU_64 | POWERPC_MMU_1TSEG | \ > + POWERPC_MMU_AMR) > +#else > +#define POWERPC_MMU_MASK ~0 > +#endif > + > typedef enum powerpc_mmu_t powerpc_mmu_t; > enum powerpc_mmu_t { > POWERPC_MMU_UNKNOWN = 0x00000000, > @@ -112,19 +123,13 @@ enum powerpc_mmu_t { > /* PowerPC 601 MMU model (specific BATs format) */ > POWERPC_MMU_601 = 0x0000000A, > #if defined(TARGET_PPC64) > -#define POWERPC_MMU_64 0x00010000 > -#define POWERPC_MMU_1TSEG 0x00020000 > -#define POWERPC_MMU_AMR 0x00040000 > /* 64 bits PowerPC MMU */ > - POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001, > - /* Architecture 2.03 and later (has LPCR) */ > - POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002, > + POWERPC_MMU_64B = 0x0000000B, > + POWERPC_MMU_2_03 = 0x0000000C, > /* Architecture 2.06 variant */ > - POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG > - | POWERPC_MMU_AMR | 0x00000003, > + POWERPC_MMU_2_06 = 0x0000000D, > /* Architecture 2.07 variant */ > - POWERPC_MMU_2_07 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG > - | POWERPC_MMU_AMR | 0x00000004, > + POWERPC_MMU_2_07 = 0x0000000E, > #endif /* defined(TARGET_PPC64) */ > }; > > diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c > index e52d0e5..9dead4b 100644 > --- a/target-ppc/mmu_helper.c > +++ b/target-ppc/mmu_helper.c > @@ -1280,7 +1280,7 @@ static void mmu6xx_dump_mmu(FILE *f, fprintf_function cpu_fprintf, > > void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env) > { > - switch (env->mmu_model) { > + switch (env->mmu_model & POWERPC_MMU_MASK) { > case POWERPC_MMU_BOOKE: > mmubooke_dump_mmu(f, cpu_fprintf, env); > break; > @@ -1430,7 +1430,7 @@ hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) > CPUPPCState *env = &cpu->env; > mmu_ctx_t ctx; > > - switch (env->mmu_model) { > + switch (env->mmu_model & POWERPC_MMU_MASK) { > #if defined(TARGET_PPC64) > case POWERPC_MMU_64B: > case POWERPC_MMU_2_03: > @@ -1911,7 +1911,7 @@ void ppc_tlb_invalidate_all(CPUPPCState *env) > { > PowerPCCPU *cpu = ppc_env_get_cpu(env); > > - switch (env->mmu_model) { > + switch (env->mmu_model & POWERPC_MMU_MASK) { > case POWERPC_MMU_SOFT_6xx: > case POWERPC_MMU_SOFT_74xx: > ppc6xx_tlb_invalidate_all(env); > @@ -1957,7 +1957,7 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr) > CPUState *cs; > > addr &= TARGET_PAGE_MASK; > - switch (env->mmu_model) { > + switch (env->mmu_model & POWERPC_MMU_MASK) { > case POWERPC_MMU_SOFT_6xx: > case POWERPC_MMU_SOFT_74xx: > ppc6xx_tlb_invalidate_virt(env, addr, 0); > diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c > index 4934c80..a19aa32 100644 > --- a/target-ppc/translate_init.c > +++ b/target-ppc/translate_init.c > @@ -7967,7 +7967,7 @@ POWERPC_FAMILY(970)(ObjectClass *oc, void *data) > (1ull << MSR_DR) | > (1ull << MSR_PMM) | > (1ull << MSR_RI); > - pcc->mmu_model = POWERPC_MMU_64B; > + pcc->mmu_model = POWERPC_MMU_64B | POWERPC_MMU_64; > #if defined(CONFIG_SOFTMMU) > pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; > #endif > @@ -8020,7 +8020,8 @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) > (1ull << MSR_DR) | > (1ull << MSR_PMM) | > (1ull << MSR_RI); > - pcc->mmu_model = POWERPC_MMU_2_03; > + /* Architecture 2.03 and later (has LPCR) */ > + pcc->mmu_model = POWERPC_MMU_2_03 | POWERPC_MMU_64; > #if defined(CONFIG_SOFTMMU) > pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; > #endif > @@ -8164,7 +8165,8 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) > (1ull << MSR_PMM) | > (1ull << MSR_RI) | > (1ull << MSR_LE); > - pcc->mmu_model = POWERPC_MMU_2_06; > + pcc->mmu_model = POWERPC_MMU_2_06 | POWERPC_MMU_64 | POWERPC_MMU_1TSEG | > + POWERPC_MMU_AMR; > #if defined(CONFIG_SOFTMMU) > pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; > #endif > @@ -8244,7 +8246,8 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) > (1ull << MSR_PMM) | > (1ull << MSR_RI) | > (1ull << MSR_LE); > - pcc->mmu_model = POWERPC_MMU_2_07; > + pcc->mmu_model = POWERPC_MMU_2_07 | POWERPC_MMU_64 | POWERPC_MMU_1TSEG | > + POWERPC_MMU_AMR; > #if defined(CONFIG_SOFTMMU) > pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; > #endif > -- David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 819 bytes --] ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2015-11-11 1:07 UTC | newest] Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2015-11-06 7:42 [Qemu-devel] [PATCH] ppc: Add/Re-introduce MMU model definitions needed by PR KVM Bharata B Rao 2015-11-06 21:12 ` Benjamin Herrenschmidt 2015-11-10 1:13 ` Alexey Kardashevskiy 2015-11-10 5:29 ` Bharata B Rao 2015-11-11 0:43 ` Alexey Kardashevskiy 2015-11-11 0:46 ` David Gibson
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