* [PATCH] drm/i915: Make sure DC writes are coherent on flush.
@ 2016-01-14 2:59 Francisco Jerez
2016-01-14 5:33 ` Mark Janes
` (4 more replies)
0 siblings, 5 replies; 31+ messages in thread
From: Francisco Jerez @ 2016-01-14 2:59 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
We need to set the DC FLUSH PIPE_CONTROL bit on Gen7+ to guarantee
that writes performed via the HDC are visible in memory. Fixes an
intermittent failure in a Piglit test that writes to a BO from a
shader using GL atomic counters (implemented as HDC untyped atomics)
and then expects the memory to read back the same value after mapping
it on the CPU.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91298
Tested-by: Mark Janes <mark.a.janes@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_lrc.c | 1 +
drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index ab344e0..02213c6 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1735,6 +1735,7 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
if (flush_domains) {
flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
+ flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
flags |= PIPE_CONTROL_FLUSH_ENABLE;
}
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 4060acf..8cd8aab 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -331,6 +331,7 @@ gen7_render_ring_flush(struct drm_i915_gem_request *req,
if (flush_domains) {
flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
+ flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
flags |= PIPE_CONTROL_FLUSH_ENABLE;
}
if (invalidate_domains) {
@@ -403,6 +404,7 @@ gen8_render_ring_flush(struct drm_i915_gem_request *req,
if (flush_domains) {
flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
+ flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
flags |= PIPE_CONTROL_FLUSH_ENABLE;
}
if (invalidate_domains) {
--
2.7.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 31+ messages in thread
* Re: [PATCH] drm/i915: Make sure DC writes are coherent on flush.
2016-01-14 2:59 [PATCH] drm/i915: Make sure DC writes are coherent on flush Francisco Jerez
@ 2016-01-14 5:33 ` Mark Janes
2016-01-14 7:58 ` Jani Nikula
` (3 subsequent siblings)
4 siblings, 0 replies; 31+ messages in thread
From: Mark Janes @ 2016-01-14 5:33 UTC (permalink / raw)
To: Francisco Jerez, intel-gfx; +Cc: Rodrigo Vivi
Tested-by: Mark Janes <mark.a.janes@intel.com>
Francisco Jerez <currojerez@riseup.net> writes:
> We need to set the DC FLUSH PIPE_CONTROL bit on Gen7+ to guarantee
> that writes performed via the HDC are visible in memory. Fixes an
> intermittent failure in a Piglit test that writes to a BO from a
> shader using GL atomic counters (implemented as HDC untyped atomics)
> and then expects the memory to read back the same value after mapping
> it on the CPU.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91298
> Tested-by: Mark Janes <mark.a.janes@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/intel_lrc.c | 1 +
> drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++
> 2 files changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index ab344e0..02213c6 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1735,6 +1735,7 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
> if (flush_domains) {
> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
> flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
> + flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
> flags |= PIPE_CONTROL_FLUSH_ENABLE;
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 4060acf..8cd8aab 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -331,6 +331,7 @@ gen7_render_ring_flush(struct drm_i915_gem_request *req,
> if (flush_domains) {
> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
> flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
> + flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
> flags |= PIPE_CONTROL_FLUSH_ENABLE;
> }
> if (invalidate_domains) {
> @@ -403,6 +404,7 @@ gen8_render_ring_flush(struct drm_i915_gem_request *req,
> if (flush_domains) {
> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
> flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
> + flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
> flags |= PIPE_CONTROL_FLUSH_ENABLE;
> }
> if (invalidate_domains) {
> --
> 2.7.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH] drm/i915: Make sure DC writes are coherent on flush.
2016-01-14 2:59 [PATCH] drm/i915: Make sure DC writes are coherent on flush Francisco Jerez
2016-01-14 5:33 ` Mark Janes
@ 2016-01-14 7:58 ` Jani Nikula
2016-01-14 10:01 ` Ville Syrjälä
2016-01-14 9:19 ` Ville Syrjälä
` (2 subsequent siblings)
4 siblings, 1 reply; 31+ messages in thread
From: Jani Nikula @ 2016-01-14 7:58 UTC (permalink / raw)
To: Francisco Jerez, intel-gfx; +Cc: Rodrigo Vivi
On Thu, 14 Jan 2016, Francisco Jerez <currojerez@riseup.net> wrote:
> We need to set the DC FLUSH PIPE_CONTROL bit on Gen7+ to guarantee
> that writes performed via the HDC are visible in memory. Fixes an
> intermittent failure in a Piglit test that writes to a BO from a
> shader using GL atomic counters (implemented as HDC untyped atomics)
> and then expects the memory to read back the same value after mapping
> it on the CPU.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91298
> Tested-by: Mark Janes <mark.a.janes@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Should this be backported to stable kernels? Is this a regression, or
has it always been broken?
BR,
Jani.
> ---
> drivers/gpu/drm/i915/intel_lrc.c | 1 +
> drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++
> 2 files changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index ab344e0..02213c6 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1735,6 +1735,7 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
> if (flush_domains) {
> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
> flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
> + flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
> flags |= PIPE_CONTROL_FLUSH_ENABLE;
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 4060acf..8cd8aab 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -331,6 +331,7 @@ gen7_render_ring_flush(struct drm_i915_gem_request *req,
> if (flush_domains) {
> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
> flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
> + flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
> flags |= PIPE_CONTROL_FLUSH_ENABLE;
> }
> if (invalidate_domains) {
> @@ -403,6 +404,7 @@ gen8_render_ring_flush(struct drm_i915_gem_request *req,
> if (flush_domains) {
> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
> flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
> + flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
> flags |= PIPE_CONTROL_FLUSH_ENABLE;
> }
> if (invalidate_domains) {
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH] drm/i915: Make sure DC writes are coherent on flush.
2016-01-14 2:59 [PATCH] drm/i915: Make sure DC writes are coherent on flush Francisco Jerez
2016-01-14 5:33 ` Mark Janes
2016-01-14 7:58 ` Jani Nikula
@ 2016-01-14 9:19 ` Ville Syrjälä
2016-01-14 10:32 ` Jani Nikula
2016-01-14 10:49 ` ✓ success: Fi.CI.BAT Patchwork
4 siblings, 0 replies; 31+ messages in thread
From: Ville Syrjälä @ 2016-01-14 9:19 UTC (permalink / raw)
To: Francisco Jerez; +Cc: intel-gfx, Rodrigo Vivi
On Wed, Jan 13, 2016 at 06:59:39PM -0800, Francisco Jerez wrote:
> We need to set the DC FLUSH PIPE_CONTROL bit on Gen7+ to guarantee
> that writes performed via the HDC are visible in memory. Fixes an
> intermittent failure in a Piglit test that writes to a BO from a
> shader using GL atomic counters (implemented as HDC untyped atomics)
> and then expects the memory to read back the same value after mapping
> it on the CPU.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91298
> Tested-by: Mark Janes <mark.a.janes@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_lrc.c | 1 +
> drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++
> 2 files changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index ab344e0..02213c6 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1735,6 +1735,7 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
> if (flush_domains) {
> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
> flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
> + flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
> flags |= PIPE_CONTROL_FLUSH_ENABLE;
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 4060acf..8cd8aab 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -331,6 +331,7 @@ gen7_render_ring_flush(struct drm_i915_gem_request *req,
> if (flush_domains) {
> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
> flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
> + flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
> flags |= PIPE_CONTROL_FLUSH_ENABLE;
> }
> if (invalidate_domains) {
> @@ -403,6 +404,7 @@ gen8_render_ring_flush(struct drm_i915_gem_request *req,
> if (flush_domains) {
> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
> flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
> + flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
> flags |= PIPE_CONTROL_FLUSH_ENABLE;
> }
> if (invalidate_domains) {
> --
> 2.7.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH] drm/i915: Make sure DC writes are coherent on flush.
2016-01-14 7:58 ` Jani Nikula
@ 2016-01-14 10:01 ` Ville Syrjälä
0 siblings, 0 replies; 31+ messages in thread
From: Ville Syrjälä @ 2016-01-14 10:01 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, Rodrigo Vivi
On Thu, Jan 14, 2016 at 09:58:00AM +0200, Jani Nikula wrote:
> On Thu, 14 Jan 2016, Francisco Jerez <currojerez@riseup.net> wrote:
> > We need to set the DC FLUSH PIPE_CONTROL bit on Gen7+ to guarantee
> > that writes performed via the HDC are visible in memory. Fixes an
> > intermittent failure in a Piglit test that writes to a BO from a
> > shader using GL atomic counters (implemented as HDC untyped atomics)
> > and then expects the memory to read back the same value after mapping
> > it on the CPU.
> >
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91298
> > Tested-by: Mark Janes <mark.a.janes@intel.com>
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> Should this be backported to stable kernels? Is this a regression, or
> has it always been broken?
It was always missing, but since Mesa wasn't dirtying the DC it didn't
matter.
I'd say put cc:stable on it. I can't see much risk of regressions from
this, and it would allow using a modern Mesa with stable kernels without
hitting these problems.
>
> BR,
> Jani.
>
>
> > ---
> > drivers/gpu/drm/i915/intel_lrc.c | 1 +
> > drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++
> > 2 files changed, 3 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> > index ab344e0..02213c6 100644
> > --- a/drivers/gpu/drm/i915/intel_lrc.c
> > +++ b/drivers/gpu/drm/i915/intel_lrc.c
> > @@ -1735,6 +1735,7 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
> > if (flush_domains) {
> > flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
> > flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
> > + flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
> > flags |= PIPE_CONTROL_FLUSH_ENABLE;
> > }
> >
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > index 4060acf..8cd8aab 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > @@ -331,6 +331,7 @@ gen7_render_ring_flush(struct drm_i915_gem_request *req,
> > if (flush_domains) {
> > flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
> > flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
> > + flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
> > flags |= PIPE_CONTROL_FLUSH_ENABLE;
> > }
> > if (invalidate_domains) {
> > @@ -403,6 +404,7 @@ gen8_render_ring_flush(struct drm_i915_gem_request *req,
> > if (flush_domains) {
> > flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
> > flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
> > + flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
> > flags |= PIPE_CONTROL_FLUSH_ENABLE;
> > }
> > if (invalidate_domains) {
>
> --
> Jani Nikula, Intel Open Source Technology Center
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH] drm/i915: Make sure DC writes are coherent on flush.
2016-01-14 2:59 [PATCH] drm/i915: Make sure DC writes are coherent on flush Francisco Jerez
` (2 preceding siblings ...)
2016-01-14 9:19 ` Ville Syrjälä
@ 2016-01-14 10:32 ` Jani Nikula
2016-01-14 17:16 ` Francisco Jerez
2016-01-14 10:49 ` ✓ success: Fi.CI.BAT Patchwork
4 siblings, 1 reply; 31+ messages in thread
From: Jani Nikula @ 2016-01-14 10:32 UTC (permalink / raw)
To: Francisco Jerez, intel-gfx; +Cc: Rodrigo Vivi
On Thu, 14 Jan 2016, Francisco Jerez <currojerez@riseup.net> wrote:
> We need to set the DC FLUSH PIPE_CONTROL bit on Gen7+ to guarantee
> that writes performed via the HDC are visible in memory. Fixes an
> intermittent failure in a Piglit test that writes to a BO from a
> shader using GL atomic counters (implemented as HDC untyped atomics)
> and then expects the memory to read back the same value after mapping
> it on the CPU.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91298
> Tested-by: Mark Janes <mark.a.janes@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Francisco, this is missing your Signed-off-by i.e. developer certificate
of origin http://developercertificate.org/ - can't push without. Please
reply with that.
BR,
Jani.
> ---
> drivers/gpu/drm/i915/intel_lrc.c | 1 +
> drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++
> 2 files changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index ab344e0..02213c6 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1735,6 +1735,7 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
> if (flush_domains) {
> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
> flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
> + flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
> flags |= PIPE_CONTROL_FLUSH_ENABLE;
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 4060acf..8cd8aab 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -331,6 +331,7 @@ gen7_render_ring_flush(struct drm_i915_gem_request *req,
> if (flush_domains) {
> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
> flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
> + flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
> flags |= PIPE_CONTROL_FLUSH_ENABLE;
> }
> if (invalidate_domains) {
> @@ -403,6 +404,7 @@ gen8_render_ring_flush(struct drm_i915_gem_request *req,
> if (flush_domains) {
> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
> flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
> + flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
> flags |= PIPE_CONTROL_FLUSH_ENABLE;
> }
> if (invalidate_domains) {
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* ✓ success: Fi.CI.BAT
2016-01-14 2:59 [PATCH] drm/i915: Make sure DC writes are coherent on flush Francisco Jerez
` (3 preceding siblings ...)
2016-01-14 10:32 ` Jani Nikula
@ 2016-01-14 10:49 ` Patchwork
4 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2016-01-14 10:49 UTC (permalink / raw)
To: Francisco Jerez; +Cc: intel-gfx
== Summary ==
Built on 058740f8fced6851aeda34f366f5330322cd585f drm-intel-nightly: 2016y-01m-13d-17h-07m-44s UTC integration manifest
Test gem_storedw_loop:
Subgroup basic-render:
dmesg-warn -> PASS (skl-i7k-2) UNSTABLE
Test kms_flip:
Subgroup basic-flip-vs-dpms:
dmesg-warn -> PASS (ilk-hp8440p)
bdw-nuci7 total:138 pass:128 dwarn:1 dfail:0 fail:0 skip:9
bdw-ultra total:138 pass:132 dwarn:0 dfail:0 fail:0 skip:6
bsw-nuc-2 total:141 pass:115 dwarn:2 dfail:0 fail:0 skip:24
hsw-brixbox total:141 pass:134 dwarn:0 dfail:0 fail:0 skip:7
ilk-hp8440p total:141 pass:101 dwarn:3 dfail:0 fail:0 skip:37
ivb-t430s total:135 pass:122 dwarn:3 dfail:4 fail:0 skip:6
skl-i5k-2 total:141 pass:131 dwarn:2 dfail:0 fail:0 skip:8
skl-i7k-2 total:141 pass:132 dwarn:1 dfail:0 fail:0 skip:8
snb-dellxps total:141 pass:122 dwarn:5 dfail:0 fail:0 skip:14
snb-x220t total:141 pass:122 dwarn:5 dfail:0 fail:1 skip:13
Results at /archive/results/CI_IGT_test/Patchwork_1181/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH] drm/i915: Make sure DC writes are coherent on flush.
2016-01-14 10:32 ` Jani Nikula
@ 2016-01-14 17:16 ` Francisco Jerez
2016-01-15 9:52 ` Jani Nikula
0 siblings, 1 reply; 31+ messages in thread
From: Francisco Jerez @ 2016-01-14 17:16 UTC (permalink / raw)
To: Jani Nikula, intel-gfx; +Cc: Rodrigo Vivi
[-- Attachment #1.1.1: Type: text/plain, Size: 2663 bytes --]
Jani Nikula <jani.nikula@linux.intel.com> writes:
> On Thu, 14 Jan 2016, Francisco Jerez <currojerez@riseup.net> wrote:
>> We need to set the DC FLUSH PIPE_CONTROL bit on Gen7+ to guarantee
>> that writes performed via the HDC are visible in memory. Fixes an
>> intermittent failure in a Piglit test that writes to a BO from a
>> shader using GL atomic counters (implemented as HDC untyped atomics)
>> and then expects the memory to read back the same value after mapping
>> it on the CPU.
>>
>> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91298
>> Tested-by: Mark Janes <mark.a.janes@intel.com>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> Francisco, this is missing your Signed-off-by i.e. developer certificate
> of origin http://developercertificate.org/ - can't push without. Please
> reply with that.
>
Oops, sorry for that -- And yeah it shouldn't hurt to CC stable too.
Signed-off-by: Francisco Jerez <currojerez@riseup.net>
> BR,
> Jani.
>
>
>> ---
>> drivers/gpu/drm/i915/intel_lrc.c | 1 +
>> drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++
>> 2 files changed, 3 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
>> index ab344e0..02213c6 100644
>> --- a/drivers/gpu/drm/i915/intel_lrc.c
>> +++ b/drivers/gpu/drm/i915/intel_lrc.c
>> @@ -1735,6 +1735,7 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
>> if (flush_domains) {
>> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
>> flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
>> + flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
>> flags |= PIPE_CONTROL_FLUSH_ENABLE;
>> }
>>
>> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> index 4060acf..8cd8aab 100644
>> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
>> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> @@ -331,6 +331,7 @@ gen7_render_ring_flush(struct drm_i915_gem_request *req,
>> if (flush_domains) {
>> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
>> flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
>> + flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
>> flags |= PIPE_CONTROL_FLUSH_ENABLE;
>> }
>> if (invalidate_domains) {
>> @@ -403,6 +404,7 @@ gen8_render_ring_flush(struct drm_i915_gem_request *req,
>> if (flush_domains) {
>> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
>> flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
>> + flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
>> flags |= PIPE_CONTROL_FLUSH_ENABLE;
>> }
>> if (invalidate_domains) {
>
> --
> Jani Nikula, Intel Open Source Technology Center
[-- Attachment #1.2: signature.asc --]
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[-- Attachment #2: Type: text/plain, Size: 159 bytes --]
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^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH] drm/i915: Make sure DC writes are coherent on flush.
2016-01-14 17:16 ` Francisco Jerez
@ 2016-01-15 9:52 ` Jani Nikula
0 siblings, 0 replies; 31+ messages in thread
From: Jani Nikula @ 2016-01-15 9:52 UTC (permalink / raw)
To: Francisco Jerez, intel-gfx; +Cc: Rodrigo Vivi
On Thu, 14 Jan 2016, Francisco Jerez <currojerez@riseup.net> wrote:
> Jani Nikula <jani.nikula@linux.intel.com> writes:
>
>> On Thu, 14 Jan 2016, Francisco Jerez <currojerez@riseup.net> wrote:
>>> We need to set the DC FLUSH PIPE_CONTROL bit on Gen7+ to guarantee
>>> that writes performed via the HDC are visible in memory. Fixes an
>>> intermittent failure in a Piglit test that writes to a BO from a
>>> shader using GL atomic counters (implemented as HDC untyped atomics)
>>> and then expects the memory to read back the same value after mapping
>>> it on the CPU.
>>>
>>> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91298
>>> Tested-by: Mark Janes <mark.a.janes@intel.com>
>>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>
>> Francisco, this is missing your Signed-off-by i.e. developer certificate
>> of origin http://developercertificate.org/ - can't push without. Please
>> reply with that.
>>
> Oops, sorry for that -- And yeah it shouldn't hurt to CC stable too.
>
> Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Pushed to drm-intel-next-queued, thanks for the patch and review.
BR,
Jani.
>
>> BR,
>> Jani.
>>
>>
>>> ---
>>> drivers/gpu/drm/i915/intel_lrc.c | 1 +
>>> drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++
>>> 2 files changed, 3 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
>>> index ab344e0..02213c6 100644
>>> --- a/drivers/gpu/drm/i915/intel_lrc.c
>>> +++ b/drivers/gpu/drm/i915/intel_lrc.c
>>> @@ -1735,6 +1735,7 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
>>> if (flush_domains) {
>>> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
>>> flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
>>> + flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
>>> flags |= PIPE_CONTROL_FLUSH_ENABLE;
>>> }
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
>>> index 4060acf..8cd8aab 100644
>>> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
>>> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
>>> @@ -331,6 +331,7 @@ gen7_render_ring_flush(struct drm_i915_gem_request *req,
>>> if (flush_domains) {
>>> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
>>> flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
>>> + flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
>>> flags |= PIPE_CONTROL_FLUSH_ENABLE;
>>> }
>>> if (invalidate_domains) {
>>> @@ -403,6 +404,7 @@ gen8_render_ring_flush(struct drm_i915_gem_request *req,
>>> if (flush_domains) {
>>> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
>>> flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
>>> + flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
>>> flags |= PIPE_CONTROL_FLUSH_ENABLE;
>>> }
>>> if (invalidate_domains) {
>>
>> --
>> Jani Nikula, Intel Open Source Technology Center
--
Jani Nikula, Intel Open Source Technology Center
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^ permalink raw reply [flat|nested] 31+ messages in thread
* ✓ success: Fi.CI.BAT
2016-01-14 10:53 [PATCH] drm/i915: add onoff utility function Jani Nikula
@ 2016-01-14 12:49 ` Patchwork
0 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2016-01-14 12:49 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Summary ==
Built on 058740f8fced6851aeda34f366f5330322cd585f drm-intel-nightly: 2016y-01m-13d-17h-07m-44s UTC integration manifest
bdw-nuci7 total:138 pass:128 dwarn:1 dfail:0 fail:0 skip:9
bdw-ultra total:138 pass:132 dwarn:0 dfail:0 fail:0 skip:6
hsw-brixbox total:141 pass:134 dwarn:0 dfail:0 fail:0 skip:7
hsw-gt2 total:141 pass:137 dwarn:0 dfail:0 fail:0 skip:4
ilk-hp8440p total:141 pass:100 dwarn:4 dfail:0 fail:0 skip:37
ivb-t430s total:135 pass:122 dwarn:3 dfail:4 fail:0 skip:6
skl-i7k-2 total:141 pass:131 dwarn:2 dfail:0 fail:0 skip:8
snb-dellxps total:141 pass:122 dwarn:5 dfail:0 fail:0 skip:14
Results at /archive/results/CI_IGT_test/Patchwork_1185/
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^ permalink raw reply [flat|nested] 31+ messages in thread
* ✓ success: Fi.CI.BAT
2016-01-13 17:38 [PATCH] drm/i915: Demote user facing DMC firmware load failure message Chris Wilson
@ 2016-01-14 9:20 ` Patchwork
0 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2016-01-14 9:20 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Summary ==
Built on 058740f8fced6851aeda34f366f5330322cd585f drm-intel-nightly: 2016y-01m-13d-17h-07m-44s UTC integration manifest
Test kms_flip:
Subgroup basic-flip-vs-dpms:
dmesg-warn -> PASS (ilk-hp8440p)
bdw-nuci7 total:138 pass:128 dwarn:1 dfail:0 fail:0 skip:9
bdw-ultra total:138 pass:132 dwarn:0 dfail:0 fail:0 skip:6
bsw-nuc-2 total:141 pass:115 dwarn:2 dfail:0 fail:0 skip:24
hsw-brixbox total:141 pass:134 dwarn:0 dfail:0 fail:0 skip:7
ilk-hp8440p total:141 pass:101 dwarn:3 dfail:0 fail:0 skip:37
ivb-t430s total:135 pass:122 dwarn:3 dfail:4 fail:0 skip:6
skl-i5k-2 total:141 pass:131 dwarn:2 dfail:0 fail:0 skip:8
skl-i7k-2 total:141 pass:131 dwarn:2 dfail:0 fail:0 skip:8
snb-dellxps total:141 pass:122 dwarn:5 dfail:0 fail:0 skip:14
snb-x220t total:141 pass:122 dwarn:5 dfail:0 fail:1 skip:13
Results at /archive/results/CI_IGT_test/Patchwork_1178/
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^ permalink raw reply [flat|nested] 31+ messages in thread
* ✓ success: Fi.CI.BAT
2016-01-13 17:04 [PATCH] drm/i915: Force ordering on request submission and hangcheck Mika Kuoppala
@ 2016-01-14 8:20 ` Patchwork
0 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2016-01-14 8:20 UTC (permalink / raw)
To: Mika Kuoppala; +Cc: intel-gfx
== Summary ==
Built on 058740f8fced6851aeda34f366f5330322cd585f drm-intel-nightly: 2016y-01m-13d-17h-07m-44s UTC integration manifest
Test gem_storedw_loop:
Subgroup basic-render:
dmesg-warn -> PASS (bdw-nuci7)
Test kms_flip:
Subgroup basic-flip-vs-dpms:
dmesg-warn -> PASS (ilk-hp8440p)
bdw-nuci7 total:138 pass:129 dwarn:0 dfail:0 fail:0 skip:9
bdw-ultra total:138 pass:132 dwarn:0 dfail:0 fail:0 skip:6
bsw-nuc-2 total:141 pass:115 dwarn:2 dfail:0 fail:0 skip:24
hsw-brixbox total:141 pass:134 dwarn:0 dfail:0 fail:0 skip:7
ilk-hp8440p total:141 pass:101 dwarn:3 dfail:0 fail:0 skip:37
ivb-t430s total:135 pass:122 dwarn:3 dfail:4 fail:0 skip:6
skl-i5k-2 total:141 pass:131 dwarn:2 dfail:0 fail:0 skip:8
skl-i7k-2 total:141 pass:131 dwarn:2 dfail:0 fail:0 skip:8
snb-dellxps total:141 pass:122 dwarn:5 dfail:0 fail:0 skip:14
snb-x220t total:141 pass:122 dwarn:5 dfail:0 fail:1 skip:13
Results at /archive/results/CI_IGT_test/Patchwork_1176/
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* ✓ success: Fi.CI.BAT
2016-01-13 16:33 [PATCH] drm/i915: Dump power well states on unclaimed trace Mika Kuoppala
@ 2016-01-14 7:49 ` Patchwork
0 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2016-01-14 7:49 UTC (permalink / raw)
To: Mika Kuoppala; +Cc: intel-gfx
== Summary ==
Built on 058740f8fced6851aeda34f366f5330322cd585f drm-intel-nightly: 2016y-01m-13d-17h-07m-44s UTC integration manifest
Test gem_storedw_loop:
Subgroup basic-render:
dmesg-warn -> PASS (bdw-nuci7)
dmesg-warn -> PASS (skl-i7k-2) UNSTABLE
bdw-nuci7 total:138 pass:129 dwarn:0 dfail:0 fail:0 skip:9
bdw-ultra total:138 pass:132 dwarn:0 dfail:0 fail:0 skip:6
bsw-nuc-2 total:141 pass:115 dwarn:2 dfail:0 fail:0 skip:24
hsw-brixbox total:141 pass:134 dwarn:0 dfail:0 fail:0 skip:7
ilk-hp8440p total:141 pass:100 dwarn:4 dfail:0 fail:0 skip:37
ivb-t430s total:135 pass:122 dwarn:3 dfail:4 fail:0 skip:6
skl-i5k-2 total:141 pass:131 dwarn:2 dfail:0 fail:0 skip:8
skl-i7k-2 total:141 pass:132 dwarn:1 dfail:0 fail:0 skip:8
snb-dellxps total:141 pass:122 dwarn:5 dfail:0 fail:0 skip:14
snb-x220t total:141 pass:122 dwarn:5 dfail:0 fail:1 skip:13
Results at /archive/results/CI_IGT_test/Patchwork_1175/
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^ permalink raw reply [flat|nested] 31+ messages in thread
* ✓ success: Fi.CI.BAT
2015-12-21 11:57 [PATCH] drm/i915: Handle PipeC fused off on HSW Gabriel Feceoru
@ 2016-01-13 15:41 ` Patchwork
0 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2016-01-13 15:41 UTC (permalink / raw)
To: Feceoru, Gabriel; +Cc: intel-gfx
== Summary ==
Built on aa7ddea990dfc10c7e90ad10820e0121a9667453 drm-intel-nightly: 2016y-01m-13d-15h-05m-13s UTC integration manifest
Test kms_pipe_crc_basic:
Subgroup nonblocking-crc-pipe-b:
skip -> PASS (bdw-nuci7)
Subgroup nonblocking-crc-pipe-c:
pass -> SKIP (bdw-nuci7)
bdw-nuci7 total:138 pass:128 dwarn:0 dfail:0 fail:0 skip:10
bdw-ultra total:138 pass:131 dwarn:1 dfail:0 fail:0 skip:6
bsw-nuc-2 total:141 pass:115 dwarn:2 dfail:0 fail:0 skip:24
hsw-brixbox total:141 pass:134 dwarn:0 dfail:0 fail:0 skip:7
hsw-gt2 total:141 pass:137 dwarn:0 dfail:0 fail:0 skip:4
ilk-hp8440p total:141 pass:101 dwarn:3 dfail:0 fail:0 skip:37
ivb-t430s total:135 pass:122 dwarn:3 dfail:4 fail:0 skip:6
skl-i5k-2 total:141 pass:131 dwarn:2 dfail:0 fail:0 skip:8
skl-i7k-2 total:141 pass:131 dwarn:2 dfail:0 fail:0 skip:8
snb-dellxps total:141 pass:122 dwarn:5 dfail:0 fail:0 skip:14
Results at /archive/results/CI_IGT_test/Patchwork_1171/
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^ permalink raw reply [flat|nested] 31+ messages in thread
* ✓ success: Fi.CI.BAT
2016-01-13 10:44 [PATCH] drm/i915: Expose exec parameter to force non IA-Coherent for Gen9+ Artur Harasimiuk
@ 2016-01-13 11:49 ` Patchwork
0 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2016-01-13 11:49 UTC (permalink / raw)
To: Artur Harasimiuk; +Cc: intel-gfx
== Summary ==
Built on 8da57dfe6c675c35109dac986e3f8b627cffab49 drm-intel-nightly: 2016y-01m-13d-10h-33m-04s UTC integration manifest
Test gem_storedw_loop:
Subgroup basic-render:
pass -> DMESG-WARN (skl-i5k-2) UNSTABLE
dmesg-warn -> PASS (bdw-nuci7)
dmesg-warn -> PASS (bdw-ultra)
Test kms_flip:
Subgroup basic-flip-vs-dpms:
dmesg-warn -> PASS (ilk-hp8440p)
Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-b:
dmesg-warn -> PASS (bdw-ultra)
Subgroup suspend-read-crc-pipe-a:
dmesg-warn -> PASS (snb-x220t)
bdw-nuci7 total:138 pass:129 dwarn:0 dfail:0 fail:0 skip:9
bdw-ultra total:138 pass:132 dwarn:0 dfail:0 fail:0 skip:6
bsw-nuc-2 total:141 pass:115 dwarn:2 dfail:0 fail:0 skip:24
hsw-brixbox total:141 pass:134 dwarn:0 dfail:0 fail:0 skip:7
hsw-gt2 total:141 pass:137 dwarn:0 dfail:0 fail:0 skip:4
ilk-hp8440p total:141 pass:101 dwarn:3 dfail:0 fail:0 skip:37
ivb-t430s total:135 pass:122 dwarn:3 dfail:4 fail:0 skip:6
skl-i5k-2 total:141 pass:131 dwarn:2 dfail:0 fail:0 skip:8
skl-i7k-2 total:141 pass:131 dwarn:2 dfail:0 fail:0 skip:8
snb-dellxps total:141 pass:122 dwarn:5 dfail:0 fail:0 skip:14
snb-x220t total:141 pass:122 dwarn:5 dfail:0 fail:1 skip:13
Results at /archive/results/CI_IGT_test/Patchwork_1162/
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* ✓ success: Fi.CI.BAT
2016-01-13 10:06 [PATCH 0/8] Gen9 HW whitelist and Preemption WA patches Arun Siluvery
@ 2016-01-13 10:50 ` Patchwork
0 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2016-01-13 10:50 UTC (permalink / raw)
To: arun.siluvery; +Cc: intel-gfx
== Summary ==
Built on dd4a7926b4118f72b7ae0f7b97e9644172df472c drm-intel-nightly: 2016y-01m-13d-09h-05m-34s UTC integration manifest
Test gem_storedw_loop:
Subgroup basic-render:
pass -> DMESG-WARN (skl-i5k-2) UNSTABLE
bdw-nuci7 total:138 pass:129 dwarn:0 dfail:0 fail:0 skip:9
bdw-ultra total:138 pass:132 dwarn:0 dfail:0 fail:0 skip:6
bsw-nuc-2 total:141 pass:115 dwarn:2 dfail:0 fail:0 skip:24
hsw-brixbox total:141 pass:134 dwarn:0 dfail:0 fail:0 skip:7
hsw-gt2 total:141 pass:137 dwarn:0 dfail:0 fail:0 skip:4
hsw-xps12 total:138 pass:133 dwarn:1 dfail:0 fail:0 skip:4
ilk-hp8440p total:141 pass:101 dwarn:3 dfail:0 fail:0 skip:37
ivb-t430s total:135 pass:122 dwarn:3 dfail:4 fail:0 skip:6
skl-i5k-2 total:141 pass:131 dwarn:2 dfail:0 fail:0 skip:8
snb-dellxps total:141 pass:122 dwarn:5 dfail:0 fail:0 skip:14
snb-x220t total:141 pass:122 dwarn:5 dfail:0 fail:1 skip:13
Results at /archive/results/CI_IGT_test/Patchwork_1161/
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^ permalink raw reply [flat|nested] 31+ messages in thread
* ✓ success: Fi.CI.BAT
2016-01-12 23:40 [PATCH] drm/i915: Allow i915_gem_object_get_page() on userptr as well Chris Wilson
@ 2016-01-13 9:20 ` Patchwork
0 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2016-01-13 9:20 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Summary ==
Built on 06d0112e293dfdea7f796d4085f755898850947b drm-intel-nightly: 2016y-01m-12d-21h-16m-40s UTC integration manifest
Test gem_storedw_loop:
Subgroup basic-render:
dmesg-warn -> PASS (bdw-ultra)
Test kms_flip:
Subgroup basic-flip-vs-dpms:
dmesg-warn -> PASS (skl-i7k-2)
Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-a-frame-sequence:
fail -> PASS (snb-x220t)
bdw-nuci7 total:138 pass:129 dwarn:0 dfail:0 fail:0 skip:9
bdw-ultra total:138 pass:132 dwarn:0 dfail:0 fail:0 skip:6
bsw-nuc-2 total:141 pass:115 dwarn:2 dfail:0 fail:0 skip:24
byt-nuc total:141 pass:123 dwarn:3 dfail:0 fail:0 skip:15
hsw-brixbox total:141 pass:134 dwarn:0 dfail:0 fail:0 skip:7
hsw-gt2 total:141 pass:137 dwarn:0 dfail:0 fail:0 skip:4
ilk-hp8440p total:141 pass:100 dwarn:4 dfail:0 fail:0 skip:37
skl-i5k-2 total:141 pass:132 dwarn:1 dfail:0 fail:0 skip:8
skl-i7k-2 total:141 pass:131 dwarn:2 dfail:0 fail:0 skip:8
snb-dellxps total:141 pass:122 dwarn:5 dfail:0 fail:0 skip:14
snb-x220t total:141 pass:122 dwarn:5 dfail:0 fail:1 skip:13
Results at /archive/results/CI_IGT_test/Patchwork_1159/
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* ✓ success: Fi.CI.BAT
2016-01-12 17:32 [PATCH 1/3] drm/i915: Extract vfunc setup from logical ring initializers Tvrtko Ursulin
@ 2016-01-13 8:11 ` Patchwork
0 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2016-01-13 8:11 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: intel-gfx
== Summary ==
Built on 06d0112e293dfdea7f796d4085f755898850947b drm-intel-nightly: 2016y-01m-12d-21h-16m-40s UTC integration manifest
Test gem_storedw_loop:
Subgroup basic-render:
dmesg-warn -> PASS (bdw-ultra)
Test kms_flip:
Subgroup basic-flip-vs-dpms:
dmesg-warn -> PASS (skl-i7k-2)
Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-a-frame-sequence:
fail -> PASS (snb-x220t)
bdw-nuci7 total:138 pass:129 dwarn:0 dfail:0 fail:0 skip:9
bdw-ultra total:138 pass:132 dwarn:0 dfail:0 fail:0 skip:6
byt-nuc total:141 pass:123 dwarn:3 dfail:0 fail:0 skip:15
hsw-brixbox total:141 pass:134 dwarn:0 dfail:0 fail:0 skip:7
hsw-gt2 total:141 pass:137 dwarn:0 dfail:0 fail:0 skip:4
hsw-xps12 total:138 pass:133 dwarn:1 dfail:0 fail:0 skip:4
ivb-t430s total:135 pass:122 dwarn:3 dfail:4 fail:0 skip:6
skl-i7k-2 total:141 pass:131 dwarn:2 dfail:0 fail:0 skip:8
snb-dellxps total:141 pass:122 dwarn:5 dfail:0 fail:0 skip:14
snb-x220t total:141 pass:122 dwarn:5 dfail:0 fail:1 skip:13
Results at /archive/results/CI_IGT_test/Patchwork_1156/
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: ✓ success: Fi.CI.BAT
2016-01-11 11:53 ` ✓ success: Fi.CI.BAT Patchwork
@ 2016-01-12 16:50 ` Daniel Vetter
0 siblings, 0 replies; 31+ messages in thread
From: Daniel Vetter @ 2016-01-12 16:50 UTC (permalink / raw)
To: Patchwork; +Cc: intel-gfx
On Mon, Jan 11, 2016 at 11:53:53AM -0000, Patchwork wrote:
> == Summary ==
>
> Built on ff88655b3a5467bbc3be8c67d3e05ebf182557d3 drm-intel-nightly: 2016y-01m-11d-07h-30m-16s UTC integration manifest
>
> Test gem_storedw_loop:
> Subgroup basic-render:
> dmesg-warn -> PASS (bdw-ultra)
> Test kms_flip:
> Subgroup basic-flip-vs-dpms:
> dmesg-warn -> PASS (ilk-hp8440p)
> Test kms_pipe_crc_basic:
> Subgroup read-crc-pipe-b:
> dmesg-warn -> PASS (byt-nuc)
>
> bdw-nuci7 total:138 pass:129 dwarn:0 dfail:0 fail:0 skip:9
> bdw-ultra total:138 pass:132 dwarn:0 dfail:0 fail:0 skip:6
> bsw-nuc-2 total:141 pass:114 dwarn:3 dfail:0 fail:0 skip:24
> byt-nuc total:141 pass:119 dwarn:7 dfail:0 fail:0 skip:15
> hsw-brixbox total:141 pass:134 dwarn:0 dfail:0 fail:0 skip:7
> hsw-gt2 total:141 pass:136 dwarn:0 dfail:0 fail:1 skip:4
> hsw-xps12 total:138 pass:133 dwarn:1 dfail:0 fail:0 skip:4
> ilk-hp8440p total:141 pass:101 dwarn:3 dfail:0 fail:0 skip:37
> ivb-t430s total:135 pass:122 dwarn:3 dfail:4 fail:0 skip:6
> skl-i5k-2 total:141 pass:132 dwarn:1 dfail:0 fail:0 skip:8
> skl-i7k-2 total:141 pass:131 dwarn:2 dfail:0 fail:0 skip:8
> snb-dellxps total:141 pass:122 dwarn:5 dfail:0 fail:0 skip:14
> snb-x220t total:141 pass:122 dwarn:5 dfail:0 fail:1 skip:13
>
> Results at /archive/results/CI_IGT_test/Patchwork_1125/
Yay, a lucky patch that passed bat, so merged it to dinq!
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* ✓ success: Fi.CI.BAT
2016-01-12 15:28 [PATCH] drm/i915: Only complain about n_edp_entries with eDP ports ville.syrjala
@ 2016-01-12 16:49 ` Patchwork
0 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2016-01-12 16:49 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
== Summary ==
Built on 37f6c2ae666fbba9eff4355115252b8b0fd43050 drm-intel-nightly: 2016y-01m-12d-14h-25m-44s UTC integration manifest
Test drv_module_reload_basic:
Subgroup none:
dmesg-warn -> PASS (skl-i5k-2)
dmesg-warn -> PASS (skl-i7k-2)
Test gem_storedw_loop:
Subgroup basic-render:
pass -> DMESG-WARN (skl-i5k-2) UNSTABLE
dmesg-warn -> PASS (bdw-nuci7)
Test kms_flip:
Subgroup basic-flip-vs-dpms:
dmesg-warn -> PASS (skl-i5k-2)
dmesg-warn -> PASS (skl-i7k-2)
Subgroup basic-flip-vs-modeset:
dmesg-warn -> PASS (skl-i5k-2)
dmesg-warn -> PASS (skl-i7k-2)
Subgroup basic-flip-vs-wf_vblank:
dmesg-warn -> PASS (skl-i5k-2)
dmesg-warn -> PASS (skl-i7k-2)
Subgroup basic-plain-flip:
dmesg-warn -> PASS (skl-i5k-2)
dmesg-warn -> PASS (skl-i7k-2)
Test kms_pipe_crc_basic:
Subgroup hang-read-crc-pipe-a:
dmesg-warn -> PASS (skl-i5k-2)
dmesg-warn -> PASS (skl-i7k-2)
Subgroup hang-read-crc-pipe-b:
dmesg-warn -> PASS (skl-i5k-2)
dmesg-warn -> PASS (skl-i7k-2)
Subgroup hang-read-crc-pipe-c:
dmesg-warn -> PASS (skl-i5k-2)
dmesg-warn -> PASS (skl-i7k-2)
Subgroup nonblocking-crc-pipe-a:
dmesg-warn -> PASS (skl-i5k-2)
dmesg-warn -> PASS (skl-i7k-2)
Subgroup nonblocking-crc-pipe-a-frame-sequence:
dmesg-warn -> PASS (skl-i5k-2)
dmesg-warn -> PASS (skl-i7k-2)
Subgroup nonblocking-crc-pipe-b:
dmesg-warn -> PASS (skl-i5k-2)
dmesg-warn -> PASS (skl-i7k-2)
Subgroup nonblocking-crc-pipe-b-frame-sequence:
dmesg-warn -> PASS (skl-i5k-2)
dmesg-warn -> PASS (skl-i7k-2)
Subgroup nonblocking-crc-pipe-c:
dmesg-warn -> PASS (skl-i5k-2)
dmesg-warn -> PASS (skl-i7k-2)
Subgroup nonblocking-crc-pipe-c-frame-sequence:
dmesg-warn -> PASS (skl-i5k-2)
dmesg-warn -> PASS (skl-i7k-2)
Subgroup read-crc-pipe-a:
dmesg-warn -> PASS (skl-i5k-2)
dmesg-warn -> PASS (skl-i7k-2)
Subgroup read-crc-pipe-a-frame-sequence:
dmesg-warn -> PASS (skl-i5k-2)
dmesg-warn -> PASS (skl-i7k-2)
dmesg-warn -> PASS (byt-nuc)
Subgroup read-crc-pipe-b:
dmesg-warn -> PASS (skl-i5k-2)
dmesg-warn -> PASS (skl-i7k-2)
Subgroup read-crc-pipe-b-frame-sequence:
dmesg-warn -> PASS (skl-i5k-2)
dmesg-warn -> PASS (skl-i7k-2)
Subgroup read-crc-pipe-c:
dmesg-warn -> PASS (skl-i5k-2)
dmesg-warn -> PASS (bdw-ultra)
dmesg-warn -> PASS (skl-i7k-2)
Subgroup read-crc-pipe-c-frame-sequence:
dmesg-warn -> PASS (skl-i5k-2)
dmesg-warn -> PASS (skl-i7k-2)
Subgroup suspend-read-crc-pipe-a:
dmesg-warn -> PASS (skl-i5k-2)
dmesg-warn -> PASS (skl-i7k-2)
Subgroup suspend-read-crc-pipe-c:
dmesg-warn -> PASS (skl-i5k-2)
dmesg-warn -> PASS (skl-i7k-2)
Test pm_rpm:
Subgroup basic-pci-d3-state:
dmesg-warn -> PASS (skl-i5k-2)
dmesg-warn -> PASS (skl-i7k-2)
Subgroup basic-rte:
dmesg-warn -> PASS (skl-i5k-2)
dmesg-warn -> PASS (skl-i7k-2)
bdw-nuci7 total:138 pass:129 dwarn:0 dfail:0 fail:0 skip:9
bdw-ultra total:138 pass:132 dwarn:0 dfail:0 fail:0 skip:6
bsw-nuc-2 total:141 pass:115 dwarn:2 dfail:0 fail:0 skip:24
byt-nuc total:141 pass:123 dwarn:3 dfail:0 fail:0 skip:15
hsw-brixbox total:141 pass:134 dwarn:0 dfail:0 fail:0 skip:7
hsw-gt2 total:141 pass:137 dwarn:0 dfail:0 fail:0 skip:4
hsw-xps12 total:138 pass:133 dwarn:1 dfail:0 fail:0 skip:4
ilk-hp8440p total:141 pass:101 dwarn:3 dfail:0 fail:0 skip:37
ivb-t430s total:135 pass:122 dwarn:3 dfail:4 fail:0 skip:6
skl-i5k-2 total:141 pass:131 dwarn:2 dfail:0 fail:0 skip:8
skl-i7k-2 total:141 pass:131 dwarn:2 dfail:0 fail:0 skip:8
snb-dellxps total:141 pass:122 dwarn:5 dfail:0 fail:0 skip:14
snb-x220t total:141 pass:122 dwarn:5 dfail:0 fail:1 skip:13
Results at /archive/results/CI_IGT_test/Patchwork_1153/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* ✓ success: Fi.CI.BAT
2016-01-12 15:00 [PATCH 0/3] LPSS PWM support for devices that support it Shobhit Kumar
@ 2016-01-12 15:20 ` Patchwork
0 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2016-01-12 15:20 UTC (permalink / raw)
To: Shobhit Kumar; +Cc: intel-gfx
== Summary ==
Built on 37f6c2ae666fbba9eff4355115252b8b0fd43050 drm-intel-nightly: 2016y-01m-12d-14h-25m-44s UTC integration manifest
Test gem_storedw_loop:
Subgroup basic-render:
dmesg-warn -> PASS (bdw-nuci7)
Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-a-frame-sequence:
dmesg-warn -> PASS (byt-nuc)
Subgroup read-crc-pipe-c:
dmesg-warn -> PASS (bdw-ultra)
bdw-nuci7 total:138 pass:129 dwarn:0 dfail:0 fail:0 skip:9
bdw-ultra total:138 pass:132 dwarn:0 dfail:0 fail:0 skip:6
bsw-nuc-2 total:141 pass:115 dwarn:2 dfail:0 fail:0 skip:24
byt-nuc total:141 pass:123 dwarn:3 dfail:0 fail:0 skip:15
hsw-brixbox total:141 pass:134 dwarn:0 dfail:0 fail:0 skip:7
hsw-gt2 total:141 pass:137 dwarn:0 dfail:0 fail:0 skip:4
ilk-hp8440p total:141 pass:101 dwarn:3 dfail:0 fail:0 skip:37
ivb-t430s total:135 pass:122 dwarn:3 dfail:4 fail:0 skip:6
skl-i5k-2 total:141 pass:108 dwarn:25 dfail:0 fail:0 skip:8
skl-i7k-2 total:141 pass:107 dwarn:26 dfail:0 fail:0 skip:8
snb-dellxps total:141 pass:122 dwarn:5 dfail:0 fail:0 skip:14
snb-x220t total:141 pass:122 dwarn:5 dfail:0 fail:1 skip:13
Results at /archive/results/CI_IGT_test/Patchwork_1150/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* ✓ success: Fi.CI.BAT
2016-01-11 19:54 [PATCH v2 0/6] drm/i915: start hiding away vbt structure from the driver Jani Nikula
@ 2016-01-12 8:20 ` Patchwork
0 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2016-01-12 8:20 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Summary ==
Built on a90796840c30dac6d9907439bf98d1d08046c49d drm-intel-nightly: 2016y-01m-11d-17h-22m-54s UTC integration manifest
Test gem_storedw_loop:
Subgroup basic-render:
pass -> DMESG-WARN (skl-i5k-2) UNSTABLE
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
dmesg-warn -> PASS (ilk-hp8440p)
bdw-nuci7 total:138 pass:129 dwarn:0 dfail:0 fail:0 skip:9
bdw-ultra total:138 pass:132 dwarn:0 dfail:0 fail:0 skip:6
bsw-nuc-2 total:141 pass:115 dwarn:2 dfail:0 fail:0 skip:24
byt-nuc total:141 pass:123 dwarn:3 dfail:0 fail:0 skip:15
hsw-brixbox total:141 pass:134 dwarn:0 dfail:0 fail:0 skip:7
hsw-gt2 total:141 pass:137 dwarn:0 dfail:0 fail:0 skip:4
ilk-hp8440p total:141 pass:102 dwarn:2 dfail:0 fail:0 skip:37
ivb-t430s total:135 pass:122 dwarn:3 dfail:4 fail:0 skip:6
skl-i5k-2 total:141 pass:131 dwarn:2 dfail:0 fail:0 skip:8
skl-i7k-2 total:141 pass:132 dwarn:1 dfail:0 fail:0 skip:8
snb-dellxps total:141 pass:122 dwarn:5 dfail:0 fail:0 skip:14
snb-x220t total:141 pass:122 dwarn:5 dfail:0 fail:1 skip:13
Results at /archive/results/CI_IGT_test/Patchwork_1138/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* ✓ success: Fi.CI.BAT
2016-01-11 11:39 [PATCH] drm/i915/gen9: Set PIN_ZONE_4G end to 4GB - 1 page Michel Thierry
@ 2016-01-11 11:53 ` Patchwork
2016-01-12 16:50 ` Daniel Vetter
0 siblings, 1 reply; 31+ messages in thread
From: Patchwork @ 2016-01-11 11:53 UTC (permalink / raw)
To: Michel Thierry; +Cc: intel-gfx
== Summary ==
Built on ff88655b3a5467bbc3be8c67d3e05ebf182557d3 drm-intel-nightly: 2016y-01m-11d-07h-30m-16s UTC integration manifest
Test gem_storedw_loop:
Subgroup basic-render:
dmesg-warn -> PASS (bdw-ultra)
Test kms_flip:
Subgroup basic-flip-vs-dpms:
dmesg-warn -> PASS (ilk-hp8440p)
Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-b:
dmesg-warn -> PASS (byt-nuc)
bdw-nuci7 total:138 pass:129 dwarn:0 dfail:0 fail:0 skip:9
bdw-ultra total:138 pass:132 dwarn:0 dfail:0 fail:0 skip:6
bsw-nuc-2 total:141 pass:114 dwarn:3 dfail:0 fail:0 skip:24
byt-nuc total:141 pass:119 dwarn:7 dfail:0 fail:0 skip:15
hsw-brixbox total:141 pass:134 dwarn:0 dfail:0 fail:0 skip:7
hsw-gt2 total:141 pass:136 dwarn:0 dfail:0 fail:1 skip:4
hsw-xps12 total:138 pass:133 dwarn:1 dfail:0 fail:0 skip:4
ilk-hp8440p total:141 pass:101 dwarn:3 dfail:0 fail:0 skip:37
ivb-t430s total:135 pass:122 dwarn:3 dfail:4 fail:0 skip:6
skl-i5k-2 total:141 pass:132 dwarn:1 dfail:0 fail:0 skip:8
skl-i7k-2 total:141 pass:131 dwarn:2 dfail:0 fail:0 skip:8
snb-dellxps total:141 pass:122 dwarn:5 dfail:0 fail:0 skip:14
snb-x220t total:141 pass:122 dwarn:5 dfail:0 fail:1 skip:13
Results at /archive/results/CI_IGT_test/Patchwork_1125/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* ✓ success: Fi.CI.BAT
2016-01-09 11:30 [PATCH] drm/i915: Support to enable TRTT on GEN9 akash.goel
@ 2016-01-11 11:19 ` Patchwork
0 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2016-01-11 11:19 UTC (permalink / raw)
To: Akash Goel; +Cc: intel-gfx
== Summary ==
Built on ff88655b3a5467bbc3be8c67d3e05ebf182557d3 drm-intel-nightly: 2016y-01m-11d-07h-30m-16s UTC integration manifest
Test gem_storedw_loop:
Subgroup basic-render:
pass -> DMESG-WARN (skl-i5k-2) UNSTABLE
dmesg-warn -> PASS (bdw-ultra)
dmesg-warn -> PASS (skl-i7k-2) UNSTABLE
Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-b:
dmesg-warn -> PASS (byt-nuc)
bdw-nuci7 total:138 pass:129 dwarn:0 dfail:0 fail:0 skip:9
bdw-ultra total:138 pass:132 dwarn:0 dfail:0 fail:0 skip:6
bsw-nuc-2 total:141 pass:114 dwarn:3 dfail:0 fail:0 skip:24
byt-nuc total:141 pass:119 dwarn:7 dfail:0 fail:0 skip:15
hsw-brixbox total:141 pass:134 dwarn:0 dfail:0 fail:0 skip:7
hsw-gt2 total:141 pass:137 dwarn:0 dfail:0 fail:0 skip:4
ilk-hp8440p total:141 pass:100 dwarn:4 dfail:0 fail:0 skip:37
ivb-t430s total:135 pass:122 dwarn:3 dfail:4 fail:0 skip:6
skl-i5k-2 total:141 pass:131 dwarn:2 dfail:0 fail:0 skip:8
skl-i7k-2 total:141 pass:132 dwarn:1 dfail:0 fail:0 skip:8
snb-dellxps total:141 pass:122 dwarn:5 dfail:0 fail:0 skip:14
snb-x220t total:141 pass:122 dwarn:5 dfail:0 fail:1 skip:13
Results at /archive/results/CI_IGT_test/Patchwork_1121/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* ✓ success: Fi.CI.BAT
2016-01-07 16:36 [PATCH 0/6] Misc cleanups Tvrtko Ursulin
@ 2016-01-11 9:27 ` Patchwork
0 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2016-01-11 9:27 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: intel-gfx
== Summary ==
Built on ff88655b3a5467bbc3be8c67d3e05ebf182557d3 drm-intel-nightly: 2016y-01m-11d-07h-30m-16s UTC integration manifest
Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-b:
dmesg-warn -> PASS (byt-nuc)
bdw-ultra total:138 pass:130 dwarn:1 dfail:0 fail:1 skip:6
bsw-nuc-2 total:141 pass:114 dwarn:3 dfail:0 fail:0 skip:24
byt-nuc total:141 pass:119 dwarn:7 dfail:0 fail:0 skip:15
hsw-brixbox total:141 pass:134 dwarn:0 dfail:0 fail:0 skip:7
hsw-gt2 total:141 pass:137 dwarn:0 dfail:0 fail:0 skip:4
ilk-hp8440p total:141 pass:100 dwarn:4 dfail:0 fail:0 skip:37
skl-i5k-2 total:141 pass:132 dwarn:1 dfail:0 fail:0 skip:8
skl-i7k-2 total:141 pass:131 dwarn:2 dfail:0 fail:0 skip:8
snb-dellxps total:141 pass:122 dwarn:5 dfail:0 fail:0 skip:14
snb-x220t total:141 pass:122 dwarn:5 dfail:0 fail:1 skip:13
Results at /archive/results/CI_IGT_test/Patchwork_1113/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* ✓ success: Fi.CI.BAT
2016-01-06 20:53 [PATCH] drm/i915/guc: Fix a memory leak where guc->execbuf_client is not freed yu.dai
@ 2016-01-07 7:49 ` Patchwork
0 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2016-01-07 7:49 UTC (permalink / raw)
To: yu.dai; +Cc: intel-gfx
== Summary ==
Built on 532a438d16e609a4b8f161c0a18b34f24001ed8f drm-intel-nightly: 2016y-01m-06d-15h-38m-17s UTC integration manifest
Test gem_storedw_loop:
Subgroup basic-vebox:
skip -> PASS (bdw-nuci7)
Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-c:
pass -> SKIP (bdw-nuci7)
bdw-nuci7 total:132 pass:1 dwarn:0 dfail:0 fail:0 skip:131
bsw-nuc-2 total:135 pass:115 dwarn:0 dfail:0 fail:0 skip:20
byt-nuc total:135 pass:121 dwarn:1 dfail:0 fail:0 skip:13
skl-i5k-2 total:135 pass:125 dwarn:2 dfail:0 fail:0 skip:8
skl-i7k-2 total:135 pass:125 dwarn:2 dfail:0 fail:0 skip:8
snb-dellxps total:135 pass:123 dwarn:0 dfail:0 fail:0 skip:12
Results at /archive/results/CI_IGT_test/Patchwork_1107/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* ✓ success: Fi.CI.BAT
2016-01-06 1:44 [PATCH] drm/i915/bxt: Don't save/restore eDP panel power during suspend Matt Roper
2016-01-06 12:20 ` ✓ success: Fi.CI.BAT Patchwork
@ 2016-01-07 7:20 ` Patchwork
1 sibling, 0 replies; 31+ messages in thread
From: Patchwork @ 2016-01-07 7:20 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
== Summary ==
Built on 532a438d16e609a4b8f161c0a18b34f24001ed8f drm-intel-nightly: 2016y-01m-06d-15h-38m-17s UTC integration manifest
Test gem_storedw_loop:
Subgroup basic-render:
dmesg-warn -> PASS (skl-i5k-2) UNSTABLE
Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-a-frame-sequence:
pass -> DMESG-WARN (byt-nuc) UNSTABLE
Subgroup read-crc-pipe-c:
pass -> SKIP (bdw-nuci7)
bdw-nuci7 total:132 pass:1 dwarn:0 dfail:0 fail:0 skip:131
bsw-nuc-2 total:135 pass:115 dwarn:0 dfail:0 fail:0 skip:20
byt-nuc total:135 pass:120 dwarn:2 dfail:0 fail:0 skip:13
skl-i5k-2 total:135 pass:126 dwarn:1 dfail:0 fail:0 skip:8
skl-i7k-2 total:135 pass:125 dwarn:2 dfail:0 fail:0 skip:8
snb-dellxps total:135 pass:123 dwarn:0 dfail:0 fail:0 skip:12
Results at /archive/results/CI_IGT_test/Patchwork_1106/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* ✓ success: Fi.CI.BAT
2016-01-06 12:08 [PATCH] drm/i915/kbl: Enable PW1 and Misc I/O power wells Michel Thierry
@ 2016-01-06 14:20 ` Patchwork
0 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2016-01-06 14:20 UTC (permalink / raw)
To: Michel Thierry; +Cc: intel-gfx
== Summary ==
Built on 142b83d5713d07d01f6a0a1993761651459c2e66 drm-intel-nightly: 2016y-01m-06d-13h-21m-32s UTC integration manifest
Test gem_storedw_loop:
Subgroup basic-render:
pass -> DMESG-WARN (skl-i7k-2) UNSTABLE
Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-a-frame-sequence:
pass -> DMESG-WARN (byt-nuc) UNSTABLE
bdw-nuci7 total:132 pass:0 dwarn:0 dfail:0 fail:0 skip:132
bsw-nuc-2 total:135 pass:115 dwarn:0 dfail:0 fail:0 skip:20
byt-nuc total:135 pass:120 dwarn:2 dfail:0 fail:0 skip:13
skl-i5k-2 total:135 pass:125 dwarn:2 dfail:0 fail:0 skip:8
skl-i7k-2 total:135 pass:125 dwarn:2 dfail:0 fail:0 skip:8
snb-dellxps total:135 pass:123 dwarn:0 dfail:0 fail:0 skip:12
Results at /archive/results/CI_IGT_test/Patchwork_1099/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* ✓ success: Fi.CI.BAT
2016-01-06 1:44 [PATCH] drm/i915/bxt: Don't save/restore eDP panel power during suspend Matt Roper
@ 2016-01-06 12:20 ` Patchwork
2016-01-07 7:20 ` Patchwork
1 sibling, 0 replies; 31+ messages in thread
From: Patchwork @ 2016-01-06 12:20 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
== Summary ==
Built on 89d0d1b6f0e9c3a6b90476bd115cfe1881646fd6 drm-intel-nightly: 2016y-01m-06d-10h-37m-17s UTC integration manifest
Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-a-frame-sequence:
pass -> DMESG-WARN (byt-nuc) UNSTABLE
bdw-nuci7 total:132 pass:0 dwarn:0 dfail:0 fail:0 skip:132
bsw-nuc-2 total:135 pass:115 dwarn:0 dfail:0 fail:0 skip:20
byt-nuc total:135 pass:121 dwarn:1 dfail:0 fail:0 skip:13
skl-i5k-2 total:135 pass:125 dwarn:2 dfail:0 fail:0 skip:8
skl-i7k-2 total:135 pass:125 dwarn:2 dfail:0 fail:0 skip:8
snb-dellxps total:135 pass:123 dwarn:0 dfail:0 fail:0 skip:12
Results at /archive/results/CI_IGT_test/Patchwork_1096/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* ✓ success: Fi.CI.BAT
2016-01-05 15:32 [PATCH] drm/i915: Update Skylake DDI translation table for HDMI Rodrigo Vivi
@ 2016-01-06 9:49 ` Patchwork
0 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2016-01-06 9:49 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Summary ==
Built on 24b053acb16b4b3b021575e4ee30ffedd3ab2920 drm-intel-nightly: 2016y-01m-06d-08h-16m-11s UTC integration manifest
Test gem_storedw_loop:
Subgroup basic-render:
dmesg-warn -> PASS (skl-i5k-2) UNSTABLE
dmesg-warn -> PASS (bdw-ultra) UNSTABLE
pass -> DMESG-WARN (skl-i7k-2) UNSTABLE
bdw-nuci7 total:132 pass:123 dwarn:0 dfail:0 fail:0 skip:9
bdw-ultra total:132 pass:126 dwarn:0 dfail:0 fail:0 skip:6
bsw-nuc-2 total:135 pass:115 dwarn:0 dfail:0 fail:0 skip:20
byt-nuc total:135 pass:121 dwarn:1 dfail:0 fail:0 skip:13
hsw-brixbox total:135 pass:128 dwarn:0 dfail:0 fail:0 skip:7
hsw-gt2 total:135 pass:131 dwarn:0 dfail:0 fail:0 skip:4
ilk-hp8440p total:135 pass:100 dwarn:0 dfail:0 fail:0 skip:35
ivb-t430s total:135 pass:129 dwarn:0 dfail:0 fail:0 skip:6
skl-i5k-2 total:135 pass:126 dwarn:1 dfail:0 fail:0 skip:8
skl-i7k-2 total:135 pass:125 dwarn:2 dfail:0 fail:0 skip:8
snb-dellxps total:135 pass:123 dwarn:0 dfail:0 fail:0 skip:12
snb-x220t total:135 pass:123 dwarn:0 dfail:0 fail:1 skip:11
Results at /archive/results/CI_IGT_test/Patchwork_1093/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* ✓ success: Fi.CI.BAT
2016-01-05 13:49 [PATCH v6 0/3] drm/i915: Disable link training optimization if DP config has changed Mika Kahola
@ 2016-01-05 14:27 ` Patchwork
0 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2016-01-05 14:27 UTC (permalink / raw)
To: Mika Kahola; +Cc: intel-gfx
== Summary ==
Built on 05ade905f2fda5416476677509e016ef830d181a drm-intel-nightly: 2016y-01m-05d-13h-00m-24s UTC integration manifest
Test gem_storedw_loop:
Subgroup basic-render:
dmesg-warn -> PASS (bdw-nuci7)
Test kms_flip:
Subgroup basic-flip-vs-modeset:
dmesg-warn -> PASS (bsw-nuc-2) UNSTABLE
Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-a:
dmesg-warn -> PASS (skl-i7k-2) UNSTABLE
Subgroup read-crc-pipe-a-frame-sequence:
pass -> DMESG-WARN (byt-nuc) UNSTABLE
Subgroup read-crc-pipe-b:
dmesg-warn -> PASS (skl-i5k-2) UNSTABLE
dmesg-warn -> PASS (snb-dellxps) UNSTABLE
Subgroup suspend-read-crc-pipe-a:
dmesg-warn -> PASS (snb-x220t) UNSTABLE
Subgroup suspend-read-crc-pipe-b:
pass -> DMESG-WARN (snb-x220t) UNSTABLE
dmesg-warn -> PASS (skl-i7k-2)
Test pm_rpm:
Subgroup basic-rte:
dmesg-warn -> PASS (byt-nuc) UNSTABLE
bdw-nuci7 total:132 pass:122 dwarn:1 dfail:0 fail:0 skip:9
bdw-ultra total:132 pass:124 dwarn:2 dfail:0 fail:0 skip:6
bsw-nuc-2 total:135 pass:114 dwarn:1 dfail:0 fail:0 skip:20
byt-nuc total:135 pass:120 dwarn:2 dfail:0 fail:0 skip:13
hsw-brixbox total:135 pass:126 dwarn:2 dfail:0 fail:0 skip:7
hsw-gt2 total:135 pass:130 dwarn:1 dfail:0 fail:0 skip:4
hsw-xps12 total:132 pass:125 dwarn:3 dfail:0 fail:0 skip:4
ilk-hp8440p total:135 pass:100 dwarn:0 dfail:0 fail:0 skip:35
ivb-t430s total:135 pass:127 dwarn:2 dfail:0 fail:0 skip:6
skl-i5k-2 total:135 pass:125 dwarn:2 dfail:0 fail:0 skip:8
skl-i7k-2 total:135 pass:125 dwarn:2 dfail:0 fail:0 skip:8
snb-dellxps total:135 pass:122 dwarn:1 dfail:0 fail:0 skip:12
snb-x220t total:135 pass:121 dwarn:2 dfail:0 fail:1 skip:11
Results at /archive/results/CI_IGT_test/Patchwork_1084/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
end of thread, other threads:[~2016-01-15 9:52 UTC | newest]
Thread overview: 31+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-01-14 2:59 [PATCH] drm/i915: Make sure DC writes are coherent on flush Francisco Jerez
2016-01-14 5:33 ` Mark Janes
2016-01-14 7:58 ` Jani Nikula
2016-01-14 10:01 ` Ville Syrjälä
2016-01-14 9:19 ` Ville Syrjälä
2016-01-14 10:32 ` Jani Nikula
2016-01-14 17:16 ` Francisco Jerez
2016-01-15 9:52 ` Jani Nikula
2016-01-14 10:49 ` ✓ success: Fi.CI.BAT Patchwork
-- strict thread matches above, loose matches on Subject: below --
2016-01-14 10:53 [PATCH] drm/i915: add onoff utility function Jani Nikula
2016-01-14 12:49 ` ✓ success: Fi.CI.BAT Patchwork
2016-01-13 17:38 [PATCH] drm/i915: Demote user facing DMC firmware load failure message Chris Wilson
2016-01-14 9:20 ` ✓ success: Fi.CI.BAT Patchwork
2016-01-13 17:04 [PATCH] drm/i915: Force ordering on request submission and hangcheck Mika Kuoppala
2016-01-14 8:20 ` ✓ success: Fi.CI.BAT Patchwork
2016-01-13 16:33 [PATCH] drm/i915: Dump power well states on unclaimed trace Mika Kuoppala
2016-01-14 7:49 ` ✓ success: Fi.CI.BAT Patchwork
2016-01-13 10:44 [PATCH] drm/i915: Expose exec parameter to force non IA-Coherent for Gen9+ Artur Harasimiuk
2016-01-13 11:49 ` ✓ success: Fi.CI.BAT Patchwork
2016-01-13 10:06 [PATCH 0/8] Gen9 HW whitelist and Preemption WA patches Arun Siluvery
2016-01-13 10:50 ` ✓ success: Fi.CI.BAT Patchwork
2016-01-12 23:40 [PATCH] drm/i915: Allow i915_gem_object_get_page() on userptr as well Chris Wilson
2016-01-13 9:20 ` ✓ success: Fi.CI.BAT Patchwork
2016-01-12 17:32 [PATCH 1/3] drm/i915: Extract vfunc setup from logical ring initializers Tvrtko Ursulin
2016-01-13 8:11 ` ✓ success: Fi.CI.BAT Patchwork
2016-01-12 15:28 [PATCH] drm/i915: Only complain about n_edp_entries with eDP ports ville.syrjala
2016-01-12 16:49 ` ✓ success: Fi.CI.BAT Patchwork
2016-01-12 15:00 [PATCH 0/3] LPSS PWM support for devices that support it Shobhit Kumar
2016-01-12 15:20 ` ✓ success: Fi.CI.BAT Patchwork
2016-01-11 19:54 [PATCH v2 0/6] drm/i915: start hiding away vbt structure from the driver Jani Nikula
2016-01-12 8:20 ` ✓ success: Fi.CI.BAT Patchwork
2016-01-11 11:39 [PATCH] drm/i915/gen9: Set PIN_ZONE_4G end to 4GB - 1 page Michel Thierry
2016-01-11 11:53 ` ✓ success: Fi.CI.BAT Patchwork
2016-01-12 16:50 ` Daniel Vetter
2016-01-09 11:30 [PATCH] drm/i915: Support to enable TRTT on GEN9 akash.goel
2016-01-11 11:19 ` ✓ success: Fi.CI.BAT Patchwork
2016-01-07 16:36 [PATCH 0/6] Misc cleanups Tvrtko Ursulin
2016-01-11 9:27 ` ✓ success: Fi.CI.BAT Patchwork
2016-01-06 20:53 [PATCH] drm/i915/guc: Fix a memory leak where guc->execbuf_client is not freed yu.dai
2016-01-07 7:49 ` ✓ success: Fi.CI.BAT Patchwork
2016-01-06 12:08 [PATCH] drm/i915/kbl: Enable PW1 and Misc I/O power wells Michel Thierry
2016-01-06 14:20 ` ✓ success: Fi.CI.BAT Patchwork
2016-01-06 1:44 [PATCH] drm/i915/bxt: Don't save/restore eDP panel power during suspend Matt Roper
2016-01-06 12:20 ` ✓ success: Fi.CI.BAT Patchwork
2016-01-07 7:20 ` Patchwork
2016-01-05 15:32 [PATCH] drm/i915: Update Skylake DDI translation table for HDMI Rodrigo Vivi
2016-01-06 9:49 ` ✓ success: Fi.CI.BAT Patchwork
2016-01-05 13:49 [PATCH v6 0/3] drm/i915: Disable link training optimization if DP config has changed Mika Kahola
2016-01-05 14:27 ` ✓ success: Fi.CI.BAT Patchwork
2015-12-21 11:57 [PATCH] drm/i915: Handle PipeC fused off on HSW Gabriel Feceoru
2016-01-13 15:41 ` ✓ success: Fi.CI.BAT Patchwork
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