* Re: [PATCH] drm/i915: Make sure DC writes are coherent on flush.
2016-01-14 2:59 [PATCH] drm/i915: Make sure DC writes are coherent on flush Francisco Jerez
@ 2016-01-14 5:33 ` Mark Janes
2016-01-14 7:58 ` Jani Nikula
` (3 subsequent siblings)
4 siblings, 0 replies; 9+ messages in thread
From: Mark Janes @ 2016-01-14 5:33 UTC (permalink / raw)
To: Francisco Jerez, intel-gfx; +Cc: Rodrigo Vivi
Tested-by: Mark Janes <mark.a.janes@intel.com>
Francisco Jerez <currojerez@riseup.net> writes:
> We need to set the DC FLUSH PIPE_CONTROL bit on Gen7+ to guarantee
> that writes performed via the HDC are visible in memory. Fixes an
> intermittent failure in a Piglit test that writes to a BO from a
> shader using GL atomic counters (implemented as HDC untyped atomics)
> and then expects the memory to read back the same value after mapping
> it on the CPU.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91298
> Tested-by: Mark Janes <mark.a.janes@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/intel_lrc.c | 1 +
> drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++
> 2 files changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index ab344e0..02213c6 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1735,6 +1735,7 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
> if (flush_domains) {
> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
> flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
> + flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
> flags |= PIPE_CONTROL_FLUSH_ENABLE;
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 4060acf..8cd8aab 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -331,6 +331,7 @@ gen7_render_ring_flush(struct drm_i915_gem_request *req,
> if (flush_domains) {
> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
> flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
> + flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
> flags |= PIPE_CONTROL_FLUSH_ENABLE;
> }
> if (invalidate_domains) {
> @@ -403,6 +404,7 @@ gen8_render_ring_flush(struct drm_i915_gem_request *req,
> if (flush_domains) {
> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
> flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
> + flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
> flags |= PIPE_CONTROL_FLUSH_ENABLE;
> }
> if (invalidate_domains) {
> --
> 2.7.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH] drm/i915: Make sure DC writes are coherent on flush.
2016-01-14 2:59 [PATCH] drm/i915: Make sure DC writes are coherent on flush Francisco Jerez
2016-01-14 5:33 ` Mark Janes
@ 2016-01-14 7:58 ` Jani Nikula
2016-01-14 10:01 ` Ville Syrjälä
2016-01-14 9:19 ` Ville Syrjälä
` (2 subsequent siblings)
4 siblings, 1 reply; 9+ messages in thread
From: Jani Nikula @ 2016-01-14 7:58 UTC (permalink / raw)
To: Francisco Jerez, intel-gfx; +Cc: Rodrigo Vivi
On Thu, 14 Jan 2016, Francisco Jerez <currojerez@riseup.net> wrote:
> We need to set the DC FLUSH PIPE_CONTROL bit on Gen7+ to guarantee
> that writes performed via the HDC are visible in memory. Fixes an
> intermittent failure in a Piglit test that writes to a BO from a
> shader using GL atomic counters (implemented as HDC untyped atomics)
> and then expects the memory to read back the same value after mapping
> it on the CPU.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91298
> Tested-by: Mark Janes <mark.a.janes@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Should this be backported to stable kernels? Is this a regression, or
has it always been broken?
BR,
Jani.
> ---
> drivers/gpu/drm/i915/intel_lrc.c | 1 +
> drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++
> 2 files changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index ab344e0..02213c6 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1735,6 +1735,7 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
> if (flush_domains) {
> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
> flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
> + flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
> flags |= PIPE_CONTROL_FLUSH_ENABLE;
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 4060acf..8cd8aab 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -331,6 +331,7 @@ gen7_render_ring_flush(struct drm_i915_gem_request *req,
> if (flush_domains) {
> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
> flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
> + flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
> flags |= PIPE_CONTROL_FLUSH_ENABLE;
> }
> if (invalidate_domains) {
> @@ -403,6 +404,7 @@ gen8_render_ring_flush(struct drm_i915_gem_request *req,
> if (flush_domains) {
> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
> flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
> + flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
> flags |= PIPE_CONTROL_FLUSH_ENABLE;
> }
> if (invalidate_domains) {
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH] drm/i915: Make sure DC writes are coherent on flush.
2016-01-14 7:58 ` Jani Nikula
@ 2016-01-14 10:01 ` Ville Syrjälä
0 siblings, 0 replies; 9+ messages in thread
From: Ville Syrjälä @ 2016-01-14 10:01 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, Rodrigo Vivi
On Thu, Jan 14, 2016 at 09:58:00AM +0200, Jani Nikula wrote:
> On Thu, 14 Jan 2016, Francisco Jerez <currojerez@riseup.net> wrote:
> > We need to set the DC FLUSH PIPE_CONTROL bit on Gen7+ to guarantee
> > that writes performed via the HDC are visible in memory. Fixes an
> > intermittent failure in a Piglit test that writes to a BO from a
> > shader using GL atomic counters (implemented as HDC untyped atomics)
> > and then expects the memory to read back the same value after mapping
> > it on the CPU.
> >
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91298
> > Tested-by: Mark Janes <mark.a.janes@intel.com>
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> Should this be backported to stable kernels? Is this a regression, or
> has it always been broken?
It was always missing, but since Mesa wasn't dirtying the DC it didn't
matter.
I'd say put cc:stable on it. I can't see much risk of regressions from
this, and it would allow using a modern Mesa with stable kernels without
hitting these problems.
>
> BR,
> Jani.
>
>
> > ---
> > drivers/gpu/drm/i915/intel_lrc.c | 1 +
> > drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++
> > 2 files changed, 3 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> > index ab344e0..02213c6 100644
> > --- a/drivers/gpu/drm/i915/intel_lrc.c
> > +++ b/drivers/gpu/drm/i915/intel_lrc.c
> > @@ -1735,6 +1735,7 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
> > if (flush_domains) {
> > flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
> > flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
> > + flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
> > flags |= PIPE_CONTROL_FLUSH_ENABLE;
> > }
> >
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > index 4060acf..8cd8aab 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > @@ -331,6 +331,7 @@ gen7_render_ring_flush(struct drm_i915_gem_request *req,
> > if (flush_domains) {
> > flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
> > flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
> > + flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
> > flags |= PIPE_CONTROL_FLUSH_ENABLE;
> > }
> > if (invalidate_domains) {
> > @@ -403,6 +404,7 @@ gen8_render_ring_flush(struct drm_i915_gem_request *req,
> > if (flush_domains) {
> > flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
> > flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
> > + flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
> > flags |= PIPE_CONTROL_FLUSH_ENABLE;
> > }
> > if (invalidate_domains) {
>
> --
> Jani Nikula, Intel Open Source Technology Center
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915: Make sure DC writes are coherent on flush.
2016-01-14 2:59 [PATCH] drm/i915: Make sure DC writes are coherent on flush Francisco Jerez
2016-01-14 5:33 ` Mark Janes
2016-01-14 7:58 ` Jani Nikula
@ 2016-01-14 9:19 ` Ville Syrjälä
2016-01-14 10:32 ` Jani Nikula
2016-01-14 10:49 ` ✓ success: Fi.CI.BAT Patchwork
4 siblings, 0 replies; 9+ messages in thread
From: Ville Syrjälä @ 2016-01-14 9:19 UTC (permalink / raw)
To: Francisco Jerez; +Cc: intel-gfx, Rodrigo Vivi
On Wed, Jan 13, 2016 at 06:59:39PM -0800, Francisco Jerez wrote:
> We need to set the DC FLUSH PIPE_CONTROL bit on Gen7+ to guarantee
> that writes performed via the HDC are visible in memory. Fixes an
> intermittent failure in a Piglit test that writes to a BO from a
> shader using GL atomic counters (implemented as HDC untyped atomics)
> and then expects the memory to read back the same value after mapping
> it on the CPU.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91298
> Tested-by: Mark Janes <mark.a.janes@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_lrc.c | 1 +
> drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++
> 2 files changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index ab344e0..02213c6 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1735,6 +1735,7 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
> if (flush_domains) {
> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
> flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
> + flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
> flags |= PIPE_CONTROL_FLUSH_ENABLE;
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 4060acf..8cd8aab 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -331,6 +331,7 @@ gen7_render_ring_flush(struct drm_i915_gem_request *req,
> if (flush_domains) {
> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
> flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
> + flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
> flags |= PIPE_CONTROL_FLUSH_ENABLE;
> }
> if (invalidate_domains) {
> @@ -403,6 +404,7 @@ gen8_render_ring_flush(struct drm_i915_gem_request *req,
> if (flush_domains) {
> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
> flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
> + flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
> flags |= PIPE_CONTROL_FLUSH_ENABLE;
> }
> if (invalidate_domains) {
> --
> 2.7.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH] drm/i915: Make sure DC writes are coherent on flush.
2016-01-14 2:59 [PATCH] drm/i915: Make sure DC writes are coherent on flush Francisco Jerez
` (2 preceding siblings ...)
2016-01-14 9:19 ` Ville Syrjälä
@ 2016-01-14 10:32 ` Jani Nikula
2016-01-14 17:16 ` Francisco Jerez
2016-01-14 10:49 ` ✓ success: Fi.CI.BAT Patchwork
4 siblings, 1 reply; 9+ messages in thread
From: Jani Nikula @ 2016-01-14 10:32 UTC (permalink / raw)
To: Francisco Jerez, intel-gfx; +Cc: Rodrigo Vivi
On Thu, 14 Jan 2016, Francisco Jerez <currojerez@riseup.net> wrote:
> We need to set the DC FLUSH PIPE_CONTROL bit on Gen7+ to guarantee
> that writes performed via the HDC are visible in memory. Fixes an
> intermittent failure in a Piglit test that writes to a BO from a
> shader using GL atomic counters (implemented as HDC untyped atomics)
> and then expects the memory to read back the same value after mapping
> it on the CPU.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91298
> Tested-by: Mark Janes <mark.a.janes@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Francisco, this is missing your Signed-off-by i.e. developer certificate
of origin http://developercertificate.org/ - can't push without. Please
reply with that.
BR,
Jani.
> ---
> drivers/gpu/drm/i915/intel_lrc.c | 1 +
> drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++
> 2 files changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index ab344e0..02213c6 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1735,6 +1735,7 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
> if (flush_domains) {
> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
> flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
> + flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
> flags |= PIPE_CONTROL_FLUSH_ENABLE;
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 4060acf..8cd8aab 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -331,6 +331,7 @@ gen7_render_ring_flush(struct drm_i915_gem_request *req,
> if (flush_domains) {
> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
> flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
> + flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
> flags |= PIPE_CONTROL_FLUSH_ENABLE;
> }
> if (invalidate_domains) {
> @@ -403,6 +404,7 @@ gen8_render_ring_flush(struct drm_i915_gem_request *req,
> if (flush_domains) {
> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
> flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
> + flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
> flags |= PIPE_CONTROL_FLUSH_ENABLE;
> }
> if (invalidate_domains) {
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH] drm/i915: Make sure DC writes are coherent on flush.
2016-01-14 10:32 ` Jani Nikula
@ 2016-01-14 17:16 ` Francisco Jerez
2016-01-15 9:52 ` Jani Nikula
0 siblings, 1 reply; 9+ messages in thread
From: Francisco Jerez @ 2016-01-14 17:16 UTC (permalink / raw)
To: Jani Nikula, intel-gfx; +Cc: Rodrigo Vivi
[-- Attachment #1.1.1: Type: text/plain, Size: 2663 bytes --]
Jani Nikula <jani.nikula@linux.intel.com> writes:
> On Thu, 14 Jan 2016, Francisco Jerez <currojerez@riseup.net> wrote:
>> We need to set the DC FLUSH PIPE_CONTROL bit on Gen7+ to guarantee
>> that writes performed via the HDC are visible in memory. Fixes an
>> intermittent failure in a Piglit test that writes to a BO from a
>> shader using GL atomic counters (implemented as HDC untyped atomics)
>> and then expects the memory to read back the same value after mapping
>> it on the CPU.
>>
>> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91298
>> Tested-by: Mark Janes <mark.a.janes@intel.com>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> Francisco, this is missing your Signed-off-by i.e. developer certificate
> of origin http://developercertificate.org/ - can't push without. Please
> reply with that.
>
Oops, sorry for that -- And yeah it shouldn't hurt to CC stable too.
Signed-off-by: Francisco Jerez <currojerez@riseup.net>
> BR,
> Jani.
>
>
>> ---
>> drivers/gpu/drm/i915/intel_lrc.c | 1 +
>> drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++
>> 2 files changed, 3 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
>> index ab344e0..02213c6 100644
>> --- a/drivers/gpu/drm/i915/intel_lrc.c
>> +++ b/drivers/gpu/drm/i915/intel_lrc.c
>> @@ -1735,6 +1735,7 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
>> if (flush_domains) {
>> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
>> flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
>> + flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
>> flags |= PIPE_CONTROL_FLUSH_ENABLE;
>> }
>>
>> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> index 4060acf..8cd8aab 100644
>> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
>> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> @@ -331,6 +331,7 @@ gen7_render_ring_flush(struct drm_i915_gem_request *req,
>> if (flush_domains) {
>> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
>> flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
>> + flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
>> flags |= PIPE_CONTROL_FLUSH_ENABLE;
>> }
>> if (invalidate_domains) {
>> @@ -403,6 +404,7 @@ gen8_render_ring_flush(struct drm_i915_gem_request *req,
>> if (flush_domains) {
>> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
>> flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
>> + flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
>> flags |= PIPE_CONTROL_FLUSH_ENABLE;
>> }
>> if (invalidate_domains) {
>
> --
> Jani Nikula, Intel Open Source Technology Center
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 212 bytes --]
[-- Attachment #2: Type: text/plain, Size: 159 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH] drm/i915: Make sure DC writes are coherent on flush.
2016-01-14 17:16 ` Francisco Jerez
@ 2016-01-15 9:52 ` Jani Nikula
0 siblings, 0 replies; 9+ messages in thread
From: Jani Nikula @ 2016-01-15 9:52 UTC (permalink / raw)
To: Francisco Jerez, intel-gfx; +Cc: Rodrigo Vivi
On Thu, 14 Jan 2016, Francisco Jerez <currojerez@riseup.net> wrote:
> Jani Nikula <jani.nikula@linux.intel.com> writes:
>
>> On Thu, 14 Jan 2016, Francisco Jerez <currojerez@riseup.net> wrote:
>>> We need to set the DC FLUSH PIPE_CONTROL bit on Gen7+ to guarantee
>>> that writes performed via the HDC are visible in memory. Fixes an
>>> intermittent failure in a Piglit test that writes to a BO from a
>>> shader using GL atomic counters (implemented as HDC untyped atomics)
>>> and then expects the memory to read back the same value after mapping
>>> it on the CPU.
>>>
>>> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91298
>>> Tested-by: Mark Janes <mark.a.janes@intel.com>
>>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>
>> Francisco, this is missing your Signed-off-by i.e. developer certificate
>> of origin http://developercertificate.org/ - can't push without. Please
>> reply with that.
>>
> Oops, sorry for that -- And yeah it shouldn't hurt to CC stable too.
>
> Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Pushed to drm-intel-next-queued, thanks for the patch and review.
BR,
Jani.
>
>> BR,
>> Jani.
>>
>>
>>> ---
>>> drivers/gpu/drm/i915/intel_lrc.c | 1 +
>>> drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++
>>> 2 files changed, 3 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
>>> index ab344e0..02213c6 100644
>>> --- a/drivers/gpu/drm/i915/intel_lrc.c
>>> +++ b/drivers/gpu/drm/i915/intel_lrc.c
>>> @@ -1735,6 +1735,7 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
>>> if (flush_domains) {
>>> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
>>> flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
>>> + flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
>>> flags |= PIPE_CONTROL_FLUSH_ENABLE;
>>> }
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
>>> index 4060acf..8cd8aab 100644
>>> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
>>> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
>>> @@ -331,6 +331,7 @@ gen7_render_ring_flush(struct drm_i915_gem_request *req,
>>> if (flush_domains) {
>>> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
>>> flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
>>> + flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
>>> flags |= PIPE_CONTROL_FLUSH_ENABLE;
>>> }
>>> if (invalidate_domains) {
>>> @@ -403,6 +404,7 @@ gen8_render_ring_flush(struct drm_i915_gem_request *req,
>>> if (flush_domains) {
>>> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
>>> flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
>>> + flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
>>> flags |= PIPE_CONTROL_FLUSH_ENABLE;
>>> }
>>> if (invalidate_domains) {
>>
>> --
>> Jani Nikula, Intel Open Source Technology Center
--
Jani Nikula, Intel Open Source Technology Center
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* ✓ success: Fi.CI.BAT
2016-01-14 2:59 [PATCH] drm/i915: Make sure DC writes are coherent on flush Francisco Jerez
` (3 preceding siblings ...)
2016-01-14 10:32 ` Jani Nikula
@ 2016-01-14 10:49 ` Patchwork
4 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2016-01-14 10:49 UTC (permalink / raw)
To: Francisco Jerez; +Cc: intel-gfx
== Summary ==
Built on 058740f8fced6851aeda34f366f5330322cd585f drm-intel-nightly: 2016y-01m-13d-17h-07m-44s UTC integration manifest
Test gem_storedw_loop:
Subgroup basic-render:
dmesg-warn -> PASS (skl-i7k-2) UNSTABLE
Test kms_flip:
Subgroup basic-flip-vs-dpms:
dmesg-warn -> PASS (ilk-hp8440p)
bdw-nuci7 total:138 pass:128 dwarn:1 dfail:0 fail:0 skip:9
bdw-ultra total:138 pass:132 dwarn:0 dfail:0 fail:0 skip:6
bsw-nuc-2 total:141 pass:115 dwarn:2 dfail:0 fail:0 skip:24
hsw-brixbox total:141 pass:134 dwarn:0 dfail:0 fail:0 skip:7
ilk-hp8440p total:141 pass:101 dwarn:3 dfail:0 fail:0 skip:37
ivb-t430s total:135 pass:122 dwarn:3 dfail:4 fail:0 skip:6
skl-i5k-2 total:141 pass:131 dwarn:2 dfail:0 fail:0 skip:8
skl-i7k-2 total:141 pass:132 dwarn:1 dfail:0 fail:0 skip:8
snb-dellxps total:141 pass:122 dwarn:5 dfail:0 fail:0 skip:14
snb-x220t total:141 pass:122 dwarn:5 dfail:0 fail:1 skip:13
Results at /archive/results/CI_IGT_test/Patchwork_1181/
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