From: Andrew Jones <drjones@redhat.com> To: Shannon Zhao <zhaoshenglong@huawei.com> Cc: kvmarm@lists.cs.columbia.edu, marc.zyngier@arm.com, christoffer.dall@linaro.org, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, will.deacon@arm.com, wei@redhat.com, cov@codeaurora.org, shannon.zhao@linaro.org, peter.huangpeng@huawei.com, hangaohuai@huawei.com Subject: Re: [PATCH v10 13/21] KVM: ARM64: Add access handler for PMSWINC register Date: Thu, 28 Jan 2016 19:37:52 +0100 [thread overview] Message-ID: <20160128183752.GD16453@hawk.localdomain> (raw) In-Reply-To: <1453866709-20324-14-git-send-email-zhaoshenglong@huawei.com> On Wed, Jan 27, 2016 at 11:51:41AM +0800, Shannon Zhao wrote: > From: Shannon Zhao <shannon.zhao@linaro.org> > > Add access handler which emulates writing and reading PMSWINC > register and add support for creating software increment event. > > Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> > --- > arch/arm64/include/asm/pmu.h | 2 ++ > arch/arm64/kvm/sys_regs.c | 20 +++++++++++++++++++- > include/kvm/arm_pmu.h | 2 ++ > virt/kvm/arm/pmu.c | 33 +++++++++++++++++++++++++++++++++ > 4 files changed, 56 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/include/asm/pmu.h b/arch/arm64/include/asm/pmu.h > index 2588f9c..6f14a01 100644 > --- a/arch/arm64/include/asm/pmu.h > +++ b/arch/arm64/include/asm/pmu.h > @@ -60,6 +60,8 @@ > #define ARMV8_EVTYPE_MASK 0xc80003ff /* Mask for writable bits */ > #define ARMV8_EVTYPE_EVENT 0x3ff /* Mask for EVENT bits */ > > +#define ARMV8_EVTYPE_EVENT_SW_INCR 0 /* Software increment event */ > + > /* > * Event filters for PMUv3 > */ > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > index 60b24ea..f45c227 100644 > --- a/arch/arm64/kvm/sys_regs.c > +++ b/arch/arm64/kvm/sys_regs.c > @@ -676,6 +676,23 @@ static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p, > return true; > } > > +static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p, > + const struct sys_reg_desc *r) > +{ > + u64 mask; > + > + if (!kvm_arm_pmu_v3_ready(vcpu)) > + return trap_raz_wi(vcpu, p, r); > + > + if (p->is_write) { > + mask = kvm_pmu_valid_counter_mask(vcpu); > + kvm_pmu_software_increment(vcpu, p->regval & mask); > + return true; > + } > + > + return false; > +} > + > /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */ > #define DBG_BCR_BVR_WCR_WVR_EL1(n) \ > /* DBGBVRn_EL1 */ \ > @@ -886,7 +903,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { > access_pmovs, NULL, PMOVSSET_EL0 }, > /* PMSWINC_EL0 */ > { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b100), > - trap_raz_wi }, > + access_pmswinc, reset_unknown, PMSWINC_EL0 }, > /* PMSELR_EL0 */ > { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b101), > access_pmselr, reset_unknown, PMSELR_EL0 }, > @@ -1225,6 +1242,7 @@ static const struct sys_reg_desc cp15_regs[] = { > { Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmcnten }, > { Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmcnten }, > { Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmovs }, > + { Op1( 0), CRn( 9), CRm(12), Op2( 4), access_pmswinc }, > { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr }, > { Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid }, > { Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid }, > diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h > index 4f8409d..caa706e 100644 > --- a/include/kvm/arm_pmu.h > +++ b/include/kvm/arm_pmu.h > @@ -41,6 +41,7 @@ u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu); > void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u64 val); > void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u64 val); > void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u64 val); > +void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val); > void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data, > u64 select_idx); > #else > @@ -60,6 +61,7 @@ static inline u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu) > static inline void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u64 val) {} > static inline void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u64 val) {} > static inline void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u64 val) {} > +static inline void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val) {} > static inline void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, > u64 data, u64 select_idx) {} > #endif > diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c > index ee75fac..706c935 100644 > --- a/virt/kvm/arm/pmu.c > +++ b/virt/kvm/arm/pmu.c > @@ -161,6 +161,35 @@ void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u64 val) > kvm_vcpu_kick(vcpu); > } > > +/** > + * kvm_pmu_software_increment - do software increment > + * @vcpu: The vcpu pointer > + * @val: the value guest writes to PMSWINC register > + */ > +void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val) > +{ > + int i; > + u64 type, enable, reg; > + > + if (val == 0) > + return; > + > + for (i = 0; i < ARMV8_CYCLE_IDX; i++) { > + if (!(val & BIT(i))) > + continue; > + type = vcpu_sys_reg(vcpu, PMEVTYPER0_EL0 + i) > + & ARMV8_EVTYPE_EVENT; > + enable = vcpu_sys_reg(vcpu, PMCNTENSET_EL0); The PMCNTENSET_EL0 read can be moved outside the loop. > + if ((type == ARMV8_EVTYPE_EVENT_SW_INCR) && (enable & BIT(i))) { > + reg = vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + i) + 1; > + reg = lower_32_bits(reg); > + vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + i) = reg; > + if (!reg) > + kvm_pmu_overflow_set(vcpu, BIT(i)); > + } > + } > +} > + > static bool kvm_pmu_counter_is_enabled(struct kvm_vcpu *vcpu, u64 select_idx) > { > return (vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMCR_E) && > @@ -189,6 +218,10 @@ void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data, > kvm_pmu_stop_counter(vcpu, pmc); > eventsel = data & ARMV8_EVTYPE_EVENT; > > + /* Software increment event does't need to be backed by a perf event */ > + if (eventsel == ARMV8_EVTYPE_EVENT_SW_INCR) > + return; > + > memset(&attr, 0, sizeof(struct perf_event_attr)); > attr.type = PERF_TYPE_RAW; > attr.size = sizeof(attr); > -- > 2.0.4 > > > -- > To unsubscribe from this list: send the line "unsubscribe kvm" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html
WARNING: multiple messages have this Message-ID (diff)
From: drjones@redhat.com (Andrew Jones) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v10 13/21] KVM: ARM64: Add access handler for PMSWINC register Date: Thu, 28 Jan 2016 19:37:52 +0100 [thread overview] Message-ID: <20160128183752.GD16453@hawk.localdomain> (raw) In-Reply-To: <1453866709-20324-14-git-send-email-zhaoshenglong@huawei.com> On Wed, Jan 27, 2016 at 11:51:41AM +0800, Shannon Zhao wrote: > From: Shannon Zhao <shannon.zhao@linaro.org> > > Add access handler which emulates writing and reading PMSWINC > register and add support for creating software increment event. > > Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> > --- > arch/arm64/include/asm/pmu.h | 2 ++ > arch/arm64/kvm/sys_regs.c | 20 +++++++++++++++++++- > include/kvm/arm_pmu.h | 2 ++ > virt/kvm/arm/pmu.c | 33 +++++++++++++++++++++++++++++++++ > 4 files changed, 56 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/include/asm/pmu.h b/arch/arm64/include/asm/pmu.h > index 2588f9c..6f14a01 100644 > --- a/arch/arm64/include/asm/pmu.h > +++ b/arch/arm64/include/asm/pmu.h > @@ -60,6 +60,8 @@ > #define ARMV8_EVTYPE_MASK 0xc80003ff /* Mask for writable bits */ > #define ARMV8_EVTYPE_EVENT 0x3ff /* Mask for EVENT bits */ > > +#define ARMV8_EVTYPE_EVENT_SW_INCR 0 /* Software increment event */ > + > /* > * Event filters for PMUv3 > */ > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > index 60b24ea..f45c227 100644 > --- a/arch/arm64/kvm/sys_regs.c > +++ b/arch/arm64/kvm/sys_regs.c > @@ -676,6 +676,23 @@ static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p, > return true; > } > > +static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p, > + const struct sys_reg_desc *r) > +{ > + u64 mask; > + > + if (!kvm_arm_pmu_v3_ready(vcpu)) > + return trap_raz_wi(vcpu, p, r); > + > + if (p->is_write) { > + mask = kvm_pmu_valid_counter_mask(vcpu); > + kvm_pmu_software_increment(vcpu, p->regval & mask); > + return true; > + } > + > + return false; > +} > + > /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */ > #define DBG_BCR_BVR_WCR_WVR_EL1(n) \ > /* DBGBVRn_EL1 */ \ > @@ -886,7 +903,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { > access_pmovs, NULL, PMOVSSET_EL0 }, > /* PMSWINC_EL0 */ > { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b100), > - trap_raz_wi }, > + access_pmswinc, reset_unknown, PMSWINC_EL0 }, > /* PMSELR_EL0 */ > { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b101), > access_pmselr, reset_unknown, PMSELR_EL0 }, > @@ -1225,6 +1242,7 @@ static const struct sys_reg_desc cp15_regs[] = { > { Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmcnten }, > { Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmcnten }, > { Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmovs }, > + { Op1( 0), CRn( 9), CRm(12), Op2( 4), access_pmswinc }, > { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr }, > { Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid }, > { Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid }, > diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h > index 4f8409d..caa706e 100644 > --- a/include/kvm/arm_pmu.h > +++ b/include/kvm/arm_pmu.h > @@ -41,6 +41,7 @@ u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu); > void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u64 val); > void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u64 val); > void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u64 val); > +void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val); > void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data, > u64 select_idx); > #else > @@ -60,6 +61,7 @@ static inline u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu) > static inline void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u64 val) {} > static inline void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u64 val) {} > static inline void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u64 val) {} > +static inline void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val) {} > static inline void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, > u64 data, u64 select_idx) {} > #endif > diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c > index ee75fac..706c935 100644 > --- a/virt/kvm/arm/pmu.c > +++ b/virt/kvm/arm/pmu.c > @@ -161,6 +161,35 @@ void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u64 val) > kvm_vcpu_kick(vcpu); > } > > +/** > + * kvm_pmu_software_increment - do software increment > + * @vcpu: The vcpu pointer > + * @val: the value guest writes to PMSWINC register > + */ > +void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val) > +{ > + int i; > + u64 type, enable, reg; > + > + if (val == 0) > + return; > + > + for (i = 0; i < ARMV8_CYCLE_IDX; i++) { > + if (!(val & BIT(i))) > + continue; > + type = vcpu_sys_reg(vcpu, PMEVTYPER0_EL0 + i) > + & ARMV8_EVTYPE_EVENT; > + enable = vcpu_sys_reg(vcpu, PMCNTENSET_EL0); The PMCNTENSET_EL0 read can be moved outside the loop. > + if ((type == ARMV8_EVTYPE_EVENT_SW_INCR) && (enable & BIT(i))) { > + reg = vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + i) + 1; > + reg = lower_32_bits(reg); > + vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + i) = reg; > + if (!reg) > + kvm_pmu_overflow_set(vcpu, BIT(i)); > + } > + } > +} > + > static bool kvm_pmu_counter_is_enabled(struct kvm_vcpu *vcpu, u64 select_idx) > { > return (vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMCR_E) && > @@ -189,6 +218,10 @@ void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data, > kvm_pmu_stop_counter(vcpu, pmc); > eventsel = data & ARMV8_EVTYPE_EVENT; > > + /* Software increment event does't need to be backed by a perf event */ > + if (eventsel == ARMV8_EVTYPE_EVENT_SW_INCR) > + return; > + > memset(&attr, 0, sizeof(struct perf_event_attr)); > attr.type = PERF_TYPE_RAW; > attr.size = sizeof(attr); > -- > 2.0.4 > > > -- > To unsubscribe from this list: send the line "unsubscribe kvm" in > the body of a message to majordomo at vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html
next prev parent reply other threads:[~2016-01-28 18:37 UTC|newest] Thread overview: 127+ messages / expand[flat|nested] mbox.gz Atom feed top 2016-01-27 3:51 [PATCH v10 00/21] KVM: ARM64: Add guest PMU support Shannon Zhao 2016-01-27 3:51 ` Shannon Zhao 2016-01-27 3:51 ` Shannon Zhao 2016-01-27 3:51 ` [PATCH v10 01/21] ARM64: Move PMU register related defines to asm/pmu.h Shannon Zhao 2016-01-27 3:51 ` Shannon Zhao 2016-01-27 3:51 ` Shannon Zhao 2016-02-10 10:36 ` Will Deacon 2016-02-10 10:36 ` Will Deacon 2016-01-27 3:51 ` [PATCH v10 02/21] KVM: ARM64: Define PMU data structure for each vcpu Shannon Zhao 2016-01-27 3:51 ` Shannon Zhao 2016-01-27 3:51 ` Shannon Zhao 2016-01-27 3:51 ` [PATCH v10 03/21] KVM: ARM64: Add offset defines for PMU registers Shannon Zhao 2016-01-27 3:51 ` Shannon Zhao 2016-01-27 3:51 ` Shannon Zhao 2016-01-27 3:51 ` [PATCH v10 04/21] KVM: ARM64: Add access handler for PMCR register Shannon Zhao 2016-01-27 3:51 ` Shannon Zhao 2016-01-27 3:51 ` Shannon Zhao 2016-01-28 15:36 ` Andrew Jones 2016-01-28 15:36 ` Andrew Jones 2016-01-28 20:43 ` Andrew Jones 2016-01-28 20:43 ` Andrew Jones 2016-01-29 2:07 ` Shannon Zhao 2016-01-29 2:07 ` Shannon Zhao 2016-01-27 3:51 ` [PATCH v10 05/21] KVM: ARM64: Add access handler for PMSELR register Shannon Zhao 2016-01-27 3:51 ` Shannon Zhao 2016-01-27 3:51 ` Shannon Zhao 2016-01-28 20:10 ` Andrew Jones 2016-01-28 20:10 ` Andrew Jones 2016-01-27 3:51 ` [PATCH v10 06/21] KVM: ARM64: Add access handler for PMCEID0 and PMCEID1 register Shannon Zhao 2016-01-27 3:51 ` Shannon Zhao 2016-01-27 3:51 ` Shannon Zhao 2016-01-28 20:34 ` Andrew Jones 2016-01-28 20:34 ` Andrew Jones 2016-01-29 3:47 ` Shannon Zhao 2016-01-29 3:47 ` Shannon Zhao 2016-01-27 3:51 ` [PATCH v10 07/21] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function Shannon Zhao 2016-01-27 3:51 ` Shannon Zhao 2016-01-27 3:51 ` Shannon Zhao 2016-01-28 16:31 ` Andrew Jones 2016-01-28 16:31 ` Andrew Jones 2016-01-28 16:45 ` Marc Zyngier 2016-01-28 16:45 ` Marc Zyngier 2016-01-28 18:06 ` Will Deacon 2016-01-28 18:06 ` Will Deacon 2016-01-29 6:14 ` Shannon Zhao 2016-01-29 6:14 ` Shannon Zhao 2016-01-29 6:14 ` Shannon Zhao 2016-01-29 6:26 ` Shannon Zhao 2016-01-29 6:26 ` Shannon Zhao 2016-01-29 6:26 ` Shannon Zhao 2016-01-29 10:18 ` Will Deacon 2016-01-29 10:18 ` Will Deacon 2016-01-29 13:11 ` Shannon Zhao 2016-01-29 13:11 ` Shannon Zhao 2016-01-27 3:51 ` [PATCH v10 08/21] KVM: ARM64: Add access handler for event type register Shannon Zhao 2016-01-27 3:51 ` Shannon Zhao 2016-01-27 3:51 ` Shannon Zhao 2016-01-28 20:11 ` Andrew Jones 2016-01-28 20:11 ` Andrew Jones 2016-01-29 1:42 ` Shannon Zhao 2016-01-29 1:42 ` Shannon Zhao 2016-01-29 1:42 ` Shannon Zhao 2016-01-29 11:25 ` Andrew Jones 2016-01-29 11:25 ` Andrew Jones 2016-01-27 3:51 ` [PATCH v10 09/21] KVM: ARM64: Add access handler for event counter register Shannon Zhao 2016-01-27 3:51 ` Shannon Zhao 2016-01-27 3:51 ` Shannon Zhao 2016-01-27 3:51 ` [PATCH v10 10/21] KVM: ARM64: Add access handler for PMCNTENSET and PMCNTENCLR register Shannon Zhao 2016-01-27 3:51 ` Shannon Zhao 2016-01-27 3:51 ` Shannon Zhao 2016-01-28 18:08 ` Andrew Jones 2016-01-28 18:08 ` Andrew Jones 2016-01-28 18:12 ` Andrew Jones 2016-01-28 18:12 ` Andrew Jones 2016-01-27 3:51 ` [PATCH v10 11/21] KVM: ARM64: Add access handler for PMINTENSET and PMINTENCLR register Shannon Zhao 2016-01-27 3:51 ` Shannon Zhao 2016-01-27 3:51 ` Shannon Zhao 2016-01-28 18:18 ` Andrew Jones 2016-01-28 18:18 ` Andrew Jones 2016-01-27 3:51 ` [PATCH v10 12/21] KVM: ARM64: Add access handler for PMOVSSET and PMOVSCLR register Shannon Zhao 2016-01-27 3:51 ` Shannon Zhao 2016-01-27 3:51 ` Shannon Zhao 2016-01-27 3:51 ` [PATCH v10 13/21] KVM: ARM64: Add access handler for PMSWINC register Shannon Zhao 2016-01-27 3:51 ` Shannon Zhao 2016-01-27 3:51 ` Shannon Zhao 2016-01-28 18:37 ` Andrew Jones [this message] 2016-01-28 18:37 ` Andrew Jones 2016-01-27 3:51 ` [PATCH v10 14/21] KVM: ARM64: Add helper to handle PMCR register bits Shannon Zhao 2016-01-27 3:51 ` Shannon Zhao 2016-01-27 3:51 ` Shannon Zhao 2016-01-28 19:15 ` Andrew Jones 2016-01-28 19:15 ` Andrew Jones 2016-01-27 3:51 ` [PATCH v10 15/21] KVM: ARM64: Add access handler for PMUSERENR register Shannon Zhao 2016-01-27 3:51 ` Shannon Zhao 2016-01-27 3:51 ` Shannon Zhao 2016-01-28 19:58 ` Andrew Jones 2016-01-28 19:58 ` Andrew Jones 2016-01-29 7:37 ` Shannon Zhao 2016-01-29 7:37 ` Shannon Zhao 2016-01-29 11:08 ` Andrew Jones 2016-01-29 11:08 ` Andrew Jones 2016-01-29 13:17 ` Shannon Zhao 2016-01-29 13:17 ` Shannon Zhao 2016-01-27 3:51 ` [PATCH v10 16/21] KVM: ARM64: Add PMU overflow interrupt routing Shannon Zhao 2016-01-27 3:51 ` Shannon Zhao 2016-01-27 3:51 ` Shannon Zhao 2016-01-27 3:51 ` [PATCH v10 17/21] KVM: ARM64: Reset PMU state when resetting vcpu Shannon Zhao 2016-01-27 3:51 ` Shannon Zhao 2016-01-27 3:51 ` Shannon Zhao 2016-01-27 3:51 ` [PATCH v10 18/21] KVM: ARM64: Free perf event of PMU when destroying vcpu Shannon Zhao 2016-01-27 3:51 ` Shannon Zhao 2016-01-27 3:51 ` Shannon Zhao 2016-01-27 3:51 ` [PATCH v10 19/21] KVM: ARM64: Add a new feature bit for PMUv3 Shannon Zhao 2016-01-27 3:51 ` Shannon Zhao 2016-01-27 3:51 ` Shannon Zhao 2016-01-28 20:54 ` Andrew Jones 2016-01-28 20:54 ` Andrew Jones 2016-01-27 3:51 ` [PATCH v10 20/21] KVM: ARM: Introduce per-vcpu kvm device controls Shannon Zhao 2016-01-27 3:51 ` Shannon Zhao 2016-01-27 3:51 ` Shannon Zhao 2016-01-27 3:51 ` [PATCH v10 21/21] KVM: ARM64: Add a new vcpu device control group for PMUv3 Shannon Zhao 2016-01-27 3:51 ` Shannon Zhao 2016-01-27 3:51 ` Shannon Zhao 2016-01-28 21:12 ` Andrew Jones 2016-01-28 21:12 ` Andrew Jones 2016-01-28 21:30 ` [PATCH v10 00/21] KVM: ARM64: Add guest PMU support Andrew Jones 2016-01-28 21:30 ` Andrew Jones
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