[PATCH v4 0/9] ARM/arm64: dts: rcar: Enable SCIF_CLK frequency and pins

[PATCH v4 0/9] ARM/arm64: dts: rcar: Enable SCIF_CLK frequency and pins

[Geert Uytterhoeven]

	Hi Simon, Magnus,

This patch series adds support for the external crystal feeding SCIF_CLK
to (H)SCIF on the various Renesas R-Car Gen1, Gen2, and Gen3 development
boards.  This increases the range and accuracy of supported baud rates.
Support for this has been accepted in the driver in v4.5-rc1.

Changes compared to v3:
  - Change one-line summary prefix to match current arm-soc practices,
  - Tested on r8a7794/alt,
  - Rebased,

Changes compared to v2:
  - Add support for r8a7778/bockw, r8a7779/marzen, r8a7790/lager,
    r8a7791/porter, r8a7793/gose, r8a7794/alt, and r8a7794/silk,
  - Add Reviewed-by.

Testing:
  - This was tested locally on r8a7791/koelsch and r8a7795/salvator-x,
  - This was tested remotely on r8a7778/bockw, r8a7779/marzen, and
    r8a7794/alt,
  - This has been in renesas-drivers for a while, so I assume it has
    received basic testing on other boards,
  - Hints for various levels of testing:
      - Change the "dev_dbg" after "done:" in
	drivers/tty/serial/sh-sci.c to "dev_info" to print clock and bit
	rate,
      - "yes U | tr -d '\n' > /dev/ttySCx" outputs a square wave with a
        frequency of half the bit rate on TXD,
      - Modifying the frequency of SCIF_CLK causes garbage on the serial
        console, unless you compensate by changing the bit rate in
        /chosen/stdout-path,
      - If you disable the SCIF_CLK, the brg_int clock will be used. If
        you change that clock, you'll get garbage again.

Dependencies:
  - renesas-devel-20160129-v4.5-rc1,
  - series "[PATCH v4 0/7] ARM: dts: R-Car: Add SCIF fallback
    compatibility strings",
  - series "[PATCH v4 00/11] ARM: dts: shmobile: Rename the serial port
    clock to fck",
  - series "[PATCH v4 0/7] ARM: dts: r-car: Add BRG support for
    (H)SCIF".

Thanks for applying!

Geert Uytterhoeven (9):
  ARM: dts: alt: Enable SCIF_CLK frequency and pins
  ARM: dts: bockw: Enable SCIF_CLK frequency and pins
  ARM: dts: gose: Enable SCIF_CLK frequency and pins
  ARM: dts: koelsch: Enable SCIF_CLK frequency and pins
  ARM: dts: lager: Enable SCIF_CLK frequency and pins
  ARM: dts: marzen: Enable SCIF_CLK frequency and pins
  ARM: dts: porter: Enable SCIF_CLK frequency and pins
  ARM: dts: silk: Enable SCIF_CLK frequency and pins
  arm64: dts: salvator-x: Enable SCIF_CLK frequency and pins

 arch/arm/boot/dts/r8a7778-bockw.dts                | 13 +++++++++++++
 arch/arm/boot/dts/r8a7779-marzen.dts               | 13 +++++++++++++
 arch/arm/boot/dts/r8a7790-lager.dts                | 13 +++++++++++++
 arch/arm/boot/dts/r8a7791-koelsch.dts              | 13 +++++++++++++
 arch/arm/boot/dts/r8a7791-porter.dts               | 13 +++++++++++++
 arch/arm/boot/dts/r8a7793-gose.dts                 | 13 +++++++++++++
 arch/arm/boot/dts/r8a7794-alt.dts                  | 13 +++++++++++++
 arch/arm/boot/dts/r8a7794-silk.dts                 | 13 +++++++++++++
 arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 12 ++++++++++++
 9 files changed, 116 insertions(+)

-- 
1.9.1

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds

[PATCH v4 0/9] ARM/arm64: dts: rcar: Enable SCIF_CLK frequency and pins

[Geert Uytterhoeven]

	Hi Simon, Magnus,

This patch series adds support for the external crystal feeding SCIF_CLK
to (H)SCIF on the various Renesas R-Car Gen1, Gen2, and Gen3 development
boards.  This increases the range and accuracy of supported baud rates.
Support for this has been accepted in the driver in v4.5-rc1.

Changes compared to v3:
  - Change one-line summary prefix to match current arm-soc practices,
  - Tested on r8a7794/alt,
  - Rebased,

Changes compared to v2:
  - Add support for r8a7778/bockw, r8a7779/marzen, r8a7790/lager,
    r8a7791/porter, r8a7793/gose, r8a7794/alt, and r8a7794/silk,
  - Add Reviewed-by.

Testing:
  - This was tested locally on r8a7791/koelsch and r8a7795/salvator-x,
  - This was tested remotely on r8a7778/bockw, r8a7779/marzen, and
    r8a7794/alt,
  - This has been in renesas-drivers for a while, so I assume it has
    received basic testing on other boards,
  - Hints for various levels of testing:
      - Change the "dev_dbg" after "done:" in
	drivers/tty/serial/sh-sci.c to "dev_info" to print clock and bit
	rate,
      - "yes U | tr -d '\n' > /dev/ttySCx" outputs a square wave with a
        frequency of half the bit rate on TXD,
      - Modifying the frequency of SCIF_CLK causes garbage on the serial
        console, unless you compensate by changing the bit rate in
        /chosen/stdout-path,
      - If you disable the SCIF_CLK, the brg_int clock will be used. If
        you change that clock, you'll get garbage again.

Dependencies:
  - renesas-devel-20160129-v4.5-rc1,
  - series "[PATCH v4 0/7] ARM: dts: R-Car: Add SCIF fallback
    compatibility strings",
  - series "[PATCH v4 00/11] ARM: dts: shmobile: Rename the serial port
    clock to fck",
  - series "[PATCH v4 0/7] ARM: dts: r-car: Add BRG support for
    (H)SCIF".

Thanks for applying!

Geert Uytterhoeven (9):
  ARM: dts: alt: Enable SCIF_CLK frequency and pins
  ARM: dts: bockw: Enable SCIF_CLK frequency and pins
  ARM: dts: gose: Enable SCIF_CLK frequency and pins
  ARM: dts: koelsch: Enable SCIF_CLK frequency and pins
  ARM: dts: lager: Enable SCIF_CLK frequency and pins
  ARM: dts: marzen: Enable SCIF_CLK frequency and pins
  ARM: dts: porter: Enable SCIF_CLK frequency and pins
  ARM: dts: silk: Enable SCIF_CLK frequency and pins
  arm64: dts: salvator-x: Enable SCIF_CLK frequency and pins

 arch/arm/boot/dts/r8a7778-bockw.dts                | 13 +++++++++++++
 arch/arm/boot/dts/r8a7779-marzen.dts               | 13 +++++++++++++
 arch/arm/boot/dts/r8a7790-lager.dts                | 13 +++++++++++++
 arch/arm/boot/dts/r8a7791-koelsch.dts              | 13 +++++++++++++
 arch/arm/boot/dts/r8a7791-porter.dts               | 13 +++++++++++++
 arch/arm/boot/dts/r8a7793-gose.dts                 | 13 +++++++++++++
 arch/arm/boot/dts/r8a7794-alt.dts                  | 13 +++++++++++++
 arch/arm/boot/dts/r8a7794-silk.dts                 | 13 +++++++++++++
 arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 12 ++++++++++++
 9 files changed, 116 insertions(+)

-- 
1.9.1

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds

[PATCH v4 1/9] ARM: dts: alt: Enable SCIF_CLK frequency and pins

[Geert Uytterhoeven]

Add and enable the external crystal for the SCIF_CLK and its pinctrl, to
be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF.

This increases the range and accuracy of supported baud rates.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Based on schematics, tested with remote access

v4:
  - Change one-line summary prefix to match current arm-soc practices,
  - Rebased,

v3:
  - New.
---
 arch/arm/boot/dts/r8a7794-alt.dts | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts
index 773f304d1142b585..ca9bc4fff28751ea 100644
--- a/arch/arm/boot/dts/r8a7794-alt.dts
+++ b/arch/arm/boot/dts/r8a7794-alt.dts
@@ -103,6 +103,9 @@
 };
 
 &pfc {
+	pinctrl-0 = <&scif_clk_pins>;
+	pinctrl-names = "default";
+
 	du_pins: du {
 		renesas,groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_dotclkout0";
 		renesas,function = "du";
@@ -113,6 +116,11 @@
 		renesas,function = "scif2";
 	};
 
+	scif_clk_pins: scif_clk {
+		renesas,groups = "scif_clk";
+		renesas,function = "scif_clk";
+	};
+
 	ether_pins: ether {
 		renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
 		renesas,function = "eth";
@@ -205,6 +213,11 @@
 	status = "okay";
 };
 
+&scif_clk {
+	clock-frequency = <14745600>;
+	status = "okay";
+};
+
 &qspi {
 	pinctrl-0 = <&qspi_pins>;
 	pinctrl-names = "default";
-- 
1.9.1

[PATCH v4 1/9] ARM: dts: alt: Enable SCIF_CLK frequency and pins

[Geert Uytterhoeven]

Add and enable the external crystal for the SCIF_CLK and its pinctrl, to
be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF.

This increases the range and accuracy of supported baud rates.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Based on schematics, tested with remote access

v4:
  - Change one-line summary prefix to match current arm-soc practices,
  - Rebased,

v3:
  - New.
---
 arch/arm/boot/dts/r8a7794-alt.dts | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts
index 773f304d1142b585..ca9bc4fff28751ea 100644
--- a/arch/arm/boot/dts/r8a7794-alt.dts
+++ b/arch/arm/boot/dts/r8a7794-alt.dts
@@ -103,6 +103,9 @@
 };
 
 &pfc {
+	pinctrl-0 = <&scif_clk_pins>;
+	pinctrl-names = "default";
+
 	du_pins: du {
 		renesas,groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_dotclkout0";
 		renesas,function = "du";
@@ -113,6 +116,11 @@
 		renesas,function = "scif2";
 	};
 
+	scif_clk_pins: scif_clk {
+		renesas,groups = "scif_clk";
+		renesas,function = "scif_clk";
+	};
+
 	ether_pins: ether {
 		renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
 		renesas,function = "eth";
@@ -205,6 +213,11 @@
 	status = "okay";
 };
 
+&scif_clk {
+	clock-frequency = <14745600>;
+	status = "okay";
+};
+
 &qspi {
 	pinctrl-0 = <&qspi_pins>;
 	pinctrl-names = "default";
-- 
1.9.1

[PATCH v4 2/9] ARM: dts: bockw: Enable SCIF_CLK frequency and pins

[Geert Uytterhoeven]

Add and enable the external crystal for the SCIF_CLK and its pinctrl, to
be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF.

This increases the range and accuracy of supported baud rates.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Based on schematics, tested with remote access.

v4:
  - Change one-line summary prefix to match current arm-soc practices,
  - Move scif_clk next to scif0, for consistency with other boards,

v3:
  - New.
---
 arch/arm/boot/dts/r8a7778-bockw.dts | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7778-bockw.dts b/arch/arm/boot/dts/r8a7778-bockw.dts
index a52b359e2ae24a30..21e3b9dda2dabf5e 100644
--- a/arch/arm/boot/dts/r8a7778-bockw.dts
+++ b/arch/arm/boot/dts/r8a7778-bockw.dts
@@ -126,11 +126,19 @@
 };
 
 &pfc {
+	pinctrl-0 = <&scif_clk_pins>;
+	pinctrl-names = "default";
+
 	scif0_pins: serial0 {
 		renesas,groups = "scif0_data_a", "scif0_ctrl";
 		renesas,function = "scif0";
 	};
 
+	scif_clk_pins: scif_clk {
+		renesas,groups = "scif_clk";
+		renesas,function = "scif_clk";
+	};
+
 	mmc_pins: mmc {
 		renesas,groups = "mmc_data8", "mmc_ctrl";
 		renesas,function = "mmc";
@@ -217,3 +225,8 @@
 
 	status = "okay";
 };
+
+&scif_clk {
+	clock-frequency = <14745600>;
+	status = "okay";
+};
-- 
1.9.1

[PATCH v4 2/9] ARM: dts: bockw: Enable SCIF_CLK frequency and pins

[Geert Uytterhoeven]

Add and enable the external crystal for the SCIF_CLK and its pinctrl, to
be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF.

This increases the range and accuracy of supported baud rates.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Based on schematics, tested with remote access.

v4:
  - Change one-line summary prefix to match current arm-soc practices,
  - Move scif_clk next to scif0, for consistency with other boards,

v3:
  - New.
---
 arch/arm/boot/dts/r8a7778-bockw.dts | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7778-bockw.dts b/arch/arm/boot/dts/r8a7778-bockw.dts
index a52b359e2ae24a30..21e3b9dda2dabf5e 100644
--- a/arch/arm/boot/dts/r8a7778-bockw.dts
+++ b/arch/arm/boot/dts/r8a7778-bockw.dts
@@ -126,11 +126,19 @@
 };
 
 &pfc {
+	pinctrl-0 = <&scif_clk_pins>;
+	pinctrl-names = "default";
+
 	scif0_pins: serial0 {
 		renesas,groups = "scif0_data_a", "scif0_ctrl";
 		renesas,function = "scif0";
 	};
 
+	scif_clk_pins: scif_clk {
+		renesas,groups = "scif_clk";
+		renesas,function = "scif_clk";
+	};
+
 	mmc_pins: mmc {
 		renesas,groups = "mmc_data8", "mmc_ctrl";
 		renesas,function = "mmc";
@@ -217,3 +225,8 @@
 
 	status = "okay";
 };
+
+&scif_clk {
+	clock-frequency = <14745600>;
+	status = "okay";
+};
-- 
1.9.1

[PATCH v4 3/9] ARM: dts: gose: Enable SCIF_CLK frequency and pins

[Geert Uytterhoeven]

Add and enable the external crystal for the SCIF_CLK and its pinctrl, to
be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF.

This increases the range and accuracy of supported baud rates.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Untested, based on (non)differences in U-Boot sources between koelsch
and gose.

v4:
  - Change one-line summary prefix to match current arm-soc practices,

v3:
  - New.
---
 arch/arm/boot/dts/r8a7793-gose.dts | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts
index 2fa052036dbc0040..cfe142c2ba389031 100644
--- a/arch/arm/boot/dts/r8a7793-gose.dts
+++ b/arch/arm/boot/dts/r8a7793-gose.dts
@@ -236,6 +236,9 @@
 };
 
 &pfc {
+	pinctrl-0 = <&scif_clk_pins>;
+	pinctrl-names = "default";
+
 	i2c2_pins: i2c2 {
 		renesas,groups = "i2c2";
 		renesas,function = "i2c2";
@@ -256,6 +259,11 @@
 		renesas,function = "scif1";
 	};
 
+	scif_clk_pins: scif_clk {
+		renesas,groups = "scif_clk";
+		renesas,function = "scif_clk";
+	};
+
 	ether_pins: ether {
 		renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
 		renesas,function = "eth";
@@ -316,6 +324,11 @@
 	status = "okay";
 };
 
+&scif_clk {
+	clock-frequency = <14745600>;
+	status = "okay";
+};
+
 &qspi {
 	pinctrl-0 = <&qspi_pins>;
 	pinctrl-names = "default";
-- 
1.9.1

[PATCH v4 3/9] ARM: dts: gose: Enable SCIF_CLK frequency and pins

[Geert Uytterhoeven]

Add and enable the external crystal for the SCIF_CLK and its pinctrl, to
be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF.

This increases the range and accuracy of supported baud rates.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Untested, based on (non)differences in U-Boot sources between koelsch
and gose.

v4:
  - Change one-line summary prefix to match current arm-soc practices,

v3:
  - New.
---
 arch/arm/boot/dts/r8a7793-gose.dts | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts
index 2fa052036dbc0040..cfe142c2ba389031 100644
--- a/arch/arm/boot/dts/r8a7793-gose.dts
+++ b/arch/arm/boot/dts/r8a7793-gose.dts
@@ -236,6 +236,9 @@
 };
 
 &pfc {
+	pinctrl-0 = <&scif_clk_pins>;
+	pinctrl-names = "default";
+
 	i2c2_pins: i2c2 {
 		renesas,groups = "i2c2";
 		renesas,function = "i2c2";
@@ -256,6 +259,11 @@
 		renesas,function = "scif1";
 	};
 
+	scif_clk_pins: scif_clk {
+		renesas,groups = "scif_clk";
+		renesas,function = "scif_clk";
+	};
+
 	ether_pins: ether {
 		renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
 		renesas,function = "eth";
@@ -316,6 +324,11 @@
 	status = "okay";
 };
 
+&scif_clk {
+	clock-frequency = <14745600>;
+	status = "okay";
+};
+
 &qspi {
 	pinctrl-0 = <&qspi_pins>;
 	pinctrl-names = "default";
-- 
1.9.1

[PATCH v4 4/9] ARM: dts: koelsch: Enable SCIF_CLK frequency and pins

[Geert Uytterhoeven]

Add and enable the external crystal for the SCIF_CLK and its pinctrl, to
be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF.

This increases the range and accuracy of supported baud rates:
  - SCIF:
      - Supports now 50, 75, 110, 1152000, 1500000, 2000000, and
        4000000 bps,
      - Perfect match for standard 50-460800, and 9216000 bps.
      - More accurate 576000 bps.
  - HSCIF:
      - Supports now 50, 75, 110, 134, 150, and 200 bps,
      - Perfect match for standard 50-460800, and 9216000 bps.
      - More accurate 576000, 1152000, 3000000, 3500000, and 4000000
	bps.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
v4:
  - Change one-line summary prefix to match current arm-soc practices,

v3:
  - Add Reviewed-by.
---
 arch/arm/boot/dts/r8a7791-koelsch.dts | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
index 45256f3cc83560a8..0ad71b81d3a25f59 100644
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -320,6 +320,9 @@
 };
 
 &pfc {
+	pinctrl-0 = <&scif_clk_pins>;
+	pinctrl-names = "default";
+
 	i2c2_pins: i2c2 {
 		renesas,groups = "i2c2";
 		renesas,function = "i2c2";
@@ -340,6 +343,11 @@
 		renesas,function = "scif1";
 	};
 
+	scif_clk_pins: scif_clk {
+		renesas,groups = "scif_clk";
+		renesas,function = "scif_clk";
+	};
+
 	ether_pins: ether {
 		renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
 		renesas,function = "eth";
@@ -440,6 +448,11 @@
 	status = "okay";
 };
 
+&scif_clk {
+	clock-frequency = <14745600>;
+	status = "okay";
+};
+
 &sdhi0 {
 	pinctrl-0 = <&sdhi0_pins>;
 	pinctrl-names = "default";
-- 
1.9.1

[PATCH v4 4/9] ARM: dts: koelsch: Enable SCIF_CLK frequency and pins

[Geert Uytterhoeven]

Add and enable the external crystal for the SCIF_CLK and its pinctrl, to
be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF.

This increases the range and accuracy of supported baud rates:
  - SCIF:
      - Supports now 50, 75, 110, 1152000, 1500000, 2000000, and
        4000000 bps,
      - Perfect match for standard 50-460800, and 9216000 bps.
      - More accurate 576000 bps.
  - HSCIF:
      - Supports now 50, 75, 110, 134, 150, and 200 bps,
      - Perfect match for standard 50-460800, and 9216000 bps.
      - More accurate 576000, 1152000, 3000000, 3500000, and 4000000
	bps.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
v4:
  - Change one-line summary prefix to match current arm-soc practices,

v3:
  - Add Reviewed-by.
---
 arch/arm/boot/dts/r8a7791-koelsch.dts | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
index 45256f3cc83560a8..0ad71b81d3a25f59 100644
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -320,6 +320,9 @@
 };
 
 &pfc {
+	pinctrl-0 = <&scif_clk_pins>;
+	pinctrl-names = "default";
+
 	i2c2_pins: i2c2 {
 		renesas,groups = "i2c2";
 		renesas,function = "i2c2";
@@ -340,6 +343,11 @@
 		renesas,function = "scif1";
 	};
 
+	scif_clk_pins: scif_clk {
+		renesas,groups = "scif_clk";
+		renesas,function = "scif_clk";
+	};
+
 	ether_pins: ether {
 		renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
 		renesas,function = "eth";
@@ -440,6 +448,11 @@
 	status = "okay";
 };
 
+&scif_clk {
+	clock-frequency = <14745600>;
+	status = "okay";
+};
+
 &sdhi0 {
 	pinctrl-0 = <&sdhi0_pins>;
 	pinctrl-names = "default";
-- 
1.9.1

[PATCH v4 5/9] ARM: dts: lager: Enable SCIF_CLK frequency and pins

[Geert Uytterhoeven]

Add and enable the external crystal for the SCIF_CLK and its pinctrl, to
be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF.

This increases the range and accuracy of supported baud rates.

Signed-off-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
---
Untested, based on schematics.

v4:
  - Change one-line summary prefix to match current arm-soc practices,

v3:
  - New.
---
 arch/arm/boot/dts/r8a7790-lager.dts | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index 052dcee4790dd298..cdc0414f5f0716dd 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -291,6 +291,9 @@
 };
 
 &pfc {
+	pinctrl-0 = <&scif_clk_pins>;
+	pinctrl-names = "default";
+
 	du_pins: du {
 		renesas,groups = "du_rgb666", "du_sync_1", "du_clk_out_0";
 		renesas,function = "du";
@@ -301,6 +304,11 @@
 		renesas,function = "scif0";
 	};
 
+	scif_clk_pins: scif_clk {
+		renesas,groups = "scif_clk";
+		renesas,function = "scif_clk";
+	};
+
 	ether_pins: ether {
 		renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
 		renesas,function = "eth";
@@ -485,6 +493,11 @@
 	status = "okay";
 };
 
+&scif_clk {
+	clock-frequency = <14745600>;
+	status = "okay";
+};
+
 &msiof1 {
 	pinctrl-0 = <&msiof1_pins>;
 	pinctrl-names = "default";
-- 
1.9.1

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[PATCH v4 5/9] ARM: dts: lager: Enable SCIF_CLK frequency and pins

[Geert Uytterhoeven]

Add and enable the external crystal for the SCIF_CLK and its pinctrl, to
be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF.

This increases the range and accuracy of supported baud rates.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Untested, based on schematics.

v4:
  - Change one-line summary prefix to match current arm-soc practices,

v3:
  - New.
---
 arch/arm/boot/dts/r8a7790-lager.dts | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index 052dcee4790dd298..cdc0414f5f0716dd 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -291,6 +291,9 @@
 };
 
 &pfc {
+	pinctrl-0 = <&scif_clk_pins>;
+	pinctrl-names = "default";
+
 	du_pins: du {
 		renesas,groups = "du_rgb666", "du_sync_1", "du_clk_out_0";
 		renesas,function = "du";
@@ -301,6 +304,11 @@
 		renesas,function = "scif0";
 	};
 
+	scif_clk_pins: scif_clk {
+		renesas,groups = "scif_clk";
+		renesas,function = "scif_clk";
+	};
+
 	ether_pins: ether {
 		renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
 		renesas,function = "eth";
@@ -485,6 +493,11 @@
 	status = "okay";
 };
 
+&scif_clk {
+	clock-frequency = <14745600>;
+	status = "okay";
+};
+
 &msiof1 {
 	pinctrl-0 = <&msiof1_pins>;
 	pinctrl-names = "default";
-- 
1.9.1

[PATCH v4 5/9] ARM: dts: lager: Enable SCIF_CLK frequency and pins

[Geert Uytterhoeven]

Add and enable the external crystal for the SCIF_CLK and its pinctrl, to
be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF.

This increases the range and accuracy of supported baud rates.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Untested, based on schematics.

v4:
  - Change one-line summary prefix to match current arm-soc practices,

v3:
  - New.
---
 arch/arm/boot/dts/r8a7790-lager.dts | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index 052dcee4790dd298..cdc0414f5f0716dd 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -291,6 +291,9 @@
 };
 
 &pfc {
+	pinctrl-0 = <&scif_clk_pins>;
+	pinctrl-names = "default";
+
 	du_pins: du {
 		renesas,groups = "du_rgb666", "du_sync_1", "du_clk_out_0";
 		renesas,function = "du";
@@ -301,6 +304,11 @@
 		renesas,function = "scif0";
 	};
 
+	scif_clk_pins: scif_clk {
+		renesas,groups = "scif_clk";
+		renesas,function = "scif_clk";
+	};
+
 	ether_pins: ether {
 		renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
 		renesas,function = "eth";
@@ -485,6 +493,11 @@
 	status = "okay";
 };
 
+&scif_clk {
+	clock-frequency = <14745600>;
+	status = "okay";
+};
+
 &msiof1 {
 	pinctrl-0 = <&msiof1_pins>;
 	pinctrl-names = "default";
-- 
1.9.1

[PATCH v4 6/9] ARM: dts: marzen: Enable SCIF_CLK frequency and pins

[Geert Uytterhoeven]

Add and enable the external crystal for the SCIF_CLK and its pinctrl, to
be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF.

This increases the range and accuracy of supported baud rates.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Based on schematics, tested with remote access.

v4:
  - Change one-line summary prefix to match current arm-soc practices,

v3:
  - New.
---
 arch/arm/boot/dts/r8a7779-marzen.dts | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts
index fe396c8d58db7986..e111d35d02aebe19 100644
--- a/arch/arm/boot/dts/r8a7779-marzen.dts
+++ b/arch/arm/boot/dts/r8a7779-marzen.dts
@@ -165,6 +165,9 @@
 };
 
 &pfc {
+	pinctrl-0 = <&scif_clk_pins>;
+	pinctrl-names = "default";
+
 	du_pins: du {
 		du0 {
 			renesas,groups = "du0_rgb888", "du0_sync_1", "du0_clk_out_0";
@@ -176,6 +179,11 @@
 		};
 	};
 
+	scif_clk_pins: scif_clk {
+		renesas,groups = "scif_clk_b";
+		renesas,function = "scif_clk";
+	};
+
 	ethernet_pins: ethernet {
 		intc {
 			renesas,groups = "intc_irq1_b";
@@ -222,6 +230,11 @@
 	status = "okay";
 };
 
+&scif_clk {
+	clock-frequency = <14745600>;
+	status = "okay";
+};
+
 &sdhi0 {
 	pinctrl-0 = <&sdhi0_pins>;
 	pinctrl-names = "default";
-- 
1.9.1

[PATCH v4 6/9] ARM: dts: marzen: Enable SCIF_CLK frequency and pins

[Geert Uytterhoeven]

Add and enable the external crystal for the SCIF_CLK and its pinctrl, to
be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF.

This increases the range and accuracy of supported baud rates.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Based on schematics, tested with remote access.

v4:
  - Change one-line summary prefix to match current arm-soc practices,

v3:
  - New.
---
 arch/arm/boot/dts/r8a7779-marzen.dts | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts
index fe396c8d58db7986..e111d35d02aebe19 100644
--- a/arch/arm/boot/dts/r8a7779-marzen.dts
+++ b/arch/arm/boot/dts/r8a7779-marzen.dts
@@ -165,6 +165,9 @@
 };
 
 &pfc {
+	pinctrl-0 = <&scif_clk_pins>;
+	pinctrl-names = "default";
+
 	du_pins: du {
 		du0 {
 			renesas,groups = "du0_rgb888", "du0_sync_1", "du0_clk_out_0";
@@ -176,6 +179,11 @@
 		};
 	};
 
+	scif_clk_pins: scif_clk {
+		renesas,groups = "scif_clk_b";
+		renesas,function = "scif_clk";
+	};
+
 	ethernet_pins: ethernet {
 		intc {
 			renesas,groups = "intc_irq1_b";
@@ -222,6 +230,11 @@
 	status = "okay";
 };
 
+&scif_clk {
+	clock-frequency = <14745600>;
+	status = "okay";
+};
+
 &sdhi0 {
 	pinctrl-0 = <&sdhi0_pins>;
 	pinctrl-names = "default";
-- 
1.9.1

[PATCH v4 7/9] ARM: dts: porter: Enable SCIF_CLK frequency and pins

[Geert Uytterhoeven]

Add and enable the external crystal for the SCIF_CLK and its pinctrl, to
be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF.

This increases the range and accuracy of supported baud rates.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Untested, based on hardware manual.

Note that U-Boot doesn't use SCIF_CLK on porter, like salvator-x, but
unlike all other supported R-Car Gen2 boards.

v4:
  - Change one-line summary prefix to match current arm-soc practices,

v3:
  - New.
---
 arch/arm/boot/dts/r8a7791-porter.dts | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7791-porter.dts b/arch/arm/boot/dts/r8a7791-porter.dts
index 5015eaa0ae50039e..ed1f6f884e2b2168 100644
--- a/arch/arm/boot/dts/r8a7791-porter.dts
+++ b/arch/arm/boot/dts/r8a7791-porter.dts
@@ -143,11 +143,19 @@
 };
 
 &pfc {
+	pinctrl-0 = <&scif_clk_pins>;
+	pinctrl-names = "default";
+
 	scif0_pins: serial0 {
 		renesas,groups = "scif0_data_d";
 		renesas,function = "scif0";
 	};
 
+	scif_clk_pins: scif_clk {
+		renesas,groups = "scif_clk";
+		renesas,function = "scif_clk";
+	};
+
 	ether_pins: ether {
 		renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
 		renesas,function = "eth";
@@ -221,6 +229,11 @@
 	status = "okay";
 };
 
+&scif_clk {
+	clock-frequency = <14745600>;
+	status = "okay";
+};
+
 &ether {
 	pinctrl-0 = <&ether_pins &phy1_pins>;
 	pinctrl-names = "default";
-- 
1.9.1

[PATCH v4 7/9] ARM: dts: porter: Enable SCIF_CLK frequency and pins

[Geert Uytterhoeven]

Add and enable the external crystal for the SCIF_CLK and its pinctrl, to
be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF.

This increases the range and accuracy of supported baud rates.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Untested, based on hardware manual.

Note that U-Boot doesn't use SCIF_CLK on porter, like salvator-x, but
unlike all other supported R-Car Gen2 boards.

v4:
  - Change one-line summary prefix to match current arm-soc practices,

v3:
  - New.
---
 arch/arm/boot/dts/r8a7791-porter.dts | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7791-porter.dts b/arch/arm/boot/dts/r8a7791-porter.dts
index 5015eaa0ae50039e..ed1f6f884e2b2168 100644
--- a/arch/arm/boot/dts/r8a7791-porter.dts
+++ b/arch/arm/boot/dts/r8a7791-porter.dts
@@ -143,11 +143,19 @@
 };
 
 &pfc {
+	pinctrl-0 = <&scif_clk_pins>;
+	pinctrl-names = "default";
+
 	scif0_pins: serial0 {
 		renesas,groups = "scif0_data_d";
 		renesas,function = "scif0";
 	};
 
+	scif_clk_pins: scif_clk {
+		renesas,groups = "scif_clk";
+		renesas,function = "scif_clk";
+	};
+
 	ether_pins: ether {
 		renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
 		renesas,function = "eth";
@@ -221,6 +229,11 @@
 	status = "okay";
 };
 
+&scif_clk {
+	clock-frequency = <14745600>;
+	status = "okay";
+};
+
 &ether {
 	pinctrl-0 = <&ether_pins &phy1_pins>;
 	pinctrl-names = "default";
-- 
1.9.1

[PATCH v4 8/9] ARM: dts: silk: Enable SCIF_CLK frequency and pins

[Geert Uytterhoeven]

Add and enable the external crystal for the SCIF_CLK and its pinctrl, to
be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF.

This increases the range and accuracy of supported baud rates.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Untested, based on hardware manual.

v4:
  - Change one-line summary prefix to match current arm-soc practices,

v3:
  - New.
---
 arch/arm/boot/dts/r8a7794-silk.dts | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts
index 98b8bcca84dac732..66f077a3ca41d1b0 100644
--- a/arch/arm/boot/dts/r8a7794-silk.dts
+++ b/arch/arm/boot/dts/r8a7794-silk.dts
@@ -126,11 +126,19 @@
 };
 
 &pfc {
+	pinctrl-0 = <&scif_clk_pins>;
+	pinctrl-names = "default";
+
 	scif2_pins: serial2 {
 		renesas,groups = "scif2_data";
 		renesas,function = "scif2";
 	};
 
+	scif_clk_pins: scif_clk {
+		renesas,groups = "scif_clk";
+		renesas,function = "scif_clk";
+	};
+
 	ether_pins: ether {
 		renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
 		renesas,function = "eth";
@@ -184,6 +192,11 @@
 	status = "okay";
 };
 
+&scif_clk {
+	clock-frequency = <14745600>;
+	status = "okay";
+};
+
 &ether {
 	pinctrl-0 = <&ether_pins &phy1_pins>;
 	pinctrl-names = "default";
-- 
1.9.1

[PATCH v4 8/9] ARM: dts: silk: Enable SCIF_CLK frequency and pins

[Geert Uytterhoeven]

Add and enable the external crystal for the SCIF_CLK and its pinctrl, to
be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF.

This increases the range and accuracy of supported baud rates.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Untested, based on hardware manual.

v4:
  - Change one-line summary prefix to match current arm-soc practices,

v3:
  - New.
---
 arch/arm/boot/dts/r8a7794-silk.dts | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts
index 98b8bcca84dac732..66f077a3ca41d1b0 100644
--- a/arch/arm/boot/dts/r8a7794-silk.dts
+++ b/arch/arm/boot/dts/r8a7794-silk.dts
@@ -126,11 +126,19 @@
 };
 
 &pfc {
+	pinctrl-0 = <&scif_clk_pins>;
+	pinctrl-names = "default";
+
 	scif2_pins: serial2 {
 		renesas,groups = "scif2_data";
 		renesas,function = "scif2";
 	};
 
+	scif_clk_pins: scif_clk {
+		renesas,groups = "scif_clk";
+		renesas,function = "scif_clk";
+	};
+
 	ether_pins: ether {
 		renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
 		renesas,function = "eth";
@@ -184,6 +192,11 @@
 	status = "okay";
 };
 
+&scif_clk {
+	clock-frequency = <14745600>;
+	status = "okay";
+};
+
 &ether {
 	pinctrl-0 = <&ether_pins &phy1_pins>;
 	pinctrl-names = "default";
-- 
1.9.1

[PATCH v4 9/9] arm64: dts: salvator-x: Enable SCIF_CLK frequency and pins

[Geert Uytterhoeven]

Add and enable the external crystal for the SCIF_CLK and its pinctrl, to
be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF.

This increases the range and accuracy of supported baud rates:
  - SCIF:
      - Supports now 50, 230400, 460800, 500000, and 921600 bps,
      - Perfect match for standard 50-460800, and 9216000 bps.
  - HSCIF:
      - Supports now 50, 75, and 110 bps,
      - Perfect match for standard 50-460800, and 9216000 bps.

Signed-off-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>
---
v4:
  - Change one-line summary prefix to match current arm-soc practices,

v3:
  - Add Reviewed-by.
---
 arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
index 9af1e3fdc468c76f..31ace9c1f79dc70c 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
@@ -93,6 +93,9 @@
 };
 
 &pfc {
+	pinctrl-0 = <&scif_clk_pins>;
+	pinctrl-names = "default";
+
 	scif1_pins: scif1 {
 		renesas,groups = "scif1_data_a", "scif1_ctrl";
 		renesas,function = "scif1";
@@ -101,6 +104,10 @@
 		renesas,groups = "scif2_data_a";
 		renesas,function = "scif2";
 	};
+	scif_clk_pins: scif_clk {
+		renesas,groups = "scif_clk_a";
+		renesas,function = "scif_clk";
+	};
 
 	i2c2_pins: i2c2 {
 		renesas,groups = "i2c2_a";
@@ -138,6 +145,11 @@
 	status = "okay";
 };
 
+&scif_clk {
+	clock-frequency = <14745600>;
+	status = "okay";
+};
+
 &i2c2 {
 	pinctrl-0 = <&i2c2_pins>;
 	pinctrl-names = "default";
-- 
1.9.1

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH v4 9/9] arm64: dts: salvator-x: Enable SCIF_CLK frequency and pins

[Geert Uytterhoeven]

Add and enable the external crystal for the SCIF_CLK and its pinctrl, to
be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF.

This increases the range and accuracy of supported baud rates:
  - SCIF:
      - Supports now 50, 230400, 460800, 500000, and 921600 bps,
      - Perfect match for standard 50-460800, and 9216000 bps.
  - HSCIF:
      - Supports now 50, 75, and 110 bps,
      - Perfect match for standard 50-460800, and 9216000 bps.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
v4:
  - Change one-line summary prefix to match current arm-soc practices,

v3:
  - Add Reviewed-by.
---
 arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
index 9af1e3fdc468c76f..31ace9c1f79dc70c 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
@@ -93,6 +93,9 @@
 };
 
 &pfc {
+	pinctrl-0 = <&scif_clk_pins>;
+	pinctrl-names = "default";
+
 	scif1_pins: scif1 {
 		renesas,groups = "scif1_data_a", "scif1_ctrl";
 		renesas,function = "scif1";
@@ -101,6 +104,10 @@
 		renesas,groups = "scif2_data_a";
 		renesas,function = "scif2";
 	};
+	scif_clk_pins: scif_clk {
+		renesas,groups = "scif_clk_a";
+		renesas,function = "scif_clk";
+	};
 
 	i2c2_pins: i2c2 {
 		renesas,groups = "i2c2_a";
@@ -138,6 +145,11 @@
 	status = "okay";
 };
 
+&scif_clk {
+	clock-frequency = <14745600>;
+	status = "okay";
+};
+
 &i2c2 {
 	pinctrl-0 = <&i2c2_pins>;
 	pinctrl-names = "default";
-- 
1.9.1

[PATCH v4 9/9] arm64: dts: salvator-x: Enable SCIF_CLK frequency and pins

[Geert Uytterhoeven]

Add and enable the external crystal for the SCIF_CLK and its pinctrl, to
be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF.

This increases the range and accuracy of supported baud rates:
  - SCIF:
      - Supports now 50, 230400, 460800, 500000, and 921600 bps,
      - Perfect match for standard 50-460800, and 9216000 bps.
  - HSCIF:
      - Supports now 50, 75, and 110 bps,
      - Perfect match for standard 50-460800, and 9216000 bps.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
v4:
  - Change one-line summary prefix to match current arm-soc practices,

v3:
  - Add Reviewed-by.
---
 arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
index 9af1e3fdc468c76f..31ace9c1f79dc70c 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
@@ -93,6 +93,9 @@
 };
 
 &pfc {
+	pinctrl-0 = <&scif_clk_pins>;
+	pinctrl-names = "default";
+
 	scif1_pins: scif1 {
 		renesas,groups = "scif1_data_a", "scif1_ctrl";
 		renesas,function = "scif1";
@@ -101,6 +104,10 @@
 		renesas,groups = "scif2_data_a";
 		renesas,function = "scif2";
 	};
+	scif_clk_pins: scif_clk {
+		renesas,groups = "scif_clk_a";
+		renesas,function = "scif_clk";
+	};
 
 	i2c2_pins: i2c2 {
 		renesas,groups = "i2c2_a";
@@ -138,6 +145,11 @@
 	status = "okay";
 };
 
+&scif_clk {
+	clock-frequency = <14745600>;
+	status = "okay";
+};
+
 &i2c2 {
 	pinctrl-0 = <&i2c2_pins>;
 	pinctrl-names = "default";
-- 
1.9.1

Re: [PATCH v4 0/9] ARM/arm64: dts: rcar: Enable SCIF_CLK frequency and pins

[Simon Horman]

On Fri, Jan 29, 2016 at 11:17:17AM +0100, Geert Uytterhoeven wrote:
> 	Hi Simon, Magnus,
> 
> This patch series adds support for the external crystal feeding SCIF_CLK
> to (H)SCIF on the various Renesas R-Car Gen1, Gen2, and Gen3 development
> boards.  This increases the range and accuracy of supported baud rates.
> Support for this has been accepted in the driver in v4.5-rc1.
> 
> Changes compared to v3:
>   - Change one-line summary prefix to match current arm-soc practices,
>   - Tested on r8a7794/alt,
>   - Rebased,
> 
> Changes compared to v2:
>   - Add support for r8a7778/bockw, r8a7779/marzen, r8a7790/lager,
>     r8a7791/porter, r8a7793/gose, r8a7794/alt, and r8a7794/silk,
>   - Add Reviewed-by.
> 
> Testing:
>   - This was tested locally on r8a7791/koelsch and r8a7795/salvator-x,
>   - This was tested remotely on r8a7778/bockw, r8a7779/marzen, and
>     r8a7794/alt,
>   - This has been in renesas-drivers for a while, so I assume it has
>     received basic testing on other boards,
>   - Hints for various levels of testing:
>       - Change the "dev_dbg" after "done:" in
> 	drivers/tty/serial/sh-sci.c to "dev_info" to print clock and bit
> 	rate,
>       - "yes U | tr -d '\n' > /dev/ttySCx" outputs a square wave with a
>         frequency of half the bit rate on TXD,
>       - Modifying the frequency of SCIF_CLK causes garbage on the serial
>         console, unless you compensate by changing the bit rate in
>         /chosen/stdout-path,
>       - If you disable the SCIF_CLK, the brg_int clock will be used. If
>         you change that clock, you'll get garbage again.
> 
> Dependencies:
>   - renesas-devel-20160129-v4.5-rc1,
>   - series "[PATCH v4 0/7] ARM: dts: R-Car: Add SCIF fallback
>     compatibility strings",
>   - series "[PATCH v4 00/11] ARM: dts: shmobile: Rename the serial port
>     clock to fck",
>   - series "[PATCH v4 0/7] ARM: dts: r-car: Add BRG support for
>     (H)SCIF".
> 
> Thanks for applying!

Is this safe to queue up in the light of the dependency on
renesas-devel-20160129-v4.5-rc1?

[PATCH v4 0/9] ARM/arm64: dts: rcar: Enable SCIF_CLK frequency and pins

[Simon Horman]

On Fri, Jan 29, 2016 at 11:17:17AM +0100, Geert Uytterhoeven wrote:
> 	Hi Simon, Magnus,
> 
> This patch series adds support for the external crystal feeding SCIF_CLK
> to (H)SCIF on the various Renesas R-Car Gen1, Gen2, and Gen3 development
> boards.  This increases the range and accuracy of supported baud rates.
> Support for this has been accepted in the driver in v4.5-rc1.
> 
> Changes compared to v3:
>   - Change one-line summary prefix to match current arm-soc practices,
>   - Tested on r8a7794/alt,
>   - Rebased,
> 
> Changes compared to v2:
>   - Add support for r8a7778/bockw, r8a7779/marzen, r8a7790/lager,
>     r8a7791/porter, r8a7793/gose, r8a7794/alt, and r8a7794/silk,
>   - Add Reviewed-by.
> 
> Testing:
>   - This was tested locally on r8a7791/koelsch and r8a7795/salvator-x,
>   - This was tested remotely on r8a7778/bockw, r8a7779/marzen, and
>     r8a7794/alt,
>   - This has been in renesas-drivers for a while, so I assume it has
>     received basic testing on other boards,
>   - Hints for various levels of testing:
>       - Change the "dev_dbg" after "done:" in
> 	drivers/tty/serial/sh-sci.c to "dev_info" to print clock and bit
> 	rate,
>       - "yes U | tr -d '\n' > /dev/ttySCx" outputs a square wave with a
>         frequency of half the bit rate on TXD,
>       - Modifying the frequency of SCIF_CLK causes garbage on the serial
>         console, unless you compensate by changing the bit rate in
>         /chosen/stdout-path,
>       - If you disable the SCIF_CLK, the brg_int clock will be used. If
>         you change that clock, you'll get garbage again.
> 
> Dependencies:
>   - renesas-devel-20160129-v4.5-rc1,
>   - series "[PATCH v4 0/7] ARM: dts: R-Car: Add SCIF fallback
>     compatibility strings",
>   - series "[PATCH v4 00/11] ARM: dts: shmobile: Rename the serial port
>     clock to fck",
>   - series "[PATCH v4 0/7] ARM: dts: r-car: Add BRG support for
>     (H)SCIF".
> 
> Thanks for applying!

Is this safe to queue up in the light of the dependency on
renesas-devel-20160129-v4.5-rc1?

Re: [PATCH v4 0/9] ARM/arm64: dts: rcar: Enable SCIF_CLK frequency and pins

[Simon Horman]

On Tue, Feb 02, 2016 at 11:21:33AM +0100, Simon Horman wrote:
> On Fri, Jan 29, 2016 at 11:17:17AM +0100, Geert Uytterhoeven wrote:
> > 	Hi Simon, Magnus,
> > 
> > This patch series adds support for the external crystal feeding SCIF_CLK
> > to (H)SCIF on the various Renesas R-Car Gen1, Gen2, and Gen3 development
> > boards.  This increases the range and accuracy of supported baud rates.
> > Support for this has been accepted in the driver in v4.5-rc1.
> > 
> > Changes compared to v3:
> >   - Change one-line summary prefix to match current arm-soc practices,
> >   - Tested on r8a7794/alt,
> >   - Rebased,
> > 
> > Changes compared to v2:
> >   - Add support for r8a7778/bockw, r8a7779/marzen, r8a7790/lager,
> >     r8a7791/porter, r8a7793/gose, r8a7794/alt, and r8a7794/silk,
> >   - Add Reviewed-by.
> > 
> > Testing:
> >   - This was tested locally on r8a7791/koelsch and r8a7795/salvator-x,
> >   - This was tested remotely on r8a7778/bockw, r8a7779/marzen, and
> >     r8a7794/alt,
> >   - This has been in renesas-drivers for a while, so I assume it has
> >     received basic testing on other boards,
> >   - Hints for various levels of testing:
> >       - Change the "dev_dbg" after "done:" in
> > 	drivers/tty/serial/sh-sci.c to "dev_info" to print clock and bit
> > 	rate,
> >       - "yes U | tr -d '\n' > /dev/ttySCx" outputs a square wave with a
> >         frequency of half the bit rate on TXD,
> >       - Modifying the frequency of SCIF_CLK causes garbage on the serial
> >         console, unless you compensate by changing the bit rate in
> >         /chosen/stdout-path,
> >       - If you disable the SCIF_CLK, the brg_int clock will be used. If
> >         you change that clock, you'll get garbage again.
> > 
> > Dependencies:
> >   - renesas-devel-20160129-v4.5-rc1,
> >   - series "[PATCH v4 0/7] ARM: dts: R-Car: Add SCIF fallback
> >     compatibility strings",
> >   - series "[PATCH v4 00/11] ARM: dts: shmobile: Rename the serial port
> >     clock to fck",
> >   - series "[PATCH v4 0/7] ARM: dts: r-car: Add BRG support for
> >     (H)SCIF".
> > 
> > Thanks for applying!
> 
> Is this safe to queue up in the light of the dependency on
> renesas-devel-20160129-v4.5-rc1?

Discussed elsewhere; I have queued this up.

[PATCH v4 0/9] ARM/arm64: dts: rcar: Enable SCIF_CLK frequency and pins

[Simon Horman]

On Tue, Feb 02, 2016 at 11:21:33AM +0100, Simon Horman wrote:
> On Fri, Jan 29, 2016 at 11:17:17AM +0100, Geert Uytterhoeven wrote:
> > 	Hi Simon, Magnus,
> > 
> > This patch series adds support for the external crystal feeding SCIF_CLK
> > to (H)SCIF on the various Renesas R-Car Gen1, Gen2, and Gen3 development
> > boards.  This increases the range and accuracy of supported baud rates.
> > Support for this has been accepted in the driver in v4.5-rc1.
> > 
> > Changes compared to v3:
> >   - Change one-line summary prefix to match current arm-soc practices,
> >   - Tested on r8a7794/alt,
> >   - Rebased,
> > 
> > Changes compared to v2:
> >   - Add support for r8a7778/bockw, r8a7779/marzen, r8a7790/lager,
> >     r8a7791/porter, r8a7793/gose, r8a7794/alt, and r8a7794/silk,
> >   - Add Reviewed-by.
> > 
> > Testing:
> >   - This was tested locally on r8a7791/koelsch and r8a7795/salvator-x,
> >   - This was tested remotely on r8a7778/bockw, r8a7779/marzen, and
> >     r8a7794/alt,
> >   - This has been in renesas-drivers for a while, so I assume it has
> >     received basic testing on other boards,
> >   - Hints for various levels of testing:
> >       - Change the "dev_dbg" after "done:" in
> > 	drivers/tty/serial/sh-sci.c to "dev_info" to print clock and bit
> > 	rate,
> >       - "yes U | tr -d '\n' > /dev/ttySCx" outputs a square wave with a
> >         frequency of half the bit rate on TXD,
> >       - Modifying the frequency of SCIF_CLK causes garbage on the serial
> >         console, unless you compensate by changing the bit rate in
> >         /chosen/stdout-path,
> >       - If you disable the SCIF_CLK, the brg_int clock will be used. If
> >         you change that clock, you'll get garbage again.
> > 
> > Dependencies:
> >   - renesas-devel-20160129-v4.5-rc1,
> >   - series "[PATCH v4 0/7] ARM: dts: R-Car: Add SCIF fallback
> >     compatibility strings",
> >   - series "[PATCH v4 00/11] ARM: dts: shmobile: Rename the serial port
> >     clock to fck",
> >   - series "[PATCH v4 0/7] ARM: dts: r-car: Add BRG support for
> >     (H)SCIF".
> > 
> > Thanks for applying!
> 
> Is this safe to queue up in the light of the dependency on
> renesas-devel-20160129-v4.5-rc1?

Discussed elsewhere; I have queued this up.