* [PATCH 1/5] drm/i915: Add TIMESTAMP to register whitelist
2016-03-07 7:30 [PATCH 0/5] Haswell Command Parser updates for Vulkan Jordan Justen
@ 2016-03-07 7:30 ` Jordan Justen
2016-03-08 22:06 ` Francisco Jerez
2016-03-07 7:30 ` [PATCH 2/5] drm/i915: Use an array of register tables in command parser Jordan Justen
` (4 subsequent siblings)
5 siblings, 1 reply; 14+ messages in thread
From: Jordan Justen @ 2016-03-07 7:30 UTC (permalink / raw)
To: intel-gfx; +Cc: Kenneth Graunke
This is needed for the Mesa Vulkan driver on Haswell.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Cc: Kristian Høgsberg <krh@bitplanet.net>
Cc: Kenneth Graunke <kenneth@whitecape.org>
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
index 814d894..86d7cda 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -444,6 +444,7 @@ static const struct drm_i915_reg_descriptor gen7_render_regs[] = {
REG64(CL_PRIMITIVES_COUNT),
REG64(PS_INVOCATION_COUNT),
REG64(PS_DEPTH_COUNT),
+ REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE),
REG32(OACONTROL), /* Only allowed for LRI and SRM. See below. */
REG64(MI_PREDICATE_SRC0),
REG64(MI_PREDICATE_SRC1),
--
2.7.0
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^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH 1/5] drm/i915: Add TIMESTAMP to register whitelist
2016-03-07 7:30 ` [PATCH 1/5] drm/i915: Add TIMESTAMP to register whitelist Jordan Justen
@ 2016-03-08 22:06 ` Francisco Jerez
0 siblings, 0 replies; 14+ messages in thread
From: Francisco Jerez @ 2016-03-08 22:06 UTC (permalink / raw)
To: Jordan Justen, intel-gfx; +Cc: Kenneth Graunke
[-- Attachment #1.1.1: Type: text/plain, Size: 1200 bytes --]
Jordan Justen <jordan.l.justen@intel.com> writes:
> This is needed for the Mesa Vulkan driver on Haswell.
>
> Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
> Cc: Kristian Høgsberg <krh@bitplanet.net>
> Cc: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
> ---
> drivers/gpu/drm/i915/i915_cmd_parser.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
> index 814d894..86d7cda 100644
> --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> @@ -444,6 +444,7 @@ static const struct drm_i915_reg_descriptor gen7_render_regs[] = {
> REG64(CL_PRIMITIVES_COUNT),
> REG64(PS_INVOCATION_COUNT),
> REG64(PS_DEPTH_COUNT),
> + REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE),
> REG32(OACONTROL), /* Only allowed for LRI and SRM. See below. */
> REG64(MI_PREDICATE_SRC0),
> REG64(MI_PREDICATE_SRC1),
> --
> 2.7.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 2/5] drm/i915: Use an array of register tables in command parser
2016-03-07 7:30 [PATCH 0/5] Haswell Command Parser updates for Vulkan Jordan Justen
2016-03-07 7:30 ` [PATCH 1/5] drm/i915: Add TIMESTAMP to register whitelist Jordan Justen
@ 2016-03-07 7:30 ` Jordan Justen
2016-03-16 23:33 ` Francisco Jerez
2016-03-07 7:30 ` [PATCH 3/5] drm/i915: Move Haswell registers to separate whitelist table Jordan Justen
` (3 subsequent siblings)
5 siblings, 1 reply; 14+ messages in thread
From: Jordan Justen @ 2016-03-07 7:30 UTC (permalink / raw)
To: intel-gfx
For Haswell, we will want another table of registers while retaining
the large common table of whitelisted registers shared by all gen7
devices.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 101 +++++++++++++++++++++++---------
drivers/gpu/drm/i915/intel_ringbuffer.h | 13 +---
2 files changed, 75 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
index 86d7cda..46ea40b 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -501,6 +501,32 @@ static const struct drm_i915_reg_descriptor hsw_master_regs[] = {
#undef REG64
#undef REG32
+struct drm_i915_reg_table {
+ const struct drm_i915_reg_descriptor *regs;
+ int num_regs;
+ bool master;
+};
+
+static const struct drm_i915_reg_table ivb_render_reg_tables[] = {
+ { gen7_render_regs, ARRAY_SIZE(gen7_render_regs), false },
+ { ivb_master_regs, ARRAY_SIZE(ivb_master_regs), true },
+};
+
+static const struct drm_i915_reg_table ivb_blt_reg_tables[] = {
+ { gen7_blt_regs, ARRAY_SIZE(gen7_blt_regs), false },
+ { ivb_master_regs, ARRAY_SIZE(ivb_master_regs), true },
+};
+
+static const struct drm_i915_reg_table hsw_render_reg_tables[] = {
+ { gen7_render_regs, ARRAY_SIZE(gen7_render_regs), false },
+ { hsw_master_regs, ARRAY_SIZE(hsw_master_regs), true },
+};
+
+static const struct drm_i915_reg_table hsw_blt_reg_tables[] = {
+ { gen7_blt_regs, ARRAY_SIZE(gen7_blt_regs), false },
+ { hsw_master_regs, ARRAY_SIZE(hsw_master_regs), true },
+};
+
static u32 gen7_render_get_cmd_length_mask(u32 cmd_header)
{
u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT;
@@ -614,9 +640,16 @@ static bool check_sorted(int ring_id,
static bool validate_regs_sorted(struct intel_engine_cs *ring)
{
- return check_sorted(ring->id, ring->reg_table, ring->reg_count) &&
- check_sorted(ring->id, ring->master_reg_table,
- ring->master_reg_count);
+ int i;
+ const struct drm_i915_reg_table *table;
+
+ for (i = 0; i < ring->reg_table_count; i++) {
+ table = &ring->reg_tables[i];
+ if (!check_sorted(ring->id, table->regs, table->num_regs))
+ return false;
+ }
+
+ return true;
}
struct cmd_node {
@@ -711,15 +744,12 @@ int i915_cmd_parser_init_ring(struct intel_engine_cs *ring)
cmd_table_count = ARRAY_SIZE(gen7_render_cmds);
}
- ring->reg_table = gen7_render_regs;
- ring->reg_count = ARRAY_SIZE(gen7_render_regs);
-
if (IS_HASWELL(ring->dev)) {
- ring->master_reg_table = hsw_master_regs;
- ring->master_reg_count = ARRAY_SIZE(hsw_master_regs);
+ ring->reg_tables = hsw_render_reg_tables;
+ ring->reg_table_count = ARRAY_SIZE(hsw_render_reg_tables);
} else {
- ring->master_reg_table = ivb_master_regs;
- ring->master_reg_count = ARRAY_SIZE(ivb_master_regs);
+ ring->reg_tables = ivb_render_reg_tables;
+ ring->reg_table_count = ARRAY_SIZE(ivb_render_reg_tables);
}
ring->get_cmd_length_mask = gen7_render_get_cmd_length_mask;
@@ -738,15 +768,12 @@ int i915_cmd_parser_init_ring(struct intel_engine_cs *ring)
cmd_table_count = ARRAY_SIZE(gen7_blt_cmds);
}
- ring->reg_table = gen7_blt_regs;
- ring->reg_count = ARRAY_SIZE(gen7_blt_regs);
-
if (IS_HASWELL(ring->dev)) {
- ring->master_reg_table = hsw_master_regs;
- ring->master_reg_count = ARRAY_SIZE(hsw_master_regs);
+ ring->reg_tables = hsw_blt_reg_tables;
+ ring->reg_table_count = ARRAY_SIZE(hsw_blt_reg_tables);
} else {
- ring->master_reg_table = ivb_master_regs;
- ring->master_reg_count = ARRAY_SIZE(ivb_master_regs);
+ ring->reg_tables = ivb_blt_reg_tables;
+ ring->reg_table_count = ARRAY_SIZE(ivb_blt_reg_tables);
}
ring->get_cmd_length_mask = gen7_blt_get_cmd_length_mask;
@@ -849,12 +876,31 @@ static const struct drm_i915_reg_descriptor *
find_reg(const struct drm_i915_reg_descriptor *table,
int count, u32 addr)
{
- if (table) {
- int i;
+ int i;
+
+ for (i = 0; i < count; i++) {
+ if (i915_mmio_reg_offset(table[i].addr) == addr)
+ return &table[i];
+ }
- for (i = 0; i < count; i++) {
- if (i915_mmio_reg_offset(table[i].addr) == addr)
- return &table[i];
+ return NULL;
+}
+
+static const struct drm_i915_reg_descriptor *
+find_reg_in_tables(const struct drm_i915_reg_table *tables,
+ int count, bool is_master, u32 addr)
+{
+ int i;
+ const struct drm_i915_reg_table *table;
+ const struct drm_i915_reg_descriptor *reg;
+
+ for (i = 0; i < count; i++) {
+ table = &tables[i];
+ if (!table->master || is_master) {
+ reg = find_reg(table->regs, table->num_regs,
+ addr);
+ if (reg != NULL)
+ return reg;
}
}
@@ -1005,13 +1051,10 @@ static bool check_cmd(const struct intel_engine_cs *ring,
offset += step) {
const u32 reg_addr = cmd[offset] & desc->reg.mask;
const struct drm_i915_reg_descriptor *reg =
- find_reg(ring->reg_table, ring->reg_count,
- reg_addr);
-
- if (!reg && is_master)
- reg = find_reg(ring->master_reg_table,
- ring->master_reg_count,
- reg_addr);
+ find_reg_in_tables(ring->reg_tables,
+ ring->reg_table_count,
+ is_master,
+ reg_addr);
if (!reg) {
DRM_DEBUG_DRIVER("CMD: Rejected register 0x%08X in command: 0x%08X (ring=%d)\n",
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 566b0ae..5f89261 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -125,7 +125,7 @@ struct intel_ringbuffer {
};
struct intel_context;
-struct drm_i915_reg_descriptor;
+struct drm_i915_reg_table;
/*
* we use a single page to load ctx workarounds so all of these
@@ -332,15 +332,8 @@ struct intel_engine_cs {
/*
* Table of registers allowed in commands that read/write registers.
*/
- const struct drm_i915_reg_descriptor *reg_table;
- int reg_count;
-
- /*
- * Table of registers allowed in commands that read/write registers, but
- * only from the DRM master.
- */
- const struct drm_i915_reg_descriptor *master_reg_table;
- int master_reg_count;
+ const struct drm_i915_reg_table *reg_tables;
+ int reg_table_count;
/*
* Returns the bitmask for the length field of the specified command.
--
2.7.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH 2/5] drm/i915: Use an array of register tables in command parser
2016-03-07 7:30 ` [PATCH 2/5] drm/i915: Use an array of register tables in command parser Jordan Justen
@ 2016-03-16 23:33 ` Francisco Jerez
0 siblings, 0 replies; 14+ messages in thread
From: Francisco Jerez @ 2016-03-16 23:33 UTC (permalink / raw)
To: Jordan Justen, intel-gfx
[-- Attachment #1.1.1: Type: text/plain, Size: 7157 bytes --]
Jordan Justen <jordan.l.justen@intel.com> writes:
> For Haswell, we will want another table of registers while retaining
> the large common table of whitelisted registers shared by all gen7
> devices.
>
> Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
> ---
> drivers/gpu/drm/i915/i915_cmd_parser.c | 101 +++++++++++++++++++++++---------
> drivers/gpu/drm/i915/intel_ringbuffer.h | 13 +---
> 2 files changed, 75 insertions(+), 39 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
> index 86d7cda..46ea40b 100644
> --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> @@ -501,6 +501,32 @@ static const struct drm_i915_reg_descriptor hsw_master_regs[] = {
> #undef REG64
> #undef REG32
>
> +struct drm_i915_reg_table {
> + const struct drm_i915_reg_descriptor *regs;
> + int num_regs;
> + bool master;
> +};
> +
> +static const struct drm_i915_reg_table ivb_render_reg_tables[] = {
> + { gen7_render_regs, ARRAY_SIZE(gen7_render_regs), false },
> + { ivb_master_regs, ARRAY_SIZE(ivb_master_regs), true },
> +};
> +
> +static const struct drm_i915_reg_table ivb_blt_reg_tables[] = {
> + { gen7_blt_regs, ARRAY_SIZE(gen7_blt_regs), false },
> + { ivb_master_regs, ARRAY_SIZE(ivb_master_regs), true },
> +};
> +
> +static const struct drm_i915_reg_table hsw_render_reg_tables[] = {
> + { gen7_render_regs, ARRAY_SIZE(gen7_render_regs), false },
> + { hsw_master_regs, ARRAY_SIZE(hsw_master_regs), true },
> +};
> +
> +static const struct drm_i915_reg_table hsw_blt_reg_tables[] = {
> + { gen7_blt_regs, ARRAY_SIZE(gen7_blt_regs), false },
> + { hsw_master_regs, ARRAY_SIZE(hsw_master_regs), true },
> +};
> +
> static u32 gen7_render_get_cmd_length_mask(u32 cmd_header)
> {
> u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT;
> @@ -614,9 +640,16 @@ static bool check_sorted(int ring_id,
>
> static bool validate_regs_sorted(struct intel_engine_cs *ring)
> {
> - return check_sorted(ring->id, ring->reg_table, ring->reg_count) &&
> - check_sorted(ring->id, ring->master_reg_table,
> - ring->master_reg_count);
> + int i;
> + const struct drm_i915_reg_table *table;
> +
> + for (i = 0; i < ring->reg_table_count; i++) {
> + table = &ring->reg_tables[i];
> + if (!check_sorted(ring->id, table->regs, table->num_regs))
> + return false;
> + }
> +
> + return true;
> }
>
> struct cmd_node {
> @@ -711,15 +744,12 @@ int i915_cmd_parser_init_ring(struct intel_engine_cs *ring)
> cmd_table_count = ARRAY_SIZE(gen7_render_cmds);
> }
>
> - ring->reg_table = gen7_render_regs;
> - ring->reg_count = ARRAY_SIZE(gen7_render_regs);
> -
> if (IS_HASWELL(ring->dev)) {
> - ring->master_reg_table = hsw_master_regs;
> - ring->master_reg_count = ARRAY_SIZE(hsw_master_regs);
> + ring->reg_tables = hsw_render_reg_tables;
> + ring->reg_table_count = ARRAY_SIZE(hsw_render_reg_tables);
> } else {
> - ring->master_reg_table = ivb_master_regs;
> - ring->master_reg_count = ARRAY_SIZE(ivb_master_regs);
> + ring->reg_tables = ivb_render_reg_tables;
> + ring->reg_table_count = ARRAY_SIZE(ivb_render_reg_tables);
> }
>
> ring->get_cmd_length_mask = gen7_render_get_cmd_length_mask;
> @@ -738,15 +768,12 @@ int i915_cmd_parser_init_ring(struct intel_engine_cs *ring)
> cmd_table_count = ARRAY_SIZE(gen7_blt_cmds);
> }
>
> - ring->reg_table = gen7_blt_regs;
> - ring->reg_count = ARRAY_SIZE(gen7_blt_regs);
> -
> if (IS_HASWELL(ring->dev)) {
> - ring->master_reg_table = hsw_master_regs;
> - ring->master_reg_count = ARRAY_SIZE(hsw_master_regs);
> + ring->reg_tables = hsw_blt_reg_tables;
> + ring->reg_table_count = ARRAY_SIZE(hsw_blt_reg_tables);
> } else {
> - ring->master_reg_table = ivb_master_regs;
> - ring->master_reg_count = ARRAY_SIZE(ivb_master_regs);
> + ring->reg_tables = ivb_blt_reg_tables;
> + ring->reg_table_count = ARRAY_SIZE(ivb_blt_reg_tables);
> }
>
> ring->get_cmd_length_mask = gen7_blt_get_cmd_length_mask;
> @@ -849,12 +876,31 @@ static const struct drm_i915_reg_descriptor *
> find_reg(const struct drm_i915_reg_descriptor *table,
> int count, u32 addr)
> {
> - if (table) {
> - int i;
> + int i;
> +
> + for (i = 0; i < count; i++) {
> + if (i915_mmio_reg_offset(table[i].addr) == addr)
> + return &table[i];
> + }
>
> - for (i = 0; i < count; i++) {
> - if (i915_mmio_reg_offset(table[i].addr) == addr)
> - return &table[i];
> + return NULL;
> +}
> +
> +static const struct drm_i915_reg_descriptor *
> +find_reg_in_tables(const struct drm_i915_reg_table *tables,
> + int count, bool is_master, u32 addr)
> +{
> + int i;
> + const struct drm_i915_reg_table *table;
> + const struct drm_i915_reg_descriptor *reg;
> +
> + for (i = 0; i < count; i++) {
> + table = &tables[i];
> + if (!table->master || is_master) {
> + reg = find_reg(table->regs, table->num_regs,
> + addr);
> + if (reg != NULL)
> + return reg;
> }
> }
>
> @@ -1005,13 +1051,10 @@ static bool check_cmd(const struct intel_engine_cs *ring,
> offset += step) {
> const u32 reg_addr = cmd[offset] & desc->reg.mask;
> const struct drm_i915_reg_descriptor *reg =
> - find_reg(ring->reg_table, ring->reg_count,
> - reg_addr);
> -
> - if (!reg && is_master)
> - reg = find_reg(ring->master_reg_table,
> - ring->master_reg_count,
> - reg_addr);
> + find_reg_in_tables(ring->reg_tables,
> + ring->reg_table_count,
> + is_master,
> + reg_addr);
>
> if (!reg) {
> DRM_DEBUG_DRIVER("CMD: Rejected register 0x%08X in command: 0x%08X (ring=%d)\n",
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index 566b0ae..5f89261 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -125,7 +125,7 @@ struct intel_ringbuffer {
> };
>
> struct intel_context;
> -struct drm_i915_reg_descriptor;
> +struct drm_i915_reg_table;
>
> /*
> * we use a single page to load ctx workarounds so all of these
> @@ -332,15 +332,8 @@ struct intel_engine_cs {
> /*
> * Table of registers allowed in commands that read/write registers.
> */
> - const struct drm_i915_reg_descriptor *reg_table;
> - int reg_count;
> -
> - /*
> - * Table of registers allowed in commands that read/write registers, but
> - * only from the DRM master.
> - */
> - const struct drm_i915_reg_descriptor *master_reg_table;
> - int master_reg_count;
> + const struct drm_i915_reg_table *reg_tables;
> + int reg_table_count;
>
> /*
> * Returns the bitmask for the length field of the specified command.
> --
> 2.7.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 3/5] drm/i915: Move Haswell registers to separate whitelist table
2016-03-07 7:30 [PATCH 0/5] Haswell Command Parser updates for Vulkan Jordan Justen
2016-03-07 7:30 ` [PATCH 1/5] drm/i915: Add TIMESTAMP to register whitelist Jordan Justen
2016-03-07 7:30 ` [PATCH 2/5] drm/i915: Use an array of register tables in command parser Jordan Justen
@ 2016-03-07 7:30 ` Jordan Justen
2016-03-08 22:05 ` Francisco Jerez
2016-03-07 7:30 ` [PATCH 4/5] drm/i915: Add Haswell CS GPR registers to whitelist Jordan Justen
` (2 subsequent siblings)
5 siblings, 1 reply; 14+ messages in thread
From: Jordan Justen @ 2016-03-07 7:30 UTC (permalink / raw)
To: intel-gfx
Now that we can whitelist registers only on Haswell, move HSW_SCRATCH1
and HSW_ROW_CHICKEN3 into a separate Haswell only table.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Cc: Francisco Jerez <currojerez@riseup.net>
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
index 46ea40b..ba01836 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -472,6 +472,9 @@ static const struct drm_i915_reg_descriptor gen7_render_regs[] = {
REG32(GEN7_L3SQCREG1),
REG32(GEN7_L3CNTLREG2),
REG32(GEN7_L3CNTLREG3),
+};
+
+static const struct drm_i915_reg_descriptor hsw_render_regs[] = {
REG32(HSW_SCRATCH1,
.mask = ~HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE,
.value = 0),
@@ -519,6 +522,7 @@ static const struct drm_i915_reg_table ivb_blt_reg_tables[] = {
static const struct drm_i915_reg_table hsw_render_reg_tables[] = {
{ gen7_render_regs, ARRAY_SIZE(gen7_render_regs), false },
+ { hsw_render_regs, ARRAY_SIZE(hsw_render_regs), false },
{ hsw_master_regs, ARRAY_SIZE(hsw_master_regs), true },
};
--
2.7.0
_______________________________________________
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^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH 3/5] drm/i915: Move Haswell registers to separate whitelist table
2016-03-07 7:30 ` [PATCH 3/5] drm/i915: Move Haswell registers to separate whitelist table Jordan Justen
@ 2016-03-08 22:05 ` Francisco Jerez
0 siblings, 0 replies; 14+ messages in thread
From: Francisco Jerez @ 2016-03-08 22:05 UTC (permalink / raw)
To: Jordan Justen, intel-gfx
[-- Attachment #1.1.1: Type: text/plain, Size: 1421 bytes --]
Jordan Justen <jordan.l.justen@intel.com> writes:
> Now that we can whitelist registers only on Haswell, move HSW_SCRATCH1
> and HSW_ROW_CHICKEN3 into a separate Haswell only table.
>
> Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
> Cc: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
> ---
> drivers/gpu/drm/i915/i915_cmd_parser.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
> index 46ea40b..ba01836 100644
> --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> @@ -472,6 +472,9 @@ static const struct drm_i915_reg_descriptor gen7_render_regs[] = {
> REG32(GEN7_L3SQCREG1),
> REG32(GEN7_L3CNTLREG2),
> REG32(GEN7_L3CNTLREG3),
> +};
> +
> +static const struct drm_i915_reg_descriptor hsw_render_regs[] = {
> REG32(HSW_SCRATCH1,
> .mask = ~HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE,
> .value = 0),
> @@ -519,6 +522,7 @@ static const struct drm_i915_reg_table ivb_blt_reg_tables[] = {
>
> static const struct drm_i915_reg_table hsw_render_reg_tables[] = {
> { gen7_render_regs, ARRAY_SIZE(gen7_render_regs), false },
> + { hsw_render_regs, ARRAY_SIZE(hsw_render_regs), false },
> { hsw_master_regs, ARRAY_SIZE(hsw_master_regs), true },
> };
>
> --
> 2.7.0
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^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 4/5] drm/i915: Add Haswell CS GPR registers to whitelist
2016-03-07 7:30 [PATCH 0/5] Haswell Command Parser updates for Vulkan Jordan Justen
` (2 preceding siblings ...)
2016-03-07 7:30 ` [PATCH 3/5] drm/i915: Move Haswell registers to separate whitelist table Jordan Justen
@ 2016-03-07 7:30 ` Jordan Justen
2016-03-08 22:06 ` Francisco Jerez
2016-03-07 7:30 ` [PATCH 5/5] drm/i915: Bump command parser version for new whitelisted registers Jordan Justen
2016-03-07 12:27 ` ✗ Fi.CI.BAT: failure for Haswell Command Parser updates for Vulkan Patchwork
5 siblings, 1 reply; 14+ messages in thread
From: Jordan Justen @ 2016-03-07 7:30 UTC (permalink / raw)
To: intel-gfx
This is needed for the Mesa Vulkan driver on Haswell.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 16 ++++++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 4 ++++
2 files changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
index ba01836..e1608da 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -475,6 +475,22 @@ static const struct drm_i915_reg_descriptor gen7_render_regs[] = {
};
static const struct drm_i915_reg_descriptor hsw_render_regs[] = {
+ REG64_IDX(HSW_CS_GPR, 0),
+ REG64_IDX(HSW_CS_GPR, 1),
+ REG64_IDX(HSW_CS_GPR, 2),
+ REG64_IDX(HSW_CS_GPR, 3),
+ REG64_IDX(HSW_CS_GPR, 4),
+ REG64_IDX(HSW_CS_GPR, 5),
+ REG64_IDX(HSW_CS_GPR, 6),
+ REG64_IDX(HSW_CS_GPR, 7),
+ REG64_IDX(HSW_CS_GPR, 8),
+ REG64_IDX(HSW_CS_GPR, 9),
+ REG64_IDX(HSW_CS_GPR, 10),
+ REG64_IDX(HSW_CS_GPR, 11),
+ REG64_IDX(HSW_CS_GPR, 12),
+ REG64_IDX(HSW_CS_GPR, 13),
+ REG64_IDX(HSW_CS_GPR, 14),
+ REG64_IDX(HSW_CS_GPR, 15),
REG32(HSW_SCRATCH1,
.mask = ~HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE,
.value = 0),
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f76cbf3..5ba7761 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -586,6 +586,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GEN7_GPGPU_DISPATCHDIMY _MMIO(0x2504)
#define GEN7_GPGPU_DISPATCHDIMZ _MMIO(0x2508)
+/* There are the 16 64-bit CS General Purpose Registers */
+#define HSW_CS_GPR(n) _MMIO(0x2600 + (n) * 8)
+#define HSW_CS_GPR_UDW(n) _MMIO(0x2600 + (n) * 8 + 4)
+
#define OACONTROL _MMIO(0x2360)
#define _GEN7_PIPEA_DE_LOAD_SL 0x70068
--
2.7.0
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^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH 4/5] drm/i915: Add Haswell CS GPR registers to whitelist
2016-03-07 7:30 ` [PATCH 4/5] drm/i915: Add Haswell CS GPR registers to whitelist Jordan Justen
@ 2016-03-08 22:06 ` Francisco Jerez
0 siblings, 0 replies; 14+ messages in thread
From: Francisco Jerez @ 2016-03-08 22:06 UTC (permalink / raw)
To: Jordan Justen, intel-gfx
[-- Attachment #1.1.1: Type: text/plain, Size: 2284 bytes --]
Jordan Justen <jordan.l.justen@intel.com> writes:
> This is needed for the Mesa Vulkan driver on Haswell.
>
> Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
> ---
> drivers/gpu/drm/i915/i915_cmd_parser.c | 16 ++++++++++++++++
> drivers/gpu/drm/i915/i915_reg.h | 4 ++++
> 2 files changed, 20 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
> index ba01836..e1608da 100644
> --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> @@ -475,6 +475,22 @@ static const struct drm_i915_reg_descriptor gen7_render_regs[] = {
> };
>
> static const struct drm_i915_reg_descriptor hsw_render_regs[] = {
> + REG64_IDX(HSW_CS_GPR, 0),
> + REG64_IDX(HSW_CS_GPR, 1),
> + REG64_IDX(HSW_CS_GPR, 2),
> + REG64_IDX(HSW_CS_GPR, 3),
> + REG64_IDX(HSW_CS_GPR, 4),
> + REG64_IDX(HSW_CS_GPR, 5),
> + REG64_IDX(HSW_CS_GPR, 6),
> + REG64_IDX(HSW_CS_GPR, 7),
> + REG64_IDX(HSW_CS_GPR, 8),
> + REG64_IDX(HSW_CS_GPR, 9),
> + REG64_IDX(HSW_CS_GPR, 10),
> + REG64_IDX(HSW_CS_GPR, 11),
> + REG64_IDX(HSW_CS_GPR, 12),
> + REG64_IDX(HSW_CS_GPR, 13),
> + REG64_IDX(HSW_CS_GPR, 14),
> + REG64_IDX(HSW_CS_GPR, 15),
> REG32(HSW_SCRATCH1,
> .mask = ~HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE,
> .value = 0),
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f76cbf3..5ba7761 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -586,6 +586,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define GEN7_GPGPU_DISPATCHDIMY _MMIO(0x2504)
> #define GEN7_GPGPU_DISPATCHDIMZ _MMIO(0x2508)
>
> +/* There are the 16 64-bit CS General Purpose Registers */
> +#define HSW_CS_GPR(n) _MMIO(0x2600 + (n) * 8)
> +#define HSW_CS_GPR_UDW(n) _MMIO(0x2600 + (n) * 8 + 4)
> +
> #define OACONTROL _MMIO(0x2360)
>
> #define _GEN7_PIPEA_DE_LOAD_SL 0x70068
> --
> 2.7.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 5/5] drm/i915: Bump command parser version for new whitelisted registers
2016-03-07 7:30 [PATCH 0/5] Haswell Command Parser updates for Vulkan Jordan Justen
` (3 preceding siblings ...)
2016-03-07 7:30 ` [PATCH 4/5] drm/i915: Add Haswell CS GPR registers to whitelist Jordan Justen
@ 2016-03-07 7:30 ` Jordan Justen
2016-03-08 22:07 ` Francisco Jerez
2016-03-07 12:27 ` ✗ Fi.CI.BAT: failure for Haswell Command Parser updates for Vulkan Patchwork
5 siblings, 1 reply; 14+ messages in thread
From: Jordan Justen @ 2016-03-07 7:30 UTC (permalink / raw)
To: intel-gfx
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
index e1608da..f8381be 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -1287,6 +1287,7 @@ int i915_cmd_parser_get_version(void)
* 3. Allow access to the GPGPU_THREADS_DISPATCHED register.
* 4. L3 atomic chicken bits of HSW_SCRATCH1 and HSW_ROW_CHICKEN3.
* 5. GPGPU dispatch compute indirect registers.
+ * 6. TIMESTAMP register and Haswell CS GPR registers
*/
- return 5;
+ return 6;
}
--
2.7.0
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^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH 5/5] drm/i915: Bump command parser version for new whitelisted registers
2016-03-07 7:30 ` [PATCH 5/5] drm/i915: Bump command parser version for new whitelisted registers Jordan Justen
@ 2016-03-08 22:07 ` Francisco Jerez
2016-03-21 9:03 ` Daniel Vetter
0 siblings, 1 reply; 14+ messages in thread
From: Francisco Jerez @ 2016-03-08 22:07 UTC (permalink / raw)
To: Jordan Justen, intel-gfx
[-- Attachment #1.1.1: Type: text/plain, Size: 1058 bytes --]
Jordan Justen <jordan.l.justen@intel.com> writes:
> Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
> ---
> drivers/gpu/drm/i915/i915_cmd_parser.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
> index e1608da..f8381be 100644
> --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> @@ -1287,6 +1287,7 @@ int i915_cmd_parser_get_version(void)
> * 3. Allow access to the GPGPU_THREADS_DISPATCHED register.
> * 4. L3 atomic chicken bits of HSW_SCRATCH1 and HSW_ROW_CHICKEN3.
> * 5. GPGPU dispatch compute indirect registers.
> + * 6. TIMESTAMP register and Haswell CS GPR registers
> */
> - return 5;
> + return 6;
> }
> --
> 2.7.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 5/5] drm/i915: Bump command parser version for new whitelisted registers
2016-03-08 22:07 ` Francisco Jerez
@ 2016-03-21 9:03 ` Daniel Vetter
0 siblings, 0 replies; 14+ messages in thread
From: Daniel Vetter @ 2016-03-21 9:03 UTC (permalink / raw)
To: Francisco Jerez; +Cc: intel-gfx
On Tue, Mar 08, 2016 at 02:07:03PM -0800, Francisco Jerez wrote:
> Jordan Justen <jordan.l.justen@intel.com> writes:
>
> > Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
>
> Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Entire series applied to dinq, thanks for patches&review.
-Daniel
>
> > ---
> > drivers/gpu/drm/i915/i915_cmd_parser.c | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
> > index e1608da..f8381be 100644
> > --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> > +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> > @@ -1287,6 +1287,7 @@ int i915_cmd_parser_get_version(void)
> > * 3. Allow access to the GPGPU_THREADS_DISPATCHED register.
> > * 4. L3 atomic chicken bits of HSW_SCRATCH1 and HSW_ROW_CHICKEN3.
> > * 5. GPGPU dispatch compute indirect registers.
> > + * 6. TIMESTAMP register and Haswell CS GPR registers
> > */
> > - return 5;
> > + return 6;
> > }
> > --
> > 2.7.0
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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^ permalink raw reply [flat|nested] 14+ messages in thread
* ✗ Fi.CI.BAT: failure for Haswell Command Parser updates for Vulkan
2016-03-07 7:30 [PATCH 0/5] Haswell Command Parser updates for Vulkan Jordan Justen
` (4 preceding siblings ...)
2016-03-07 7:30 ` [PATCH 5/5] drm/i915: Bump command parser version for new whitelisted registers Jordan Justen
@ 2016-03-07 12:27 ` Patchwork
2016-03-21 8:53 ` Daniel Vetter
5 siblings, 1 reply; 14+ messages in thread
From: Patchwork @ 2016-03-07 12:27 UTC (permalink / raw)
To: Jordan Justen; +Cc: intel-gfx
== Series Details ==
Series: Haswell Command Parser updates for Vulkan
URL : https://patchwork.freedesktop.org/series/4168/
State : failure
== Summary ==
Series 4168v1 Haswell Command Parser updates for Vulkan
http://patchwork.freedesktop.org/api/1.0/series/4168/revisions/1/mbox/
Test kms_flip:
Subgroup basic-flip-vs-dpms:
pass -> DMESG-WARN (ilk-hp8440p) UNSTABLE
Subgroup basic-flip-vs-wf_vblank:
pass -> FAIL (snb-x220t)
pass -> DMESG-WARN (hsw-gt2)
Subgroup basic-plain-flip:
dmesg-warn -> PASS (hsw-gt2)
pass -> DMESG-WARN (hsw-brixbox)
Test kms_pipe_crc_basic:
Subgroup nonblocking-crc-pipe-b:
pass -> DMESG-WARN (hsw-gt2)
Subgroup read-crc-pipe-a:
pass -> DMESG-WARN (snb-x220t)
Subgroup read-crc-pipe-c:
dmesg-warn -> PASS (hsw-gt2)
Subgroup suspend-read-crc-pipe-a:
dmesg-warn -> PASS (skl-i5k-2)
skip -> PASS (hsw-brixbox)
Subgroup suspend-read-crc-pipe-c:
pass -> DMESG-WARN (bsw-nuc-2)
bdw-ultra total:183 pass:165 dwarn:0 dfail:0 fail:0 skip:18
bsw-nuc-2 total:183 pass:147 dwarn:1 dfail:0 fail:1 skip:34
byt-nuc total:183 pass:152 dwarn:0 dfail:0 fail:0 skip:31
hsw-brixbox total:183 pass:163 dwarn:1 dfail:0 fail:0 skip:19
hsw-gt2 total:183 pass:167 dwarn:2 dfail:0 fail:0 skip:14
ilk-hp8440p total:183 pass:124 dwarn:1 dfail:0 fail:0 skip:58
ivb-t430s total:183 pass:162 dwarn:0 dfail:0 fail:0 skip:21
skl-i5k-2 total:183 pass:163 dwarn:0 dfail:0 fail:0 skip:20
skl-i7k-2 total:183 pass:163 dwarn:0 dfail:0 fail:0 skip:20
snb-x220t total:183 pass:152 dwarn:1 dfail:0 fail:2 skip:28
Results at /archive/results/CI_IGT_test/Patchwork_1534/
d369e0096716c6000139162b3b340f684f0a51da drm-intel-nightly: 2016y-03m-04d-17h-18m-08s UTC integration manifest
bc2a29615c1072bef5e47ed28ea9cd510fb5cf39 drm/i915: Bump command parser version for new whitelisted registers
cdc1284902a326ba23595675d5ebbcb0e7c84a3f drm/i915: Add Haswell CS GPR registers to whitelist
445b54f7d50ea9afa0e90f61e5c5af491205f484 drm/i915: Move Haswell registers to separate whitelist table
bcd2251c3f03094647ce8bd09f8470324aa38693 drm/i915: Use an array of register tables in command parser
8fcd1943a696715b792cb043d3dae5e4dc0c6f1b drm/i915: Add TIMESTAMP to register whitelist
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: ✗ Fi.CI.BAT: failure for Haswell Command Parser updates for Vulkan
2016-03-07 12:27 ` ✗ Fi.CI.BAT: failure for Haswell Command Parser updates for Vulkan Patchwork
@ 2016-03-21 8:53 ` Daniel Vetter
0 siblings, 0 replies; 14+ messages in thread
From: Daniel Vetter @ 2016-03-21 8:53 UTC (permalink / raw)
To: intel-gfx
On Mon, Mar 07, 2016 at 12:27:39PM -0000, Patchwork wrote:
> == Series Details ==
>
> Series: Haswell Command Parser updates for Vulkan
> URL : https://patchwork.freedesktop.org/series/4168/
> State : failure
>
> == Summary ==
>
> Series 4168v1 Haswell Command Parser updates for Vulkan
> http://patchwork.freedesktop.org/api/1.0/series/4168/revisions/1/mbox/
>
> Test kms_flip:
> Subgroup basic-flip-vs-dpms:
> pass -> DMESG-WARN (ilk-hp8440p) UNSTABLE
> Subgroup basic-flip-vs-wf_vblank:
> pass -> FAIL (snb-x220t)
> pass -> DMESG-WARN (hsw-gt2)
> Subgroup basic-plain-flip:
> dmesg-warn -> PASS (hsw-gt2)
> pass -> DMESG-WARN (hsw-brixbox)
> Test kms_pipe_crc_basic:
> Subgroup nonblocking-crc-pipe-b:
> pass -> DMESG-WARN (hsw-gt2)
> Subgroup read-crc-pipe-a:
> pass -> DMESG-WARN (snb-x220t)
> Subgroup read-crc-pipe-c:
> dmesg-warn -> PASS (hsw-gt2)
> Subgroup suspend-read-crc-pipe-a:
> dmesg-warn -> PASS (skl-i5k-2)
> skip -> PASS (hsw-brixbox)
> Subgroup suspend-read-crc-pipe-c:
> pass -> DMESG-WARN (bsw-nuc-2)
cpu hotplug lockdep splat, but not the one we've had on skl. Fairly
sporadic, and apparently no one file it yet. Created a new one:
https://bugs.freedesktop.org/show_bug.cgi?id=94644
All the other regressions to dmesg-warn above are runtime PM fail in the
ilk wm code:
https://bugs.freedesktop.org/show_bug.cgi?id=94645
>
> bdw-ultra total:183 pass:165 dwarn:0 dfail:0 fail:0 skip:18
> bsw-nuc-2 total:183 pass:147 dwarn:1 dfail:0 fail:1 skip:34
> byt-nuc total:183 pass:152 dwarn:0 dfail:0 fail:0 skip:31
> hsw-brixbox total:183 pass:163 dwarn:1 dfail:0 fail:0 skip:19
> hsw-gt2 total:183 pass:167 dwarn:2 dfail:0 fail:0 skip:14
> ilk-hp8440p total:183 pass:124 dwarn:1 dfail:0 fail:0 skip:58
> ivb-t430s total:183 pass:162 dwarn:0 dfail:0 fail:0 skip:21
> skl-i5k-2 total:183 pass:163 dwarn:0 dfail:0 fail:0 skip:20
> skl-i7k-2 total:183 pass:163 dwarn:0 dfail:0 fail:0 skip:20
> snb-x220t total:183 pass:152 dwarn:1 dfail:0 fail:2 skip:28
>
> Results at /archive/results/CI_IGT_test/Patchwork_1534/
>
> d369e0096716c6000139162b3b340f684f0a51da drm-intel-nightly: 2016y-03m-04d-17h-18m-08s UTC integration manifest
> bc2a29615c1072bef5e47ed28ea9cd510fb5cf39 drm/i915: Bump command parser version for new whitelisted registers
> cdc1284902a326ba23595675d5ebbcb0e7c84a3f drm/i915: Add Haswell CS GPR registers to whitelist
> 445b54f7d50ea9afa0e90f61e5c5af491205f484 drm/i915: Move Haswell registers to separate whitelist table
> bcd2251c3f03094647ce8bd09f8470324aa38693 drm/i915: Use an array of register tables in command parser
> 8fcd1943a696715b792cb043d3dae5e4dc0c6f1b drm/i915: Add TIMESTAMP to register whitelist
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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