From: Marc Zyngier <marc.zyngier-5wv7dgnIgG8@public.gmane.org> To: Jon Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> Cc: "Thomas Gleixner" <tglx-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org>, "Jason Cooper" <jason-NLaQJdtUoK4Be96aLqz0jA@public.gmane.org>, "Benoît Cousson" <bcousson-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>, "Tony Lindgren" <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>, "Rob Herring" <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>, "Pawel Moll" <pawel.moll-5wv7dgnIgG8@public.gmane.org>, "Mark Rutland" <mark.rutland-5wv7dgnIgG8@public.gmane.org>, "Ian Campbell" <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>, "Kumar Gala" <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>, "Stephen Warren" <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>, "Thierry Reding" <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>, "Kevin Hilman" <khilman-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>, "Geert Uytterhoeven" <geert-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org>, "Grygorii Strashko" <grygorii.strashko-l0cyMroinI0@public.gmane.org>, "Lars-Peter Clausen" <lars-Qo5EllUWu/uELgA04lAiVw@public.gmane.org>, "Linus Walleij" <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-omap-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org Subject: Re: [PATCH 11/15] irqchip/gic: Return an error if GIC initialisation fails Date: Sat, 9 Apr 2016 12:43:33 +0100 [thread overview] Message-ID: <20160409124333.6b7f695d@arm.com> (raw) In-Reply-To: <1458224359-32665-12-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> On Thu, 17 Mar 2016 14:19:15 +0000 Jon Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote: > If the GIC initialisation fails, then currently we do not return an error > or clean-up afterwards. Although for root controllers, this failure may be > fatal anyway, for secondary controllers, it may not be fatal and so return > an error on failure and clean-up. > > For non-banked GIC controllers, make sure that we free any memory > allocated if we fail to initialise the IRQ domain. Please note that > free_percpu() only frees memory if the pointer passed to it is not NULL > and so it is unnecessary to check if both pointers are valid or not. > > Signed-off-by: Jon Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> > --- > drivers/irqchip/irq-gic.c | 57 ++++++++++++++++++++++++++++++++++------------- > 1 file changed, 41 insertions(+), 16 deletions(-) > > diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c > index b0a781f8c450..42a1412b5186 100644 > --- a/drivers/irqchip/irq-gic.c > +++ b/drivers/irqchip/irq-gic.c > @@ -999,13 +999,13 @@ static const struct irq_domain_ops gic_irq_domain_ops = { > .unmap = gic_irq_domain_unmap, > }; > > -static void __init __gic_init_bases(unsigned int gic_nr, int irq_start, > +static int __init __gic_init_bases(unsigned int gic_nr, int irq_start, > void __iomem *dist_base, void __iomem *cpu_base, > u32 percpu_offset, struct fwnode_handle *handle) > { > irq_hw_number_t hwirq_base; > struct gic_chip_data *gic; > - int gic_irqs, irq_base, i; > + int gic_irqs, irq_base, i, ret; > > BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR); > > @@ -1030,17 +1030,16 @@ static void __init __gic_init_bases(unsigned int gic_nr, int irq_start, > gic->chip.irq_set_affinity = gic_set_affinity; > #endif > > -#ifdef CONFIG_GIC_NON_BANKED > - if (percpu_offset) { /* Frankein-GIC without banked registers... */ > + if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && percpu_offset) { > + /* Frankein-GIC without banked registers... */ > unsigned int cpu; > > gic->dist_base.percpu_base = alloc_percpu(void __iomem *); > gic->cpu_base.percpu_base = alloc_percpu(void __iomem *); > if (WARN_ON(!gic->dist_base.percpu_base || > !gic->cpu_base.percpu_base)) { > - free_percpu(gic->dist_base.percpu_base); > - free_percpu(gic->cpu_base.percpu_base); > - return; > + ret = -ENOMEM; > + goto error; > } > > for_each_possible_cpu(cpu) { > @@ -1052,9 +1051,8 @@ static void __init __gic_init_bases(unsigned int gic_nr, int irq_start, > } > > gic_set_base_accessor(gic, gic_get_percpu_base); > - } else > -#endif > - { /* Normal, sane GIC... */ > + } else { > + /* Normal, sane GIC... */ > WARN(percpu_offset, > "GIC_NON_BANKED not enabled, ignoring %08x offset!", > percpu_offset); > @@ -1104,8 +1102,10 @@ static void __init __gic_init_bases(unsigned int gic_nr, int irq_start, > hwirq_base, &gic_irq_domain_ops, gic); > } > > - if (WARN_ON(!gic->domain)) > - return; > + if (WARN_ON(!gic->domain)) { > + ret = -ENODEV; > + goto error; > + } > > if (gic_nr == 0) { > /* > @@ -1127,6 +1127,18 @@ static void __init __gic_init_bases(unsigned int gic_nr, int irq_start, > gic_dist_init(gic); > gic_cpu_init(gic); > gic_pm_init(gic); > + > + return 0; > + > +error: > + if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && percpu_offset) { > + free_percpu(gic->dist_base.percpu_base); > + free_percpu(gic->cpu_base.percpu_base); > + } > + > + kfree(gic->chip.name); Ah, this is where Linus' remark about "GICv2" clashes. Either you keep the allocation in the previous patch, or you guard this with a test on the EOImode. I'll leave it up to you. > + > + return ret; > } > > void __init gic_init(unsigned int gic_nr, int irq_start, > @@ -1187,7 +1199,7 @@ gic_of_init(struct device_node *node, struct device_node *parent) > void __iomem *cpu_base; > void __iomem *dist_base; > u32 percpu_offset; > - int irq; > + int irq, ret; > > if (WARN_ON(!node)) > return -ENODEV; > @@ -1212,8 +1224,14 @@ gic_of_init(struct device_node *node, struct device_node *parent) > if (of_property_read_u32(node, "cpu-offset", &percpu_offset)) > percpu_offset = 0; > > - __gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset, > + ret = __gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset, > &node->fwnode); > + if (ret) { > + iounmap(dist_base); > + iounmap(cpu_base); > + return ret; > + } > + > if (!gic_cnt) > gic_init_physaddr(node); > > @@ -1302,7 +1320,7 @@ static int __init gic_v2_acpi_init(struct acpi_subtable_header *header, > struct acpi_madt_generic_distributor *dist; > void __iomem *cpu_base, *dist_base; > struct fwnode_handle *domain_handle; > - int count; > + int count, ret; > > /* Collect CPU base addresses */ > count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, > @@ -1345,7 +1363,14 @@ static int __init gic_v2_acpi_init(struct acpi_subtable_header *header, > return -ENOMEM; > } > > - __gic_init_bases(0, -1, dist_base, cpu_base, 0, domain_handle); > + ret = __gic_init_bases(0, -1, dist_base, cpu_base, 0, domain_handle); > + if (ret) { > + pr_err("Failed to initialise GIC\n"); > + irq_domain_free_fwnode(domain_handle); > + iounmap(cpu_base); > + iounmap(dist_base); > + return ret; > + } > > acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle); > Otherwise looks good. M. -- Jazz is not dead. It just smells funny.
WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <marc.zyngier@arm.com> To: Jon Hunter <jonathanh@nvidia.com> Cc: "Thomas Gleixner" <tglx@linutronix.de>, "Jason Cooper" <jason@lakedaemon.net>, "Benoît Cousson" <bcousson@baylibre.com>, "Tony Lindgren" <tony@atomide.com>, "Rob Herring" <robh+dt@kernel.org>, "Pawel Moll" <pawel.moll@arm.com>, "Mark Rutland" <mark.rutland@arm.com>, "Ian Campbell" <ijc+devicetree@hellion.org.uk>, "Kumar Gala" <galak@codeaurora.org>, "Stephen Warren" <swarren@wwwdotorg.org>, "Thierry Reding" <thierry.reding@gmail.com>, "Kevin Hilman" <khilman@kernel.org>, "Geert Uytterhoeven" <geert@linux-m68k.org>, "Grygorii Strashko" <grygorii.strashko@ti.com>, "Lars-Peter Clausen" <lars@metafoo.de>, "Linus Walleij" <linus.walleij@linaro.org>, linux-tegra@vger.kernel.org, linux-omap@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 11/15] irqchip/gic: Return an error if GIC initialisation fails Date: Sat, 9 Apr 2016 12:43:33 +0100 [thread overview] Message-ID: <20160409124333.6b7f695d@arm.com> (raw) In-Reply-To: <1458224359-32665-12-git-send-email-jonathanh@nvidia.com> On Thu, 17 Mar 2016 14:19:15 +0000 Jon Hunter <jonathanh@nvidia.com> wrote: > If the GIC initialisation fails, then currently we do not return an error > or clean-up afterwards. Although for root controllers, this failure may be > fatal anyway, for secondary controllers, it may not be fatal and so return > an error on failure and clean-up. > > For non-banked GIC controllers, make sure that we free any memory > allocated if we fail to initialise the IRQ domain. Please note that > free_percpu() only frees memory if the pointer passed to it is not NULL > and so it is unnecessary to check if both pointers are valid or not. > > Signed-off-by: Jon Hunter <jonathanh@nvidia.com> > --- > drivers/irqchip/irq-gic.c | 57 ++++++++++++++++++++++++++++++++++------------- > 1 file changed, 41 insertions(+), 16 deletions(-) > > diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c > index b0a781f8c450..42a1412b5186 100644 > --- a/drivers/irqchip/irq-gic.c > +++ b/drivers/irqchip/irq-gic.c > @@ -999,13 +999,13 @@ static const struct irq_domain_ops gic_irq_domain_ops = { > .unmap = gic_irq_domain_unmap, > }; > > -static void __init __gic_init_bases(unsigned int gic_nr, int irq_start, > +static int __init __gic_init_bases(unsigned int gic_nr, int irq_start, > void __iomem *dist_base, void __iomem *cpu_base, > u32 percpu_offset, struct fwnode_handle *handle) > { > irq_hw_number_t hwirq_base; > struct gic_chip_data *gic; > - int gic_irqs, irq_base, i; > + int gic_irqs, irq_base, i, ret; > > BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR); > > @@ -1030,17 +1030,16 @@ static void __init __gic_init_bases(unsigned int gic_nr, int irq_start, > gic->chip.irq_set_affinity = gic_set_affinity; > #endif > > -#ifdef CONFIG_GIC_NON_BANKED > - if (percpu_offset) { /* Frankein-GIC without banked registers... */ > + if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && percpu_offset) { > + /* Frankein-GIC without banked registers... */ > unsigned int cpu; > > gic->dist_base.percpu_base = alloc_percpu(void __iomem *); > gic->cpu_base.percpu_base = alloc_percpu(void __iomem *); > if (WARN_ON(!gic->dist_base.percpu_base || > !gic->cpu_base.percpu_base)) { > - free_percpu(gic->dist_base.percpu_base); > - free_percpu(gic->cpu_base.percpu_base); > - return; > + ret = -ENOMEM; > + goto error; > } > > for_each_possible_cpu(cpu) { > @@ -1052,9 +1051,8 @@ static void __init __gic_init_bases(unsigned int gic_nr, int irq_start, > } > > gic_set_base_accessor(gic, gic_get_percpu_base); > - } else > -#endif > - { /* Normal, sane GIC... */ > + } else { > + /* Normal, sane GIC... */ > WARN(percpu_offset, > "GIC_NON_BANKED not enabled, ignoring %08x offset!", > percpu_offset); > @@ -1104,8 +1102,10 @@ static void __init __gic_init_bases(unsigned int gic_nr, int irq_start, > hwirq_base, &gic_irq_domain_ops, gic); > } > > - if (WARN_ON(!gic->domain)) > - return; > + if (WARN_ON(!gic->domain)) { > + ret = -ENODEV; > + goto error; > + } > > if (gic_nr == 0) { > /* > @@ -1127,6 +1127,18 @@ static void __init __gic_init_bases(unsigned int gic_nr, int irq_start, > gic_dist_init(gic); > gic_cpu_init(gic); > gic_pm_init(gic); > + > + return 0; > + > +error: > + if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && percpu_offset) { > + free_percpu(gic->dist_base.percpu_base); > + free_percpu(gic->cpu_base.percpu_base); > + } > + > + kfree(gic->chip.name); Ah, this is where Linus' remark about "GICv2" clashes. Either you keep the allocation in the previous patch, or you guard this with a test on the EOImode. I'll leave it up to you. > + > + return ret; > } > > void __init gic_init(unsigned int gic_nr, int irq_start, > @@ -1187,7 +1199,7 @@ gic_of_init(struct device_node *node, struct device_node *parent) > void __iomem *cpu_base; > void __iomem *dist_base; > u32 percpu_offset; > - int irq; > + int irq, ret; > > if (WARN_ON(!node)) > return -ENODEV; > @@ -1212,8 +1224,14 @@ gic_of_init(struct device_node *node, struct device_node *parent) > if (of_property_read_u32(node, "cpu-offset", &percpu_offset)) > percpu_offset = 0; > > - __gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset, > + ret = __gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset, > &node->fwnode); > + if (ret) { > + iounmap(dist_base); > + iounmap(cpu_base); > + return ret; > + } > + > if (!gic_cnt) > gic_init_physaddr(node); > > @@ -1302,7 +1320,7 @@ static int __init gic_v2_acpi_init(struct acpi_subtable_header *header, > struct acpi_madt_generic_distributor *dist; > void __iomem *cpu_base, *dist_base; > struct fwnode_handle *domain_handle; > - int count; > + int count, ret; > > /* Collect CPU base addresses */ > count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, > @@ -1345,7 +1363,14 @@ static int __init gic_v2_acpi_init(struct acpi_subtable_header *header, > return -ENOMEM; > } > > - __gic_init_bases(0, -1, dist_base, cpu_base, 0, domain_handle); > + ret = __gic_init_bases(0, -1, dist_base, cpu_base, 0, domain_handle); > + if (ret) { > + pr_err("Failed to initialise GIC\n"); > + irq_domain_free_fwnode(domain_handle); > + iounmap(cpu_base); > + iounmap(dist_base); > + return ret; > + } > > acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle); > Otherwise looks good. M. -- Jazz is not dead. It just smells funny.
next prev parent reply other threads:[~2016-04-09 11:43 UTC|newest] Thread overview: 125+ messages / expand[flat|nested] mbox.gz Atom feed top 2016-03-17 14:19 [PATCH 00/15] Add support for Tegra210 AGIC Jon Hunter 2016-03-17 14:19 ` [PATCH 01/15] ARM: tegra: Correct interrupt type for ARM TWD Jon Hunter [not found] ` <1458224359-32665-2-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2016-04-01 23:25 ` Kevin Hilman 2016-04-01 23:25 ` Kevin Hilman 2016-04-05 14:04 ` Thierry Reding 2016-04-05 14:04 ` Thierry Reding 2016-03-17 14:19 ` [PATCH 02/15] ARM: OMAP: " Jon Hunter [not found] ` <1458224359-32665-3-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2016-03-18 15:41 ` Grygorii Strashko 2016-03-18 15:41 ` Grygorii Strashko [not found] ` <56EC2191.2060800-l0cyMroinI0@public.gmane.org> 2016-03-29 14:02 ` Jon Hunter 2016-03-29 14:02 ` Jon Hunter [not found] ` <56FA8AEA.3000208-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2016-03-30 21:23 ` Tony Lindgren 2016-03-30 21:23 ` Tony Lindgren [not found] ` <1458224359-32665-1-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2016-03-17 14:19 ` [PATCH 03/15] irqchip/gic: Don't unnecessarily write the IRQ configuration Jon Hunter 2016-03-17 14:19 ` Jon Hunter [not found] ` <1458224359-32665-4-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2016-04-09 10:50 ` Marc Zyngier 2016-04-09 10:50 ` Marc Zyngier 2016-03-17 14:19 ` [PATCH 04/15] irqchip/gic: WARN if setting the interrupt type fails Jon Hunter 2016-03-17 14:19 ` Jon Hunter [not found] ` <1458224359-32665-5-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2016-03-17 14:51 ` Thomas Gleixner 2016-03-17 14:51 ` Thomas Gleixner 2016-03-17 15:04 ` Jon Hunter 2016-03-17 15:18 ` Jason Cooper [not found] ` <20160317151800.GH1184-fahSIxCzskDQ+YiMSub0/l6hYfS7NtTn@public.gmane.org> 2016-03-17 16:20 ` Jon Hunter 2016-03-17 16:20 ` Jon Hunter 2016-03-18 9:20 ` Geert Uytterhoeven [not found] ` <CAMuHMdU8PDUVZ8=S04fkahez1dh7JHjpj2-3w+Vfz05X=ZFMUQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 2016-03-18 9:54 ` Jon Hunter 2016-03-18 9:54 ` Jon Hunter [not found] ` <56EBD061.6030502-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2016-03-18 10:22 ` Geert Uytterhoeven 2016-03-18 10:22 ` Geert Uytterhoeven [not found] ` <56EAC761.1040801-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2016-04-09 10:58 ` Marc Zyngier 2016-04-09 10:58 ` Marc Zyngier 2016-04-11 15:31 ` Jon Hunter [not found] ` <570BC34A.5030806-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2016-04-11 15:39 ` Marc Zyngier 2016-04-11 15:39 ` Marc Zyngier [not found] ` <570BC528.9050601-5wv7dgnIgG8@public.gmane.org> 2016-04-12 8:50 ` Jon Hunter 2016-04-12 8:50 ` Jon Hunter 2016-04-12 10:14 ` Marc Zyngier 2016-03-17 14:19 ` [PATCH 07/15] irqdomain: Don't set type when mapping an IRQ Jon Hunter 2016-03-17 14:19 ` Jon Hunter [not found] ` <1458224359-32665-8-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2016-03-17 14:55 ` Thomas Gleixner 2016-03-17 14:55 ` Thomas Gleixner 2016-03-17 15:06 ` Jon Hunter 2016-03-17 18:19 ` Jon Hunter 2016-03-17 18:19 ` Jon Hunter 2016-03-17 14:19 ` [PATCH 08/15] genirq: Add runtime power management support for IRQ chips Jon Hunter 2016-03-17 14:19 ` Jon Hunter [not found] ` <1458224359-32665-9-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2016-03-17 15:02 ` Marc Zyngier 2016-03-17 15:02 ` Marc Zyngier 2016-03-17 15:13 ` Jon Hunter 2016-03-17 15:13 ` Jon Hunter 2016-03-17 15:28 ` Marc Zyngier [not found] ` <56EACD21.20309-5wv7dgnIgG8@public.gmane.org> 2016-03-22 11:46 ` Linus Walleij 2016-03-22 11:46 ` Linus Walleij 2016-03-18 11:11 ` Grygorii Strashko 2016-03-18 11:11 ` Grygorii Strashko [not found] ` <56EBE244.6070400-l0cyMroinI0@public.gmane.org> 2016-03-18 12:27 ` Jon Hunter 2016-03-18 12:27 ` Jon Hunter 2016-03-18 14:23 ` Grygorii Strashko 2016-03-18 14:23 ` Grygorii Strashko [not found] ` <56EC0F7D.8050106-l0cyMroinI0@public.gmane.org> 2016-03-18 14:40 ` Jon Hunter 2016-03-18 14:40 ` Jon Hunter [not found] ` <56EC1362.2000005-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2016-03-18 14:56 ` Jon Hunter 2016-03-18 14:56 ` Jon Hunter [not found] ` <56EC1719.5020408-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2016-03-18 17:52 ` Grygorii Strashko 2016-03-18 17:52 ` Grygorii Strashko 2016-03-21 10:09 ` Jon Hunter 2016-03-21 10:09 ` Jon Hunter 2016-03-17 15:02 ` Thomas Gleixner 2016-03-17 15:46 ` Jon Hunter 2016-03-17 15:46 ` Jon Hunter 2016-03-17 14:19 ` [PATCH 05/15] irqchip: Mask the non-type/sense bits when translating an IRQ Jon Hunter [not found] ` <1458224359-32665-6-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2016-04-09 11:03 ` Marc Zyngier 2016-04-09 11:03 ` Marc Zyngier [not found] ` <20160409120333.3982c53b-5wv7dgnIgG8@public.gmane.org> 2016-04-19 14:14 ` Jon Hunter 2016-04-19 14:14 ` Jon Hunter [not found] ` <57163D2F.5020005-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2016-04-19 14:23 ` Marc Zyngier 2016-04-19 14:23 ` Marc Zyngier 2016-03-17 14:19 ` [PATCH 06/15] irqdomain: Ensure type settings match for an existing mapping Jon Hunter [not found] ` <1458224359-32665-7-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2016-03-17 18:18 ` Jon Hunter 2016-03-17 18:18 ` Jon Hunter 2016-03-18 10:03 ` Grygorii Strashko 2016-03-18 10:03 ` Grygorii Strashko [not found] ` <56EBD272.1040404-l0cyMroinI0@public.gmane.org> 2016-03-18 10:33 ` Jon Hunter 2016-03-18 10:33 ` Jon Hunter 2016-03-17 14:19 ` [PATCH 09/15] irqchip/gic: Don't initialise chip if mapping IO space fails Jon Hunter [not found] ` <1458224359-32665-10-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2016-04-09 11:09 ` Marc Zyngier 2016-04-09 11:09 ` Marc Zyngier 2016-03-17 14:19 ` [PATCH 10/15] irqchip/gic: Remove static irq_chip definition for eoimode1 Jon Hunter [not found] ` <1458224359-32665-11-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2016-03-22 11:49 ` Linus Walleij 2016-03-22 11:49 ` Linus Walleij 2016-04-09 11:38 ` Marc Zyngier 2016-03-17 14:19 ` [PATCH 11/15] irqchip/gic: Return an error if GIC initialisation fails Jon Hunter [not found] ` <1458224359-32665-12-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2016-04-09 11:43 ` Marc Zyngier [this message] 2016-04-09 11:43 ` Marc Zyngier 2016-03-17 14:19 ` [PATCH 12/15] irqchip/gic: Pass GIC pointer to save/restore functions Jon Hunter 2016-04-09 11:52 ` Marc Zyngier 2016-03-17 14:19 ` [PATCH 13/15] irqchip/gic: Prepare for adding platform driver Jon Hunter [not found] ` <1458224359-32665-14-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2016-03-29 13:04 ` Geert Uytterhoeven 2016-03-29 13:04 ` Geert Uytterhoeven [not found] ` <CAMuHMdVwZgsPNdkWooLHg5H9_Mmv_mKa=zh9T4K-mfjPUEk4CQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 2016-03-29 13:59 ` Jon Hunter 2016-03-29 13:59 ` Jon Hunter 2016-03-17 14:19 ` [PATCH 14/15] dt-bindings: arm-gic: Drop 'clock-names' from binding document Jon Hunter [not found] ` <1458224359-32665-15-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2016-03-17 20:14 ` Rob Herring 2016-03-17 20:14 ` Rob Herring 2016-03-18 8:37 ` Jon Hunter [not found] ` <56EBBE38.6070303-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2016-04-12 8:54 ` Jon Hunter 2016-04-12 8:54 ` Jon Hunter 2016-03-18 9:13 ` Geert Uytterhoeven 2016-03-18 9:13 ` Geert Uytterhoeven [not found] ` <CAMuHMdV0QiWR0bML44zhAx+MStmQhQWKd=b_TMKnEdu_hw_ReA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 2016-03-18 10:13 ` Jon Hunter 2016-03-18 10:13 ` Jon Hunter [not found] ` <56EBD4E5.1060002-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2016-03-18 10:52 ` Geert Uytterhoeven 2016-03-18 10:52 ` Geert Uytterhoeven [not found] ` <CAMuHMdWXqS9cru74Ckr47gFVTf2MkmjZUtMt4MeXW_1V7x+KHw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 2016-03-18 10:56 ` Jon Hunter 2016-03-18 10:56 ` Jon Hunter [not found] ` <56EBDEFA.30102-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2016-03-18 12:05 ` Geert Uytterhoeven 2016-03-18 12:05 ` Geert Uytterhoeven [not found] ` <CAMuHMdUkGiX6YWzbRVJaJ4BNskE8PUXq-7Zob40f=CEZyjtJiA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 2016-03-18 12:42 ` Jon Hunter 2016-03-18 12:42 ` Jon Hunter 2016-03-18 12:47 ` Grygorii Strashko [not found] ` <56EBF8E0.8020700-l0cyMroinI0@public.gmane.org> 2016-03-18 13:02 ` Geert Uytterhoeven 2016-03-18 13:02 ` Geert Uytterhoeven 2016-03-18 18:36 ` Grygorii Strashko 2016-03-17 14:19 ` [PATCH 15/15] irqchip/gic: Add support for tegra AGIC interrupt controller Jon Hunter
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