[PATCH 00/11] Addition of Altera Arria10 System Resource Chip

[PATCH 00/11] Addition of Altera Arria10 System Resource Chip

[tthayer]

From: Thor Thayer <tthayer@opensource.altera.com>

This patch series adds the SPI MultiFunction Device for the Altera System
Resource Chip for the Arria10 Developement Kit. The MFD implements GPIO
expansion and power supply alarms on an Altera MAX5.

Thor Thayer (11):
  dt-bindings: mfd: Add Altera Arria10 System Resource Chip bindings
  MAINTAINERS: Add Altera Arria10 System Resource Chip
  mfd: altr_a10sr: Add Altera Arria10 DevKit System Resource Chip
  gpio: altera-a10sr: Add A10 System Resource Chip GPIO support.
  ARM: socfpga: dts: Add SPI Master1 for Arria10 System Resource chip
  ARM: socfpga: dts: Add Devkit A10-SR fields for Arria10
  ARM: socfpga: dts: Add LED framework to A10-SR GPIO
  dt-bindings: mfd: Add Altera A10-SR power supply alarm
  mfd: altr_a10sr: Add Altera A10-SR power supply alarms
  hwmon: Add Altera A10-SR power supply alarms
  ARM: socfpga: dts: Add A10-SR Devkit power supply alarms

 .../devicetree/bindings/mfd/altera-a10sr.txt       |   43 ++++
 MAINTAINERS                                        |    8 +
 arch/arm/boot/dts/socfpga_arria10.dtsi             |   15 ++
 arch/arm/boot/dts/socfpga_arria10_socdk.dtsi       |   44 ++++
 drivers/gpio/Kconfig                               |    8 +
 drivers/gpio/Makefile                              |    1 +
 drivers/gpio/gpio-altera-a10sr.c                   |  140 +++++++++++++
 drivers/hwmon/Kconfig                              |    9 +
 drivers/hwmon/Makefile                             |    1 +
 drivers/hwmon/altera-a10sr-hwmon.c                 |  215 ++++++++++++++++++++
 drivers/mfd/Kconfig                                |   11 +
 drivers/mfd/Makefile                               |    2 +
 drivers/mfd/altera-a10sr.c                         |  183 +++++++++++++++++
 include/linux/mfd/altera-a10sr.h                   |  111 ++++++++++
 14 files changed, 791 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mfd/altera-a10sr.txt
 create mode 100644 drivers/gpio/gpio-altera-a10sr.c
 create mode 100644 drivers/hwmon/altera-a10sr-hwmon.c
 create mode 100644 drivers/mfd/altera-a10sr.c
 create mode 100644 include/linux/mfd/altera-a10sr.h

-- 
1.7.9.5

[PATCH 00/11] Addition of Altera Arria10 System Resource Chip

[tthayer]

From: Thor Thayer <tthayer@opensource.altera.com>

This patch series adds the SPI MultiFunction Device for the Altera System
Resource Chip for the Arria10 Developement Kit. The MFD implements GPIO
expansion and power supply alarms on an Altera MAX5.

Thor Thayer (11):
  dt-bindings: mfd: Add Altera Arria10 System Resource Chip bindings
  MAINTAINERS: Add Altera Arria10 System Resource Chip
  mfd: altr_a10sr: Add Altera Arria10 DevKit System Resource Chip
  gpio: altera-a10sr: Add A10 System Resource Chip GPIO support.
  ARM: socfpga: dts: Add SPI Master1 for Arria10 System Resource chip
  ARM: socfpga: dts: Add Devkit A10-SR fields for Arria10
  ARM: socfpga: dts: Add LED framework to A10-SR GPIO
  dt-bindings: mfd: Add Altera A10-SR power supply alarm
  mfd: altr_a10sr: Add Altera A10-SR power supply alarms
  hwmon: Add Altera A10-SR power supply alarms
  ARM: socfpga: dts: Add A10-SR Devkit power supply alarms

 .../devicetree/bindings/mfd/altera-a10sr.txt       |   43 ++++
 MAINTAINERS                                        |    8 +
 arch/arm/boot/dts/socfpga_arria10.dtsi             |   15 ++
 arch/arm/boot/dts/socfpga_arria10_socdk.dtsi       |   44 ++++
 drivers/gpio/Kconfig                               |    8 +
 drivers/gpio/Makefile                              |    1 +
 drivers/gpio/gpio-altera-a10sr.c                   |  140 +++++++++++++
 drivers/hwmon/Kconfig                              |    9 +
 drivers/hwmon/Makefile                             |    1 +
 drivers/hwmon/altera-a10sr-hwmon.c                 |  215 ++++++++++++++++++++
 drivers/mfd/Kconfig                                |   11 +
 drivers/mfd/Makefile                               |    2 +
 drivers/mfd/altera-a10sr.c                         |  183 +++++++++++++++++
 include/linux/mfd/altera-a10sr.h                   |  111 ++++++++++
 14 files changed, 791 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mfd/altera-a10sr.txt
 create mode 100644 drivers/gpio/gpio-altera-a10sr.c
 create mode 100644 drivers/hwmon/altera-a10sr-hwmon.c
 create mode 100644 drivers/mfd/altera-a10sr.c
 create mode 100644 include/linux/mfd/altera-a10sr.h

-- 
1.7.9.5

[PATCH 01/11] dt-bindings: mfd: Add Altera Arria10 System Resource Chip bindings

[tthayer]

From: Thor Thayer <tthayer@opensource.altera.com>

The Altera Arria10 Devkit System Resource chip is a Multi-Function
Device with a GPIO expander and power supply alarm.

This patch adds documentation for the Altera A10-SR DT bindings.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
 .../devicetree/bindings/mfd/altera-a10sr.txt       |   35 ++++++++++++++++++++
 1 file changed, 35 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mfd/altera-a10sr.txt

diff --git a/Documentation/devicetree/bindings/mfd/altera-a10sr.txt b/Documentation/devicetree/bindings/mfd/altera-a10sr.txt
new file mode 100644
index 0000000..8e17d05
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/altera-a10sr.txt
@@ -0,0 +1,35 @@
+* Altera Arria10 Development Kit System Resource Chip
+
+Required parent device properties:
+- compatible	    : "altr,a10sr"
+- spi-max-frequency : Maximum SPI frequency.
+- reg		    : The SPI Chip Select address for the Arria10
+		      System Resource chip
+
+The A10SR consists of this varied group of sub-devices:
+
+Device                   Description
+------                   ----------
+a10sr_gpio               GPIO Controller
+
+Arria10 GPIO
+Required Properties:
+- compatible        : Should be "altr,a10sr-gpio"
+- gpio-controller   : Marks the device node as a GPIO Controller.
+- #gpio-cells       : Should be two.  The first cell is the pin number and
+                      the second cell is used to specify flags.
+                      See ../gpio/gpio.txt for more information.
+
+Example:
+
+        resource-manager@0 {
+		compatible = "altr,a10sr";
+		reg = <0>;
+		spi-max-frequency = <100000>;
+
+		a10sr_gpio: gpio-controller {
+			compatible = "altr,a10sr-gpio";
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+	};
-- 
1.7.9.5

[PATCH 01/11] dt-bindings: mfd: Add Altera Arria10 System Resource Chip bindings

[tthayer]

From: Thor Thayer <tthayer@opensource.altera.com>

The Altera Arria10 Devkit System Resource chip is a Multi-Function
Device with a GPIO expander and power supply alarm.

This patch adds documentation for the Altera A10-SR DT bindings.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
 .../devicetree/bindings/mfd/altera-a10sr.txt       |   35 ++++++++++++++++++++
 1 file changed, 35 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mfd/altera-a10sr.txt

diff --git a/Documentation/devicetree/bindings/mfd/altera-a10sr.txt b/Documentation/devicetree/bindings/mfd/altera-a10sr.txt
new file mode 100644
index 0000000..8e17d05
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/altera-a10sr.txt
@@ -0,0 +1,35 @@
+* Altera Arria10 Development Kit System Resource Chip
+
+Required parent device properties:
+- compatible	    : "altr,a10sr"
+- spi-max-frequency : Maximum SPI frequency.
+- reg		    : The SPI Chip Select address for the Arria10
+		      System Resource chip
+
+The A10SR consists of this varied group of sub-devices:
+
+Device                   Description
+------                   ----------
+a10sr_gpio               GPIO Controller
+
+Arria10 GPIO
+Required Properties:
+- compatible        : Should be "altr,a10sr-gpio"
+- gpio-controller   : Marks the device node as a GPIO Controller.
+- #gpio-cells       : Should be two.  The first cell is the pin number and
+                      the second cell is used to specify flags.
+                      See ../gpio/gpio.txt for more information.
+
+Example:
+
+        resource-manager@0 {
+		compatible = "altr,a10sr";
+		reg = <0>;
+		spi-max-frequency = <100000>;
+
+		a10sr_gpio: gpio-controller {
+			compatible = "altr,a10sr-gpio";
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+	};
-- 
1.7.9.5

Re: [PATCH 01/11] dt-bindings: mfd: Add Altera Arria10 System Resource Chip bindings

[Rob Herring]

On Fri, Apr 22, 2016 at 10:33:29AM -0500, tthayer@opensource.altera.com wrote:
> From: Thor Thayer <tthayer@opensource.altera.com>
> 
> The Altera Arria10 Devkit System Resource chip is a Multi-Function
> Device with a GPIO expander and power supply alarm.

An alarm with no interrupt? Are the GPIOs interrupt capable?
 
> This patch adds documentation for the Altera A10-SR DT bindings.
> 
> Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
> ---
>  .../devicetree/bindings/mfd/altera-a10sr.txt       |   35 ++++++++++++++++++++
>  1 file changed, 35 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/mfd/altera-a10sr.txt
> 

Re: [PATCH 01/11] dt-bindings: mfd: Add Altera Arria10 System Resource Chip bindings

[Rob Herring]

On Fri, Apr 22, 2016 at 10:33:29AM -0500, ttha...@opensource.altera.com wrote:
> From: Thor Thayer <ttha...@opensource.altera.com>
> 
> The Altera Arria10 Devkit System Resource chip is a Multi-Function
> Device with a GPIO expander and power supply alarm.

An alarm with no interrupt? Are the GPIOs interrupt capable?
 
> This patch adds documentation for the Altera A10-SR DT bindings.
> 
> Signed-off-by: Thor Thayer <ttha...@opensource.altera.com>
> ---
>  .../devicetree/bindings/mfd/altera-a10sr.txt       |   35 
> ++++++++++++++++++++
>  1 file changed, 35 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/mfd/altera-a10sr.txt
> 
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Re: [PATCH 01/11] dt-bindings: mfd: Add Altera Arria10 System Resource Chip bindings

[Thor Thayer]

On 04/25/2016 07:55 AM, Rob Herring wrote:
> On Fri, Apr 22, 2016 at 10:33:29AM -0500, tthayer@opensource.altera.com wrote:
>> From: Thor Thayer <tthayer@opensource.altera.com>
>>
>> The Altera Arria10 Devkit System Resource chip is a Multi-Function
>> Device with a GPIO expander and power supply alarm.
>
> An alarm with no interrupt? Are the GPIOs interrupt capable?

The alarms have no interrupt but the GPIOs are interrupt capable (not 
implemented with interrupt capability in this patch series).

>
>> This patch adds documentation for the Altera A10-SR DT bindings.
>>
>> Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
>> ---
>>   .../devicetree/bindings/mfd/altera-a10sr.txt       |   35 ++++++++++++++++++++
>>   1 file changed, 35 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/mfd/altera-a10sr.txt
>>

Re: [PATCH 01/11] dt-bindings: mfd: Add Altera Arria10 System Resource Chip bindings

[Thor Thayer]

On 04/25/2016 07:55 AM, Rob Herring wrote:
> On Fri, Apr 22, 2016 at 10:33:29AM -0500, tthayer@opensource.altera.com wrote:
>> From: Thor Thayer <tthayer@opensource.altera.com>
>>
>> The Altera Arria10 Devkit System Resource chip is a Multi-Function
>> Device with a GPIO expander and power supply alarm.
>
> An alarm with no interrupt? Are the GPIOs interrupt capable?

The alarms have no interrupt but the GPIOs are interrupt capable (not 
implemented with interrupt capability in this patch series).

>
>> This patch adds documentation for the Altera A10-SR DT bindings.
>>
>> Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
>> ---
>>   .../devicetree/bindings/mfd/altera-a10sr.txt       |   35 ++++++++++++++++++++
>>   1 file changed, 35 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/mfd/altera-a10sr.txt
>>

Re: [PATCH 01/11] dt-bindings: mfd: Add Altera Arria10 System Resource Chip bindings

[Rob Herring]

On Mon, Apr 25, 2016 at 10:01:52AM -0500, Thor Thayer wrote:
> 
> 
> On 04/25/2016 07:55 AM, Rob Herring wrote:
> >On Fri, Apr 22, 2016 at 10:33:29AM -0500, tthayer@opensource.altera.com wrote:
> >>From: Thor Thayer <tthayer@opensource.altera.com>
> >>
> >>The Altera Arria10 Devkit System Resource chip is a Multi-Function
> >>Device with a GPIO expander and power supply alarm.
> >
> >An alarm with no interrupt? Are the GPIOs interrupt capable?
> 
> The alarms have no interrupt but the GPIOs are interrupt capable (not
> implemented with interrupt capability in this patch series).

Please make the binding as complete as possible even if you don't 
support features in the driver yet. Driver features may evolve, but a 
specific h/w doesn't.

Rob

Re: [PATCH 01/11] dt-bindings: mfd: Add Altera Arria10 System Resource Chip bindings

[Rob Herring]

On Mon, Apr 25, 2016 at 10:01:52AM -0500, Thor Thayer wrote:
> 
> 
> On 04/25/2016 07:55 AM, Rob Herring wrote:
> >On Fri, Apr 22, 2016 at 10:33:29AM -0500, ttha...@opensource.altera.com 
> >wrote:
> >>From: Thor Thayer <ttha...@opensource.altera.com>
> >>
> >>The Altera Arria10 Devkit System Resource chip is a Multi-Function
> >>Device with a GPIO expander and power supply alarm.
> >
> >An alarm with no interrupt? Are the GPIOs interrupt capable?
> 
> The alarms have no interrupt but the GPIOs are interrupt capable (not
> implemented with interrupt capability in this patch series).

Please make the binding as complete as possible even if you don't 
support features in the driver yet. Driver features may evolve, but a 
specific h/w doesn't.

Rob
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[PATCH 02/11] MAINTAINERS: Add Altera Arria10 System Resource Chip

[tthayer]

From: Thor Thayer <tthayer@opensource.altera.com>

Add maintainer for the Altera Arria10 Max5 System Resource chip files.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
 MAINTAINERS |    8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 724bb86..e5f2621 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -608,6 +608,14 @@ L:	linux-gpio@vger.kernel.org
 S:	Maintained
 F:	drivers/gpio/gpio-altera.c
 
+ALTERA SYSTEM RESOURCE DRIVER FOR ARRIA10 DEVKIT
+M:	Thor Thayer <tthayer@opensource.altera.com>
+S:	Maintained
+F:	drivers/gpio/gpio-altera-a10sr.c
+F:	drivers/hwmon/altera-a10sr-hwmon.c
+F:	drivers/mfd/altera-a10sr.c
+F:	include/linux/mfd/altera-a10sr.h
+
 ALTERA TRIPLE SPEED ETHERNET DRIVER
 M:	Vince Bridgers <vbridger@opensource.altera.com>
 L:	netdev@vger.kernel.org
-- 
1.7.9.5

[PATCH 02/11] MAINTAINERS: Add Altera Arria10 System Resource Chip

[tthayer]

From: Thor Thayer <tthayer@opensource.altera.com>

Add maintainer for the Altera Arria10 Max5 System Resource chip files.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
 MAINTAINERS |    8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 724bb86..e5f2621 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -608,6 +608,14 @@ L:	linux-gpio@vger.kernel.org
 S:	Maintained
 F:	drivers/gpio/gpio-altera.c
 
+ALTERA SYSTEM RESOURCE DRIVER FOR ARRIA10 DEVKIT
+M:	Thor Thayer <tthayer@opensource.altera.com>
+S:	Maintained
+F:	drivers/gpio/gpio-altera-a10sr.c
+F:	drivers/hwmon/altera-a10sr-hwmon.c
+F:	drivers/mfd/altera-a10sr.c
+F:	include/linux/mfd/altera-a10sr.h
+
 ALTERA TRIPLE SPEED ETHERNET DRIVER
 M:	Vince Bridgers <vbridger@opensource.altera.com>
 L:	netdev@vger.kernel.org
-- 
1.7.9.5

Re: [PATCH 02/11] MAINTAINERS: Add Altera Arria10 System Resource Chip

[Lee Jones]

On Fri, 22 Apr 2016, tthayer@opensource.altera.com wrote:

> From: Thor Thayer <tthayer@opensource.altera.com>
> 
> Add maintainer for the Altera Arria10 Max5 System Resource chip files.
> 
> Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
> ---
>  MAINTAINERS |    8 ++++++++
>  1 file changed, 8 insertions(+)

For my own reference:
  Acked-by: Lee Jones <lee.jones@linaro.org>

> diff --git a/MAINTAINERS b/MAINTAINERS
> index 724bb86..e5f2621 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -608,6 +608,14 @@ L:	linux-gpio@vger.kernel.org
>  S:	Maintained
>  F:	drivers/gpio/gpio-altera.c
>  
> +ALTERA SYSTEM RESOURCE DRIVER FOR ARRIA10 DEVKIT
> +M:	Thor Thayer <tthayer@opensource.altera.com>
> +S:	Maintained
> +F:	drivers/gpio/gpio-altera-a10sr.c
> +F:	drivers/hwmon/altera-a10sr-hwmon.c
> +F:	drivers/mfd/altera-a10sr.c
> +F:	include/linux/mfd/altera-a10sr.h
> +
>  ALTERA TRIPLE SPEED ETHERNET DRIVER
>  M:	Vince Bridgers <vbridger@opensource.altera.com>
>  L:	netdev@vger.kernel.org

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
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Re: [PATCH 02/11] MAINTAINERS: Add Altera Arria10 System Resource Chip

[Lee Jones]

On Fri, 22 Apr 2016, ttha...@opensource.altera.com wrote:

> From: Thor Thayer <ttha...@opensource.altera.com>
> 
> Add maintainer for the Altera Arria10 Max5 System Resource chip files.
> 
> Signed-off-by: Thor Thayer <ttha...@opensource.altera.com>
> ---
>  MAINTAINERS |    8 ++++++++
>  1 file changed, 8 insertions(+)

For my own reference:
  Acked-by: Lee Jones <lee.jo...@linaro.org>

> diff --git a/MAINTAINERS b/MAINTAINERS
> index 724bb86..e5f2621 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -608,6 +608,14 @@ L:       linux-g...@vger.kernel.org
>  S:   Maintained
>  F:   drivers/gpio/gpio-altera.c
>  
> +ALTERA SYSTEM RESOURCE DRIVER FOR ARRIA10 DEVKIT
> +M:   Thor Thayer <ttha...@opensource.altera.com>
> +S:   Maintained
> +F:   drivers/gpio/gpio-altera-a10sr.c
> +F:   drivers/hwmon/altera-a10sr-hwmon.c
> +F:   drivers/mfd/altera-a10sr.c
> +F:   include/linux/mfd/altera-a10sr.h
> +
>  ALTERA TRIPLE SPEED ETHERNET DRIVER
>  M:   Vince Bridgers <vbrid...@opensource.altera.com>
>  L:   net...@vger.kernel.org

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
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[PATCH 03/11] mfd: altr_a10sr: Add Altera Arria10 DevKit System Resource Chip

[tthayer]

From: Thor Thayer <tthayer@opensource.altera.com>

Add support for the Altera Arria10 Development Kit System Resource
chip which is implemented using a MAX5 as a external gpio extender,
and power supply alarm (hwmon) with the regmap framework over a SPI bus.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
 drivers/mfd/Kconfig              |   11 +++
 drivers/mfd/Makefile             |    2 +
 drivers/mfd/altera-a10sr.c       |  179 ++++++++++++++++++++++++++++++++++++++
 include/linux/mfd/altera-a10sr.h |   87 ++++++++++++++++++
 4 files changed, 279 insertions(+)
 create mode 100644 drivers/mfd/altera-a10sr.c
 create mode 100644 include/linux/mfd/altera-a10sr.h

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index eea61e3..4fc27c6 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -18,6 +18,17 @@ config MFD_CS5535
 	  This is the core driver for CS5535/CS5536 MFD functions.  This is
           necessary for using the board's GPIO and MFGPT functionality.
 
+config MFD_ALTERA_A10SR
+       bool "Altera Arria10 DevKit System Resource chip"
+       depends on ARCH_SOCFPGA && SPI_MASTER=y && OF
+       select REGMAP_SPI
+       select MFD_CORE
+       help
+         Support for the Altera Arria10 DevKit MAX5 System Resource chip
+         using the SPI interface. This driver provides common support for
+         accessing the external gpio extender (LEDs & buttons) and
+         power supply alarms (hwmon).
+
 config MFD_ACT8945A
 	tristate "Active-semi ACT8945A"
 	select MFD_CORE
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 5eaa6465d..4f1ff91 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -203,3 +203,5 @@ intel-soc-pmic-objs		:= intel_soc_pmic_core.o intel_soc_pmic_crc.o
 intel-soc-pmic-$(CONFIG_INTEL_PMC_IPC)	+= intel_soc_pmic_bxtwc.o
 obj-$(CONFIG_INTEL_SOC_PMIC)	+= intel-soc-pmic.o
 obj-$(CONFIG_MFD_MT6397)	+= mt6397-core.o
+
+obj-$(CONFIG_MFD_ALTERA_A10SR)	+= altera-a10sr.o
diff --git a/drivers/mfd/altera-a10sr.c b/drivers/mfd/altera-a10sr.c
new file mode 100644
index 0000000..2ff08e3
--- /dev/null
+++ b/drivers/mfd/altera-a10sr.c
@@ -0,0 +1,179 @@
+/*
+ * Copyright Altera Corporation (C) 2014-2016. All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * SPI access for Altera Arria10 MAX5 System Resource Chip
+ *
+ * Adapted from DA9052
+ * Copyright(c) 2011 Dialog Semiconductor Ltd.
+ * Author: David Dajun Chen <dchen@diasemi.com>
+ */
+
+#include <linux/mfd/altera-a10sr.h>
+#include <linux/mfd/core.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/spi/spi.h>
+
+static const struct mfd_cell altr_a10sr_subdev_info[] = {
+	{
+		.name = "altr_a10sr_gpio",
+		.of_compatible = "altr,a10sr-gpio",
+	},
+};
+
+static bool altr_a10sr_reg_readable(struct device *dev, unsigned int reg)
+{
+	switch (reg) {
+	case ALTR_A10SR_VERSION_READ:
+	case ALTR_A10SR_LED_REG:
+	case ALTR_A10SR_PBDSW_REG:
+	case ALTR_A10SR_PBDSW_IRQ_REG:
+	case ALTR_A10SR_PWR_GOOD1_REG:
+	case ALTR_A10SR_PWR_GOOD2_REG:
+	case ALTR_A10SR_PWR_GOOD3_REG:
+	case ALTR_A10SR_FMCAB_REG:
+	case ALTR_A10SR_HPS_RST_REG:
+	case ALTR_A10SR_USB_QSPI_REG:
+	case ALTR_A10SR_SFPA_REG:
+	case ALTR_A10SR_SFPB_REG:
+	case ALTR_A10SR_I2C_M_REG:
+	case ALTR_A10SR_WARM_RST_REG:
+	case ALTR_A10SR_WR_KEY_REG:
+	case ALTR_A10SR_PMBUS_REG:
+		return true;
+	default:
+		return false;
+	}
+}
+
+static bool altr_a10sr_reg_writeable(struct device *dev, unsigned int reg)
+{
+	switch (reg) {
+	case ALTR_A10SR_LED_REG:
+	case ALTR_A10SR_PBDSW_IRQ_REG:
+	case ALTR_A10SR_FMCAB_REG:
+	case ALTR_A10SR_HPS_RST_REG:
+	case ALTR_A10SR_USB_QSPI_REG:
+	case ALTR_A10SR_SFPA_REG:
+	case ALTR_A10SR_SFPB_REG:
+	case ALTR_A10SR_WARM_RST_REG:
+	case ALTR_A10SR_WR_KEY_REG:
+	case ALTR_A10SR_PMBUS_REG:
+		return true;
+	default:
+		return false;
+	}
+}
+
+static bool altr_a10sr_reg_volatile(struct device *dev, unsigned int reg)
+{
+	switch (reg) {
+	case ALTR_A10SR_PBDSW_REG:
+	case ALTR_A10SR_PBDSW_IRQ_REG:
+	case ALTR_A10SR_PWR_GOOD1_REG:
+	case ALTR_A10SR_PWR_GOOD2_REG:
+	case ALTR_A10SR_PWR_GOOD3_REG:
+	case ALTR_A10SR_HPS_RST_REG:
+	case ALTR_A10SR_I2C_M_REG:
+	case ALTR_A10SR_WARM_RST_REG:
+	case ALTR_A10SR_WR_KEY_REG:
+	case ALTR_A10SR_PMBUS_REG:
+		return true;
+	default:
+		return false;
+	}
+}
+
+const struct regmap_config altr_a10sr_regmap_config = {
+	.reg_bits = 8,
+	.val_bits = 8,
+
+	.cache_type = REGCACHE_NONE,
+
+	.use_single_rw = true,
+	.read_flag_mask = 1,
+	.write_flag_mask = 0,
+
+	.max_register = ALTR_A10SR_WR_KEY_REG,
+	.readable_reg = altr_a10sr_reg_readable,
+	.writeable_reg = altr_a10sr_reg_writeable,
+	.volatile_reg = altr_a10sr_reg_volatile,
+
+};
+
+static int altr_a10sr_spi_probe(struct spi_device *spi)
+{
+	int ret;
+	struct altr_a10sr *a10sr;
+
+	a10sr = devm_kzalloc(&spi->dev, sizeof(*a10sr),
+			     GFP_KERNEL);
+	if (!a10sr)
+		return -ENOMEM;
+
+	spi->mode = SPI_MODE_3;
+	spi->bits_per_word = 8;
+	spi_setup(spi);
+
+	a10sr->dev = &spi->dev;
+
+	spi_set_drvdata(spi, a10sr);
+
+	a10sr->regmap = devm_regmap_init_spi(spi, &altr_a10sr_regmap_config);
+	if (IS_ERR(a10sr->regmap)) {
+		ret = PTR_ERR(a10sr->regmap);
+		dev_err(&spi->dev, "Failed to allocate register map: %d\n",
+			ret);
+		return ret;
+	}
+
+	ret = mfd_add_devices(a10sr->dev, PLATFORM_DEVID_AUTO,
+			      altr_a10sr_subdev_info,
+			      ARRAY_SIZE(altr_a10sr_subdev_info),
+			      NULL, 0, NULL);
+	if (ret)
+		dev_err(a10sr->dev, "Failed to register sub-devices: %d\n",
+			ret);
+
+	return ret;
+}
+
+static int altr_a10sr_spi_remove(struct spi_device *spi)
+{
+	mfd_remove_devices(&spi->dev);
+
+	return 0;
+}
+
+static const struct of_device_id altr_a10sr_spi_of_match[] = {
+	{ .compatible = "altr,a10sr" },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, altr_a10sr_spi_of_match);
+
+static struct spi_driver altr_a10sr_spi_driver = {
+	.probe = altr_a10sr_spi_probe,
+	.remove = altr_a10sr_spi_remove,
+	.driver = {
+		.name = "altr_a10sr",
+		.of_match_table = of_match_ptr(altr_a10sr_spi_of_match),
+	},
+};
+
+module_spi_driver(altr_a10sr_spi_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Thor Thayer <tthayer@opensource.altera.com>");
+MODULE_DESCRIPTION("Altera Arria10 DevKit System Resource MFD Driver");
diff --git a/include/linux/mfd/altera-a10sr.h b/include/linux/mfd/altera-a10sr.h
new file mode 100644
index 0000000..c869fe7
--- /dev/null
+++ b/include/linux/mfd/altera-a10sr.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright Altera Corporation (C) 2014-2016. All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * Declarations for Altera Arria10 MAX5 System Resource Chip
+ *
+ * Adapted from DA9052
+ * Copyright(c) 2011 Dialog Semiconductor Ltd.
+ * Author: David Dajun Chen <dchen@diasemi.com>
+ */
+
+#ifndef __MFD_ALTERA_A10SR_H
+#define __MFD_ALTERA_A10SR_H
+
+#include <linux/completion.h>
+#include <linux/list.h>
+#include <linux/mfd/core.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+
+/* Write registers are always on even addresses */
+#define  WRITE_REG_MASK              0xFE
+/* Odd registers are always on odd addresses */
+#define  READ_REG_MASK               0x01
+
+#define ALTR_A10SR_BITS_PER_REGISTER  8
+/*
+ * To find the correct register, we divide the input GPIO by
+ * the number of GPIO in each register. We then need to multiply
+ * by 2 because the reads are at odd addresses.
+ */
+#define ALTR_A10SR_REG_OFFSET(X)     (((X) / ALTR_A10SR_BITS_PER_REGISTER) << 1)
+#define ALTR_A10SR_REG_BIT(X)        ((X) % ALTR_A10SR_BITS_PER_REGISTER)
+#define ALTR_A10SR_REG_BIT_CHG(X, Y) ((X) << ALTR_A10SR_REG_BIT(Y))
+#define ALTR_A10SR_REG_BIT_MASK(X)   (1 << ALTR_A10SR_REG_BIT(X))
+
+/* Arria10 System Controller Register Defines */
+#define ALTR_A10SR_NOP                0x00    /* No Change */
+#define ALTR_A10SR_VERSION_READ       0x00    /* MAX5 Version Read */
+
+#define ALTR_A10SR_LED_REG            0x02    /* LED - Upper 4 bits */
+/* LED register Bit Definitions */
+#define ALTR_A10SR_LED_VALID_SHIFT        4       /* LED - Upper 4 bits valid */
+#define ALTR_A10SR_OUT_VALID_RANGE_LO     ALTR_A10SR_LED_VALID_SHIFT
+#define ALTR_A10SR_OUT_VALID_RANGE_HI     7
+
+#define ALTR_A10SR_PBDSW_REG          0x04    /* PB & DIP SW - Input only */
+#define ALTR_A10SR_PBDSW_IRQ_REG      0x06    /* PB & DIP SW Flag Clear */
+/* Pushbutton & DIP Switch Bit Definitions */
+#define ALTR_A10SR_IN_VALID_RANGE_LO      8
+#define ALTR_A10SR_IN_VALID_RANGE_HI      15
+
+#define ALTR_A10SR_PWR_GOOD1_REG      0x08    /* Power Good1 Read */
+#define ALTR_A10SR_PWR_GOOD2_REG      0x0A    /* Power Good2 Read */
+#define ALTR_A10SR_PWR_GOOD3_REG      0x0C    /* Power Good3 Read */
+#define ALTR_A10SR_FMCAB_REG          0x0E    /* FMCA/B & PCIe Pwr Enable */
+#define ALTR_A10SR_HPS_RST_REG        0x10    /* HPS Reset */
+#define ALTR_A10SR_USB_QSPI_REG       0x12    /* USB, BQSPI, FILE Reset */
+#define ALTR_A10SR_SFPA_REG           0x14    /* SFPA Control Reg */
+#define ALTR_A10SR_SFPB_REG           0x16    /* SFPB Control Reg */
+#define ALTR_A10SR_I2C_M_REG          0x18    /* I2C Master Select */
+#define ALTR_A10SR_WARM_RST_REG       0x1A    /* HPS Warm Reset */
+#define ALTR_A10SR_WR_KEY_REG         0x1C    /* HPS Warm Reset Key */
+#define ALTR_A10SR_PMBUS_REG          0x1E    /* HPS PM Bus */
+
+/**
+ * struct altr_a10sr - Altera Max5 MFD device private data structure
+ * @dev:  : this device
+ * @regmap: the regmap assigned to the parent device.
+ */
+struct altr_a10sr {
+	struct device *dev;
+	struct regmap *regmap;
+};
+
+#endif /* __MFD_ALTERA_A10SR_H */
-- 
1.7.9.5

[PATCH 03/11] mfd: altr_a10sr: Add Altera Arria10 DevKit System Resource Chip

[tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx]

From: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>

Add support for the Altera Arria10 Development Kit System Resource
chip which is implemented using a MAX5 as a external gpio extender,
and power supply alarm (hwmon) with the regmap framework over a SPI bus.

Signed-off-by: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
---
 drivers/mfd/Kconfig              |   11 +++
 drivers/mfd/Makefile             |    2 +
 drivers/mfd/altera-a10sr.c       |  179 ++++++++++++++++++++++++++++++++++++++
 include/linux/mfd/altera-a10sr.h |   87 ++++++++++++++++++
 4 files changed, 279 insertions(+)
 create mode 100644 drivers/mfd/altera-a10sr.c
 create mode 100644 include/linux/mfd/altera-a10sr.h

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index eea61e3..4fc27c6 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -18,6 +18,17 @@ config MFD_CS5535
 	  This is the core driver for CS5535/CS5536 MFD functions.  This is
           necessary for using the board's GPIO and MFGPT functionality.
 
+config MFD_ALTERA_A10SR
+       bool "Altera Arria10 DevKit System Resource chip"
+       depends on ARCH_SOCFPGA && SPI_MASTER=y && OF
+       select REGMAP_SPI
+       select MFD_CORE
+       help
+         Support for the Altera Arria10 DevKit MAX5 System Resource chip
+         using the SPI interface. This driver provides common support for
+         accessing the external gpio extender (LEDs & buttons) and
+         power supply alarms (hwmon).
+
 config MFD_ACT8945A
 	tristate "Active-semi ACT8945A"
 	select MFD_CORE
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 5eaa6465d..4f1ff91 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -203,3 +203,5 @@ intel-soc-pmic-objs		:= intel_soc_pmic_core.o intel_soc_pmic_crc.o
 intel-soc-pmic-$(CONFIG_INTEL_PMC_IPC)	+= intel_soc_pmic_bxtwc.o
 obj-$(CONFIG_INTEL_SOC_PMIC)	+= intel-soc-pmic.o
 obj-$(CONFIG_MFD_MT6397)	+= mt6397-core.o
+
+obj-$(CONFIG_MFD_ALTERA_A10SR)	+= altera-a10sr.o
diff --git a/drivers/mfd/altera-a10sr.c b/drivers/mfd/altera-a10sr.c
new file mode 100644
index 0000000..2ff08e3
--- /dev/null
+++ b/drivers/mfd/altera-a10sr.c
@@ -0,0 +1,179 @@
+/*
+ * Copyright Altera Corporation (C) 2014-2016. All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * SPI access for Altera Arria10 MAX5 System Resource Chip
+ *
+ * Adapted from DA9052
+ * Copyright(c) 2011 Dialog Semiconductor Ltd.
+ * Author: David Dajun Chen <dchen-WBD+wuPFNBhBDgjK7y7TUQ@public.gmane.org>
+ */
+
+#include <linux/mfd/altera-a10sr.h>
+#include <linux/mfd/core.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/spi/spi.h>
+
+static const struct mfd_cell altr_a10sr_subdev_info[] = {
+	{
+		.name = "altr_a10sr_gpio",
+		.of_compatible = "altr,a10sr-gpio",
+	},
+};
+
+static bool altr_a10sr_reg_readable(struct device *dev, unsigned int reg)
+{
+	switch (reg) {
+	case ALTR_A10SR_VERSION_READ:
+	case ALTR_A10SR_LED_REG:
+	case ALTR_A10SR_PBDSW_REG:
+	case ALTR_A10SR_PBDSW_IRQ_REG:
+	case ALTR_A10SR_PWR_GOOD1_REG:
+	case ALTR_A10SR_PWR_GOOD2_REG:
+	case ALTR_A10SR_PWR_GOOD3_REG:
+	case ALTR_A10SR_FMCAB_REG:
+	case ALTR_A10SR_HPS_RST_REG:
+	case ALTR_A10SR_USB_QSPI_REG:
+	case ALTR_A10SR_SFPA_REG:
+	case ALTR_A10SR_SFPB_REG:
+	case ALTR_A10SR_I2C_M_REG:
+	case ALTR_A10SR_WARM_RST_REG:
+	case ALTR_A10SR_WR_KEY_REG:
+	case ALTR_A10SR_PMBUS_REG:
+		return true;
+	default:
+		return false;
+	}
+}
+
+static bool altr_a10sr_reg_writeable(struct device *dev, unsigned int reg)
+{
+	switch (reg) {
+	case ALTR_A10SR_LED_REG:
+	case ALTR_A10SR_PBDSW_IRQ_REG:
+	case ALTR_A10SR_FMCAB_REG:
+	case ALTR_A10SR_HPS_RST_REG:
+	case ALTR_A10SR_USB_QSPI_REG:
+	case ALTR_A10SR_SFPA_REG:
+	case ALTR_A10SR_SFPB_REG:
+	case ALTR_A10SR_WARM_RST_REG:
+	case ALTR_A10SR_WR_KEY_REG:
+	case ALTR_A10SR_PMBUS_REG:
+		return true;
+	default:
+		return false;
+	}
+}
+
+static bool altr_a10sr_reg_volatile(struct device *dev, unsigned int reg)
+{
+	switch (reg) {
+	case ALTR_A10SR_PBDSW_REG:
+	case ALTR_A10SR_PBDSW_IRQ_REG:
+	case ALTR_A10SR_PWR_GOOD1_REG:
+	case ALTR_A10SR_PWR_GOOD2_REG:
+	case ALTR_A10SR_PWR_GOOD3_REG:
+	case ALTR_A10SR_HPS_RST_REG:
+	case ALTR_A10SR_I2C_M_REG:
+	case ALTR_A10SR_WARM_RST_REG:
+	case ALTR_A10SR_WR_KEY_REG:
+	case ALTR_A10SR_PMBUS_REG:
+		return true;
+	default:
+		return false;
+	}
+}
+
+const struct regmap_config altr_a10sr_regmap_config = {
+	.reg_bits = 8,
+	.val_bits = 8,
+
+	.cache_type = REGCACHE_NONE,
+
+	.use_single_rw = true,
+	.read_flag_mask = 1,
+	.write_flag_mask = 0,
+
+	.max_register = ALTR_A10SR_WR_KEY_REG,
+	.readable_reg = altr_a10sr_reg_readable,
+	.writeable_reg = altr_a10sr_reg_writeable,
+	.volatile_reg = altr_a10sr_reg_volatile,
+
+};
+
+static int altr_a10sr_spi_probe(struct spi_device *spi)
+{
+	int ret;
+	struct altr_a10sr *a10sr;
+
+	a10sr = devm_kzalloc(&spi->dev, sizeof(*a10sr),
+			     GFP_KERNEL);
+	if (!a10sr)
+		return -ENOMEM;
+
+	spi->mode = SPI_MODE_3;
+	spi->bits_per_word = 8;
+	spi_setup(spi);
+
+	a10sr->dev = &spi->dev;
+
+	spi_set_drvdata(spi, a10sr);
+
+	a10sr->regmap = devm_regmap_init_spi(spi, &altr_a10sr_regmap_config);
+	if (IS_ERR(a10sr->regmap)) {
+		ret = PTR_ERR(a10sr->regmap);
+		dev_err(&spi->dev, "Failed to allocate register map: %d\n",
+			ret);
+		return ret;
+	}
+
+	ret = mfd_add_devices(a10sr->dev, PLATFORM_DEVID_AUTO,
+			      altr_a10sr_subdev_info,
+			      ARRAY_SIZE(altr_a10sr_subdev_info),
+			      NULL, 0, NULL);
+	if (ret)
+		dev_err(a10sr->dev, "Failed to register sub-devices: %d\n",
+			ret);
+
+	return ret;
+}
+
+static int altr_a10sr_spi_remove(struct spi_device *spi)
+{
+	mfd_remove_devices(&spi->dev);
+
+	return 0;
+}
+
+static const struct of_device_id altr_a10sr_spi_of_match[] = {
+	{ .compatible = "altr,a10sr" },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, altr_a10sr_spi_of_match);
+
+static struct spi_driver altr_a10sr_spi_driver = {
+	.probe = altr_a10sr_spi_probe,
+	.remove = altr_a10sr_spi_remove,
+	.driver = {
+		.name = "altr_a10sr",
+		.of_match_table = of_match_ptr(altr_a10sr_spi_of_match),
+	},
+};
+
+module_spi_driver(altr_a10sr_spi_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>");
+MODULE_DESCRIPTION("Altera Arria10 DevKit System Resource MFD Driver");
diff --git a/include/linux/mfd/altera-a10sr.h b/include/linux/mfd/altera-a10sr.h
new file mode 100644
index 0000000..c869fe7
--- /dev/null
+++ b/include/linux/mfd/altera-a10sr.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright Altera Corporation (C) 2014-2016. All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * Declarations for Altera Arria10 MAX5 System Resource Chip
+ *
+ * Adapted from DA9052
+ * Copyright(c) 2011 Dialog Semiconductor Ltd.
+ * Author: David Dajun Chen <dchen-WBD+wuPFNBhBDgjK7y7TUQ@public.gmane.org>
+ */
+
+#ifndef __MFD_ALTERA_A10SR_H
+#define __MFD_ALTERA_A10SR_H
+
+#include <linux/completion.h>
+#include <linux/list.h>
+#include <linux/mfd/core.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+
+/* Write registers are always on even addresses */
+#define  WRITE_REG_MASK              0xFE
+/* Odd registers are always on odd addresses */
+#define  READ_REG_MASK               0x01
+
+#define ALTR_A10SR_BITS_PER_REGISTER  8
+/*
+ * To find the correct register, we divide the input GPIO by
+ * the number of GPIO in each register. We then need to multiply
+ * by 2 because the reads are at odd addresses.
+ */
+#define ALTR_A10SR_REG_OFFSET(X)     (((X) / ALTR_A10SR_BITS_PER_REGISTER) << 1)
+#define ALTR_A10SR_REG_BIT(X)        ((X) % ALTR_A10SR_BITS_PER_REGISTER)
+#define ALTR_A10SR_REG_BIT_CHG(X, Y) ((X) << ALTR_A10SR_REG_BIT(Y))
+#define ALTR_A10SR_REG_BIT_MASK(X)   (1 << ALTR_A10SR_REG_BIT(X))
+
+/* Arria10 System Controller Register Defines */
+#define ALTR_A10SR_NOP                0x00    /* No Change */
+#define ALTR_A10SR_VERSION_READ       0x00    /* MAX5 Version Read */
+
+#define ALTR_A10SR_LED_REG            0x02    /* LED - Upper 4 bits */
+/* LED register Bit Definitions */
+#define ALTR_A10SR_LED_VALID_SHIFT        4       /* LED - Upper 4 bits valid */
+#define ALTR_A10SR_OUT_VALID_RANGE_LO     ALTR_A10SR_LED_VALID_SHIFT
+#define ALTR_A10SR_OUT_VALID_RANGE_HI     7
+
+#define ALTR_A10SR_PBDSW_REG          0x04    /* PB & DIP SW - Input only */
+#define ALTR_A10SR_PBDSW_IRQ_REG      0x06    /* PB & DIP SW Flag Clear */
+/* Pushbutton & DIP Switch Bit Definitions */
+#define ALTR_A10SR_IN_VALID_RANGE_LO      8
+#define ALTR_A10SR_IN_VALID_RANGE_HI      15
+
+#define ALTR_A10SR_PWR_GOOD1_REG      0x08    /* Power Good1 Read */
+#define ALTR_A10SR_PWR_GOOD2_REG      0x0A    /* Power Good2 Read */
+#define ALTR_A10SR_PWR_GOOD3_REG      0x0C    /* Power Good3 Read */
+#define ALTR_A10SR_FMCAB_REG          0x0E    /* FMCA/B & PCIe Pwr Enable */
+#define ALTR_A10SR_HPS_RST_REG        0x10    /* HPS Reset */
+#define ALTR_A10SR_USB_QSPI_REG       0x12    /* USB, BQSPI, FILE Reset */
+#define ALTR_A10SR_SFPA_REG           0x14    /* SFPA Control Reg */
+#define ALTR_A10SR_SFPB_REG           0x16    /* SFPB Control Reg */
+#define ALTR_A10SR_I2C_M_REG          0x18    /* I2C Master Select */
+#define ALTR_A10SR_WARM_RST_REG       0x1A    /* HPS Warm Reset */
+#define ALTR_A10SR_WR_KEY_REG         0x1C    /* HPS Warm Reset Key */
+#define ALTR_A10SR_PMBUS_REG          0x1E    /* HPS PM Bus */
+
+/**
+ * struct altr_a10sr - Altera Max5 MFD device private data structure
+ * @dev:  : this device
+ * @regmap: the regmap assigned to the parent device.
+ */
+struct altr_a10sr {
+	struct device *dev;
+	struct regmap *regmap;
+};
+
+#endif /* __MFD_ALTERA_A10SR_H */
-- 
1.7.9.5

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Re: [PATCH 03/11] mfd: altr_a10sr: Add Altera Arria10 DevKit System Resource Chip

[Lee Jones]

On Fri, 22 Apr 2016, tthayer@opensource.altera.com wrote:

> From: Thor Thayer <tthayer@opensource.altera.com>
> 
> Add support for the Altera Arria10 Development Kit System Resource
> chip which is implemented using a MAX5 as a external gpio extender,
> and power supply alarm (hwmon) with the regmap framework over a SPI bus.
> 
> Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
> ---
>  drivers/mfd/Kconfig              |   11 +++
>  drivers/mfd/Makefile             |    2 +
>  drivers/mfd/altera-a10sr.c       |  179 ++++++++++++++++++++++++++++++++++++++
>  include/linux/mfd/altera-a10sr.h |   87 ++++++++++++++++++
>  4 files changed, 279 insertions(+)
>  create mode 100644 drivers/mfd/altera-a10sr.c
>  create mode 100644 include/linux/mfd/altera-a10sr.h
> 
> diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
> index eea61e3..4fc27c6 100644
> --- a/drivers/mfd/Kconfig
> +++ b/drivers/mfd/Kconfig
> @@ -18,6 +18,17 @@ config MFD_CS5535
>  	  This is the core driver for CS5535/CS5536 MFD functions.  This is
>            necessary for using the board's GPIO and MFGPT functionality.
>  
> +config MFD_ALTERA_A10SR
> +       bool "Altera Arria10 DevKit System Resource chip"
> +       depends on ARCH_SOCFPGA && SPI_MASTER=y && OF
> +       select REGMAP_SPI
> +       select MFD_CORE
> +       help
> +         Support for the Altera Arria10 DevKit MAX5 System Resource chip
> +         using the SPI interface. This driver provides common support for
> +         accessing the external gpio extender (LEDs & buttons) and
> +         power supply alarms (hwmon).
> +
>  config MFD_ACT8945A
>  	tristate "Active-semi ACT8945A"
>  	select MFD_CORE
> diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
> index 5eaa6465d..4f1ff91 100644
> --- a/drivers/mfd/Makefile
> +++ b/drivers/mfd/Makefile
> @@ -203,3 +203,5 @@ intel-soc-pmic-objs		:= intel_soc_pmic_core.o intel_soc_pmic_crc.o
>  intel-soc-pmic-$(CONFIG_INTEL_PMC_IPC)	+= intel_soc_pmic_bxtwc.o
>  obj-$(CONFIG_INTEL_SOC_PMIC)	+= intel-soc-pmic.o
>  obj-$(CONFIG_MFD_MT6397)	+= mt6397-core.o
> +
> +obj-$(CONFIG_MFD_ALTERA_A10SR)	+= altera-a10sr.o
> diff --git a/drivers/mfd/altera-a10sr.c b/drivers/mfd/altera-a10sr.c
> new file mode 100644
> index 0000000..2ff08e3
> --- /dev/null
> +++ b/drivers/mfd/altera-a10sr.c
> @@ -0,0 +1,179 @@
> +/*
> + * Copyright Altera Corporation (C) 2014-2016. All Rights Reserved
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program.  If not, see <http://www.gnu.org/licenses/>.
> + *
> + * SPI access for Altera Arria10 MAX5 System Resource Chip
> + *
> + * Adapted from DA9052
> + * Copyright(c) 2011 Dialog Semiconductor Ltd.
> + * Author: David Dajun Chen <dchen@diasemi.com>

You don't need to carry the copyright or authorship tags over.

> + */
> +
> +#include <linux/mfd/altera-a10sr.h>
> +#include <linux/mfd/core.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/spi/spi.h>
> +
> +static const struct mfd_cell altr_a10sr_subdev_info[] = {
> +	{
> +		.name = "altr_a10sr_gpio",
> +		.of_compatible = "altr,a10sr-gpio",
> +	},
> +};
> +
> +static bool altr_a10sr_reg_readable(struct device *dev, unsigned int reg)
> +{
> +	switch (reg) {
> +	case ALTR_A10SR_VERSION_READ:
> +	case ALTR_A10SR_LED_REG:
> +	case ALTR_A10SR_PBDSW_REG:
> +	case ALTR_A10SR_PBDSW_IRQ_REG:
> +	case ALTR_A10SR_PWR_GOOD1_REG:
> +	case ALTR_A10SR_PWR_GOOD2_REG:
> +	case ALTR_A10SR_PWR_GOOD3_REG:
> +	case ALTR_A10SR_FMCAB_REG:
> +	case ALTR_A10SR_HPS_RST_REG:
> +	case ALTR_A10SR_USB_QSPI_REG:
> +	case ALTR_A10SR_SFPA_REG:
> +	case ALTR_A10SR_SFPB_REG:
> +	case ALTR_A10SR_I2C_M_REG:
> +	case ALTR_A10SR_WARM_RST_REG:
> +	case ALTR_A10SR_WR_KEY_REG:
> +	case ALTR_A10SR_PMBUS_REG:
> +		return true;
> +	default:
> +		return false;
> +	}
> +}
> +
> +static bool altr_a10sr_reg_writeable(struct device *dev, unsigned int reg)
> +{
> +	switch (reg) {
> +	case ALTR_A10SR_LED_REG:
> +	case ALTR_A10SR_PBDSW_IRQ_REG:
> +	case ALTR_A10SR_FMCAB_REG:
> +	case ALTR_A10SR_HPS_RST_REG:
> +	case ALTR_A10SR_USB_QSPI_REG:
> +	case ALTR_A10SR_SFPA_REG:
> +	case ALTR_A10SR_SFPB_REG:
> +	case ALTR_A10SR_WARM_RST_REG:
> +	case ALTR_A10SR_WR_KEY_REG:
> +	case ALTR_A10SR_PMBUS_REG:
> +		return true;
> +	default:
> +		return false;
> +	}
> +}
> +
> +static bool altr_a10sr_reg_volatile(struct device *dev, unsigned int reg)
> +{
> +	switch (reg) {
> +	case ALTR_A10SR_PBDSW_REG:
> +	case ALTR_A10SR_PBDSW_IRQ_REG:
> +	case ALTR_A10SR_PWR_GOOD1_REG:
> +	case ALTR_A10SR_PWR_GOOD2_REG:
> +	case ALTR_A10SR_PWR_GOOD3_REG:
> +	case ALTR_A10SR_HPS_RST_REG:
> +	case ALTR_A10SR_I2C_M_REG:
> +	case ALTR_A10SR_WARM_RST_REG:
> +	case ALTR_A10SR_WR_KEY_REG:
> +	case ALTR_A10SR_PMBUS_REG:
> +		return true;
> +	default:
> +		return false;
> +	}
> +}
> +
> +const struct regmap_config altr_a10sr_regmap_config = {
> +	.reg_bits = 8,
> +	.val_bits = 8,
> +
> +	.cache_type = REGCACHE_NONE,
> +
> +	.use_single_rw = true,
> +	.read_flag_mask = 1,
> +	.write_flag_mask = 0,
> +
> +	.max_register = ALTR_A10SR_WR_KEY_REG,
> +	.readable_reg = altr_a10sr_reg_readable,
> +	.writeable_reg = altr_a10sr_reg_writeable,
> +	.volatile_reg = altr_a10sr_reg_volatile,
> +
> +};
> +
> +static int altr_a10sr_spi_probe(struct spi_device *spi)
> +{
> +	int ret;
> +	struct altr_a10sr *a10sr;
> +
> +	a10sr = devm_kzalloc(&spi->dev, sizeof(*a10sr),
> +			     GFP_KERNEL);
> +	if (!a10sr)
> +		return -ENOMEM;
> +
> +	spi->mode = SPI_MODE_3;
> +	spi->bits_per_word = 8;
> +	spi_setup(spi);
> +
> +	a10sr->dev = &spi->dev;
> +
> +	spi_set_drvdata(spi, a10sr);
> +
> +	a10sr->regmap = devm_regmap_init_spi(spi, &altr_a10sr_regmap_config);
> +	if (IS_ERR(a10sr->regmap)) {
> +		ret = PTR_ERR(a10sr->regmap);
> +		dev_err(&spi->dev, "Failed to allocate register map: %d\n",
> +			ret);
> +		return ret;
> +	}

Is this regmap used it more than one driver?

> +	ret = mfd_add_devices(a10sr->dev, PLATFORM_DEVID_AUTO,
> +			      altr_a10sr_subdev_info,
> +			      ARRAY_SIZE(altr_a10sr_subdev_info),
> +			      NULL, 0, NULL);
> +	if (ret)
> +		dev_err(a10sr->dev, "Failed to register sub-devices: %d\n",
> +			ret);
> +
> +	return ret;
> +}
> +
> +static int altr_a10sr_spi_remove(struct spi_device *spi)
> +{
> +	mfd_remove_devices(&spi->dev);
> +
> +	return 0;
> +}

Use devm_mfd_add_devices() and remove this function.

> +static const struct of_device_id altr_a10sr_spi_of_match[] = {
> +	{ .compatible = "altr,a10sr" },
> +	{ },
> +};
> +MODULE_DEVICE_TABLE(of, altr_a10sr_spi_of_match);
> +
> +static struct spi_driver altr_a10sr_spi_driver = {
> +	.probe = altr_a10sr_spi_probe,
> +	.remove = altr_a10sr_spi_remove,

Remove .remove.

> +	.driver = {
> +		.name = "altr_a10sr",
> +		.of_match_table = of_match_ptr(altr_a10sr_spi_of_match),
> +	},
> +};
> +
> +module_spi_driver(altr_a10sr_spi_driver);
> +
> +MODULE_LICENSE("GPL v2");
> +MODULE_AUTHOR("Thor Thayer <tthayer@opensource.altera.com>");
> +MODULE_DESCRIPTION("Altera Arria10 DevKit System Resource MFD Driver");
> diff --git a/include/linux/mfd/altera-a10sr.h b/include/linux/mfd/altera-a10sr.h
> new file mode 100644
> index 0000000..c869fe7
> --- /dev/null
> +++ b/include/linux/mfd/altera-a10sr.h
> @@ -0,0 +1,87 @@
> +/*
> + * Copyright Altera Corporation (C) 2014-2016. All Rights Reserved
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program.  If not, see <http://www.gnu.org/licenses/>.
> + *
> + * Declarations for Altera Arria10 MAX5 System Resource Chip
> + *
> + * Adapted from DA9052
> + * Copyright(c) 2011 Dialog Semiconductor Ltd.
> + * Author: David Dajun Chen <dchen@diasemi.com>

Remove these two lines.

> + */
> +
> +#ifndef __MFD_ALTERA_A10SR_H
> +#define __MFD_ALTERA_A10SR_H
> +
> +#include <linux/completion.h>
> +#include <linux/list.h>
> +#include <linux/mfd/core.h>
> +#include <linux/regmap.h>
> +#include <linux/slab.h>
> +
> +/* Write registers are always on even addresses */
> +#define  WRITE_REG_MASK              0xFE
> +/* Odd registers are always on odd addresses */
> +#define  READ_REG_MASK               0x01
> +
> +#define ALTR_A10SR_BITS_PER_REGISTER  8
> +/*
> + * To find the correct register, we divide the input GPIO by
> + * the number of GPIO in each register. We then need to multiply
> + * by 2 because the reads are at odd addresses.
> + */
> +#define ALTR_A10SR_REG_OFFSET(X)     (((X) / ALTR_A10SR_BITS_PER_REGISTER) << 1)
> +#define ALTR_A10SR_REG_BIT(X)        ((X) % ALTR_A10SR_BITS_PER_REGISTER)
> +#define ALTR_A10SR_REG_BIT_CHG(X, Y) ((X) << ALTR_A10SR_REG_BIT(Y))
> +#define ALTR_A10SR_REG_BIT_MASK(X)   (1 << ALTR_A10SR_REG_BIT(X))
> +
> +/* Arria10 System Controller Register Defines */
> +#define ALTR_A10SR_NOP                0x00    /* No Change */
> +#define ALTR_A10SR_VERSION_READ       0x00    /* MAX5 Version Read */
> +
> +#define ALTR_A10SR_LED_REG            0x02    /* LED - Upper 4 bits */
> +/* LED register Bit Definitions */
> +#define ALTR_A10SR_LED_VALID_SHIFT        4       /* LED - Upper 4 bits valid */
> +#define ALTR_A10SR_OUT_VALID_RANGE_LO     ALTR_A10SR_LED_VALID_SHIFT
> +#define ALTR_A10SR_OUT_VALID_RANGE_HI     7
> +
> +#define ALTR_A10SR_PBDSW_REG          0x04    /* PB & DIP SW - Input only */
> +#define ALTR_A10SR_PBDSW_IRQ_REG      0x06    /* PB & DIP SW Flag Clear */
> +/* Pushbutton & DIP Switch Bit Definitions */
> +#define ALTR_A10SR_IN_VALID_RANGE_LO      8
> +#define ALTR_A10SR_IN_VALID_RANGE_HI      15
> +
> +#define ALTR_A10SR_PWR_GOOD1_REG      0x08    /* Power Good1 Read */
> +#define ALTR_A10SR_PWR_GOOD2_REG      0x0A    /* Power Good2 Read */
> +#define ALTR_A10SR_PWR_GOOD3_REG      0x0C    /* Power Good3 Read */
> +#define ALTR_A10SR_FMCAB_REG          0x0E    /* FMCA/B & PCIe Pwr Enable */
> +#define ALTR_A10SR_HPS_RST_REG        0x10    /* HPS Reset */
> +#define ALTR_A10SR_USB_QSPI_REG       0x12    /* USB, BQSPI, FILE Reset */
> +#define ALTR_A10SR_SFPA_REG           0x14    /* SFPA Control Reg */
> +#define ALTR_A10SR_SFPB_REG           0x16    /* SFPB Control Reg */
> +#define ALTR_A10SR_I2C_M_REG          0x18    /* I2C Master Select */
> +#define ALTR_A10SR_WARM_RST_REG       0x1A    /* HPS Warm Reset */
> +#define ALTR_A10SR_WR_KEY_REG         0x1C    /* HPS Warm Reset Key */
> +#define ALTR_A10SR_PMBUS_REG          0x1E    /* HPS PM Bus */
> +
> +/**
> + * struct altr_a10sr - Altera Max5 MFD device private data structure
> + * @dev:  : this device
> + * @regmap: the regmap assigned to the parent device.
> + */
> +struct altr_a10sr {
> +	struct device *dev;
> +	struct regmap *regmap;
> +};
> +
> +#endif /* __MFD_ALTERA_A10SR_H */

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
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Re: [PATCH 03/11] mfd: altr_a10sr: Add Altera Arria10 DevKit System Resource Chip

[Lee Jones]

On Fri, 22 Apr 2016, ttha...@opensource.altera.com wrote:

> From: Thor Thayer <ttha...@opensource.altera.com>
> 
> Add support for the Altera Arria10 Development Kit System Resource
> chip which is implemented using a MAX5 as a external gpio extender,
> and power supply alarm (hwmon) with the regmap framework over a SPI bus.
> 
> Signed-off-by: Thor Thayer <ttha...@opensource.altera.com>
> ---
>  drivers/mfd/Kconfig              |   11 +++
>  drivers/mfd/Makefile             |    2 +
>  drivers/mfd/altera-a10sr.c       |  179 
> ++++++++++++++++++++++++++++++++++++++
>  include/linux/mfd/altera-a10sr.h |   87 ++++++++++++++++++
>  4 files changed, 279 insertions(+)
>  create mode 100644 drivers/mfd/altera-a10sr.c
>  create mode 100644 include/linux/mfd/altera-a10sr.h
> 
> diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
> index eea61e3..4fc27c6 100644
> --- a/drivers/mfd/Kconfig
> +++ b/drivers/mfd/Kconfig
> @@ -18,6 +18,17 @@ config MFD_CS5535
>         This is the core driver for CS5535/CS5536 MFD functions.  This is
>            necessary for using the board's GPIO and MFGPT functionality.
>  
> +config MFD_ALTERA_A10SR
> +       bool "Altera Arria10 DevKit System Resource chip"
> +       depends on ARCH_SOCFPGA && SPI_MASTER=y && OF
> +       select REGMAP_SPI
> +       select MFD_CORE
> +       help
> +         Support for the Altera Arria10 DevKit MAX5 System Resource chip
> +         using the SPI interface. This driver provides common support for
> +         accessing the external gpio extender (LEDs & buttons) and
> +         power supply alarms (hwmon).
> +
>  config MFD_ACT8945A
>       tristate "Active-semi ACT8945A"
>       select MFD_CORE
> diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
> index 5eaa6465d..4f1ff91 100644
> --- a/drivers/mfd/Makefile
> +++ b/drivers/mfd/Makefile
> @@ -203,3 +203,5 @@ intel-soc-pmic-objs               := 
> intel_soc_pmic_core.o intel_soc_pmic_crc.o
>  intel-soc-pmic-$(CONFIG_INTEL_PMC_IPC)       += intel_soc_pmic_bxtwc.o
>  obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o
>  obj-$(CONFIG_MFD_MT6397)     += mt6397-core.o
> +
> +obj-$(CONFIG_MFD_ALTERA_A10SR)       += altera-a10sr.o
> diff --git a/drivers/mfd/altera-a10sr.c b/drivers/mfd/altera-a10sr.c
> new file mode 100644
> index 0000000..2ff08e3
> --- /dev/null
> +++ b/drivers/mfd/altera-a10sr.c
> @@ -0,0 +1,179 @@
> +/*
> + * Copyright Altera Corporation (C) 2014-2016. All Rights Reserved
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along 
> with
> + * this program.  If not, see <http://www.gnu.org/licenses/>.
> + *
> + * SPI access for Altera Arria10 MAX5 System Resource Chip
> + *
> + * Adapted from DA9052
> + * Copyright(c) 2011 Dialog Semiconductor Ltd.
> + * Author: David Dajun Chen <dc...@diasemi.com>

You don't need to carry the copyright or authorship tags over.

> + */
> +
> +#include <linux/mfd/altera-a10sr.h>
> +#include <linux/mfd/core.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/spi/spi.h>
> +
> +static const struct mfd_cell altr_a10sr_subdev_info[] = {
> +     {
> +             .name = "altr_a10sr_gpio",
> +             .of_compatible = "altr,a10sr-gpio",
> +     },
> +};
> +
> +static bool altr_a10sr_reg_readable(struct device *dev, unsigned int reg)
> +{
> +     switch (reg) {
> +     case ALTR_A10SR_VERSION_READ:
> +     case ALTR_A10SR_LED_REG:
> +     case ALTR_A10SR_PBDSW_REG:
> +     case ALTR_A10SR_PBDSW_IRQ_REG:
> +     case ALTR_A10SR_PWR_GOOD1_REG:
> +     case ALTR_A10SR_PWR_GOOD2_REG:
> +     case ALTR_A10SR_PWR_GOOD3_REG:
> +     case ALTR_A10SR_FMCAB_REG:
> +     case ALTR_A10SR_HPS_RST_REG:
> +     case ALTR_A10SR_USB_QSPI_REG:
> +     case ALTR_A10SR_SFPA_REG:
> +     case ALTR_A10SR_SFPB_REG:
> +     case ALTR_A10SR_I2C_M_REG:
> +     case ALTR_A10SR_WARM_RST_REG:
> +     case ALTR_A10SR_WR_KEY_REG:
> +     case ALTR_A10SR_PMBUS_REG:
> +             return true;
> +     default:
> +             return false;
> +     }
> +}
> +
> +static bool altr_a10sr_reg_writeable(struct device *dev, unsigned int reg)
> +{
> +     switch (reg) {
> +     case ALTR_A10SR_LED_REG:
> +     case ALTR_A10SR_PBDSW_IRQ_REG:
> +     case ALTR_A10SR_FMCAB_REG:
> +     case ALTR_A10SR_HPS_RST_REG:
> +     case ALTR_A10SR_USB_QSPI_REG:
> +     case ALTR_A10SR_SFPA_REG:
> +     case ALTR_A10SR_SFPB_REG:
> +     case ALTR_A10SR_WARM_RST_REG:
> +     case ALTR_A10SR_WR_KEY_REG:
> +     case ALTR_A10SR_PMBUS_REG:
> +             return true;
> +     default:
> +             return false;
> +     }
> +}
> +
> +static bool altr_a10sr_reg_volatile(struct device *dev, unsigned int reg)
> +{
> +     switch (reg) {
> +     case ALTR_A10SR_PBDSW_REG:
> +     case ALTR_A10SR_PBDSW_IRQ_REG:
> +     case ALTR_A10SR_PWR_GOOD1_REG:
> +     case ALTR_A10SR_PWR_GOOD2_REG:
> +     case ALTR_A10SR_PWR_GOOD3_REG:
> +     case ALTR_A10SR_HPS_RST_REG:
> +     case ALTR_A10SR_I2C_M_REG:
> +     case ALTR_A10SR_WARM_RST_REG:
> +     case ALTR_A10SR_WR_KEY_REG:
> +     case ALTR_A10SR_PMBUS_REG:
> +             return true;
> +     default:
> +             return false;
> +     }
> +}
> +
> +const struct regmap_config altr_a10sr_regmap_config = {
> +     .reg_bits = 8,
> +     .val_bits = 8,
> +
> +     .cache_type = REGCACHE_NONE,
> +
> +     .use_single_rw = true,
> +     .read_flag_mask = 1,
> +     .write_flag_mask = 0,
> +
> +     .max_register = ALTR_A10SR_WR_KEY_REG,
> +     .readable_reg = altr_a10sr_reg_readable,
> +     .writeable_reg = altr_a10sr_reg_writeable,
> +     .volatile_reg = altr_a10sr_reg_volatile,
> +
> +};
> +
> +static int altr_a10sr_spi_probe(struct spi_device *spi)
> +{
> +     int ret;
> +     struct altr_a10sr *a10sr;
> +
> +     a10sr = devm_kzalloc(&spi->dev, sizeof(*a10sr),
> +                          GFP_KERNEL);
> +     if (!a10sr)
> +             return -ENOMEM;
> +
> +     spi->mode = SPI_MODE_3;
> +     spi->bits_per_word = 8;
> +     spi_setup(spi);
> +
> +     a10sr->dev = &spi->dev;
> +
> +     spi_set_drvdata(spi, a10sr);
> +
> +     a10sr->regmap = devm_regmap_init_spi(spi, &altr_a10sr_regmap_config);
> +     if (IS_ERR(a10sr->regmap)) {
> +             ret = PTR_ERR(a10sr->regmap);
> +             dev_err(&spi->dev, "Failed to allocate register map: %d\n",
> +                     ret);
> +             return ret;
> +     }

Is this regmap used it more than one driver?

> +     ret = mfd_add_devices(a10sr->dev, PLATFORM_DEVID_AUTO,
> +                           altr_a10sr_subdev_info,
> +                           ARRAY_SIZE(altr_a10sr_subdev_info),
> +                           NULL, 0, NULL);
> +     if (ret)
> +             dev_err(a10sr->dev, "Failed to register sub-devices: %d\n",
> +                     ret);
> +
> +     return ret;
> +}
> +
> +static int altr_a10sr_spi_remove(struct spi_device *spi)
> +{
> +     mfd_remove_devices(&spi->dev);
> +
> +     return 0;
> +}

Use devm_mfd_add_devices() and remove this function.

> +static const struct of_device_id altr_a10sr_spi_of_match[] = {
> +     { .compatible = "altr,a10sr" },
> +     { },
> +};
> +MODULE_DEVICE_TABLE(of, altr_a10sr_spi_of_match);
> +
> +static struct spi_driver altr_a10sr_spi_driver = {
> +     .probe = altr_a10sr_spi_probe,
> +     .remove = altr_a10sr_spi_remove,

Remove .remove.

> +     .driver = {
> +             .name = "altr_a10sr",
> +             .of_match_table = of_match_ptr(altr_a10sr_spi_of_match),
> +     },
> +};
> +
> +module_spi_driver(altr_a10sr_spi_driver);
> +
> +MODULE_LICENSE("GPL v2");
> +MODULE_AUTHOR("Thor Thayer <ttha...@opensource.altera.com>");
> +MODULE_DESCRIPTION("Altera Arria10 DevKit System Resource MFD Driver");
> diff --git a/include/linux/mfd/altera-a10sr.h 
> b/include/linux/mfd/altera-a10sr.h
> new file mode 100644
> index 0000000..c869fe7
> --- /dev/null
> +++ b/include/linux/mfd/altera-a10sr.h
> @@ -0,0 +1,87 @@
> +/*
> + * Copyright Altera Corporation (C) 2014-2016. All Rights Reserved
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along 
> with
> + * this program.  If not, see <http://www.gnu.org/licenses/>.
> + *
> + * Declarations for Altera Arria10 MAX5 System Resource Chip
> + *
> + * Adapted from DA9052
> + * Copyright(c) 2011 Dialog Semiconductor Ltd.
> + * Author: David Dajun Chen <dc...@diasemi.com>

Remove these two lines.

> + */
> +
> +#ifndef __MFD_ALTERA_A10SR_H
> +#define __MFD_ALTERA_A10SR_H
> +
> +#include <linux/completion.h>
> +#include <linux/list.h>
> +#include <linux/mfd/core.h>
> +#include <linux/regmap.h>
> +#include <linux/slab.h>
> +
> +/* Write registers are always on even addresses */
> +#define  WRITE_REG_MASK              0xFE
> +/* Odd registers are always on odd addresses */
> +#define  READ_REG_MASK               0x01
> +
> +#define ALTR_A10SR_BITS_PER_REGISTER  8
> +/*
> + * To find the correct register, we divide the input GPIO by
> + * the number of GPIO in each register. We then need to multiply
> + * by 2 because the reads are at odd addresses.
> + */
> +#define ALTR_A10SR_REG_OFFSET(X)     (((X) / ALTR_A10SR_BITS_PER_REGISTER) 
> << 1)
> +#define ALTR_A10SR_REG_BIT(X)        ((X) % ALTR_A10SR_BITS_PER_REGISTER)
> +#define ALTR_A10SR_REG_BIT_CHG(X, Y) ((X) << ALTR_A10SR_REG_BIT(Y))
> +#define ALTR_A10SR_REG_BIT_MASK(X)   (1 << ALTR_A10SR_REG_BIT(X))
> +
> +/* Arria10 System Controller Register Defines */
> +#define ALTR_A10SR_NOP                0x00    /* No Change */
> +#define ALTR_A10SR_VERSION_READ       0x00    /* MAX5 Version Read */
> +
> +#define ALTR_A10SR_LED_REG            0x02    /* LED - Upper 4 bits */
> +/* LED register Bit Definitions */
> +#define ALTR_A10SR_LED_VALID_SHIFT        4       /* LED - Upper 4 bits 
> valid */
> +#define ALTR_A10SR_OUT_VALID_RANGE_LO     ALTR_A10SR_LED_VALID_SHIFT
> +#define ALTR_A10SR_OUT_VALID_RANGE_HI     7
> +
> +#define ALTR_A10SR_PBDSW_REG          0x04    /* PB & DIP SW - Input only */
> +#define ALTR_A10SR_PBDSW_IRQ_REG      0x06    /* PB & DIP SW Flag Clear */
> +/* Pushbutton & DIP Switch Bit Definitions */
> +#define ALTR_A10SR_IN_VALID_RANGE_LO      8
> +#define ALTR_A10SR_IN_VALID_RANGE_HI      15
> +
> +#define ALTR_A10SR_PWR_GOOD1_REG      0x08    /* Power Good1 Read */
> +#define ALTR_A10SR_PWR_GOOD2_REG      0x0A    /* Power Good2 Read */
> +#define ALTR_A10SR_PWR_GOOD3_REG      0x0C    /* Power Good3 Read */
> +#define ALTR_A10SR_FMCAB_REG          0x0E    /* FMCA/B & PCIe Pwr Enable */
> +#define ALTR_A10SR_HPS_RST_REG        0x10    /* HPS Reset */
> +#define ALTR_A10SR_USB_QSPI_REG       0x12    /* USB, BQSPI, FILE Reset */
> +#define ALTR_A10SR_SFPA_REG           0x14    /* SFPA Control Reg */
> +#define ALTR_A10SR_SFPB_REG           0x16    /* SFPB Control Reg */
> +#define ALTR_A10SR_I2C_M_REG          0x18    /* I2C Master Select */
> +#define ALTR_A10SR_WARM_RST_REG       0x1A    /* HPS Warm Reset */
> +#define ALTR_A10SR_WR_KEY_REG         0x1C    /* HPS Warm Reset Key */
> +#define ALTR_A10SR_PMBUS_REG          0x1E    /* HPS PM Bus */
> +
> +/**
> + * struct altr_a10sr - Altera Max5 MFD device private data structure
> + * @dev:  : this device
> + * @regmap: the regmap assigned to the parent device.
> + */
> +struct altr_a10sr {
> +     struct device *dev;
> +     struct regmap *regmap;
> +};
> +
> +#endif /* __MFD_ALTERA_A10SR_H */

-- 
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Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
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[PATCH 04/11] gpio: altera-a10sr: Add A10 System Resource Chip GPIO support.

[tthayer]

From: Thor Thayer <tthayer@opensource.altera.com>

Add the GPIO functionality for the Altera Arria10 MAX5 System Resource
Chip. The A10 MAX5 has 12 bits of GPIO assigned to switches, buttons,
and LEDs as a GPIO extender on the SPI bus.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
 drivers/gpio/Kconfig             |    8 +++
 drivers/gpio/Makefile            |    1 +
 drivers/gpio/gpio-altera-a10sr.c |  140 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 149 insertions(+)
 create mode 100644 drivers/gpio/gpio-altera-a10sr.c

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 37f0378..66c8789 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -775,6 +775,14 @@ config GPIO_ADP5520
 	  This option enables support for on-chip GPIO found
 	  on Analog Devices ADP5520 PMICs.
 
+config GPIO_ALTERA_A10SR
+	tristate "Altera Arria10 System Resource GPIO"
+	depends on MFD_ALTERA_A10SR
+	help
+	  Driver for Arria10 Development Kit GPIO expansion which
+	  includes reads of pushbuttons and DIP switches as well
+	  as writes to LEDs.
+
 config GPIO_ARIZONA
 	tristate "Wolfson Microelectronics Arizona class devices"
 	depends on MFD_ARIZONA
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 40ab913..410e981 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_GPIO_ADNP)		+= gpio-adnp.o
 obj-$(CONFIG_GPIO_ADP5520)	+= gpio-adp5520.o
 obj-$(CONFIG_GPIO_ADP5588)	+= gpio-adp5588.o
 obj-$(CONFIG_GPIO_ALTERA)  	+= gpio-altera.o
+obj-$(CONFIG_GPIO_ALTERA_A10SR)	+= gpio-altera-a10sr.o
 obj-$(CONFIG_GPIO_AMD8111)	+= gpio-amd8111.o
 obj-$(CONFIG_GPIO_AMDPT)	+= gpio-amdpt.o
 obj-$(CONFIG_GPIO_ARIZONA)	+= gpio-arizona.o
diff --git a/drivers/gpio/gpio-altera-a10sr.c b/drivers/gpio/gpio-altera-a10sr.c
new file mode 100644
index 0000000..a65fbe6
--- /dev/null
+++ b/drivers/gpio/gpio-altera-a10sr.c
@@ -0,0 +1,140 @@
+/*
+ *  Copyright Altera Corporation (C) 2014-2016. All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * GPIO driver for  Altera Arria10 MAX5 System Resource Chip
+ *
+ * Adapted from gpio-tps65910.c
+ */
+
+#include <linux/gpio/driver.h>
+#include <linux/mfd/altera-a10sr.h>
+#include <linux/module.h>
+
+/**
+ * struct altr_a10sr_gpio - Altera Max5 GPIO device private data structure
+ * @gp:   : instance of the gpio_chip
+ * @regmap: the regmap from the parent device.
+ */
+struct altr_a10sr_gpio {
+	struct gpio_chip gp;
+	struct regmap *regmap;
+};
+
+static int altr_a10sr_gpio_get(struct gpio_chip *chip, unsigned int offset)
+{
+	struct altr_a10sr_gpio *gpio = gpiochip_get_data(chip);
+	int ret, val;
+
+	ret = regmap_read(gpio->regmap, ALTR_A10SR_PBDSW_REG, &val);
+	if (ret < 0)
+		return ret;
+
+	return !!(val & BIT(offset - ALTR_A10SR_LED_VALID_SHIFT));
+}
+
+static void altr_a10sr_gpio_set(struct gpio_chip *chip, unsigned int offset,
+				int value)
+{
+	struct altr_a10sr_gpio *gpio = gpiochip_get_data(chip);
+
+	regmap_update_bits(gpio->regmap, ALTR_A10SR_LED_REG,
+			   BIT(ALTR_A10SR_LED_VALID_SHIFT + offset),
+			   value ? BIT(ALTR_A10SR_LED_VALID_SHIFT + offset)
+			   : 0);
+}
+
+static int altr_a10sr_gpio_direction_input(struct gpio_chip *gc,
+					   unsigned int nr)
+{
+	if (nr >= (ALTR_A10SR_IN_VALID_RANGE_LO - ALTR_A10SR_LED_VALID_SHIFT))
+		return 0;
+	return -EINVAL;
+}
+
+static int altr_a10sr_gpio_direction_output(struct gpio_chip *gc,
+					    unsigned int nr, int value)
+{
+	if (nr <= (ALTR_A10SR_OUT_VALID_RANGE_HI - ALTR_A10SR_LED_VALID_SHIFT))
+		return 0;
+	return -EINVAL;
+}
+
+static struct gpio_chip altr_a10sr_gc = {
+	.label = "altr_a10sr_gpio",
+	.owner = THIS_MODULE,
+	.get = altr_a10sr_gpio_get,
+	.set = altr_a10sr_gpio_set,
+	.direction_input = altr_a10sr_gpio_direction_input,
+	.direction_output = altr_a10sr_gpio_direction_output,
+	.can_sleep = true,
+	.ngpio = 12,
+	.base = -1,
+};
+
+static int altr_a10sr_gpio_probe(struct platform_device *pdev)
+{
+	struct altr_a10sr_gpio *gpio;
+	int ret;
+	struct altr_a10sr *a10sr = dev_get_drvdata(pdev->dev.parent);
+
+	gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
+	if (!gpio)
+		return -ENOMEM;
+
+	gpio->regmap = a10sr->regmap;
+
+	gpio->gp = altr_a10sr_gc;
+
+	gpio->gp.of_node = pdev->dev.of_node;
+
+	ret = devm_gpiochip_add_data(&pdev->dev, &gpio->gp, gpio);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "Could not register gpiochip, %d\n", ret);
+		return ret;
+	}
+
+	platform_set_drvdata(pdev, gpio);
+
+	return 0;
+}
+
+static int altr_a10sr_gpio_remove(struct platform_device *pdev)
+{
+	struct altr_a10sr_gpio *gpio = platform_get_drvdata(pdev);
+
+	gpiochip_remove(&gpio->gp);
+
+	return 0;
+}
+
+static const struct of_device_id altr_a10sr_gpio_of_match[] = {
+	{ .compatible = "altr,a10sr-gpio" },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, altr_a10sr_gpio_of_match);
+
+static struct platform_driver altr_a10sr_gpio_driver = {
+	.probe = altr_a10sr_gpio_probe,
+	.remove = altr_a10sr_gpio_remove,
+	.driver = {
+		.name	= "altr_a10sr_gpio",
+		.of_match_table = of_match_ptr(altr_a10sr_gpio_of_match),
+	},
+};
+module_platform_driver(altr_a10sr_gpio_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Thor Thayer <tthayer@opensource.altera.com>");
+MODULE_DESCRIPTION("Altera Arria10 System Resource Chip GPIO");
-- 
1.7.9.5

[PATCH 04/11] gpio: altera-a10sr: Add A10 System Resource Chip GPIO support.

[tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx]

From: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>

Add the GPIO functionality for the Altera Arria10 MAX5 System Resource
Chip. The A10 MAX5 has 12 bits of GPIO assigned to switches, buttons,
and LEDs as a GPIO extender on the SPI bus.

Signed-off-by: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
---
 drivers/gpio/Kconfig             |    8 +++
 drivers/gpio/Makefile            |    1 +
 drivers/gpio/gpio-altera-a10sr.c |  140 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 149 insertions(+)
 create mode 100644 drivers/gpio/gpio-altera-a10sr.c

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 37f0378..66c8789 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -775,6 +775,14 @@ config GPIO_ADP5520
 	  This option enables support for on-chip GPIO found
 	  on Analog Devices ADP5520 PMICs.
 
+config GPIO_ALTERA_A10SR
+	tristate "Altera Arria10 System Resource GPIO"
+	depends on MFD_ALTERA_A10SR
+	help
+	  Driver for Arria10 Development Kit GPIO expansion which
+	  includes reads of pushbuttons and DIP switches as well
+	  as writes to LEDs.
+
 config GPIO_ARIZONA
 	tristate "Wolfson Microelectronics Arizona class devices"
 	depends on MFD_ARIZONA
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 40ab913..410e981 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_GPIO_ADNP)		+= gpio-adnp.o
 obj-$(CONFIG_GPIO_ADP5520)	+= gpio-adp5520.o
 obj-$(CONFIG_GPIO_ADP5588)	+= gpio-adp5588.o
 obj-$(CONFIG_GPIO_ALTERA)  	+= gpio-altera.o
+obj-$(CONFIG_GPIO_ALTERA_A10SR)	+= gpio-altera-a10sr.o
 obj-$(CONFIG_GPIO_AMD8111)	+= gpio-amd8111.o
 obj-$(CONFIG_GPIO_AMDPT)	+= gpio-amdpt.o
 obj-$(CONFIG_GPIO_ARIZONA)	+= gpio-arizona.o
diff --git a/drivers/gpio/gpio-altera-a10sr.c b/drivers/gpio/gpio-altera-a10sr.c
new file mode 100644
index 0000000..a65fbe6
--- /dev/null
+++ b/drivers/gpio/gpio-altera-a10sr.c
@@ -0,0 +1,140 @@
+/*
+ *  Copyright Altera Corporation (C) 2014-2016. All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * GPIO driver for  Altera Arria10 MAX5 System Resource Chip
+ *
+ * Adapted from gpio-tps65910.c
+ */
+
+#include <linux/gpio/driver.h>
+#include <linux/mfd/altera-a10sr.h>
+#include <linux/module.h>
+
+/**
+ * struct altr_a10sr_gpio - Altera Max5 GPIO device private data structure
+ * @gp:   : instance of the gpio_chip
+ * @regmap: the regmap from the parent device.
+ */
+struct altr_a10sr_gpio {
+	struct gpio_chip gp;
+	struct regmap *regmap;
+};
+
+static int altr_a10sr_gpio_get(struct gpio_chip *chip, unsigned int offset)
+{
+	struct altr_a10sr_gpio *gpio = gpiochip_get_data(chip);
+	int ret, val;
+
+	ret = regmap_read(gpio->regmap, ALTR_A10SR_PBDSW_REG, &val);
+	if (ret < 0)
+		return ret;
+
+	return !!(val & BIT(offset - ALTR_A10SR_LED_VALID_SHIFT));
+}
+
+static void altr_a10sr_gpio_set(struct gpio_chip *chip, unsigned int offset,
+				int value)
+{
+	struct altr_a10sr_gpio *gpio = gpiochip_get_data(chip);
+
+	regmap_update_bits(gpio->regmap, ALTR_A10SR_LED_REG,
+			   BIT(ALTR_A10SR_LED_VALID_SHIFT + offset),
+			   value ? BIT(ALTR_A10SR_LED_VALID_SHIFT + offset)
+			   : 0);
+}
+
+static int altr_a10sr_gpio_direction_input(struct gpio_chip *gc,
+					   unsigned int nr)
+{
+	if (nr >= (ALTR_A10SR_IN_VALID_RANGE_LO - ALTR_A10SR_LED_VALID_SHIFT))
+		return 0;
+	return -EINVAL;
+}
+
+static int altr_a10sr_gpio_direction_output(struct gpio_chip *gc,
+					    unsigned int nr, int value)
+{
+	if (nr <= (ALTR_A10SR_OUT_VALID_RANGE_HI - ALTR_A10SR_LED_VALID_SHIFT))
+		return 0;
+	return -EINVAL;
+}
+
+static struct gpio_chip altr_a10sr_gc = {
+	.label = "altr_a10sr_gpio",
+	.owner = THIS_MODULE,
+	.get = altr_a10sr_gpio_get,
+	.set = altr_a10sr_gpio_set,
+	.direction_input = altr_a10sr_gpio_direction_input,
+	.direction_output = altr_a10sr_gpio_direction_output,
+	.can_sleep = true,
+	.ngpio = 12,
+	.base = -1,
+};
+
+static int altr_a10sr_gpio_probe(struct platform_device *pdev)
+{
+	struct altr_a10sr_gpio *gpio;
+	int ret;
+	struct altr_a10sr *a10sr = dev_get_drvdata(pdev->dev.parent);
+
+	gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
+	if (!gpio)
+		return -ENOMEM;
+
+	gpio->regmap = a10sr->regmap;
+
+	gpio->gp = altr_a10sr_gc;
+
+	gpio->gp.of_node = pdev->dev.of_node;
+
+	ret = devm_gpiochip_add_data(&pdev->dev, &gpio->gp, gpio);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "Could not register gpiochip, %d\n", ret);
+		return ret;
+	}
+
+	platform_set_drvdata(pdev, gpio);
+
+	return 0;
+}
+
+static int altr_a10sr_gpio_remove(struct platform_device *pdev)
+{
+	struct altr_a10sr_gpio *gpio = platform_get_drvdata(pdev);
+
+	gpiochip_remove(&gpio->gp);
+
+	return 0;
+}
+
+static const struct of_device_id altr_a10sr_gpio_of_match[] = {
+	{ .compatible = "altr,a10sr-gpio" },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, altr_a10sr_gpio_of_match);
+
+static struct platform_driver altr_a10sr_gpio_driver = {
+	.probe = altr_a10sr_gpio_probe,
+	.remove = altr_a10sr_gpio_remove,
+	.driver = {
+		.name	= "altr_a10sr_gpio",
+		.of_match_table = of_match_ptr(altr_a10sr_gpio_of_match),
+	},
+};
+module_platform_driver(altr_a10sr_gpio_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>");
+MODULE_DESCRIPTION("Altera Arria10 System Resource Chip GPIO");
-- 
1.7.9.5

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Re: [PATCH 04/11] gpio: altera-a10sr: Add A10 System Resource Chip GPIO support.

[Linus Walleij]

On Fri, Apr 22, 2016 at 5:33 PM,  <tthayer@opensource.altera.com> wrote:

> From: Thor Thayer <tthayer@opensource.altera.com>
>
> Add the GPIO functionality for the Altera Arria10 MAX5 System Resource
> Chip. The A10 MAX5 has 12 bits of GPIO assigned to switches, buttons,
> and LEDs as a GPIO extender on the SPI bus.
>
> Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>

Acked-by: Linus Walleij <linus.walleij@linaro.org>

Lee feel free to queue this.

Yours,
Linus Walleij

Re: [PATCH 04/11] gpio: altera-a10sr: Add A10 System Resource Chip GPIO support.

[Linus Walleij]

On Fri, Apr 22, 2016 at 5:33 PM,  <ttha...@opensource.altera.com> wrote:

> From: Thor Thayer <ttha...@opensource.altera.com>
>
> Add the GPIO functionality for the Altera Arria10 MAX5 System Resource
> Chip. The A10 MAX5 has 12 bits of GPIO assigned to switches, buttons,
> and LEDs as a GPIO extender on the SPI bus.
>
> Signed-off-by: Thor Thayer <ttha...@opensource.altera.com>

Acked-by: Linus Walleij <linus.wall...@linaro.org>

Lee feel free to queue this.

Yours,
Linus Walleij
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[PATCH 05/11] ARM: socfpga: dts: Add SPI Master1 for Arria10 System Resource chip

[tthayer]

From: Thor Thayer <tthayer@opensource.altera.com>

Add the Altera Arria10 SPI Master Node in preparation for the A10SR
MFD node.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
 arch/arm/boot/dts/socfpga_arria10.dtsi |   15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index 17e81dc..e7b6c4a 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -567,6 +567,21 @@
 			status = "disabled";
 		};
 
+		spi1: spi@ffda5000 {
+			compatible = "snps,dw-apb-ssi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xffda5000 0x100>;
+			interrupts = <0 102 4>;
+			num-chipselect = <4>;
+			bus-num = <0>;
+			/*32bit_access;*/
+			tx-dma-channel = <&pdma 16>;
+			rx-dma-channel = <&pdma 17>;
+			clocks = <&spi_m_clk>;
+			status = "disabled";
+		};
+
 		sdr: sdr@ffc25000 {
 			compatible = "syscon";
 			reg = <0xffcfb100 0x80>;
-- 
1.7.9.5

[PATCH 05/11] ARM: socfpga: dts: Add SPI Master1 for Arria10 System Resource chip

[tthayer]

From: Thor Thayer <tthayer@opensource.altera.com>

Add the Altera Arria10 SPI Master Node in preparation for the A10SR
MFD node.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
 arch/arm/boot/dts/socfpga_arria10.dtsi |   15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index 17e81dc..e7b6c4a 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -567,6 +567,21 @@
 			status = "disabled";
 		};
 
+		spi1: spi@ffda5000 {
+			compatible = "snps,dw-apb-ssi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xffda5000 0x100>;
+			interrupts = <0 102 4>;
+			num-chipselect = <4>;
+			bus-num = <0>;
+			/*32bit_access;*/
+			tx-dma-channel = <&pdma 16>;
+			rx-dma-channel = <&pdma 17>;
+			clocks = <&spi_m_clk>;
+			status = "disabled";
+		};
+
 		sdr: sdr@ffc25000 {
 			compatible = "syscon";
 			reg = <0xffcfb100 0x80>;
-- 
1.7.9.5

[PATCH 06/11] ARM: socfpga: dts: Add Devkit A10-SR fields for Arria10

[tthayer]

From: Thor Thayer <tthayer@opensource.altera.com>

Add the Altera Arria10 System Resource node. This is a Multi-Function
device with GPIO expander support.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
 arch/arm/boot/dts/socfpga_arria10_socdk.dtsi |   16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
index 567df98..9eb1e3e 100644
--- a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
@@ -70,6 +70,22 @@
 	status = "okay";
 };
 
+&spi1 {
+	status = "okay";
+
+	resource-manager@0 {
+		compatible = "altr,a10sr";
+		reg = <0>;
+		spi-max-frequency = <100000>;
+
+		a10sr_gpio: gpio-controller {
+			compatible = "altr,a10sr-gpio";
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+	};
+};
+
 &i2c1 {
 	speed-mode = <0>;
 	status = "okay";
-- 
1.7.9.5

[PATCH 06/11] ARM: socfpga: dts: Add Devkit A10-SR fields for Arria10

[tthayer]

From: Thor Thayer <tthayer@opensource.altera.com>

Add the Altera Arria10 System Resource node. This is a Multi-Function
device with GPIO expander support.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
 arch/arm/boot/dts/socfpga_arria10_socdk.dtsi |   16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
index 567df98..9eb1e3e 100644
--- a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
@@ -70,6 +70,22 @@
 	status = "okay";
 };
 
+&spi1 {
+	status = "okay";
+
+	resource-manager@0 {
+		compatible = "altr,a10sr";
+		reg = <0>;
+		spi-max-frequency = <100000>;
+
+		a10sr_gpio: gpio-controller {
+			compatible = "altr,a10sr-gpio";
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+	};
+};
+
 &i2c1 {
 	speed-mode = <0>;
 	status = "okay";
-- 
1.7.9.5

[PATCH 07/11] ARM: socfpga: dts: Add LED framework to A10-SR GPIO

[tthayer]

From: Thor Thayer <tthayer@opensource.altera.com>

Add the LED framework to the Arria10 System Resource chip GPIO hooks.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
 arch/arm/boot/dts/socfpga_arria10_socdk.dtsi |   24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
index 9eb1e3e..e2addf9 100644
--- a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
@@ -31,6 +31,30 @@
 		reg = <0x0 0x40000000>; /* 1GB */
 	};
 
+	a10leds {
+		compatible = "gpio-leds";
+
+		a10sr_led0 {
+			label = "a10sr-led0";
+			gpios = <&a10sr_gpio 0 1>;
+		};
+
+		a10sr_led1 {
+			label = "a10sr-led1";
+			gpios = <&a10sr_gpio 1 1>;
+		};
+
+		a10sr_led2 {
+			label = "a10sr-led2";
+			gpios = <&a10sr_gpio 2 1>;
+		};
+
+		a10sr_led3 {
+			label = "a10sr-led3";
+			gpios = <&a10sr_gpio 3 1>;
+		};
+	};
+
 	soc {
 		clkmgr@ffd04000 {
 			clocks {
-- 
1.7.9.5

[PATCH 07/11] ARM: socfpga: dts: Add LED framework to A10-SR GPIO

[tthayer]

From: Thor Thayer <tthayer@opensource.altera.com>

Add the LED framework to the Arria10 System Resource chip GPIO hooks.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
 arch/arm/boot/dts/socfpga_arria10_socdk.dtsi |   24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
index 9eb1e3e..e2addf9 100644
--- a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
@@ -31,6 +31,30 @@
 		reg = <0x0 0x40000000>; /* 1GB */
 	};
 
+	a10leds {
+		compatible = "gpio-leds";
+
+		a10sr_led0 {
+			label = "a10sr-led0";
+			gpios = <&a10sr_gpio 0 1>;
+		};
+
+		a10sr_led1 {
+			label = "a10sr-led1";
+			gpios = <&a10sr_gpio 1 1>;
+		};
+
+		a10sr_led2 {
+			label = "a10sr-led2";
+			gpios = <&a10sr_gpio 2 1>;
+		};
+
+		a10sr_led3 {
+			label = "a10sr-led3";
+			gpios = <&a10sr_gpio 3 1>;
+		};
+	};
+
 	soc {
 		clkmgr@ffd04000 {
 			clocks {
-- 
1.7.9.5

[PATCH 08/11] dt-bindings: mfd: Add Altera A10-SR power supply alarm

[tthayer]

From: Thor Thayer <tthayer@opensource.altera.com>

Add power supply alarm from the hwmon framework.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
 .../devicetree/bindings/mfd/altera-a10sr.txt       |    8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/mfd/altera-a10sr.txt b/Documentation/devicetree/bindings/mfd/altera-a10sr.txt
index 8e17d05..75c51ab 100644
--- a/Documentation/devicetree/bindings/mfd/altera-a10sr.txt
+++ b/Documentation/devicetree/bindings/mfd/altera-a10sr.txt
@@ -11,6 +11,7 @@ The A10SR consists of this varied group of sub-devices:
 Device                   Description
 ------                   ----------
 a10sr_gpio               GPIO Controller
+ps_alarm                 Power Supply Alarms
 
 Arria10 GPIO
 Required Properties:
@@ -20,6 +21,9 @@ Required Properties:
                       the second cell is used to specify flags.
                       See ../gpio/gpio.txt for more information.
 
+Arria10 Power Supply Alarms
+- compatible        : Should be "altr,a10sr-hwmon"
+
 Example:
 
         resource-manager@0 {
@@ -32,4 +36,8 @@ Example:
 			gpio-controller;
 			#gpio-cells = <2>;
 		};
+
+		ps_alarm {
+			compatible = "altr,a10sr-hwmon";
+		};
 	};
-- 
1.7.9.5

[PATCH 08/11] dt-bindings: mfd: Add Altera A10-SR power supply alarm

[tthayer]

From: Thor Thayer <tthayer@opensource.altera.com>

Add power supply alarm from the hwmon framework.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
 .../devicetree/bindings/mfd/altera-a10sr.txt       |    8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/mfd/altera-a10sr.txt b/Documentation/devicetree/bindings/mfd/altera-a10sr.txt
index 8e17d05..75c51ab 100644
--- a/Documentation/devicetree/bindings/mfd/altera-a10sr.txt
+++ b/Documentation/devicetree/bindings/mfd/altera-a10sr.txt
@@ -11,6 +11,7 @@ The A10SR consists of this varied group of sub-devices:
 Device                   Description
 ------                   ----------
 a10sr_gpio               GPIO Controller
+ps_alarm                 Power Supply Alarms
 
 Arria10 GPIO
 Required Properties:
@@ -20,6 +21,9 @@ Required Properties:
                       the second cell is used to specify flags.
                       See ../gpio/gpio.txt for more information.
 
+Arria10 Power Supply Alarms
+- compatible        : Should be "altr,a10sr-hwmon"
+
 Example:
 
         resource-manager@0 {
@@ -32,4 +36,8 @@ Example:
 			gpio-controller;
 			#gpio-cells = <2>;
 		};
+
+		ps_alarm {
+			compatible = "altr,a10sr-hwmon";
+		};
 	};
-- 
1.7.9.5

Re: [PATCH 08/11] dt-bindings: mfd: Add Altera A10-SR power supply alarm

[Rob Herring]

On Fri, Apr 22, 2016 at 10:33:36AM -0500, tthayer@opensource.altera.com wrote:
> From: Thor Thayer <tthayer@opensource.altera.com>
> 
> Add power supply alarm from the hwmon framework.

hwmon framework is a Linuxism that has nothing to do with the h/w 
description.
 
> Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
> ---
>  .../devicetree/bindings/mfd/altera-a10sr.txt       |    8 ++++++++
>  1 file changed, 8 insertions(+)

Just squash this into the 1st patch.

Rob

Re: [PATCH 08/11] dt-bindings: mfd: Add Altera A10-SR power supply alarm

[Rob Herring]

On Fri, Apr 22, 2016 at 10:33:36AM -0500, ttha...@opensource.altera.com wrote:
> From: Thor Thayer <ttha...@opensource.altera.com>
> 
> Add power supply alarm from the hwmon framework.

hwmon framework is a Linuxism that has nothing to do with the h/w 
description.
 
> Signed-off-by: Thor Thayer <ttha...@opensource.altera.com>
> ---
>  .../devicetree/bindings/mfd/altera-a10sr.txt       |    8 ++++++++
>  1 file changed, 8 insertions(+)

Just squash this into the 1st patch.

Rob
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Re: [PATCH 08/11] dt-bindings: mfd: Add Altera A10-SR power supply alarm

[Thor Thayer]

On 04/25/2016 07:57 AM, Rob Herring wrote:
> On Fri, Apr 22, 2016 at 10:33:36AM -0500, tthayer@opensource.altera.com wrote:
>> From: Thor Thayer <tthayer@opensource.altera.com>
>>
>> Add power supply alarm from the hwmon framework.
>
> hwmon framework is a Linuxism that has nothing to do with the h/w
> description.
>
OK. I was careful to remove it in the binding and will remove it from 
the description as well.

>> Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
>> ---
>>   .../devicetree/bindings/mfd/altera-a10sr.txt       |    8 ++++++++
>>   1 file changed, 8 insertions(+)
>
> Just squash this into the 1st patch.
>
> Rob
>
OK. Thank you for reviewing.

Re: [PATCH 08/11] dt-bindings: mfd: Add Altera A10-SR power supply alarm

[Thor Thayer]

On 04/25/2016 07:57 AM, Rob Herring wrote:
> On Fri, Apr 22, 2016 at 10:33:36AM -0500, tthayer@opensource.altera.com wrote:
>> From: Thor Thayer <tthayer@opensource.altera.com>
>>
>> Add power supply alarm from the hwmon framework.
>
> hwmon framework is a Linuxism that has nothing to do with the h/w
> description.
>
OK. I was careful to remove it in the binding and will remove it from 
the description as well.

>> Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
>> ---
>>   .../devicetree/bindings/mfd/altera-a10sr.txt       |    8 ++++++++
>>   1 file changed, 8 insertions(+)
>
> Just squash this into the 1st patch.
>
> Rob
>
OK. Thank you for reviewing.

[PATCH 09/11] mfd: altr_a10sr: Add Altera A10-SR power supply alarms

[tthayer]

From: Thor Thayer <tthayer@opensource.altera.com>

Add support for power supply alarms to the Altera Arria10
Development Kit System Resource chip.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
 drivers/mfd/altera-a10sr.c       |    4 ++++
 include/linux/mfd/altera-a10sr.h |   24 ++++++++++++++++++++++++
 2 files changed, 28 insertions(+)

diff --git a/drivers/mfd/altera-a10sr.c b/drivers/mfd/altera-a10sr.c
index 2ff08e3..2b2a90c 100644
--- a/drivers/mfd/altera-a10sr.c
+++ b/drivers/mfd/altera-a10sr.c
@@ -31,6 +31,10 @@ static const struct mfd_cell altr_a10sr_subdev_info[] = {
 		.name = "altr_a10sr_gpio",
 		.of_compatible = "altr,a10sr-gpio",
 	},
+	{
+		.name = "altr_a10sr_hwmon",
+		.of_compatible = "altr,a10sr-hwmon",
+	},
 };
 
 static bool altr_a10sr_reg_readable(struct device *dev, unsigned int reg)
diff --git a/include/linux/mfd/altera-a10sr.h b/include/linux/mfd/altera-a10sr.h
index c869fe7..22aa830 100644
--- a/include/linux/mfd/altera-a10sr.h
+++ b/include/linux/mfd/altera-a10sr.h
@@ -62,8 +62,32 @@
 #define ALTR_A10SR_IN_VALID_RANGE_HI      15
 
 #define ALTR_A10SR_PWR_GOOD1_REG      0x08    /* Power Good1 Read */
+/* Power Good #1 Register Bit Definitions */
+#define ALTR_A10SR_PG1_OP_FLAG_SHIFT    7       /* Power On Complete */
+#define ALTR_A10SR_PG1_1V8_SHIFT        6       /* 1.8V Power Good */
+#define ALTR_A10SR_PG1_2V5_SHIFT        5       /* 2.5V Power Good */
+#define ALTR_A10SR_PG1_3V3_SHIFT        4       /* 3.3V Power Good */
+#define ALTR_A10SR_PG1_5V0_SHIFT        3       /* 5.0V Power Good */
+#define ALTR_A10SR_PG1_0V9_SHIFT        2       /* 0.9V Power Good */
+#define ALTR_A10SR_PG1_0V95_SHIFT       1       /* 0.95V Power Good */
+#define ALTR_A10SR_PG1_1V0_SHIFT        0       /* 1.0V Power Good */
+
 #define ALTR_A10SR_PWR_GOOD2_REG      0x0A    /* Power Good2 Read */
+/* Power Good #2 Register Bit Definitions */
+#define ALTR_A10SR_PG2_HPS_SHIFT        7       /* HPS Power Good */
+#define ALTR_A10SR_PG2_HL_HPS_SHIFT     6       /* HILOHPS_VDD Power Good */
+#define ALTR_A10SR_PG2_HL_VDD_SHIFT     5       /* HILO VDD Power Good */
+#define ALTR_A10SR_PG2_HL_VDDQ_SHIFT    4       /* HILO VDDQ Power Good */
+#define ALTR_A10SR_PG2_FMCAVADJ_SHIFT   3       /* FMCA VADJ Power Good */
+#define ALTR_A10SR_PG2_FMCBVADJ_SHIFT   2       /* FMCB VADJ Power Good */
+#define ALTR_A10SR_PG2_FAC2MP_SHIFT     1       /* FAC2MP Power Good */
+#define ALTR_A10SR_PG2_FBC2MP_SHIFT     0       /* FBC2MP Power Good */
+
 #define ALTR_A10SR_PWR_GOOD3_REG      0x0C    /* Power Good3 Read */
+/* Power Good #3 Register Bit Definitions */
+#define ALTR_A10SR_PG3_FAM2C_SHIFT      7       /* FAM2C Power Good */
+#define ALTR_A10SR_PG3_10V_FAIL_SHIFT   6       /* 10V Fail n */
+
 #define ALTR_A10SR_FMCAB_REG          0x0E    /* FMCA/B & PCIe Pwr Enable */
 #define ALTR_A10SR_HPS_RST_REG        0x10    /* HPS Reset */
 #define ALTR_A10SR_USB_QSPI_REG       0x12    /* USB, BQSPI, FILE Reset */
-- 
1.7.9.5

[PATCH 09/11] mfd: altr_a10sr: Add Altera A10-SR power supply alarms

[tthayer]

From: Thor Thayer <tthayer@opensource.altera.com>

Add support for power supply alarms to the Altera Arria10
Development Kit System Resource chip.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
 drivers/mfd/altera-a10sr.c       |    4 ++++
 include/linux/mfd/altera-a10sr.h |   24 ++++++++++++++++++++++++
 2 files changed, 28 insertions(+)

diff --git a/drivers/mfd/altera-a10sr.c b/drivers/mfd/altera-a10sr.c
index 2ff08e3..2b2a90c 100644
--- a/drivers/mfd/altera-a10sr.c
+++ b/drivers/mfd/altera-a10sr.c
@@ -31,6 +31,10 @@ static const struct mfd_cell altr_a10sr_subdev_info[] = {
 		.name = "altr_a10sr_gpio",
 		.of_compatible = "altr,a10sr-gpio",
 	},
+	{
+		.name = "altr_a10sr_hwmon",
+		.of_compatible = "altr,a10sr-hwmon",
+	},
 };
 
 static bool altr_a10sr_reg_readable(struct device *dev, unsigned int reg)
diff --git a/include/linux/mfd/altera-a10sr.h b/include/linux/mfd/altera-a10sr.h
index c869fe7..22aa830 100644
--- a/include/linux/mfd/altera-a10sr.h
+++ b/include/linux/mfd/altera-a10sr.h
@@ -62,8 +62,32 @@
 #define ALTR_A10SR_IN_VALID_RANGE_HI      15
 
 #define ALTR_A10SR_PWR_GOOD1_REG      0x08    /* Power Good1 Read */
+/* Power Good #1 Register Bit Definitions */
+#define ALTR_A10SR_PG1_OP_FLAG_SHIFT    7       /* Power On Complete */
+#define ALTR_A10SR_PG1_1V8_SHIFT        6       /* 1.8V Power Good */
+#define ALTR_A10SR_PG1_2V5_SHIFT        5       /* 2.5V Power Good */
+#define ALTR_A10SR_PG1_3V3_SHIFT        4       /* 3.3V Power Good */
+#define ALTR_A10SR_PG1_5V0_SHIFT        3       /* 5.0V Power Good */
+#define ALTR_A10SR_PG1_0V9_SHIFT        2       /* 0.9V Power Good */
+#define ALTR_A10SR_PG1_0V95_SHIFT       1       /* 0.95V Power Good */
+#define ALTR_A10SR_PG1_1V0_SHIFT        0       /* 1.0V Power Good */
+
 #define ALTR_A10SR_PWR_GOOD2_REG      0x0A    /* Power Good2 Read */
+/* Power Good #2 Register Bit Definitions */
+#define ALTR_A10SR_PG2_HPS_SHIFT        7       /* HPS Power Good */
+#define ALTR_A10SR_PG2_HL_HPS_SHIFT     6       /* HILOHPS_VDD Power Good */
+#define ALTR_A10SR_PG2_HL_VDD_SHIFT     5       /* HILO VDD Power Good */
+#define ALTR_A10SR_PG2_HL_VDDQ_SHIFT    4       /* HILO VDDQ Power Good */
+#define ALTR_A10SR_PG2_FMCAVADJ_SHIFT   3       /* FMCA VADJ Power Good */
+#define ALTR_A10SR_PG2_FMCBVADJ_SHIFT   2       /* FMCB VADJ Power Good */
+#define ALTR_A10SR_PG2_FAC2MP_SHIFT     1       /* FAC2MP Power Good */
+#define ALTR_A10SR_PG2_FBC2MP_SHIFT     0       /* FBC2MP Power Good */
+
 #define ALTR_A10SR_PWR_GOOD3_REG      0x0C    /* Power Good3 Read */
+/* Power Good #3 Register Bit Definitions */
+#define ALTR_A10SR_PG3_FAM2C_SHIFT      7       /* FAM2C Power Good */
+#define ALTR_A10SR_PG3_10V_FAIL_SHIFT   6       /* 10V Fail n */
+
 #define ALTR_A10SR_FMCAB_REG          0x0E    /* FMCA/B & PCIe Pwr Enable */
 #define ALTR_A10SR_HPS_RST_REG        0x10    /* HPS Reset */
 #define ALTR_A10SR_USB_QSPI_REG       0x12    /* USB, BQSPI, FILE Reset */
-- 
1.7.9.5

Re: [PATCH 09/11] mfd: altr_a10sr: Add Altera A10-SR power supply alarms

[Lee Jones]

On Fri, 22 Apr 2016, tthayer@opensource.altera.com wrote:

> From: Thor Thayer <tthayer@opensource.altera.com>
> 
> Add support for power supply alarms to the Altera Arria10
> Development Kit System Resource chip.
> 
> Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
> ---
>  drivers/mfd/altera-a10sr.c       |    4 ++++
>  include/linux/mfd/altera-a10sr.h |   24 ++++++++++++++++++++++++
>  2 files changed, 28 insertions(+)

For my own reference:
  Acked-by: Lee Jones <lee.jones@linaro.org>
  
> diff --git a/drivers/mfd/altera-a10sr.c b/drivers/mfd/altera-a10sr.c
> index 2ff08e3..2b2a90c 100644
> --- a/drivers/mfd/altera-a10sr.c
> +++ b/drivers/mfd/altera-a10sr.c
> @@ -31,6 +31,10 @@ static const struct mfd_cell altr_a10sr_subdev_info[] = {
>  		.name = "altr_a10sr_gpio",
>  		.of_compatible = "altr,a10sr-gpio",
>  	},
> +	{
> +		.name = "altr_a10sr_hwmon",
> +		.of_compatible = "altr,a10sr-hwmon",
> +	},
>  };
>  
>  static bool altr_a10sr_reg_readable(struct device *dev, unsigned int reg)
> diff --git a/include/linux/mfd/altera-a10sr.h b/include/linux/mfd/altera-a10sr.h
> index c869fe7..22aa830 100644
> --- a/include/linux/mfd/altera-a10sr.h
> +++ b/include/linux/mfd/altera-a10sr.h
> @@ -62,8 +62,32 @@
>  #define ALTR_A10SR_IN_VALID_RANGE_HI      15
>  
>  #define ALTR_A10SR_PWR_GOOD1_REG      0x08    /* Power Good1 Read */
> +/* Power Good #1 Register Bit Definitions */
> +#define ALTR_A10SR_PG1_OP_FLAG_SHIFT    7       /* Power On Complete */
> +#define ALTR_A10SR_PG1_1V8_SHIFT        6       /* 1.8V Power Good */
> +#define ALTR_A10SR_PG1_2V5_SHIFT        5       /* 2.5V Power Good */
> +#define ALTR_A10SR_PG1_3V3_SHIFT        4       /* 3.3V Power Good */
> +#define ALTR_A10SR_PG1_5V0_SHIFT        3       /* 5.0V Power Good */
> +#define ALTR_A10SR_PG1_0V9_SHIFT        2       /* 0.9V Power Good */
> +#define ALTR_A10SR_PG1_0V95_SHIFT       1       /* 0.95V Power Good */
> +#define ALTR_A10SR_PG1_1V0_SHIFT        0       /* 1.0V Power Good */
> +
>  #define ALTR_A10SR_PWR_GOOD2_REG      0x0A    /* Power Good2 Read */
> +/* Power Good #2 Register Bit Definitions */
> +#define ALTR_A10SR_PG2_HPS_SHIFT        7       /* HPS Power Good */
> +#define ALTR_A10SR_PG2_HL_HPS_SHIFT     6       /* HILOHPS_VDD Power Good */
> +#define ALTR_A10SR_PG2_HL_VDD_SHIFT     5       /* HILO VDD Power Good */
> +#define ALTR_A10SR_PG2_HL_VDDQ_SHIFT    4       /* HILO VDDQ Power Good */
> +#define ALTR_A10SR_PG2_FMCAVADJ_SHIFT   3       /* FMCA VADJ Power Good */
> +#define ALTR_A10SR_PG2_FMCBVADJ_SHIFT   2       /* FMCB VADJ Power Good */
> +#define ALTR_A10SR_PG2_FAC2MP_SHIFT     1       /* FAC2MP Power Good */
> +#define ALTR_A10SR_PG2_FBC2MP_SHIFT     0       /* FBC2MP Power Good */
> +
>  #define ALTR_A10SR_PWR_GOOD3_REG      0x0C    /* Power Good3 Read */
> +/* Power Good #3 Register Bit Definitions */
> +#define ALTR_A10SR_PG3_FAM2C_SHIFT      7       /* FAM2C Power Good */
> +#define ALTR_A10SR_PG3_10V_FAIL_SHIFT   6       /* 10V Fail n */
> +
>  #define ALTR_A10SR_FMCAB_REG          0x0E    /* FMCA/B & PCIe Pwr Enable */
>  #define ALTR_A10SR_HPS_RST_REG        0x10    /* HPS Reset */
>  #define ALTR_A10SR_USB_QSPI_REG       0x12    /* USB, BQSPI, FILE Reset */

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
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Re: [PATCH 09/11] mfd: altr_a10sr: Add Altera A10-SR power supply alarms

[Lee Jones]

On Fri, 22 Apr 2016, ttha...@opensource.altera.com wrote:

> From: Thor Thayer <ttha...@opensource.altera.com>
> 
> Add support for power supply alarms to the Altera Arria10
> Development Kit System Resource chip.
> 
> Signed-off-by: Thor Thayer <ttha...@opensource.altera.com>
> ---
>  drivers/mfd/altera-a10sr.c       |    4 ++++
>  include/linux/mfd/altera-a10sr.h |   24 ++++++++++++++++++++++++
>  2 files changed, 28 insertions(+)

For my own reference:
  Acked-by: Lee Jones <lee.jo...@linaro.org>
  
> diff --git a/drivers/mfd/altera-a10sr.c b/drivers/mfd/altera-a10sr.c
> index 2ff08e3..2b2a90c 100644
> --- a/drivers/mfd/altera-a10sr.c
> +++ b/drivers/mfd/altera-a10sr.c
> @@ -31,6 +31,10 @@ static const struct mfd_cell altr_a10sr_subdev_info[] = {
>               .name = "altr_a10sr_gpio",
>               .of_compatible = "altr,a10sr-gpio",
>       },
> +     {
> +             .name = "altr_a10sr_hwmon",
> +             .of_compatible = "altr,a10sr-hwmon",
> +     },
>  };
>  
>  static bool altr_a10sr_reg_readable(struct device *dev, unsigned int reg)
> diff --git a/include/linux/mfd/altera-a10sr.h 
> b/include/linux/mfd/altera-a10sr.h
> index c869fe7..22aa830 100644
> --- a/include/linux/mfd/altera-a10sr.h
> +++ b/include/linux/mfd/altera-a10sr.h
> @@ -62,8 +62,32 @@
>  #define ALTR_A10SR_IN_VALID_RANGE_HI      15
>  
>  #define ALTR_A10SR_PWR_GOOD1_REG      0x08    /* Power Good1 Read */
> +/* Power Good #1 Register Bit Definitions */
> +#define ALTR_A10SR_PG1_OP_FLAG_SHIFT    7       /* Power On Complete */
> +#define ALTR_A10SR_PG1_1V8_SHIFT        6       /* 1.8V Power Good */
> +#define ALTR_A10SR_PG1_2V5_SHIFT        5       /* 2.5V Power Good */
> +#define ALTR_A10SR_PG1_3V3_SHIFT        4       /* 3.3V Power Good */
> +#define ALTR_A10SR_PG1_5V0_SHIFT        3       /* 5.0V Power Good */
> +#define ALTR_A10SR_PG1_0V9_SHIFT        2       /* 0.9V Power Good */
> +#define ALTR_A10SR_PG1_0V95_SHIFT       1       /* 0.95V Power Good */
> +#define ALTR_A10SR_PG1_1V0_SHIFT        0       /* 1.0V Power Good */
> +
>  #define ALTR_A10SR_PWR_GOOD2_REG      0x0A    /* Power Good2 Read */
> +/* Power Good #2 Register Bit Definitions */
> +#define ALTR_A10SR_PG2_HPS_SHIFT        7       /* HPS Power Good */
> +#define ALTR_A10SR_PG2_HL_HPS_SHIFT     6       /* HILOHPS_VDD Power Good */
> +#define ALTR_A10SR_PG2_HL_VDD_SHIFT     5       /* HILO VDD Power Good */
> +#define ALTR_A10SR_PG2_HL_VDDQ_SHIFT    4       /* HILO VDDQ Power Good */
> +#define ALTR_A10SR_PG2_FMCAVADJ_SHIFT   3       /* FMCA VADJ Power Good */
> +#define ALTR_A10SR_PG2_FMCBVADJ_SHIFT   2       /* FMCB VADJ Power Good */
> +#define ALTR_A10SR_PG2_FAC2MP_SHIFT     1       /* FAC2MP Power Good */
> +#define ALTR_A10SR_PG2_FBC2MP_SHIFT     0       /* FBC2MP Power Good */
> +
>  #define ALTR_A10SR_PWR_GOOD3_REG      0x0C    /* Power Good3 Read */
> +/* Power Good #3 Register Bit Definitions */
> +#define ALTR_A10SR_PG3_FAM2C_SHIFT      7       /* FAM2C Power Good */
> +#define ALTR_A10SR_PG3_10V_FAIL_SHIFT   6       /* 10V Fail n */
> +
>  #define ALTR_A10SR_FMCAB_REG          0x0E    /* FMCA/B & PCIe Pwr Enable */
>  #define ALTR_A10SR_HPS_RST_REG        0x10    /* HPS Reset */
>  #define ALTR_A10SR_USB_QSPI_REG       0x12    /* USB, BQSPI, FILE Reset */

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
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Re: [PATCH 09/11] mfd: altr_a10sr: Add Altera A10-SR power supply alarms

[Lee Jones]

On Mon, 09 May 2016, Lee Jones wrote:

> On Fri, 22 Apr 2016, tthayer@opensource.altera.com wrote:
> 
> > From: Thor Thayer <tthayer@opensource.altera.com>
> > 
> > Add support for power supply alarms to the Altera Arria10
> > Development Kit System Resource chip.
> > 
> > Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
> > ---
> >  drivers/mfd/altera-a10sr.c       |    4 ++++
> >  include/linux/mfd/altera-a10sr.h |   24 ++++++++++++++++++++++++
> >  2 files changed, 28 insertions(+)
> 
> For my own reference:
>   Acked-by: Lee Jones <lee.jones@linaro.org>

Change of plan, this should really be squashed into patch 3.

> > diff --git a/drivers/mfd/altera-a10sr.c b/drivers/mfd/altera-a10sr.c
> > index 2ff08e3..2b2a90c 100644
> > --- a/drivers/mfd/altera-a10sr.c
> > +++ b/drivers/mfd/altera-a10sr.c
> > @@ -31,6 +31,10 @@ static const struct mfd_cell altr_a10sr_subdev_info[] = {
> >  		.name = "altr_a10sr_gpio",
> >  		.of_compatible = "altr,a10sr-gpio",
> >  	},
> > +	{
> > +		.name = "altr_a10sr_hwmon",
> > +		.of_compatible = "altr,a10sr-hwmon",
> > +	},
> >  };
> >  
> >  static bool altr_a10sr_reg_readable(struct device *dev, unsigned int reg)
> > diff --git a/include/linux/mfd/altera-a10sr.h b/include/linux/mfd/altera-a10sr.h
> > index c869fe7..22aa830 100644
> > --- a/include/linux/mfd/altera-a10sr.h
> > +++ b/include/linux/mfd/altera-a10sr.h
> > @@ -62,8 +62,32 @@
> >  #define ALTR_A10SR_IN_VALID_RANGE_HI      15
> >  
> >  #define ALTR_A10SR_PWR_GOOD1_REG      0x08    /* Power Good1 Read */
> > +/* Power Good #1 Register Bit Definitions */
> > +#define ALTR_A10SR_PG1_OP_FLAG_SHIFT    7       /* Power On Complete */
> > +#define ALTR_A10SR_PG1_1V8_SHIFT        6       /* 1.8V Power Good */
> > +#define ALTR_A10SR_PG1_2V5_SHIFT        5       /* 2.5V Power Good */
> > +#define ALTR_A10SR_PG1_3V3_SHIFT        4       /* 3.3V Power Good */
> > +#define ALTR_A10SR_PG1_5V0_SHIFT        3       /* 5.0V Power Good */
> > +#define ALTR_A10SR_PG1_0V9_SHIFT        2       /* 0.9V Power Good */
> > +#define ALTR_A10SR_PG1_0V95_SHIFT       1       /* 0.95V Power Good */
> > +#define ALTR_A10SR_PG1_1V0_SHIFT        0       /* 1.0V Power Good */
> > +
> >  #define ALTR_A10SR_PWR_GOOD2_REG      0x0A    /* Power Good2 Read */
> > +/* Power Good #2 Register Bit Definitions */
> > +#define ALTR_A10SR_PG2_HPS_SHIFT        7       /* HPS Power Good */
> > +#define ALTR_A10SR_PG2_HL_HPS_SHIFT     6       /* HILOHPS_VDD Power Good */
> > +#define ALTR_A10SR_PG2_HL_VDD_SHIFT     5       /* HILO VDD Power Good */
> > +#define ALTR_A10SR_PG2_HL_VDDQ_SHIFT    4       /* HILO VDDQ Power Good */
> > +#define ALTR_A10SR_PG2_FMCAVADJ_SHIFT   3       /* FMCA VADJ Power Good */
> > +#define ALTR_A10SR_PG2_FMCBVADJ_SHIFT   2       /* FMCB VADJ Power Good */
> > +#define ALTR_A10SR_PG2_FAC2MP_SHIFT     1       /* FAC2MP Power Good */
> > +#define ALTR_A10SR_PG2_FBC2MP_SHIFT     0       /* FBC2MP Power Good */
> > +
> >  #define ALTR_A10SR_PWR_GOOD3_REG      0x0C    /* Power Good3 Read */
> > +/* Power Good #3 Register Bit Definitions */
> > +#define ALTR_A10SR_PG3_FAM2C_SHIFT      7       /* FAM2C Power Good */
> > +#define ALTR_A10SR_PG3_10V_FAIL_SHIFT   6       /* 10V Fail n */
> > +
> >  #define ALTR_A10SR_FMCAB_REG          0x0E    /* FMCA/B & PCIe Pwr Enable */
> >  #define ALTR_A10SR_HPS_RST_REG        0x10    /* HPS Reset */
> >  #define ALTR_A10SR_USB_QSPI_REG       0x12    /* USB, BQSPI, FILE Reset */
> 

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
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Re: [PATCH 09/11] mfd: altr_a10sr: Add Altera A10-SR power supply alarms

[Lee Jones]

On Mon, 09 May 2016, Lee Jones wrote:

> On Fri, 22 Apr 2016, ttha...@opensource.altera.com wrote:
> 
> > From: Thor Thayer <ttha...@opensource.altera.com>
> > 
> > Add support for power supply alarms to the Altera Arria10
> > Development Kit System Resource chip.
> > 
> > Signed-off-by: Thor Thayer <ttha...@opensource.altera.com>
> > ---
> >  drivers/mfd/altera-a10sr.c       |    4 ++++
> >  include/linux/mfd/altera-a10sr.h |   24 ++++++++++++++++++++++++
> >  2 files changed, 28 insertions(+)
> 
> For my own reference:
>   Acked-by: Lee Jones <lee.jo...@linaro.org>

Change of plan, this should really be squashed into patch 3.

> > diff --git a/drivers/mfd/altera-a10sr.c b/drivers/mfd/altera-a10sr.c
> > index 2ff08e3..2b2a90c 100644
> > --- a/drivers/mfd/altera-a10sr.c
> > +++ b/drivers/mfd/altera-a10sr.c
> > @@ -31,6 +31,10 @@ static const struct mfd_cell altr_a10sr_subdev_info[] = {
> >             .name = "altr_a10sr_gpio",
> >             .of_compatible = "altr,a10sr-gpio",
> >     },
> > +   {
> > +           .name = "altr_a10sr_hwmon",
> > +           .of_compatible = "altr,a10sr-hwmon",
> > +   },
> >  };
> >  
> >  static bool altr_a10sr_reg_readable(struct device *dev, unsigned int reg)
> > diff --git a/include/linux/mfd/altera-a10sr.h 
> > b/include/linux/mfd/altera-a10sr.h
> > index c869fe7..22aa830 100644
> > --- a/include/linux/mfd/altera-a10sr.h
> > +++ b/include/linux/mfd/altera-a10sr.h
> > @@ -62,8 +62,32 @@
> >  #define ALTR_A10SR_IN_VALID_RANGE_HI      15
> >  
> >  #define ALTR_A10SR_PWR_GOOD1_REG      0x08    /* Power Good1 Read */
> > +/* Power Good #1 Register Bit Definitions */
> > +#define ALTR_A10SR_PG1_OP_FLAG_SHIFT    7       /* Power On Complete */
> > +#define ALTR_A10SR_PG1_1V8_SHIFT        6       /* 1.8V Power Good */
> > +#define ALTR_A10SR_PG1_2V5_SHIFT        5       /* 2.5V Power Good */
> > +#define ALTR_A10SR_PG1_3V3_SHIFT        4       /* 3.3V Power Good */
> > +#define ALTR_A10SR_PG1_5V0_SHIFT        3       /* 5.0V Power Good */
> > +#define ALTR_A10SR_PG1_0V9_SHIFT        2       /* 0.9V Power Good */
> > +#define ALTR_A10SR_PG1_0V95_SHIFT       1       /* 0.95V Power Good */
> > +#define ALTR_A10SR_PG1_1V0_SHIFT        0       /* 1.0V Power Good */
> > +
> >  #define ALTR_A10SR_PWR_GOOD2_REG      0x0A    /* Power Good2 Read */
> > +/* Power Good #2 Register Bit Definitions */
> > +#define ALTR_A10SR_PG2_HPS_SHIFT        7       /* HPS Power Good */
> > +#define ALTR_A10SR_PG2_HL_HPS_SHIFT     6       /* HILOHPS_VDD Power Good 
> > */
> > +#define ALTR_A10SR_PG2_HL_VDD_SHIFT     5       /* HILO VDD Power Good */
> > +#define ALTR_A10SR_PG2_HL_VDDQ_SHIFT    4       /* HILO VDDQ Power Good */
> > +#define ALTR_A10SR_PG2_FMCAVADJ_SHIFT   3       /* FMCA VADJ Power Good */
> > +#define ALTR_A10SR_PG2_FMCBVADJ_SHIFT   2       /* FMCB VADJ Power Good */
> > +#define ALTR_A10SR_PG2_FAC2MP_SHIFT     1       /* FAC2MP Power Good */
> > +#define ALTR_A10SR_PG2_FBC2MP_SHIFT     0       /* FBC2MP Power Good */
> > +
> >  #define ALTR_A10SR_PWR_GOOD3_REG      0x0C    /* Power Good3 Read */
> > +/* Power Good #3 Register Bit Definitions */
> > +#define ALTR_A10SR_PG3_FAM2C_SHIFT      7       /* FAM2C Power Good */
> > +#define ALTR_A10SR_PG3_10V_FAIL_SHIFT   6       /* 10V Fail n */
> > +
> >  #define ALTR_A10SR_FMCAB_REG          0x0E    /* FMCA/B & PCIe Pwr Enable 
> > */
> >  #define ALTR_A10SR_HPS_RST_REG        0x10    /* HPS Reset */
> >  #define ALTR_A10SR_USB_QSPI_REG       0x12    /* USB, BQSPI, FILE Reset */
> 

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
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[PATCH 10/11] hwmon: Add Altera A10-SR power supply alarms

[tthayer]

From: Thor Thayer <tthayer@opensource.altera.com>

This patch adds the power supply alarms of the hwmon framework
to the Arria10 System Resource chip.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
 drivers/hwmon/Kconfig              |    9 ++
 drivers/hwmon/Makefile             |    1 +
 drivers/hwmon/altera-a10sr-hwmon.c |  215 ++++++++++++++++++++++++++++++++++++
 3 files changed, 225 insertions(+)
 create mode 100644 drivers/hwmon/altera-a10sr-hwmon.c

diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
index ff94007..af08846 100644
--- a/drivers/hwmon/Kconfig
+++ b/drivers/hwmon/Kconfig
@@ -248,6 +248,15 @@ config SENSORS_ADT7475
 	  This driver can also be build as a module.  If so, the module
 	  will be called adt7475.
 
+config SENSORS_ALTERA_A10SR
+	bool "Altera Arria10 System Status"
+	depends on MFD_ALTERA_A10SR
+	help
+	  If you say yes here you get support for the power ready status
+	  for the Arria10's external power supplies on the Arria10 DevKit.
+	  These values are read over the SPI bus from the Arria10 System
+	  Resource chip.
+
 config SENSORS_ASC7621
 	tristate "Andigilog aSC7621"
 	depends on I2C
diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
index 2ef5b7c..17d72a7 100644
--- a/drivers/hwmon/Makefile
+++ b/drivers/hwmon/Makefile
@@ -43,6 +43,7 @@ obj-$(CONFIG_SENSORS_ADT7411)	+= adt7411.o
 obj-$(CONFIG_SENSORS_ADT7462)	+= adt7462.o
 obj-$(CONFIG_SENSORS_ADT7470)	+= adt7470.o
 obj-$(CONFIG_SENSORS_ADT7475)	+= adt7475.o
+obj-$(CONFIG_SENSORS_ALTERA_A10SR) += altera-a10sr-hwmon.o
 obj-$(CONFIG_SENSORS_APPLESMC)	+= applesmc.o
 obj-$(CONFIG_SENSORS_ARM_SCPI)	+= scpi-hwmon.o
 obj-$(CONFIG_SENSORS_ASC7621)	+= asc7621.o
diff --git a/drivers/hwmon/altera-a10sr-hwmon.c b/drivers/hwmon/altera-a10sr-hwmon.c
new file mode 100644
index 0000000..1eecc6b
--- /dev/null
+++ b/drivers/hwmon/altera-a10sr-hwmon.c
@@ -0,0 +1,215 @@
+/*
+ *  Copyright Altera Corporation (C) 2014-2016. All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * HW Monitor driver for  Altera Arria10 MAX5 System Resource Chip
+ * Adapted from DA9052
+ */
+
+#include <linux/hwmon.h>
+#include <linux/hwmon-sysfs.h>
+#include <linux/mfd/altera-a10sr.h>
+#include <linux/module.h>
+#include <linux/of.h>
+
+#define ALTR_A10SR_1V0_BIT_POS          ALTR_A10SR_PG1_1V0_SHIFT
+#define ALTR_A10SR_0V95_BIT_POS         ALTR_A10SR_PG1_0V95_SHIFT
+#define ALTR_A10SR_0V9_BIT_POS          ALTR_A10SR_PG1_0V9_SHIFT
+#define ALTR_A10SR_10V_BIT_POS          ALTR_A10SR_PG1_10V_SHIFT
+#define ALTR_A10SR_5V0_BIT_POS          ALTR_A10SR_PG1_5V0_SHIFT
+#define ALTR_A10SR_3V3_BIT_POS          ALTR_A10SR_PG1_3V3_SHIFT
+#define ALTR_A10SR_2V5_BIT_POS          ALTR_A10SR_PG1_2V5_SHIFT
+#define ALTR_A10SR_1V8_BIT_POS          ALTR_A10SR_PG1_1V8_SHIFT
+#define ALTR_A10SR_OP_FLAG_BIT_POS      ALTR_A10SR_PG1_OP_FLAG_SHIFT
+/* 2nd register needs an offset of 8 to get to 2nd register */
+#define ALTR_A10SR_FBC2MP_BIT_POS       (8 + ALTR_A10SR_PG2_FBC2MP_SHIFT)
+#define ALTR_A10SR_FAC2MP_BIT_POS       (8 + ALTR_A10SR_PG2_FAC2MP_SHIFT)
+#define ALTR_A10SR_FMCBVADJ_BIT_POS     (8 + ALTR_A10SR_PG2_FMCBVADJ_SHIFT)
+#define ALTR_A10SR_FMCAVADJ_BIT_POS     (8 + ALTR_A10SR_PG2_FMCAVADJ_SHIFT)
+#define ALTR_A10SR_HL_VDDQ_BIT_POS      (8 + ALTR_A10SR_PG2_HL_VDDQ_SHIFT)
+#define ALTR_A10SR_HL_VDD_BIT_POS       (8 + ALTR_A10SR_PG2_HL_VDD_SHIFT)
+#define ALTR_A10SR_HL_HPS_BIT_POS       (8 + ALTR_A10SR_PG2_HL_HPS_SHIFT)
+#define ALTR_A10SR_HPS_BIT_POS          (8 + ALTR_A10SR_PG2_HPS_SHIFT)
+/* 3rd register needs an offset of 16 to get to 3rd register */
+#define ALTR_A10SR_10V_FAIL_BIT_POS     (16 + ALTR_A10SR_PG3_10V_FAIL_SHIFT)
+#define ALTR_A10SR_FAM2C_BIT_POS        (16 + ALTR_A10SR_PG3_FAM2C_SHIFT)
+
+/**
+ * struct altr_a10sr_hwmon - Altera Max5 HWMON device private data structure
+ * @device: hwmon class.
+ * @regmap: the regmap from the parent device.
+ */
+struct altr_a10sr_hwmon {
+	struct device		*class_device;
+	struct regmap		*regmap;
+};
+
+static ssize_t altr_a10sr_read_status(struct device *dev,
+				      struct device_attribute *devattr,
+				      char *buf)
+{
+	struct altr_a10sr_hwmon *hwmon = dev_get_drvdata(dev);
+	int val, ret, index = to_sensor_dev_attr(devattr)->index;
+	int mask = ALTR_A10SR_REG_BIT_MASK(index);
+	unsigned char reg = ALTR_A10SR_PWR_GOOD1_REG +
+			    ALTR_A10SR_REG_OFFSET(index);
+
+	ret = regmap_read(hwmon->regmap, reg, &val);
+	if (ret < 0)
+		return ret;
+
+	return sprintf(buf, "%d\n", !!(~val & mask));
+}
+
+static ssize_t altr_a10sr_hwmon_show_name(struct device *dev,
+					  struct device_attribute *devattr,
+					  char *buf)
+{
+	return sprintf(buf, "altr_a10sr\n");
+}
+
+/* First Power Good Register Bits */
+static SENSOR_DEVICE_ATTR(1v0_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
+			  ALTR_A10SR_1V0_BIT_POS);
+static SENSOR_DEVICE_ATTR(0v95_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
+			  ALTR_A10SR_0V95_BIT_POS);
+static SENSOR_DEVICE_ATTR(0v9_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
+			  ALTR_A10SR_0V9_BIT_POS);
+static SENSOR_DEVICE_ATTR(5v0_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
+			  ALTR_A10SR_5V0_BIT_POS);
+static SENSOR_DEVICE_ATTR(3v3_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
+			  ALTR_A10SR_3V3_BIT_POS);
+static SENSOR_DEVICE_ATTR(2v5_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
+			  ALTR_A10SR_2V5_BIT_POS);
+static SENSOR_DEVICE_ATTR(1v8_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
+			  ALTR_A10SR_1V8_BIT_POS);
+static SENSOR_DEVICE_ATTR(opflag_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
+			  ALTR_A10SR_OP_FLAG_BIT_POS);
+/* Second Power Good Register Bits */
+static SENSOR_DEVICE_ATTR(fbc2mp_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
+			  ALTR_A10SR_FBC2MP_BIT_POS);
+static SENSOR_DEVICE_ATTR(fac2mp_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
+			  ALTR_A10SR_FAC2MP_BIT_POS);
+static SENSOR_DEVICE_ATTR(fmcbvadj_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
+			  ALTR_A10SR_FMCBVADJ_BIT_POS);
+static SENSOR_DEVICE_ATTR(fmcavadj_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
+			  ALTR_A10SR_FMCAVADJ_BIT_POS);
+static SENSOR_DEVICE_ATTR(hl_vddq_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
+			  ALTR_A10SR_HL_VDDQ_BIT_POS);
+static SENSOR_DEVICE_ATTR(hl_vdd_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
+			  ALTR_A10SR_HL_VDD_BIT_POS);
+static SENSOR_DEVICE_ATTR(hlhps_vdd_alarm, S_IRUGO, altr_a10sr_read_status,
+			  NULL, ALTR_A10SR_HL_HPS_BIT_POS);
+static SENSOR_DEVICE_ATTR(hps_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
+			  ALTR_A10SR_HPS_BIT_POS);
+/* Third Power Good Register Bits */
+static SENSOR_DEVICE_ATTR(10v_alarm, S_IRUGO, altr_a10sr_read_status,
+			  NULL, ALTR_A10SR_10V_FAIL_BIT_POS);
+static SENSOR_DEVICE_ATTR(fam2c_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
+			  ALTR_A10SR_FAM2C_BIT_POS);
+
+static DEVICE_ATTR(name, S_IRUGO, altr_a10sr_hwmon_show_name, NULL);
+
+static struct attribute *altr_a10sr_attr[] = {
+	&dev_attr_name.attr,
+	/* First Power Good Register */
+	&sensor_dev_attr_opflag_alarm.dev_attr.attr,
+	&sensor_dev_attr_1v8_alarm.dev_attr.attr,
+	&sensor_dev_attr_2v5_alarm.dev_attr.attr,
+	&sensor_dev_attr_1v0_alarm.dev_attr.attr,
+	&sensor_dev_attr_3v3_alarm.dev_attr.attr,
+	&sensor_dev_attr_5v0_alarm.dev_attr.attr,
+	&sensor_dev_attr_0v9_alarm.dev_attr.attr,
+	&sensor_dev_attr_0v95_alarm.dev_attr.attr,
+	/* Second Power Good Register */
+	&sensor_dev_attr_hps_alarm.dev_attr.attr,
+	&sensor_dev_attr_hlhps_vdd_alarm.dev_attr.attr,
+	&sensor_dev_attr_hl_vdd_alarm.dev_attr.attr,
+	&sensor_dev_attr_hl_vddq_alarm.dev_attr.attr,
+	&sensor_dev_attr_fmcavadj_alarm.dev_attr.attr,
+	&sensor_dev_attr_fmcbvadj_alarm.dev_attr.attr,
+	&sensor_dev_attr_fac2mp_alarm.dev_attr.attr,
+	&sensor_dev_attr_fbc2mp_alarm.dev_attr.attr,
+	/* Third Power Good Register */
+	&sensor_dev_attr_10v_alarm.dev_attr.attr,
+	&sensor_dev_attr_fam2c_alarm.dev_attr.attr,
+	NULL
+};
+
+static const struct attribute_group altr_a10sr_attr_group = {
+	.attrs = altr_a10sr_attr
+};
+
+static int altr_a10sr_hwmon_probe(struct platform_device *pdev)
+{
+	struct altr_a10sr_hwmon *hwmon;
+	int ret;
+	struct altr_a10sr *a10sr = dev_get_drvdata(pdev->dev.parent);
+
+	hwmon = devm_kzalloc(&pdev->dev, sizeof(*hwmon), GFP_KERNEL);
+	if (!hwmon)
+		return -ENOMEM;
+
+	hwmon->regmap = a10sr->regmap;
+
+	platform_set_drvdata(pdev, hwmon);
+
+	ret = sysfs_create_group(&pdev->dev.kobj, &altr_a10sr_attr_group);
+	if (ret)
+		goto err_mem;
+
+	hwmon->class_device = hwmon_device_register(&pdev->dev);
+	if (IS_ERR(hwmon->class_device)) {
+		ret = PTR_ERR(hwmon->class_device);
+		goto err_sysfs;
+	}
+
+	return 0;
+
+err_sysfs:
+	sysfs_remove_group(&pdev->dev.kobj, &altr_a10sr_attr_group);
+err_mem:
+	return ret;
+}
+
+static int altr_a10sr_hwmon_remove(struct platform_device *pdev)
+{
+	struct altr_a10sr_hwmon *hwmon = platform_get_drvdata(pdev);
+
+	hwmon_device_unregister(hwmon->class_device);
+	sysfs_remove_group(&pdev->dev.kobj, &altr_a10sr_attr_group);
+
+	return 0;
+}
+
+static const struct of_device_id altr_a10sr_hwmon_of_match[] = {
+	{ .compatible = "altr,a10sr-hwmon" },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, altr_a10sr_hwmon_of_match);
+
+static struct platform_driver altr_a10sr_hwmon_driver = {
+	.probe = altr_a10sr_hwmon_probe,
+	.remove = altr_a10sr_hwmon_remove,
+	.driver = {
+		.name = "altr_a10sr_hwmon",
+		.of_match_table = of_match_ptr(altr_a10sr_hwmon_of_match),
+	},
+};
+
+module_platform_driver(altr_a10sr_hwmon_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Thor Thayer <tthayer@opensource.altera.com>");
+MODULE_DESCRIPTION("HW Monitor driver for Altera Arria10 System Resource Chip");
-- 
1.7.9.5

[PATCH 10/11] hwmon: Add Altera A10-SR power supply alarms

[tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx]

From: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>

This patch adds the power supply alarms of the hwmon framework
to the Arria10 System Resource chip.

Signed-off-by: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
---
 drivers/hwmon/Kconfig              |    9 ++
 drivers/hwmon/Makefile             |    1 +
 drivers/hwmon/altera-a10sr-hwmon.c |  215 ++++++++++++++++++++++++++++++++++++
 3 files changed, 225 insertions(+)
 create mode 100644 drivers/hwmon/altera-a10sr-hwmon.c

diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
index ff94007..af08846 100644
--- a/drivers/hwmon/Kconfig
+++ b/drivers/hwmon/Kconfig
@@ -248,6 +248,15 @@ config SENSORS_ADT7475
 	  This driver can also be build as a module.  If so, the module
 	  will be called adt7475.
 
+config SENSORS_ALTERA_A10SR
+	bool "Altera Arria10 System Status"
+	depends on MFD_ALTERA_A10SR
+	help
+	  If you say yes here you get support for the power ready status
+	  for the Arria10's external power supplies on the Arria10 DevKit.
+	  These values are read over the SPI bus from the Arria10 System
+	  Resource chip.
+
 config SENSORS_ASC7621
 	tristate "Andigilog aSC7621"
 	depends on I2C
diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
index 2ef5b7c..17d72a7 100644
--- a/drivers/hwmon/Makefile
+++ b/drivers/hwmon/Makefile
@@ -43,6 +43,7 @@ obj-$(CONFIG_SENSORS_ADT7411)	+= adt7411.o
 obj-$(CONFIG_SENSORS_ADT7462)	+= adt7462.o
 obj-$(CONFIG_SENSORS_ADT7470)	+= adt7470.o
 obj-$(CONFIG_SENSORS_ADT7475)	+= adt7475.o
+obj-$(CONFIG_SENSORS_ALTERA_A10SR) += altera-a10sr-hwmon.o
 obj-$(CONFIG_SENSORS_APPLESMC)	+= applesmc.o
 obj-$(CONFIG_SENSORS_ARM_SCPI)	+= scpi-hwmon.o
 obj-$(CONFIG_SENSORS_ASC7621)	+= asc7621.o
diff --git a/drivers/hwmon/altera-a10sr-hwmon.c b/drivers/hwmon/altera-a10sr-hwmon.c
new file mode 100644
index 0000000..1eecc6b
--- /dev/null
+++ b/drivers/hwmon/altera-a10sr-hwmon.c
@@ -0,0 +1,215 @@
+/*
+ *  Copyright Altera Corporation (C) 2014-2016. All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * HW Monitor driver for  Altera Arria10 MAX5 System Resource Chip
+ * Adapted from DA9052
+ */
+
+#include <linux/hwmon.h>
+#include <linux/hwmon-sysfs.h>
+#include <linux/mfd/altera-a10sr.h>
+#include <linux/module.h>
+#include <linux/of.h>
+
+#define ALTR_A10SR_1V0_BIT_POS          ALTR_A10SR_PG1_1V0_SHIFT
+#define ALTR_A10SR_0V95_BIT_POS         ALTR_A10SR_PG1_0V95_SHIFT
+#define ALTR_A10SR_0V9_BIT_POS          ALTR_A10SR_PG1_0V9_SHIFT
+#define ALTR_A10SR_10V_BIT_POS          ALTR_A10SR_PG1_10V_SHIFT
+#define ALTR_A10SR_5V0_BIT_POS          ALTR_A10SR_PG1_5V0_SHIFT
+#define ALTR_A10SR_3V3_BIT_POS          ALTR_A10SR_PG1_3V3_SHIFT
+#define ALTR_A10SR_2V5_BIT_POS          ALTR_A10SR_PG1_2V5_SHIFT
+#define ALTR_A10SR_1V8_BIT_POS          ALTR_A10SR_PG1_1V8_SHIFT
+#define ALTR_A10SR_OP_FLAG_BIT_POS      ALTR_A10SR_PG1_OP_FLAG_SHIFT
+/* 2nd register needs an offset of 8 to get to 2nd register */
+#define ALTR_A10SR_FBC2MP_BIT_POS       (8 + ALTR_A10SR_PG2_FBC2MP_SHIFT)
+#define ALTR_A10SR_FAC2MP_BIT_POS       (8 + ALTR_A10SR_PG2_FAC2MP_SHIFT)
+#define ALTR_A10SR_FMCBVADJ_BIT_POS     (8 + ALTR_A10SR_PG2_FMCBVADJ_SHIFT)
+#define ALTR_A10SR_FMCAVADJ_BIT_POS     (8 + ALTR_A10SR_PG2_FMCAVADJ_SHIFT)
+#define ALTR_A10SR_HL_VDDQ_BIT_POS      (8 + ALTR_A10SR_PG2_HL_VDDQ_SHIFT)
+#define ALTR_A10SR_HL_VDD_BIT_POS       (8 + ALTR_A10SR_PG2_HL_VDD_SHIFT)
+#define ALTR_A10SR_HL_HPS_BIT_POS       (8 + ALTR_A10SR_PG2_HL_HPS_SHIFT)
+#define ALTR_A10SR_HPS_BIT_POS          (8 + ALTR_A10SR_PG2_HPS_SHIFT)
+/* 3rd register needs an offset of 16 to get to 3rd register */
+#define ALTR_A10SR_10V_FAIL_BIT_POS     (16 + ALTR_A10SR_PG3_10V_FAIL_SHIFT)
+#define ALTR_A10SR_FAM2C_BIT_POS        (16 + ALTR_A10SR_PG3_FAM2C_SHIFT)
+
+/**
+ * struct altr_a10sr_hwmon - Altera Max5 HWMON device private data structure
+ * @device: hwmon class.
+ * @regmap: the regmap from the parent device.
+ */
+struct altr_a10sr_hwmon {
+	struct device		*class_device;
+	struct regmap		*regmap;
+};
+
+static ssize_t altr_a10sr_read_status(struct device *dev,
+				      struct device_attribute *devattr,
+				      char *buf)
+{
+	struct altr_a10sr_hwmon *hwmon = dev_get_drvdata(dev);
+	int val, ret, index = to_sensor_dev_attr(devattr)->index;
+	int mask = ALTR_A10SR_REG_BIT_MASK(index);
+	unsigned char reg = ALTR_A10SR_PWR_GOOD1_REG +
+			    ALTR_A10SR_REG_OFFSET(index);
+
+	ret = regmap_read(hwmon->regmap, reg, &val);
+	if (ret < 0)
+		return ret;
+
+	return sprintf(buf, "%d\n", !!(~val & mask));
+}
+
+static ssize_t altr_a10sr_hwmon_show_name(struct device *dev,
+					  struct device_attribute *devattr,
+					  char *buf)
+{
+	return sprintf(buf, "altr_a10sr\n");
+}
+
+/* First Power Good Register Bits */
+static SENSOR_DEVICE_ATTR(1v0_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
+			  ALTR_A10SR_1V0_BIT_POS);
+static SENSOR_DEVICE_ATTR(0v95_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
+			  ALTR_A10SR_0V95_BIT_POS);
+static SENSOR_DEVICE_ATTR(0v9_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
+			  ALTR_A10SR_0V9_BIT_POS);
+static SENSOR_DEVICE_ATTR(5v0_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
+			  ALTR_A10SR_5V0_BIT_POS);
+static SENSOR_DEVICE_ATTR(3v3_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
+			  ALTR_A10SR_3V3_BIT_POS);
+static SENSOR_DEVICE_ATTR(2v5_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
+			  ALTR_A10SR_2V5_BIT_POS);
+static SENSOR_DEVICE_ATTR(1v8_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
+			  ALTR_A10SR_1V8_BIT_POS);
+static SENSOR_DEVICE_ATTR(opflag_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
+			  ALTR_A10SR_OP_FLAG_BIT_POS);
+/* Second Power Good Register Bits */
+static SENSOR_DEVICE_ATTR(fbc2mp_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
+			  ALTR_A10SR_FBC2MP_BIT_POS);
+static SENSOR_DEVICE_ATTR(fac2mp_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
+			  ALTR_A10SR_FAC2MP_BIT_POS);
+static SENSOR_DEVICE_ATTR(fmcbvadj_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
+			  ALTR_A10SR_FMCBVADJ_BIT_POS);
+static SENSOR_DEVICE_ATTR(fmcavadj_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
+			  ALTR_A10SR_FMCAVADJ_BIT_POS);
+static SENSOR_DEVICE_ATTR(hl_vddq_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
+			  ALTR_A10SR_HL_VDDQ_BIT_POS);
+static SENSOR_DEVICE_ATTR(hl_vdd_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
+			  ALTR_A10SR_HL_VDD_BIT_POS);
+static SENSOR_DEVICE_ATTR(hlhps_vdd_alarm, S_IRUGO, altr_a10sr_read_status,
+			  NULL, ALTR_A10SR_HL_HPS_BIT_POS);
+static SENSOR_DEVICE_ATTR(hps_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
+			  ALTR_A10SR_HPS_BIT_POS);
+/* Third Power Good Register Bits */
+static SENSOR_DEVICE_ATTR(10v_alarm, S_IRUGO, altr_a10sr_read_status,
+			  NULL, ALTR_A10SR_10V_FAIL_BIT_POS);
+static SENSOR_DEVICE_ATTR(fam2c_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
+			  ALTR_A10SR_FAM2C_BIT_POS);
+
+static DEVICE_ATTR(name, S_IRUGO, altr_a10sr_hwmon_show_name, NULL);
+
+static struct attribute *altr_a10sr_attr[] = {
+	&dev_attr_name.attr,
+	/* First Power Good Register */
+	&sensor_dev_attr_opflag_alarm.dev_attr.attr,
+	&sensor_dev_attr_1v8_alarm.dev_attr.attr,
+	&sensor_dev_attr_2v5_alarm.dev_attr.attr,
+	&sensor_dev_attr_1v0_alarm.dev_attr.attr,
+	&sensor_dev_attr_3v3_alarm.dev_attr.attr,
+	&sensor_dev_attr_5v0_alarm.dev_attr.attr,
+	&sensor_dev_attr_0v9_alarm.dev_attr.attr,
+	&sensor_dev_attr_0v95_alarm.dev_attr.attr,
+	/* Second Power Good Register */
+	&sensor_dev_attr_hps_alarm.dev_attr.attr,
+	&sensor_dev_attr_hlhps_vdd_alarm.dev_attr.attr,
+	&sensor_dev_attr_hl_vdd_alarm.dev_attr.attr,
+	&sensor_dev_attr_hl_vddq_alarm.dev_attr.attr,
+	&sensor_dev_attr_fmcavadj_alarm.dev_attr.attr,
+	&sensor_dev_attr_fmcbvadj_alarm.dev_attr.attr,
+	&sensor_dev_attr_fac2mp_alarm.dev_attr.attr,
+	&sensor_dev_attr_fbc2mp_alarm.dev_attr.attr,
+	/* Third Power Good Register */
+	&sensor_dev_attr_10v_alarm.dev_attr.attr,
+	&sensor_dev_attr_fam2c_alarm.dev_attr.attr,
+	NULL
+};
+
+static const struct attribute_group altr_a10sr_attr_group = {
+	.attrs = altr_a10sr_attr
+};
+
+static int altr_a10sr_hwmon_probe(struct platform_device *pdev)
+{
+	struct altr_a10sr_hwmon *hwmon;
+	int ret;
+	struct altr_a10sr *a10sr = dev_get_drvdata(pdev->dev.parent);
+
+	hwmon = devm_kzalloc(&pdev->dev, sizeof(*hwmon), GFP_KERNEL);
+	if (!hwmon)
+		return -ENOMEM;
+
+	hwmon->regmap = a10sr->regmap;
+
+	platform_set_drvdata(pdev, hwmon);
+
+	ret = sysfs_create_group(&pdev->dev.kobj, &altr_a10sr_attr_group);
+	if (ret)
+		goto err_mem;
+
+	hwmon->class_device = hwmon_device_register(&pdev->dev);
+	if (IS_ERR(hwmon->class_device)) {
+		ret = PTR_ERR(hwmon->class_device);
+		goto err_sysfs;
+	}
+
+	return 0;
+
+err_sysfs:
+	sysfs_remove_group(&pdev->dev.kobj, &altr_a10sr_attr_group);
+err_mem:
+	return ret;
+}
+
+static int altr_a10sr_hwmon_remove(struct platform_device *pdev)
+{
+	struct altr_a10sr_hwmon *hwmon = platform_get_drvdata(pdev);
+
+	hwmon_device_unregister(hwmon->class_device);
+	sysfs_remove_group(&pdev->dev.kobj, &altr_a10sr_attr_group);
+
+	return 0;
+}
+
+static const struct of_device_id altr_a10sr_hwmon_of_match[] = {
+	{ .compatible = "altr,a10sr-hwmon" },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, altr_a10sr_hwmon_of_match);
+
+static struct platform_driver altr_a10sr_hwmon_driver = {
+	.probe = altr_a10sr_hwmon_probe,
+	.remove = altr_a10sr_hwmon_remove,
+	.driver = {
+		.name = "altr_a10sr_hwmon",
+		.of_match_table = of_match_ptr(altr_a10sr_hwmon_of_match),
+	},
+};
+
+module_platform_driver(altr_a10sr_hwmon_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>");
+MODULE_DESCRIPTION("HW Monitor driver for Altera Arria10 System Resource Chip");
-- 
1.7.9.5

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Re: [PATCH 10/11] hwmon: Add Altera A10-SR power supply alarms

[Guenter Roeck]

On Fri, Apr 22, 2016 at 10:33:38AM -0500, tthayer@opensource.altera.com wrote:
> From: Thor Thayer <tthayer@opensource.altera.com>
> 
> This patch adds the power supply alarms of the hwmon framework
> to the Arria10 System Resource chip.
> 
> Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
> ---

Please read and follow Documentation/hwmon/sysfs-interface 
as well as Documentation/hwmon/submitting-patches. At the very least,
you are expected to document your driver, and you are expected to
use standard attribute names.

>  drivers/hwmon/Kconfig              |    9 ++
>  drivers/hwmon/Makefile             |    1 +
>  drivers/hwmon/altera-a10sr-hwmon.c |  215 ++++++++++++++++++++++++++++++++++++
>  3 files changed, 225 insertions(+)
>  create mode 100644 drivers/hwmon/altera-a10sr-hwmon.c
> 
> diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
> index ff94007..af08846 100644
> --- a/drivers/hwmon/Kconfig
> +++ b/drivers/hwmon/Kconfig
> @@ -248,6 +248,15 @@ config SENSORS_ADT7475
>  	  This driver can also be build as a module.  If so, the module
>  	  will be called adt7475.
>  
> +config SENSORS_ALTERA_A10SR
> +	bool "Altera Arria10 System Status"
> +	depends on MFD_ALTERA_A10SR
> +	help
> +	  If you say yes here you get support for the power ready status
> +	  for the Arria10's external power supplies on the Arria10 DevKit.
> +	  These values are read over the SPI bus from the Arria10 System
> +	  Resource chip.
> +
>  config SENSORS_ASC7621
>  	tristate "Andigilog aSC7621"
>  	depends on I2C
> diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
> index 2ef5b7c..17d72a7 100644
> --- a/drivers/hwmon/Makefile
> +++ b/drivers/hwmon/Makefile
> @@ -43,6 +43,7 @@ obj-$(CONFIG_SENSORS_ADT7411)	+= adt7411.o
>  obj-$(CONFIG_SENSORS_ADT7462)	+= adt7462.o
>  obj-$(CONFIG_SENSORS_ADT7470)	+= adt7470.o
>  obj-$(CONFIG_SENSORS_ADT7475)	+= adt7475.o
> +obj-$(CONFIG_SENSORS_ALTERA_A10SR) += altera-a10sr-hwmon.o
>  obj-$(CONFIG_SENSORS_APPLESMC)	+= applesmc.o
>  obj-$(CONFIG_SENSORS_ARM_SCPI)	+= scpi-hwmon.o
>  obj-$(CONFIG_SENSORS_ASC7621)	+= asc7621.o
> diff --git a/drivers/hwmon/altera-a10sr-hwmon.c b/drivers/hwmon/altera-a10sr-hwmon.c
> new file mode 100644
> index 0000000..1eecc6b
> --- /dev/null
> +++ b/drivers/hwmon/altera-a10sr-hwmon.c
> @@ -0,0 +1,215 @@
> +/*
> + *  Copyright Altera Corporation (C) 2014-2016. All Rights Reserved
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program.  If not, see <http://www.gnu.org/licenses/>.
> + *
> + * HW Monitor driver for  Altera Arria10 MAX5 System Resource Chip
> + * Adapted from DA9052
> + */
> +
> +#include <linux/hwmon.h>
> +#include <linux/hwmon-sysfs.h>
> +#include <linux/mfd/altera-a10sr.h>
> +#include <linux/module.h>
> +#include <linux/of.h>

Please list include files in alphabetic order.

> +
> +#define ALTR_A10SR_1V0_BIT_POS          ALTR_A10SR_PG1_1V0_SHIFT
> +#define ALTR_A10SR_0V95_BIT_POS         ALTR_A10SR_PG1_0V95_SHIFT
> +#define ALTR_A10SR_0V9_BIT_POS          ALTR_A10SR_PG1_0V9_SHIFT
> +#define ALTR_A10SR_10V_BIT_POS          ALTR_A10SR_PG1_10V_SHIFT
> +#define ALTR_A10SR_5V0_BIT_POS          ALTR_A10SR_PG1_5V0_SHIFT
> +#define ALTR_A10SR_3V3_BIT_POS          ALTR_A10SR_PG1_3V3_SHIFT
> +#define ALTR_A10SR_2V5_BIT_POS          ALTR_A10SR_PG1_2V5_SHIFT
> +#define ALTR_A10SR_1V8_BIT_POS          ALTR_A10SR_PG1_1V8_SHIFT
> +#define ALTR_A10SR_OP_FLAG_BIT_POS      ALTR_A10SR_PG1_OP_FLAG_SHIFT
> +/* 2nd register needs an offset of 8 to get to 2nd register */
> +#define ALTR_A10SR_FBC2MP_BIT_POS       (8 + ALTR_A10SR_PG2_FBC2MP_SHIFT)
> +#define ALTR_A10SR_FAC2MP_BIT_POS       (8 + ALTR_A10SR_PG2_FAC2MP_SHIFT)
> +#define ALTR_A10SR_FMCBVADJ_BIT_POS     (8 + ALTR_A10SR_PG2_FMCBVADJ_SHIFT)
> +#define ALTR_A10SR_FMCAVADJ_BIT_POS     (8 + ALTR_A10SR_PG2_FMCAVADJ_SHIFT)
> +#define ALTR_A10SR_HL_VDDQ_BIT_POS      (8 + ALTR_A10SR_PG2_HL_VDDQ_SHIFT)
> +#define ALTR_A10SR_HL_VDD_BIT_POS       (8 + ALTR_A10SR_PG2_HL_VDD_SHIFT)
> +#define ALTR_A10SR_HL_HPS_BIT_POS       (8 + ALTR_A10SR_PG2_HL_HPS_SHIFT)
> +#define ALTR_A10SR_HPS_BIT_POS          (8 + ALTR_A10SR_PG2_HPS_SHIFT)
> +/* 3rd register needs an offset of 16 to get to 3rd register */
> +#define ALTR_A10SR_10V_FAIL_BIT_POS     (16 + ALTR_A10SR_PG3_10V_FAIL_SHIFT)
> +#define ALTR_A10SR_FAM2C_BIT_POS        (16 + ALTR_A10SR_PG3_FAM2C_SHIFT)
> +
> +/**
> + * struct altr_a10sr_hwmon - Altera Max5 HWMON device private data structure
> + * @device: hwmon class.
> + * @regmap: the regmap from the parent device.
> + */
> +struct altr_a10sr_hwmon {
> +	struct device		*class_device;
> +	struct regmap		*regmap;
> +};
> +
> +static ssize_t altr_a10sr_read_status(struct device *dev,
> +				      struct device_attribute *devattr,
> +				      char *buf)
> +{
> +	struct altr_a10sr_hwmon *hwmon = dev_get_drvdata(dev);
> +	int val, ret, index = to_sensor_dev_attr(devattr)->index;
> +	int mask = ALTR_A10SR_REG_BIT_MASK(index);
> +	unsigned char reg = ALTR_A10SR_PWR_GOOD1_REG +
> +			    ALTR_A10SR_REG_OFFSET(index);
> +
> +	ret = regmap_read(hwmon->regmap, reg, &val);

The pointer parameter to regmap_read() is unsigned int. I would suggest
to use the same variable type to avoid surprises.

> +	if (ret < 0)
> +		return ret;
> +
> +	return sprintf(buf, "%d\n", !!(~val & mask));

Are alarms all active low ?

> +}
> +
> +static ssize_t altr_a10sr_hwmon_show_name(struct device *dev,
> +					  struct device_attribute *devattr,
> +					  char *buf)
> +{
> +	return sprintf(buf, "altr_a10sr\n");
> +}
> +
> +/* First Power Good Register Bits */
> +static SENSOR_DEVICE_ATTR(1v0_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
> +			  ALTR_A10SR_1V0_BIT_POS);
> +static SENSOR_DEVICE_ATTR(0v95_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
> +			  ALTR_A10SR_0V95_BIT_POS);
> +static SENSOR_DEVICE_ATTR(0v9_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
> +			  ALTR_A10SR_0V9_BIT_POS);
> +static SENSOR_DEVICE_ATTR(5v0_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
> +			  ALTR_A10SR_5V0_BIT_POS);
> +static SENSOR_DEVICE_ATTR(3v3_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
> +			  ALTR_A10SR_3V3_BIT_POS);
> +static SENSOR_DEVICE_ATTR(2v5_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
> +			  ALTR_A10SR_2V5_BIT_POS);
> +static SENSOR_DEVICE_ATTR(1v8_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
> +			  ALTR_A10SR_1V8_BIT_POS);
> +static SENSOR_DEVICE_ATTR(opflag_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
> +			  ALTR_A10SR_OP_FLAG_BIT_POS);
> +/* Second Power Good Register Bits */
> +static SENSOR_DEVICE_ATTR(fbc2mp_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
> +			  ALTR_A10SR_FBC2MP_BIT_POS);
> +static SENSOR_DEVICE_ATTR(fac2mp_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
> +			  ALTR_A10SR_FAC2MP_BIT_POS);
> +static SENSOR_DEVICE_ATTR(fmcbvadj_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
> +			  ALTR_A10SR_FMCBVADJ_BIT_POS);
> +static SENSOR_DEVICE_ATTR(fmcavadj_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
> +			  ALTR_A10SR_FMCAVADJ_BIT_POS);
> +static SENSOR_DEVICE_ATTR(hl_vddq_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
> +			  ALTR_A10SR_HL_VDDQ_BIT_POS);
> +static SENSOR_DEVICE_ATTR(hl_vdd_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
> +			  ALTR_A10SR_HL_VDD_BIT_POS);
> +static SENSOR_DEVICE_ATTR(hlhps_vdd_alarm, S_IRUGO, altr_a10sr_read_status,
> +			  NULL, ALTR_A10SR_HL_HPS_BIT_POS);
> +static SENSOR_DEVICE_ATTR(hps_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
> +			  ALTR_A10SR_HPS_BIT_POS);
> +/* Third Power Good Register Bits */
> +static SENSOR_DEVICE_ATTR(10v_alarm, S_IRUGO, altr_a10sr_read_status,
> +			  NULL, ALTR_A10SR_10V_FAIL_BIT_POS);
> +static SENSOR_DEVICE_ATTR(fam2c_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
> +			  ALTR_A10SR_FAM2C_BIT_POS);
> +
> +static DEVICE_ATTR(name, S_IRUGO, altr_a10sr_hwmon_show_name, NULL);
> +
> +static struct attribute *altr_a10sr_attr[] = {
> +	&dev_attr_name.attr,
> +	/* First Power Good Register */
> +	&sensor_dev_attr_opflag_alarm.dev_attr.attr,
> +	&sensor_dev_attr_1v8_alarm.dev_attr.attr,
> +	&sensor_dev_attr_2v5_alarm.dev_attr.attr,
> +	&sensor_dev_attr_1v0_alarm.dev_attr.attr,
> +	&sensor_dev_attr_3v3_alarm.dev_attr.attr,
> +	&sensor_dev_attr_5v0_alarm.dev_attr.attr,
> +	&sensor_dev_attr_0v9_alarm.dev_attr.attr,
> +	&sensor_dev_attr_0v95_alarm.dev_attr.attr,
> +	/* Second Power Good Register */
> +	&sensor_dev_attr_hps_alarm.dev_attr.attr,
> +	&sensor_dev_attr_hlhps_vdd_alarm.dev_attr.attr,
> +	&sensor_dev_attr_hl_vdd_alarm.dev_attr.attr,
> +	&sensor_dev_attr_hl_vddq_alarm.dev_attr.attr,
> +	&sensor_dev_attr_fmcavadj_alarm.dev_attr.attr,
> +	&sensor_dev_attr_fmcbvadj_alarm.dev_attr.attr,
> +	&sensor_dev_attr_fac2mp_alarm.dev_attr.attr,
> +	&sensor_dev_attr_fbc2mp_alarm.dev_attr.attr,
> +	/* Third Power Good Register */
> +	&sensor_dev_attr_10v_alarm.dev_attr.attr,
> +	&sensor_dev_attr_fam2c_alarm.dev_attr.attr,

Ultimately, this doesn't really make much sense, even with standard attribute
names. The ABI assumes that _input attrributes exist. Not sure if that could
be solved by providing 'dummy' unreadable input attributes (permission 0);
that might be worth a try. If you want to attach names to the attributes,
you would need to provide label attributes. Specifically you would need

	inX_input (with permission 0) - not sure if that is even possible
	inX_alarm
	inX_label

> +	NULL
> +};
> +
> +static const struct attribute_group altr_a10sr_attr_group = {
> +	.attrs = altr_a10sr_attr
> +};
> +
> +static int altr_a10sr_hwmon_probe(struct platform_device *pdev)
> +{
> +	struct altr_a10sr_hwmon *hwmon;
> +	int ret;
> +	struct altr_a10sr *a10sr = dev_get_drvdata(pdev->dev.parent);
> +

What if someone creates a stand-alone devicetree property for this driver,
and there is no parent (or parent driver data) ?

> +	hwmon = devm_kzalloc(&pdev->dev, sizeof(*hwmon), GFP_KERNEL);
> +	if (!hwmon)
> +		return -ENOMEM;
> +
> +	hwmon->regmap = a10sr->regmap;
> +
> +	platform_set_drvdata(pdev, hwmon);
> +
> +	ret = sysfs_create_group(&pdev->dev.kobj, &altr_a10sr_attr_group);
> +	if (ret)
> +		goto err_mem;
> +
> +	hwmon->class_device = hwmon_device_register(&pdev->dev);
> +	if (IS_ERR(hwmon->class_device)) {
> +		ret = PTR_ERR(hwmon->class_device);
> +		goto err_sysfs;
> +	}

Please use devm_hwmon_device_register_with_groups().

> +
> +	return 0;
> +
> +err_sysfs:
> +	sysfs_remove_group(&pdev->dev.kobj, &altr_a10sr_attr_group);
> +err_mem:
> +	return ret;
> +}
> +
> +static int altr_a10sr_hwmon_remove(struct platform_device *pdev)
> +{
> +	struct altr_a10sr_hwmon *hwmon = platform_get_drvdata(pdev);
> +
> +	hwmon_device_unregister(hwmon->class_device);
> +	sysfs_remove_group(&pdev->dev.kobj, &altr_a10sr_attr_group);
> +
> +	return 0;
> +}
> +
> +static const struct of_device_id altr_a10sr_hwmon_of_match[] = {
> +	{ .compatible = "altr,a10sr-hwmon" },
> +	{ },
> +};
> +MODULE_DEVICE_TABLE(of, altr_a10sr_hwmon_of_match);
> +
> +static struct platform_driver altr_a10sr_hwmon_driver = {
> +	.probe = altr_a10sr_hwmon_probe,
> +	.remove = altr_a10sr_hwmon_remove,
> +	.driver = {
> +		.name = "altr_a10sr_hwmon",
> +		.of_match_table = of_match_ptr(altr_a10sr_hwmon_of_match),
> +	},
> +};
> +
> +module_platform_driver(altr_a10sr_hwmon_driver);
> +
> +MODULE_LICENSE("GPL v2");
> +MODULE_AUTHOR("Thor Thayer <tthayer@opensource.altera.com>");
> +MODULE_DESCRIPTION("HW Monitor driver for Altera Arria10 System Resource Chip");
> -- 
> 1.7.9.5
> 

Re: [PATCH 10/11] hwmon: Add Altera A10-SR power supply alarms

[Guenter Roeck]

On Fri, Apr 22, 2016 at 10:33:38AM -0500, ttha...@opensource.altera.com wrote:
> From: Thor Thayer <ttha...@opensource.altera.com>
> 
> This patch adds the power supply alarms of the hwmon framework
> to the Arria10 System Resource chip.
> 
> Signed-off-by: Thor Thayer <ttha...@opensource.altera.com>
> ---

Please read and follow Documentation/hwmon/sysfs-interface 
as well as Documentation/hwmon/submitting-patches. At the very least,
you are expected to document your driver, and you are expected to
use standard attribute names.

>  drivers/hwmon/Kconfig              |    9 ++
>  drivers/hwmon/Makefile             |    1 +
>  drivers/hwmon/altera-a10sr-hwmon.c |  215 
> ++++++++++++++++++++++++++++++++++++
>  3 files changed, 225 insertions(+)
>  create mode 100644 drivers/hwmon/altera-a10sr-hwmon.c
> 
> diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
> index ff94007..af08846 100644
> --- a/drivers/hwmon/Kconfig
> +++ b/drivers/hwmon/Kconfig
> @@ -248,6 +248,15 @@ config SENSORS_ADT7475
>         This driver can also be build as a module.  If so, the module
>         will be called adt7475.
>  
> +config SENSORS_ALTERA_A10SR
> +     bool "Altera Arria10 System Status"
> +     depends on MFD_ALTERA_A10SR
> +     help
> +       If you say yes here you get support for the power ready status
> +       for the Arria10's external power supplies on the Arria10 DevKit.
> +       These values are read over the SPI bus from the Arria10 System
> +       Resource chip.
> +
>  config SENSORS_ASC7621
>       tristate "Andigilog aSC7621"
>       depends on I2C
> diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
> index 2ef5b7c..17d72a7 100644
> --- a/drivers/hwmon/Makefile
> +++ b/drivers/hwmon/Makefile
> @@ -43,6 +43,7 @@ obj-$(CONFIG_SENSORS_ADT7411)       += adt7411.o
>  obj-$(CONFIG_SENSORS_ADT7462)        += adt7462.o
>  obj-$(CONFIG_SENSORS_ADT7470)        += adt7470.o
>  obj-$(CONFIG_SENSORS_ADT7475)        += adt7475.o
> +obj-$(CONFIG_SENSORS_ALTERA_A10SR) += altera-a10sr-hwmon.o
>  obj-$(CONFIG_SENSORS_APPLESMC)       += applesmc.o
>  obj-$(CONFIG_SENSORS_ARM_SCPI)       += scpi-hwmon.o
>  obj-$(CONFIG_SENSORS_ASC7621)        += asc7621.o
> diff --git a/drivers/hwmon/altera-a10sr-hwmon.c 
> b/drivers/hwmon/altera-a10sr-hwmon.c
> new file mode 100644
> index 0000000..1eecc6b
> --- /dev/null
> +++ b/drivers/hwmon/altera-a10sr-hwmon.c
> @@ -0,0 +1,215 @@
> +/*
> + *  Copyright Altera Corporation (C) 2014-2016. All Rights Reserved
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along 
> with
> + * this program.  If not, see <http://www.gnu.org/licenses/>.
> + *
> + * HW Monitor driver for  Altera Arria10 MAX5 System Resource Chip
> + * Adapted from DA9052
> + */
> +
> +#include <linux/hwmon.h>
> +#include <linux/hwmon-sysfs.h>
> +#include <linux/mfd/altera-a10sr.h>
> +#include <linux/module.h>
> +#include <linux/of.h>

Please list include files in alphabetic order.

> +
> +#define ALTR_A10SR_1V0_BIT_POS          ALTR_A10SR_PG1_1V0_SHIFT
> +#define ALTR_A10SR_0V95_BIT_POS         ALTR_A10SR_PG1_0V95_SHIFT
> +#define ALTR_A10SR_0V9_BIT_POS          ALTR_A10SR_PG1_0V9_SHIFT
> +#define ALTR_A10SR_10V_BIT_POS          ALTR_A10SR_PG1_10V_SHIFT
> +#define ALTR_A10SR_5V0_BIT_POS          ALTR_A10SR_PG1_5V0_SHIFT
> +#define ALTR_A10SR_3V3_BIT_POS          ALTR_A10SR_PG1_3V3_SHIFT
> +#define ALTR_A10SR_2V5_BIT_POS          ALTR_A10SR_PG1_2V5_SHIFT
> +#define ALTR_A10SR_1V8_BIT_POS          ALTR_A10SR_PG1_1V8_SHIFT
> +#define ALTR_A10SR_OP_FLAG_BIT_POS      ALTR_A10SR_PG1_OP_FLAG_SHIFT
> +/* 2nd register needs an offset of 8 to get to 2nd register */
> +#define ALTR_A10SR_FBC2MP_BIT_POS       (8 + ALTR_A10SR_PG2_FBC2MP_SHIFT)
> +#define ALTR_A10SR_FAC2MP_BIT_POS       (8 + ALTR_A10SR_PG2_FAC2MP_SHIFT)
> +#define ALTR_A10SR_FMCBVADJ_BIT_POS     (8 + ALTR_A10SR_PG2_FMCBVADJ_SHIFT)
> +#define ALTR_A10SR_FMCAVADJ_BIT_POS     (8 + ALTR_A10SR_PG2_FMCAVADJ_SHIFT)
> +#define ALTR_A10SR_HL_VDDQ_BIT_POS      (8 + ALTR_A10SR_PG2_HL_VDDQ_SHIFT)
> +#define ALTR_A10SR_HL_VDD_BIT_POS       (8 + ALTR_A10SR_PG2_HL_VDD_SHIFT)
> +#define ALTR_A10SR_HL_HPS_BIT_POS       (8 + ALTR_A10SR_PG2_HL_HPS_SHIFT)
> +#define ALTR_A10SR_HPS_BIT_POS          (8 + ALTR_A10SR_PG2_HPS_SHIFT)
> +/* 3rd register needs an offset of 16 to get to 3rd register */
> +#define ALTR_A10SR_10V_FAIL_BIT_POS     (16 + ALTR_A10SR_PG3_10V_FAIL_SHIFT)
> +#define ALTR_A10SR_FAM2C_BIT_POS        (16 + ALTR_A10SR_PG3_FAM2C_SHIFT)
> +
> +/**
> + * struct altr_a10sr_hwmon - Altera Max5 HWMON device private data structure
> + * @device: hwmon class.
> + * @regmap: the regmap from the parent device.
> + */
> +struct altr_a10sr_hwmon {
> +     struct device           *class_device;
> +     struct regmap           *regmap;
> +};
> +
> +static ssize_t altr_a10sr_read_status(struct device *dev,
> +                                   struct device_attribute *devattr,
> +                                   char *buf)
> +{
> +     struct altr_a10sr_hwmon *hwmon = dev_get_drvdata(dev);
> +     int val, ret, index = to_sensor_dev_attr(devattr)->index;
> +     int mask = ALTR_A10SR_REG_BIT_MASK(index);
> +     unsigned char reg = ALTR_A10SR_PWR_GOOD1_REG +
> +                         ALTR_A10SR_REG_OFFSET(index);
> +
> +     ret = regmap_read(hwmon->regmap, reg, &val);

The pointer parameter to regmap_read() is unsigned int. I would suggest
to use the same variable type to avoid surprises.

> +     if (ret < 0)
> +             return ret;
> +
> +     return sprintf(buf, "%d\n", !!(~val & mask));

Are alarms all active low ?

> +}
> +
> +static ssize_t altr_a10sr_hwmon_show_name(struct device *dev,
> +                                       struct device_attribute *devattr,
> +                                       char *buf)
> +{
> +     return sprintf(buf, "altr_a10sr\n");
> +}
> +
> +/* First Power Good Register Bits */
> +static SENSOR_DEVICE_ATTR(1v0_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
> +                       ALTR_A10SR_1V0_BIT_POS);
> +static SENSOR_DEVICE_ATTR(0v95_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
> +                       ALTR_A10SR_0V95_BIT_POS);
> +static SENSOR_DEVICE_ATTR(0v9_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
> +                       ALTR_A10SR_0V9_BIT_POS);
> +static SENSOR_DEVICE_ATTR(5v0_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
> +                       ALTR_A10SR_5V0_BIT_POS);
> +static SENSOR_DEVICE_ATTR(3v3_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
> +                       ALTR_A10SR_3V3_BIT_POS);
> +static SENSOR_DEVICE_ATTR(2v5_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
> +                       ALTR_A10SR_2V5_BIT_POS);
> +static SENSOR_DEVICE_ATTR(1v8_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
> +                       ALTR_A10SR_1V8_BIT_POS);
> +static SENSOR_DEVICE_ATTR(opflag_alarm, S_IRUGO, altr_a10sr_read_status, 
> NULL,
> +                       ALTR_A10SR_OP_FLAG_BIT_POS);
> +/* Second Power Good Register Bits */
> +static SENSOR_DEVICE_ATTR(fbc2mp_alarm, S_IRUGO, altr_a10sr_read_status, 
> NULL,
> +                       ALTR_A10SR_FBC2MP_BIT_POS);
> +static SENSOR_DEVICE_ATTR(fac2mp_alarm, S_IRUGO, altr_a10sr_read_status, 
> NULL,
> +                       ALTR_A10SR_FAC2MP_BIT_POS);
> +static SENSOR_DEVICE_ATTR(fmcbvadj_alarm, S_IRUGO, altr_a10sr_read_status, 
> NULL,
> +                       ALTR_A10SR_FMCBVADJ_BIT_POS);
> +static SENSOR_DEVICE_ATTR(fmcavadj_alarm, S_IRUGO, altr_a10sr_read_status, 
> NULL,
> +                       ALTR_A10SR_FMCAVADJ_BIT_POS);
> +static SENSOR_DEVICE_ATTR(hl_vddq_alarm, S_IRUGO, altr_a10sr_read_status, 
> NULL,
> +                       ALTR_A10SR_HL_VDDQ_BIT_POS);
> +static SENSOR_DEVICE_ATTR(hl_vdd_alarm, S_IRUGO, altr_a10sr_read_status, 
> NULL,
> +                       ALTR_A10SR_HL_VDD_BIT_POS);
> +static SENSOR_DEVICE_ATTR(hlhps_vdd_alarm, S_IRUGO, altr_a10sr_read_status,
> +                       NULL, ALTR_A10SR_HL_HPS_BIT_POS);
> +static SENSOR_DEVICE_ATTR(hps_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
> +                       ALTR_A10SR_HPS_BIT_POS);
> +/* Third Power Good Register Bits */
> +static SENSOR_DEVICE_ATTR(10v_alarm, S_IRUGO, altr_a10sr_read_status,
> +                       NULL, ALTR_A10SR_10V_FAIL_BIT_POS);
> +static SENSOR_DEVICE_ATTR(fam2c_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
> +                       ALTR_A10SR_FAM2C_BIT_POS);
> +
> +static DEVICE_ATTR(name, S_IRUGO, altr_a10sr_hwmon_show_name, NULL);
> +
> +static struct attribute *altr_a10sr_attr[] = {
> +     &dev_attr_name.attr,
> +     /* First Power Good Register */
> +     &sensor_dev_attr_opflag_alarm.dev_attr.attr,
> +     &sensor_dev_attr_1v8_alarm.dev_attr.attr,
> +     &sensor_dev_attr_2v5_alarm.dev_attr.attr,
> +     &sensor_dev_attr_1v0_alarm.dev_attr.attr,
> +     &sensor_dev_attr_3v3_alarm.dev_attr.attr,
> +     &sensor_dev_attr_5v0_alarm.dev_attr.attr,
> +     &sensor_dev_attr_0v9_alarm.dev_attr.attr,
> +     &sensor_dev_attr_0v95_alarm.dev_attr.attr,
> +     /* Second Power Good Register */
> +     &sensor_dev_attr_hps_alarm.dev_attr.attr,
> +     &sensor_dev_attr_hlhps_vdd_alarm.dev_attr.attr,
> +     &sensor_dev_attr_hl_vdd_alarm.dev_attr.attr,
> +     &sensor_dev_attr_hl_vddq_alarm.dev_attr.attr,
> +     &sensor_dev_attr_fmcavadj_alarm.dev_attr.attr,
> +     &sensor_dev_attr_fmcbvadj_alarm.dev_attr.attr,
> +     &sensor_dev_attr_fac2mp_alarm.dev_attr.attr,
> +     &sensor_dev_attr_fbc2mp_alarm.dev_attr.attr,
> +     /* Third Power Good Register */
> +     &sensor_dev_attr_10v_alarm.dev_attr.attr,
> +     &sensor_dev_attr_fam2c_alarm.dev_attr.attr,

Ultimately, this doesn't really make much sense, even with standard attribute
names. The ABI assumes that _input attrributes exist. Not sure if that could
be solved by providing 'dummy' unreadable input attributes (permission 0);
that might be worth a try. If you want to attach names to the attributes,
you would need to provide label attributes. Specifically you would need

        inX_input (with permission 0) - not sure if that is even possible
        inX_alarm
        inX_label

> +     NULL
> +};
> +
> +static const struct attribute_group altr_a10sr_attr_group = {
> +     .attrs = altr_a10sr_attr
> +};
> +
> +static int altr_a10sr_hwmon_probe(struct platform_device *pdev)
> +{
> +     struct altr_a10sr_hwmon *hwmon;
> +     int ret;
> +     struct altr_a10sr *a10sr = dev_get_drvdata(pdev->dev.parent);
> +

What if someone creates a stand-alone devicetree property for this driver,
and there is no parent (or parent driver data) ?

> +     hwmon = devm_kzalloc(&pdev->dev, sizeof(*hwmon), GFP_KERNEL);
> +     if (!hwmon)
> +             return -ENOMEM;
> +
> +     hwmon->regmap = a10sr->regmap;
> +
> +     platform_set_drvdata(pdev, hwmon);
> +
> +     ret = sysfs_create_group(&pdev->dev.kobj, &altr_a10sr_attr_group);
> +     if (ret)
> +             goto err_mem;
> +
> +     hwmon->class_device = hwmon_device_register(&pdev->dev);
> +     if (IS_ERR(hwmon->class_device)) {
> +             ret = PTR_ERR(hwmon->class_device);
> +             goto err_sysfs;
> +     }

Please use devm_hwmon_device_register_with_groups().

> +
> +     return 0;
> +
> +err_sysfs:
> +     sysfs_remove_group(&pdev->dev.kobj, &altr_a10sr_attr_group);
> +err_mem:
> +     return ret;
> +}
> +
> +static int altr_a10sr_hwmon_remove(struct platform_device *pdev)
> +{
> +     struct altr_a10sr_hwmon *hwmon = platform_get_drvdata(pdev);
> +
> +     hwmon_device_unregister(hwmon->class_device);
> +     sysfs_remove_group(&pdev->dev.kobj, &altr_a10sr_attr_group);
> +
> +     return 0;
> +}
> +
> +static const struct of_device_id altr_a10sr_hwmon_of_match[] = {
> +     { .compatible = "altr,a10sr-hwmon" },
> +     { },
> +};
> +MODULE_DEVICE_TABLE(of, altr_a10sr_hwmon_of_match);
> +
> +static struct platform_driver altr_a10sr_hwmon_driver = {
> +     .probe = altr_a10sr_hwmon_probe,
> +     .remove = altr_a10sr_hwmon_remove,
> +     .driver = {
> +             .name = "altr_a10sr_hwmon",
> +             .of_match_table = of_match_ptr(altr_a10sr_hwmon_of_match),
> +     },
> +};
> +
> +module_platform_driver(altr_a10sr_hwmon_driver);
> +
> +MODULE_LICENSE("GPL v2");
> +MODULE_AUTHOR("Thor Thayer <ttha...@opensource.altera.com>");
> +MODULE_DESCRIPTION("HW Monitor driver for Altera Arria10 System Resource 
> Chip");
> -- 
> 1.7.9.5
> 
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Re: [PATCH 10/11] hwmon: Add Altera A10-SR power supply alarms

[Thor Thayer]

On 04/22/2016 05:24 PM, Guenter Roeck wrote:
> On Fri, Apr 22, 2016 at 10:33:38AM -0500, tthayer@opensource.altera.com wrote:
>> From: Thor Thayer <tthayer@opensource.altera.com>
>>
>> This patch adds the power supply alarms of the hwmon framework
>> to the Arria10 System Resource chip.
>>
>> Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
>> ---
>
> Please read and follow Documentation/hwmon/sysfs-interface
> as well as Documentation/hwmon/submitting-patches. At the very least,
> you are expected to document your driver, and you are expected to
> use standard attribute names.
>

OK. I misunderstood. The standard attribute names would be 
power[1-*]_alarm and the binding documentation the a10sr-hwmon portion 
for MFD doesn't cover this.

>>   drivers/hwmon/Kconfig              |    9 ++
>>   drivers/hwmon/Makefile             |    1 +
>>   drivers/hwmon/altera-a10sr-hwmon.c |  215 ++++++++++++++++++++++++++++++++++++
>>   3 files changed, 225 insertions(+)
>>   create mode 100644 drivers/hwmon/altera-a10sr-hwmon.c
>>
>> diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
>> index ff94007..af08846 100644
>> --- a/drivers/hwmon/Kconfig
>> +++ b/drivers/hwmon/Kconfig
>> @@ -248,6 +248,15 @@ config SENSORS_ADT7475
>>   	  This driver can also be build as a module.  If so, the module
>>   	  will be called adt7475.
>>
>> +config SENSORS_ALTERA_A10SR
>> +	bool "Altera Arria10 System Status"
>> +	depends on MFD_ALTERA_A10SR
>> +	help
>> +	  If you say yes here you get support for the power ready status
>> +	  for the Arria10's external power supplies on the Arria10 DevKit.
>> +	  These values are read over the SPI bus from the Arria10 System
>> +	  Resource chip.
>> +
>>   config SENSORS_ASC7621
>>   	tristate "Andigilog aSC7621"
>>   	depends on I2C
>> diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
>> index 2ef5b7c..17d72a7 100644
>> --- a/drivers/hwmon/Makefile
>> +++ b/drivers/hwmon/Makefile
>> @@ -43,6 +43,7 @@ obj-$(CONFIG_SENSORS_ADT7411)	+= adt7411.o
>>   obj-$(CONFIG_SENSORS_ADT7462)	+= adt7462.o
>>   obj-$(CONFIG_SENSORS_ADT7470)	+= adt7470.o
>>   obj-$(CONFIG_SENSORS_ADT7475)	+= adt7475.o
>> +obj-$(CONFIG_SENSORS_ALTERA_A10SR) += altera-a10sr-hwmon.o
>>   obj-$(CONFIG_SENSORS_APPLESMC)	+= applesmc.o
>>   obj-$(CONFIG_SENSORS_ARM_SCPI)	+= scpi-hwmon.o
>>   obj-$(CONFIG_SENSORS_ASC7621)	+= asc7621.o
>> diff --git a/drivers/hwmon/altera-a10sr-hwmon.c b/drivers/hwmon/altera-a10sr-hwmon.c
>> new file mode 100644
>> index 0000000..1eecc6b
>> --- /dev/null
>> +++ b/drivers/hwmon/altera-a10sr-hwmon.c
>> @@ -0,0 +1,215 @@
>> +/*
>> + *  Copyright Altera Corporation (C) 2014-2016. All Rights Reserved
>> + *
>> + * This program is free software; you can redistribute it and/or modify it
>> + * under the terms and conditions of the GNU General Public License,
>> + * version 2, as published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope it will be useful, but WITHOUT
>> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
>> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
>> + * more details.
>> + *
>> + * You should have received a copy of the GNU General Public License along with
>> + * this program.  If not, see <http://www.gnu.org/licenses/>.
>> + *
>> + * HW Monitor driver for  Altera Arria10 MAX5 System Resource Chip
>> + * Adapted from DA9052
>> + */
>> +
>> +#include <linux/hwmon.h>
>> +#include <linux/hwmon-sysfs.h>
>> +#include <linux/mfd/altera-a10sr.h>
>> +#include <linux/module.h>
>> +#include <linux/of.h>
>
> Please list include files in alphabetic order.
>

OK. I thought this was in alphabetical order. I'll update this after 
figuring out where I was wrong.

>> +
>> +#define ALTR_A10SR_1V0_BIT_POS          ALTR_A10SR_PG1_1V0_SHIFT
>> +#define ALTR_A10SR_0V95_BIT_POS         ALTR_A10SR_PG1_0V95_SHIFT
>> +#define ALTR_A10SR_0V9_BIT_POS          ALTR_A10SR_PG1_0V9_SHIFT
>> +#define ALTR_A10SR_10V_BIT_POS          ALTR_A10SR_PG1_10V_SHIFT
>> +#define ALTR_A10SR_5V0_BIT_POS          ALTR_A10SR_PG1_5V0_SHIFT
>> +#define ALTR_A10SR_3V3_BIT_POS          ALTR_A10SR_PG1_3V3_SHIFT
>> +#define ALTR_A10SR_2V5_BIT_POS          ALTR_A10SR_PG1_2V5_SHIFT
>> +#define ALTR_A10SR_1V8_BIT_POS          ALTR_A10SR_PG1_1V8_SHIFT
>> +#define ALTR_A10SR_OP_FLAG_BIT_POS      ALTR_A10SR_PG1_OP_FLAG_SHIFT
>> +/* 2nd register needs an offset of 8 to get to 2nd register */
>> +#define ALTR_A10SR_FBC2MP_BIT_POS       (8 + ALTR_A10SR_PG2_FBC2MP_SHIFT)
>> +#define ALTR_A10SR_FAC2MP_BIT_POS       (8 + ALTR_A10SR_PG2_FAC2MP_SHIFT)
>> +#define ALTR_A10SR_FMCBVADJ_BIT_POS     (8 + ALTR_A10SR_PG2_FMCBVADJ_SHIFT)
>> +#define ALTR_A10SR_FMCAVADJ_BIT_POS     (8 + ALTR_A10SR_PG2_FMCAVADJ_SHIFT)
>> +#define ALTR_A10SR_HL_VDDQ_BIT_POS      (8 + ALTR_A10SR_PG2_HL_VDDQ_SHIFT)
>> +#define ALTR_A10SR_HL_VDD_BIT_POS       (8 + ALTR_A10SR_PG2_HL_VDD_SHIFT)
>> +#define ALTR_A10SR_HL_HPS_BIT_POS       (8 + ALTR_A10SR_PG2_HL_HPS_SHIFT)
>> +#define ALTR_A10SR_HPS_BIT_POS          (8 + ALTR_A10SR_PG2_HPS_SHIFT)
>> +/* 3rd register needs an offset of 16 to get to 3rd register */
>> +#define ALTR_A10SR_10V_FAIL_BIT_POS     (16 + ALTR_A10SR_PG3_10V_FAIL_SHIFT)
>> +#define ALTR_A10SR_FAM2C_BIT_POS        (16 + ALTR_A10SR_PG3_FAM2C_SHIFT)
>> +
>> +/**
>> + * struct altr_a10sr_hwmon - Altera Max5 HWMON device private data structure
>> + * @device: hwmon class.
>> + * @regmap: the regmap from the parent device.
>> + */
>> +struct altr_a10sr_hwmon {
>> +	struct device		*class_device;
>> +	struct regmap		*regmap;
>> +};
>> +
>> +static ssize_t altr_a10sr_read_status(struct device *dev,
>> +				      struct device_attribute *devattr,
>> +				      char *buf)
>> +{
>> +	struct altr_a10sr_hwmon *hwmon = dev_get_drvdata(dev);
>> +	int val, ret, index = to_sensor_dev_attr(devattr)->index;
>> +	int mask = ALTR_A10SR_REG_BIT_MASK(index);
>> +	unsigned char reg = ALTR_A10SR_PWR_GOOD1_REG +
>> +			    ALTR_A10SR_REG_OFFSET(index);
>> +
>> +	ret = regmap_read(hwmon->regmap, reg, &val);
>
> The pointer parameter to regmap_read() is unsigned int. I would suggest
> to use the same variable type to avoid surprises.
>
Understood. Thanks.

>> +	if (ret < 0)
>> +		return ret;
>> +
>> +	return sprintf(buf, "%d\n", !!(~val & mask));
>
> Are alarms all active low ?
>
Yes, They are actually Power Good signals (Good = high) so I'm inverting.

>> +}
>> +
>> +static ssize_t altr_a10sr_hwmon_show_name(struct device *dev,
>> +					  struct device_attribute *devattr,
>> +					  char *buf)
>> +{
>> +	return sprintf(buf, "altr_a10sr\n");
>> +}
>> +
>> +/* First Power Good Register Bits */
>> +static SENSOR_DEVICE_ATTR(1v0_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
>> +			  ALTR_A10SR_1V0_BIT_POS);
>> +static SENSOR_DEVICE_ATTR(0v95_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
>> +			  ALTR_A10SR_0V95_BIT_POS);
>> +static SENSOR_DEVICE_ATTR(0v9_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
>> +			  ALTR_A10SR_0V9_BIT_POS);
>> +static SENSOR_DEVICE_ATTR(5v0_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
>> +			  ALTR_A10SR_5V0_BIT_POS);
>> +static SENSOR_DEVICE_ATTR(3v3_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
>> +			  ALTR_A10SR_3V3_BIT_POS);
>> +static SENSOR_DEVICE_ATTR(2v5_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
>> +			  ALTR_A10SR_2V5_BIT_POS);
>> +static SENSOR_DEVICE_ATTR(1v8_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
>> +			  ALTR_A10SR_1V8_BIT_POS);
>> +static SENSOR_DEVICE_ATTR(opflag_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
>> +			  ALTR_A10SR_OP_FLAG_BIT_POS);
>> +/* Second Power Good Register Bits */
>> +static SENSOR_DEVICE_ATTR(fbc2mp_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
>> +			  ALTR_A10SR_FBC2MP_BIT_POS);
>> +static SENSOR_DEVICE_ATTR(fac2mp_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
>> +			  ALTR_A10SR_FAC2MP_BIT_POS);
>> +static SENSOR_DEVICE_ATTR(fmcbvadj_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
>> +			  ALTR_A10SR_FMCBVADJ_BIT_POS);
>> +static SENSOR_DEVICE_ATTR(fmcavadj_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
>> +			  ALTR_A10SR_FMCAVADJ_BIT_POS);
>> +static SENSOR_DEVICE_ATTR(hl_vddq_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
>> +			  ALTR_A10SR_HL_VDDQ_BIT_POS);
>> +static SENSOR_DEVICE_ATTR(hl_vdd_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
>> +			  ALTR_A10SR_HL_VDD_BIT_POS);
>> +static SENSOR_DEVICE_ATTR(hlhps_vdd_alarm, S_IRUGO, altr_a10sr_read_status,
>> +			  NULL, ALTR_A10SR_HL_HPS_BIT_POS);
>> +static SENSOR_DEVICE_ATTR(hps_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
>> +			  ALTR_A10SR_HPS_BIT_POS);
>> +/* Third Power Good Register Bits */
>> +static SENSOR_DEVICE_ATTR(10v_alarm, S_IRUGO, altr_a10sr_read_status,
>> +			  NULL, ALTR_A10SR_10V_FAIL_BIT_POS);
>> +static SENSOR_DEVICE_ATTR(fam2c_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
>> +			  ALTR_A10SR_FAM2C_BIT_POS);
>> +
>> +static DEVICE_ATTR(name, S_IRUGO, altr_a10sr_hwmon_show_name, NULL);
>> +
>> +static struct attribute *altr_a10sr_attr[] = {
>> +	&dev_attr_name.attr,
>> +	/* First Power Good Register */
>> +	&sensor_dev_attr_opflag_alarm.dev_attr.attr,
>> +	&sensor_dev_attr_1v8_alarm.dev_attr.attr,
>> +	&sensor_dev_attr_2v5_alarm.dev_attr.attr,
>> +	&sensor_dev_attr_1v0_alarm.dev_attr.attr,
>> +	&sensor_dev_attr_3v3_alarm.dev_attr.attr,
>> +	&sensor_dev_attr_5v0_alarm.dev_attr.attr,
>> +	&sensor_dev_attr_0v9_alarm.dev_attr.attr,
>> +	&sensor_dev_attr_0v95_alarm.dev_attr.attr,
>> +	/* Second Power Good Register */
>> +	&sensor_dev_attr_hps_alarm.dev_attr.attr,
>> +	&sensor_dev_attr_hlhps_vdd_alarm.dev_attr.attr,
>> +	&sensor_dev_attr_hl_vdd_alarm.dev_attr.attr,
>> +	&sensor_dev_attr_hl_vddq_alarm.dev_attr.attr,
>> +	&sensor_dev_attr_fmcavadj_alarm.dev_attr.attr,
>> +	&sensor_dev_attr_fmcbvadj_alarm.dev_attr.attr,
>> +	&sensor_dev_attr_fac2mp_alarm.dev_attr.attr,
>> +	&sensor_dev_attr_fbc2mp_alarm.dev_attr.attr,
>> +	/* Third Power Good Register */
>> +	&sensor_dev_attr_10v_alarm.dev_attr.attr,
>> +	&sensor_dev_attr_fam2c_alarm.dev_attr.attr,
>
> Ultimately, this doesn't really make much sense, even with standard attribute
> names. The ABI assumes that _input attrributes exist. Not sure if that could
> be solved by providing 'dummy' unreadable input attributes (permission 0);
> that might be worth a try. If you want to attach names to the attributes,
> you would need to provide label attributes. Specifically you would need
>
> 	inX_input (with permission 0) - not sure if that is even possible
> 	inX_alarm
> 	inX_label
>
Hmm. OK. I may need to rethink this.

>> +	NULL
>> +};
>> +
>> +static const struct attribute_group altr_a10sr_attr_group = {
>> +	.attrs = altr_a10sr_attr
>> +};
>> +
>> +static int altr_a10sr_hwmon_probe(struct platform_device *pdev)
>> +{
>> +	struct altr_a10sr_hwmon *hwmon;
>> +	int ret;
>> +	struct altr_a10sr *a10sr = dev_get_drvdata(pdev->dev.parent);
>> +
>
> What if someone creates a stand-alone devicetree property for this driver,
> and there is no parent (or parent driver data) ?
>
I agree if this was a commercially available part. However, this is a 
specific driver for a programmable logic device (PLD) that will always 
be part of an MFD parent. The PLD only supports the Altera Development Kit.

>> +	hwmon = devm_kzalloc(&pdev->dev, sizeof(*hwmon), GFP_KERNEL);
>> +	if (!hwmon)
>> +		return -ENOMEM;
>> +
>> +	hwmon->regmap = a10sr->regmap;
>> +
>> +	platform_set_drvdata(pdev, hwmon);
>> +
>> +	ret = sysfs_create_group(&pdev->dev.kobj, &altr_a10sr_attr_group);
>> +	if (ret)
>> +		goto err_mem;
>> +
>> +	hwmon->class_device = hwmon_device_register(&pdev->dev);
>> +	if (IS_ERR(hwmon->class_device)) {
>> +		ret = PTR_ERR(hwmon->class_device);
>> +		goto err_sysfs;
>> +	}
>
> Please use devm_hwmon_device_register_with_groups().
>
Understood. Thanks.

Thanks for reviewing.

>> +
>> +	return 0;
>> +
>> +err_sysfs:
>> +	sysfs_remove_group(&pdev->dev.kobj, &altr_a10sr_attr_group);
>> +err_mem:
>> +	return ret;
>> +}
>> +
>> +static int altr_a10sr_hwmon_remove(struct platform_device *pdev)
>> +{
>> +	struct altr_a10sr_hwmon *hwmon = platform_get_drvdata(pdev);
>> +
>> +	hwmon_device_unregister(hwmon->class_device);
>> +	sysfs_remove_group(&pdev->dev.kobj, &altr_a10sr_attr_group);
>> +
>> +	return 0;
>> +}
>> +
>> +static const struct of_device_id altr_a10sr_hwmon_of_match[] = {
>> +	{ .compatible = "altr,a10sr-hwmon" },
>> +	{ },
>> +};
>> +MODULE_DEVICE_TABLE(of, altr_a10sr_hwmon_of_match);
>> +
>> +static struct platform_driver altr_a10sr_hwmon_driver = {
>> +	.probe = altr_a10sr_hwmon_probe,
>> +	.remove = altr_a10sr_hwmon_remove,
>> +	.driver = {
>> +		.name = "altr_a10sr_hwmon",
>> +		.of_match_table = of_match_ptr(altr_a10sr_hwmon_of_match),
>> +	},
>> +};
>> +
>> +module_platform_driver(altr_a10sr_hwmon_driver);
>> +
>> +MODULE_LICENSE("GPL v2");
>> +MODULE_AUTHOR("Thor Thayer <tthayer@opensource.altera.com>");
>> +MODULE_DESCRIPTION("HW Monitor driver for Altera Arria10 System Resource Chip");
>> --
>> 1.7.9.5
>>

Re: [PATCH 10/11] hwmon: Add Altera A10-SR power supply alarms

[Thor Thayer]

On 04/22/2016 05:24 PM, Guenter Roeck wrote:
> On Fri, Apr 22, 2016 at 10:33:38AM -0500, tthayer@opensource.altera.com wrote:
>> From: Thor Thayer <tthayer@opensource.altera.com>
>>
>> This patch adds the power supply alarms of the hwmon framework
>> to the Arria10 System Resource chip.
>>
>> Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
>> ---
>
> Please read and follow Documentation/hwmon/sysfs-interface
> as well as Documentation/hwmon/submitting-patches. At the very least,
> you are expected to document your driver, and you are expected to
> use standard attribute names.
>

OK. I misunderstood. The standard attribute names would be 
power[1-*]_alarm and the binding documentation the a10sr-hwmon portion 
for MFD doesn't cover this.

>>   drivers/hwmon/Kconfig              |    9 ++
>>   drivers/hwmon/Makefile             |    1 +
>>   drivers/hwmon/altera-a10sr-hwmon.c |  215 ++++++++++++++++++++++++++++++++++++
>>   3 files changed, 225 insertions(+)
>>   create mode 100644 drivers/hwmon/altera-a10sr-hwmon.c
>>
>> diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
>> index ff94007..af08846 100644
>> --- a/drivers/hwmon/Kconfig
>> +++ b/drivers/hwmon/Kconfig
>> @@ -248,6 +248,15 @@ config SENSORS_ADT7475
>>   	  This driver can also be build as a module.  If so, the module
>>   	  will be called adt7475.
>>
>> +config SENSORS_ALTERA_A10SR
>> +	bool "Altera Arria10 System Status"
>> +	depends on MFD_ALTERA_A10SR
>> +	help
>> +	  If you say yes here you get support for the power ready status
>> +	  for the Arria10's external power supplies on the Arria10 DevKit.
>> +	  These values are read over the SPI bus from the Arria10 System
>> +	  Resource chip.
>> +
>>   config SENSORS_ASC7621
>>   	tristate "Andigilog aSC7621"
>>   	depends on I2C
>> diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
>> index 2ef5b7c..17d72a7 100644
>> --- a/drivers/hwmon/Makefile
>> +++ b/drivers/hwmon/Makefile
>> @@ -43,6 +43,7 @@ obj-$(CONFIG_SENSORS_ADT7411)	+= adt7411.o
>>   obj-$(CONFIG_SENSORS_ADT7462)	+= adt7462.o
>>   obj-$(CONFIG_SENSORS_ADT7470)	+= adt7470.o
>>   obj-$(CONFIG_SENSORS_ADT7475)	+= adt7475.o
>> +obj-$(CONFIG_SENSORS_ALTERA_A10SR) += altera-a10sr-hwmon.o
>>   obj-$(CONFIG_SENSORS_APPLESMC)	+= applesmc.o
>>   obj-$(CONFIG_SENSORS_ARM_SCPI)	+= scpi-hwmon.o
>>   obj-$(CONFIG_SENSORS_ASC7621)	+= asc7621.o
>> diff --git a/drivers/hwmon/altera-a10sr-hwmon.c b/drivers/hwmon/altera-a10sr-hwmon.c
>> new file mode 100644
>> index 0000000..1eecc6b
>> --- /dev/null
>> +++ b/drivers/hwmon/altera-a10sr-hwmon.c
>> @@ -0,0 +1,215 @@
>> +/*
>> + *  Copyright Altera Corporation (C) 2014-2016. All Rights Reserved
>> + *
>> + * This program is free software; you can redistribute it and/or modify it
>> + * under the terms and conditions of the GNU General Public License,
>> + * version 2, as published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope it will be useful, but WITHOUT
>> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
>> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
>> + * more details.
>> + *
>> + * You should have received a copy of the GNU General Public License along with
>> + * this program.  If not, see <http://www.gnu.org/licenses/>.
>> + *
>> + * HW Monitor driver for  Altera Arria10 MAX5 System Resource Chip
>> + * Adapted from DA9052
>> + */
>> +
>> +#include <linux/hwmon.h>
>> +#include <linux/hwmon-sysfs.h>
>> +#include <linux/mfd/altera-a10sr.h>
>> +#include <linux/module.h>
>> +#include <linux/of.h>
>
> Please list include files in alphabetic order.
>

OK. I thought this was in alphabetical order. I'll update this after 
figuring out where I was wrong.

>> +
>> +#define ALTR_A10SR_1V0_BIT_POS          ALTR_A10SR_PG1_1V0_SHIFT
>> +#define ALTR_A10SR_0V95_BIT_POS         ALTR_A10SR_PG1_0V95_SHIFT
>> +#define ALTR_A10SR_0V9_BIT_POS          ALTR_A10SR_PG1_0V9_SHIFT
>> +#define ALTR_A10SR_10V_BIT_POS          ALTR_A10SR_PG1_10V_SHIFT
>> +#define ALTR_A10SR_5V0_BIT_POS          ALTR_A10SR_PG1_5V0_SHIFT
>> +#define ALTR_A10SR_3V3_BIT_POS          ALTR_A10SR_PG1_3V3_SHIFT
>> +#define ALTR_A10SR_2V5_BIT_POS          ALTR_A10SR_PG1_2V5_SHIFT
>> +#define ALTR_A10SR_1V8_BIT_POS          ALTR_A10SR_PG1_1V8_SHIFT
>> +#define ALTR_A10SR_OP_FLAG_BIT_POS      ALTR_A10SR_PG1_OP_FLAG_SHIFT
>> +/* 2nd register needs an offset of 8 to get to 2nd register */
>> +#define ALTR_A10SR_FBC2MP_BIT_POS       (8 + ALTR_A10SR_PG2_FBC2MP_SHIFT)
>> +#define ALTR_A10SR_FAC2MP_BIT_POS       (8 + ALTR_A10SR_PG2_FAC2MP_SHIFT)
>> +#define ALTR_A10SR_FMCBVADJ_BIT_POS     (8 + ALTR_A10SR_PG2_FMCBVADJ_SHIFT)
>> +#define ALTR_A10SR_FMCAVADJ_BIT_POS     (8 + ALTR_A10SR_PG2_FMCAVADJ_SHIFT)
>> +#define ALTR_A10SR_HL_VDDQ_BIT_POS      (8 + ALTR_A10SR_PG2_HL_VDDQ_SHIFT)
>> +#define ALTR_A10SR_HL_VDD_BIT_POS       (8 + ALTR_A10SR_PG2_HL_VDD_SHIFT)
>> +#define ALTR_A10SR_HL_HPS_BIT_POS       (8 + ALTR_A10SR_PG2_HL_HPS_SHIFT)
>> +#define ALTR_A10SR_HPS_BIT_POS          (8 + ALTR_A10SR_PG2_HPS_SHIFT)
>> +/* 3rd register needs an offset of 16 to get to 3rd register */
>> +#define ALTR_A10SR_10V_FAIL_BIT_POS     (16 + ALTR_A10SR_PG3_10V_FAIL_SHIFT)
>> +#define ALTR_A10SR_FAM2C_BIT_POS        (16 + ALTR_A10SR_PG3_FAM2C_SHIFT)
>> +
>> +/**
>> + * struct altr_a10sr_hwmon - Altera Max5 HWMON device private data structure
>> + * @device: hwmon class.
>> + * @regmap: the regmap from the parent device.
>> + */
>> +struct altr_a10sr_hwmon {
>> +	struct device		*class_device;
>> +	struct regmap		*regmap;
>> +};
>> +
>> +static ssize_t altr_a10sr_read_status(struct device *dev,
>> +				      struct device_attribute *devattr,
>> +				      char *buf)
>> +{
>> +	struct altr_a10sr_hwmon *hwmon = dev_get_drvdata(dev);
>> +	int val, ret, index = to_sensor_dev_attr(devattr)->index;
>> +	int mask = ALTR_A10SR_REG_BIT_MASK(index);
>> +	unsigned char reg = ALTR_A10SR_PWR_GOOD1_REG +
>> +			    ALTR_A10SR_REG_OFFSET(index);
>> +
>> +	ret = regmap_read(hwmon->regmap, reg, &val);
>
> The pointer parameter to regmap_read() is unsigned int. I would suggest
> to use the same variable type to avoid surprises.
>
Understood. Thanks.

>> +	if (ret < 0)
>> +		return ret;
>> +
>> +	return sprintf(buf, "%d\n", !!(~val & mask));
>
> Are alarms all active low ?
>
Yes, They are actually Power Good signals (Good = high) so I'm inverting.

>> +}
>> +
>> +static ssize_t altr_a10sr_hwmon_show_name(struct device *dev,
>> +					  struct device_attribute *devattr,
>> +					  char *buf)
>> +{
>> +	return sprintf(buf, "altr_a10sr\n");
>> +}
>> +
>> +/* First Power Good Register Bits */
>> +static SENSOR_DEVICE_ATTR(1v0_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
>> +			  ALTR_A10SR_1V0_BIT_POS);
>> +static SENSOR_DEVICE_ATTR(0v95_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
>> +			  ALTR_A10SR_0V95_BIT_POS);
>> +static SENSOR_DEVICE_ATTR(0v9_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
>> +			  ALTR_A10SR_0V9_BIT_POS);
>> +static SENSOR_DEVICE_ATTR(5v0_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
>> +			  ALTR_A10SR_5V0_BIT_POS);
>> +static SENSOR_DEVICE_ATTR(3v3_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
>> +			  ALTR_A10SR_3V3_BIT_POS);
>> +static SENSOR_DEVICE_ATTR(2v5_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
>> +			  ALTR_A10SR_2V5_BIT_POS);
>> +static SENSOR_DEVICE_ATTR(1v8_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
>> +			  ALTR_A10SR_1V8_BIT_POS);
>> +static SENSOR_DEVICE_ATTR(opflag_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
>> +			  ALTR_A10SR_OP_FLAG_BIT_POS);
>> +/* Second Power Good Register Bits */
>> +static SENSOR_DEVICE_ATTR(fbc2mp_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
>> +			  ALTR_A10SR_FBC2MP_BIT_POS);
>> +static SENSOR_DEVICE_ATTR(fac2mp_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
>> +			  ALTR_A10SR_FAC2MP_BIT_POS);
>> +static SENSOR_DEVICE_ATTR(fmcbvadj_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
>> +			  ALTR_A10SR_FMCBVADJ_BIT_POS);
>> +static SENSOR_DEVICE_ATTR(fmcavadj_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
>> +			  ALTR_A10SR_FMCAVADJ_BIT_POS);
>> +static SENSOR_DEVICE_ATTR(hl_vddq_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
>> +			  ALTR_A10SR_HL_VDDQ_BIT_POS);
>> +static SENSOR_DEVICE_ATTR(hl_vdd_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
>> +			  ALTR_A10SR_HL_VDD_BIT_POS);
>> +static SENSOR_DEVICE_ATTR(hlhps_vdd_alarm, S_IRUGO, altr_a10sr_read_status,
>> +			  NULL, ALTR_A10SR_HL_HPS_BIT_POS);
>> +static SENSOR_DEVICE_ATTR(hps_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
>> +			  ALTR_A10SR_HPS_BIT_POS);
>> +/* Third Power Good Register Bits */
>> +static SENSOR_DEVICE_ATTR(10v_alarm, S_IRUGO, altr_a10sr_read_status,
>> +			  NULL, ALTR_A10SR_10V_FAIL_BIT_POS);
>> +static SENSOR_DEVICE_ATTR(fam2c_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
>> +			  ALTR_A10SR_FAM2C_BIT_POS);
>> +
>> +static DEVICE_ATTR(name, S_IRUGO, altr_a10sr_hwmon_show_name, NULL);
>> +
>> +static struct attribute *altr_a10sr_attr[] = {
>> +	&dev_attr_name.attr,
>> +	/* First Power Good Register */
>> +	&sensor_dev_attr_opflag_alarm.dev_attr.attr,
>> +	&sensor_dev_attr_1v8_alarm.dev_attr.attr,
>> +	&sensor_dev_attr_2v5_alarm.dev_attr.attr,
>> +	&sensor_dev_attr_1v0_alarm.dev_attr.attr,
>> +	&sensor_dev_attr_3v3_alarm.dev_attr.attr,
>> +	&sensor_dev_attr_5v0_alarm.dev_attr.attr,
>> +	&sensor_dev_attr_0v9_alarm.dev_attr.attr,
>> +	&sensor_dev_attr_0v95_alarm.dev_attr.attr,
>> +	/* Second Power Good Register */
>> +	&sensor_dev_attr_hps_alarm.dev_attr.attr,
>> +	&sensor_dev_attr_hlhps_vdd_alarm.dev_attr.attr,
>> +	&sensor_dev_attr_hl_vdd_alarm.dev_attr.attr,
>> +	&sensor_dev_attr_hl_vddq_alarm.dev_attr.attr,
>> +	&sensor_dev_attr_fmcavadj_alarm.dev_attr.attr,
>> +	&sensor_dev_attr_fmcbvadj_alarm.dev_attr.attr,
>> +	&sensor_dev_attr_fac2mp_alarm.dev_attr.attr,
>> +	&sensor_dev_attr_fbc2mp_alarm.dev_attr.attr,
>> +	/* Third Power Good Register */
>> +	&sensor_dev_attr_10v_alarm.dev_attr.attr,
>> +	&sensor_dev_attr_fam2c_alarm.dev_attr.attr,
>
> Ultimately, this doesn't really make much sense, even with standard attribute
> names. The ABI assumes that _input attrributes exist. Not sure if that could
> be solved by providing 'dummy' unreadable input attributes (permission 0);
> that might be worth a try. If you want to attach names to the attributes,
> you would need to provide label attributes. Specifically you would need
>
> 	inX_input (with permission 0) - not sure if that is even possible
> 	inX_alarm
> 	inX_label
>
Hmm. OK. I may need to rethink this.

>> +	NULL
>> +};
>> +
>> +static const struct attribute_group altr_a10sr_attr_group = {
>> +	.attrs = altr_a10sr_attr
>> +};
>> +
>> +static int altr_a10sr_hwmon_probe(struct platform_device *pdev)
>> +{
>> +	struct altr_a10sr_hwmon *hwmon;
>> +	int ret;
>> +	struct altr_a10sr *a10sr = dev_get_drvdata(pdev->dev.parent);
>> +
>
> What if someone creates a stand-alone devicetree property for this driver,
> and there is no parent (or parent driver data) ?
>
I agree if this was a commercially available part. However, this is a 
specific driver for a programmable logic device (PLD) that will always 
be part of an MFD parent. The PLD only supports the Altera Development Kit.

>> +	hwmon = devm_kzalloc(&pdev->dev, sizeof(*hwmon), GFP_KERNEL);
>> +	if (!hwmon)
>> +		return -ENOMEM;
>> +
>> +	hwmon->regmap = a10sr->regmap;
>> +
>> +	platform_set_drvdata(pdev, hwmon);
>> +
>> +	ret = sysfs_create_group(&pdev->dev.kobj, &altr_a10sr_attr_group);
>> +	if (ret)
>> +		goto err_mem;
>> +
>> +	hwmon->class_device = hwmon_device_register(&pdev->dev);
>> +	if (IS_ERR(hwmon->class_device)) {
>> +		ret = PTR_ERR(hwmon->class_device);
>> +		goto err_sysfs;
>> +	}
>
> Please use devm_hwmon_device_register_with_groups().
>
Understood. Thanks.

Thanks for reviewing.

>> +
>> +	return 0;
>> +
>> +err_sysfs:
>> +	sysfs_remove_group(&pdev->dev.kobj, &altr_a10sr_attr_group);
>> +err_mem:
>> +	return ret;
>> +}
>> +
>> +static int altr_a10sr_hwmon_remove(struct platform_device *pdev)
>> +{
>> +	struct altr_a10sr_hwmon *hwmon = platform_get_drvdata(pdev);
>> +
>> +	hwmon_device_unregister(hwmon->class_device);
>> +	sysfs_remove_group(&pdev->dev.kobj, &altr_a10sr_attr_group);
>> +
>> +	return 0;
>> +}
>> +
>> +static const struct of_device_id altr_a10sr_hwmon_of_match[] = {
>> +	{ .compatible = "altr,a10sr-hwmon" },
>> +	{ },
>> +};
>> +MODULE_DEVICE_TABLE(of, altr_a10sr_hwmon_of_match);
>> +
>> +static struct platform_driver altr_a10sr_hwmon_driver = {
>> +	.probe = altr_a10sr_hwmon_probe,
>> +	.remove = altr_a10sr_hwmon_remove,
>> +	.driver = {
>> +		.name = "altr_a10sr_hwmon",
>> +		.of_match_table = of_match_ptr(altr_a10sr_hwmon_of_match),
>> +	},
>> +};
>> +
>> +module_platform_driver(altr_a10sr_hwmon_driver);
>> +
>> +MODULE_LICENSE("GPL v2");
>> +MODULE_AUTHOR("Thor Thayer <tthayer@opensource.altera.com>");
>> +MODULE_DESCRIPTION("HW Monitor driver for Altera Arria10 System Resource Chip");
>> --
>> 1.7.9.5
>>

Re: [PATCH 10/11] hwmon: Add Altera A10-SR power supply alarms

[Guenter Roeck]

On 04/25/2016 07:41 AM, Thor Thayer wrote:
>
>
> On 04/22/2016 05:24 PM, Guenter Roeck wrote:
>> On Fri, Apr 22, 2016 at 10:33:38AM -0500, tthayer@opensource.altera.com wrote:
>>> From: Thor Thayer <tthayer@opensource.altera.com>
>>>
>>> This patch adds the power supply alarms of the hwmon framework
>>> to the Arria10 System Resource chip.
>>>
>>> Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
>>> ---
>>
>> Please read and follow Documentation/hwmon/sysfs-interface
>> as well as Documentation/hwmon/submitting-patches. At the very least,
>> you are expected to document your driver, and you are expected to
>> use standard attribute names.
>>
>
> OK. I misunderstood. The standard attribute names would be power[1-*]_alarm and the binding documentation the a10sr-hwmon portion for MFD doesn't cover this.
>

power ? Why power ? The names suggest those are voltages.
Also not sure why those names would be in the bindings.

>>>   drivers/hwmon/Kconfig              |    9 ++
>>>   drivers/hwmon/Makefile             |    1 +
>>>   drivers/hwmon/altera-a10sr-hwmon.c |  215 ++++++++++++++++++++++++++++++++++++
>>>   3 files changed, 225 insertions(+)
>>>   create mode 100644 drivers/hwmon/altera-a10sr-hwmon.c
>>>
>>> diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
>>> index ff94007..af08846 100644
>>> --- a/drivers/hwmon/Kconfig
>>> +++ b/drivers/hwmon/Kconfig
>>> @@ -248,6 +248,15 @@ config SENSORS_ADT7475
>>>         This driver can also be build as a module.  If so, the module
>>>         will be called adt7475.
>>>
>>> +config SENSORS_ALTERA_A10SR
>>> +    bool "Altera Arria10 System Status"
>>> +    depends on MFD_ALTERA_A10SR
>>> +    help
>>> +      If you say yes here you get support for the power ready status
>>> +      for the Arria10's external power supplies on the Arria10 DevKit.
>>> +      These values are read over the SPI bus from the Arria10 System
>>> +      Resource chip.
>>> +
>>>   config SENSORS_ASC7621
>>>       tristate "Andigilog aSC7621"
>>>       depends on I2C
>>> diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
>>> index 2ef5b7c..17d72a7 100644
>>> --- a/drivers/hwmon/Makefile
>>> +++ b/drivers/hwmon/Makefile
>>> @@ -43,6 +43,7 @@ obj-$(CONFIG_SENSORS_ADT7411)    += adt7411.o
>>>   obj-$(CONFIG_SENSORS_ADT7462)    += adt7462.o
>>>   obj-$(CONFIG_SENSORS_ADT7470)    += adt7470.o
>>>   obj-$(CONFIG_SENSORS_ADT7475)    += adt7475.o
>>> +obj-$(CONFIG_SENSORS_ALTERA_A10SR) += altera-a10sr-hwmon.o
>>>   obj-$(CONFIG_SENSORS_APPLESMC)    += applesmc.o
>>>   obj-$(CONFIG_SENSORS_ARM_SCPI)    += scpi-hwmon.o
>>>   obj-$(CONFIG_SENSORS_ASC7621)    += asc7621.o
>>> diff --git a/drivers/hwmon/altera-a10sr-hwmon.c b/drivers/hwmon/altera-a10sr-hwmon.c
>>> new file mode 100644
>>> index 0000000..1eecc6b
>>> --- /dev/null
>>> +++ b/drivers/hwmon/altera-a10sr-hwmon.c
>>> @@ -0,0 +1,215 @@
>>> +/*
>>> + *  Copyright Altera Corporation (C) 2014-2016. All Rights Reserved
>>> + *
>>> + * This program is free software; you can redistribute it and/or modify it
>>> + * under the terms and conditions of the GNU General Public License,
>>> + * version 2, as published by the Free Software Foundation.
>>> + *
>>> + * This program is distributed in the hope it will be useful, but WITHOUT
>>> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
>>> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
>>> + * more details.
>>> + *
>>> + * You should have received a copy of the GNU General Public License along with
>>> + * this program.  If not, see <http://www.gnu.org/licenses/>.
>>> + *
>>> + * HW Monitor driver for  Altera Arria10 MAX5 System Resource Chip
>>> + * Adapted from DA9052
>>> + */
>>> +
>>> +#include <linux/hwmon.h>
>>> +#include <linux/hwmon-sysfs.h>
>>> +#include <linux/mfd/altera-a10sr.h>
>>> +#include <linux/module.h>
>>> +#include <linux/of.h>
>>
>> Please list include files in alphabetic order.
>>
>
> OK. I thought this was in alphabetical order. I'll update this after figuring out where I was wrong.
>

Sorry, PBKAC on my side.

Guenter

>>> +
>>> +#define ALTR_A10SR_1V0_BIT_POS          ALTR_A10SR_PG1_1V0_SHIFT
>>> +#define ALTR_A10SR_0V95_BIT_POS         ALTR_A10SR_PG1_0V95_SHIFT
>>> +#define ALTR_A10SR_0V9_BIT_POS          ALTR_A10SR_PG1_0V9_SHIFT
>>> +#define ALTR_A10SR_10V_BIT_POS          ALTR_A10SR_PG1_10V_SHIFT
>>> +#define ALTR_A10SR_5V0_BIT_POS          ALTR_A10SR_PG1_5V0_SHIFT
>>> +#define ALTR_A10SR_3V3_BIT_POS          ALTR_A10SR_PG1_3V3_SHIFT
>>> +#define ALTR_A10SR_2V5_BIT_POS          ALTR_A10SR_PG1_2V5_SHIFT
>>> +#define ALTR_A10SR_1V8_BIT_POS          ALTR_A10SR_PG1_1V8_SHIFT
>>> +#define ALTR_A10SR_OP_FLAG_BIT_POS      ALTR_A10SR_PG1_OP_FLAG_SHIFT
>>> +/* 2nd register needs an offset of 8 to get to 2nd register */
>>> +#define ALTR_A10SR_FBC2MP_BIT_POS       (8 + ALTR_A10SR_PG2_FBC2MP_SHIFT)
>>> +#define ALTR_A10SR_FAC2MP_BIT_POS       (8 + ALTR_A10SR_PG2_FAC2MP_SHIFT)
>>> +#define ALTR_A10SR_FMCBVADJ_BIT_POS     (8 + ALTR_A10SR_PG2_FMCBVADJ_SHIFT)
>>> +#define ALTR_A10SR_FMCAVADJ_BIT_POS     (8 + ALTR_A10SR_PG2_FMCAVADJ_SHIFT)
>>> +#define ALTR_A10SR_HL_VDDQ_BIT_POS      (8 + ALTR_A10SR_PG2_HL_VDDQ_SHIFT)
>>> +#define ALTR_A10SR_HL_VDD_BIT_POS       (8 + ALTR_A10SR_PG2_HL_VDD_SHIFT)
>>> +#define ALTR_A10SR_HL_HPS_BIT_POS       (8 + ALTR_A10SR_PG2_HL_HPS_SHIFT)
>>> +#define ALTR_A10SR_HPS_BIT_POS          (8 + ALTR_A10SR_PG2_HPS_SHIFT)
>>> +/* 3rd register needs an offset of 16 to get to 3rd register */
>>> +#define ALTR_A10SR_10V_FAIL_BIT_POS     (16 + ALTR_A10SR_PG3_10V_FAIL_SHIFT)
>>> +#define ALTR_A10SR_FAM2C_BIT_POS        (16 + ALTR_A10SR_PG3_FAM2C_SHIFT)
>>> +
>>> +/**
>>> + * struct altr_a10sr_hwmon - Altera Max5 HWMON device private data structure
>>> + * @device: hwmon class.
>>> + * @regmap: the regmap from the parent device.
>>> + */
>>> +struct altr_a10sr_hwmon {
>>> +    struct device        *class_device;
>>> +    struct regmap        *regmap;
>>> +};
>>> +
>>> +static ssize_t altr_a10sr_read_status(struct device *dev,
>>> +                      struct device_attribute *devattr,
>>> +                      char *buf)
>>> +{
>>> +    struct altr_a10sr_hwmon *hwmon = dev_get_drvdata(dev);
>>> +    int val, ret, index = to_sensor_dev_attr(devattr)->index;
>>> +    int mask = ALTR_A10SR_REG_BIT_MASK(index);
>>> +    unsigned char reg = ALTR_A10SR_PWR_GOOD1_REG +
>>> +                ALTR_A10SR_REG_OFFSET(index);
>>> +
>>> +    ret = regmap_read(hwmon->regmap, reg, &val);
>>
>> The pointer parameter to regmap_read() is unsigned int. I would suggest
>> to use the same variable type to avoid surprises.
>>
> Understood. Thanks.
>
>>> +    if (ret < 0)
>>> +        return ret;
>>> +
>>> +    return sprintf(buf, "%d\n", !!(~val & mask));
>>
>> Are alarms all active low ?
>>
> Yes, They are actually Power Good signals (Good = high) so I'm inverting.
>
>>> +}
>>> +
>>> +static ssize_t altr_a10sr_hwmon_show_name(struct device *dev,
>>> +                      struct device_attribute *devattr,
>>> +                      char *buf)
>>> +{
>>> +    return sprintf(buf, "altr_a10sr\n");
>>> +}
>>> +
>>> +/* First Power Good Register Bits */
>>> +static SENSOR_DEVICE_ATTR(1v0_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
>>> +              ALTR_A10SR_1V0_BIT_POS);
>>> +static SENSOR_DEVICE_ATTR(0v95_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
>>> +              ALTR_A10SR_0V95_BIT_POS);
>>> +static SENSOR_DEVICE_ATTR(0v9_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
>>> +              ALTR_A10SR_0V9_BIT_POS);
>>> +static SENSOR_DEVICE_ATTR(5v0_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
>>> +              ALTR_A10SR_5V0_BIT_POS);
>>> +static SENSOR_DEVICE_ATTR(3v3_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
>>> +              ALTR_A10SR_3V3_BIT_POS);
>>> +static SENSOR_DEVICE_ATTR(2v5_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
>>> +              ALTR_A10SR_2V5_BIT_POS);
>>> +static SENSOR_DEVICE_ATTR(1v8_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
>>> +              ALTR_A10SR_1V8_BIT_POS);
>>> +static SENSOR_DEVICE_ATTR(opflag_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
>>> +              ALTR_A10SR_OP_FLAG_BIT_POS);
>>> +/* Second Power Good Register Bits */
>>> +static SENSOR_DEVICE_ATTR(fbc2mp_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
>>> +              ALTR_A10SR_FBC2MP_BIT_POS);
>>> +static SENSOR_DEVICE_ATTR(fac2mp_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
>>> +              ALTR_A10SR_FAC2MP_BIT_POS);
>>> +static SENSOR_DEVICE_ATTR(fmcbvadj_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
>>> +              ALTR_A10SR_FMCBVADJ_BIT_POS);
>>> +static SENSOR_DEVICE_ATTR(fmcavadj_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
>>> +              ALTR_A10SR_FMCAVADJ_BIT_POS);
>>> +static SENSOR_DEVICE_ATTR(hl_vddq_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
>>> +              ALTR_A10SR_HL_VDDQ_BIT_POS);
>>> +static SENSOR_DEVICE_ATTR(hl_vdd_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
>>> +              ALTR_A10SR_HL_VDD_BIT_POS);
>>> +static SENSOR_DEVICE_ATTR(hlhps_vdd_alarm, S_IRUGO, altr_a10sr_read_status,
>>> +              NULL, ALTR_A10SR_HL_HPS_BIT_POS);
>>> +static SENSOR_DEVICE_ATTR(hps_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
>>> +              ALTR_A10SR_HPS_BIT_POS);
>>> +/* Third Power Good Register Bits */
>>> +static SENSOR_DEVICE_ATTR(10v_alarm, S_IRUGO, altr_a10sr_read_status,
>>> +              NULL, ALTR_A10SR_10V_FAIL_BIT_POS);
>>> +static SENSOR_DEVICE_ATTR(fam2c_alarm, S_IRUGO, altr_a10sr_read_status, NULL,
>>> +              ALTR_A10SR_FAM2C_BIT_POS);
>>> +
>>> +static DEVICE_ATTR(name, S_IRUGO, altr_a10sr_hwmon_show_name, NULL);
>>> +
>>> +static struct attribute *altr_a10sr_attr[] = {
>>> +    &dev_attr_name.attr,
>>> +    /* First Power Good Register */
>>> +    &sensor_dev_attr_opflag_alarm.dev_attr.attr,
>>> +    &sensor_dev_attr_1v8_alarm.dev_attr.attr,
>>> +    &sensor_dev_attr_2v5_alarm.dev_attr.attr,
>>> +    &sensor_dev_attr_1v0_alarm.dev_attr.attr,
>>> +    &sensor_dev_attr_3v3_alarm.dev_attr.attr,
>>> +    &sensor_dev_attr_5v0_alarm.dev_attr.attr,
>>> +    &sensor_dev_attr_0v9_alarm.dev_attr.attr,
>>> +    &sensor_dev_attr_0v95_alarm.dev_attr.attr,
>>> +    /* Second Power Good Register */
>>> +    &sensor_dev_attr_hps_alarm.dev_attr.attr,
>>> +    &sensor_dev_attr_hlhps_vdd_alarm.dev_attr.attr,
>>> +    &sensor_dev_attr_hl_vdd_alarm.dev_attr.attr,
>>> +    &sensor_dev_attr_hl_vddq_alarm.dev_attr.attr,
>>> +    &sensor_dev_attr_fmcavadj_alarm.dev_attr.attr,
>>> +    &sensor_dev_attr_fmcbvadj_alarm.dev_attr.attr,
>>> +    &sensor_dev_attr_fac2mp_alarm.dev_attr.attr,
>>> +    &sensor_dev_attr_fbc2mp_alarm.dev_attr.attr,
>>> +    /* Third Power Good Register */
>>> +    &sensor_dev_attr_10v_alarm.dev_attr.attr,
>>> +    &sensor_dev_attr_fam2c_alarm.dev_attr.attr,
>>
>> Ultimately, this doesn't really make much sense, even with standard attribute
>> names. The ABI assumes that _input attrributes exist. Not sure if that could
>> be solved by providing 'dummy' unreadable input attributes (permission 0);
>> that might be worth a try. If you want to attach names to the attributes,
>> you would need to provide label attributes. Specifically you would need
>>
>>     inX_input (with permission 0) - not sure if that is even possible
>>     inX_alarm
>>     inX_label
>>
> Hmm. OK. I may need to rethink this.
>
>>> +    NULL
>>> +};
>>> +
>>> +static const struct attribute_group altr_a10sr_attr_group = {
>>> +    .attrs = altr_a10sr_attr
>>> +};
>>> +
>>> +static int altr_a10sr_hwmon_probe(struct platform_device *pdev)
>>> +{
>>> +    struct altr_a10sr_hwmon *hwmon;
>>> +    int ret;
>>> +    struct altr_a10sr *a10sr = dev_get_drvdata(pdev->dev.parent);
>>> +
>>
>> What if someone creates a stand-alone devicetree property for this driver,
>> and there is no parent (or parent driver data) ?
>>
> I agree if this was a commercially available part. However, this is a specific driver for a programmable logic device (PLD) that will always be part of an MFD parent. The PLD only supports the Altera Development Kit.
>
>>> +    hwmon = devm_kzalloc(&pdev->dev, sizeof(*hwmon), GFP_KERNEL);
>>> +    if (!hwmon)
>>> +        return -ENOMEM;
>>> +
>>> +    hwmon->regmap = a10sr->regmap;
>>> +
>>> +    platform_set_drvdata(pdev, hwmon);
>>> +
>>> +    ret = sysfs_create_group(&pdev->dev.kobj, &altr_a10sr_attr_group);
>>> +    if (ret)
>>> +        goto err_mem;
>>> +
>>> +    hwmon->class_device = hwmon_device_register(&pdev->dev);
>>> +    if (IS_ERR(hwmon->class_device)) {
>>> +        ret = PTR_ERR(hwmon->class_device);
>>> +        goto err_sysfs;
>>> +    }
>>
>> Please use devm_hwmon_device_register_with_groups().
>>
> Understood. Thanks.
>
> Thanks for reviewing.
>
>>> +
>>> +    return 0;
>>> +
>>> +err_sysfs:
>>> +    sysfs_remove_group(&pdev->dev.kobj, &altr_a10sr_attr_group);
>>> +err_mem:
>>> +    return ret;
>>> +}
>>> +
>>> +static int altr_a10sr_hwmon_remove(struct platform_device *pdev)
>>> +{
>>> +    struct altr_a10sr_hwmon *hwmon = platform_get_drvdata(pdev);
>>> +
>>> +    hwmon_device_unregister(hwmon->class_device);
>>> +    sysfs_remove_group(&pdev->dev.kobj, &altr_a10sr_attr_group);
>>> +
>>> +    return 0;
>>> +}
>>> +
>>> +static const struct of_device_id altr_a10sr_hwmon_of_match[] = {
>>> +    { .compatible = "altr,a10sr-hwmon" },
>>> +    { },
>>> +};
>>> +MODULE_DEVICE_TABLE(of, altr_a10sr_hwmon_of_match);
>>> +
>>> +static struct platform_driver altr_a10sr_hwmon_driver = {
>>> +    .probe = altr_a10sr_hwmon_probe,
>>> +    .remove = altr_a10sr_hwmon_remove,
>>> +    .driver = {
>>> +        .name = "altr_a10sr_hwmon",
>>> +        .of_match_table = of_match_ptr(altr_a10sr_hwmon_of_match),
>>> +    },
>>> +};
>>> +
>>> +module_platform_driver(altr_a10sr_hwmon_driver);
>>> +
>>> +MODULE_LICENSE("GPL v2");
>>> +MODULE_AUTHOR("Thor Thayer <tthayer@opensource.altera.com>");
>>> +MODULE_DESCRIPTION("HW Monitor driver for Altera Arria10 System Resource Chip");
>>> --
>>> 1.7.9.5
>>>
>

Re: [PATCH 10/11] hwmon: Add Altera A10-SR power supply alarms

[Thor Thayer]

On 04/25/2016 09:58 AM, Guenter Roeck wrote:
> On 04/25/2016 07:41 AM, Thor Thayer wrote:
>>
>>
>> On 04/22/2016 05:24 PM, Guenter Roeck wrote:
>>> On Fri, Apr 22, 2016 at 10:33:38AM -0500,
>>> tthayer@opensource.altera.com wrote:
>>>> From: Thor Thayer <tthayer@opensource.altera.com>
>>>>
>>>> This patch adds the power supply alarms of the hwmon framework
>>>> to the Arria10 System Resource chip.
>>>>
>>>> Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
>>>> ---
>>>
>>> Please read and follow Documentation/hwmon/sysfs-interface
>>> as well as Documentation/hwmon/submitting-patches. At the very least,
>>> you are expected to document your driver, and you are expected to
>>> use standard attribute names.
>>>
>>
>> OK. I misunderstood. The standard attribute names would be
>> power[1-*]_alarm and the binding documentation the a10sr-hwmon portion
>> for MFD doesn't cover this.
>>
>
> power ? Why power ? The names suggest those are voltages.
> Also not sure why those names would be in the bindings.
>
Yes, you are correct. I should be using in[0-*]_lcrit_alarm.

I didn't phrase my reply clearly. It was my initial understanding that 
the binding documentation for the MFD would cover the documentation for 
the driver. I missed that I needed to add the documentation into 
Documentation/hwmon/altera-a10sr-hwmon.c but I will fix this oversight.

Thanks.

>>>>   drivers/hwmon/Kconfig              |    9 ++
>>>>   drivers/hwmon/Makefile             |    1 +
>>>>   drivers/hwmon/altera-a10sr-hwmon.c |  215
>>>> ++++++++++++++++++++++++++++++++++++
>>>>   3 files changed, 225 insertions(+)
>>>>   create mode 100644 drivers/hwmon/altera-a10sr-hwmon.c
>>>>
>>>> diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
>>>> index ff94007..af08846 100644
>>>> --- a/drivers/hwmon/Kconfig
>>>> +++ b/drivers/hwmon/Kconfig
>>>> @@ -248,6 +248,15 @@ config SENSORS_ADT7475
>>>>         This driver can also be build as a module.  If so, the module
>>>>         will be called adt7475.
>>>>
>>>> +config SENSORS_ALTERA_A10SR
>>>> +    bool "Altera Arria10 System Status"
>>>> +    depends on MFD_ALTERA_A10SR
>>>> +    help
>>>> +      If you say yes here you get support for the power ready status
>>>> +      for the Arria10's external power supplies on the Arria10 DevKit.
>>>> +      These values are read over the SPI bus from the Arria10 System
>>>> +      Resource chip.
>>>> +
>>>>   config SENSORS_ASC7621
>>>>       tristate "Andigilog aSC7621"
>>>>       depends on I2C
>>>> diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
>>>> index 2ef5b7c..17d72a7 100644
>>>> --- a/drivers/hwmon/Makefile
>>>> +++ b/drivers/hwmon/Makefile
>>>> @@ -43,6 +43,7 @@ obj-$(CONFIG_SENSORS_ADT7411)    += adt7411.o
>>>>   obj-$(CONFIG_SENSORS_ADT7462)    += adt7462.o
>>>>   obj-$(CONFIG_SENSORS_ADT7470)    += adt7470.o
>>>>   obj-$(CONFIG_SENSORS_ADT7475)    += adt7475.o
>>>> +obj-$(CONFIG_SENSORS_ALTERA_A10SR) += altera-a10sr-hwmon.o
>>>>   obj-$(CONFIG_SENSORS_APPLESMC)    += applesmc.o
>>>>   obj-$(CONFIG_SENSORS_ARM_SCPI)    += scpi-hwmon.o
>>>>   obj-$(CONFIG_SENSORS_ASC7621)    += asc7621.o
>>>> diff --git a/drivers/hwmon/altera-a10sr-hwmon.c
>>>> b/drivers/hwmon/altera-a10sr-hwmon.c
>>>> new file mode 100644
>>>> index 0000000..1eecc6b
>>>> --- /dev/null
>>>> +++ b/drivers/hwmon/altera-a10sr-hwmon.c
>>>> @@ -0,0 +1,215 @@
>>>> +/*
>>>> + *  Copyright Altera Corporation (C) 2014-2016. All Rights Reserved
>>>> + *
>>>> + * This program is free software; you can redistribute it and/or
>>>> modify it
>>>> + * under the terms and conditions of the GNU General Public License,
>>>> + * version 2, as published by the Free Software Foundation.
>>>> + *
>>>> + * This program is distributed in the hope it will be useful, but
>>>> WITHOUT
>>>> + * ANY WARRANTY; without even the implied warranty of
>>>> MERCHANTABILITY or
>>>> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
>>>> License for
>>>> + * more details.
>>>> + *
>>>> + * You should have received a copy of the GNU General Public
>>>> License along with
>>>> + * this program.  If not, see <http://www.gnu.org/licenses/>.
>>>> + *
>>>> + * HW Monitor driver for  Altera Arria10 MAX5 System Resource Chip
>>>> + * Adapted from DA9052
>>>> + */
>>>> +
>>>> +#include <linux/hwmon.h>
>>>> +#include <linux/hwmon-sysfs.h>
>>>> +#include <linux/mfd/altera-a10sr.h>
>>>> +#include <linux/module.h>
>>>> +#include <linux/of.h>
>>>
>>> Please list include files in alphabetic order.
>>>
>>
>> OK. I thought this was in alphabetical order. I'll update this after
>> figuring out where I was wrong.
>>
>
> Sorry, PBKAC on my side.
>
> Guenter
>
>>>> +
>>>> +#define ALTR_A10SR_1V0_BIT_POS          ALTR_A10SR_PG1_1V0_SHIFT
>>>> +#define ALTR_A10SR_0V95_BIT_POS         ALTR_A10SR_PG1_0V95_SHIFT
>>>> +#define ALTR_A10SR_0V9_BIT_POS          ALTR_A10SR_PG1_0V9_SHIFT
>>>> +#define ALTR_A10SR_10V_BIT_POS          ALTR_A10SR_PG1_10V_SHIFT
>>>> +#define ALTR_A10SR_5V0_BIT_POS          ALTR_A10SR_PG1_5V0_SHIFT
>>>> +#define ALTR_A10SR_3V3_BIT_POS          ALTR_A10SR_PG1_3V3_SHIFT
>>>> +#define ALTR_A10SR_2V5_BIT_POS          ALTR_A10SR_PG1_2V5_SHIFT
>>>> +#define ALTR_A10SR_1V8_BIT_POS          ALTR_A10SR_PG1_1V8_SHIFT
>>>> +#define ALTR_A10SR_OP_FLAG_BIT_POS      ALTR_A10SR_PG1_OP_FLAG_SHIFT
>>>> +/* 2nd register needs an offset of 8 to get to 2nd register */
>>>> +#define ALTR_A10SR_FBC2MP_BIT_POS       (8 +
>>>> ALTR_A10SR_PG2_FBC2MP_SHIFT)
>>>> +#define ALTR_A10SR_FAC2MP_BIT_POS       (8 +
>>>> ALTR_A10SR_PG2_FAC2MP_SHIFT)
>>>> +#define ALTR_A10SR_FMCBVADJ_BIT_POS     (8 +
>>>> ALTR_A10SR_PG2_FMCBVADJ_SHIFT)
>>>> +#define ALTR_A10SR_FMCAVADJ_BIT_POS     (8 +
>>>> ALTR_A10SR_PG2_FMCAVADJ_SHIFT)
>>>> +#define ALTR_A10SR_HL_VDDQ_BIT_POS      (8 +
>>>> ALTR_A10SR_PG2_HL_VDDQ_SHIFT)
>>>> +#define ALTR_A10SR_HL_VDD_BIT_POS       (8 +
>>>> ALTR_A10SR_PG2_HL_VDD_SHIFT)
>>>> +#define ALTR_A10SR_HL_HPS_BIT_POS       (8 +
>>>> ALTR_A10SR_PG2_HL_HPS_SHIFT)
>>>> +#define ALTR_A10SR_HPS_BIT_POS          (8 + ALTR_A10SR_PG2_HPS_SHIFT)
>>>> +/* 3rd register needs an offset of 16 to get to 3rd register */
>>>> +#define ALTR_A10SR_10V_FAIL_BIT_POS     (16 +
>>>> ALTR_A10SR_PG3_10V_FAIL_SHIFT)
>>>> +#define ALTR_A10SR_FAM2C_BIT_POS        (16 +
>>>> ALTR_A10SR_PG3_FAM2C_SHIFT)
>>>> +
>>>> +/**
>>>> + * struct altr_a10sr_hwmon - Altera Max5 HWMON device private data
>>>> structure
>>>> + * @device: hwmon class.
>>>> + * @regmap: the regmap from the parent device.
>>>> + */
>>>> +struct altr_a10sr_hwmon {
>>>> +    struct device        *class_device;
>>>> +    struct regmap        *regmap;
>>>> +};
>>>> +
>>>> +static ssize_t altr_a10sr_read_status(struct device *dev,
>>>> +                      struct device_attribute *devattr,
>>>> +                      char *buf)
>>>> +{
>>>> +    struct altr_a10sr_hwmon *hwmon = dev_get_drvdata(dev);
>>>> +    int val, ret, index = to_sensor_dev_attr(devattr)->index;
>>>> +    int mask = ALTR_A10SR_REG_BIT_MASK(index);
>>>> +    unsigned char reg = ALTR_A10SR_PWR_GOOD1_REG +
>>>> +                ALTR_A10SR_REG_OFFSET(index);
>>>> +
>>>> +    ret = regmap_read(hwmon->regmap, reg, &val);
>>>
>>> The pointer parameter to regmap_read() is unsigned int. I would suggest
>>> to use the same variable type to avoid surprises.
>>>
>> Understood. Thanks.
>>
>>>> +    if (ret < 0)
>>>> +        return ret;
>>>> +
>>>> +    return sprintf(buf, "%d\n", !!(~val & mask));
>>>
>>> Are alarms all active low ?
>>>
>> Yes, They are actually Power Good signals (Good = high) so I'm inverting.
>>
>>>> +}
>>>> +
>>>> +static ssize_t altr_a10sr_hwmon_show_name(struct device *dev,
>>>> +                      struct device_attribute *devattr,
>>>> +                      char *buf)
>>>> +{
>>>> +    return sprintf(buf, "altr_a10sr\n");
>>>> +}
>>>> +
>>>> +/* First Power Good Register Bits */
>>>> +static SENSOR_DEVICE_ATTR(1v0_alarm, S_IRUGO,
>>>> altr_a10sr_read_status, NULL,
>>>> +              ALTR_A10SR_1V0_BIT_POS);
>>>> +static SENSOR_DEVICE_ATTR(0v95_alarm, S_IRUGO,
>>>> altr_a10sr_read_status, NULL,
>>>> +              ALTR_A10SR_0V95_BIT_POS);
>>>> +static SENSOR_DEVICE_ATTR(0v9_alarm, S_IRUGO,
>>>> altr_a10sr_read_status, NULL,
>>>> +              ALTR_A10SR_0V9_BIT_POS);
>>>> +static SENSOR_DEVICE_ATTR(5v0_alarm, S_IRUGO,
>>>> altr_a10sr_read_status, NULL,
>>>> +              ALTR_A10SR_5V0_BIT_POS);
>>>> +static SENSOR_DEVICE_ATTR(3v3_alarm, S_IRUGO,
>>>> altr_a10sr_read_status, NULL,
>>>> +              ALTR_A10SR_3V3_BIT_POS);
>>>> +static SENSOR_DEVICE_ATTR(2v5_alarm, S_IRUGO,
>>>> altr_a10sr_read_status, NULL,
>>>> +              ALTR_A10SR_2V5_BIT_POS);
>>>> +static SENSOR_DEVICE_ATTR(1v8_alarm, S_IRUGO,
>>>> altr_a10sr_read_status, NULL,
>>>> +              ALTR_A10SR_1V8_BIT_POS);
>>>> +static SENSOR_DEVICE_ATTR(opflag_alarm, S_IRUGO,
>>>> altr_a10sr_read_status, NULL,
>>>> +              ALTR_A10SR_OP_FLAG_BIT_POS);
>>>> +/* Second Power Good Register Bits */
>>>> +static SENSOR_DEVICE_ATTR(fbc2mp_alarm, S_IRUGO,
>>>> altr_a10sr_read_status, NULL,
>>>> +              ALTR_A10SR_FBC2MP_BIT_POS);
>>>> +static SENSOR_DEVICE_ATTR(fac2mp_alarm, S_IRUGO,
>>>> altr_a10sr_read_status, NULL,
>>>> +              ALTR_A10SR_FAC2MP_BIT_POS);
>>>> +static SENSOR_DEVICE_ATTR(fmcbvadj_alarm, S_IRUGO,
>>>> altr_a10sr_read_status, NULL,
>>>> +              ALTR_A10SR_FMCBVADJ_BIT_POS);
>>>> +static SENSOR_DEVICE_ATTR(fmcavadj_alarm, S_IRUGO,
>>>> altr_a10sr_read_status, NULL,
>>>> +              ALTR_A10SR_FMCAVADJ_BIT_POS);
>>>> +static SENSOR_DEVICE_ATTR(hl_vddq_alarm, S_IRUGO,
>>>> altr_a10sr_read_status, NULL,
>>>> +              ALTR_A10SR_HL_VDDQ_BIT_POS);
>>>> +static SENSOR_DEVICE_ATTR(hl_vdd_alarm, S_IRUGO,
>>>> altr_a10sr_read_status, NULL,
>>>> +              ALTR_A10SR_HL_VDD_BIT_POS);
>>>> +static SENSOR_DEVICE_ATTR(hlhps_vdd_alarm, S_IRUGO,
>>>> altr_a10sr_read_status,
>>>> +              NULL, ALTR_A10SR_HL_HPS_BIT_POS);
>>>> +static SENSOR_DEVICE_ATTR(hps_alarm, S_IRUGO,
>>>> altr_a10sr_read_status, NULL,
>>>> +              ALTR_A10SR_HPS_BIT_POS);
>>>> +/* Third Power Good Register Bits */
>>>> +static SENSOR_DEVICE_ATTR(10v_alarm, S_IRUGO, altr_a10sr_read_status,
>>>> +              NULL, ALTR_A10SR_10V_FAIL_BIT_POS);
>>>> +static SENSOR_DEVICE_ATTR(fam2c_alarm, S_IRUGO,
>>>> altr_a10sr_read_status, NULL,
>>>> +              ALTR_A10SR_FAM2C_BIT_POS);
>>>> +
>>>> +static DEVICE_ATTR(name, S_IRUGO, altr_a10sr_hwmon_show_name, NULL);
>>>> +
>>>> +static struct attribute *altr_a10sr_attr[] = {
>>>> +    &dev_attr_name.attr,
>>>> +    /* First Power Good Register */
>>>> +    &sensor_dev_attr_opflag_alarm.dev_attr.attr,
>>>> +    &sensor_dev_attr_1v8_alarm.dev_attr.attr,
>>>> +    &sensor_dev_attr_2v5_alarm.dev_attr.attr,
>>>> +    &sensor_dev_attr_1v0_alarm.dev_attr.attr,
>>>> +    &sensor_dev_attr_3v3_alarm.dev_attr.attr,
>>>> +    &sensor_dev_attr_5v0_alarm.dev_attr.attr,
>>>> +    &sensor_dev_attr_0v9_alarm.dev_attr.attr,
>>>> +    &sensor_dev_attr_0v95_alarm.dev_attr.attr,
>>>> +    /* Second Power Good Register */
>>>> +    &sensor_dev_attr_hps_alarm.dev_attr.attr,
>>>> +    &sensor_dev_attr_hlhps_vdd_alarm.dev_attr.attr,
>>>> +    &sensor_dev_attr_hl_vdd_alarm.dev_attr.attr,
>>>> +    &sensor_dev_attr_hl_vddq_alarm.dev_attr.attr,
>>>> +    &sensor_dev_attr_fmcavadj_alarm.dev_attr.attr,
>>>> +    &sensor_dev_attr_fmcbvadj_alarm.dev_attr.attr,
>>>> +    &sensor_dev_attr_fac2mp_alarm.dev_attr.attr,
>>>> +    &sensor_dev_attr_fbc2mp_alarm.dev_attr.attr,
>>>> +    /* Third Power Good Register */
>>>> +    &sensor_dev_attr_10v_alarm.dev_attr.attr,
>>>> +    &sensor_dev_attr_fam2c_alarm.dev_attr.attr,
>>>
>>> Ultimately, this doesn't really make much sense, even with standard
>>> attribute
>>> names. The ABI assumes that _input attrributes exist. Not sure if
>>> that could
>>> be solved by providing 'dummy' unreadable input attributes
>>> (permission 0);
>>> that might be worth a try. If you want to attach names to the
>>> attributes,
>>> you would need to provide label attributes. Specifically you would need
>>>
>>>     inX_input (with permission 0) - not sure if that is even possible
>>>     inX_alarm
>>>     inX_label
>>>
>> Hmm. OK. I may need to rethink this.
>>
>>>> +    NULL
>>>> +};
>>>> +
>>>> +static const struct attribute_group altr_a10sr_attr_group = {
>>>> +    .attrs = altr_a10sr_attr
>>>> +};
>>>> +
>>>> +static int altr_a10sr_hwmon_probe(struct platform_device *pdev)
>>>> +{
>>>> +    struct altr_a10sr_hwmon *hwmon;
>>>> +    int ret;
>>>> +    struct altr_a10sr *a10sr = dev_get_drvdata(pdev->dev.parent);
>>>> +
>>>
>>> What if someone creates a stand-alone devicetree property for this
>>> driver,
>>> and there is no parent (or parent driver data) ?
>>>
>> I agree if this was a commercially available part. However, this is a
>> specific driver for a programmable logic device (PLD) that will always
>> be part of an MFD parent. The PLD only supports the Altera Development
>> Kit.
>>
>>>> +    hwmon = devm_kzalloc(&pdev->dev, sizeof(*hwmon), GFP_KERNEL);
>>>> +    if (!hwmon)
>>>> +        return -ENOMEM;
>>>> +
>>>> +    hwmon->regmap = a10sr->regmap;
>>>> +
>>>> +    platform_set_drvdata(pdev, hwmon);
>>>> +
>>>> +    ret = sysfs_create_group(&pdev->dev.kobj, &altr_a10sr_attr_group);
>>>> +    if (ret)
>>>> +        goto err_mem;
>>>> +
>>>> +    hwmon->class_device = hwmon_device_register(&pdev->dev);
>>>> +    if (IS_ERR(hwmon->class_device)) {
>>>> +        ret = PTR_ERR(hwmon->class_device);
>>>> +        goto err_sysfs;
>>>> +    }
>>>
>>> Please use devm_hwmon_device_register_with_groups().
>>>
>> Understood. Thanks.
>>
>> Thanks for reviewing.
>>
>>>> +
>>>> +    return 0;
>>>> +
>>>> +err_sysfs:
>>>> +    sysfs_remove_group(&pdev->dev.kobj, &altr_a10sr_attr_group);
>>>> +err_mem:
>>>> +    return ret;
>>>> +}
>>>> +
>>>> +static int altr_a10sr_hwmon_remove(struct platform_device *pdev)
>>>> +{
>>>> +    struct altr_a10sr_hwmon *hwmon = platform_get_drvdata(pdev);
>>>> +
>>>> +    hwmon_device_unregister(hwmon->class_device);
>>>> +    sysfs_remove_group(&pdev->dev.kobj, &altr_a10sr_attr_group);
>>>> +
>>>> +    return 0;
>>>> +}
>>>> +
>>>> +static const struct of_device_id altr_a10sr_hwmon_of_match[] = {
>>>> +    { .compatible = "altr,a10sr-hwmon" },
>>>> +    { },
>>>> +};
>>>> +MODULE_DEVICE_TABLE(of, altr_a10sr_hwmon_of_match);
>>>> +
>>>> +static struct platform_driver altr_a10sr_hwmon_driver = {
>>>> +    .probe = altr_a10sr_hwmon_probe,
>>>> +    .remove = altr_a10sr_hwmon_remove,
>>>> +    .driver = {
>>>> +        .name = "altr_a10sr_hwmon",
>>>> +        .of_match_table = of_match_ptr(altr_a10sr_hwmon_of_match),
>>>> +    },
>>>> +};
>>>> +
>>>> +module_platform_driver(altr_a10sr_hwmon_driver);
>>>> +
>>>> +MODULE_LICENSE("GPL v2");
>>>> +MODULE_AUTHOR("Thor Thayer <tthayer@opensource.altera.com>");
>>>> +MODULE_DESCRIPTION("HW Monitor driver for Altera Arria10 System
>>>> Resource Chip");
>>>> --
>>>> 1.7.9.5
>>>>
>>
>

Re: [PATCH 10/11] hwmon: Add Altera A10-SR power supply alarms

[Thor Thayer]

On 04/25/2016 09:58 AM, Guenter Roeck wrote:
> On 04/25/2016 07:41 AM, Thor Thayer wrote:
>>
>>
>> On 04/22/2016 05:24 PM, Guenter Roeck wrote:
>>> On Fri, Apr 22, 2016 at 10:33:38AM -0500,
>>> tthayer@opensource.altera.com wrote:
>>>> From: Thor Thayer <tthayer@opensource.altera.com>
>>>>
>>>> This patch adds the power supply alarms of the hwmon framework
>>>> to the Arria10 System Resource chip.
>>>>
>>>> Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
>>>> ---
>>>
>>> Please read and follow Documentation/hwmon/sysfs-interface
>>> as well as Documentation/hwmon/submitting-patches. At the very least,
>>> you are expected to document your driver, and you are expected to
>>> use standard attribute names.
>>>
>>
>> OK. I misunderstood. The standard attribute names would be
>> power[1-*]_alarm and the binding documentation the a10sr-hwmon portion
>> for MFD doesn't cover this.
>>
>
> power ? Why power ? The names suggest those are voltages.
> Also not sure why those names would be in the bindings.
>
Yes, you are correct. I should be using in[0-*]_lcrit_alarm.

I didn't phrase my reply clearly. It was my initial understanding that 
the binding documentation for the MFD would cover the documentation for 
the driver. I missed that I needed to add the documentation into 
Documentation/hwmon/altera-a10sr-hwmon.c but I will fix this oversight.

Thanks.

>>>>   drivers/hwmon/Kconfig              |    9 ++
>>>>   drivers/hwmon/Makefile             |    1 +
>>>>   drivers/hwmon/altera-a10sr-hwmon.c |  215
>>>> ++++++++++++++++++++++++++++++++++++
>>>>   3 files changed, 225 insertions(+)
>>>>   create mode 100644 drivers/hwmon/altera-a10sr-hwmon.c
>>>>
>>>> diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
>>>> index ff94007..af08846 100644
>>>> --- a/drivers/hwmon/Kconfig
>>>> +++ b/drivers/hwmon/Kconfig
>>>> @@ -248,6 +248,15 @@ config SENSORS_ADT7475
>>>>         This driver can also be build as a module.  If so, the module
>>>>         will be called adt7475.
>>>>
>>>> +config SENSORS_ALTERA_A10SR
>>>> +    bool "Altera Arria10 System Status"
>>>> +    depends on MFD_ALTERA_A10SR
>>>> +    help
>>>> +      If you say yes here you get support for the power ready status
>>>> +      for the Arria10's external power supplies on the Arria10 DevKit.
>>>> +      These values are read over the SPI bus from the Arria10 System
>>>> +      Resource chip.
>>>> +
>>>>   config SENSORS_ASC7621
>>>>       tristate "Andigilog aSC7621"
>>>>       depends on I2C
>>>> diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
>>>> index 2ef5b7c..17d72a7 100644
>>>> --- a/drivers/hwmon/Makefile
>>>> +++ b/drivers/hwmon/Makefile
>>>> @@ -43,6 +43,7 @@ obj-$(CONFIG_SENSORS_ADT7411)    += adt7411.o
>>>>   obj-$(CONFIG_SENSORS_ADT7462)    += adt7462.o
>>>>   obj-$(CONFIG_SENSORS_ADT7470)    += adt7470.o
>>>>   obj-$(CONFIG_SENSORS_ADT7475)    += adt7475.o
>>>> +obj-$(CONFIG_SENSORS_ALTERA_A10SR) += altera-a10sr-hwmon.o
>>>>   obj-$(CONFIG_SENSORS_APPLESMC)    += applesmc.o
>>>>   obj-$(CONFIG_SENSORS_ARM_SCPI)    += scpi-hwmon.o
>>>>   obj-$(CONFIG_SENSORS_ASC7621)    += asc7621.o
>>>> diff --git a/drivers/hwmon/altera-a10sr-hwmon.c
>>>> b/drivers/hwmon/altera-a10sr-hwmon.c
>>>> new file mode 100644
>>>> index 0000000..1eecc6b
>>>> --- /dev/null
>>>> +++ b/drivers/hwmon/altera-a10sr-hwmon.c
>>>> @@ -0,0 +1,215 @@
>>>> +/*
>>>> + *  Copyright Altera Corporation (C) 2014-2016. All Rights Reserved
>>>> + *
>>>> + * This program is free software; you can redistribute it and/or
>>>> modify it
>>>> + * under the terms and conditions of the GNU General Public License,
>>>> + * version 2, as published by the Free Software Foundation.
>>>> + *
>>>> + * This program is distributed in the hope it will be useful, but
>>>> WITHOUT
>>>> + * ANY WARRANTY; without even the implied warranty of
>>>> MERCHANTABILITY or
>>>> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
>>>> License for
>>>> + * more details.
>>>> + *
>>>> + * You should have received a copy of the GNU General Public
>>>> License along with
>>>> + * this program.  If not, see <http://www.gnu.org/licenses/>.
>>>> + *
>>>> + * HW Monitor driver for  Altera Arria10 MAX5 System Resource Chip
>>>> + * Adapted from DA9052
>>>> + */
>>>> +
>>>> +#include <linux/hwmon.h>
>>>> +#include <linux/hwmon-sysfs.h>
>>>> +#include <linux/mfd/altera-a10sr.h>
>>>> +#include <linux/module.h>
>>>> +#include <linux/of.h>
>>>
>>> Please list include files in alphabetic order.
>>>
>>
>> OK. I thought this was in alphabetical order. I'll update this after
>> figuring out where I was wrong.
>>
>
> Sorry, PBKAC on my side.
>
> Guenter
>
>>>> +
>>>> +#define ALTR_A10SR_1V0_BIT_POS          ALTR_A10SR_PG1_1V0_SHIFT
>>>> +#define ALTR_A10SR_0V95_BIT_POS         ALTR_A10SR_PG1_0V95_SHIFT
>>>> +#define ALTR_A10SR_0V9_BIT_POS          ALTR_A10SR_PG1_0V9_SHIFT
>>>> +#define ALTR_A10SR_10V_BIT_POS          ALTR_A10SR_PG1_10V_SHIFT
>>>> +#define ALTR_A10SR_5V0_BIT_POS          ALTR_A10SR_PG1_5V0_SHIFT
>>>> +#define ALTR_A10SR_3V3_BIT_POS          ALTR_A10SR_PG1_3V3_SHIFT
>>>> +#define ALTR_A10SR_2V5_BIT_POS          ALTR_A10SR_PG1_2V5_SHIFT
>>>> +#define ALTR_A10SR_1V8_BIT_POS          ALTR_A10SR_PG1_1V8_SHIFT
>>>> +#define ALTR_A10SR_OP_FLAG_BIT_POS      ALTR_A10SR_PG1_OP_FLAG_SHIFT
>>>> +/* 2nd register needs an offset of 8 to get to 2nd register */
>>>> +#define ALTR_A10SR_FBC2MP_BIT_POS       (8 +
>>>> ALTR_A10SR_PG2_FBC2MP_SHIFT)
>>>> +#define ALTR_A10SR_FAC2MP_BIT_POS       (8 +
>>>> ALTR_A10SR_PG2_FAC2MP_SHIFT)
>>>> +#define ALTR_A10SR_FMCBVADJ_BIT_POS     (8 +
>>>> ALTR_A10SR_PG2_FMCBVADJ_SHIFT)
>>>> +#define ALTR_A10SR_FMCAVADJ_BIT_POS     (8 +
>>>> ALTR_A10SR_PG2_FMCAVADJ_SHIFT)
>>>> +#define ALTR_A10SR_HL_VDDQ_BIT_POS      (8 +
>>>> ALTR_A10SR_PG2_HL_VDDQ_SHIFT)
>>>> +#define ALTR_A10SR_HL_VDD_BIT_POS       (8 +
>>>> ALTR_A10SR_PG2_HL_VDD_SHIFT)
>>>> +#define ALTR_A10SR_HL_HPS_BIT_POS       (8 +
>>>> ALTR_A10SR_PG2_HL_HPS_SHIFT)
>>>> +#define ALTR_A10SR_HPS_BIT_POS          (8 + ALTR_A10SR_PG2_HPS_SHIFT)
>>>> +/* 3rd register needs an offset of 16 to get to 3rd register */
>>>> +#define ALTR_A10SR_10V_FAIL_BIT_POS     (16 +
>>>> ALTR_A10SR_PG3_10V_FAIL_SHIFT)
>>>> +#define ALTR_A10SR_FAM2C_BIT_POS        (16 +
>>>> ALTR_A10SR_PG3_FAM2C_SHIFT)
>>>> +
>>>> +/**
>>>> + * struct altr_a10sr_hwmon - Altera Max5 HWMON device private data
>>>> structure
>>>> + * @device: hwmon class.
>>>> + * @regmap: the regmap from the parent device.
>>>> + */
>>>> +struct altr_a10sr_hwmon {
>>>> +    struct device        *class_device;
>>>> +    struct regmap        *regmap;
>>>> +};
>>>> +
>>>> +static ssize_t altr_a10sr_read_status(struct device *dev,
>>>> +                      struct device_attribute *devattr,
>>>> +                      char *buf)
>>>> +{
>>>> +    struct altr_a10sr_hwmon *hwmon = dev_get_drvdata(dev);
>>>> +    int val, ret, index = to_sensor_dev_attr(devattr)->index;
>>>> +    int mask = ALTR_A10SR_REG_BIT_MASK(index);
>>>> +    unsigned char reg = ALTR_A10SR_PWR_GOOD1_REG +
>>>> +                ALTR_A10SR_REG_OFFSET(index);
>>>> +
>>>> +    ret = regmap_read(hwmon->regmap, reg, &val);
>>>
>>> The pointer parameter to regmap_read() is unsigned int. I would suggest
>>> to use the same variable type to avoid surprises.
>>>
>> Understood. Thanks.
>>
>>>> +    if (ret < 0)
>>>> +        return ret;
>>>> +
>>>> +    return sprintf(buf, "%d\n", !!(~val & mask));
>>>
>>> Are alarms all active low ?
>>>
>> Yes, They are actually Power Good signals (Good = high) so I'm inverting.
>>
>>>> +}
>>>> +
>>>> +static ssize_t altr_a10sr_hwmon_show_name(struct device *dev,
>>>> +                      struct device_attribute *devattr,
>>>> +                      char *buf)
>>>> +{
>>>> +    return sprintf(buf, "altr_a10sr\n");
>>>> +}
>>>> +
>>>> +/* First Power Good Register Bits */
>>>> +static SENSOR_DEVICE_ATTR(1v0_alarm, S_IRUGO,
>>>> altr_a10sr_read_status, NULL,
>>>> +              ALTR_A10SR_1V0_BIT_POS);
>>>> +static SENSOR_DEVICE_ATTR(0v95_alarm, S_IRUGO,
>>>> altr_a10sr_read_status, NULL,
>>>> +              ALTR_A10SR_0V95_BIT_POS);
>>>> +static SENSOR_DEVICE_ATTR(0v9_alarm, S_IRUGO,
>>>> altr_a10sr_read_status, NULL,
>>>> +              ALTR_A10SR_0V9_BIT_POS);
>>>> +static SENSOR_DEVICE_ATTR(5v0_alarm, S_IRUGO,
>>>> altr_a10sr_read_status, NULL,
>>>> +              ALTR_A10SR_5V0_BIT_POS);
>>>> +static SENSOR_DEVICE_ATTR(3v3_alarm, S_IRUGO,
>>>> altr_a10sr_read_status, NULL,
>>>> +              ALTR_A10SR_3V3_BIT_POS);
>>>> +static SENSOR_DEVICE_ATTR(2v5_alarm, S_IRUGO,
>>>> altr_a10sr_read_status, NULL,
>>>> +              ALTR_A10SR_2V5_BIT_POS);
>>>> +static SENSOR_DEVICE_ATTR(1v8_alarm, S_IRUGO,
>>>> altr_a10sr_read_status, NULL,
>>>> +              ALTR_A10SR_1V8_BIT_POS);
>>>> +static SENSOR_DEVICE_ATTR(opflag_alarm, S_IRUGO,
>>>> altr_a10sr_read_status, NULL,
>>>> +              ALTR_A10SR_OP_FLAG_BIT_POS);
>>>> +/* Second Power Good Register Bits */
>>>> +static SENSOR_DEVICE_ATTR(fbc2mp_alarm, S_IRUGO,
>>>> altr_a10sr_read_status, NULL,
>>>> +              ALTR_A10SR_FBC2MP_BIT_POS);
>>>> +static SENSOR_DEVICE_ATTR(fac2mp_alarm, S_IRUGO,
>>>> altr_a10sr_read_status, NULL,
>>>> +              ALTR_A10SR_FAC2MP_BIT_POS);
>>>> +static SENSOR_DEVICE_ATTR(fmcbvadj_alarm, S_IRUGO,
>>>> altr_a10sr_read_status, NULL,
>>>> +              ALTR_A10SR_FMCBVADJ_BIT_POS);
>>>> +static SENSOR_DEVICE_ATTR(fmcavadj_alarm, S_IRUGO,
>>>> altr_a10sr_read_status, NULL,
>>>> +              ALTR_A10SR_FMCAVADJ_BIT_POS);
>>>> +static SENSOR_DEVICE_ATTR(hl_vddq_alarm, S_IRUGO,
>>>> altr_a10sr_read_status, NULL,
>>>> +              ALTR_A10SR_HL_VDDQ_BIT_POS);
>>>> +static SENSOR_DEVICE_ATTR(hl_vdd_alarm, S_IRUGO,
>>>> altr_a10sr_read_status, NULL,
>>>> +              ALTR_A10SR_HL_VDD_BIT_POS);
>>>> +static SENSOR_DEVICE_ATTR(hlhps_vdd_alarm, S_IRUGO,
>>>> altr_a10sr_read_status,
>>>> +              NULL, ALTR_A10SR_HL_HPS_BIT_POS);
>>>> +static SENSOR_DEVICE_ATTR(hps_alarm, S_IRUGO,
>>>> altr_a10sr_read_status, NULL,
>>>> +              ALTR_A10SR_HPS_BIT_POS);
>>>> +/* Third Power Good Register Bits */
>>>> +static SENSOR_DEVICE_ATTR(10v_alarm, S_IRUGO, altr_a10sr_read_status,
>>>> +              NULL, ALTR_A10SR_10V_FAIL_BIT_POS);
>>>> +static SENSOR_DEVICE_ATTR(fam2c_alarm, S_IRUGO,
>>>> altr_a10sr_read_status, NULL,
>>>> +              ALTR_A10SR_FAM2C_BIT_POS);
>>>> +
>>>> +static DEVICE_ATTR(name, S_IRUGO, altr_a10sr_hwmon_show_name, NULL);
>>>> +
>>>> +static struct attribute *altr_a10sr_attr[] = {
>>>> +    &dev_attr_name.attr,
>>>> +    /* First Power Good Register */
>>>> +    &sensor_dev_attr_opflag_alarm.dev_attr.attr,
>>>> +    &sensor_dev_attr_1v8_alarm.dev_attr.attr,
>>>> +    &sensor_dev_attr_2v5_alarm.dev_attr.attr,
>>>> +    &sensor_dev_attr_1v0_alarm.dev_attr.attr,
>>>> +    &sensor_dev_attr_3v3_alarm.dev_attr.attr,
>>>> +    &sensor_dev_attr_5v0_alarm.dev_attr.attr,
>>>> +    &sensor_dev_attr_0v9_alarm.dev_attr.attr,
>>>> +    &sensor_dev_attr_0v95_alarm.dev_attr.attr,
>>>> +    /* Second Power Good Register */
>>>> +    &sensor_dev_attr_hps_alarm.dev_attr.attr,
>>>> +    &sensor_dev_attr_hlhps_vdd_alarm.dev_attr.attr,
>>>> +    &sensor_dev_attr_hl_vdd_alarm.dev_attr.attr,
>>>> +    &sensor_dev_attr_hl_vddq_alarm.dev_attr.attr,
>>>> +    &sensor_dev_attr_fmcavadj_alarm.dev_attr.attr,
>>>> +    &sensor_dev_attr_fmcbvadj_alarm.dev_attr.attr,
>>>> +    &sensor_dev_attr_fac2mp_alarm.dev_attr.attr,
>>>> +    &sensor_dev_attr_fbc2mp_alarm.dev_attr.attr,
>>>> +    /* Third Power Good Register */
>>>> +    &sensor_dev_attr_10v_alarm.dev_attr.attr,
>>>> +    &sensor_dev_attr_fam2c_alarm.dev_attr.attr,
>>>
>>> Ultimately, this doesn't really make much sense, even with standard
>>> attribute
>>> names. The ABI assumes that _input attrributes exist. Not sure if
>>> that could
>>> be solved by providing 'dummy' unreadable input attributes
>>> (permission 0);
>>> that might be worth a try. If you want to attach names to the
>>> attributes,
>>> you would need to provide label attributes. Specifically you would need
>>>
>>>     inX_input (with permission 0) - not sure if that is even possible
>>>     inX_alarm
>>>     inX_label
>>>
>> Hmm. OK. I may need to rethink this.
>>
>>>> +    NULL
>>>> +};
>>>> +
>>>> +static const struct attribute_group altr_a10sr_attr_group = {
>>>> +    .attrs = altr_a10sr_attr
>>>> +};
>>>> +
>>>> +static int altr_a10sr_hwmon_probe(struct platform_device *pdev)
>>>> +{
>>>> +    struct altr_a10sr_hwmon *hwmon;
>>>> +    int ret;
>>>> +    struct altr_a10sr *a10sr = dev_get_drvdata(pdev->dev.parent);
>>>> +
>>>
>>> What if someone creates a stand-alone devicetree property for this
>>> driver,
>>> and there is no parent (or parent driver data) ?
>>>
>> I agree if this was a commercially available part. However, this is a
>> specific driver for a programmable logic device (PLD) that will always
>> be part of an MFD parent. The PLD only supports the Altera Development
>> Kit.
>>
>>>> +    hwmon = devm_kzalloc(&pdev->dev, sizeof(*hwmon), GFP_KERNEL);
>>>> +    if (!hwmon)
>>>> +        return -ENOMEM;
>>>> +
>>>> +    hwmon->regmap = a10sr->regmap;
>>>> +
>>>> +    platform_set_drvdata(pdev, hwmon);
>>>> +
>>>> +    ret = sysfs_create_group(&pdev->dev.kobj, &altr_a10sr_attr_group);
>>>> +    if (ret)
>>>> +        goto err_mem;
>>>> +
>>>> +    hwmon->class_device = hwmon_device_register(&pdev->dev);
>>>> +    if (IS_ERR(hwmon->class_device)) {
>>>> +        ret = PTR_ERR(hwmon->class_device);
>>>> +        goto err_sysfs;
>>>> +    }
>>>
>>> Please use devm_hwmon_device_register_with_groups().
>>>
>> Understood. Thanks.
>>
>> Thanks for reviewing.
>>
>>>> +
>>>> +    return 0;
>>>> +
>>>> +err_sysfs:
>>>> +    sysfs_remove_group(&pdev->dev.kobj, &altr_a10sr_attr_group);
>>>> +err_mem:
>>>> +    return ret;
>>>> +}
>>>> +
>>>> +static int altr_a10sr_hwmon_remove(struct platform_device *pdev)
>>>> +{
>>>> +    struct altr_a10sr_hwmon *hwmon = platform_get_drvdata(pdev);
>>>> +
>>>> +    hwmon_device_unregister(hwmon->class_device);
>>>> +    sysfs_remove_group(&pdev->dev.kobj, &altr_a10sr_attr_group);
>>>> +
>>>> +    return 0;
>>>> +}
>>>> +
>>>> +static const struct of_device_id altr_a10sr_hwmon_of_match[] = {
>>>> +    { .compatible = "altr,a10sr-hwmon" },
>>>> +    { },
>>>> +};
>>>> +MODULE_DEVICE_TABLE(of, altr_a10sr_hwmon_of_match);
>>>> +
>>>> +static struct platform_driver altr_a10sr_hwmon_driver = {
>>>> +    .probe = altr_a10sr_hwmon_probe,
>>>> +    .remove = altr_a10sr_hwmon_remove,
>>>> +    .driver = {
>>>> +        .name = "altr_a10sr_hwmon",
>>>> +        .of_match_table = of_match_ptr(altr_a10sr_hwmon_of_match),
>>>> +    },
>>>> +};
>>>> +
>>>> +module_platform_driver(altr_a10sr_hwmon_driver);
>>>> +
>>>> +MODULE_LICENSE("GPL v2");
>>>> +MODULE_AUTHOR("Thor Thayer <tthayer@opensource.altera.com>");
>>>> +MODULE_DESCRIPTION("HW Monitor driver for Altera Arria10 System
>>>> Resource Chip");
>>>> --
>>>> 1.7.9.5
>>>>
>>
>

[PATCH 11/11] ARM: socfpga: dts: Add A10-SR Devkit power supply alarms

[tthayer]

From: Thor Thayer <tthayer@opensource.altera.com>

Add the Altera Arria10 Devkit power supply alarms.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
 arch/arm/boot/dts/socfpga_arria10_socdk.dtsi |    4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
index e2addf9..dc4457b 100644
--- a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
@@ -107,6 +107,10 @@
 			gpio-controller;
 			#gpio-cells = <2>;
 		};
+
+		ps_alarm {
+			compatible = "altr,a10sr-hwmon";
+		};
 	};
 };
 
-- 
1.7.9.5

[PATCH 11/11] ARM: socfpga: dts: Add A10-SR Devkit power supply alarms

[tthayer]

From: Thor Thayer <tthayer@opensource.altera.com>

Add the Altera Arria10 Devkit power supply alarms.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
 arch/arm/boot/dts/socfpga_arria10_socdk.dtsi |    4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
index e2addf9..dc4457b 100644
--- a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
@@ -107,6 +107,10 @@
 			gpio-controller;
 			#gpio-cells = <2>;
 		};
+
+		ps_alarm {
+			compatible = "altr,a10sr-hwmon";
+		};
 	};
 };
 
-- 
1.7.9.5

Re: [PATCH 01/11] dt-bindings: mfd: Add Altera Arria10 System Resource Chip bindings

[Thor Thayer]

On 04/26/2016 07:33 AM, Rob Herring wrote:

On Mon, Apr 25, 2016 at 10:01:52AM -0500, Thor Thayer wrote:



On 04/25/2016 07:55 AM, Rob Herring wrote:

On Fri, Apr 22, 2016 at 10:33:29AM -0500, ttha...@opensource.altera.com wrote:

From: Thor Thayer <ttha...@opensource.altera.com>
To: linux-hwmon@vger.kernel.org

The Altera Arria10 Devkit System Resource chip is a Multi-Function
Device with a GPIO expander and power supply alarm.


An alarm with no interrupt? Are the GPIOs interrupt capable?


The alarms have no interrupt but the GPIOs are interrupt capable (not
implemented with interrupt capability in this patch series).


Please make the binding as complete as possible even if you don't
support features in the driver yet. Driver features may evolve, but a
specific h/w doesn't.

Rob


Understood. Thanks for the explanation.
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Re: [PATCH 01/11] dt-bindings: mfd: Add Altera Arria10 System Resource Chip bindings

[Thor Thayer]

On 04/26/2016 07:33 AM, Rob Herring wrote:
> On Mon, Apr 25, 2016 at 10:01:52AM -0500, Thor Thayer wrote:
>>
>>
>> On 04/25/2016 07:55 AM, Rob Herring wrote:
>>> On Fri, Apr 22, 2016 at 10:33:29AM -0500, tthayer@opensource.altera.com wrote:
>>>> From: Thor Thayer <tthayer@opensource.altera.com>
>>>>
>>>> The Altera Arria10 Devkit System Resource chip is a Multi-Function
>>>> Device with a GPIO expander and power supply alarm.
>>>
>>> An alarm with no interrupt? Are the GPIOs interrupt capable?
>>
>> The alarms have no interrupt but the GPIOs are interrupt capable (not
>> implemented with interrupt capability in this patch series).
>
> Please make the binding as complete as possible even if you don't
> support features in the driver yet. Driver features may evolve, but a
> specific h/w doesn't.
>
> Rob
>
Understood. Thanks for the explanation.

Re: [PATCH 03/11] mfd: altr_a10sr: Add Altera Arria10 DevKit System Resource Chip

[Thor Thayer]

On 05/09/2016 11:02 AM, Lee Jones wrote:

On Fri, 22 Apr 2016, ttha...@opensource.altera.com wrote:


From: Thor Thayer <ttha...@opensource.altera.com>
To: linux-hwmon@vger.kernel.org

Add support for the Altera Arria10 Development Kit System Resource
chip which is implemented using a MAX5 as a external gpio extender,
and power supply alarm (hwmon) with the regmap framework over a SPI bus.

Signed-off-by: Thor Thayer <ttha...@opensource.altera.com>
---
  drivers/mfd/Kconfig              |   11 +++
  drivers/mfd/Makefile             |    2 +
  drivers/mfd/altera-a10sr.c       |  179 ++++++++++++++++++++++++++++++++++++++
  include/linux/mfd/altera-a10sr.h |   87 ++++++++++++++++++
  4 files changed, 279 insertions(+)
  create mode 100644 drivers/mfd/altera-a10sr.c
  create mode 100644 include/linux/mfd/altera-a10sr.h

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index eea61e3..4fc27c6 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -18,6 +18,17 @@ config MFD_CS5535
          This is the core driver for CS5535/CS5536 MFD functions.  This is
            necessary for using the board's GPIO and MFGPT functionality.

+config MFD_ALTERA_A10SR
+       bool "Altera Arria10 DevKit System Resource chip"
+       depends on ARCH_SOCFPGA && SPI_MASTER=y && OF
+       select REGMAP_SPI
+       select MFD_CORE
+       help
+         Support for the Altera Arria10 DevKit MAX5 System Resource chip
+         using the SPI interface. This driver provides common support for
+         accessing the external gpio extender (LEDs & buttons) and
+         power supply alarms (hwmon).
+
  config MFD_ACT8945A
        tristate "Active-semi ACT8945A"
        select MFD_CORE
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 5eaa6465d..4f1ff91 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -203,3 +203,5 @@ intel-soc-pmic-objs         := intel_soc_pmic_core.o 
intel_soc_pmic_crc.o
  intel-soc-pmic-$(CONFIG_INTEL_PMC_IPC)        += intel_soc_pmic_bxtwc.o
  obj-$(CONFIG_INTEL_SOC_PMIC)  += intel-soc-pmic.o
  obj-$(CONFIG_MFD_MT6397)      += mt6397-core.o
+
+obj-$(CONFIG_MFD_ALTERA_A10SR) += altera-a10sr.o
diff --git a/drivers/mfd/altera-a10sr.c b/drivers/mfd/altera-a10sr.c
new file mode 100644
index 0000000..2ff08e3
--- /dev/null
+++ b/drivers/mfd/altera-a10sr.c
@@ -0,0 +1,179 @@
+/*
+ * Copyright Altera Corporation (C) 2014-2016. All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * SPI access for Altera Arria10 MAX5 System Resource Chip
+ *
+ * Adapted from DA9052
+ * Copyright(c) 2011 Dialog Semiconductor Ltd.
+ * Author: David Dajun Chen <dc...@diasemi.com>


You don't need to carry the copyright or authorship tags over.


OK. Thanks,


+ */
+
+#include <linux/mfd/altera-a10sr.h>
+#include <linux/mfd/core.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/spi/spi.h>
+
+static const struct mfd_cell altr_a10sr_subdev_info[] = {
+       {
+               .name = "altr_a10sr_gpio",
+               .of_compatible = "altr,a10sr-gpio",
+       },
+};
+
+static bool altr_a10sr_reg_readable(struct device *dev, unsigned int reg)
+{
+       switch (reg) {
+       case ALTR_A10SR_VERSION_READ:
+       case ALTR_A10SR_LED_REG:
+       case ALTR_A10SR_PBDSW_REG:
+       case ALTR_A10SR_PBDSW_IRQ_REG:
+       case ALTR_A10SR_PWR_GOOD1_REG:
+       case ALTR_A10SR_PWR_GOOD2_REG:
+       case ALTR_A10SR_PWR_GOOD3_REG:
+       case ALTR_A10SR_FMCAB_REG:
+       case ALTR_A10SR_HPS_RST_REG:
+       case ALTR_A10SR_USB_QSPI_REG:
+       case ALTR_A10SR_SFPA_REG:
+       case ALTR_A10SR_SFPB_REG:
+       case ALTR_A10SR_I2C_M_REG:
+       case ALTR_A10SR_WARM_RST_REG:
+       case ALTR_A10SR_WR_KEY_REG:
+       case ALTR_A10SR_PMBUS_REG:
+               return true;
+       default:
+               return false;
+       }
+}
+
+static bool altr_a10sr_reg_writeable(struct device *dev, unsigned int reg)
+{
+       switch (reg) {
+       case ALTR_A10SR_LED_REG:
+       case ALTR_A10SR_PBDSW_IRQ_REG:
+       case ALTR_A10SR_FMCAB_REG:
+       case ALTR_A10SR_HPS_RST_REG:
+       case ALTR_A10SR_USB_QSPI_REG:
+       case ALTR_A10SR_SFPA_REG:
+       case ALTR_A10SR_SFPB_REG:
+       case ALTR_A10SR_WARM_RST_REG:
+       case ALTR_A10SR_WR_KEY_REG:
+       case ALTR_A10SR_PMBUS_REG:
+               return true;
+       default:
+               return false;
+       }
+}
+
+static bool altr_a10sr_reg_volatile(struct device *dev, unsigned int reg)
+{
+       switch (reg) {
+       case ALTR_A10SR_PBDSW_REG:
+       case ALTR_A10SR_PBDSW_IRQ_REG:
+       case ALTR_A10SR_PWR_GOOD1_REG:
+       case ALTR_A10SR_PWR_GOOD2_REG:
+       case ALTR_A10SR_PWR_GOOD3_REG:
+       case ALTR_A10SR_HPS_RST_REG:
+       case ALTR_A10SR_I2C_M_REG:
+       case ALTR_A10SR_WARM_RST_REG:
+       case ALTR_A10SR_WR_KEY_REG:
+       case ALTR_A10SR_PMBUS_REG:
+               return true;
+       default:
+               return false;
+       }
+}
+
+const struct regmap_config altr_a10sr_regmap_config = {
+       .reg_bits = 8,
+       .val_bits = 8,
+
+       .cache_type = REGCACHE_NONE,
+
+       .use_single_rw = true,
+       .read_flag_mask = 1,
+       .write_flag_mask = 0,
+
+       .max_register = ALTR_A10SR_WR_KEY_REG,
+       .readable_reg = altr_a10sr_reg_readable,
+       .writeable_reg = altr_a10sr_reg_writeable,
+       .volatile_reg = altr_a10sr_reg_volatile,
+
+};
+
+static int altr_a10sr_spi_probe(struct spi_device *spi)
+{
+       int ret;
+       struct altr_a10sr *a10sr;
+
+       a10sr = devm_kzalloc(&spi->dev, sizeof(*a10sr),
+                            GFP_KERNEL);
+       if (!a10sr)
+               return -ENOMEM;
+
+       spi->mode = SPI_MODE_3;
+       spi->bits_per_word = 8;
+       spi_setup(spi);
+
+       a10sr->dev = &spi->dev;
+
+       spi_set_drvdata(spi, a10sr);
+
+       a10sr->regmap = devm_regmap_init_spi(spi, &altr_a10sr_regmap_config);
+       if (IS_ERR(a10sr->regmap)) {
+               ret = PTR_ERR(a10sr->regmap);
+               dev_err(&spi->dev, "Failed to allocate register map: %d\n",
+                       ret);
+               return ret;
+       }


Is this regmap used it more than one driver?

Yes, Currently, both the subdevices (GPIO & HWMON) use this regmap to 
communicate to the SPI registers.



+       ret = mfd_add_devices(a10sr->dev, PLATFORM_DEVID_AUTO,
+                             altr_a10sr_subdev_info,
+                             ARRAY_SIZE(altr_a10sr_subdev_info),
+                             NULL, 0, NULL);
+       if (ret)
+               dev_err(a10sr->dev, "Failed to register sub-devices: %d\n",
+                       ret);
+
+       return ret;
+}
+
+static int altr_a10sr_spi_remove(struct spi_device *spi)
+{
+       mfd_remove_devices(&spi->dev);
+
+       return 0;
+}


Use devm_mfd_add_devices() and remove this function.


OK.


+static const struct of_device_id altr_a10sr_spi_of_match[] = {
+       { .compatible = "altr,a10sr" },
+       { },
+};
+MODULE_DEVICE_TABLE(of, altr_a10sr_spi_of_match);
+
+static struct spi_driver altr_a10sr_spi_driver = {
+       .probe = altr_a10sr_spi_probe,
+       .remove = altr_a10sr_spi_remove,


Remove .remove.


+       .driver = {
+               .name = "altr_a10sr",
+               .of_match_table = of_match_ptr(altr_a10sr_spi_of_match),
+       },
+};
+
+module_spi_driver(altr_a10sr_spi_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Thor Thayer <ttha...@opensource.altera.com>");
+MODULE_DESCRIPTION("Altera Arria10 DevKit System Resource MFD Driver");
diff --git a/include/linux/mfd/altera-a10sr.h b/include/linux/mfd/altera-a10sr.h
new file mode 100644
index 0000000..c869fe7
--- /dev/null
+++ b/include/linux/mfd/altera-a10sr.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright Altera Corporation (C) 2014-2016. All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * Declarations for Altera Arria10 MAX5 System Resource Chip
+ *
+ * Adapted from DA9052
+ * Copyright(c) 2011 Dialog Semiconductor Ltd.
+ * Author: David Dajun Chen <dc...@diasemi.com>


Remove these two lines.


Will do. Thanks for reviewing!


+ */
+
+#ifndef __MFD_ALTERA_A10SR_H
+#define __MFD_ALTERA_A10SR_H
+
+#include <linux/completion.h>
+#include <linux/list.h>
+#include <linux/mfd/core.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+
+/* Write registers are always on even addresses */
+#define  WRITE_REG_MASK              0xFE
+/* Odd registers are always on odd addresses */
+#define  READ_REG_MASK               0x01
+
+#define ALTR_A10SR_BITS_PER_REGISTER  8
+/*
+ * To find the correct register, we divide the input GPIO by
+ * the number of GPIO in each register. We then need to multiply
+ * by 2 because the reads are at odd addresses.
+ */
+#define ALTR_A10SR_REG_OFFSET(X)     (((X) / ALTR_A10SR_BITS_PER_REGISTER) << 
1)
+#define ALTR_A10SR_REG_BIT(X)        ((X) % ALTR_A10SR_BITS_PER_REGISTER)
+#define ALTR_A10SR_REG_BIT_CHG(X, Y) ((X) << ALTR_A10SR_REG_BIT(Y))
+#define ALTR_A10SR_REG_BIT_MASK(X)   (1 << ALTR_A10SR_REG_BIT(X))
+
+/* Arria10 System Controller Register Defines */
+#define ALTR_A10SR_NOP                0x00    /* No Change */
+#define ALTR_A10SR_VERSION_READ       0x00    /* MAX5 Version Read */
+
+#define ALTR_A10SR_LED_REG            0x02    /* LED - Upper 4 bits */
+/* LED register Bit Definitions */
+#define ALTR_A10SR_LED_VALID_SHIFT        4       /* LED - Upper 4 bits valid 
*/
+#define ALTR_A10SR_OUT_VALID_RANGE_LO     ALTR_A10SR_LED_VALID_SHIFT
+#define ALTR_A10SR_OUT_VALID_RANGE_HI     7
+
+#define ALTR_A10SR_PBDSW_REG          0x04    /* PB & DIP SW - Input only */
+#define ALTR_A10SR_PBDSW_IRQ_REG      0x06    /* PB & DIP SW Flag Clear */
+/* Pushbutton & DIP Switch Bit Definitions */
+#define ALTR_A10SR_IN_VALID_RANGE_LO      8
+#define ALTR_A10SR_IN_VALID_RANGE_HI      15
+
+#define ALTR_A10SR_PWR_GOOD1_REG      0x08    /* Power Good1 Read */
+#define ALTR_A10SR_PWR_GOOD2_REG      0x0A    /* Power Good2 Read */
+#define ALTR_A10SR_PWR_GOOD3_REG      0x0C    /* Power Good3 Read */
+#define ALTR_A10SR_FMCAB_REG          0x0E    /* FMCA/B & PCIe Pwr Enable */
+#define ALTR_A10SR_HPS_RST_REG        0x10    /* HPS Reset */
+#define ALTR_A10SR_USB_QSPI_REG       0x12    /* USB, BQSPI, FILE Reset */
+#define ALTR_A10SR_SFPA_REG           0x14    /* SFPA Control Reg */
+#define ALTR_A10SR_SFPB_REG           0x16    /* SFPB Control Reg */
+#define ALTR_A10SR_I2C_M_REG          0x18    /* I2C Master Select */
+#define ALTR_A10SR_WARM_RST_REG       0x1A    /* HPS Warm Reset */
+#define ALTR_A10SR_WR_KEY_REG         0x1C    /* HPS Warm Reset Key */
+#define ALTR_A10SR_PMBUS_REG          0x1E    /* HPS PM Bus */
+
+/**
+ * struct altr_a10sr - Altera Max5 MFD device private data structure
+ * @dev:  : this device
+ * @regmap: the regmap assigned to the parent device.
+ */
+struct altr_a10sr {
+       struct device *dev;
+       struct regmap *regmap;
+};
+
+#endif /* __MFD_ALTERA_A10SR_H */



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Re: [PATCH 03/11] mfd: altr_a10sr: Add Altera Arria10 DevKit System Resource Chip

[Thor Thayer]

On 05/09/2016 11:02 AM, Lee Jones wrote:
> On Fri, 22 Apr 2016, tthayer@opensource.altera.com wrote:
>
>> From: Thor Thayer <tthayer@opensource.altera.com>
>>
>> Add support for the Altera Arria10 Development Kit System Resource
>> chip which is implemented using a MAX5 as a external gpio extender,
>> and power supply alarm (hwmon) with the regmap framework over a SPI bus.
>>
>> Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
>> ---
>>   drivers/mfd/Kconfig              |   11 +++
>>   drivers/mfd/Makefile             |    2 +
>>   drivers/mfd/altera-a10sr.c       |  179 ++++++++++++++++++++++++++++++++++++++
>>   include/linux/mfd/altera-a10sr.h |   87 ++++++++++++++++++
>>   4 files changed, 279 insertions(+)
>>   create mode 100644 drivers/mfd/altera-a10sr.c
>>   create mode 100644 include/linux/mfd/altera-a10sr.h
>>
>> diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
>> index eea61e3..4fc27c6 100644
>> --- a/drivers/mfd/Kconfig
>> +++ b/drivers/mfd/Kconfig
>> @@ -18,6 +18,17 @@ config MFD_CS5535
>>   	  This is the core driver for CS5535/CS5536 MFD functions.  This is
>>             necessary for using the board's GPIO and MFGPT functionality.
>>
>> +config MFD_ALTERA_A10SR
>> +       bool "Altera Arria10 DevKit System Resource chip"
>> +       depends on ARCH_SOCFPGA && SPI_MASTER=y && OF
>> +       select REGMAP_SPI
>> +       select MFD_CORE
>> +       help
>> +         Support for the Altera Arria10 DevKit MAX5 System Resource chip
>> +         using the SPI interface. This driver provides common support for
>> +         accessing the external gpio extender (LEDs & buttons) and
>> +         power supply alarms (hwmon).
>> +
>>   config MFD_ACT8945A
>>   	tristate "Active-semi ACT8945A"
>>   	select MFD_CORE
>> diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
>> index 5eaa6465d..4f1ff91 100644
>> --- a/drivers/mfd/Makefile
>> +++ b/drivers/mfd/Makefile
>> @@ -203,3 +203,5 @@ intel-soc-pmic-objs		:= intel_soc_pmic_core.o intel_soc_pmic_crc.o
>>   intel-soc-pmic-$(CONFIG_INTEL_PMC_IPC)	+= intel_soc_pmic_bxtwc.o
>>   obj-$(CONFIG_INTEL_SOC_PMIC)	+= intel-soc-pmic.o
>>   obj-$(CONFIG_MFD_MT6397)	+= mt6397-core.o
>> +
>> +obj-$(CONFIG_MFD_ALTERA_A10SR)	+= altera-a10sr.o
>> diff --git a/drivers/mfd/altera-a10sr.c b/drivers/mfd/altera-a10sr.c
>> new file mode 100644
>> index 0000000..2ff08e3
>> --- /dev/null
>> +++ b/drivers/mfd/altera-a10sr.c
>> @@ -0,0 +1,179 @@
>> +/*
>> + * Copyright Altera Corporation (C) 2014-2016. All Rights Reserved
>> + *
>> + * This program is free software; you can redistribute it and/or modify it
>> + * under the terms and conditions of the GNU General Public License,
>> + * version 2, as published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope it will be useful, but WITHOUT
>> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
>> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
>> + * more details.
>> + *
>> + * You should have received a copy of the GNU General Public License along with
>> + * this program.  If not, see <http://www.gnu.org/licenses/>.
>> + *
>> + * SPI access for Altera Arria10 MAX5 System Resource Chip
>> + *
>> + * Adapted from DA9052
>> + * Copyright(c) 2011 Dialog Semiconductor Ltd.
>> + * Author: David Dajun Chen <dchen@diasemi.com>
>
> You don't need to carry the copyright or authorship tags over.
>
OK. Thanks,

>> + */
>> +
>> +#include <linux/mfd/altera-a10sr.h>
>> +#include <linux/mfd/core.h>
>> +#include <linux/module.h>
>> +#include <linux/of.h>
>> +#include <linux/spi/spi.h>
>> +
>> +static const struct mfd_cell altr_a10sr_subdev_info[] = {
>> +	{
>> +		.name = "altr_a10sr_gpio",
>> +		.of_compatible = "altr,a10sr-gpio",
>> +	},
>> +};
>> +
>> +static bool altr_a10sr_reg_readable(struct device *dev, unsigned int reg)
>> +{
>> +	switch (reg) {
>> +	case ALTR_A10SR_VERSION_READ:
>> +	case ALTR_A10SR_LED_REG:
>> +	case ALTR_A10SR_PBDSW_REG:
>> +	case ALTR_A10SR_PBDSW_IRQ_REG:
>> +	case ALTR_A10SR_PWR_GOOD1_REG:
>> +	case ALTR_A10SR_PWR_GOOD2_REG:
>> +	case ALTR_A10SR_PWR_GOOD3_REG:
>> +	case ALTR_A10SR_FMCAB_REG:
>> +	case ALTR_A10SR_HPS_RST_REG:
>> +	case ALTR_A10SR_USB_QSPI_REG:
>> +	case ALTR_A10SR_SFPA_REG:
>> +	case ALTR_A10SR_SFPB_REG:
>> +	case ALTR_A10SR_I2C_M_REG:
>> +	case ALTR_A10SR_WARM_RST_REG:
>> +	case ALTR_A10SR_WR_KEY_REG:
>> +	case ALTR_A10SR_PMBUS_REG:
>> +		return true;
>> +	default:
>> +		return false;
>> +	}
>> +}
>> +
>> +static bool altr_a10sr_reg_writeable(struct device *dev, unsigned int reg)
>> +{
>> +	switch (reg) {
>> +	case ALTR_A10SR_LED_REG:
>> +	case ALTR_A10SR_PBDSW_IRQ_REG:
>> +	case ALTR_A10SR_FMCAB_REG:
>> +	case ALTR_A10SR_HPS_RST_REG:
>> +	case ALTR_A10SR_USB_QSPI_REG:
>> +	case ALTR_A10SR_SFPA_REG:
>> +	case ALTR_A10SR_SFPB_REG:
>> +	case ALTR_A10SR_WARM_RST_REG:
>> +	case ALTR_A10SR_WR_KEY_REG:
>> +	case ALTR_A10SR_PMBUS_REG:
>> +		return true;
>> +	default:
>> +		return false;
>> +	}
>> +}
>> +
>> +static bool altr_a10sr_reg_volatile(struct device *dev, unsigned int reg)
>> +{
>> +	switch (reg) {
>> +	case ALTR_A10SR_PBDSW_REG:
>> +	case ALTR_A10SR_PBDSW_IRQ_REG:
>> +	case ALTR_A10SR_PWR_GOOD1_REG:
>> +	case ALTR_A10SR_PWR_GOOD2_REG:
>> +	case ALTR_A10SR_PWR_GOOD3_REG:
>> +	case ALTR_A10SR_HPS_RST_REG:
>> +	case ALTR_A10SR_I2C_M_REG:
>> +	case ALTR_A10SR_WARM_RST_REG:
>> +	case ALTR_A10SR_WR_KEY_REG:
>> +	case ALTR_A10SR_PMBUS_REG:
>> +		return true;
>> +	default:
>> +		return false;
>> +	}
>> +}
>> +
>> +const struct regmap_config altr_a10sr_regmap_config = {
>> +	.reg_bits = 8,
>> +	.val_bits = 8,
>> +
>> +	.cache_type = REGCACHE_NONE,
>> +
>> +	.use_single_rw = true,
>> +	.read_flag_mask = 1,
>> +	.write_flag_mask = 0,
>> +
>> +	.max_register = ALTR_A10SR_WR_KEY_REG,
>> +	.readable_reg = altr_a10sr_reg_readable,
>> +	.writeable_reg = altr_a10sr_reg_writeable,
>> +	.volatile_reg = altr_a10sr_reg_volatile,
>> +
>> +};
>> +
>> +static int altr_a10sr_spi_probe(struct spi_device *spi)
>> +{
>> +	int ret;
>> +	struct altr_a10sr *a10sr;
>> +
>> +	a10sr = devm_kzalloc(&spi->dev, sizeof(*a10sr),
>> +			     GFP_KERNEL);
>> +	if (!a10sr)
>> +		return -ENOMEM;
>> +
>> +	spi->mode = SPI_MODE_3;
>> +	spi->bits_per_word = 8;
>> +	spi_setup(spi);
>> +
>> +	a10sr->dev = &spi->dev;
>> +
>> +	spi_set_drvdata(spi, a10sr);
>> +
>> +	a10sr->regmap = devm_regmap_init_spi(spi, &altr_a10sr_regmap_config);
>> +	if (IS_ERR(a10sr->regmap)) {
>> +		ret = PTR_ERR(a10sr->regmap);
>> +		dev_err(&spi->dev, "Failed to allocate register map: %d\n",
>> +			ret);
>> +		return ret;
>> +	}
>
> Is this regmap used it more than one driver?
>
Yes, Currently, both the subdevices (GPIO & HWMON) use this regmap to 
communicate to the SPI registers.

>> +	ret = mfd_add_devices(a10sr->dev, PLATFORM_DEVID_AUTO,
>> +			      altr_a10sr_subdev_info,
>> +			      ARRAY_SIZE(altr_a10sr_subdev_info),
>> +			      NULL, 0, NULL);
>> +	if (ret)
>> +		dev_err(a10sr->dev, "Failed to register sub-devices: %d\n",
>> +			ret);
>> +
>> +	return ret;
>> +}
>> +
>> +static int altr_a10sr_spi_remove(struct spi_device *spi)
>> +{
>> +	mfd_remove_devices(&spi->dev);
>> +
>> +	return 0;
>> +}
>
> Use devm_mfd_add_devices() and remove this function.
>
OK.

>> +static const struct of_device_id altr_a10sr_spi_of_match[] = {
>> +	{ .compatible = "altr,a10sr" },
>> +	{ },
>> +};
>> +MODULE_DEVICE_TABLE(of, altr_a10sr_spi_of_match);
>> +
>> +static struct spi_driver altr_a10sr_spi_driver = {
>> +	.probe = altr_a10sr_spi_probe,
>> +	.remove = altr_a10sr_spi_remove,
>
> Remove .remove.
>
>> +	.driver = {
>> +		.name = "altr_a10sr",
>> +		.of_match_table = of_match_ptr(altr_a10sr_spi_of_match),
>> +	},
>> +};
>> +
>> +module_spi_driver(altr_a10sr_spi_driver);
>> +
>> +MODULE_LICENSE("GPL v2");
>> +MODULE_AUTHOR("Thor Thayer <tthayer@opensource.altera.com>");
>> +MODULE_DESCRIPTION("Altera Arria10 DevKit System Resource MFD Driver");
>> diff --git a/include/linux/mfd/altera-a10sr.h b/include/linux/mfd/altera-a10sr.h
>> new file mode 100644
>> index 0000000..c869fe7
>> --- /dev/null
>> +++ b/include/linux/mfd/altera-a10sr.h
>> @@ -0,0 +1,87 @@
>> +/*
>> + * Copyright Altera Corporation (C) 2014-2016. All Rights Reserved
>> + *
>> + * This program is free software; you can redistribute it and/or modify it
>> + * under the terms and conditions of the GNU General Public License,
>> + * version 2, as published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope it will be useful, but WITHOUT
>> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
>> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
>> + * more details.
>> + *
>> + * You should have received a copy of the GNU General Public License along with
>> + * this program.  If not, see <http://www.gnu.org/licenses/>.
>> + *
>> + * Declarations for Altera Arria10 MAX5 System Resource Chip
>> + *
>> + * Adapted from DA9052
>> + * Copyright(c) 2011 Dialog Semiconductor Ltd.
>> + * Author: David Dajun Chen <dchen@diasemi.com>
>
> Remove these two lines.
>
Will do. Thanks for reviewing!

>> + */
>> +
>> +#ifndef __MFD_ALTERA_A10SR_H
>> +#define __MFD_ALTERA_A10SR_H
>> +
>> +#include <linux/completion.h>
>> +#include <linux/list.h>
>> +#include <linux/mfd/core.h>
>> +#include <linux/regmap.h>
>> +#include <linux/slab.h>
>> +
>> +/* Write registers are always on even addresses */
>> +#define  WRITE_REG_MASK              0xFE
>> +/* Odd registers are always on odd addresses */
>> +#define  READ_REG_MASK               0x01
>> +
>> +#define ALTR_A10SR_BITS_PER_REGISTER  8
>> +/*
>> + * To find the correct register, we divide the input GPIO by
>> + * the number of GPIO in each register. We then need to multiply
>> + * by 2 because the reads are at odd addresses.
>> + */
>> +#define ALTR_A10SR_REG_OFFSET(X)     (((X) / ALTR_A10SR_BITS_PER_REGISTER) << 1)
>> +#define ALTR_A10SR_REG_BIT(X)        ((X) % ALTR_A10SR_BITS_PER_REGISTER)
>> +#define ALTR_A10SR_REG_BIT_CHG(X, Y) ((X) << ALTR_A10SR_REG_BIT(Y))
>> +#define ALTR_A10SR_REG_BIT_MASK(X)   (1 << ALTR_A10SR_REG_BIT(X))
>> +
>> +/* Arria10 System Controller Register Defines */
>> +#define ALTR_A10SR_NOP                0x00    /* No Change */
>> +#define ALTR_A10SR_VERSION_READ       0x00    /* MAX5 Version Read */
>> +
>> +#define ALTR_A10SR_LED_REG            0x02    /* LED - Upper 4 bits */
>> +/* LED register Bit Definitions */
>> +#define ALTR_A10SR_LED_VALID_SHIFT        4       /* LED - Upper 4 bits valid */
>> +#define ALTR_A10SR_OUT_VALID_RANGE_LO     ALTR_A10SR_LED_VALID_SHIFT
>> +#define ALTR_A10SR_OUT_VALID_RANGE_HI     7
>> +
>> +#define ALTR_A10SR_PBDSW_REG          0x04    /* PB & DIP SW - Input only */
>> +#define ALTR_A10SR_PBDSW_IRQ_REG      0x06    /* PB & DIP SW Flag Clear */
>> +/* Pushbutton & DIP Switch Bit Definitions */
>> +#define ALTR_A10SR_IN_VALID_RANGE_LO      8
>> +#define ALTR_A10SR_IN_VALID_RANGE_HI      15
>> +
>> +#define ALTR_A10SR_PWR_GOOD1_REG      0x08    /* Power Good1 Read */
>> +#define ALTR_A10SR_PWR_GOOD2_REG      0x0A    /* Power Good2 Read */
>> +#define ALTR_A10SR_PWR_GOOD3_REG      0x0C    /* Power Good3 Read */
>> +#define ALTR_A10SR_FMCAB_REG          0x0E    /* FMCA/B & PCIe Pwr Enable */
>> +#define ALTR_A10SR_HPS_RST_REG        0x10    /* HPS Reset */
>> +#define ALTR_A10SR_USB_QSPI_REG       0x12    /* USB, BQSPI, FILE Reset */
>> +#define ALTR_A10SR_SFPA_REG           0x14    /* SFPA Control Reg */
>> +#define ALTR_A10SR_SFPB_REG           0x16    /* SFPB Control Reg */
>> +#define ALTR_A10SR_I2C_M_REG          0x18    /* I2C Master Select */
>> +#define ALTR_A10SR_WARM_RST_REG       0x1A    /* HPS Warm Reset */
>> +#define ALTR_A10SR_WR_KEY_REG         0x1C    /* HPS Warm Reset Key */
>> +#define ALTR_A10SR_PMBUS_REG          0x1E    /* HPS PM Bus */
>> +
>> +/**
>> + * struct altr_a10sr - Altera Max5 MFD device private data structure
>> + * @dev:  : this device
>> + * @regmap: the regmap assigned to the parent device.
>> + */
>> +struct altr_a10sr {
>> +	struct device *dev;
>> +	struct regmap *regmap;
>> +};
>> +
>> +#endif /* __MFD_ALTERA_A10SR_H */
>