From: Wolfram Sang <wsa@the-dreams.de>
To: Jisheng Zhang <jszhang@marvell.com>
Cc: Rob Herring <robh@kernel.org>,
pawel.moll@arm.com, mark.rutland@arm.com,
ijc+devicetree@hellion.org.uk, galak@codeaurora.org,
jarkko.nikula@linux.intel.com, andriy.shevchenko@linux.intel.com,
mika.westerberg@linux.intel.com, linux-i2c@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH] i2c: designware-platdrv: get fast/std speed scl high/low count from DT
Date: Sun, 24 Apr 2016 22:39:23 +0200 [thread overview]
Message-ID: <20160424203922.GC4317@katana> (raw)
In-Reply-To: <20160413201147.5621a17c@xhacker>
[-- Attachment #1: Type: text/plain, Size: 1480 bytes --]
On Wed, Apr 13, 2016 at 08:11:47PM +0800, Jisheng Zhang wrote:
> Dear Rob,
>
> On Thu, 7 Apr 2016 12:57:59 -0500 Rob Herring wrote:
>
> > On Wed, Apr 06, 2016 at 03:28:00PM +0800, Jisheng Zhang wrote:
> > > Sometimes, it's convenient to define the scl's high/low count directly,
> > > e.g HW people would do some measurement then directly give out the
> > > optimum counts. Previously, we solved the sda falling time and scl
> > > falling time by i2c_dw_scl_hcnt() and i2c_dw_scl_lcnt(), then put them
> > > into dt, but what we really care isn't the sda/scl falling time.
> >
> > This is just so you can put specific clock count instead of converting
> > from nanoseconds with standard properties or you gain some additional
> > control of the timing. If only the former, then I prefer we stick with
> > the common properties.
>
> To be honest, both. Let me show how I gain additional control of the timing
> with this patch while I can't do this w/o it.
>
> I want the similar high percent of SCL high for both standard-mode and
> fast-mode. Before this patch, this is not achievable because the parameters
> to cal the hcnt/lcnt via i2c_dw_scl_hcnt() and i2c_dw_scl_lcnt() are different
> for standard-mode and fast-mode.
If there is something you can't describe currently, then we can add
additional properties to allow you to do what you want. But they should
be generic bindings and not a plain value which is custom to this driver.
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WARNING: multiple messages have this Message-ID (diff)
From: Wolfram Sang <wsa-z923LK4zBo2bacvFa/9K2g@public.gmane.org>
To: Jisheng Zhang <jszhang-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>
Cc: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
pawel.moll-5wv7dgnIgG8@public.gmane.org,
mark.rutland-5wv7dgnIgG8@public.gmane.org,
ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org,
galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org,
jarkko.nikula-VuQAYsv1563Yd54FQh9/CA@public.gmane.org,
andriy.shevchenko-VuQAYsv1563Yd54FQh9/CA@public.gmane.org,
mika.westerberg-VuQAYsv1563Yd54FQh9/CA@public.gmane.org,
linux-i2c-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Subject: Re: [PATCH] i2c: designware-platdrv: get fast/std speed scl high/low count from DT
Date: Sun, 24 Apr 2016 22:39:23 +0200 [thread overview]
Message-ID: <20160424203922.GC4317@katana> (raw)
In-Reply-To: <20160413201147.5621a17c@xhacker>
[-- Attachment #1: Type: text/plain, Size: 1480 bytes --]
On Wed, Apr 13, 2016 at 08:11:47PM +0800, Jisheng Zhang wrote:
> Dear Rob,
>
> On Thu, 7 Apr 2016 12:57:59 -0500 Rob Herring wrote:
>
> > On Wed, Apr 06, 2016 at 03:28:00PM +0800, Jisheng Zhang wrote:
> > > Sometimes, it's convenient to define the scl's high/low count directly,
> > > e.g HW people would do some measurement then directly give out the
> > > optimum counts. Previously, we solved the sda falling time and scl
> > > falling time by i2c_dw_scl_hcnt() and i2c_dw_scl_lcnt(), then put them
> > > into dt, but what we really care isn't the sda/scl falling time.
> >
> > This is just so you can put specific clock count instead of converting
> > from nanoseconds with standard properties or you gain some additional
> > control of the timing. If only the former, then I prefer we stick with
> > the common properties.
>
> To be honest, both. Let me show how I gain additional control of the timing
> with this patch while I can't do this w/o it.
>
> I want the similar high percent of SCL high for both standard-mode and
> fast-mode. Before this patch, this is not achievable because the parameters
> to cal the hcnt/lcnt via i2c_dw_scl_hcnt() and i2c_dw_scl_lcnt() are different
> for standard-mode and fast-mode.
If there is something you can't describe currently, then we can add
additional properties to allow you to do what you want. But they should
be generic bindings and not a plain value which is custom to this driver.
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WARNING: multiple messages have this Message-ID (diff)
From: wsa@the-dreams.de (Wolfram Sang)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] i2c: designware-platdrv: get fast/std speed scl high/low count from DT
Date: Sun, 24 Apr 2016 22:39:23 +0200 [thread overview]
Message-ID: <20160424203922.GC4317@katana> (raw)
In-Reply-To: <20160413201147.5621a17c@xhacker>
On Wed, Apr 13, 2016 at 08:11:47PM +0800, Jisheng Zhang wrote:
> Dear Rob,
>
> On Thu, 7 Apr 2016 12:57:59 -0500 Rob Herring wrote:
>
> > On Wed, Apr 06, 2016 at 03:28:00PM +0800, Jisheng Zhang wrote:
> > > Sometimes, it's convenient to define the scl's high/low count directly,
> > > e.g HW people would do some measurement then directly give out the
> > > optimum counts. Previously, we solved the sda falling time and scl
> > > falling time by i2c_dw_scl_hcnt() and i2c_dw_scl_lcnt(), then put them
> > > into dt, but what we really care isn't the sda/scl falling time.
> >
> > This is just so you can put specific clock count instead of converting
> > from nanoseconds with standard properties or you gain some additional
> > control of the timing. If only the former, then I prefer we stick with
> > the common properties.
>
> To be honest, both. Let me show how I gain additional control of the timing
> with this patch while I can't do this w/o it.
>
> I want the similar high percent of SCL high for both standard-mode and
> fast-mode. Before this patch, this is not achievable because the parameters
> to cal the hcnt/lcnt via i2c_dw_scl_hcnt() and i2c_dw_scl_lcnt() are different
> for standard-mode and fast-mode.
If there is something you can't describe currently, then we can add
additional properties to allow you to do what you want. But they should
be generic bindings and not a plain value which is custom to this driver.
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next prev parent reply other threads:[~2016-04-24 20:39 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-04-06 7:28 [PATCH] i2c: designware-platdrv: get fast/std speed scl high/low count from DT Jisheng Zhang
2016-04-06 7:28 ` Jisheng Zhang
2016-04-06 7:28 ` Jisheng Zhang
2016-04-07 17:57 ` Rob Herring
2016-04-07 17:57 ` Rob Herring
2016-04-07 17:57 ` Rob Herring
2016-04-13 12:11 ` Jisheng Zhang
2016-04-13 12:11 ` Jisheng Zhang
2016-04-13 12:11 ` Jisheng Zhang
2016-04-24 20:39 ` Wolfram Sang [this message]
2016-04-24 20:39 ` Wolfram Sang
2016-04-24 20:39 ` Wolfram Sang
2016-04-07 18:05 ` Andy Shevchenko
2016-04-07 18:05 ` Andy Shevchenko
2016-04-13 12:16 ` Jisheng Zhang
2016-04-13 12:16 ` Jisheng Zhang
2016-04-13 12:16 ` Jisheng Zhang
2016-04-13 13:23 ` Andy Shevchenko
2016-04-13 13:23 ` Andy Shevchenko
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