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From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
To: Arnd Bergmann <arnd@arndb.de>
Cc: Lior Amsalem <alior@marvell.com>, Andrew Lunn <andrew@lunn.ch>,
	Yehuda Yitschak <yehuday@marvell.com>,
	Jason Cooper <jason@lakedaemon.net>,
	linux-pci@vger.kernel.org, Hanna Hawa <hannah@marvell.com>,
	Nadav Haklai <nadavh@marvell.com>,
	Gregory Clement <gregory.clement@free-electrons.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Marcin Wojtas <mw@semihalf.com>,
	linux-arm-kernel@lists.infradead.org,
	Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Subject: Re: [PATCH 1/3] dt-bindings: add DT binding for the Aardvark PCIe controller
Date: Wed, 8 Jun 2016 16:27:50 +0200	[thread overview]
Message-ID: <20160608162750.712916ce@free-electrons.com> (raw)
In-Reply-To: <33469694.MLbpCUJe2G@wuerfel>

Hello,

Thanks for your review!

On Thu, 02 Jun 2016 11:35:38 +0200, Arnd Bergmann wrote:
> On Thursday, June 2, 2016 11:09:43 AM CEST Thomas Petazzoni wrote:
> > +               ranges = <0x82000000 0 0xe8000000   0 0xe8000000 0 0x1000000 /* Port 0 MEM */
> > +                         0x81000000 0 0xe9000000   0 0xe9000000 0 0x10000>; /* Port 0 IO*/
> >   
> 
> Any reason for not having a 64-bit MEM prefetchable area in the example?
> Does the host not support that?

I'll have to admit I am not sure how to find this out from the
datasheet. My datasheet says about the PCIe controller:

"""
64-bit PCIe address and system address space for outbound transactions
"""

So I guess this would indicate that a 64-bit MEM area is possible.
However, since anyway the area used above is at 0xe8000000 for a length
of 0x1000000, what would be the benefit of declaring this range as a
64-bit one ?

Regarding the prefetchable aspect, I couldn't find any reference in the
datasheet. However, the original driver code explicitly errors out if
there is no non-prefetchable memory area, so I guess prefetchable
areas is not supported.

In of_bus_pci_get_flags(), both the 32-bit and 64-bit cases are handled
in the same way, so is this distinction actually being used by the
kernel?

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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WARNING: multiple messages have this Message-ID (diff)
From: thomas.petazzoni@free-electrons.com (Thomas Petazzoni)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 1/3] dt-bindings: add DT binding for the Aardvark PCIe controller
Date: Wed, 8 Jun 2016 16:27:50 +0200	[thread overview]
Message-ID: <20160608162750.712916ce@free-electrons.com> (raw)
In-Reply-To: <33469694.MLbpCUJe2G@wuerfel>

Hello,

Thanks for your review!

On Thu, 02 Jun 2016 11:35:38 +0200, Arnd Bergmann wrote:
> On Thursday, June 2, 2016 11:09:43 AM CEST Thomas Petazzoni wrote:
> > +               ranges = <0x82000000 0 0xe8000000   0 0xe8000000 0 0x1000000 /* Port 0 MEM */
> > +                         0x81000000 0 0xe9000000   0 0xe9000000 0 0x10000>; /* Port 0 IO*/
> >   
> 
> Any reason for not having a 64-bit MEM prefetchable area in the example?
> Does the host not support that?

I'll have to admit I am not sure how to find this out from the
datasheet. My datasheet says about the PCIe controller:

"""
64-bit PCIe address and system address space for outbound transactions
"""

So I guess this would indicate that a 64-bit MEM area is possible.
However, since anyway the area used above is at 0xe8000000 for a length
of 0x1000000, what would be the benefit of declaring this range as a
64-bit one ?

Regarding the prefetchable aspect, I couldn't find any reference in the
datasheet. However, the original driver code explicitly errors out if
there is no non-prefetchable memory area, so I guess prefetchable
areas is not supported.

In of_bus_pci_get_flags(), both the 32-bit and 64-bit cases are handled
in the same way, so is this distinction actually being used by the
kernel?

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

  reply	other threads:[~2016-06-08 14:27 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-06-02  9:09 [PATCH 0/3] PCIe controller driver for Marvell Armada 3700 Thomas Petazzoni
2016-06-02  9:09 ` Thomas Petazzoni
2016-06-02  9:09 ` [PATCH 1/3] dt-bindings: add DT binding for the Aardvark PCIe controller Thomas Petazzoni
2016-06-02  9:09   ` Thomas Petazzoni
2016-06-02  9:35   ` Arnd Bergmann
2016-06-02  9:35     ` Arnd Bergmann
2016-06-08 14:27     ` Thomas Petazzoni [this message]
2016-06-08 14:27       ` Thomas Petazzoni
2016-06-08 15:34       ` Arnd Bergmann
2016-06-08 15:34         ` Arnd Bergmann
2016-06-02 12:24   ` Andrew Lunn
2016-06-02 12:24     ` Andrew Lunn
2016-06-02 12:34     ` Arnd Bergmann
2016-06-02 12:34       ` Arnd Bergmann
2016-06-02 12:45       ` Thomas Petazzoni
2016-06-02 12:45         ` Thomas Petazzoni
2016-06-02 13:53         ` Arnd Bergmann
2016-06-02 13:53           ` Arnd Bergmann
2016-06-08 14:28       ` Thomas Petazzoni
2016-06-08 14:28         ` Thomas Petazzoni
2016-06-10 15:44   ` Bjorn Helgaas
2016-06-10 15:44     ` Bjorn Helgaas
2016-06-10 15:47     ` Thomas Petazzoni
2016-06-10 15:47       ` Thomas Petazzoni
2016-06-02  9:09 ` [PATCH 2/3] PCI: host: new PCI host controller driver for Marvell Armada 3700 Thomas Petazzoni
2016-06-02  9:09   ` Thomas Petazzoni
2016-06-02  9:46   ` Arnd Bergmann
2016-06-02  9:46     ` Arnd Bergmann
2016-06-09  9:19     ` Thomas Petazzoni
2016-06-09  9:19       ` Thomas Petazzoni
2016-06-09 12:19       ` Arnd Bergmann
2016-06-09 12:19         ` Arnd Bergmann
2016-06-09 12:36         ` Thomas Petazzoni
2016-06-09 12:36           ` Thomas Petazzoni
2016-06-04  0:24   ` kbuild test robot
2016-06-04  0:24     ` kbuild test robot
2016-06-08 15:15   ` Marcin Wojtas
2016-06-08 15:15     ` Marcin Wojtas
2016-06-08 15:47     ` Thomas Petazzoni
2016-06-08 15:47       ` Thomas Petazzoni
2016-06-02  9:09 ` [PATCH 3/3] arm64: dts: marvell: PCIe support for " Thomas Petazzoni
2016-06-02  9:09   ` Thomas Petazzoni

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