From: Arnd Bergmann <arnd@arndb.de> To: linux-arm-kernel@lists.infradead.org Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>, Bjorn Helgaas <bhelgaas@google.com>, linux-pci@vger.kernel.org, Lior Amsalem <alior@marvell.com>, Andrew Lunn <andrew@lunn.ch>, Yehuda Yitschak <yehuday@marvell.com>, Jason Cooper <jason@lakedaemon.net>, Hanna Hawa <hannah@marvell.com>, Nadav Haklai <nadavh@marvell.com>, Gregory Clement <gregory.clement@free-electrons.com>, Marcin Wojtas <mw@semihalf.com>, Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Subject: Re: [PATCH 2/3] PCI: host: new PCI host controller driver for Marvell Armada 3700 Date: Thu, 02 Jun 2016 11:46:04 +0200 [thread overview] Message-ID: <3112077.0RPfokLCAs@wuerfel> (raw) In-Reply-To: <1464858585-10963-3-git-send-email-thomas.petazzoni@free-electrons.com> On Thursday, June 2, 2016 11:09:44 AM CEST Thomas Petazzoni wrote: > +static bool advk_pcie_link_up(struct advk_pcie *pcie) > +{ > + int timeout; > + u32 ltssm_state; > + u32 val; > + > + timeout = PCIE_LINKUP_TIMEOUT; > + do { > + val = advk_readl(pcie, CFG_REG); > + ltssm_state = (val >> LTSSM_SHIFT) & LTSSM_MASK; > + timeout--; > + /* Use ltssm < LTSSM_L0 instead of ltssm != LTSSM_L0 */ > + } while (ltssm_state < LTSSM_L0 && timeout > 0); > + > + return (timeout > 0); > +} Maybe wait for some amount of time to have passed here (using time_before(jiffies, end)) rather than a number of retries, for robustness and determinism. > + /* Point PCIe unit MBUS decode windows to DRAM space. */ > + for (i = 0; i < 8; i++) > + advk_pcie_set_ob_win(pcie, i, 0, 0, 0, 0, 0, 0, 0); Is this actually mbus based, or is the comment copied from some other Marvell driver? > +static int advk_pcie_setup_msi_irq(struct msi_controller *chip, > + struct pci_dev *pdev, > + struct msi_desc *desc) > +{ > + struct advk_pcie *pcie = pdev->bus->sysdata; > + struct msi_msg msg; > + int virq, hwirq; > + phys_addr_t msi_msg_phys; > + > + /* We support MSI, but not MSI-X */ > + if (desc->msi_attrib.is_msix) > + return -EINVAL; > + > + hwirq = advk_pcie_alloc_msi(pcie); > + if (hwirq < 0) > + return hwirq; > + > + virq = irq_create_mapping(pcie->msi_domain, hwirq); > + if (!virq) { > + advk_pcie_free_msi(pcie, hwirq); > + return -EINVAL; > + } What is the version of the GIC in the Armada 3700? If you have GICv3 or GICv2m, could you use that instead of the built-in MSI logic? We typically handle this using the msi-map or msi-parent properties pointing to either the gic or the PCI host, depending on which one you want to use, but either of them should work, and the GIC should be more efficient because you can distribute the interrupts of the PCI devices over all CPUs by workload, rather than having to multiplex all MSI through a single GIC interrupt. Arnd
WARNING: multiple messages have this Message-ID (diff)
From: arnd@arndb.de (Arnd Bergmann) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 2/3] PCI: host: new PCI host controller driver for Marvell Armada 3700 Date: Thu, 02 Jun 2016 11:46:04 +0200 [thread overview] Message-ID: <3112077.0RPfokLCAs@wuerfel> (raw) In-Reply-To: <1464858585-10963-3-git-send-email-thomas.petazzoni@free-electrons.com> On Thursday, June 2, 2016 11:09:44 AM CEST Thomas Petazzoni wrote: > +static bool advk_pcie_link_up(struct advk_pcie *pcie) > +{ > + int timeout; > + u32 ltssm_state; > + u32 val; > + > + timeout = PCIE_LINKUP_TIMEOUT; > + do { > + val = advk_readl(pcie, CFG_REG); > + ltssm_state = (val >> LTSSM_SHIFT) & LTSSM_MASK; > + timeout--; > + /* Use ltssm < LTSSM_L0 instead of ltssm != LTSSM_L0 */ > + } while (ltssm_state < LTSSM_L0 && timeout > 0); > + > + return (timeout > 0); > +} Maybe wait for some amount of time to have passed here (using time_before(jiffies, end)) rather than a number of retries, for robustness and determinism. > + /* Point PCIe unit MBUS decode windows to DRAM space. */ > + for (i = 0; i < 8; i++) > + advk_pcie_set_ob_win(pcie, i, 0, 0, 0, 0, 0, 0, 0); Is this actually mbus based, or is the comment copied from some other Marvell driver? > +static int advk_pcie_setup_msi_irq(struct msi_controller *chip, > + struct pci_dev *pdev, > + struct msi_desc *desc) > +{ > + struct advk_pcie *pcie = pdev->bus->sysdata; > + struct msi_msg msg; > + int virq, hwirq; > + phys_addr_t msi_msg_phys; > + > + /* We support MSI, but not MSI-X */ > + if (desc->msi_attrib.is_msix) > + return -EINVAL; > + > + hwirq = advk_pcie_alloc_msi(pcie); > + if (hwirq < 0) > + return hwirq; > + > + virq = irq_create_mapping(pcie->msi_domain, hwirq); > + if (!virq) { > + advk_pcie_free_msi(pcie, hwirq); > + return -EINVAL; > + } What is the version of the GIC in the Armada 3700? If you have GICv3 or GICv2m, could you use that instead of the built-in MSI logic? We typically handle this using the msi-map or msi-parent properties pointing to either the gic or the PCI host, depending on which one you want to use, but either of them should work, and the GIC should be more efficient because you can distribute the interrupts of the PCI devices over all CPUs by workload, rather than having to multiplex all MSI through a single GIC interrupt. Arnd
next prev parent reply other threads:[~2016-06-02 9:46 UTC|newest] Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top 2016-06-02 9:09 [PATCH 0/3] PCIe controller driver for Marvell Armada 3700 Thomas Petazzoni 2016-06-02 9:09 ` Thomas Petazzoni 2016-06-02 9:09 ` [PATCH 1/3] dt-bindings: add DT binding for the Aardvark PCIe controller Thomas Petazzoni 2016-06-02 9:09 ` Thomas Petazzoni 2016-06-02 9:35 ` Arnd Bergmann 2016-06-02 9:35 ` Arnd Bergmann 2016-06-08 14:27 ` Thomas Petazzoni 2016-06-08 14:27 ` Thomas Petazzoni 2016-06-08 15:34 ` Arnd Bergmann 2016-06-08 15:34 ` Arnd Bergmann 2016-06-02 12:24 ` Andrew Lunn 2016-06-02 12:24 ` Andrew Lunn 2016-06-02 12:34 ` Arnd Bergmann 2016-06-02 12:34 ` Arnd Bergmann 2016-06-02 12:45 ` Thomas Petazzoni 2016-06-02 12:45 ` Thomas Petazzoni 2016-06-02 13:53 ` Arnd Bergmann 2016-06-02 13:53 ` Arnd Bergmann 2016-06-08 14:28 ` Thomas Petazzoni 2016-06-08 14:28 ` Thomas Petazzoni 2016-06-10 15:44 ` Bjorn Helgaas 2016-06-10 15:44 ` Bjorn Helgaas 2016-06-10 15:47 ` Thomas Petazzoni 2016-06-10 15:47 ` Thomas Petazzoni 2016-06-02 9:09 ` [PATCH 2/3] PCI: host: new PCI host controller driver for Marvell Armada 3700 Thomas Petazzoni 2016-06-02 9:09 ` Thomas Petazzoni 2016-06-02 9:46 ` Arnd Bergmann [this message] 2016-06-02 9:46 ` Arnd Bergmann 2016-06-09 9:19 ` Thomas Petazzoni 2016-06-09 9:19 ` Thomas Petazzoni 2016-06-09 12:19 ` Arnd Bergmann 2016-06-09 12:19 ` Arnd Bergmann 2016-06-09 12:36 ` Thomas Petazzoni 2016-06-09 12:36 ` Thomas Petazzoni 2016-06-04 0:24 ` kbuild test robot 2016-06-04 0:24 ` kbuild test robot 2016-06-08 15:15 ` Marcin Wojtas 2016-06-08 15:15 ` Marcin Wojtas 2016-06-08 15:47 ` Thomas Petazzoni 2016-06-08 15:47 ` Thomas Petazzoni 2016-06-02 9:09 ` [PATCH 3/3] arm64: dts: marvell: PCIe support for " Thomas Petazzoni 2016-06-02 9:09 ` Thomas Petazzoni
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=3112077.0RPfokLCAs@wuerfel \ --to=arnd@arndb.de \ --cc=alior@marvell.com \ --cc=andrew@lunn.ch \ --cc=bhelgaas@google.com \ --cc=gregory.clement@free-electrons.com \ --cc=hannah@marvell.com \ --cc=jason@lakedaemon.net \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-pci@vger.kernel.org \ --cc=mw@semihalf.com \ --cc=nadavh@marvell.com \ --cc=sebastian.hesselbarth@gmail.com \ --cc=thomas.petazzoni@free-electrons.com \ --cc=yehuday@marvell.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.