* [PATCH 1/3] PCI: rockchip: Rename accessors
@ 2016-10-07 16:27 Bjorn Helgaas
2016-10-07 16:27 ` [PATCH 2/3] PCI: rockchip: Swap order of rockchip_writel() reg/val arguments Bjorn Helgaas
` (2 more replies)
0 siblings, 3 replies; 9+ messages in thread
From: Bjorn Helgaas @ 2016-10-07 16:27 UTC (permalink / raw)
To: Shawn Lin, Wenrui Li, Heiko Stuebner; +Cc: linux-rockchip, linux-pci
Rename rockchip_pcie_read() to rockchip_readl() and rockchip_pcie_write()
to rockchip_writel() for consistency with other drivers. No functional
change intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
drivers/pci/host/pcie-rockchip.c | 85 +++++++++++++++++++-------------------
1 file changed, 42 insertions(+), 43 deletions(-)
diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index b8c82fc..0ef2f9f 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -204,12 +204,12 @@ struct rockchip_pcie {
struct irq_domain *irq_domain;
};
-static u32 rockchip_pcie_read(struct rockchip_pcie *rockchip, u32 reg)
+static u32 rockchip_readl(struct rockchip_pcie *rockchip, u32 reg)
{
return readl(rockchip->apb_base + reg);
}
-static void rockchip_pcie_write(struct rockchip_pcie *rockchip, u32 val,
+static void rockchip_writel(struct rockchip_pcie *rockchip, u32 val,
u32 reg)
{
writel(val, rockchip->apb_base + reg);
@@ -219,18 +219,18 @@ static void rockchip_pcie_enable_bw_int(struct rockchip_pcie *rockchip)
{
u32 status;
- status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
+ status = rockchip_readl(rockchip, PCIE_RC_CONFIG_LCS);
status |= (PCIE_RC_CONFIG_LCS_LBMIE | PCIE_RC_CONFIG_LCS_LABIE);
- rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
+ rockchip_writel(rockchip, status, PCIE_RC_CONFIG_LCS);
}
static void rockchip_pcie_clr_bw_int(struct rockchip_pcie *rockchip)
{
u32 status;
- status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
+ status = rockchip_readl(rockchip, PCIE_RC_CONFIG_LCS);
status |= (PCIE_RC_CONFIG_LCS_LBMS | PCIE_RC_CONFIG_LCS_LAMS);
- rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
+ rockchip_writel(rockchip, status, PCIE_RC_CONFIG_LCS);
}
static void rockchip_pcie_update_txcredit_mui(struct rockchip_pcie *rockchip)
@@ -238,10 +238,10 @@ static void rockchip_pcie_update_txcredit_mui(struct rockchip_pcie *rockchip)
u32 val;
/* Update Tx credit maximum update interval */
- val = rockchip_pcie_read(rockchip, PCIE_CORE_TXCREDIT_CFG1);
+ val = rockchip_readl(rockchip, PCIE_CORE_TXCREDIT_CFG1);
val &= ~PCIE_CORE_TXCREDIT_CFG1_MUI_MASK;
val |= PCIE_CORE_TXCREDIT_CFG1_MUI_ENCODE(24000); /* ns */
- rockchip_pcie_write(rockchip, val, PCIE_CORE_TXCREDIT_CFG1);
+ rockchip_writel(rockchip, val, PCIE_CORE_TXCREDIT_CFG1);
}
static int rockchip_pcie_valid_device(struct rockchip_pcie *rockchip,
@@ -438,7 +438,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
return err;
}
- rockchip_pcie_write(rockchip,
+ rockchip_writel(rockchip,
PCIE_CLIENT_CONF_ENABLE |
PCIE_CLIENT_LINK_TRAIN_ENABLE |
PCIE_CLIENT_ARI_ENABLE |
@@ -487,17 +487,17 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
* reliable and enabling ASPM doesn't work. This is a controller
* bug we need to work around.
*/
- status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
- rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
+ status = rockchip_readl(rockchip, PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
+ rockchip_writel(rockchip, status, PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
/* Fix the transmitted FTS count desired to exit from L0s. */
- status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL_PLC1);
+ status = rockchip_readl(rockchip, PCIE_CORE_CTRL_PLC1);
status = (status & PCIE_CORE_CTRL_PLC1_FTS_MASK) |
(PCIE_CORE_CTRL_PLC1_FTS_CNT << PCIE_CORE_CTRL_PLC1_FTS_SHIFT);
- rockchip_pcie_write(rockchip, status, PCIE_CORE_CTRL_PLC1);
+ rockchip_writel(rockchip, status, PCIE_CORE_CTRL_PLC1);
/* Enable Gen1 training */
- rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
+ rockchip_writel(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
PCIE_CLIENT_CONFIG);
gpiod_set_value(rockchip->ep_gpio, 1);
@@ -506,8 +506,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
timeout = jiffies + msecs_to_jiffies(500);
for (;;) {
- status = rockchip_pcie_read(rockchip,
- PCIE_CLIENT_BASIC_STATUS1);
+ status = rockchip_readl(rockchip, PCIE_CLIENT_BASIC_STATUS1);
if ((status & PCIE_CLIENT_LINK_STATUS_MASK) ==
PCIE_CLIENT_LINK_STATUS_UP) {
dev_dbg(dev, "PCIe link training gen1 pass!\n");
@@ -526,13 +525,13 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
* Enable retrain for gen2. This should be configured only after
* gen1 finished.
*/
- status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
+ status = rockchip_readl(rockchip, PCIE_RC_CONFIG_LCS);
status |= PCIE_RC_CONFIG_LCS_RETRAIN_LINK;
- rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
+ rockchip_writel(rockchip, status, PCIE_RC_CONFIG_LCS);
timeout = jiffies + msecs_to_jiffies(500);
for (;;) {
- status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);
+ status = rockchip_readl(rockchip, PCIE_CORE_CTRL);
if ((status & PCIE_CORE_PL_CONF_SPEED_MASK) ==
PCIE_CORE_PL_CONF_SPEED_5G) {
dev_dbg(dev, "PCIe link training gen2 pass!\n");
@@ -548,25 +547,25 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
}
/* Check the final link width from negotiated lane counter from MGMT */
- status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);
+ status = rockchip_readl(rockchip, PCIE_CORE_CTRL);
status = 0x1 << ((status & PCIE_CORE_PL_CONF_LANE_MASK) >>
PCIE_CORE_PL_CONF_LANE_MASK);
dev_dbg(dev, "current link width is x%d\n", status);
- rockchip_pcie_write(rockchip, ROCKCHIP_VENDOR_ID,
+ rockchip_writel(rockchip, ROCKCHIP_VENDOR_ID,
PCIE_RC_CONFIG_VENDOR);
- rockchip_pcie_write(rockchip,
+ rockchip_writel(rockchip,
PCI_CLASS_BRIDGE_PCI << PCIE_RC_CONFIG_SCC_SHIFT,
PCIE_RC_CONFIG_RID_CCR);
- rockchip_pcie_write(rockchip, 0x0, PCIE_RC_BAR_CONF);
+ rockchip_writel(rockchip, 0x0, PCIE_RC_BAR_CONF);
- rockchip_pcie_write(rockchip,
+ rockchip_writel(rockchip,
(RC_REGION_0_ADDR_TRANS_L + RC_REGION_0_PASS_BITS),
PCIE_CORE_OB_REGION_ADDR0);
- rockchip_pcie_write(rockchip, RC_REGION_0_ADDR_TRANS_H,
+ rockchip_writel(rockchip, RC_REGION_0_ADDR_TRANS_H,
PCIE_CORE_OB_REGION_ADDR1);
- rockchip_pcie_write(rockchip, 0x0080000a, PCIE_CORE_OB_REGION_DESC0);
- rockchip_pcie_write(rockchip, 0x0, PCIE_CORE_OB_REGION_DESC1);
+ rockchip_writel(rockchip, 0x0080000a, PCIE_CORE_OB_REGION_DESC0);
+ rockchip_writel(rockchip, 0x0, PCIE_CORE_OB_REGION_DESC1);
return 0;
}
@@ -578,10 +577,10 @@ static irqreturn_t rockchip_pcie_subsys_irq_handler(int irq, void *arg)
u32 reg;
u32 sub_reg;
- reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
+ reg = rockchip_readl(rockchip, PCIE_CLIENT_INT_STATUS);
if (reg & PCIE_CLIENT_INT_LOCAL) {
dev_dbg(dev, "local interrupt received\n");
- sub_reg = rockchip_pcie_read(rockchip, PCIE_CORE_INT_STATUS);
+ sub_reg = rockchip_readl(rockchip, PCIE_CORE_INT_STATUS);
if (sub_reg & PCIE_CORE_INT_PRFPE)
dev_dbg(dev, "parity error detected while reading from the PNP receive FIFO RAM\n");
@@ -624,15 +623,15 @@ static irqreturn_t rockchip_pcie_subsys_irq_handler(int irq, void *arg)
if (sub_reg & PCIE_CORE_INT_MMVC)
dev_dbg(dev, "MSI mask register changes\n");
- rockchip_pcie_write(rockchip, sub_reg, PCIE_CORE_INT_STATUS);
+ rockchip_writel(rockchip, sub_reg, PCIE_CORE_INT_STATUS);
} else if (reg & PCIE_CLIENT_INT_PHY) {
dev_dbg(dev, "phy link changes\n");
rockchip_pcie_update_txcredit_mui(rockchip);
rockchip_pcie_clr_bw_int(rockchip);
}
- rockchip_pcie_write(rockchip, reg & PCIE_CLIENT_INT_LOCAL,
- PCIE_CLIENT_INT_STATUS);
+ rockchip_writel(rockchip, reg & PCIE_CLIENT_INT_LOCAL,
+ PCIE_CLIENT_INT_STATUS);
return IRQ_HANDLED;
}
@@ -643,7 +642,7 @@ static irqreturn_t rockchip_pcie_client_irq_handler(int irq, void *arg)
struct device *dev = rockchip->dev;
u32 reg;
- reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
+ reg = rockchip_readl(rockchip, PCIE_CLIENT_INT_STATUS);
if (reg & PCIE_CLIENT_INT_LEGACY_DONE)
dev_dbg(dev, "legacy done interrupt received\n");
@@ -668,7 +667,7 @@ static irqreturn_t rockchip_pcie_client_irq_handler(int irq, void *arg)
if (reg & PCIE_CLIENT_INT_PHY)
dev_dbg(dev, "phy interrupt received\n");
- rockchip_pcie_write(rockchip, reg & (PCIE_CLIENT_INT_LEGACY_DONE |
+ rockchip_writel(rockchip, reg & (PCIE_CLIENT_INT_LEGACY_DONE |
PCIE_CLIENT_INT_MSG | PCIE_CLIENT_INT_HOT_RST |
PCIE_CLIENT_INT_DPA | PCIE_CLIENT_INT_FATAL_ERR |
PCIE_CLIENT_INT_NFATAL_ERR |
@@ -690,7 +689,7 @@ static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc)
chained_irq_enter(chip, desc);
- reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
+ reg = rockchip_readl(rockchip, PCIE_CLIENT_INT_STATUS);
reg = (reg & PCIE_CLIENT_INTR_MASK) >> PCIE_CLIENT_INTR_SHIFT;
while (reg) {
@@ -914,9 +913,9 @@ err_out:
static void rockchip_pcie_enable_interrupts(struct rockchip_pcie *rockchip)
{
- rockchip_pcie_write(rockchip, (PCIE_CLIENT_INT_CLI << 16) &
+ rockchip_writel(rockchip, (PCIE_CLIENT_INT_CLI << 16) &
(~PCIE_CLIENT_INT_CLI), PCIE_CLIENT_INT_MASK);
- rockchip_pcie_write(rockchip, (u32)(~PCIE_CORE_INT),
+ rockchip_writel(rockchip, (u32)(~PCIE_CORE_INT),
PCIE_CORE_INT_MASK);
rockchip_pcie_enable_bw_int(rockchip);
@@ -986,13 +985,13 @@ static int rockchip_pcie_prog_ob_atu(struct rockchip_pcie *rockchip,
ob_addr_1 = upper_addr;
ob_desc_0 = (1 << 23 | type);
- rockchip_pcie_write(rockchip, ob_addr_0,
+ rockchip_writel(rockchip, ob_addr_0,
PCIE_CORE_OB_REGION_ADDR0 + aw_offset);
- rockchip_pcie_write(rockchip, ob_addr_1,
+ rockchip_writel(rockchip, ob_addr_1,
PCIE_CORE_OB_REGION_ADDR1 + aw_offset);
- rockchip_pcie_write(rockchip, ob_desc_0,
+ rockchip_writel(rockchip, ob_desc_0,
PCIE_CORE_OB_REGION_DESC0 + aw_offset);
- rockchip_pcie_write(rockchip, 0,
+ rockchip_writel(rockchip, 0,
PCIE_CORE_OB_REGION_DESC1 + aw_offset);
return 0;
@@ -1019,8 +1018,8 @@ static int rockchip_pcie_prog_ib_atu(struct rockchip_pcie *rockchip,
ib_addr_0 |= (lower_addr << 8) & PCIE_CORE_IB_REGION_ADDR0_LO_ADDR;
ib_addr_1 = upper_addr;
- rockchip_pcie_write(rockchip, ib_addr_0, PCIE_RP_IB_ADDR0 + aw_offset);
- rockchip_pcie_write(rockchip, ib_addr_1, PCIE_RP_IB_ADDR1 + aw_offset);
+ rockchip_writel(rockchip, ib_addr_0, PCIE_RP_IB_ADDR0 + aw_offset);
+ rockchip_writel(rockchip, ib_addr_1, PCIE_RP_IB_ADDR1 + aw_offset);
return 0;
}
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH 2/3] PCI: rockchip: Swap order of rockchip_writel() reg/val arguments
2016-10-07 16:27 [PATCH 1/3] PCI: rockchip: Rename accessors Bjorn Helgaas
@ 2016-10-07 16:27 ` Bjorn Helgaas
2016-10-08 2:52 ` Shawn Lin
2016-10-07 16:27 ` [PATCH 3/3] PCI: rockchip: Remove unused platform data Bjorn Helgaas
2016-10-08 2:51 ` Shawn Lin
2 siblings, 1 reply; 9+ messages in thread
From: Bjorn Helgaas @ 2016-10-07 16:27 UTC (permalink / raw)
To: Shawn Lin, Wenrui Li, Heiko Stuebner; +Cc: linux-rockchip, linux-pci
Swap order of rockchip_writel() arguments to match the "dev, pos, val"
order used by pci_write_config_word() and other drivers. No functional
change intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
drivers/pci/host/pcie-rockchip.c | 95 ++++++++++++++++++--------------------
1 file changed, 44 insertions(+), 51 deletions(-)
diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index 0ef2f9f..0a89d02 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -209,8 +209,7 @@ static u32 rockchip_readl(struct rockchip_pcie *rockchip, u32 reg)
return readl(rockchip->apb_base + reg);
}
-static void rockchip_writel(struct rockchip_pcie *rockchip, u32 val,
- u32 reg)
+static void rockchip_writel(struct rockchip_pcie *rockchip, u32 reg, u32 val)
{
writel(val, rockchip->apb_base + reg);
}
@@ -221,7 +220,7 @@ static void rockchip_pcie_enable_bw_int(struct rockchip_pcie *rockchip)
status = rockchip_readl(rockchip, PCIE_RC_CONFIG_LCS);
status |= (PCIE_RC_CONFIG_LCS_LBMIE | PCIE_RC_CONFIG_LCS_LABIE);
- rockchip_writel(rockchip, status, PCIE_RC_CONFIG_LCS);
+ rockchip_writel(rockchip, PCIE_RC_CONFIG_LCS, status);
}
static void rockchip_pcie_clr_bw_int(struct rockchip_pcie *rockchip)
@@ -230,7 +229,7 @@ static void rockchip_pcie_clr_bw_int(struct rockchip_pcie *rockchip)
status = rockchip_readl(rockchip, PCIE_RC_CONFIG_LCS);
status |= (PCIE_RC_CONFIG_LCS_LBMS | PCIE_RC_CONFIG_LCS_LAMS);
- rockchip_writel(rockchip, status, PCIE_RC_CONFIG_LCS);
+ rockchip_writel(rockchip, PCIE_RC_CONFIG_LCS, status);
}
static void rockchip_pcie_update_txcredit_mui(struct rockchip_pcie *rockchip)
@@ -241,7 +240,7 @@ static void rockchip_pcie_update_txcredit_mui(struct rockchip_pcie *rockchip)
val = rockchip_readl(rockchip, PCIE_CORE_TXCREDIT_CFG1);
val &= ~PCIE_CORE_TXCREDIT_CFG1_MUI_MASK;
val |= PCIE_CORE_TXCREDIT_CFG1_MUI_ENCODE(24000); /* ns */
- rockchip_writel(rockchip, val, PCIE_CORE_TXCREDIT_CFG1);
+ rockchip_writel(rockchip, PCIE_CORE_TXCREDIT_CFG1, val);
}
static int rockchip_pcie_valid_device(struct rockchip_pcie *rockchip,
@@ -438,14 +437,13 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
return err;
}
- rockchip_writel(rockchip,
+ rockchip_writel(rockchip, PCIE_CLIENT_CONFIG,
PCIE_CLIENT_CONF_ENABLE |
PCIE_CLIENT_LINK_TRAIN_ENABLE |
PCIE_CLIENT_ARI_ENABLE |
PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes) |
PCIE_CLIENT_MODE_RC |
- PCIE_CLIENT_GEN_SEL_2,
- PCIE_CLIENT_CONFIG);
+ PCIE_CLIENT_GEN_SEL_2);
err = phy_power_on(rockchip->phy);
if (err) {
@@ -488,17 +486,17 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
* bug we need to work around.
*/
status = rockchip_readl(rockchip, PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
- rockchip_writel(rockchip, status, PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
+ rockchip_writel(rockchip, PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2, status);
/* Fix the transmitted FTS count desired to exit from L0s. */
status = rockchip_readl(rockchip, PCIE_CORE_CTRL_PLC1);
status = (status & PCIE_CORE_CTRL_PLC1_FTS_MASK) |
(PCIE_CORE_CTRL_PLC1_FTS_CNT << PCIE_CORE_CTRL_PLC1_FTS_SHIFT);
- rockchip_writel(rockchip, status, PCIE_CORE_CTRL_PLC1);
+ rockchip_writel(rockchip, PCIE_CORE_CTRL_PLC1, status);
/* Enable Gen1 training */
- rockchip_writel(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
- PCIE_CLIENT_CONFIG);
+ rockchip_writel(rockchip, PCIE_CLIENT_CONFIG,
+ PCIE_CLIENT_LINK_TRAIN_ENABLE);
gpiod_set_value(rockchip->ep_gpio, 1);
@@ -527,7 +525,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
*/
status = rockchip_readl(rockchip, PCIE_RC_CONFIG_LCS);
status |= PCIE_RC_CONFIG_LCS_RETRAIN_LINK;
- rockchip_writel(rockchip, status, PCIE_RC_CONFIG_LCS);
+ rockchip_writel(rockchip, PCIE_RC_CONFIG_LCS, status);
timeout = jiffies + msecs_to_jiffies(500);
for (;;) {
@@ -552,20 +550,17 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
PCIE_CORE_PL_CONF_LANE_MASK);
dev_dbg(dev, "current link width is x%d\n", status);
- rockchip_writel(rockchip, ROCKCHIP_VENDOR_ID,
- PCIE_RC_CONFIG_VENDOR);
- rockchip_writel(rockchip,
- PCI_CLASS_BRIDGE_PCI << PCIE_RC_CONFIG_SCC_SHIFT,
- PCIE_RC_CONFIG_RID_CCR);
- rockchip_writel(rockchip, 0x0, PCIE_RC_BAR_CONF);
-
- rockchip_writel(rockchip,
- (RC_REGION_0_ADDR_TRANS_L + RC_REGION_0_PASS_BITS),
- PCIE_CORE_OB_REGION_ADDR0);
- rockchip_writel(rockchip, RC_REGION_0_ADDR_TRANS_H,
- PCIE_CORE_OB_REGION_ADDR1);
- rockchip_writel(rockchip, 0x0080000a, PCIE_CORE_OB_REGION_DESC0);
- rockchip_writel(rockchip, 0x0, PCIE_CORE_OB_REGION_DESC1);
+ rockchip_writel(rockchip, PCIE_RC_CONFIG_VENDOR, ROCKCHIP_VENDOR_ID);
+ rockchip_writel(rockchip, PCIE_RC_CONFIG_RID_CCR,
+ PCI_CLASS_BRIDGE_PCI << PCIE_RC_CONFIG_SCC_SHIFT);
+ rockchip_writel(rockchip, PCIE_RC_BAR_CONF, 0);
+
+ rockchip_writel(rockchip, PCIE_CORE_OB_REGION_ADDR0,
+ RC_REGION_0_ADDR_TRANS_L + RC_REGION_0_PASS_BITS);
+ rockchip_writel(rockchip, PCIE_CORE_OB_REGION_ADDR1,
+ RC_REGION_0_ADDR_TRANS_H);
+ rockchip_writel(rockchip, PCIE_CORE_OB_REGION_DESC0, 0x0080000a);
+ rockchip_writel(rockchip, PCIE_CORE_OB_REGION_DESC1, 0);
return 0;
}
@@ -623,15 +618,15 @@ static irqreturn_t rockchip_pcie_subsys_irq_handler(int irq, void *arg)
if (sub_reg & PCIE_CORE_INT_MMVC)
dev_dbg(dev, "MSI mask register changes\n");
- rockchip_writel(rockchip, sub_reg, PCIE_CORE_INT_STATUS);
+ rockchip_writel(rockchip, PCIE_CORE_INT_STATUS, sub_reg);
} else if (reg & PCIE_CLIENT_INT_PHY) {
dev_dbg(dev, "phy link changes\n");
rockchip_pcie_update_txcredit_mui(rockchip);
rockchip_pcie_clr_bw_int(rockchip);
}
- rockchip_writel(rockchip, reg & PCIE_CLIENT_INT_LOCAL,
- PCIE_CLIENT_INT_STATUS);
+ rockchip_writel(rockchip, PCIE_CLIENT_INT_STATUS,
+ reg & PCIE_CLIENT_INT_LOCAL);
return IRQ_HANDLED;
}
@@ -667,13 +662,13 @@ static irqreturn_t rockchip_pcie_client_irq_handler(int irq, void *arg)
if (reg & PCIE_CLIENT_INT_PHY)
dev_dbg(dev, "phy interrupt received\n");
- rockchip_writel(rockchip, reg & (PCIE_CLIENT_INT_LEGACY_DONE |
- PCIE_CLIENT_INT_MSG | PCIE_CLIENT_INT_HOT_RST |
- PCIE_CLIENT_INT_DPA | PCIE_CLIENT_INT_FATAL_ERR |
- PCIE_CLIENT_INT_NFATAL_ERR |
- PCIE_CLIENT_INT_CORR_ERR |
- PCIE_CLIENT_INT_PHY),
- PCIE_CLIENT_INT_STATUS);
+ rockchip_writel(rockchip, PCIE_CLIENT_INT_STATUS,
+ reg & (PCIE_CLIENT_INT_LEGACY_DONE |
+ PCIE_CLIENT_INT_MSG | PCIE_CLIENT_INT_HOT_RST |
+ PCIE_CLIENT_INT_DPA | PCIE_CLIENT_INT_FATAL_ERR |
+ PCIE_CLIENT_INT_NFATAL_ERR |
+ PCIE_CLIENT_INT_CORR_ERR |
+ PCIE_CLIENT_INT_PHY));
return IRQ_HANDLED;
}
@@ -913,10 +908,9 @@ err_out:
static void rockchip_pcie_enable_interrupts(struct rockchip_pcie *rockchip)
{
- rockchip_writel(rockchip, (PCIE_CLIENT_INT_CLI << 16) &
- (~PCIE_CLIENT_INT_CLI), PCIE_CLIENT_INT_MASK);
- rockchip_writel(rockchip, (u32)(~PCIE_CORE_INT),
- PCIE_CORE_INT_MASK);
+ rockchip_writel(rockchip, PCIE_CLIENT_INT_MASK,
+ (PCIE_CLIENT_INT_CLI << 16) & (~PCIE_CLIENT_INT_CLI));
+ rockchip_writel(rockchip, PCIE_CORE_INT_MASK, (u32)(~PCIE_CORE_INT));
rockchip_pcie_enable_bw_int(rockchip);
}
@@ -985,14 +979,13 @@ static int rockchip_pcie_prog_ob_atu(struct rockchip_pcie *rockchip,
ob_addr_1 = upper_addr;
ob_desc_0 = (1 << 23 | type);
- rockchip_writel(rockchip, ob_addr_0,
- PCIE_CORE_OB_REGION_ADDR0 + aw_offset);
- rockchip_writel(rockchip, ob_addr_1,
- PCIE_CORE_OB_REGION_ADDR1 + aw_offset);
- rockchip_writel(rockchip, ob_desc_0,
- PCIE_CORE_OB_REGION_DESC0 + aw_offset);
- rockchip_writel(rockchip, 0,
- PCIE_CORE_OB_REGION_DESC1 + aw_offset);
+ rockchip_writel(rockchip, PCIE_CORE_OB_REGION_ADDR0 + aw_offset,
+ ob_addr_0);
+ rockchip_writel(rockchip, PCIE_CORE_OB_REGION_ADDR1 + aw_offset,
+ ob_addr_1);
+ rockchip_writel(rockchip, PCIE_CORE_OB_REGION_DESC0 + aw_offset,
+ ob_desc_0);
+ rockchip_writel(rockchip, PCIE_CORE_OB_REGION_DESC1 + aw_offset, 0);
return 0;
}
@@ -1018,8 +1011,8 @@ static int rockchip_pcie_prog_ib_atu(struct rockchip_pcie *rockchip,
ib_addr_0 |= (lower_addr << 8) & PCIE_CORE_IB_REGION_ADDR0_LO_ADDR;
ib_addr_1 = upper_addr;
- rockchip_writel(rockchip, ib_addr_0, PCIE_RP_IB_ADDR0 + aw_offset);
- rockchip_writel(rockchip, ib_addr_1, PCIE_RP_IB_ADDR1 + aw_offset);
+ rockchip_writel(rockchip, PCIE_RP_IB_ADDR0 + aw_offset, ib_addr_0);
+ rockchip_writel(rockchip, PCIE_RP_IB_ADDR1 + aw_offset, ib_addr_1);
return 0;
}
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH 2/3] PCI: rockchip: Swap order of rockchip_writel() reg/val arguments
2016-10-07 16:27 ` [PATCH 2/3] PCI: rockchip: Swap order of rockchip_writel() reg/val arguments Bjorn Helgaas
@ 2016-10-08 2:52 ` Shawn Lin
0 siblings, 0 replies; 9+ messages in thread
From: Shawn Lin @ 2016-10-08 2:52 UTC (permalink / raw)
To: Bjorn Helgaas, Shawn Lin, Wenrui Li, Heiko Stuebner
Cc: shawn.lin, linux-rockchip, linux-pci
在 2016/10/8 0:27, Bjorn Helgaas 写道:
> Swap order of rockchip_writel() arguments to match the "dev, pos, val"
> order used by pci_write_config_word() and other drivers. No functional
> change intended.
>
okay, i saw the pci-tree cleanup for all the host drivers there, so
Acked-by: Shawn Lin <shawn.lin@rock-chips.com>
> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
> ---
> drivers/pci/host/pcie-rockchip.c | 95 ++++++++++++++++++--------------------
> 1 file changed, 44 insertions(+), 51 deletions(-)
>
> diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
> index 0ef2f9f..0a89d02 100644
> --- a/drivers/pci/host/pcie-rockchip.c
> +++ b/drivers/pci/host/pcie-rockchip.c
> @@ -209,8 +209,7 @@ static u32 rockchip_readl(struct rockchip_pcie *rockchip, u32 reg)
> return readl(rockchip->apb_base + reg);
> }
>
> -static void rockchip_writel(struct rockchip_pcie *rockchip, u32 val,
> - u32 reg)
> +static void rockchip_writel(struct rockchip_pcie *rockchip, u32 reg, u32 val)
> {
> writel(val, rockchip->apb_base + reg);
> }
> @@ -221,7 +220,7 @@ static void rockchip_pcie_enable_bw_int(struct rockchip_pcie *rockchip)
>
> status = rockchip_readl(rockchip, PCIE_RC_CONFIG_LCS);
> status |= (PCIE_RC_CONFIG_LCS_LBMIE | PCIE_RC_CONFIG_LCS_LABIE);
> - rockchip_writel(rockchip, status, PCIE_RC_CONFIG_LCS);
> + rockchip_writel(rockchip, PCIE_RC_CONFIG_LCS, status);
> }
>
> static void rockchip_pcie_clr_bw_int(struct rockchip_pcie *rockchip)
> @@ -230,7 +229,7 @@ static void rockchip_pcie_clr_bw_int(struct rockchip_pcie *rockchip)
>
> status = rockchip_readl(rockchip, PCIE_RC_CONFIG_LCS);
> status |= (PCIE_RC_CONFIG_LCS_LBMS | PCIE_RC_CONFIG_LCS_LAMS);
> - rockchip_writel(rockchip, status, PCIE_RC_CONFIG_LCS);
> + rockchip_writel(rockchip, PCIE_RC_CONFIG_LCS, status);
> }
>
> static void rockchip_pcie_update_txcredit_mui(struct rockchip_pcie *rockchip)
> @@ -241,7 +240,7 @@ static void rockchip_pcie_update_txcredit_mui(struct rockchip_pcie *rockchip)
> val = rockchip_readl(rockchip, PCIE_CORE_TXCREDIT_CFG1);
> val &= ~PCIE_CORE_TXCREDIT_CFG1_MUI_MASK;
> val |= PCIE_CORE_TXCREDIT_CFG1_MUI_ENCODE(24000); /* ns */
> - rockchip_writel(rockchip, val, PCIE_CORE_TXCREDIT_CFG1);
> + rockchip_writel(rockchip, PCIE_CORE_TXCREDIT_CFG1, val);
> }
>
> static int rockchip_pcie_valid_device(struct rockchip_pcie *rockchip,
> @@ -438,14 +437,13 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
> return err;
> }
>
> - rockchip_writel(rockchip,
> + rockchip_writel(rockchip, PCIE_CLIENT_CONFIG,
> PCIE_CLIENT_CONF_ENABLE |
> PCIE_CLIENT_LINK_TRAIN_ENABLE |
> PCIE_CLIENT_ARI_ENABLE |
> PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes) |
> PCIE_CLIENT_MODE_RC |
> - PCIE_CLIENT_GEN_SEL_2,
> - PCIE_CLIENT_CONFIG);
> + PCIE_CLIENT_GEN_SEL_2);
>
> err = phy_power_on(rockchip->phy);
> if (err) {
> @@ -488,17 +486,17 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
> * bug we need to work around.
> */
> status = rockchip_readl(rockchip, PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
> - rockchip_writel(rockchip, status, PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
> + rockchip_writel(rockchip, PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2, status);
>
> /* Fix the transmitted FTS count desired to exit from L0s. */
> status = rockchip_readl(rockchip, PCIE_CORE_CTRL_PLC1);
> status = (status & PCIE_CORE_CTRL_PLC1_FTS_MASK) |
> (PCIE_CORE_CTRL_PLC1_FTS_CNT << PCIE_CORE_CTRL_PLC1_FTS_SHIFT);
> - rockchip_writel(rockchip, status, PCIE_CORE_CTRL_PLC1);
> + rockchip_writel(rockchip, PCIE_CORE_CTRL_PLC1, status);
>
> /* Enable Gen1 training */
> - rockchip_writel(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
> - PCIE_CLIENT_CONFIG);
> + rockchip_writel(rockchip, PCIE_CLIENT_CONFIG,
> + PCIE_CLIENT_LINK_TRAIN_ENABLE);
>
> gpiod_set_value(rockchip->ep_gpio, 1);
>
> @@ -527,7 +525,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
> */
> status = rockchip_readl(rockchip, PCIE_RC_CONFIG_LCS);
> status |= PCIE_RC_CONFIG_LCS_RETRAIN_LINK;
> - rockchip_writel(rockchip, status, PCIE_RC_CONFIG_LCS);
> + rockchip_writel(rockchip, PCIE_RC_CONFIG_LCS, status);
>
> timeout = jiffies + msecs_to_jiffies(500);
> for (;;) {
> @@ -552,20 +550,17 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
> PCIE_CORE_PL_CONF_LANE_MASK);
> dev_dbg(dev, "current link width is x%d\n", status);
>
> - rockchip_writel(rockchip, ROCKCHIP_VENDOR_ID,
> - PCIE_RC_CONFIG_VENDOR);
> - rockchip_writel(rockchip,
> - PCI_CLASS_BRIDGE_PCI << PCIE_RC_CONFIG_SCC_SHIFT,
> - PCIE_RC_CONFIG_RID_CCR);
> - rockchip_writel(rockchip, 0x0, PCIE_RC_BAR_CONF);
> -
> - rockchip_writel(rockchip,
> - (RC_REGION_0_ADDR_TRANS_L + RC_REGION_0_PASS_BITS),
> - PCIE_CORE_OB_REGION_ADDR0);
> - rockchip_writel(rockchip, RC_REGION_0_ADDR_TRANS_H,
> - PCIE_CORE_OB_REGION_ADDR1);
> - rockchip_writel(rockchip, 0x0080000a, PCIE_CORE_OB_REGION_DESC0);
> - rockchip_writel(rockchip, 0x0, PCIE_CORE_OB_REGION_DESC1);
> + rockchip_writel(rockchip, PCIE_RC_CONFIG_VENDOR, ROCKCHIP_VENDOR_ID);
> + rockchip_writel(rockchip, PCIE_RC_CONFIG_RID_CCR,
> + PCI_CLASS_BRIDGE_PCI << PCIE_RC_CONFIG_SCC_SHIFT);
> + rockchip_writel(rockchip, PCIE_RC_BAR_CONF, 0);
> +
> + rockchip_writel(rockchip, PCIE_CORE_OB_REGION_ADDR0,
> + RC_REGION_0_ADDR_TRANS_L + RC_REGION_0_PASS_BITS);
> + rockchip_writel(rockchip, PCIE_CORE_OB_REGION_ADDR1,
> + RC_REGION_0_ADDR_TRANS_H);
> + rockchip_writel(rockchip, PCIE_CORE_OB_REGION_DESC0, 0x0080000a);
> + rockchip_writel(rockchip, PCIE_CORE_OB_REGION_DESC1, 0);
>
> return 0;
> }
> @@ -623,15 +618,15 @@ static irqreturn_t rockchip_pcie_subsys_irq_handler(int irq, void *arg)
> if (sub_reg & PCIE_CORE_INT_MMVC)
> dev_dbg(dev, "MSI mask register changes\n");
>
> - rockchip_writel(rockchip, sub_reg, PCIE_CORE_INT_STATUS);
> + rockchip_writel(rockchip, PCIE_CORE_INT_STATUS, sub_reg);
> } else if (reg & PCIE_CLIENT_INT_PHY) {
> dev_dbg(dev, "phy link changes\n");
> rockchip_pcie_update_txcredit_mui(rockchip);
> rockchip_pcie_clr_bw_int(rockchip);
> }
>
> - rockchip_writel(rockchip, reg & PCIE_CLIENT_INT_LOCAL,
> - PCIE_CLIENT_INT_STATUS);
> + rockchip_writel(rockchip, PCIE_CLIENT_INT_STATUS,
> + reg & PCIE_CLIENT_INT_LOCAL);
>
> return IRQ_HANDLED;
> }
> @@ -667,13 +662,13 @@ static irqreturn_t rockchip_pcie_client_irq_handler(int irq, void *arg)
> if (reg & PCIE_CLIENT_INT_PHY)
> dev_dbg(dev, "phy interrupt received\n");
>
> - rockchip_writel(rockchip, reg & (PCIE_CLIENT_INT_LEGACY_DONE |
> - PCIE_CLIENT_INT_MSG | PCIE_CLIENT_INT_HOT_RST |
> - PCIE_CLIENT_INT_DPA | PCIE_CLIENT_INT_FATAL_ERR |
> - PCIE_CLIENT_INT_NFATAL_ERR |
> - PCIE_CLIENT_INT_CORR_ERR |
> - PCIE_CLIENT_INT_PHY),
> - PCIE_CLIENT_INT_STATUS);
> + rockchip_writel(rockchip, PCIE_CLIENT_INT_STATUS,
> + reg & (PCIE_CLIENT_INT_LEGACY_DONE |
> + PCIE_CLIENT_INT_MSG | PCIE_CLIENT_INT_HOT_RST |
> + PCIE_CLIENT_INT_DPA | PCIE_CLIENT_INT_FATAL_ERR |
> + PCIE_CLIENT_INT_NFATAL_ERR |
> + PCIE_CLIENT_INT_CORR_ERR |
> + PCIE_CLIENT_INT_PHY));
>
> return IRQ_HANDLED;
> }
> @@ -913,10 +908,9 @@ err_out:
>
> static void rockchip_pcie_enable_interrupts(struct rockchip_pcie *rockchip)
> {
> - rockchip_writel(rockchip, (PCIE_CLIENT_INT_CLI << 16) &
> - (~PCIE_CLIENT_INT_CLI), PCIE_CLIENT_INT_MASK);
> - rockchip_writel(rockchip, (u32)(~PCIE_CORE_INT),
> - PCIE_CORE_INT_MASK);
> + rockchip_writel(rockchip, PCIE_CLIENT_INT_MASK,
> + (PCIE_CLIENT_INT_CLI << 16) & (~PCIE_CLIENT_INT_CLI));
> + rockchip_writel(rockchip, PCIE_CORE_INT_MASK, (u32)(~PCIE_CORE_INT));
>
> rockchip_pcie_enable_bw_int(rockchip);
> }
> @@ -985,14 +979,13 @@ static int rockchip_pcie_prog_ob_atu(struct rockchip_pcie *rockchip,
> ob_addr_1 = upper_addr;
> ob_desc_0 = (1 << 23 | type);
>
> - rockchip_writel(rockchip, ob_addr_0,
> - PCIE_CORE_OB_REGION_ADDR0 + aw_offset);
> - rockchip_writel(rockchip, ob_addr_1,
> - PCIE_CORE_OB_REGION_ADDR1 + aw_offset);
> - rockchip_writel(rockchip, ob_desc_0,
> - PCIE_CORE_OB_REGION_DESC0 + aw_offset);
> - rockchip_writel(rockchip, 0,
> - PCIE_CORE_OB_REGION_DESC1 + aw_offset);
> + rockchip_writel(rockchip, PCIE_CORE_OB_REGION_ADDR0 + aw_offset,
> + ob_addr_0);
> + rockchip_writel(rockchip, PCIE_CORE_OB_REGION_ADDR1 + aw_offset,
> + ob_addr_1);
> + rockchip_writel(rockchip, PCIE_CORE_OB_REGION_DESC0 + aw_offset,
> + ob_desc_0);
> + rockchip_writel(rockchip, PCIE_CORE_OB_REGION_DESC1 + aw_offset, 0);
>
> return 0;
> }
> @@ -1018,8 +1011,8 @@ static int rockchip_pcie_prog_ib_atu(struct rockchip_pcie *rockchip,
> ib_addr_0 |= (lower_addr << 8) & PCIE_CORE_IB_REGION_ADDR0_LO_ADDR;
> ib_addr_1 = upper_addr;
>
> - rockchip_writel(rockchip, ib_addr_0, PCIE_RP_IB_ADDR0 + aw_offset);
> - rockchip_writel(rockchip, ib_addr_1, PCIE_RP_IB_ADDR1 + aw_offset);
> + rockchip_writel(rockchip, PCIE_RP_IB_ADDR0 + aw_offset, ib_addr_0);
> + rockchip_writel(rockchip, PCIE_RP_IB_ADDR1 + aw_offset, ib_addr_1);
>
> return 0;
> }
>
>
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip
>
--
Best Regards
Shawn Lin
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH 2/3] PCI: rockchip: Swap order of rockchip_writel() reg/val arguments
@ 2016-10-08 2:52 ` Shawn Lin
0 siblings, 0 replies; 9+ messages in thread
From: Shawn Lin @ 2016-10-08 2:52 UTC (permalink / raw)
To: Bjorn Helgaas, Wenrui Li, Heiko Stuebner
Cc: shawn.lin, linux-rockchip, linux-pci
在 2016/10/8 0:27, Bjorn Helgaas 写道:
> Swap order of rockchip_writel() arguments to match the "dev, pos, val"
> order used by pci_write_config_word() and other drivers. No functional
> change intended.
>
okay, i saw the pci-tree cleanup for all the host drivers there, so
Acked-by: Shawn Lin <shawn.lin@rock-chips.com>
> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
> ---
> drivers/pci/host/pcie-rockchip.c | 95 ++++++++++++++++++--------------------
> 1 file changed, 44 insertions(+), 51 deletions(-)
>
> diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
> index 0ef2f9f..0a89d02 100644
> --- a/drivers/pci/host/pcie-rockchip.c
> +++ b/drivers/pci/host/pcie-rockchip.c
> @@ -209,8 +209,7 @@ static u32 rockchip_readl(struct rockchip_pcie *rockchip, u32 reg)
> return readl(rockchip->apb_base + reg);
> }
>
> -static void rockchip_writel(struct rockchip_pcie *rockchip, u32 val,
> - u32 reg)
> +static void rockchip_writel(struct rockchip_pcie *rockchip, u32 reg, u32 val)
> {
> writel(val, rockchip->apb_base + reg);
> }
> @@ -221,7 +220,7 @@ static void rockchip_pcie_enable_bw_int(struct rockchip_pcie *rockchip)
>
> status = rockchip_readl(rockchip, PCIE_RC_CONFIG_LCS);
> status |= (PCIE_RC_CONFIG_LCS_LBMIE | PCIE_RC_CONFIG_LCS_LABIE);
> - rockchip_writel(rockchip, status, PCIE_RC_CONFIG_LCS);
> + rockchip_writel(rockchip, PCIE_RC_CONFIG_LCS, status);
> }
>
> static void rockchip_pcie_clr_bw_int(struct rockchip_pcie *rockchip)
> @@ -230,7 +229,7 @@ static void rockchip_pcie_clr_bw_int(struct rockchip_pcie *rockchip)
>
> status = rockchip_readl(rockchip, PCIE_RC_CONFIG_LCS);
> status |= (PCIE_RC_CONFIG_LCS_LBMS | PCIE_RC_CONFIG_LCS_LAMS);
> - rockchip_writel(rockchip, status, PCIE_RC_CONFIG_LCS);
> + rockchip_writel(rockchip, PCIE_RC_CONFIG_LCS, status);
> }
>
> static void rockchip_pcie_update_txcredit_mui(struct rockchip_pcie *rockchip)
> @@ -241,7 +240,7 @@ static void rockchip_pcie_update_txcredit_mui(struct rockchip_pcie *rockchip)
> val = rockchip_readl(rockchip, PCIE_CORE_TXCREDIT_CFG1);
> val &= ~PCIE_CORE_TXCREDIT_CFG1_MUI_MASK;
> val |= PCIE_CORE_TXCREDIT_CFG1_MUI_ENCODE(24000); /* ns */
> - rockchip_writel(rockchip, val, PCIE_CORE_TXCREDIT_CFG1);
> + rockchip_writel(rockchip, PCIE_CORE_TXCREDIT_CFG1, val);
> }
>
> static int rockchip_pcie_valid_device(struct rockchip_pcie *rockchip,
> @@ -438,14 +437,13 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
> return err;
> }
>
> - rockchip_writel(rockchip,
> + rockchip_writel(rockchip, PCIE_CLIENT_CONFIG,
> PCIE_CLIENT_CONF_ENABLE |
> PCIE_CLIENT_LINK_TRAIN_ENABLE |
> PCIE_CLIENT_ARI_ENABLE |
> PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes) |
> PCIE_CLIENT_MODE_RC |
> - PCIE_CLIENT_GEN_SEL_2,
> - PCIE_CLIENT_CONFIG);
> + PCIE_CLIENT_GEN_SEL_2);
>
> err = phy_power_on(rockchip->phy);
> if (err) {
> @@ -488,17 +486,17 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
> * bug we need to work around.
> */
> status = rockchip_readl(rockchip, PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
> - rockchip_writel(rockchip, status, PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
> + rockchip_writel(rockchip, PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2, status);
>
> /* Fix the transmitted FTS count desired to exit from L0s. */
> status = rockchip_readl(rockchip, PCIE_CORE_CTRL_PLC1);
> status = (status & PCIE_CORE_CTRL_PLC1_FTS_MASK) |
> (PCIE_CORE_CTRL_PLC1_FTS_CNT << PCIE_CORE_CTRL_PLC1_FTS_SHIFT);
> - rockchip_writel(rockchip, status, PCIE_CORE_CTRL_PLC1);
> + rockchip_writel(rockchip, PCIE_CORE_CTRL_PLC1, status);
>
> /* Enable Gen1 training */
> - rockchip_writel(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
> - PCIE_CLIENT_CONFIG);
> + rockchip_writel(rockchip, PCIE_CLIENT_CONFIG,
> + PCIE_CLIENT_LINK_TRAIN_ENABLE);
>
> gpiod_set_value(rockchip->ep_gpio, 1);
>
> @@ -527,7 +525,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
> */
> status = rockchip_readl(rockchip, PCIE_RC_CONFIG_LCS);
> status |= PCIE_RC_CONFIG_LCS_RETRAIN_LINK;
> - rockchip_writel(rockchip, status, PCIE_RC_CONFIG_LCS);
> + rockchip_writel(rockchip, PCIE_RC_CONFIG_LCS, status);
>
> timeout = jiffies + msecs_to_jiffies(500);
> for (;;) {
> @@ -552,20 +550,17 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
> PCIE_CORE_PL_CONF_LANE_MASK);
> dev_dbg(dev, "current link width is x%d\n", status);
>
> - rockchip_writel(rockchip, ROCKCHIP_VENDOR_ID,
> - PCIE_RC_CONFIG_VENDOR);
> - rockchip_writel(rockchip,
> - PCI_CLASS_BRIDGE_PCI << PCIE_RC_CONFIG_SCC_SHIFT,
> - PCIE_RC_CONFIG_RID_CCR);
> - rockchip_writel(rockchip, 0x0, PCIE_RC_BAR_CONF);
> -
> - rockchip_writel(rockchip,
> - (RC_REGION_0_ADDR_TRANS_L + RC_REGION_0_PASS_BITS),
> - PCIE_CORE_OB_REGION_ADDR0);
> - rockchip_writel(rockchip, RC_REGION_0_ADDR_TRANS_H,
> - PCIE_CORE_OB_REGION_ADDR1);
> - rockchip_writel(rockchip, 0x0080000a, PCIE_CORE_OB_REGION_DESC0);
> - rockchip_writel(rockchip, 0x0, PCIE_CORE_OB_REGION_DESC1);
> + rockchip_writel(rockchip, PCIE_RC_CONFIG_VENDOR, ROCKCHIP_VENDOR_ID);
> + rockchip_writel(rockchip, PCIE_RC_CONFIG_RID_CCR,
> + PCI_CLASS_BRIDGE_PCI << PCIE_RC_CONFIG_SCC_SHIFT);
> + rockchip_writel(rockchip, PCIE_RC_BAR_CONF, 0);
> +
> + rockchip_writel(rockchip, PCIE_CORE_OB_REGION_ADDR0,
> + RC_REGION_0_ADDR_TRANS_L + RC_REGION_0_PASS_BITS);
> + rockchip_writel(rockchip, PCIE_CORE_OB_REGION_ADDR1,
> + RC_REGION_0_ADDR_TRANS_H);
> + rockchip_writel(rockchip, PCIE_CORE_OB_REGION_DESC0, 0x0080000a);
> + rockchip_writel(rockchip, PCIE_CORE_OB_REGION_DESC1, 0);
>
> return 0;
> }
> @@ -623,15 +618,15 @@ static irqreturn_t rockchip_pcie_subsys_irq_handler(int irq, void *arg)
> if (sub_reg & PCIE_CORE_INT_MMVC)
> dev_dbg(dev, "MSI mask register changes\n");
>
> - rockchip_writel(rockchip, sub_reg, PCIE_CORE_INT_STATUS);
> + rockchip_writel(rockchip, PCIE_CORE_INT_STATUS, sub_reg);
> } else if (reg & PCIE_CLIENT_INT_PHY) {
> dev_dbg(dev, "phy link changes\n");
> rockchip_pcie_update_txcredit_mui(rockchip);
> rockchip_pcie_clr_bw_int(rockchip);
> }
>
> - rockchip_writel(rockchip, reg & PCIE_CLIENT_INT_LOCAL,
> - PCIE_CLIENT_INT_STATUS);
> + rockchip_writel(rockchip, PCIE_CLIENT_INT_STATUS,
> + reg & PCIE_CLIENT_INT_LOCAL);
>
> return IRQ_HANDLED;
> }
> @@ -667,13 +662,13 @@ static irqreturn_t rockchip_pcie_client_irq_handler(int irq, void *arg)
> if (reg & PCIE_CLIENT_INT_PHY)
> dev_dbg(dev, "phy interrupt received\n");
>
> - rockchip_writel(rockchip, reg & (PCIE_CLIENT_INT_LEGACY_DONE |
> - PCIE_CLIENT_INT_MSG | PCIE_CLIENT_INT_HOT_RST |
> - PCIE_CLIENT_INT_DPA | PCIE_CLIENT_INT_FATAL_ERR |
> - PCIE_CLIENT_INT_NFATAL_ERR |
> - PCIE_CLIENT_INT_CORR_ERR |
> - PCIE_CLIENT_INT_PHY),
> - PCIE_CLIENT_INT_STATUS);
> + rockchip_writel(rockchip, PCIE_CLIENT_INT_STATUS,
> + reg & (PCIE_CLIENT_INT_LEGACY_DONE |
> + PCIE_CLIENT_INT_MSG | PCIE_CLIENT_INT_HOT_RST |
> + PCIE_CLIENT_INT_DPA | PCIE_CLIENT_INT_FATAL_ERR |
> + PCIE_CLIENT_INT_NFATAL_ERR |
> + PCIE_CLIENT_INT_CORR_ERR |
> + PCIE_CLIENT_INT_PHY));
>
> return IRQ_HANDLED;
> }
> @@ -913,10 +908,9 @@ err_out:
>
> static void rockchip_pcie_enable_interrupts(struct rockchip_pcie *rockchip)
> {
> - rockchip_writel(rockchip, (PCIE_CLIENT_INT_CLI << 16) &
> - (~PCIE_CLIENT_INT_CLI), PCIE_CLIENT_INT_MASK);
> - rockchip_writel(rockchip, (u32)(~PCIE_CORE_INT),
> - PCIE_CORE_INT_MASK);
> + rockchip_writel(rockchip, PCIE_CLIENT_INT_MASK,
> + (PCIE_CLIENT_INT_CLI << 16) & (~PCIE_CLIENT_INT_CLI));
> + rockchip_writel(rockchip, PCIE_CORE_INT_MASK, (u32)(~PCIE_CORE_INT));
>
> rockchip_pcie_enable_bw_int(rockchip);
> }
> @@ -985,14 +979,13 @@ static int rockchip_pcie_prog_ob_atu(struct rockchip_pcie *rockchip,
> ob_addr_1 = upper_addr;
> ob_desc_0 = (1 << 23 | type);
>
> - rockchip_writel(rockchip, ob_addr_0,
> - PCIE_CORE_OB_REGION_ADDR0 + aw_offset);
> - rockchip_writel(rockchip, ob_addr_1,
> - PCIE_CORE_OB_REGION_ADDR1 + aw_offset);
> - rockchip_writel(rockchip, ob_desc_0,
> - PCIE_CORE_OB_REGION_DESC0 + aw_offset);
> - rockchip_writel(rockchip, 0,
> - PCIE_CORE_OB_REGION_DESC1 + aw_offset);
> + rockchip_writel(rockchip, PCIE_CORE_OB_REGION_ADDR0 + aw_offset,
> + ob_addr_0);
> + rockchip_writel(rockchip, PCIE_CORE_OB_REGION_ADDR1 + aw_offset,
> + ob_addr_1);
> + rockchip_writel(rockchip, PCIE_CORE_OB_REGION_DESC0 + aw_offset,
> + ob_desc_0);
> + rockchip_writel(rockchip, PCIE_CORE_OB_REGION_DESC1 + aw_offset, 0);
>
> return 0;
> }
> @@ -1018,8 +1011,8 @@ static int rockchip_pcie_prog_ib_atu(struct rockchip_pcie *rockchip,
> ib_addr_0 |= (lower_addr << 8) & PCIE_CORE_IB_REGION_ADDR0_LO_ADDR;
> ib_addr_1 = upper_addr;
>
> - rockchip_writel(rockchip, ib_addr_0, PCIE_RP_IB_ADDR0 + aw_offset);
> - rockchip_writel(rockchip, ib_addr_1, PCIE_RP_IB_ADDR1 + aw_offset);
> + rockchip_writel(rockchip, PCIE_RP_IB_ADDR0 + aw_offset, ib_addr_0);
> + rockchip_writel(rockchip, PCIE_RP_IB_ADDR1 + aw_offset, ib_addr_1);
>
> return 0;
> }
>
>
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip
>
--
Best Regards
Shawn Lin
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 3/3] PCI: rockchip: Remove unused platform data
2016-10-07 16:27 [PATCH 1/3] PCI: rockchip: Rename accessors Bjorn Helgaas
2016-10-07 16:27 ` [PATCH 2/3] PCI: rockchip: Swap order of rockchip_writel() reg/val arguments Bjorn Helgaas
@ 2016-10-07 16:27 ` Bjorn Helgaas
2016-10-08 2:54 ` Shawn Lin
2016-10-08 2:51 ` Shawn Lin
2 siblings, 1 reply; 9+ messages in thread
From: Bjorn Helgaas @ 2016-10-07 16:27 UTC (permalink / raw)
To: Shawn Lin, Wenrui Li, Heiko Stuebner; +Cc: linux-rockchip, linux-pci
The rockchip driver never uses the platform drvdata pointer, so don't
bother setting it. No functional change intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
drivers/pci/host/pcie-rockchip.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index 0a89d02..b3548d0 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -1019,8 +1019,8 @@ static int rockchip_pcie_prog_ib_atu(struct rockchip_pcie *rockchip,
static int rockchip_pcie_probe(struct platform_device *pdev)
{
- struct rockchip_pcie *rockchip;
struct device *dev = &pdev->dev;
+ struct rockchip_pcie *rockchip;
struct pci_bus *bus, *child;
struct resource_entry *win;
resource_size_t io_base;
@@ -1083,8 +1083,6 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
if (err)
goto err_vpcie;
- platform_set_drvdata(pdev, rockchip);
-
rockchip_pcie_enable_interrupts(rockchip);
err = rockchip_pcie_init_irq_domain(rockchip);
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH 3/3] PCI: rockchip: Remove unused platform data
2016-10-07 16:27 ` [PATCH 3/3] PCI: rockchip: Remove unused platform data Bjorn Helgaas
@ 2016-10-08 2:54 ` Shawn Lin
0 siblings, 0 replies; 9+ messages in thread
From: Shawn Lin @ 2016-10-08 2:54 UTC (permalink / raw)
To: Bjorn Helgaas, Shawn Lin, Wenrui Li, Heiko Stuebner
Cc: shawn.lin, linux-rockchip, linux-pci
在 2016/10/8 0:27, Bjorn Helgaas 写道:
> The rockchip driver never uses the platform drvdata pointer, so don't
> bother setting it. No functional change intended.
>
Currently it's a build-in driver, so it seems okay to remove
this now.
Acked-by: Shawn Lin <shawn.lin@rock-chips.com>
> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
> ---
> drivers/pci/host/pcie-rockchip.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
> index 0a89d02..b3548d0 100644
> --- a/drivers/pci/host/pcie-rockchip.c
> +++ b/drivers/pci/host/pcie-rockchip.c
> @@ -1019,8 +1019,8 @@ static int rockchip_pcie_prog_ib_atu(struct rockchip_pcie *rockchip,
>
> static int rockchip_pcie_probe(struct platform_device *pdev)
> {
> - struct rockchip_pcie *rockchip;
> struct device *dev = &pdev->dev;
> + struct rockchip_pcie *rockchip;
> struct pci_bus *bus, *child;
> struct resource_entry *win;
> resource_size_t io_base;
> @@ -1083,8 +1083,6 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
> if (err)
> goto err_vpcie;
>
> - platform_set_drvdata(pdev, rockchip);
> -
> rockchip_pcie_enable_interrupts(rockchip);
>
> err = rockchip_pcie_init_irq_domain(rockchip);
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
--
Best Regards
Shawn Lin
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH 3/3] PCI: rockchip: Remove unused platform data
@ 2016-10-08 2:54 ` Shawn Lin
0 siblings, 0 replies; 9+ messages in thread
From: Shawn Lin @ 2016-10-08 2:54 UTC (permalink / raw)
To: Bjorn Helgaas, Wenrui Li, Heiko Stuebner
Cc: shawn.lin, linux-rockchip, linux-pci
在 2016/10/8 0:27, Bjorn Helgaas 写道:
> The rockchip driver never uses the platform drvdata pointer, so don't
> bother setting it. No functional change intended.
>
Currently it's a build-in driver, so it seems okay to remove
this now.
Acked-by: Shawn Lin <shawn.lin@rock-chips.com>
> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
> ---
> drivers/pci/host/pcie-rockchip.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
> index 0a89d02..b3548d0 100644
> --- a/drivers/pci/host/pcie-rockchip.c
> +++ b/drivers/pci/host/pcie-rockchip.c
> @@ -1019,8 +1019,8 @@ static int rockchip_pcie_prog_ib_atu(struct rockchip_pcie *rockchip,
>
> static int rockchip_pcie_probe(struct platform_device *pdev)
> {
> - struct rockchip_pcie *rockchip;
> struct device *dev = &pdev->dev;
> + struct rockchip_pcie *rockchip;
> struct pci_bus *bus, *child;
> struct resource_entry *win;
> resource_size_t io_base;
> @@ -1083,8 +1083,6 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
> if (err)
> goto err_vpcie;
>
> - platform_set_drvdata(pdev, rockchip);
> -
> rockchip_pcie_enable_interrupts(rockchip);
>
> err = rockchip_pcie_init_irq_domain(rockchip);
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
--
Best Regards
Shawn Lin
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/3] PCI: rockchip: Rename accessors
2016-10-07 16:27 [PATCH 1/3] PCI: rockchip: Rename accessors Bjorn Helgaas
@ 2016-10-08 2:51 ` Shawn Lin
2016-10-07 16:27 ` [PATCH 3/3] PCI: rockchip: Remove unused platform data Bjorn Helgaas
2016-10-08 2:51 ` Shawn Lin
2 siblings, 0 replies; 9+ messages in thread
From: Shawn Lin @ 2016-10-08 2:51 UTC (permalink / raw)
To: Bjorn Helgaas, Shawn Lin, Wenrui Li, Heiko Stuebner
Cc: shawn.lin, linux-rockchip, linux-pci
在 2016/10/8 0:27, Bjorn Helgaas 写道:
> Rename rockchip_pcie_read() to rockchip_readl() and rockchip_pcie_write()
> to rockchip_writel() for consistency with other drivers. No functional
> change intended.
>
It looks okay to me if this modification make pcie-rockchip looks more
consisten with other drivers.
Acked-by: Shawn Lin <shawn.lin@rock-chips.com>
> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
> ---
> drivers/pci/host/pcie-rockchip.c | 85 +++++++++++++++++++-------------------
> 1 file changed, 42 insertions(+), 43 deletions(-)
>
> diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
> index b8c82fc..0ef2f9f 100644
> --- a/drivers/pci/host/pcie-rockchip.c
> +++ b/drivers/pci/host/pcie-rockchip.c
> @@ -204,12 +204,12 @@ struct rockchip_pcie {
> struct irq_domain *irq_domain;
> };
>
> -static u32 rockchip_pcie_read(struct rockchip_pcie *rockchip, u32 reg)
> +static u32 rockchip_readl(struct rockchip_pcie *rockchip, u32 reg)
> {
> return readl(rockchip->apb_base + reg);
> }
>
> -static void rockchip_pcie_write(struct rockchip_pcie *rockchip, u32 val,
> +static void rockchip_writel(struct rockchip_pcie *rockchip, u32 val,
> u32 reg)
> {
> writel(val, rockchip->apb_base + reg);
> @@ -219,18 +219,18 @@ static void rockchip_pcie_enable_bw_int(struct rockchip_pcie *rockchip)
> {
> u32 status;
>
> - status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
> + status = rockchip_readl(rockchip, PCIE_RC_CONFIG_LCS);
> status |= (PCIE_RC_CONFIG_LCS_LBMIE | PCIE_RC_CONFIG_LCS_LABIE);
> - rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
> + rockchip_writel(rockchip, status, PCIE_RC_CONFIG_LCS);
> }
>
> static void rockchip_pcie_clr_bw_int(struct rockchip_pcie *rockchip)
> {
> u32 status;
>
> - status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
> + status = rockchip_readl(rockchip, PCIE_RC_CONFIG_LCS);
> status |= (PCIE_RC_CONFIG_LCS_LBMS | PCIE_RC_CONFIG_LCS_LAMS);
> - rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
> + rockchip_writel(rockchip, status, PCIE_RC_CONFIG_LCS);
> }
>
> static void rockchip_pcie_update_txcredit_mui(struct rockchip_pcie *rockchip)
> @@ -238,10 +238,10 @@ static void rockchip_pcie_update_txcredit_mui(struct rockchip_pcie *rockchip)
> u32 val;
>
> /* Update Tx credit maximum update interval */
> - val = rockchip_pcie_read(rockchip, PCIE_CORE_TXCREDIT_CFG1);
> + val = rockchip_readl(rockchip, PCIE_CORE_TXCREDIT_CFG1);
> val &= ~PCIE_CORE_TXCREDIT_CFG1_MUI_MASK;
> val |= PCIE_CORE_TXCREDIT_CFG1_MUI_ENCODE(24000); /* ns */
> - rockchip_pcie_write(rockchip, val, PCIE_CORE_TXCREDIT_CFG1);
> + rockchip_writel(rockchip, val, PCIE_CORE_TXCREDIT_CFG1);
> }
>
> static int rockchip_pcie_valid_device(struct rockchip_pcie *rockchip,
> @@ -438,7 +438,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
> return err;
> }
>
> - rockchip_pcie_write(rockchip,
> + rockchip_writel(rockchip,
> PCIE_CLIENT_CONF_ENABLE |
> PCIE_CLIENT_LINK_TRAIN_ENABLE |
> PCIE_CLIENT_ARI_ENABLE |
> @@ -487,17 +487,17 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
> * reliable and enabling ASPM doesn't work. This is a controller
> * bug we need to work around.
> */
> - status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
> - rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
> + status = rockchip_readl(rockchip, PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
> + rockchip_writel(rockchip, status, PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
>
> /* Fix the transmitted FTS count desired to exit from L0s. */
> - status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL_PLC1);
> + status = rockchip_readl(rockchip, PCIE_CORE_CTRL_PLC1);
> status = (status & PCIE_CORE_CTRL_PLC1_FTS_MASK) |
> (PCIE_CORE_CTRL_PLC1_FTS_CNT << PCIE_CORE_CTRL_PLC1_FTS_SHIFT);
> - rockchip_pcie_write(rockchip, status, PCIE_CORE_CTRL_PLC1);
> + rockchip_writel(rockchip, status, PCIE_CORE_CTRL_PLC1);
>
> /* Enable Gen1 training */
> - rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
> + rockchip_writel(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
> PCIE_CLIENT_CONFIG);
>
> gpiod_set_value(rockchip->ep_gpio, 1);
> @@ -506,8 +506,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
> timeout = jiffies + msecs_to_jiffies(500);
>
> for (;;) {
> - status = rockchip_pcie_read(rockchip,
> - PCIE_CLIENT_BASIC_STATUS1);
> + status = rockchip_readl(rockchip, PCIE_CLIENT_BASIC_STATUS1);
> if ((status & PCIE_CLIENT_LINK_STATUS_MASK) ==
> PCIE_CLIENT_LINK_STATUS_UP) {
> dev_dbg(dev, "PCIe link training gen1 pass!\n");
> @@ -526,13 +525,13 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
> * Enable retrain for gen2. This should be configured only after
> * gen1 finished.
> */
> - status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
> + status = rockchip_readl(rockchip, PCIE_RC_CONFIG_LCS);
> status |= PCIE_RC_CONFIG_LCS_RETRAIN_LINK;
> - rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
> + rockchip_writel(rockchip, status, PCIE_RC_CONFIG_LCS);
>
> timeout = jiffies + msecs_to_jiffies(500);
> for (;;) {
> - status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);
> + status = rockchip_readl(rockchip, PCIE_CORE_CTRL);
> if ((status & PCIE_CORE_PL_CONF_SPEED_MASK) ==
> PCIE_CORE_PL_CONF_SPEED_5G) {
> dev_dbg(dev, "PCIe link training gen2 pass!\n");
> @@ -548,25 +547,25 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
> }
>
> /* Check the final link width from negotiated lane counter from MGMT */
> - status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);
> + status = rockchip_readl(rockchip, PCIE_CORE_CTRL);
> status = 0x1 << ((status & PCIE_CORE_PL_CONF_LANE_MASK) >>
> PCIE_CORE_PL_CONF_LANE_MASK);
> dev_dbg(dev, "current link width is x%d\n", status);
>
> - rockchip_pcie_write(rockchip, ROCKCHIP_VENDOR_ID,
> + rockchip_writel(rockchip, ROCKCHIP_VENDOR_ID,
> PCIE_RC_CONFIG_VENDOR);
> - rockchip_pcie_write(rockchip,
> + rockchip_writel(rockchip,
> PCI_CLASS_BRIDGE_PCI << PCIE_RC_CONFIG_SCC_SHIFT,
> PCIE_RC_CONFIG_RID_CCR);
> - rockchip_pcie_write(rockchip, 0x0, PCIE_RC_BAR_CONF);
> + rockchip_writel(rockchip, 0x0, PCIE_RC_BAR_CONF);
>
> - rockchip_pcie_write(rockchip,
> + rockchip_writel(rockchip,
> (RC_REGION_0_ADDR_TRANS_L + RC_REGION_0_PASS_BITS),
> PCIE_CORE_OB_REGION_ADDR0);
> - rockchip_pcie_write(rockchip, RC_REGION_0_ADDR_TRANS_H,
> + rockchip_writel(rockchip, RC_REGION_0_ADDR_TRANS_H,
> PCIE_CORE_OB_REGION_ADDR1);
> - rockchip_pcie_write(rockchip, 0x0080000a, PCIE_CORE_OB_REGION_DESC0);
> - rockchip_pcie_write(rockchip, 0x0, PCIE_CORE_OB_REGION_DESC1);
> + rockchip_writel(rockchip, 0x0080000a, PCIE_CORE_OB_REGION_DESC0);
> + rockchip_writel(rockchip, 0x0, PCIE_CORE_OB_REGION_DESC1);
>
> return 0;
> }
> @@ -578,10 +577,10 @@ static irqreturn_t rockchip_pcie_subsys_irq_handler(int irq, void *arg)
> u32 reg;
> u32 sub_reg;
>
> - reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
> + reg = rockchip_readl(rockchip, PCIE_CLIENT_INT_STATUS);
> if (reg & PCIE_CLIENT_INT_LOCAL) {
> dev_dbg(dev, "local interrupt received\n");
> - sub_reg = rockchip_pcie_read(rockchip, PCIE_CORE_INT_STATUS);
> + sub_reg = rockchip_readl(rockchip, PCIE_CORE_INT_STATUS);
> if (sub_reg & PCIE_CORE_INT_PRFPE)
> dev_dbg(dev, "parity error detected while reading from the PNP receive FIFO RAM\n");
>
> @@ -624,15 +623,15 @@ static irqreturn_t rockchip_pcie_subsys_irq_handler(int irq, void *arg)
> if (sub_reg & PCIE_CORE_INT_MMVC)
> dev_dbg(dev, "MSI mask register changes\n");
>
> - rockchip_pcie_write(rockchip, sub_reg, PCIE_CORE_INT_STATUS);
> + rockchip_writel(rockchip, sub_reg, PCIE_CORE_INT_STATUS);
> } else if (reg & PCIE_CLIENT_INT_PHY) {
> dev_dbg(dev, "phy link changes\n");
> rockchip_pcie_update_txcredit_mui(rockchip);
> rockchip_pcie_clr_bw_int(rockchip);
> }
>
> - rockchip_pcie_write(rockchip, reg & PCIE_CLIENT_INT_LOCAL,
> - PCIE_CLIENT_INT_STATUS);
> + rockchip_writel(rockchip, reg & PCIE_CLIENT_INT_LOCAL,
> + PCIE_CLIENT_INT_STATUS);
>
> return IRQ_HANDLED;
> }
> @@ -643,7 +642,7 @@ static irqreturn_t rockchip_pcie_client_irq_handler(int irq, void *arg)
> struct device *dev = rockchip->dev;
> u32 reg;
>
> - reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
> + reg = rockchip_readl(rockchip, PCIE_CLIENT_INT_STATUS);
> if (reg & PCIE_CLIENT_INT_LEGACY_DONE)
> dev_dbg(dev, "legacy done interrupt received\n");
>
> @@ -668,7 +667,7 @@ static irqreturn_t rockchip_pcie_client_irq_handler(int irq, void *arg)
> if (reg & PCIE_CLIENT_INT_PHY)
> dev_dbg(dev, "phy interrupt received\n");
>
> - rockchip_pcie_write(rockchip, reg & (PCIE_CLIENT_INT_LEGACY_DONE |
> + rockchip_writel(rockchip, reg & (PCIE_CLIENT_INT_LEGACY_DONE |
> PCIE_CLIENT_INT_MSG | PCIE_CLIENT_INT_HOT_RST |
> PCIE_CLIENT_INT_DPA | PCIE_CLIENT_INT_FATAL_ERR |
> PCIE_CLIENT_INT_NFATAL_ERR |
> @@ -690,7 +689,7 @@ static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc)
>
> chained_irq_enter(chip, desc);
>
> - reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
> + reg = rockchip_readl(rockchip, PCIE_CLIENT_INT_STATUS);
> reg = (reg & PCIE_CLIENT_INTR_MASK) >> PCIE_CLIENT_INTR_SHIFT;
>
> while (reg) {
> @@ -914,9 +913,9 @@ err_out:
>
> static void rockchip_pcie_enable_interrupts(struct rockchip_pcie *rockchip)
> {
> - rockchip_pcie_write(rockchip, (PCIE_CLIENT_INT_CLI << 16) &
> + rockchip_writel(rockchip, (PCIE_CLIENT_INT_CLI << 16) &
> (~PCIE_CLIENT_INT_CLI), PCIE_CLIENT_INT_MASK);
> - rockchip_pcie_write(rockchip, (u32)(~PCIE_CORE_INT),
> + rockchip_writel(rockchip, (u32)(~PCIE_CORE_INT),
> PCIE_CORE_INT_MASK);
>
> rockchip_pcie_enable_bw_int(rockchip);
> @@ -986,13 +985,13 @@ static int rockchip_pcie_prog_ob_atu(struct rockchip_pcie *rockchip,
> ob_addr_1 = upper_addr;
> ob_desc_0 = (1 << 23 | type);
>
> - rockchip_pcie_write(rockchip, ob_addr_0,
> + rockchip_writel(rockchip, ob_addr_0,
> PCIE_CORE_OB_REGION_ADDR0 + aw_offset);
> - rockchip_pcie_write(rockchip, ob_addr_1,
> + rockchip_writel(rockchip, ob_addr_1,
> PCIE_CORE_OB_REGION_ADDR1 + aw_offset);
> - rockchip_pcie_write(rockchip, ob_desc_0,
> + rockchip_writel(rockchip, ob_desc_0,
> PCIE_CORE_OB_REGION_DESC0 + aw_offset);
> - rockchip_pcie_write(rockchip, 0,
> + rockchip_writel(rockchip, 0,
> PCIE_CORE_OB_REGION_DESC1 + aw_offset);
>
> return 0;
> @@ -1019,8 +1018,8 @@ static int rockchip_pcie_prog_ib_atu(struct rockchip_pcie *rockchip,
> ib_addr_0 |= (lower_addr << 8) & PCIE_CORE_IB_REGION_ADDR0_LO_ADDR;
> ib_addr_1 = upper_addr;
>
> - rockchip_pcie_write(rockchip, ib_addr_0, PCIE_RP_IB_ADDR0 + aw_offset);
> - rockchip_pcie_write(rockchip, ib_addr_1, PCIE_RP_IB_ADDR1 + aw_offset);
> + rockchip_writel(rockchip, ib_addr_0, PCIE_RP_IB_ADDR0 + aw_offset);
> + rockchip_writel(rockchip, ib_addr_1, PCIE_RP_IB_ADDR1 + aw_offset);
>
> return 0;
> }
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
--
Best Regards
Shawn Lin
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH 1/3] PCI: rockchip: Rename accessors
@ 2016-10-08 2:51 ` Shawn Lin
0 siblings, 0 replies; 9+ messages in thread
From: Shawn Lin @ 2016-10-08 2:51 UTC (permalink / raw)
To: Bjorn Helgaas, Wenrui Li, Heiko Stuebner
Cc: shawn.lin, linux-rockchip, linux-pci
在 2016/10/8 0:27, Bjorn Helgaas 写道:
> Rename rockchip_pcie_read() to rockchip_readl() and rockchip_pcie_write()
> to rockchip_writel() for consistency with other drivers. No functional
> change intended.
>
It looks okay to me if this modification make pcie-rockchip looks more
consisten with other drivers.
Acked-by: Shawn Lin <shawn.lin@rock-chips.com>
> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
> ---
> drivers/pci/host/pcie-rockchip.c | 85 +++++++++++++++++++-------------------
> 1 file changed, 42 insertions(+), 43 deletions(-)
>
> diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
> index b8c82fc..0ef2f9f 100644
> --- a/drivers/pci/host/pcie-rockchip.c
> +++ b/drivers/pci/host/pcie-rockchip.c
> @@ -204,12 +204,12 @@ struct rockchip_pcie {
> struct irq_domain *irq_domain;
> };
>
> -static u32 rockchip_pcie_read(struct rockchip_pcie *rockchip, u32 reg)
> +static u32 rockchip_readl(struct rockchip_pcie *rockchip, u32 reg)
> {
> return readl(rockchip->apb_base + reg);
> }
>
> -static void rockchip_pcie_write(struct rockchip_pcie *rockchip, u32 val,
> +static void rockchip_writel(struct rockchip_pcie *rockchip, u32 val,
> u32 reg)
> {
> writel(val, rockchip->apb_base + reg);
> @@ -219,18 +219,18 @@ static void rockchip_pcie_enable_bw_int(struct rockchip_pcie *rockchip)
> {
> u32 status;
>
> - status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
> + status = rockchip_readl(rockchip, PCIE_RC_CONFIG_LCS);
> status |= (PCIE_RC_CONFIG_LCS_LBMIE | PCIE_RC_CONFIG_LCS_LABIE);
> - rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
> + rockchip_writel(rockchip, status, PCIE_RC_CONFIG_LCS);
> }
>
> static void rockchip_pcie_clr_bw_int(struct rockchip_pcie *rockchip)
> {
> u32 status;
>
> - status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
> + status = rockchip_readl(rockchip, PCIE_RC_CONFIG_LCS);
> status |= (PCIE_RC_CONFIG_LCS_LBMS | PCIE_RC_CONFIG_LCS_LAMS);
> - rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
> + rockchip_writel(rockchip, status, PCIE_RC_CONFIG_LCS);
> }
>
> static void rockchip_pcie_update_txcredit_mui(struct rockchip_pcie *rockchip)
> @@ -238,10 +238,10 @@ static void rockchip_pcie_update_txcredit_mui(struct rockchip_pcie *rockchip)
> u32 val;
>
> /* Update Tx credit maximum update interval */
> - val = rockchip_pcie_read(rockchip, PCIE_CORE_TXCREDIT_CFG1);
> + val = rockchip_readl(rockchip, PCIE_CORE_TXCREDIT_CFG1);
> val &= ~PCIE_CORE_TXCREDIT_CFG1_MUI_MASK;
> val |= PCIE_CORE_TXCREDIT_CFG1_MUI_ENCODE(24000); /* ns */
> - rockchip_pcie_write(rockchip, val, PCIE_CORE_TXCREDIT_CFG1);
> + rockchip_writel(rockchip, val, PCIE_CORE_TXCREDIT_CFG1);
> }
>
> static int rockchip_pcie_valid_device(struct rockchip_pcie *rockchip,
> @@ -438,7 +438,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
> return err;
> }
>
> - rockchip_pcie_write(rockchip,
> + rockchip_writel(rockchip,
> PCIE_CLIENT_CONF_ENABLE |
> PCIE_CLIENT_LINK_TRAIN_ENABLE |
> PCIE_CLIENT_ARI_ENABLE |
> @@ -487,17 +487,17 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
> * reliable and enabling ASPM doesn't work. This is a controller
> * bug we need to work around.
> */
> - status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
> - rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
> + status = rockchip_readl(rockchip, PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
> + rockchip_writel(rockchip, status, PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
>
> /* Fix the transmitted FTS count desired to exit from L0s. */
> - status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL_PLC1);
> + status = rockchip_readl(rockchip, PCIE_CORE_CTRL_PLC1);
> status = (status & PCIE_CORE_CTRL_PLC1_FTS_MASK) |
> (PCIE_CORE_CTRL_PLC1_FTS_CNT << PCIE_CORE_CTRL_PLC1_FTS_SHIFT);
> - rockchip_pcie_write(rockchip, status, PCIE_CORE_CTRL_PLC1);
> + rockchip_writel(rockchip, status, PCIE_CORE_CTRL_PLC1);
>
> /* Enable Gen1 training */
> - rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
> + rockchip_writel(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
> PCIE_CLIENT_CONFIG);
>
> gpiod_set_value(rockchip->ep_gpio, 1);
> @@ -506,8 +506,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
> timeout = jiffies + msecs_to_jiffies(500);
>
> for (;;) {
> - status = rockchip_pcie_read(rockchip,
> - PCIE_CLIENT_BASIC_STATUS1);
> + status = rockchip_readl(rockchip, PCIE_CLIENT_BASIC_STATUS1);
> if ((status & PCIE_CLIENT_LINK_STATUS_MASK) ==
> PCIE_CLIENT_LINK_STATUS_UP) {
> dev_dbg(dev, "PCIe link training gen1 pass!\n");
> @@ -526,13 +525,13 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
> * Enable retrain for gen2. This should be configured only after
> * gen1 finished.
> */
> - status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
> + status = rockchip_readl(rockchip, PCIE_RC_CONFIG_LCS);
> status |= PCIE_RC_CONFIG_LCS_RETRAIN_LINK;
> - rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
> + rockchip_writel(rockchip, status, PCIE_RC_CONFIG_LCS);
>
> timeout = jiffies + msecs_to_jiffies(500);
> for (;;) {
> - status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);
> + status = rockchip_readl(rockchip, PCIE_CORE_CTRL);
> if ((status & PCIE_CORE_PL_CONF_SPEED_MASK) ==
> PCIE_CORE_PL_CONF_SPEED_5G) {
> dev_dbg(dev, "PCIe link training gen2 pass!\n");
> @@ -548,25 +547,25 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
> }
>
> /* Check the final link width from negotiated lane counter from MGMT */
> - status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);
> + status = rockchip_readl(rockchip, PCIE_CORE_CTRL);
> status = 0x1 << ((status & PCIE_CORE_PL_CONF_LANE_MASK) >>
> PCIE_CORE_PL_CONF_LANE_MASK);
> dev_dbg(dev, "current link width is x%d\n", status);
>
> - rockchip_pcie_write(rockchip, ROCKCHIP_VENDOR_ID,
> + rockchip_writel(rockchip, ROCKCHIP_VENDOR_ID,
> PCIE_RC_CONFIG_VENDOR);
> - rockchip_pcie_write(rockchip,
> + rockchip_writel(rockchip,
> PCI_CLASS_BRIDGE_PCI << PCIE_RC_CONFIG_SCC_SHIFT,
> PCIE_RC_CONFIG_RID_CCR);
> - rockchip_pcie_write(rockchip, 0x0, PCIE_RC_BAR_CONF);
> + rockchip_writel(rockchip, 0x0, PCIE_RC_BAR_CONF);
>
> - rockchip_pcie_write(rockchip,
> + rockchip_writel(rockchip,
> (RC_REGION_0_ADDR_TRANS_L + RC_REGION_0_PASS_BITS),
> PCIE_CORE_OB_REGION_ADDR0);
> - rockchip_pcie_write(rockchip, RC_REGION_0_ADDR_TRANS_H,
> + rockchip_writel(rockchip, RC_REGION_0_ADDR_TRANS_H,
> PCIE_CORE_OB_REGION_ADDR1);
> - rockchip_pcie_write(rockchip, 0x0080000a, PCIE_CORE_OB_REGION_DESC0);
> - rockchip_pcie_write(rockchip, 0x0, PCIE_CORE_OB_REGION_DESC1);
> + rockchip_writel(rockchip, 0x0080000a, PCIE_CORE_OB_REGION_DESC0);
> + rockchip_writel(rockchip, 0x0, PCIE_CORE_OB_REGION_DESC1);
>
> return 0;
> }
> @@ -578,10 +577,10 @@ static irqreturn_t rockchip_pcie_subsys_irq_handler(int irq, void *arg)
> u32 reg;
> u32 sub_reg;
>
> - reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
> + reg = rockchip_readl(rockchip, PCIE_CLIENT_INT_STATUS);
> if (reg & PCIE_CLIENT_INT_LOCAL) {
> dev_dbg(dev, "local interrupt received\n");
> - sub_reg = rockchip_pcie_read(rockchip, PCIE_CORE_INT_STATUS);
> + sub_reg = rockchip_readl(rockchip, PCIE_CORE_INT_STATUS);
> if (sub_reg & PCIE_CORE_INT_PRFPE)
> dev_dbg(dev, "parity error detected while reading from the PNP receive FIFO RAM\n");
>
> @@ -624,15 +623,15 @@ static irqreturn_t rockchip_pcie_subsys_irq_handler(int irq, void *arg)
> if (sub_reg & PCIE_CORE_INT_MMVC)
> dev_dbg(dev, "MSI mask register changes\n");
>
> - rockchip_pcie_write(rockchip, sub_reg, PCIE_CORE_INT_STATUS);
> + rockchip_writel(rockchip, sub_reg, PCIE_CORE_INT_STATUS);
> } else if (reg & PCIE_CLIENT_INT_PHY) {
> dev_dbg(dev, "phy link changes\n");
> rockchip_pcie_update_txcredit_mui(rockchip);
> rockchip_pcie_clr_bw_int(rockchip);
> }
>
> - rockchip_pcie_write(rockchip, reg & PCIE_CLIENT_INT_LOCAL,
> - PCIE_CLIENT_INT_STATUS);
> + rockchip_writel(rockchip, reg & PCIE_CLIENT_INT_LOCAL,
> + PCIE_CLIENT_INT_STATUS);
>
> return IRQ_HANDLED;
> }
> @@ -643,7 +642,7 @@ static irqreturn_t rockchip_pcie_client_irq_handler(int irq, void *arg)
> struct device *dev = rockchip->dev;
> u32 reg;
>
> - reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
> + reg = rockchip_readl(rockchip, PCIE_CLIENT_INT_STATUS);
> if (reg & PCIE_CLIENT_INT_LEGACY_DONE)
> dev_dbg(dev, "legacy done interrupt received\n");
>
> @@ -668,7 +667,7 @@ static irqreturn_t rockchip_pcie_client_irq_handler(int irq, void *arg)
> if (reg & PCIE_CLIENT_INT_PHY)
> dev_dbg(dev, "phy interrupt received\n");
>
> - rockchip_pcie_write(rockchip, reg & (PCIE_CLIENT_INT_LEGACY_DONE |
> + rockchip_writel(rockchip, reg & (PCIE_CLIENT_INT_LEGACY_DONE |
> PCIE_CLIENT_INT_MSG | PCIE_CLIENT_INT_HOT_RST |
> PCIE_CLIENT_INT_DPA | PCIE_CLIENT_INT_FATAL_ERR |
> PCIE_CLIENT_INT_NFATAL_ERR |
> @@ -690,7 +689,7 @@ static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc)
>
> chained_irq_enter(chip, desc);
>
> - reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
> + reg = rockchip_readl(rockchip, PCIE_CLIENT_INT_STATUS);
> reg = (reg & PCIE_CLIENT_INTR_MASK) >> PCIE_CLIENT_INTR_SHIFT;
>
> while (reg) {
> @@ -914,9 +913,9 @@ err_out:
>
> static void rockchip_pcie_enable_interrupts(struct rockchip_pcie *rockchip)
> {
> - rockchip_pcie_write(rockchip, (PCIE_CLIENT_INT_CLI << 16) &
> + rockchip_writel(rockchip, (PCIE_CLIENT_INT_CLI << 16) &
> (~PCIE_CLIENT_INT_CLI), PCIE_CLIENT_INT_MASK);
> - rockchip_pcie_write(rockchip, (u32)(~PCIE_CORE_INT),
> + rockchip_writel(rockchip, (u32)(~PCIE_CORE_INT),
> PCIE_CORE_INT_MASK);
>
> rockchip_pcie_enable_bw_int(rockchip);
> @@ -986,13 +985,13 @@ static int rockchip_pcie_prog_ob_atu(struct rockchip_pcie *rockchip,
> ob_addr_1 = upper_addr;
> ob_desc_0 = (1 << 23 | type);
>
> - rockchip_pcie_write(rockchip, ob_addr_0,
> + rockchip_writel(rockchip, ob_addr_0,
> PCIE_CORE_OB_REGION_ADDR0 + aw_offset);
> - rockchip_pcie_write(rockchip, ob_addr_1,
> + rockchip_writel(rockchip, ob_addr_1,
> PCIE_CORE_OB_REGION_ADDR1 + aw_offset);
> - rockchip_pcie_write(rockchip, ob_desc_0,
> + rockchip_writel(rockchip, ob_desc_0,
> PCIE_CORE_OB_REGION_DESC0 + aw_offset);
> - rockchip_pcie_write(rockchip, 0,
> + rockchip_writel(rockchip, 0,
> PCIE_CORE_OB_REGION_DESC1 + aw_offset);
>
> return 0;
> @@ -1019,8 +1018,8 @@ static int rockchip_pcie_prog_ib_atu(struct rockchip_pcie *rockchip,
> ib_addr_0 |= (lower_addr << 8) & PCIE_CORE_IB_REGION_ADDR0_LO_ADDR;
> ib_addr_1 = upper_addr;
>
> - rockchip_pcie_write(rockchip, ib_addr_0, PCIE_RP_IB_ADDR0 + aw_offset);
> - rockchip_pcie_write(rockchip, ib_addr_1, PCIE_RP_IB_ADDR1 + aw_offset);
> + rockchip_writel(rockchip, ib_addr_0, PCIE_RP_IB_ADDR0 + aw_offset);
> + rockchip_writel(rockchip, ib_addr_1, PCIE_RP_IB_ADDR1 + aw_offset);
>
> return 0;
> }
>
> --
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>
--
Best Regards
Shawn Lin
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2016-10-08 2:54 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-10-07 16:27 [PATCH 1/3] PCI: rockchip: Rename accessors Bjorn Helgaas
2016-10-07 16:27 ` [PATCH 2/3] PCI: rockchip: Swap order of rockchip_writel() reg/val arguments Bjorn Helgaas
2016-10-08 2:52 ` Shawn Lin
2016-10-08 2:52 ` Shawn Lin
2016-10-07 16:27 ` [PATCH 3/3] PCI: rockchip: Remove unused platform data Bjorn Helgaas
2016-10-08 2:54 ` Shawn Lin
2016-10-08 2:54 ` Shawn Lin
2016-10-08 2:51 ` [PATCH 1/3] PCI: rockchip: Rename accessors Shawn Lin
2016-10-08 2:51 ` Shawn Lin
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