[PATCH] drm/i915/gen9+: Whitelist TIMESTAMP register from BLT ring

From: Andrzej Lawrynowicz <andrzej.lawrynowicz@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: andrzej.lawrynowicz@intel.com
Subject: [PATCH] drm/i915/gen9+: Whitelist TIMESTAMP register from BLT ring
Date: Thu, 27 Oct 2016 16:39:31 +0200	[thread overview]
Message-ID: <20161027143931.28160-1-andrzej.lawrynowicz@intel.com> (raw)

Since gen9 timestamp can be read from BLT ring (TIMESTAMP_BCSUNIT).
Add this register to reg_read ioctl whitelist.

cc=chris@chris-wilson.co.uk
cc=arkadiusz.hiler@intel.com
cc=michal.winiarski@intel.com

Signed-off-by: Andrzej Lawrynowicz <andrzej.lawrynowicz@intel.com>
---
 drivers/gpu/drm/i915/intel_uncore.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index e2b188d..c2c3fe6 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1354,6 +1354,9 @@ static const struct register_whitelist {
 	{ .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
 	  .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
 	  .size = 8, .gen_bitmask = GEN_RANGE(4, 9) },
+	{ .offset_ldw = RING_TIMESTAMP(BLT_RING_BASE),
+	  .offset_udw = RING_TIMESTAMP_UDW(BLT_RING_BASE),
+	  .size = 8, .gen_bitmask = GEN_RANGE(9, 9) },
 };
 
 int i915_reg_read_ioctl(struct drm_device *dev,
-- 
2.10.1

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