From: Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> To: Vivek Gautam <vivek.gautam-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> Cc: kishon-l0cyMroinI0@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, mark.rutland-5wv7dgnIgG8@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, srinivas.kandagatla-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org Subject: Re: [PATCH v2 3/4] dt-bindings: phy: Add support for QMP phy Date: Mon, 28 Nov 2016 14:55:43 -0800 [thread overview] Message-ID: <20161128225543.GM6095@codeaurora.org> (raw) In-Reply-To: <1479816163-5260-4-git-send-email-vivek.gautam-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> On 11/22, Vivek Gautam wrote: > diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt > new file mode 100644 > index 0000000..ffb173b > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt > @@ -0,0 +1,74 @@ > +Qualcomm QMP PHY > +---------------- > + > +QMP phy controller supports physical layer functionality for a number of > +controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB. > + > +Required properties: > + - compatible: compatible list, contains: > + "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996, > + "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996. > + - reg: list of offset and length pair of the PHY register sets. > + at index 0: offset and length of register set for PHY common > + serdes block. > + from index 1 - N: offset and length of register set for each lane, > + for N number of phy lanes (ports). > + - lane-offsets: array of offsets to tx, rx and pcs blocks for phy lanes. > + - #phy-cells: must be 1 > + - Cell after phy phandle should be the port (lane) number. > + - clocks: a list of phandles and clock-specifier pairs, > + one for each entry in clock-names. > + - clock-names: must be "cfg_ahb" for phy config clock, > + "aux" for phy aux clock, > + "ref_clk" for 19.2 MHz ref clk, > + "ref_clk_src" for reference clock source, We typically leave "clk" out of clk names because it's redundant. > + "pipe<port-number>" for pipe clock specific to > + each port/lane (Optional). The pipe clocks are orphaned right now. We should add an output clock from the phy to go into the controller and back into the phy if I recall correctly. The phy should be a clock provider itself so it can output the pipe clock source into GCC and back into the phy and controller. > + - resets: a list of phandles and reset controller specifier pairs, > + one for each entry in reset-names. > + - reset-names: must be "phy" for reset of phy block, > + "common" for phy common block reset, > + "cfg" for phy's ahb cfg block reset (Optional). > + "port<port-number>" for reset specific to > + each port/lane (Optional). > + - vdda-phy-supply: Phandle to a regulator supply to PHY core block. > + - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block. > + > +Optional properties: > + - vddp-ref-clk-supply: Phandle to a regulator supply to any specific refclk > + pll block. > + > +Example: > + pcie_phy: pciephy@34000 { pcie-phy or just phy as the node name? -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html
WARNING: multiple messages have this Message-ID (diff)
From: Stephen Boyd <sboyd@codeaurora.org> To: Vivek Gautam <vivek.gautam@codeaurora.org> Cc: kishon@ti.com, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, srinivas.kandagatla@linaro.org, linux-arm-msm@vger.kernel.org Subject: Re: [PATCH v2 3/4] dt-bindings: phy: Add support for QMP phy Date: Mon, 28 Nov 2016 14:55:43 -0800 [thread overview] Message-ID: <20161128225543.GM6095@codeaurora.org> (raw) In-Reply-To: <1479816163-5260-4-git-send-email-vivek.gautam@codeaurora.org> On 11/22, Vivek Gautam wrote: > diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt > new file mode 100644 > index 0000000..ffb173b > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt > @@ -0,0 +1,74 @@ > +Qualcomm QMP PHY > +---------------- > + > +QMP phy controller supports physical layer functionality for a number of > +controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB. > + > +Required properties: > + - compatible: compatible list, contains: > + "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996, > + "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996. > + - reg: list of offset and length pair of the PHY register sets. > + at index 0: offset and length of register set for PHY common > + serdes block. > + from index 1 - N: offset and length of register set for each lane, > + for N number of phy lanes (ports). > + - lane-offsets: array of offsets to tx, rx and pcs blocks for phy lanes. > + - #phy-cells: must be 1 > + - Cell after phy phandle should be the port (lane) number. > + - clocks: a list of phandles and clock-specifier pairs, > + one for each entry in clock-names. > + - clock-names: must be "cfg_ahb" for phy config clock, > + "aux" for phy aux clock, > + "ref_clk" for 19.2 MHz ref clk, > + "ref_clk_src" for reference clock source, We typically leave "clk" out of clk names because it's redundant. > + "pipe<port-number>" for pipe clock specific to > + each port/lane (Optional). The pipe clocks are orphaned right now. We should add an output clock from the phy to go into the controller and back into the phy if I recall correctly. The phy should be a clock provider itself so it can output the pipe clock source into GCC and back into the phy and controller. > + - resets: a list of phandles and reset controller specifier pairs, > + one for each entry in reset-names. > + - reset-names: must be "phy" for reset of phy block, > + "common" for phy common block reset, > + "cfg" for phy's ahb cfg block reset (Optional). > + "port<port-number>" for reset specific to > + each port/lane (Optional). > + - vdda-phy-supply: Phandle to a regulator supply to PHY core block. > + - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block. > + > +Optional properties: > + - vddp-ref-clk-supply: Phandle to a regulator supply to any specific refclk > + pll block. > + > +Example: > + pcie_phy: pciephy@34000 { pcie-phy or just phy as the node name? -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2016-11-28 22:55 UTC|newest] Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top 2016-11-22 12:02 [PATCH v2 0/4] phy: USB and PCIe phy drivers for Qcom chipsets Vivek Gautam 2016-11-22 12:02 ` [PATCH v2 1/4] dt-bindings: phy: Add support for QUSB2 phy Vivek Gautam 2016-11-28 14:19 ` Rob Herring 2016-11-29 5:20 ` Vivek Gautam [not found] ` <1479816163-5260-2-git-send-email-vivek.gautam-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> 2016-11-28 22:49 ` Stephen Boyd 2016-11-28 22:49 ` Stephen Boyd 2016-11-29 5:22 ` Vivek Gautam 2016-11-22 12:02 ` [PATCH v2 2/4] phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips Vivek Gautam [not found] ` <1479816163-5260-3-git-send-email-vivek.gautam-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> 2016-11-28 23:14 ` Stephen Boyd 2016-11-28 23:14 ` Stephen Boyd [not found] ` <20161128231424.GN6095-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> 2016-12-01 8:42 ` Vivek Gautam 2016-12-01 8:42 ` Vivek Gautam 2016-12-02 18:47 ` Stephen Boyd 2016-12-06 8:11 ` Vivek Gautam 2016-11-22 12:02 ` [PATCH v2 3/4] dt-bindings: phy: Add support for QMP phy Vivek Gautam [not found] ` <1479816163-5260-4-git-send-email-vivek.gautam-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> 2016-11-28 22:55 ` Stephen Boyd [this message] 2016-11-28 22:55 ` Stephen Boyd 2016-11-29 5:25 ` Vivek Gautam 2016-11-30 19:12 ` Stephen Boyd [not found] ` <20161128225543.GM6095-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> 2016-12-12 16:40 ` Vivek Gautam 2016-12-12 16:40 ` Vivek Gautam 2016-11-28 23:19 ` Stephen Boyd 2016-12-13 9:18 ` Vivek Gautam 2016-11-22 12:02 ` [PATCH v2 4/4] phy: qcom-qmp: new qmp phy driver for qcom-chipsets Vivek Gautam 2016-11-29 0:35 ` Stephen Boyd 2016-12-20 5:42 ` Vivek Gautam
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