* [PATCH 0/8] HuC Loading Patches @ 2016-11-30 23:31 Anusha Srivatsa 2016-11-30 23:31 ` [PATCH 1/8] drm/i915/guc: Make the GuC fw loading helper functions general Anusha Srivatsa ` (8 more replies) 0 siblings, 9 replies; 43+ messages in thread From: Anusha Srivatsa @ 2016-11-30 23:31 UTC (permalink / raw) To: intel-gfx These patches add HuC loading support. The GuC is required to authenticate the HuC. The userspace patches that check for a fully loaded HuC firmware and use it can be found at: https://lists.freedesktop.org/archives/libva/2016-September/004554.html https://lists.freedesktop.org/archives/libva/2016-September/004555.html More information regarding the HuC, batch commands that configure the HuC etc can be found at- https://01.org/sites/default/files/documentation/intel-gfx-prm-osrc-skl-vol02a-commandreference-instructions-huc.pdf https://www.x.org/docs/intel/CHV/intel-gfx-prm-osrc-chv-bsw-vol10-hevc.pdf v2: rebased. v3: rebased. Changed the code following the review comments. v4: Added action_lock initialization fix provided by Arek (Hiler Arkadiusz) to the first patch in the series- Make the GuC fw loading helper functions general. v5: rebased on top of drm-tip. The patch series is now in sync with GuC code reorganization efforts by Arek- https://patchwork.freedesktop.org/series/15896/ Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Arek <arkadiusz.hiler@intel.com> Cc: Jeff Mcgee <jeff.mcgee@intel.com> Anusha Srivatsa (2): drm/i915/huc: Add BXT HuC Loading Support drm/i915/HuC: Add KBL huC loading Support Peter Antoine (6): drm/i915/guc: Make the GuC fw loading helper functions general drm/i915/huc: Unified css_header struct for GuC and HuC drm/i914/huc: Add HuC fw loading support drm/i915/huc: Add debugfs for HuC loading status check drm/i915/huc: Support HuC authentication drm/i915/get_params: Add HuC status to getparams drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/i915_debugfs.c | 43 +++- drivers/gpu/drm/i915/i915_drv.c | 9 +- drivers/gpu/drm/i915/i915_drv.h | 4 +- drivers/gpu/drm/i915/i915_guc_reg.h | 3 + drivers/gpu/drm/i915/i915_guc_submission.c | 67 ++++++- drivers/gpu/drm/i915/intel_guc_fwif.h | 22 ++- drivers/gpu/drm/i915/intel_guc_loader.c | 196 +++++++++--------- drivers/gpu/drm/i915/intel_huc.h | 43 ++++ drivers/gpu/drm/i915/intel_huc_loader.c | 306 +++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_uc.h | 47 +++-- include/uapi/drm/i915_drm.h | 1 + 12 files changed, 620 insertions(+), 122 deletions(-) create mode 100644 drivers/gpu/drm/i915/intel_huc.h create mode 100644 drivers/gpu/drm/i915/intel_huc_loader.c -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH 1/8] drm/i915/guc: Make the GuC fw loading helper functions general 2016-11-30 23:31 [PATCH 0/8] HuC Loading Patches Anusha Srivatsa @ 2016-11-30 23:31 ` Anusha Srivatsa 2016-11-30 23:31 ` [PATCH 2/8] drm/i915/huc: Unified css_header struct for GuC and HuC Anusha Srivatsa ` (7 subsequent siblings) 8 siblings, 0 replies; 43+ messages in thread From: Anusha Srivatsa @ 2016-11-30 23:31 UTC (permalink / raw) To: intel-gfx; +Cc: Alex Dai, Peter Antoine From: Peter Antoine <peter.antoine@intel.com> Rename some of the GuC fw loading code to make them more general. We will utilise them for HuC loading as well. s/intel_guc_fw/intel_uc_fw/g s/GUC_FIRMWARE/UC_FIRMWARE/g Struct intel_guc_fw is renamed to intel_uc_fw. Prefix of tts members, such as 'guc' or 'guc_fw' either is renamed to 'uc' or removed for same purpose. v2: rebased on top of nightly. reapplied the search/replace as upstream code as changed. v3: rebased again on drm-nightly. v4: removed G from messages in shared fw fetch function. v5: rebased. v7: rebased. v8: rebased. v9: rebased. v10: rebased. v11: rebased. v12: rebased on top of drm-tip Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Alex Dai <yu.dai@intel.com> Signed-off-by: Peter Antoine <peter.antoine@intel.com> Reviewed-by: Dave Gordon <david.s.gordon@intel.com> Reviewed-by: Jeff McGee <jeff.mcgee@intel.com> Reviewed-by: Carlos Santa <carlos.santa@intel.com> Tested-by: Carlos Santa <carlos.santa@intel.com> --- drivers/gpu/drm/i915/i915_debugfs.c | 12 +-- drivers/gpu/drm/i915/i915_guc_submission.c | 4 +- drivers/gpu/drm/i915/intel_guc_loader.c | 155 +++++++++++++++-------------- drivers/gpu/drm/i915/intel_uc.h | 40 ++++---- 4 files changed, 107 insertions(+), 104 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 2434130..d6efda9 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -2337,7 +2337,7 @@ static int i915_llc(struct seq_file *m, void *data) static int i915_guc_load_status_info(struct seq_file *m, void *data) { struct drm_i915_private *dev_priv = node_to_i915(m->private); - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw; + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw; u32 tmp, i; if (!HAS_GUC_UCODE(dev_priv)) @@ -2345,15 +2345,15 @@ static int i915_guc_load_status_info(struct seq_file *m, void *data) seq_printf(m, "GuC firmware status:\n"); seq_printf(m, "\tpath: %s\n", - guc_fw->guc_fw_path); + guc_fw->uc_fw_path); seq_printf(m, "\tfetch: %s\n", - intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status)); + intel_uc_fw_status_repr(guc_fw->fetch_status)); seq_printf(m, "\tload: %s\n", - intel_guc_fw_status_repr(guc_fw->guc_fw_load_status)); + intel_uc_fw_status_repr(guc_fw->load_status)); seq_printf(m, "\tversion wanted: %d.%d\n", - guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted); + guc_fw->major_ver_wanted, guc_fw->minor_ver_wanted); seq_printf(m, "\tversion found: %d.%d\n", - guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found); + guc_fw->major_ver_found, guc_fw->minor_ver_found); seq_printf(m, "\theader: offset is %d; size = %d\n", guc_fw->header_offset, guc_fw->header_size); seq_printf(m, "\tuCode: offset is %d; size = %d\n", diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c index 5841380..4bae8e4 100644 --- a/drivers/gpu/drm/i915/i915_guc_submission.c +++ b/drivers/gpu/drm/i915/i915_guc_submission.c @@ -1494,7 +1494,7 @@ int intel_guc_suspend(struct drm_device *dev) struct i915_gem_context *ctx; u32 data[3]; - if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS) + if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS) return 0; gen9_disable_guc_interrupts(dev_priv); @@ -1522,7 +1522,7 @@ int intel_guc_resume(struct drm_device *dev) struct i915_gem_context *ctx; u32 data[3]; - if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS) + if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS) return 0; if (i915.guc_log_level >= 0) diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c index a330fa4..e55ec2c 100644 --- a/drivers/gpu/drm/i915/intel_guc_loader.c +++ b/drivers/gpu/drm/i915/intel_guc_loader.c @@ -81,16 +81,16 @@ MODULE_FIRMWARE(I915_BXT_GUC_UCODE); MODULE_FIRMWARE(I915_KBL_GUC_UCODE); /* User-friendly representation of an enum */ -const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status) +const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status) { switch (status) { - case GUC_FIRMWARE_FAIL: + case UC_FIRMWARE_FAIL: return "FAIL"; - case GUC_FIRMWARE_NONE: + case UC_FIRMWARE_NONE: return "NONE"; - case GUC_FIRMWARE_PENDING: + case UC_FIRMWARE_PENDING: return "PENDING"; - case GUC_FIRMWARE_SUCCESS: + case UC_FIRMWARE_SUCCESS: return "SUCCESS"; default: return "UNKNOWN!"; @@ -278,7 +278,7 @@ static inline bool guc_ucode_response(struct drm_i915_private *dev_priv, static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv, struct i915_vma *vma) { - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw; + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw; unsigned long offset; struct sg_table *sg = vma->pages; u32 status, rsa[UOS_RSA_SCRATCH_MAX_COUNT]; @@ -350,17 +350,17 @@ static u32 guc_wopcm_size(struct drm_i915_private *dev_priv) */ static int guc_ucode_xfer(struct drm_i915_private *dev_priv) { - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw; + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw; struct i915_vma *vma; int ret; - ret = i915_gem_object_set_to_gtt_domain(guc_fw->guc_fw_obj, false); + ret = i915_gem_object_set_to_gtt_domain(guc_fw->uc_fw_obj, false); if (ret) { DRM_DEBUG_DRIVER("set-domain failed %d\n", ret); return ret; } - vma = i915_gem_object_ggtt_pin(guc_fw->guc_fw_obj, NULL, 0, 0, 0); + vma = i915_gem_object_ggtt_pin(guc_fw->uc_fw_obj, NULL, 0, 0, 0); if (IS_ERR(vma)) { DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma)); return PTR_ERR(vma); @@ -451,14 +451,14 @@ static int guc_hw_reset(struct drm_i915_private *dev_priv) int intel_guc_setup(struct drm_device *dev) { struct drm_i915_private *dev_priv = to_i915(dev); - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw; - const char *fw_path = guc_fw->guc_fw_path; + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw; + const char *fw_path = guc_fw->uc_fw_path; int retries, ret, err; DRM_DEBUG_DRIVER("GuC fw status: path %s, fetch %s, load %s\n", fw_path, - intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status), - intel_guc_fw_status_repr(guc_fw->guc_fw_load_status)); + intel_uc_fw_status_repr(guc_fw->fetch_status), + intel_uc_fw_status_repr(guc_fw->load_status)); /* Loading forbidden, or no firmware to load? */ if (!i915.enable_guc_loading) { @@ -476,10 +476,10 @@ int intel_guc_setup(struct drm_device *dev) } /* Fetch failed, or already fetched but failed to load? */ - if (guc_fw->guc_fw_fetch_status != GUC_FIRMWARE_SUCCESS) { + if (guc_fw->fetch_status != UC_FIRMWARE_SUCCESS) { err = -EIO; goto fail; - } else if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_FAIL) { + } else if (guc_fw->load_status == UC_FIRMWARE_FAIL) { err = -ENOEXEC; goto fail; } @@ -487,11 +487,11 @@ int intel_guc_setup(struct drm_device *dev) guc_interrupts_release(dev_priv); gen9_reset_guc_interrupts(dev_priv); - guc_fw->guc_fw_load_status = GUC_FIRMWARE_PENDING; + guc_fw->load_status = UC_FIRMWARE_PENDING; DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n", - intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status), - intel_guc_fw_status_repr(guc_fw->guc_fw_load_status)); + intel_uc_fw_status_repr(guc_fw->fetch_status), + intel_uc_fw_status_repr(guc_fw->load_status)); err = i915_guc_submission_init(dev_priv); if (err) @@ -523,11 +523,11 @@ int intel_guc_setup(struct drm_device *dev) "retry %d more time(s)\n", err, retries); } - guc_fw->guc_fw_load_status = GUC_FIRMWARE_SUCCESS; + guc_fw->load_status = UC_FIRMWARE_SUCCESS; DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n", - intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status), - intel_guc_fw_status_repr(guc_fw->guc_fw_load_status)); + intel_uc_fw_status_repr(guc_fw->fetch_status), + intel_uc_fw_status_repr(guc_fw->load_status)); if (i915.enable_guc_submission) { if (i915.guc_log_level >= 0) @@ -542,8 +542,8 @@ int intel_guc_setup(struct drm_device *dev) return 0; fail: - if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_PENDING) - guc_fw->guc_fw_load_status = GUC_FIRMWARE_FAIL; + if (guc_fw->load_status == UC_FIRMWARE_PENDING) + guc_fw->load_status = UC_FIRMWARE_FAIL; guc_interrupts_release(dev_priv); i915_guc_submission_disable(dev_priv); @@ -588,7 +588,7 @@ int intel_guc_setup(struct drm_device *dev) return ret; } -static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw) +void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw) { struct pci_dev *pdev = dev->pdev; struct drm_i915_gem_object *obj; @@ -597,17 +597,17 @@ static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw) size_t size; int err; - DRM_DEBUG_DRIVER("before requesting firmware: GuC fw fetch status %s\n", - intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status)); + DRM_DEBUG_DRIVER("before requesting firmware: uC fw fetch status %s\n", + intel_uc_fw_status_repr(uc_fw->fetch_status)); - err = request_firmware(&fw, guc_fw->guc_fw_path, &pdev->dev); + err = request_firmware(&fw, uc_fw->uc_fw_path, &pdev->dev); if (err) goto fail; if (!fw) goto fail; - DRM_DEBUG_DRIVER("fetch GuC fw from %s succeeded, fw %p\n", - guc_fw->guc_fw_path, fw); + DRM_DEBUG_DRIVER("fetch uC fw from %s succeeded, fw %p\n", + uc_fw->uc_fw_path, fw); /* Check the size of the blob before examining buffer contents */ if (fw->size < sizeof(struct guc_css_header)) { @@ -618,36 +618,36 @@ static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw) css = (struct guc_css_header *)fw->data; /* Firmware bits always start from header */ - guc_fw->header_offset = 0; - guc_fw->header_size = (css->header_size_dw - css->modulus_size_dw - + uc_fw->header_offset = 0; + uc_fw->header_size = (css->header_size_dw - css->modulus_size_dw - css->key_size_dw - css->exponent_size_dw) * sizeof(u32); - if (guc_fw->header_size != sizeof(struct guc_css_header)) { + if (uc_fw->header_size != sizeof(struct guc_css_header)) { DRM_NOTE("CSS header definition mismatch\n"); goto fail; } /* then, uCode */ - guc_fw->ucode_offset = guc_fw->header_offset + guc_fw->header_size; - guc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32); + uc_fw->ucode_offset = uc_fw->header_offset + uc_fw->header_size; + uc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32); /* now RSA */ if (css->key_size_dw != UOS_RSA_SCRATCH_MAX_COUNT) { DRM_NOTE("RSA key size is bad\n"); goto fail; } - guc_fw->rsa_offset = guc_fw->ucode_offset + guc_fw->ucode_size; - guc_fw->rsa_size = css->key_size_dw * sizeof(u32); + uc_fw->rsa_offset = uc_fw->ucode_offset + uc_fw->ucode_size; + uc_fw->rsa_size = css->key_size_dw * sizeof(u32); /* At least, it should have header, uCode and RSA. Size of all three. */ - size = guc_fw->header_size + guc_fw->ucode_size + guc_fw->rsa_size; + size = uc_fw->header_size + uc_fw->ucode_size + uc_fw->rsa_size; if (fw->size < size) { DRM_NOTE("Missing firmware components\n"); goto fail; } /* Header and uCode will be loaded to WOPCM. Size of the two. */ - size = guc_fw->header_size + guc_fw->ucode_size; + size = uc_fw->header_size + uc_fw->ucode_size; if (size > guc_wopcm_size(to_i915(dev))) { DRM_NOTE("Firmware is too large to fit in WOPCM\n"); goto fail; @@ -659,21 +659,21 @@ static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw) * TWO bytes each (i.e. u16), although all pointers and offsets are defined * in terms of bytes (u8). */ - guc_fw->guc_fw_major_found = css->guc_sw_version >> 16; - guc_fw->guc_fw_minor_found = css->guc_sw_version & 0xFFFF; - - if (guc_fw->guc_fw_major_found != guc_fw->guc_fw_major_wanted || - guc_fw->guc_fw_minor_found < guc_fw->guc_fw_minor_wanted) { - DRM_NOTE("GuC firmware version %d.%d, required %d.%d\n", - guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found, - guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted); + uc_fw->major_ver_found = css->guc_sw_version >> 16; + uc_fw->minor_ver_found = css->guc_sw_version & 0xFFFF; + + if (uc_fw->major_ver_found != uc_fw->major_ver_wanted || + uc_fw->minor_ver_found < uc_fw->minor_ver_wanted) { + DRM_NOTE("uC firmware version %d.%d, required %d.%d\n", + uc_fw->major_ver_found, uc_fw->minor_ver_found, + uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted); err = -ENOEXEC; goto fail; } DRM_DEBUG_DRIVER("firmware version %d.%d OK (minimum %d.%d)\n", - guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found, - guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted); + uc_fw->major_ver_found, uc_fw->minor_ver_found, + uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted); mutex_lock(&dev->struct_mutex); obj = i915_gem_object_create_from_data(dev, fw->data, fw->size); @@ -683,31 +683,31 @@ static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw) goto fail; } - guc_fw->guc_fw_obj = obj; - guc_fw->guc_fw_size = fw->size; + uc_fw->uc_fw_obj = obj; + uc_fw->uc_fw_size = fw->size; - DRM_DEBUG_DRIVER("GuC fw fetch status SUCCESS, obj %p\n", - guc_fw->guc_fw_obj); + DRM_DEBUG_DRIVER("uC fw fetch status SUCCESS, obj %p\n", + uc_fw->uc_fw_obj); release_firmware(fw); - guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_SUCCESS; + uc_fw->fetch_status = UC_FIRMWARE_SUCCESS; return; fail: - DRM_WARN("Failed to fetch valid GuC firmware from %s (error %d)\n", - guc_fw->guc_fw_path, err); - DRM_DEBUG_DRIVER("GuC fw fetch status FAIL; err %d, fw %p, obj %p\n", - err, fw, guc_fw->guc_fw_obj); + DRM_WARN("Failed to fetch valid uC firmware from %s (error %d)\n", + uc_fw->uc_fw_path, err); + DRM_DEBUG_DRIVER("uC fw fetch status FAIL; err %d, fw %p, obj %p\n", + err, fw, uc_fw->uc_fw_obj); mutex_lock(&dev->struct_mutex); - obj = guc_fw->guc_fw_obj; + obj = uc_fw->uc_fw_obj; if (obj) i915_gem_object_put(obj); - guc_fw->guc_fw_obj = NULL; + uc_fw->uc_fw_obj = NULL; mutex_unlock(&dev->struct_mutex); release_firmware(fw); /* OK even if fw is NULL */ - guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL; + uc_fw->fetch_status = UC_FIRMWARE_FAIL; } /** @@ -722,7 +722,7 @@ static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw) void intel_guc_init(struct drm_device *dev) { struct drm_i915_private *dev_priv = to_i915(dev); - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw; + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw; const char *fw_path; if (!HAS_GUC(dev_priv)) { @@ -740,23 +740,24 @@ void intel_guc_init(struct drm_device *dev) fw_path = NULL; } else if (IS_SKYLAKE(dev_priv)) { fw_path = I915_SKL_GUC_UCODE; - guc_fw->guc_fw_major_wanted = SKL_FW_MAJOR; - guc_fw->guc_fw_minor_wanted = SKL_FW_MINOR; + guc_fw->major_ver_wanted = SKL_FW_MAJOR; + guc_fw->minor_ver_wanted = SKL_FW_MINOR; } else if (IS_BROXTON(dev_priv)) { fw_path = I915_BXT_GUC_UCODE; - guc_fw->guc_fw_major_wanted = BXT_FW_MAJOR; - guc_fw->guc_fw_minor_wanted = BXT_FW_MINOR; + guc_fw->major_ver_wanted = BXT_FW_MAJOR; + guc_fw->minor_ver_wanted = BXT_FW_MINOR; } else if (IS_KABYLAKE(dev_priv)) { fw_path = I915_KBL_GUC_UCODE; - guc_fw->guc_fw_major_wanted = KBL_FW_MAJOR; - guc_fw->guc_fw_minor_wanted = KBL_FW_MINOR; + guc_fw->major_ver_wanted = KBL_FW_MAJOR; + guc_fw->minor_ver_wanted = KBL_FW_MINOR; } else { fw_path = ""; /* unknown device */ } - guc_fw->guc_fw_path = fw_path; - guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE; - guc_fw->guc_fw_load_status = GUC_FIRMWARE_NONE; + guc_fw->uc_dev = dev; + guc_fw->uc_fw_path = fw_path; + guc_fw->fetch_status = UC_FIRMWARE_NONE; + guc_fw->load_status = UC_FIRMWARE_NONE; /* Early (and silent) return if GuC loading is disabled */ if (!i915.enable_guc_loading) @@ -766,9 +767,9 @@ void intel_guc_init(struct drm_device *dev) if (*fw_path == '\0') return; - guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_PENDING; + guc_fw->fetch_status = UC_FIRMWARE_PENDING; DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path); - guc_fw_fetch(dev, guc_fw); + intel_uc_fw_fetch(dev, guc_fw); /* status must now be FAIL or SUCCESS */ } @@ -779,17 +780,17 @@ void intel_guc_init(struct drm_device *dev) void intel_guc_fini(struct drm_device *dev) { struct drm_i915_private *dev_priv = to_i915(dev); - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw; + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw; mutex_lock(&dev->struct_mutex); guc_interrupts_release(dev_priv); i915_guc_submission_disable(dev_priv); i915_guc_submission_fini(dev_priv); - if (guc_fw->guc_fw_obj) - i915_gem_object_put(guc_fw->guc_fw_obj); - guc_fw->guc_fw_obj = NULL; + if (guc_fw->uc_fw_obj) + i915_gem_object_put(guc_fw->uc_fw_obj); + guc_fw->uc_fw_obj = NULL; mutex_unlock(&dev->struct_mutex); - guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE; + guc_fw->fetch_status = UC_FIRMWARE_NONE; } diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h index 8507a8f..a1c771f 100644 --- a/drivers/gpu/drm/i915/intel_uc.h +++ b/drivers/gpu/drm/i915/intel_uc.h @@ -91,29 +91,31 @@ struct i915_guc_client { uint64_t submissions[I915_NUM_ENGINES]; }; -enum intel_guc_fw_status { - GUC_FIRMWARE_FAIL = -1, - GUC_FIRMWARE_NONE = 0, - GUC_FIRMWARE_PENDING, - GUC_FIRMWARE_SUCCESS +enum intel_uc_fw_status { + UC_FIRMWARE_FAIL = -1, + UC_FIRMWARE_NONE = 0, + UC_FIRMWARE_PENDING, + UC_FIRMWARE_SUCCESS }; /* * This structure encapsulates all the data needed during the process * of fetching, caching, and loading the firmware image into the GuC. */ -struct intel_guc_fw { - const char * guc_fw_path; - size_t guc_fw_size; - struct drm_i915_gem_object * guc_fw_obj; - enum intel_guc_fw_status guc_fw_fetch_status; - enum intel_guc_fw_status guc_fw_load_status; - - uint16_t guc_fw_major_wanted; - uint16_t guc_fw_minor_wanted; - uint16_t guc_fw_major_found; - uint16_t guc_fw_minor_found; - +struct intel_uc_fw { + struct drm_device *uc_dev; + const char *uc_fw_path; + size_t uc_fw_size; + struct drm_i915_gem_object *uc_fw_obj; + enum intel_uc_fw_status fetch_status; + enum intel_uc_fw_status load_status; + + uint16_t major_ver_wanted; + uint16_t minor_ver_wanted; + uint16_t major_ver_found; + uint16_t minor_ver_found; + + uint32_t fw_type; uint32_t header_size; uint32_t header_offset; uint32_t rsa_size; @@ -139,7 +141,7 @@ struct intel_guc_log { }; struct intel_guc { - struct intel_guc_fw guc_fw; + struct intel_uc_fw guc_fw; struct intel_guc_log log; /* intel_guc_recv interrupt related state */ @@ -181,7 +183,7 @@ int intel_guc_log_control(struct intel_guc *guc, u32 control_val); extern void intel_guc_init(struct drm_device *dev); extern int intel_guc_setup(struct drm_device *dev); extern void intel_guc_fini(struct drm_device *dev); -extern const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status); +extern const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status); extern int intel_guc_suspend(struct drm_device *dev); extern int intel_guc_resume(struct drm_device *dev); -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH 2/8] drm/i915/huc: Unified css_header struct for GuC and HuC 2016-11-30 23:31 [PATCH 0/8] HuC Loading Patches Anusha Srivatsa 2016-11-30 23:31 ` [PATCH 1/8] drm/i915/guc: Make the GuC fw loading helper functions general Anusha Srivatsa @ 2016-11-30 23:31 ` Anusha Srivatsa 2016-12-01 12:22 ` Arkadiusz Hiler 2016-11-30 23:31 ` [PATCH 3/8] drm/i915/huc: Add HuC fw loading support Anusha Srivatsa ` (6 subsequent siblings) 8 siblings, 1 reply; 43+ messages in thread From: Anusha Srivatsa @ 2016-11-30 23:31 UTC (permalink / raw) To: intel-gfx; +Cc: Alex Dai, Peter Antoine From: Peter Antoine <peter.antoine@intel.com> HuC firmware css header has almost exactly same definition as GuC firmware except for the sw_version. Also, add a new member fw_type into intel_uc_fw to indicate what kind of fw it is. So, the loader will pull right sw_version from header. v2: rebased on-top of drm-intel-nightly v3: rebased on-top of drm-intel-nightly (again). v4: rebased + spaces. v7: rebased. v8: rebased. v9: rebased. Rename device_id to guc_branch_client_version, make guc_sw_version a union. <Jeff Mcgee>. Put UC_FW_TYPE_GUC and UC_FW_TYPE_HUC into an enum. v10: rebased. v11: rebased. v12: rebased on top of drm-tip. Tested-by: Xiang Haihao <haihao.xiang@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Alex Dai <yu.dai@intel.com> Signed-off-by: Peter Antoine <peter.antoine@intel.com> Reviewed-by: Dave Gordon <david.s.gordon@intel.com> Reviewed-by: Jeff McGee <jeff.mcgee@intel.com> --- drivers/gpu/drm/i915/intel_guc_fwif.h | 21 +++++++++++++---- drivers/gpu/drm/i915/intel_guc_loader.c | 41 ++++++++++++++++++++++----------- drivers/gpu/drm/i915/intel_uc.h | 5 ++++ 3 files changed, 50 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h index 00ca0df..c07d9da 100644 --- a/drivers/gpu/drm/i915/intel_guc_fwif.h +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h @@ -154,7 +154,7 @@ * The GuC firmware layout looks like this: * * +-------------------------------+ - * | guc_css_header | + * | uc_css_header | * | | * | contains major/minor version | * +-------------------------------+ @@ -181,9 +181,16 @@ * 3. Length info of each component can be found in header, in dwords. * 4. Modulus and exponent key are not required by driver. They may not appear * in fw. So driver will load a truncated firmware in this case. + * + * HuC firmware layout is same as GuC firmware. + * + * HuC firmware css header is different. However, the only difference is where + * the version information is saved. The uc_css_header is unified to support + * both. Driver should get HuC version from uc_css_header.huc_sw_version, while + * uc_css_header.guc_sw_version for GuC. */ -struct guc_css_header { +struct uc_css_header { uint32_t module_type; /* header_size includes all non-uCode bits, including css_header, rsa * key, modulus key and exponent data. */ @@ -214,8 +221,14 @@ struct guc_css_header { char username[8]; char buildnumber[12]; - uint32_t device_id; - uint32_t guc_sw_version; + union { + uint32_t guc_branch_client_version; + uint32_t huc_sw_version; + }; + union { + uint32_t guc_sw_version; + uint32_t huc_reserved; + }; uint32_t prod_preprod_fw; uint32_t reserved[12]; uint32_t header_info; diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c index e55ec2c..557d4b4 100644 --- a/drivers/gpu/drm/i915/intel_guc_loader.c +++ b/drivers/gpu/drm/i915/intel_guc_loader.c @@ -593,7 +593,7 @@ void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw) struct pci_dev *pdev = dev->pdev; struct drm_i915_gem_object *obj; const struct firmware *fw = NULL; - struct guc_css_header *css; + struct uc_css_header *css; size_t size; int err; @@ -610,19 +610,19 @@ void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw) uc_fw->uc_fw_path, fw); /* Check the size of the blob before examining buffer contents */ - if (fw->size < sizeof(struct guc_css_header)) { + if (fw->size < sizeof(struct uc_css_header)) { DRM_NOTE("Firmware header is missing\n"); goto fail; } - css = (struct guc_css_header *)fw->data; + css = (struct uc_css_header *)fw->data; /* Firmware bits always start from header */ uc_fw->header_offset = 0; uc_fw->header_size = (css->header_size_dw - css->modulus_size_dw - css->key_size_dw - css->exponent_size_dw) * sizeof(u32); - if (uc_fw->header_size != sizeof(struct guc_css_header)) { + if (uc_fw->header_size != sizeof(struct uc_css_header)) { DRM_NOTE("CSS header definition mismatch\n"); goto fail; } @@ -646,21 +646,36 @@ void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw) goto fail; } - /* Header and uCode will be loaded to WOPCM. Size of the two. */ - size = uc_fw->header_size + uc_fw->ucode_size; - if (size > guc_wopcm_size(to_i915(dev))) { - DRM_NOTE("Firmware is too large to fit in WOPCM\n"); - goto fail; - } - /* * The GuC firmware image has the version number embedded at a well-known * offset within the firmware blob; note that major / minor version are * TWO bytes each (i.e. u16), although all pointers and offsets are defined * in terms of bytes (u8). */ - uc_fw->major_ver_found = css->guc_sw_version >> 16; - uc_fw->minor_ver_found = css->guc_sw_version & 0xFFFF; + switch (uc_fw->fw_type) { + case UC_FW_TYPE_GUC: + /* Header and uCode will be loaded to WOPCM. Size of the two. */ + size = uc_fw->header_size + uc_fw->ucode_size; + + /* Top 32k of WOPCM is reserved (8K stack + 24k RC6 context). */ + if (size > guc_wopcm_size(to_i915(dev))) { + DRM_ERROR("Firmware is too large to fit in WOPCM\n"); + goto fail; + } + uc_fw->major_ver_found = css->guc_sw_version >> 16; + uc_fw->minor_ver_found = css->guc_sw_version & 0xFFFF; + break; + + case UC_FW_TYPE_HUC: + uc_fw->major_ver_found = css->huc_sw_version >> 16; + uc_fw->minor_ver_found = css->huc_sw_version & 0xFFFF; + break; + + default: + DRM_ERROR("Unknown firmware type %d\n", uc_fw->fw_type); + err = -ENOEXEC; + goto fail; + } if (uc_fw->major_ver_found != uc_fw->major_ver_wanted || uc_fw->minor_ver_found < uc_fw->minor_ver_wanted) { diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h index a1c771f..1616cac 100644 --- a/drivers/gpu/drm/i915/intel_uc.h +++ b/drivers/gpu/drm/i915/intel_uc.h @@ -98,6 +98,11 @@ enum intel_uc_fw_status { UC_FIRMWARE_SUCCESS }; +enum { + UC_FW_TYPE_GUC, + UC_FW_TYPE_HUC +}; + /* * This structure encapsulates all the data needed during the process * of fetching, caching, and loading the firmware image into the GuC. -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 43+ messages in thread
* Re: [PATCH 2/8] drm/i915/huc: Unified css_header struct for GuC and HuC 2016-11-30 23:31 ` [PATCH 2/8] drm/i915/huc: Unified css_header struct for GuC and HuC Anusha Srivatsa @ 2016-12-01 12:22 ` Arkadiusz Hiler 2016-12-01 18:22 ` Srivatsa, Anusha 0 siblings, 1 reply; 43+ messages in thread From: Arkadiusz Hiler @ 2016-12-01 12:22 UTC (permalink / raw) To: Anusha Srivatsa; +Cc: intel-gfx On Wed, Nov 30, 2016 at 03:31:28PM -0800, Anusha Srivatsa wrote: > From: Peter Antoine <peter.antoine@intel.com> > > HuC firmware css header has almost exactly same definition as GuC > firmware except for the sw_version. Also, add a new member fw_type > into intel_uc_fw to indicate what kind of fw it is. So, the loader > will pull right sw_version from header. > > v2: rebased on-top of drm-intel-nightly > v3: rebased on-top of drm-intel-nightly (again). > v4: rebased + spaces. > v7: rebased. > v8: rebased. > v9: rebased. Rename device_id to guc_branch_client_version, > make guc_sw_version a union. <Jeff Mcgee>. Put UC_FW_TYPE_GUC > and UC_FW_TYPE_HUC into an enum. > v10: rebased. > v11: rebased. > v12: rebased on top of drm-tip. > > Tested-by: Xiang Haihao <haihao.xiang@intel.com> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> > Signed-off-by: Alex Dai <yu.dai@intel.com> > Signed-off-by: Peter Antoine <peter.antoine@intel.com> > Reviewed-by: Dave Gordon <david.s.gordon@intel.com> > Reviewed-by: Jeff McGee <jeff.mcgee@intel.com> > --- > drivers/gpu/drm/i915/intel_guc_fwif.h | 21 +++++++++++++---- > drivers/gpu/drm/i915/intel_guc_loader.c | 41 ++++++++++++++++++++++----------- > drivers/gpu/drm/i915/intel_uc.h | 5 ++++ > 3 files changed, 50 insertions(+), 17 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h > index 00ca0df..c07d9da 100644 > --- a/drivers/gpu/drm/i915/intel_guc_fwif.h > +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h > @@ -154,7 +154,7 @@ > * The GuC firmware layout looks like this: > * > * +-------------------------------+ > - * | guc_css_header | > + * | uc_css_header | > * | | > * | contains major/minor version | > * +-------------------------------+ > @@ -181,9 +181,16 @@ > * 3. Length info of each component can be found in header, in dwords. > * 4. Modulus and exponent key are not required by driver. They may not appear > * in fw. So driver will load a truncated firmware in this case. > + * > + * HuC firmware layout is same as GuC firmware. > + * > + * HuC firmware css header is different. However, the only difference is where > + * the version information is saved. The uc_css_header is unified to support > + * both. Driver should get HuC version from uc_css_header.huc_sw_version, while > + * uc_css_header.guc_sw_version for GuC. > */ > > -struct guc_css_header { > +struct uc_css_header { I think we should either move most of this stuff to intel_uc.{c,h} or rename the file to intel_uc_fwif.h. Anyway, this file contains information on top that this is automatically generated and your changes might be lost... The file was introduced and then *manually edited* *multiple times* by *many people*, without any signs of changes lost or file being regenerated. I think we can, at least, drop the warning. I am in favor of drooping the file completely though. If something would change, we can assume it would be done by hand anyway. Jeff, Sagar: any thought on that? > uint32_t module_type; > /* header_size includes all non-uCode bits, including css_header, rsa > * key, modulus key and exponent data. */ > @@ -214,8 +221,14 @@ struct guc_css_header { > > char username[8]; > char buildnumber[12]; > - uint32_t device_id; > - uint32_t guc_sw_version; > + union { > + uint32_t guc_branch_client_version; > + uint32_t huc_sw_version; > + }; > + union { > + uint32_t guc_sw_version; > + uint32_t huc_reserved; > + }; > uint32_t prod_preprod_fw; > uint32_t reserved[12]; > uint32_t header_info; > diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c > index e55ec2c..557d4b4 100644 > --- a/drivers/gpu/drm/i915/intel_guc_loader.c > +++ b/drivers/gpu/drm/i915/intel_guc_loader.c > @@ -593,7 +593,7 @@ void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw) > struct pci_dev *pdev = dev->pdev; > struct drm_i915_gem_object *obj; > const struct firmware *fw = NULL; > - struct guc_css_header *css; > + struct uc_css_header *css; > size_t size; > int err; > > @@ -610,19 +610,19 @@ void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw) > uc_fw->uc_fw_path, fw); > > /* Check the size of the blob before examining buffer contents */ > - if (fw->size < sizeof(struct guc_css_header)) { > + if (fw->size < sizeof(struct uc_css_header)) { > DRM_NOTE("Firmware header is missing\n"); > goto fail; > } > > - css = (struct guc_css_header *)fw->data; > + css = (struct uc_css_header *)fw->data; > > /* Firmware bits always start from header */ > uc_fw->header_offset = 0; > uc_fw->header_size = (css->header_size_dw - css->modulus_size_dw - > css->key_size_dw - css->exponent_size_dw) * sizeof(u32); > > - if (uc_fw->header_size != sizeof(struct guc_css_header)) { > + if (uc_fw->header_size != sizeof(struct uc_css_header)) { > DRM_NOTE("CSS header definition mismatch\n"); > goto fail; > } > @@ -646,21 +646,36 @@ void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw) > goto fail; > } > > - /* Header and uCode will be loaded to WOPCM. Size of the two. */ > - size = uc_fw->header_size + uc_fw->ucode_size; > - if (size > guc_wopcm_size(to_i915(dev))) { > - DRM_NOTE("Firmware is too large to fit in WOPCM\n"); > - goto fail; > - } > - > /* > * The GuC firmware image has the version number embedded at a well-known > * offset within the firmware blob; note that major / minor version are > * TWO bytes each (i.e. u16), although all pointers and offsets are defined > * in terms of bytes (u8). > */ > - uc_fw->major_ver_found = css->guc_sw_version >> 16; > - uc_fw->minor_ver_found = css->guc_sw_version & 0xFFFF; > + switch (uc_fw->fw_type) { > + case UC_FW_TYPE_GUC: > + /* Header and uCode will be loaded to WOPCM. Size of the two. */ > + size = uc_fw->header_size + uc_fw->ucode_size; > + > + /* Top 32k of WOPCM is reserved (8K stack + 24k RC6 context). */ > + if (size > guc_wopcm_size(to_i915(dev))) { > + DRM_ERROR("Firmware is too large to fit in WOPCM\n"); > + goto fail; > + } > + uc_fw->major_ver_found = css->guc_sw_version >> 16; > + uc_fw->minor_ver_found = css->guc_sw_version & 0xFFFF; > + break; > + > + case UC_FW_TYPE_HUC: > + uc_fw->major_ver_found = css->huc_sw_version >> 16; > + uc_fw->minor_ver_found = css->huc_sw_version & 0xFFFF; > + break; > + > + default: > + DRM_ERROR("Unknown firmware type %d\n", uc_fw->fw_type); > + err = -ENOEXEC; > + goto fail; > + } > > if (uc_fw->major_ver_found != uc_fw->major_ver_wanted || > uc_fw->minor_ver_found < uc_fw->minor_ver_wanted) { > diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h > index a1c771f..1616cac 100644 > --- a/drivers/gpu/drm/i915/intel_uc.h > +++ b/drivers/gpu/drm/i915/intel_uc.h > @@ -98,6 +98,11 @@ enum intel_uc_fw_status { > UC_FIRMWARE_SUCCESS > }; > > +enum { > + UC_FW_TYPE_GUC, > + UC_FW_TYPE_HUC > +}; > + > /* > * This structure encapsulates all the data needed during the process > * of fetching, caching, and loading the firmware image into the GuC. > -- > 2.7.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Cheers, Arek _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH 2/8] drm/i915/huc: Unified css_header struct for GuC and HuC 2016-12-01 12:22 ` Arkadiusz Hiler @ 2016-12-01 18:22 ` Srivatsa, Anusha 0 siblings, 0 replies; 43+ messages in thread From: Srivatsa, Anusha @ 2016-12-01 18:22 UTC (permalink / raw) To: Hiler, Arkadiusz; +Cc: intel-gfx >-----Original Message----- >From: Hiler, Arkadiusz >Sent: Thursday, December 1, 2016 4:23 AM >To: Srivatsa, Anusha <anusha.srivatsa@intel.com> >Cc: intel-gfx@lists.freedesktop.org; Mcgee, Jeff <jeff.mcgee@intel.com>; >Kamble, Sagar A <sagar.a.kamble@intel.com> >Subject: Re: [Intel-gfx] [PATCH 2/8] drm/i915/huc: Unified css_header struct for >GuC and HuC > >On Wed, Nov 30, 2016 at 03:31:28PM -0800, Anusha Srivatsa wrote: >> From: Peter Antoine <peter.antoine@intel.com> >> >> HuC firmware css header has almost exactly same definition as GuC >> firmware except for the sw_version. Also, add a new member fw_type >> into intel_uc_fw to indicate what kind of fw it is. So, the loader >> will pull right sw_version from header. >> >> v2: rebased on-top of drm-intel-nightly >> v3: rebased on-top of drm-intel-nightly (again). >> v4: rebased + spaces. >> v7: rebased. >> v8: rebased. >> v9: rebased. Rename device_id to guc_branch_client_version, make >> guc_sw_version a union. <Jeff Mcgee>. Put UC_FW_TYPE_GUC and >> UC_FW_TYPE_HUC into an enum. >> v10: rebased. >> v11: rebased. >> v12: rebased on top of drm-tip. >> >> Tested-by: Xiang Haihao <haihao.xiang@intel.com> >> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> >> Signed-off-by: Alex Dai <yu.dai@intel.com> >> Signed-off-by: Peter Antoine <peter.antoine@intel.com> >> Reviewed-by: Dave Gordon <david.s.gordon@intel.com> >> Reviewed-by: Jeff McGee <jeff.mcgee@intel.com> >> --- >> drivers/gpu/drm/i915/intel_guc_fwif.h | 21 +++++++++++++---- >> drivers/gpu/drm/i915/intel_guc_loader.c | 41 ++++++++++++++++++++++------- >---- >> drivers/gpu/drm/i915/intel_uc.h | 5 ++++ >> 3 files changed, 50 insertions(+), 17 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h >> b/drivers/gpu/drm/i915/intel_guc_fwif.h >> index 00ca0df..c07d9da 100644 >> --- a/drivers/gpu/drm/i915/intel_guc_fwif.h >> +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h >> @@ -154,7 +154,7 @@ >> * The GuC firmware layout looks like this: >> * >> * +-------------------------------+ >> - * | guc_css_header | >> + * | uc_css_header | >> * | | >> * | contains major/minor version | >> * +-------------------------------+ >> @@ -181,9 +181,16 @@ >> * 3. Length info of each component can be found in header, in dwords. >> * 4. Modulus and exponent key are not required by driver. They may not >appear >> * in fw. So driver will load a truncated firmware in this case. >> + * >> + * HuC firmware layout is same as GuC firmware. >> + * >> + * HuC firmware css header is different. However, the only difference >> + is where >> + * the version information is saved. The uc_css_header is unified to >> + support >> + * both. Driver should get HuC version from >> + uc_css_header.huc_sw_version, while >> + * uc_css_header.guc_sw_version for GuC. >> */ >> >> -struct guc_css_header { >> +struct uc_css_header { > >I think we should either move most of this stuff to intel_uc.{c,h} or rename the >file to intel_uc_fwif.h. > >Anyway, this file contains information on top that this is automatically generated >and your changes might be lost... > >The file was introduced and then *manually edited* *multiple times* by *many >people*, without any signs of changes lost or file being regenerated. > >I think we can, at least, drop the warning. I am in favor of drooping the file >completely though. So, basically move all these struct and union declarations to intel_uc.h? >If something would change, we can assume it would be done by hand anyway. > >Jeff, Sagar: any thought on that? > >> uint32_t module_type; >> /* header_size includes all non-uCode bits, including css_header, rsa >> * key, modulus key and exponent data. */ @@ -214,8 +221,14 @@ >> struct guc_css_header { >> >> char username[8]; >> char buildnumber[12]; >> - uint32_t device_id; >> - uint32_t guc_sw_version; >> + union { >> + uint32_t guc_branch_client_version; >> + uint32_t huc_sw_version; >> + }; >> + union { >> + uint32_t guc_sw_version; >> + uint32_t huc_reserved; >> + }; >> uint32_t prod_preprod_fw; >> uint32_t reserved[12]; >> uint32_t header_info; >> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c >> b/drivers/gpu/drm/i915/intel_guc_loader.c >> index e55ec2c..557d4b4 100644 >> --- a/drivers/gpu/drm/i915/intel_guc_loader.c >> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c >> @@ -593,7 +593,7 @@ void intel_uc_fw_fetch(struct drm_device *dev, struct >intel_uc_fw *uc_fw) >> struct pci_dev *pdev = dev->pdev; >> struct drm_i915_gem_object *obj; >> const struct firmware *fw = NULL; >> - struct guc_css_header *css; >> + struct uc_css_header *css; >> size_t size; >> int err; >> >> @@ -610,19 +610,19 @@ void intel_uc_fw_fetch(struct drm_device *dev, >struct intel_uc_fw *uc_fw) >> uc_fw->uc_fw_path, fw); >> >> /* Check the size of the blob before examining buffer contents */ >> - if (fw->size < sizeof(struct guc_css_header)) { >> + if (fw->size < sizeof(struct uc_css_header)) { >> DRM_NOTE("Firmware header is missing\n"); >> goto fail; >> } >> >> - css = (struct guc_css_header *)fw->data; >> + css = (struct uc_css_header *)fw->data; >> >> /* Firmware bits always start from header */ >> uc_fw->header_offset = 0; >> uc_fw->header_size = (css->header_size_dw - css->modulus_size_dw - >> css->key_size_dw - css->exponent_size_dw) * sizeof(u32); >> >> - if (uc_fw->header_size != sizeof(struct guc_css_header)) { >> + if (uc_fw->header_size != sizeof(struct uc_css_header)) { >> DRM_NOTE("CSS header definition mismatch\n"); >> goto fail; >> } >> @@ -646,21 +646,36 @@ void intel_uc_fw_fetch(struct drm_device *dev, >struct intel_uc_fw *uc_fw) >> goto fail; >> } >> >> - /* Header and uCode will be loaded to WOPCM. Size of the two. */ >> - size = uc_fw->header_size + uc_fw->ucode_size; >> - if (size > guc_wopcm_size(to_i915(dev))) { >> - DRM_NOTE("Firmware is too large to fit in WOPCM\n"); >> - goto fail; >> - } >> - >> /* >> * The GuC firmware image has the version number embedded at a well- >known >> * offset within the firmware blob; note that major / minor version are >> * TWO bytes each (i.e. u16), although all pointers and offsets are defined >> * in terms of bytes (u8). >> */ >> - uc_fw->major_ver_found = css->guc_sw_version >> 16; >> - uc_fw->minor_ver_found = css->guc_sw_version & 0xFFFF; >> + switch (uc_fw->fw_type) { >> + case UC_FW_TYPE_GUC: >> + /* Header and uCode will be loaded to WOPCM. Size of the two. >*/ >> + size = uc_fw->header_size + uc_fw->ucode_size; >> + >> + /* Top 32k of WOPCM is reserved (8K stack + 24k RC6 context). >*/ >> + if (size > guc_wopcm_size(to_i915(dev))) { >> + DRM_ERROR("Firmware is too large to fit in >WOPCM\n"); >> + goto fail; >> + } >> + uc_fw->major_ver_found = css->guc_sw_version >> 16; >> + uc_fw->minor_ver_found = css->guc_sw_version & 0xFFFF; >> + break; >> + >> + case UC_FW_TYPE_HUC: >> + uc_fw->major_ver_found = css->huc_sw_version >> 16; >> + uc_fw->minor_ver_found = css->huc_sw_version & 0xFFFF; >> + break; >> + >> + default: >> + DRM_ERROR("Unknown firmware type %d\n", uc_fw->fw_type); >> + err = -ENOEXEC; >> + goto fail; >> + } >> >> if (uc_fw->major_ver_found != uc_fw->major_ver_wanted || >> uc_fw->minor_ver_found < uc_fw->minor_ver_wanted) { diff --git >> a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h >> index a1c771f..1616cac 100644 >> --- a/drivers/gpu/drm/i915/intel_uc.h >> +++ b/drivers/gpu/drm/i915/intel_uc.h >> @@ -98,6 +98,11 @@ enum intel_uc_fw_status { >> UC_FIRMWARE_SUCCESS >> }; >> >> +enum { >> + UC_FW_TYPE_GUC, >> + UC_FW_TYPE_HUC >> +}; >> + >> /* >> * This structure encapsulates all the data needed during the process >> * of fetching, caching, and loading the firmware image into the GuC. >> -- >> 2.7.4 >> >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx@lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx > >-- >Cheers, >Arek _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH 3/8] drm/i915/huc: Add HuC fw loading support 2016-11-30 23:31 [PATCH 0/8] HuC Loading Patches Anusha Srivatsa 2016-11-30 23:31 ` [PATCH 1/8] drm/i915/guc: Make the GuC fw loading helper functions general Anusha Srivatsa 2016-11-30 23:31 ` [PATCH 2/8] drm/i915/huc: Unified css_header struct for GuC and HuC Anusha Srivatsa @ 2016-11-30 23:31 ` Anusha Srivatsa 2016-12-01 13:24 ` Tvrtko Ursulin 2016-11-30 23:31 ` [PATCH 4/8] drm/i915/huc: Add BXT HuC Loading Support Anusha Srivatsa ` (5 subsequent siblings) 8 siblings, 1 reply; 43+ messages in thread From: Anusha Srivatsa @ 2016-11-30 23:31 UTC (permalink / raw) To: intel-gfx; +Cc: Alex Dai, Peter Antoine The HuC loading process is similar to GuC. The intel_uc_fw_fetch() is used for both cases. HuC loading needs to be before GuC loading. The WOPCM setting must be done early before loading any of them. v2: rebased on-top of drm-intel-nightly. removed if(HAS_GUC()) before the guc call. (D.Gordon) update huc_version number of format. v3: rebased to drm-intel-nightly, changed the file name format to match the one in the huc package. Changed dev->dev_private to to_i915() v4: moved function back to where it was. change wait_for_atomic to wait_for. v5: rebased + comment changes. v7: rebased. v8: rebased. v9: rebased. Changed the year in the copyright message to reflect the right year.Correct the comments,remove the unwanted WARN message, replace drm_gem_object_unreference() with i915_gem_object_put().Make the prototypes in intel_huc.h non-extern. v10: rebased. Update the file construction done by HuC. It is similar to GuC.Adopted the approach used in- https://patchwork.freedesktop.org/patch/104355/ <Tvrtko Ursulin> v11: Fix warnings remove old declaration v12: Change dev to dev_priv in macro definition. Corrected comments. v13: rebased. v14: rebased on top of drm-tip Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Tested-by: Xiang Haihao <haihao.xiang@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Alex Dai <yu.dai@intel.com> Signed-off-by: Peter Antoine <peter.antoine@intel.com> Reviewed-by: Dave Gordon <david.s.gordon@intel.com> --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/i915_drv.c | 4 +- drivers/gpu/drm/i915/i915_drv.h | 4 +- drivers/gpu/drm/i915/i915_guc_reg.h | 3 + drivers/gpu/drm/i915/intel_guc_loader.c | 6 +- drivers/gpu/drm/i915/intel_huc.h | 42 +++++ drivers/gpu/drm/i915/intel_huc_loader.c | 267 ++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_uc.h | 2 + 8 files changed, 324 insertions(+), 5 deletions(-) create mode 100644 drivers/gpu/drm/i915/intel_huc.h create mode 100644 drivers/gpu/drm/i915/intel_huc_loader.c diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 3c30916..01d4f4b 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -57,6 +57,7 @@ i915-y += i915_cmd_parser.o \ # general-purpose microcontroller (GuC) support i915-y += intel_uc.o \ intel_guc_loader.o \ + intel_huc_loader.o \ i915_guc_submission.o # autogenerated null render state diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 8dac298..075d9ce 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -603,6 +603,7 @@ static int i915_load_modeset_init(struct drm_device *dev) if (ret) goto cleanup_irq; + intel_huc_init(dev); intel_guc_init(dev); ret = i915_gem_init(dev); @@ -630,6 +631,7 @@ static int i915_load_modeset_init(struct drm_device *dev) DRM_ERROR("failed to idle hardware; continuing to unload!\n"); i915_gem_fini(dev_priv); cleanup_irq: + intel_huc_fini(dev); intel_guc_fini(dev); drm_irq_uninstall(dev); intel_teardown_gmbus(dev); @@ -1326,7 +1328,7 @@ void i915_driver_unload(struct drm_device *dev) /* Flush any outstanding unpin_work. */ drain_workqueue(dev_priv->wq); - + intel_huc_fini(dev); intel_guc_fini(dev); i915_gem_fini(dev_priv); intel_fbc_cleanup_cfb(dev_priv); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 297ad03..8edfae6 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -56,6 +56,7 @@ #include "intel_bios.h" #include "intel_dpll_mgr.h" #include "intel_uc.h" +#include "intel_huc.h" #include "intel_lrc.h" #include "intel_ringbuffer.h" @@ -1933,6 +1934,7 @@ struct drm_i915_private { struct intel_gvt *gvt; + struct intel_huc huc; struct intel_guc guc; struct intel_csr csr; @@ -2698,7 +2700,7 @@ intel_info(const struct drm_i915_private *dev_priv) #define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc) #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv)) #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv)) - +#define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv)) #define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer) #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu) diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h b/drivers/gpu/drm/i915/i915_guc_reg.h index 5e638fc..f9829f6 100644 --- a/drivers/gpu/drm/i915/i915_guc_reg.h +++ b/drivers/gpu/drm/i915/i915_guc_reg.h @@ -61,9 +61,12 @@ #define DMA_ADDRESS_SPACE_GTT (8 << 16) #define DMA_COPY_SIZE _MMIO(0xc310) #define DMA_CTRL _MMIO(0xc314) +#define HUC_UKERNEL (1<<9) #define UOS_MOVE (1<<4) #define START_DMA (1<<0) #define DMA_GUC_WOPCM_OFFSET _MMIO(0xc340) +#define HUC_LOADING_AGENT_VCR (0<<1) +#define HUC_LOADING_AGENT_GUC (1<<1) #define GUC_WOPCM_OFFSET_VALUE 0x80000 /* 512KB */ #define GUC_MAX_IDLE_COUNT _MMIO(0xC3E4) diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c index 557d4b4..7ca5556 100644 --- a/drivers/gpu/drm/i915/intel_guc_loader.c +++ b/drivers/gpu/drm/i915/intel_guc_loader.c @@ -309,8 +309,8 @@ static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv, I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM); /* Finally start the DMA */ - I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA)); - + I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA) | + _MASKED_BIT_DISABLE(HUC_UKERNEL)); /* * Wait for the DMA to complete & the GuC to start up. * NB: Docs recommend not using the interrupt for completion. @@ -334,7 +334,7 @@ static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv, return ret; } -static u32 guc_wopcm_size(struct drm_i915_private *dev_priv) +u32 guc_wopcm_size(struct drm_i915_private *dev_priv) { u32 wopcm_size = GUC_WOPCM_TOP; diff --git a/drivers/gpu/drm/i915/intel_huc.h b/drivers/gpu/drm/i915/intel_huc.h new file mode 100644 index 0000000..1dd18c5 --- /dev/null +++ b/drivers/gpu/drm/i915/intel_huc.h @@ -0,0 +1,42 @@ +/* + * Copyright © 2016 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + */ +#ifndef _INTEL_HUC_H_ +#define _INTEL_HUC_H_ + +#include "intel_uc.h" + +#define HUC_STATUS2 _MMIO(0xD3B0) +#define HUC_FW_VERIFIED (1<<7) + +struct intel_huc { + /* Generic uC firmware management */ + struct intel_uc_fw huc_fw; + + /* HuC-specific additions */ +}; + +void intel_huc_init(struct drm_device *dev); +void intel_huc_fini(struct drm_device *dev); +int intel_huc_load(struct drm_device *dev); +#endif diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c new file mode 100644 index 0000000..663fcc4 --- /dev/null +++ b/drivers/gpu/drm/i915/intel_huc_loader.c @@ -0,0 +1,267 @@ +/* + * Copyright © 2016 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + */ +#include <linux/firmware.h> +#include "i915_drv.h" +#include "intel_huc.h" + +/** + * DOC: HuC Firmware + * + * Motivation: + * GEN9 introduces a new dedicated firmware for usage in media HEVC (High + * Efficiency Video Coding) operations. Userspace can use the firmware + * capabilities by adding HuC specific commands to batch buffers. + * + * Implementation: + * The same firmware loader is used as the GuC. However, the actual + * loading to HW is deferred until GEM initialization is done. + * + * Note that HuC firmware loading must be done before GuC loading. + */ + +#define SKL_FW_MAJOR 01 +#define SKL_FW_MINOR 07 +#define SKL_BLD_NUM 1398 + +#define HUC_FW_PATH(platform, major, minor, bld_num) \ + "i915/" __stringify(platform) "_huc_ver" __stringify(major) "_" \ + __stringify(minor) "_" __stringify(bld_num) ".bin" + +#define I915_SKL_HUC_UCODE HUC_FW_PATH(skl, SKL_FW_MAJOR, \ + SKL_FW_MINOR, SKL_BLD_NUM) +MODULE_FIRMWARE(I915_SKL_HUC_UCODE); + +/** + * huc_ucode_xfer() - DMA's the firmware + * @dev_priv: the drm device + * + * This function takes the gem object containing the firmware, sets up the DMA + * engine MMIO, triggers the DMA operation and waits for it to finish. + * + * Transfer the firmware image to RAM for execution by the microcontroller. + * + * Return: 0 on success, non-zero on failure + */ + +static int huc_ucode_xfer(struct drm_i915_private *dev_priv) +{ + struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw; + struct i915_vma *vma; + unsigned long offset = 0; + u32 size; + int ret; + + ret = i915_gem_object_set_to_gtt_domain(huc_fw->uc_fw_obj, false); + if (ret) { + DRM_DEBUG_DRIVER("set-domain failed %d\n", ret); + return ret; + } + + vma = i915_gem_object_ggtt_pin(huc_fw->uc_fw_obj, NULL, 0, 0, 0); + if (IS_ERR(vma)) { + DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma)); + return PTR_ERR(vma); + } + + /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */ + I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); + + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); + + /* init WOPCM */ + I915_WRITE(GUC_WOPCM_SIZE, guc_wopcm_size(dev_priv)); + I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE | + HUC_LOADING_AGENT_GUC); + + /* Set the source address for the uCode */ + offset = i915_ggtt_offset(vma) + huc_fw->header_offset; + I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset)); + I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF); + + /* Hardware doesn't look at destination address for HuC. Set it to 0, + * but still program the correct address space. + */ + I915_WRITE(DMA_ADDR_1_LOW, 0); + I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM); + + size = huc_fw->header_size + huc_fw->ucode_size; + I915_WRITE(DMA_COPY_SIZE, size); + + /* Start the DMA */ + I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(HUC_UKERNEL | START_DMA)); + + /* Wait for DMA to finish */ + ret = wait_for((I915_READ(DMA_CTRL) & START_DMA) == 0, 100); + + DRM_DEBUG_DRIVER("HuC DMA transfer wait over with ret %d\n", ret); + + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); + + /* + * We keep the object pages for reuse during resume. But we can unpin it + * now that DMA has completed, so it doesn't continue to take up space. + */ + i915_vma_unpin(vma); + + return ret; +} + +/** + * intel_huc_init() - initiate HuC firmware loading request + * @dev: the drm device + * + * Called early during driver load, but after GEM is initialised. The loading + * will continue only when driver explicitly specify firmware name and version. + * All other cases are considered as UC_FIRMWARE_NONE either because HW is not + * capable or driver yet support it. And there will be no error message for + * UC_FIRMWARE_NONE cases. + * + * The DMA-copying to HW is done later when intel_huc_load() is called. + */ +void intel_huc_init(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_huc *huc = &dev_priv->huc; + struct intel_uc_fw *huc_fw = &huc->huc_fw; + const char *fw_path = NULL; + + huc_fw->uc_dev = dev; + huc_fw->uc_fw_path = NULL; + huc_fw->fetch_status = UC_FIRMWARE_NONE; + huc_fw->load_status = UC_FIRMWARE_NONE; + huc_fw->fw_type = UC_FW_TYPE_HUC; + + if (!HAS_HUC_UCODE(dev_priv)) + return; + + if (IS_SKYLAKE(dev_priv)) { + fw_path = I915_SKL_HUC_UCODE; + huc_fw->major_ver_wanted = SKL_FW_MAJOR; + huc_fw->minor_ver_wanted = SKL_FW_MINOR; + } + + huc_fw->uc_fw_path = fw_path; + huc_fw->fetch_status = UC_FIRMWARE_PENDING; + + DRM_DEBUG_DRIVER("HuC firmware pending, path %s\n", fw_path); + + intel_uc_fw_fetch(dev, huc_fw); +} + +/** + * intel_huc_load() - load HuC uCode to device + * @dev: the drm device + * + * Called from gem_init_hw() during driver loading and also after a GPU reset. + * Be note that HuC loading must be done before GuC loading. + * + * The firmware image should have already been fetched into memory by the + * earlier call to intel_huc_init(), so here we need only check that + * is succeeded, and then transfer the image to the h/w. + * + * Return: non-zero code on error + */ +int intel_huc_load(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw; + int err; + + if (huc_fw->fetch_status == UC_FIRMWARE_NONE) + return 0; + + DRM_DEBUG_DRIVER("%s fw status: fetch %s, load %s\n", + huc_fw->uc_fw_path, + intel_uc_fw_status_repr(huc_fw->fetch_status), + intel_uc_fw_status_repr(huc_fw->load_status)); + + if (huc_fw->fetch_status == UC_FIRMWARE_SUCCESS && + huc_fw->load_status == UC_FIRMWARE_FAIL) + return -ENOEXEC; + + huc_fw->load_status = UC_FIRMWARE_PENDING; + + switch (huc_fw->fetch_status) { + case UC_FIRMWARE_FAIL: + /* something went wrong :( */ + err = -EIO; + goto fail; + + case UC_FIRMWARE_NONE: + case UC_FIRMWARE_PENDING: + default: + /* "can't happen" */ + WARN_ONCE(1, "HuC fw %s invalid fetch_status %s [%d]\n", + huc_fw->uc_fw_path, + intel_uc_fw_status_repr(huc_fw->fetch_status), + huc_fw->fetch_status); + err = -ENXIO; + goto fail; + + case UC_FIRMWARE_SUCCESS: + break; + } + + err = huc_ucode_xfer(dev_priv); + if (err) + goto fail; + + huc_fw->load_status = UC_FIRMWARE_SUCCESS; + + DRM_DEBUG_DRIVER("%s fw status: fetch %s, load %s\n", + huc_fw->uc_fw_path, + intel_uc_fw_status_repr(huc_fw->fetch_status), + intel_uc_fw_status_repr(huc_fw->load_status)); + + return 0; + +fail: + if (huc_fw->load_status == UC_FIRMWARE_PENDING) + huc_fw->load_status = UC_FIRMWARE_FAIL; + + DRM_ERROR("Failed to complete HuC uCode load with ret %d\n", err); + + return err; +} + +/** + * intel_huc_fini() - clean up resources allocated for HuC + * @dev: the drm device + * + * Cleans up by releasing the huc firmware GEM obj. + */ +void intel_huc_fini(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw; + + mutex_lock(&dev->struct_mutex); + if (huc_fw->uc_fw_obj) + i915_gem_object_put(huc_fw->uc_fw_obj); + huc_fw->uc_fw_obj = NULL; + mutex_unlock(&dev->struct_mutex); + + huc_fw->fetch_status = UC_FIRMWARE_NONE; +} + diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h index 1616cac..9321225 100644 --- a/drivers/gpu/drm/i915/intel_uc.h +++ b/drivers/gpu/drm/i915/intel_uc.h @@ -191,6 +191,8 @@ extern void intel_guc_fini(struct drm_device *dev); extern const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status); extern int intel_guc_suspend(struct drm_device *dev); extern int intel_guc_resume(struct drm_device *dev); +void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw); +u32 guc_wopcm_size(struct drm_i915_private *dev_priv); /* i915_guc_submission.c */ int i915_guc_submission_init(struct drm_i915_private *dev_priv); -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 43+ messages in thread
* Re: [PATCH 3/8] drm/i915/huc: Add HuC fw loading support 2016-11-30 23:31 ` [PATCH 3/8] drm/i915/huc: Add HuC fw loading support Anusha Srivatsa @ 2016-12-01 13:24 ` Tvrtko Ursulin 2016-12-01 17:18 ` Srivatsa, Anusha 0 siblings, 1 reply; 43+ messages in thread From: Tvrtko Ursulin @ 2016-12-01 13:24 UTC (permalink / raw) To: Anusha Srivatsa, intel-gfx Hi, On 30/11/2016 23:31, Anusha Srivatsa wrote: > The HuC loading process is similar to GuC. The intel_uc_fw_fetch() > is used for both cases. > > HuC loading needs to be before GuC loading. The WOPCM setting must > be done early before loading any of them. > > v2: rebased on-top of drm-intel-nightly. > removed if(HAS_GUC()) before the guc call. (D.Gordon) > update huc_version number of format. > v3: rebased to drm-intel-nightly, changed the file name format to > match the one in the huc package. > Changed dev->dev_private to to_i915() > v4: moved function back to where it was. > change wait_for_atomic to wait_for. > v5: rebased + comment changes. > v7: rebased. > v8: rebased. > v9: rebased. Changed the year in the copyright message to reflect > the right year.Correct the comments,remove the unwanted WARN message, > replace drm_gem_object_unreference() with i915_gem_object_put().Make the > prototypes in intel_huc.h non-extern. > v10: rebased. Update the file construction done by HuC. It is similar to > GuC.Adopted the approach used in- > https://patchwork.freedesktop.org/patch/104355/ <Tvrtko Ursulin> > v11: Fix warnings remove old declaration > v12: Change dev to dev_priv in macro definition. > Corrected comments. > v13: rebased. > v14: rebased on top of drm-tip I thought we basically agreed to add i915.enable_huc (default=yes) and hide i915.enable_guc_loading, making it automatically turn on if either huc or guc submission are enabled? Regards, Tvrtko > > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > Tested-by: Xiang Haihao <haihao.xiang@intel.com> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> > Signed-off-by: Alex Dai <yu.dai@intel.com> > Signed-off-by: Peter Antoine <peter.antoine@intel.com> > Reviewed-by: Dave Gordon <david.s.gordon@intel.com> > --- > drivers/gpu/drm/i915/Makefile | 1 + > drivers/gpu/drm/i915/i915_drv.c | 4 +- > drivers/gpu/drm/i915/i915_drv.h | 4 +- > drivers/gpu/drm/i915/i915_guc_reg.h | 3 + > drivers/gpu/drm/i915/intel_guc_loader.c | 6 +- > drivers/gpu/drm/i915/intel_huc.h | 42 +++++ > drivers/gpu/drm/i915/intel_huc_loader.c | 267 ++++++++++++++++++++++++++++++++ > drivers/gpu/drm/i915/intel_uc.h | 2 + > 8 files changed, 324 insertions(+), 5 deletions(-) > create mode 100644 drivers/gpu/drm/i915/intel_huc.h > create mode 100644 drivers/gpu/drm/i915/intel_huc_loader.c > > diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile > index 3c30916..01d4f4b 100644 > --- a/drivers/gpu/drm/i915/Makefile > +++ b/drivers/gpu/drm/i915/Makefile > @@ -57,6 +57,7 @@ i915-y += i915_cmd_parser.o \ > # general-purpose microcontroller (GuC) support > i915-y += intel_uc.o \ > intel_guc_loader.o \ > + intel_huc_loader.o \ > i915_guc_submission.o > > # autogenerated null render state > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c > index 8dac298..075d9ce 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -603,6 +603,7 @@ static int i915_load_modeset_init(struct drm_device *dev) > if (ret) > goto cleanup_irq; > > + intel_huc_init(dev); > intel_guc_init(dev); > > ret = i915_gem_init(dev); > @@ -630,6 +631,7 @@ static int i915_load_modeset_init(struct drm_device *dev) > DRM_ERROR("failed to idle hardware; continuing to unload!\n"); > i915_gem_fini(dev_priv); > cleanup_irq: > + intel_huc_fini(dev); > intel_guc_fini(dev); > drm_irq_uninstall(dev); > intel_teardown_gmbus(dev); > @@ -1326,7 +1328,7 @@ void i915_driver_unload(struct drm_device *dev) > > /* Flush any outstanding unpin_work. */ > drain_workqueue(dev_priv->wq); > - > + intel_huc_fini(dev); > intel_guc_fini(dev); > i915_gem_fini(dev_priv); > intel_fbc_cleanup_cfb(dev_priv); > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 297ad03..8edfae6 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -56,6 +56,7 @@ > #include "intel_bios.h" > #include "intel_dpll_mgr.h" > #include "intel_uc.h" > +#include "intel_huc.h" > #include "intel_lrc.h" > #include "intel_ringbuffer.h" > > @@ -1933,6 +1934,7 @@ struct drm_i915_private { > > struct intel_gvt *gvt; > > + struct intel_huc huc; > struct intel_guc guc; > > struct intel_csr csr; > @@ -2698,7 +2700,7 @@ intel_info(const struct drm_i915_private *dev_priv) > #define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc) > #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv)) > #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv)) > - > +#define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv)) > #define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer) > > #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu) > diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h b/drivers/gpu/drm/i915/i915_guc_reg.h > index 5e638fc..f9829f6 100644 > --- a/drivers/gpu/drm/i915/i915_guc_reg.h > +++ b/drivers/gpu/drm/i915/i915_guc_reg.h > @@ -61,9 +61,12 @@ > #define DMA_ADDRESS_SPACE_GTT (8 << 16) > #define DMA_COPY_SIZE _MMIO(0xc310) > #define DMA_CTRL _MMIO(0xc314) > +#define HUC_UKERNEL (1<<9) > #define UOS_MOVE (1<<4) > #define START_DMA (1<<0) > #define DMA_GUC_WOPCM_OFFSET _MMIO(0xc340) > +#define HUC_LOADING_AGENT_VCR (0<<1) > +#define HUC_LOADING_AGENT_GUC (1<<1) > #define GUC_WOPCM_OFFSET_VALUE 0x80000 /* 512KB */ > #define GUC_MAX_IDLE_COUNT _MMIO(0xC3E4) > > diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c > index 557d4b4..7ca5556 100644 > --- a/drivers/gpu/drm/i915/intel_guc_loader.c > +++ b/drivers/gpu/drm/i915/intel_guc_loader.c > @@ -309,8 +309,8 @@ static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv, > I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM); > > /* Finally start the DMA */ > - I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA)); > - > + I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA) | > + _MASKED_BIT_DISABLE(HUC_UKERNEL)); > /* > * Wait for the DMA to complete & the GuC to start up. > * NB: Docs recommend not using the interrupt for completion. > @@ -334,7 +334,7 @@ static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv, > return ret; > } > > -static u32 guc_wopcm_size(struct drm_i915_private *dev_priv) > +u32 guc_wopcm_size(struct drm_i915_private *dev_priv) > { > u32 wopcm_size = GUC_WOPCM_TOP; > > diff --git a/drivers/gpu/drm/i915/intel_huc.h b/drivers/gpu/drm/i915/intel_huc.h > new file mode 100644 > index 0000000..1dd18c5 > --- /dev/null > +++ b/drivers/gpu/drm/i915/intel_huc.h > @@ -0,0 +1,42 @@ > +/* > + * Copyright © 2016 Intel Corporation > + * > + * Permission is hereby granted, free of charge, to any person obtaining a > + * copy of this software and associated documentation files (the "Software"), > + * to deal in the Software without restriction, including without limitation > + * the rights to use, copy, modify, merge, publish, distribute, sublicense, > + * and/or sell copies of the Software, and to permit persons to whom the > + * Software is furnished to do so, subject to the following conditions: > + * > + * The above copyright notice and this permission notice (including the next > + * paragraph) shall be included in all copies or substantial portions of the > + * Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS > + * IN THE SOFTWARE. > + * > + */ > +#ifndef _INTEL_HUC_H_ > +#define _INTEL_HUC_H_ > + > +#include "intel_uc.h" > + > +#define HUC_STATUS2 _MMIO(0xD3B0) > +#define HUC_FW_VERIFIED (1<<7) > + > +struct intel_huc { > + /* Generic uC firmware management */ > + struct intel_uc_fw huc_fw; > + > + /* HuC-specific additions */ > +}; > + > +void intel_huc_init(struct drm_device *dev); > +void intel_huc_fini(struct drm_device *dev); > +int intel_huc_load(struct drm_device *dev); > +#endif > diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c > new file mode 100644 > index 0000000..663fcc4 > --- /dev/null > +++ b/drivers/gpu/drm/i915/intel_huc_loader.c > @@ -0,0 +1,267 @@ > +/* > + * Copyright © 2016 Intel Corporation > + * > + * Permission is hereby granted, free of charge, to any person obtaining a > + * copy of this software and associated documentation files (the "Software"), > + * to deal in the Software without restriction, including without limitation > + * the rights to use, copy, modify, merge, publish, distribute, sublicense, > + * and/or sell copies of the Software, and to permit persons to whom the > + * Software is furnished to do so, subject to the following conditions: > + * > + * The above copyright notice and this permission notice (including the next > + * paragraph) shall be included in all copies or substantial portions of the > + * Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS > + * IN THE SOFTWARE. > + * > + */ > +#include <linux/firmware.h> > +#include "i915_drv.h" > +#include "intel_huc.h" > + > +/** > + * DOC: HuC Firmware > + * > + * Motivation: > + * GEN9 introduces a new dedicated firmware for usage in media HEVC (High > + * Efficiency Video Coding) operations. Userspace can use the firmware > + * capabilities by adding HuC specific commands to batch buffers. > + * > + * Implementation: > + * The same firmware loader is used as the GuC. However, the actual > + * loading to HW is deferred until GEM initialization is done. > + * > + * Note that HuC firmware loading must be done before GuC loading. > + */ > + > +#define SKL_FW_MAJOR 01 > +#define SKL_FW_MINOR 07 > +#define SKL_BLD_NUM 1398 > + > +#define HUC_FW_PATH(platform, major, minor, bld_num) \ > + "i915/" __stringify(platform) "_huc_ver" __stringify(major) "_" \ > + __stringify(minor) "_" __stringify(bld_num) ".bin" > + > +#define I915_SKL_HUC_UCODE HUC_FW_PATH(skl, SKL_FW_MAJOR, \ > + SKL_FW_MINOR, SKL_BLD_NUM) > +MODULE_FIRMWARE(I915_SKL_HUC_UCODE); > + > +/** > + * huc_ucode_xfer() - DMA's the firmware > + * @dev_priv: the drm device > + * > + * This function takes the gem object containing the firmware, sets up the DMA > + * engine MMIO, triggers the DMA operation and waits for it to finish. > + * > + * Transfer the firmware image to RAM for execution by the microcontroller. > + * > + * Return: 0 on success, non-zero on failure > + */ > + > +static int huc_ucode_xfer(struct drm_i915_private *dev_priv) > +{ > + struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw; > + struct i915_vma *vma; > + unsigned long offset = 0; > + u32 size; > + int ret; > + > + ret = i915_gem_object_set_to_gtt_domain(huc_fw->uc_fw_obj, false); > + if (ret) { > + DRM_DEBUG_DRIVER("set-domain failed %d\n", ret); > + return ret; > + } > + > + vma = i915_gem_object_ggtt_pin(huc_fw->uc_fw_obj, NULL, 0, 0, 0); > + if (IS_ERR(vma)) { > + DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma)); > + return PTR_ERR(vma); > + } > + > + /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */ > + I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); > + > + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); > + > + /* init WOPCM */ > + I915_WRITE(GUC_WOPCM_SIZE, guc_wopcm_size(dev_priv)); > + I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE | > + HUC_LOADING_AGENT_GUC); > + > + /* Set the source address for the uCode */ > + offset = i915_ggtt_offset(vma) + huc_fw->header_offset; > + I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset)); > + I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF); > + > + /* Hardware doesn't look at destination address for HuC. Set it to 0, > + * but still program the correct address space. > + */ > + I915_WRITE(DMA_ADDR_1_LOW, 0); > + I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM); > + > + size = huc_fw->header_size + huc_fw->ucode_size; > + I915_WRITE(DMA_COPY_SIZE, size); > + > + /* Start the DMA */ > + I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(HUC_UKERNEL | START_DMA)); > + > + /* Wait for DMA to finish */ > + ret = wait_for((I915_READ(DMA_CTRL) & START_DMA) == 0, 100); > + > + DRM_DEBUG_DRIVER("HuC DMA transfer wait over with ret %d\n", ret); > + > + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); > + > + /* > + * We keep the object pages for reuse during resume. But we can unpin it > + * now that DMA has completed, so it doesn't continue to take up space. > + */ > + i915_vma_unpin(vma); > + > + return ret; > +} > + > +/** > + * intel_huc_init() - initiate HuC firmware loading request > + * @dev: the drm device > + * > + * Called early during driver load, but after GEM is initialised. The loading > + * will continue only when driver explicitly specify firmware name and version. > + * All other cases are considered as UC_FIRMWARE_NONE either because HW is not > + * capable or driver yet support it. And there will be no error message for > + * UC_FIRMWARE_NONE cases. > + * > + * The DMA-copying to HW is done later when intel_huc_load() is called. > + */ > +void intel_huc_init(struct drm_device *dev) > +{ > + struct drm_i915_private *dev_priv = to_i915(dev); > + struct intel_huc *huc = &dev_priv->huc; > + struct intel_uc_fw *huc_fw = &huc->huc_fw; > + const char *fw_path = NULL; > + > + huc_fw->uc_dev = dev; > + huc_fw->uc_fw_path = NULL; > + huc_fw->fetch_status = UC_FIRMWARE_NONE; > + huc_fw->load_status = UC_FIRMWARE_NONE; > + huc_fw->fw_type = UC_FW_TYPE_HUC; > + > + if (!HAS_HUC_UCODE(dev_priv)) > + return; > + > + if (IS_SKYLAKE(dev_priv)) { > + fw_path = I915_SKL_HUC_UCODE; > + huc_fw->major_ver_wanted = SKL_FW_MAJOR; > + huc_fw->minor_ver_wanted = SKL_FW_MINOR; > + } > + > + huc_fw->uc_fw_path = fw_path; > + huc_fw->fetch_status = UC_FIRMWARE_PENDING; > + > + DRM_DEBUG_DRIVER("HuC firmware pending, path %s\n", fw_path); > + > + intel_uc_fw_fetch(dev, huc_fw); > +} > + > +/** > + * intel_huc_load() - load HuC uCode to device > + * @dev: the drm device > + * > + * Called from gem_init_hw() during driver loading and also after a GPU reset. > + * Be note that HuC loading must be done before GuC loading. > + * > + * The firmware image should have already been fetched into memory by the > + * earlier call to intel_huc_init(), so here we need only check that > + * is succeeded, and then transfer the image to the h/w. > + * > + * Return: non-zero code on error > + */ > +int intel_huc_load(struct drm_device *dev) > +{ > + struct drm_i915_private *dev_priv = to_i915(dev); > + struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw; > + int err; > + > + if (huc_fw->fetch_status == UC_FIRMWARE_NONE) > + return 0; > + > + DRM_DEBUG_DRIVER("%s fw status: fetch %s, load %s\n", > + huc_fw->uc_fw_path, > + intel_uc_fw_status_repr(huc_fw->fetch_status), > + intel_uc_fw_status_repr(huc_fw->load_status)); > + > + if (huc_fw->fetch_status == UC_FIRMWARE_SUCCESS && > + huc_fw->load_status == UC_FIRMWARE_FAIL) > + return -ENOEXEC; > + > + huc_fw->load_status = UC_FIRMWARE_PENDING; > + > + switch (huc_fw->fetch_status) { > + case UC_FIRMWARE_FAIL: > + /* something went wrong :( */ > + err = -EIO; > + goto fail; > + > + case UC_FIRMWARE_NONE: > + case UC_FIRMWARE_PENDING: > + default: > + /* "can't happen" */ > + WARN_ONCE(1, "HuC fw %s invalid fetch_status %s [%d]\n", > + huc_fw->uc_fw_path, > + intel_uc_fw_status_repr(huc_fw->fetch_status), > + huc_fw->fetch_status); > + err = -ENXIO; > + goto fail; > + > + case UC_FIRMWARE_SUCCESS: > + break; > + } > + > + err = huc_ucode_xfer(dev_priv); > + if (err) > + goto fail; > + > + huc_fw->load_status = UC_FIRMWARE_SUCCESS; > + > + DRM_DEBUG_DRIVER("%s fw status: fetch %s, load %s\n", > + huc_fw->uc_fw_path, > + intel_uc_fw_status_repr(huc_fw->fetch_status), > + intel_uc_fw_status_repr(huc_fw->load_status)); > + > + return 0; > + > +fail: > + if (huc_fw->load_status == UC_FIRMWARE_PENDING) > + huc_fw->load_status = UC_FIRMWARE_FAIL; > + > + DRM_ERROR("Failed to complete HuC uCode load with ret %d\n", err); > + > + return err; > +} > + > +/** > + * intel_huc_fini() - clean up resources allocated for HuC > + * @dev: the drm device > + * > + * Cleans up by releasing the huc firmware GEM obj. > + */ > +void intel_huc_fini(struct drm_device *dev) > +{ > + struct drm_i915_private *dev_priv = to_i915(dev); > + struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw; > + > + mutex_lock(&dev->struct_mutex); > + if (huc_fw->uc_fw_obj) > + i915_gem_object_put(huc_fw->uc_fw_obj); > + huc_fw->uc_fw_obj = NULL; > + mutex_unlock(&dev->struct_mutex); > + > + huc_fw->fetch_status = UC_FIRMWARE_NONE; > +} > + > diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h > index 1616cac..9321225 100644 > --- a/drivers/gpu/drm/i915/intel_uc.h > +++ b/drivers/gpu/drm/i915/intel_uc.h > @@ -191,6 +191,8 @@ extern void intel_guc_fini(struct drm_device *dev); > extern const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status); > extern int intel_guc_suspend(struct drm_device *dev); > extern int intel_guc_resume(struct drm_device *dev); > +void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw); > +u32 guc_wopcm_size(struct drm_i915_private *dev_priv); > > /* i915_guc_submission.c */ > int i915_guc_submission_init(struct drm_i915_private *dev_priv); > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH 3/8] drm/i915/huc: Add HuC fw loading support 2016-12-01 13:24 ` Tvrtko Ursulin @ 2016-12-01 17:18 ` Srivatsa, Anusha 0 siblings, 0 replies; 43+ messages in thread From: Srivatsa, Anusha @ 2016-12-01 17:18 UTC (permalink / raw) To: Tvrtko Ursulin, intel-gfx >-----Original Message----- >From: Tvrtko Ursulin [mailto:tvrtko.ursulin@linux.intel.com] >Sent: Thursday, December 1, 2016 5:24 AM >To: Srivatsa, Anusha <anusha.srivatsa@intel.com>; intel- >gfx@lists.freedesktop.org >Subject: Re: [Intel-gfx] [PATCH 3/8] drm/i915/huc: Add HuC fw loading support > >Hi, > >On 30/11/2016 23:31, Anusha Srivatsa wrote: >> The HuC loading process is similar to GuC. The intel_uc_fw_fetch() is >> used for both cases. >> >> HuC loading needs to be before GuC loading. The WOPCM setting must be >> done early before loading any of them. >> >> v2: rebased on-top of drm-intel-nightly. >> removed if(HAS_GUC()) before the guc call. (D.Gordon) >> update huc_version number of format. >> v3: rebased to drm-intel-nightly, changed the file name format to >> match the one in the huc package. >> Changed dev->dev_private to to_i915() >> v4: moved function back to where it was. >> change wait_for_atomic to wait_for. >> v5: rebased + comment changes. >> v7: rebased. >> v8: rebased. >> v9: rebased. Changed the year in the copyright message to reflect the >> right year.Correct the comments,remove the unwanted WARN message, >> replace drm_gem_object_unreference() with i915_gem_object_put().Make >> the prototypes in intel_huc.h non-extern. >> v10: rebased. Update the file construction done by HuC. It is similar >> to GuC.Adopted the approach used in- >> https://patchwork.freedesktop.org/patch/104355/ <Tvrtko Ursulin> >> v11: Fix warnings remove old declaration >> v12: Change dev to dev_priv in macro definition. >> Corrected comments. >> v13: rebased. >> v14: rebased on top of drm-tip > >I thought we basically agreed to add i915.enable_huc (default=yes) and hide >i915.enable_guc_loading, making it automatically turn on if either huc or guc >submission are enabled? Yes, I will be sending the patch for the same soon. >Regards, > >Tvrtko > >> >> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> >> Tested-by: Xiang Haihao <haihao.xiang@intel.com> >> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> >> Signed-off-by: Alex Dai <yu.dai@intel.com> >> Signed-off-by: Peter Antoine <peter.antoine@intel.com> >> Reviewed-by: Dave Gordon <david.s.gordon@intel.com> >> --- >> drivers/gpu/drm/i915/Makefile | 1 + >> drivers/gpu/drm/i915/i915_drv.c | 4 +- >> drivers/gpu/drm/i915/i915_drv.h | 4 +- >> drivers/gpu/drm/i915/i915_guc_reg.h | 3 + >> drivers/gpu/drm/i915/intel_guc_loader.c | 6 +- >> drivers/gpu/drm/i915/intel_huc.h | 42 +++++ >> drivers/gpu/drm/i915/intel_huc_loader.c | 267 >++++++++++++++++++++++++++++++++ >> drivers/gpu/drm/i915/intel_uc.h | 2 + >> 8 files changed, 324 insertions(+), 5 deletions(-) create mode >> 100644 drivers/gpu/drm/i915/intel_huc.h create mode 100644 >> drivers/gpu/drm/i915/intel_huc_loader.c >> >> diff --git a/drivers/gpu/drm/i915/Makefile >> b/drivers/gpu/drm/i915/Makefile index 3c30916..01d4f4b 100644 >> --- a/drivers/gpu/drm/i915/Makefile >> +++ b/drivers/gpu/drm/i915/Makefile >> @@ -57,6 +57,7 @@ i915-y += i915_cmd_parser.o \ # general-purpose >> microcontroller (GuC) support i915-y += intel_uc.o \ >> intel_guc_loader.o \ >> + intel_huc_loader.o \ >> i915_guc_submission.o >> >> # autogenerated null render state >> diff --git a/drivers/gpu/drm/i915/i915_drv.c >> b/drivers/gpu/drm/i915/i915_drv.c index 8dac298..075d9ce 100644 >> --- a/drivers/gpu/drm/i915/i915_drv.c >> +++ b/drivers/gpu/drm/i915/i915_drv.c >> @@ -603,6 +603,7 @@ static int i915_load_modeset_init(struct drm_device >*dev) >> if (ret) >> goto cleanup_irq; >> >> + intel_huc_init(dev); >> intel_guc_init(dev); >> >> ret = i915_gem_init(dev); >> @@ -630,6 +631,7 @@ static int i915_load_modeset_init(struct drm_device >*dev) >> DRM_ERROR("failed to idle hardware; continuing to unload!\n"); >> i915_gem_fini(dev_priv); >> cleanup_irq: >> + intel_huc_fini(dev); >> intel_guc_fini(dev); >> drm_irq_uninstall(dev); >> intel_teardown_gmbus(dev); >> @@ -1326,7 +1328,7 @@ void i915_driver_unload(struct drm_device *dev) >> >> /* Flush any outstanding unpin_work. */ >> drain_workqueue(dev_priv->wq); >> - >> + intel_huc_fini(dev); >> intel_guc_fini(dev); >> i915_gem_fini(dev_priv); >> intel_fbc_cleanup_cfb(dev_priv); >> diff --git a/drivers/gpu/drm/i915/i915_drv.h >> b/drivers/gpu/drm/i915/i915_drv.h index 297ad03..8edfae6 100644 >> --- a/drivers/gpu/drm/i915/i915_drv.h >> +++ b/drivers/gpu/drm/i915/i915_drv.h >> @@ -56,6 +56,7 @@ >> #include "intel_bios.h" >> #include "intel_dpll_mgr.h" >> #include "intel_uc.h" >> +#include "intel_huc.h" >> #include "intel_lrc.h" >> #include "intel_ringbuffer.h" >> >> @@ -1933,6 +1934,7 @@ struct drm_i915_private { >> >> struct intel_gvt *gvt; >> >> + struct intel_huc huc; >> struct intel_guc guc; >> >> struct intel_csr csr; >> @@ -2698,7 +2700,7 @@ intel_info(const struct drm_i915_private *dev_priv) >> #define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc) >> #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv)) >> #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv)) >> - >> +#define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv)) >> #define HAS_RESOURCE_STREAMER(dev_priv) >> ((dev_priv)->info.has_resource_streamer) >> >> #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu) >> diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h >> b/drivers/gpu/drm/i915/i915_guc_reg.h >> index 5e638fc..f9829f6 100644 >> --- a/drivers/gpu/drm/i915/i915_guc_reg.h >> +++ b/drivers/gpu/drm/i915/i915_guc_reg.h >> @@ -61,9 +61,12 @@ >> #define DMA_ADDRESS_SPACE_GTT (8 << 16) >> #define DMA_COPY_SIZE _MMIO(0xc310) >> #define DMA_CTRL _MMIO(0xc314) >> +#define HUC_UKERNEL (1<<9) >> #define UOS_MOVE (1<<4) >> #define START_DMA (1<<0) >> #define DMA_GUC_WOPCM_OFFSET _MMIO(0xc340) >> +#define HUC_LOADING_AGENT_VCR (0<<1) >> +#define HUC_LOADING_AGENT_GUC (1<<1) >> #define GUC_WOPCM_OFFSET_VALUE 0x80000 /* 512KB */ >> #define GUC_MAX_IDLE_COUNT _MMIO(0xC3E4) >> >> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c >> b/drivers/gpu/drm/i915/intel_guc_loader.c >> index 557d4b4..7ca5556 100644 >> --- a/drivers/gpu/drm/i915/intel_guc_loader.c >> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c >> @@ -309,8 +309,8 @@ static int guc_ucode_xfer_dma(struct drm_i915_private >*dev_priv, >> I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM); >> >> /* Finally start the DMA */ >> - I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | >START_DMA)); >> - >> + I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | >START_DMA) | >> + _MASKED_BIT_DISABLE(HUC_UKERNEL)); >> /* >> * Wait for the DMA to complete & the GuC to start up. >> * NB: Docs recommend not using the interrupt for completion. >> @@ -334,7 +334,7 @@ static int guc_ucode_xfer_dma(struct drm_i915_private >*dev_priv, >> return ret; >> } >> >> -static u32 guc_wopcm_size(struct drm_i915_private *dev_priv) >> +u32 guc_wopcm_size(struct drm_i915_private *dev_priv) >> { >> u32 wopcm_size = GUC_WOPCM_TOP; >> >> diff --git a/drivers/gpu/drm/i915/intel_huc.h >> b/drivers/gpu/drm/i915/intel_huc.h >> new file mode 100644 >> index 0000000..1dd18c5 >> --- /dev/null >> +++ b/drivers/gpu/drm/i915/intel_huc.h >> @@ -0,0 +1,42 @@ >> +/* >> + * Copyright © 2016 Intel Corporation >> + * >> + * Permission is hereby granted, free of charge, to any person >> +obtaining a >> + * copy of this software and associated documentation files (the >> +"Software"), >> + * to deal in the Software without restriction, including without >> +limitation >> + * the rights to use, copy, modify, merge, publish, distribute, >> +sublicense, >> + * and/or sell copies of the Software, and to permit persons to whom >> +the >> + * Software is furnished to do so, subject to the following conditions: >> + * >> + * The above copyright notice and this permission notice (including >> +the next >> + * paragraph) shall be included in all copies or substantial portions >> +of the >> + * Software. >> + * >> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, >> +EXPRESS OR >> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF >> +MERCHANTABILITY, >> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO >EVENT >> +SHALL >> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, >DAMAGES >> +OR OTHER >> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >> +ARISING >> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >> +OTHER DEALINGS >> + * IN THE SOFTWARE. >> + * >> + */ >> +#ifndef _INTEL_HUC_H_ >> +#define _INTEL_HUC_H_ >> + >> +#include "intel_uc.h" >> + >> +#define HUC_STATUS2 _MMIO(0xD3B0) >> +#define HUC_FW_VERIFIED (1<<7) >> + >> +struct intel_huc { >> + /* Generic uC firmware management */ >> + struct intel_uc_fw huc_fw; >> + >> + /* HuC-specific additions */ >> +}; >> + >> +void intel_huc_init(struct drm_device *dev); void >> +intel_huc_fini(struct drm_device *dev); int intel_huc_load(struct >> +drm_device *dev); #endif >> diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c >> b/drivers/gpu/drm/i915/intel_huc_loader.c >> new file mode 100644 >> index 0000000..663fcc4 >> --- /dev/null >> +++ b/drivers/gpu/drm/i915/intel_huc_loader.c >> @@ -0,0 +1,267 @@ >> +/* >> + * Copyright © 2016 Intel Corporation >> + * >> + * Permission is hereby granted, free of charge, to any person >> +obtaining a >> + * copy of this software and associated documentation files (the >> +"Software"), >> + * to deal in the Software without restriction, including without >> +limitation >> + * the rights to use, copy, modify, merge, publish, distribute, >> +sublicense, >> + * and/or sell copies of the Software, and to permit persons to whom >> +the >> + * Software is furnished to do so, subject to the following conditions: >> + * >> + * The above copyright notice and this permission notice (including >> +the next >> + * paragraph) shall be included in all copies or substantial portions >> +of the >> + * Software. >> + * >> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, >> +EXPRESS OR >> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF >> +MERCHANTABILITY, >> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO >EVENT >> +SHALL >> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, >DAMAGES >> +OR OTHER >> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >> +ARISING >> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >> +OTHER DEALINGS >> + * IN THE SOFTWARE. >> + * >> + */ >> +#include <linux/firmware.h> >> +#include "i915_drv.h" >> +#include "intel_huc.h" >> + >> +/** >> + * DOC: HuC Firmware >> + * >> + * Motivation: >> + * GEN9 introduces a new dedicated firmware for usage in media HEVC >> +(High >> + * Efficiency Video Coding) operations. Userspace can use the >> +firmware >> + * capabilities by adding HuC specific commands to batch buffers. >> + * >> + * Implementation: >> + * The same firmware loader is used as the GuC. However, the actual >> + * loading to HW is deferred until GEM initialization is done. >> + * >> + * Note that HuC firmware loading must be done before GuC loading. >> + */ >> + >> +#define SKL_FW_MAJOR 01 >> +#define SKL_FW_MINOR 07 >> +#define SKL_BLD_NUM 1398 >> + >> +#define HUC_FW_PATH(platform, major, minor, bld_num) \ >> + "i915/" __stringify(platform) "_huc_ver" __stringify(major) "_" \ >> + __stringify(minor) "_" __stringify(bld_num) ".bin" >> + >> +#define I915_SKL_HUC_UCODE HUC_FW_PATH(skl, SKL_FW_MAJOR, \ >> + SKL_FW_MINOR, SKL_BLD_NUM) >> +MODULE_FIRMWARE(I915_SKL_HUC_UCODE); >> + >> +/** >> + * huc_ucode_xfer() - DMA's the firmware >> + * @dev_priv: the drm device >> + * >> + * This function takes the gem object containing the firmware, sets >> +up the DMA >> + * engine MMIO, triggers the DMA operation and waits for it to finish. >> + * >> + * Transfer the firmware image to RAM for execution by the microcontroller. >> + * >> + * Return: 0 on success, non-zero on failure */ >> + >> +static int huc_ucode_xfer(struct drm_i915_private *dev_priv) { >> + struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw; >> + struct i915_vma *vma; >> + unsigned long offset = 0; >> + u32 size; >> + int ret; >> + >> + ret = i915_gem_object_set_to_gtt_domain(huc_fw->uc_fw_obj, false); >> + if (ret) { >> + DRM_DEBUG_DRIVER("set-domain failed %d\n", ret); >> + return ret; >> + } >> + >> + vma = i915_gem_object_ggtt_pin(huc_fw->uc_fw_obj, NULL, 0, 0, 0); >> + if (IS_ERR(vma)) { >> + DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma)); >> + return PTR_ERR(vma); >> + } >> + >> + /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */ >> + I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); >> + >> + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); >> + >> + /* init WOPCM */ >> + I915_WRITE(GUC_WOPCM_SIZE, guc_wopcm_size(dev_priv)); >> + I915_WRITE(DMA_GUC_WOPCM_OFFSET, >GUC_WOPCM_OFFSET_VALUE | >> + HUC_LOADING_AGENT_GUC); >> + >> + /* Set the source address for the uCode */ >> + offset = i915_ggtt_offset(vma) + huc_fw->header_offset; >> + I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset)); >> + I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF); >> + >> + /* Hardware doesn't look at destination address for HuC. Set it to 0, >> + * but still program the correct address space. >> + */ >> + I915_WRITE(DMA_ADDR_1_LOW, 0); >> + I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM); >> + >> + size = huc_fw->header_size + huc_fw->ucode_size; >> + I915_WRITE(DMA_COPY_SIZE, size); >> + >> + /* Start the DMA */ >> + I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(HUC_UKERNEL | >START_DMA)); >> + >> + /* Wait for DMA to finish */ >> + ret = wait_for((I915_READ(DMA_CTRL) & START_DMA) == 0, 100); >> + >> + DRM_DEBUG_DRIVER("HuC DMA transfer wait over with ret %d\n", ret); >> + >> + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); >> + >> + /* >> + * We keep the object pages for reuse during resume. But we can unpin it >> + * now that DMA has completed, so it doesn't continue to take up space. >> + */ >> + i915_vma_unpin(vma); >> + >> + return ret; >> +} >> + >> +/** >> + * intel_huc_init() - initiate HuC firmware loading request >> + * @dev: the drm device >> + * >> + * Called early during driver load, but after GEM is initialised. The >> +loading >> + * will continue only when driver explicitly specify firmware name and version. >> + * All other cases are considered as UC_FIRMWARE_NONE either because >> +HW is not >> + * capable or driver yet support it. And there will be no error >> +message for >> + * UC_FIRMWARE_NONE cases. >> + * >> + * The DMA-copying to HW is done later when intel_huc_load() is called. >> + */ >> +void intel_huc_init(struct drm_device *dev) { >> + struct drm_i915_private *dev_priv = to_i915(dev); >> + struct intel_huc *huc = &dev_priv->huc; >> + struct intel_uc_fw *huc_fw = &huc->huc_fw; >> + const char *fw_path = NULL; >> + >> + huc_fw->uc_dev = dev; >> + huc_fw->uc_fw_path = NULL; >> + huc_fw->fetch_status = UC_FIRMWARE_NONE; >> + huc_fw->load_status = UC_FIRMWARE_NONE; >> + huc_fw->fw_type = UC_FW_TYPE_HUC; >> + >> + if (!HAS_HUC_UCODE(dev_priv)) >> + return; >> + >> + if (IS_SKYLAKE(dev_priv)) { >> + fw_path = I915_SKL_HUC_UCODE; >> + huc_fw->major_ver_wanted = SKL_FW_MAJOR; >> + huc_fw->minor_ver_wanted = SKL_FW_MINOR; >> + } >> + >> + huc_fw->uc_fw_path = fw_path; >> + huc_fw->fetch_status = UC_FIRMWARE_PENDING; >> + >> + DRM_DEBUG_DRIVER("HuC firmware pending, path %s\n", fw_path); >> + >> + intel_uc_fw_fetch(dev, huc_fw); >> +} >> + >> +/** >> + * intel_huc_load() - load HuC uCode to device >> + * @dev: the drm device >> + * >> + * Called from gem_init_hw() during driver loading and also after a GPU reset. >> + * Be note that HuC loading must be done before GuC loading. >> + * >> + * The firmware image should have already been fetched into memory by >> +the >> + * earlier call to intel_huc_init(), so here we need only check that >> + * is succeeded, and then transfer the image to the h/w. >> + * >> + * Return: non-zero code on error >> + */ >> +int intel_huc_load(struct drm_device *dev) { >> + struct drm_i915_private *dev_priv = to_i915(dev); >> + struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw; >> + int err; >> + >> + if (huc_fw->fetch_status == UC_FIRMWARE_NONE) >> + return 0; >> + >> + DRM_DEBUG_DRIVER("%s fw status: fetch %s, load %s\n", >> + huc_fw->uc_fw_path, >> + intel_uc_fw_status_repr(huc_fw->fetch_status), >> + intel_uc_fw_status_repr(huc_fw->load_status)); >> + >> + if (huc_fw->fetch_status == UC_FIRMWARE_SUCCESS && >> + huc_fw->load_status == UC_FIRMWARE_FAIL) >> + return -ENOEXEC; >> + >> + huc_fw->load_status = UC_FIRMWARE_PENDING; >> + >> + switch (huc_fw->fetch_status) { >> + case UC_FIRMWARE_FAIL: >> + /* something went wrong :( */ >> + err = -EIO; >> + goto fail; >> + >> + case UC_FIRMWARE_NONE: >> + case UC_FIRMWARE_PENDING: >> + default: >> + /* "can't happen" */ >> + WARN_ONCE(1, "HuC fw %s invalid fetch_status %s [%d]\n", >> + huc_fw->uc_fw_path, >> + intel_uc_fw_status_repr(huc_fw->fetch_status), >> + huc_fw->fetch_status); >> + err = -ENXIO; >> + goto fail; >> + >> + case UC_FIRMWARE_SUCCESS: >> + break; >> + } >> + >> + err = huc_ucode_xfer(dev_priv); >> + if (err) >> + goto fail; >> + >> + huc_fw->load_status = UC_FIRMWARE_SUCCESS; >> + >> + DRM_DEBUG_DRIVER("%s fw status: fetch %s, load %s\n", >> + huc_fw->uc_fw_path, >> + intel_uc_fw_status_repr(huc_fw->fetch_status), >> + intel_uc_fw_status_repr(huc_fw->load_status)); >> + >> + return 0; >> + >> +fail: >> + if (huc_fw->load_status == UC_FIRMWARE_PENDING) >> + huc_fw->load_status = UC_FIRMWARE_FAIL; >> + >> + DRM_ERROR("Failed to complete HuC uCode load with ret %d\n", err); >> + >> + return err; >> +} >> + >> +/** >> + * intel_huc_fini() - clean up resources allocated for HuC >> + * @dev: the drm device >> + * >> + * Cleans up by releasing the huc firmware GEM obj. >> + */ >> +void intel_huc_fini(struct drm_device *dev) { >> + struct drm_i915_private *dev_priv = to_i915(dev); >> + struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw; >> + >> + mutex_lock(&dev->struct_mutex); >> + if (huc_fw->uc_fw_obj) >> + i915_gem_object_put(huc_fw->uc_fw_obj); >> + huc_fw->uc_fw_obj = NULL; >> + mutex_unlock(&dev->struct_mutex); >> + >> + huc_fw->fetch_status = UC_FIRMWARE_NONE; } >> + >> diff --git a/drivers/gpu/drm/i915/intel_uc.h >> b/drivers/gpu/drm/i915/intel_uc.h index 1616cac..9321225 100644 >> --- a/drivers/gpu/drm/i915/intel_uc.h >> +++ b/drivers/gpu/drm/i915/intel_uc.h >> @@ -191,6 +191,8 @@ extern void intel_guc_fini(struct drm_device >> *dev); extern const char *intel_uc_fw_status_repr(enum >> intel_uc_fw_status status); extern int intel_guc_suspend(struct >> drm_device *dev); extern int intel_guc_resume(struct drm_device >> *dev); >> +void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw >> +*uc_fw); >> +u32 guc_wopcm_size(struct drm_i915_private *dev_priv); >> >> /* i915_guc_submission.c */ >> int i915_guc_submission_init(struct drm_i915_private *dev_priv); >> _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH 4/8] drm/i915/huc: Add BXT HuC Loading Support 2016-11-30 23:31 [PATCH 0/8] HuC Loading Patches Anusha Srivatsa ` (2 preceding siblings ...) 2016-11-30 23:31 ` [PATCH 3/8] drm/i915/huc: Add HuC fw loading support Anusha Srivatsa @ 2016-11-30 23:31 ` Anusha Srivatsa 2016-12-01 13:10 ` Tvrtko Ursulin 2016-11-30 23:31 ` [PATCH 5/8] drm/i915/HuC: Add KBL huC loading Support Anusha Srivatsa ` (4 subsequent siblings) 8 siblings, 1 reply; 43+ messages in thread From: Anusha Srivatsa @ 2016-11-30 23:31 UTC (permalink / raw) To: intel-gfx This patch adds the HuC Loading for the BXT by using the updated file construction. Version 1.7 of the HuC firmware. v2: rebased. v3: rebased on top of drm-tip Cc: Jeff Mcgee <jeff.mcgee@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by: Jeff McGee <jeff.mcgee@intel.com> --- drivers/gpu/drm/i915/intel_huc_loader.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c index 663fcc4..6357c19 100644 --- a/drivers/gpu/drm/i915/intel_huc_loader.c +++ b/drivers/gpu/drm/i915/intel_huc_loader.c @@ -40,6 +40,10 @@ * Note that HuC firmware loading must be done before GuC loading. */ +#define BXT_FW_MAJOR 01 +#define BXT_FW_MINOR 07 +#define BXT_BLD_NUM 1398 + #define SKL_FW_MAJOR 01 #define SKL_FW_MINOR 07 #define SKL_BLD_NUM 1398 @@ -52,6 +56,9 @@ SKL_FW_MINOR, SKL_BLD_NUM) MODULE_FIRMWARE(I915_SKL_HUC_UCODE); +#define I915_BXT_HUC_UCODE HUC_FW_PATH(bxt, BXT_FW_MAJOR, \ + BXT_FW_MINOR, BXT_BLD_NUM) +MODULE_FIRMWARE(I915_BXT_HUC_UCODE); /** * huc_ucode_xfer() - DMA's the firmware * @dev_priv: the drm device @@ -159,6 +166,10 @@ void intel_huc_init(struct drm_device *dev) fw_path = I915_SKL_HUC_UCODE; huc_fw->major_ver_wanted = SKL_FW_MAJOR; huc_fw->minor_ver_wanted = SKL_FW_MINOR; + } else if (IS_BROXTON(dev_priv)) { + fw_path = I915_BXT_HUC_UCODE; + huc_fw->major_ver_wanted = BXT_FW_MAJOR; + huc_fw->minor_ver_wanted = BXT_FW_MINOR; } huc_fw->uc_fw_path = fw_path; -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 43+ messages in thread
* Re: [PATCH 4/8] drm/i915/huc: Add BXT HuC Loading Support 2016-11-30 23:31 ` [PATCH 4/8] drm/i915/huc: Add BXT HuC Loading Support Anusha Srivatsa @ 2016-12-01 13:10 ` Tvrtko Ursulin 2016-12-05 20:42 ` Srivatsa, Anusha 0 siblings, 1 reply; 43+ messages in thread From: Tvrtko Ursulin @ 2016-12-01 13:10 UTC (permalink / raw) To: Anusha Srivatsa, intel-gfx On 30/11/2016 23:31, Anusha Srivatsa wrote: > This patch adds the HuC Loading for the BXT by using > the updated file construction. > > Version 1.7 of the HuC firmware. > > v2: rebased. > v3: rebased on top of drm-tip > > Cc: Jeff Mcgee <jeff.mcgee@intel.com> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> > Reviewed-by: Jeff McGee <jeff.mcgee@intel.com> > --- > drivers/gpu/drm/i915/intel_huc_loader.c | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c > index 663fcc4..6357c19 100644 > --- a/drivers/gpu/drm/i915/intel_huc_loader.c > +++ b/drivers/gpu/drm/i915/intel_huc_loader.c > @@ -40,6 +40,10 @@ > * Note that HuC firmware loading must be done before GuC loading. > */ > > +#define BXT_FW_MAJOR 01 > +#define BXT_FW_MINOR 07 > +#define BXT_BLD_NUM 1398 > + > #define SKL_FW_MAJOR 01 > #define SKL_FW_MINOR 07 > #define SKL_BLD_NUM 1398 > @@ -52,6 +56,9 @@ > SKL_FW_MINOR, SKL_BLD_NUM) > MODULE_FIRMWARE(I915_SKL_HUC_UCODE); > > +#define I915_BXT_HUC_UCODE HUC_FW_PATH(bxt, BXT_FW_MAJOR, \ > + BXT_FW_MINOR, BXT_BLD_NUM) > +MODULE_FIRMWARE(I915_BXT_HUC_UCODE); > /** > * huc_ucode_xfer() - DMA's the firmware > * @dev_priv: the drm device > @@ -159,6 +166,10 @@ void intel_huc_init(struct drm_device *dev) > fw_path = I915_SKL_HUC_UCODE; > huc_fw->major_ver_wanted = SKL_FW_MAJOR; > huc_fw->minor_ver_wanted = SKL_FW_MINOR; > + } else if (IS_BROXTON(dev_priv)) { > + fw_path = I915_BXT_HUC_UCODE; > + huc_fw->major_ver_wanted = BXT_FW_MAJOR; > + huc_fw->minor_ver_wanted = BXT_FW_MINOR; > } > > huc_fw->uc_fw_path = fw_path; > Build number in the file name still worries me. Last time I've asked about it the thread kind of died off so I will re-state it. My concern is that if we will be getting firmware releases with the same major-minor but different build numbers, then embedding the build number into the driver prevents loading of a newer firmware unless the kernel is also updated. I am not sure if that is what we want. Perhaps it is not expected at all that will happen in production so it is not a concern? Or if it could happen, perhaps we should either push back on the scheme - drop the build number and bump the minor in all cases, or alternatively for our purposes drop the build number from the driver and have a symlinked scheme on disk? Regards, Tvrtko _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH 4/8] drm/i915/huc: Add BXT HuC Loading Support 2016-12-01 13:10 ` Tvrtko Ursulin @ 2016-12-05 20:42 ` Srivatsa, Anusha 2016-12-08 15:43 ` Jeff McGee 0 siblings, 1 reply; 43+ messages in thread From: Srivatsa, Anusha @ 2016-12-05 20:42 UTC (permalink / raw) To: Tvrtko Ursulin, intel-gfx >-----Original Message----- >From: Tvrtko Ursulin [mailto:tvrtko.ursulin@linux.intel.com] >Sent: Thursday, December 1, 2016 5:11 AM >To: Srivatsa, Anusha <anusha.srivatsa@intel.com>; intel- >gfx@lists.freedesktop.org >Subject: Re: [Intel-gfx] [PATCH 4/8] drm/i915/huc: Add BXT HuC Loading Support > > >On 30/11/2016 23:31, Anusha Srivatsa wrote: >> This patch adds the HuC Loading for the BXT by using the updated file >> construction. >> >> Version 1.7 of the HuC firmware. >> >> v2: rebased. >> v3: rebased on top of drm-tip >> >> Cc: Jeff Mcgee <jeff.mcgee@intel.com> >> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> >> Reviewed-by: Jeff McGee <jeff.mcgee@intel.com> >> --- >> drivers/gpu/drm/i915/intel_huc_loader.c | 11 +++++++++++ >> 1 file changed, 11 insertions(+) >> >> diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c >> b/drivers/gpu/drm/i915/intel_huc_loader.c >> index 663fcc4..6357c19 100644 >> --- a/drivers/gpu/drm/i915/intel_huc_loader.c >> +++ b/drivers/gpu/drm/i915/intel_huc_loader.c >> @@ -40,6 +40,10 @@ >> * Note that HuC firmware loading must be done before GuC loading. >> */ >> >> +#define BXT_FW_MAJOR 01 >> +#define BXT_FW_MINOR 07 >> +#define BXT_BLD_NUM 1398 >> + >> #define SKL_FW_MAJOR 01 >> #define SKL_FW_MINOR 07 >> #define SKL_BLD_NUM 1398 >> @@ -52,6 +56,9 @@ >> SKL_FW_MINOR, SKL_BLD_NUM) >> MODULE_FIRMWARE(I915_SKL_HUC_UCODE); >> >> +#define I915_BXT_HUC_UCODE HUC_FW_PATH(bxt, BXT_FW_MAJOR, \ >> + BXT_FW_MINOR, BXT_BLD_NUM) >> +MODULE_FIRMWARE(I915_BXT_HUC_UCODE); >> /** >> * huc_ucode_xfer() - DMA's the firmware >> * @dev_priv: the drm device >> @@ -159,6 +166,10 @@ void intel_huc_init(struct drm_device *dev) >> fw_path = I915_SKL_HUC_UCODE; >> huc_fw->major_ver_wanted = SKL_FW_MAJOR; >> huc_fw->minor_ver_wanted = SKL_FW_MINOR; >> + } else if (IS_BROXTON(dev_priv)) { >> + fw_path = I915_BXT_HUC_UCODE; >> + huc_fw->major_ver_wanted = BXT_FW_MAJOR; >> + huc_fw->minor_ver_wanted = BXT_FW_MINOR; >> } >> >> huc_fw->uc_fw_path = fw_path; >> > >Build number in the file name still worries me. Last time I've asked about it the >thread kind of died off so I will re-state it. > >My concern is that if we will be getting firmware releases with the same major- >minor but different build numbers, then embedding the build number into the >driver prevents loading of a newer firmware unless the kernel is also updated. > >I am not sure if that is what we want. Perhaps it is not expected at all that will >happen in production so it is not a concern? > >Or if it could happen, perhaps we should either push back on the scheme >- drop the build number and bump the minor in all cases, or alternatively for our >purposes drop the build number from the driver and have a symlinked scheme on >disk? > >Regards, > >Tvrtko Hi Tvrtko, Sincere apologies for responding so late. According to my understanding, Jeff correct me if I am wrong, we are finalizing the firmware version number for every kernel version. So a certain kernel will have only one possible firware major-minor and build number for a certain platform. I have cc-ed Jeff in this thread so he can add his comment on build number. Jeff, any comments? Regards, Anusha _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH 4/8] drm/i915/huc: Add BXT HuC Loading Support 2016-12-05 20:42 ` Srivatsa, Anusha @ 2016-12-08 15:43 ` Jeff McGee 0 siblings, 0 replies; 43+ messages in thread From: Jeff McGee @ 2016-12-08 15:43 UTC (permalink / raw) To: Srivatsa, Anusha; +Cc: intel-gfx On Mon, Dec 05, 2016 at 12:42:11PM -0800, Srivatsa, Anusha wrote: > > > >-----Original Message----- > >From: Tvrtko Ursulin [mailto:tvrtko.ursulin@linux.intel.com] > >Sent: Thursday, December 1, 2016 5:11 AM > >To: Srivatsa, Anusha <anusha.srivatsa@intel.com>; intel- > >gfx@lists.freedesktop.org > >Subject: Re: [Intel-gfx] [PATCH 4/8] drm/i915/huc: Add BXT HuC Loading Support > > > > > >On 30/11/2016 23:31, Anusha Srivatsa wrote: > >> This patch adds the HuC Loading for the BXT by using the updated file > >> construction. > >> > >> Version 1.7 of the HuC firmware. > >> > >> v2: rebased. > >> v3: rebased on top of drm-tip > >> > >> Cc: Jeff Mcgee <jeff.mcgee@intel.com> > >> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> > >> Reviewed-by: Jeff McGee <jeff.mcgee@intel.com> > >> --- > >> drivers/gpu/drm/i915/intel_huc_loader.c | 11 +++++++++++ > >> 1 file changed, 11 insertions(+) > >> > >> diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c > >> b/drivers/gpu/drm/i915/intel_huc_loader.c > >> index 663fcc4..6357c19 100644 > >> --- a/drivers/gpu/drm/i915/intel_huc_loader.c > >> +++ b/drivers/gpu/drm/i915/intel_huc_loader.c > >> @@ -40,6 +40,10 @@ > >> * Note that HuC firmware loading must be done before GuC loading. > >> */ > >> > >> +#define BXT_FW_MAJOR 01 > >> +#define BXT_FW_MINOR 07 > >> +#define BXT_BLD_NUM 1398 > >> + > >> #define SKL_FW_MAJOR 01 > >> #define SKL_FW_MINOR 07 > >> #define SKL_BLD_NUM 1398 > >> @@ -52,6 +56,9 @@ > >> SKL_FW_MINOR, SKL_BLD_NUM) > >> MODULE_FIRMWARE(I915_SKL_HUC_UCODE); > >> > >> +#define I915_BXT_HUC_UCODE HUC_FW_PATH(bxt, BXT_FW_MAJOR, \ > >> + BXT_FW_MINOR, BXT_BLD_NUM) > >> +MODULE_FIRMWARE(I915_BXT_HUC_UCODE); > >> /** > >> * huc_ucode_xfer() - DMA's the firmware > >> * @dev_priv: the drm device > >> @@ -159,6 +166,10 @@ void intel_huc_init(struct drm_device *dev) > >> fw_path = I915_SKL_HUC_UCODE; > >> huc_fw->major_ver_wanted = SKL_FW_MAJOR; > >> huc_fw->minor_ver_wanted = SKL_FW_MINOR; > >> + } else if (IS_BROXTON(dev_priv)) { > >> + fw_path = I915_BXT_HUC_UCODE; > >> + huc_fw->major_ver_wanted = BXT_FW_MAJOR; > >> + huc_fw->minor_ver_wanted = BXT_FW_MINOR; > >> } > >> > >> huc_fw->uc_fw_path = fw_path; > >> > > > >Build number in the file name still worries me. Last time I've asked about it the > >thread kind of died off so I will re-state it. > > > >My concern is that if we will be getting firmware releases with the same major- > >minor but different build numbers, then embedding the build number into the > >driver prevents loading of a newer firmware unless the kernel is also updated. > > > >I am not sure if that is what we want. Perhaps it is not expected at all that will > >happen in production so it is not a concern? > > > >Or if it could happen, perhaps we should either push back on the scheme > >- drop the build number and bump the minor in all cases, or alternatively for our > >purposes drop the build number from the driver and have a symlinked scheme on > >disk? > > > >Regards, > > > >Tvrtko > > Hi Tvrtko, > Sincere apologies for responding so late. According to my understanding, Jeff correct me if I am wrong, we are finalizing the firmware version number for every kernel version. So a certain kernel will have only one possible firware major-minor and build number for a certain platform. > > I have cc-ed Jeff in this thread so he can add his comment on build number. Jeff, any comments? > > Regards, > Anusha Sorry for delayed response. I'm checking with HuC firmware team on their intended release model. -Jeff _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH 5/8] drm/i915/HuC: Add KBL huC loading Support 2016-11-30 23:31 [PATCH 0/8] HuC Loading Patches Anusha Srivatsa ` (3 preceding siblings ...) 2016-11-30 23:31 ` [PATCH 4/8] drm/i915/huc: Add BXT HuC Loading Support Anusha Srivatsa @ 2016-11-30 23:31 ` Anusha Srivatsa 2016-11-30 23:31 ` [PATCH 6/8] drm/i915/huc: Add debugfs for HuC loading status check Anusha Srivatsa ` (3 subsequent siblings) 8 siblings, 0 replies; 43+ messages in thread From: Anusha Srivatsa @ 2016-11-30 23:31 UTC (permalink / raw) To: intel-gfx This patch adds the support to load HuC on KBL Version 2.0 v2: rebased. v3: rebased on top of drm-tip Cc: Jeff Mcgee <jeff.mcgee@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by: Jeff McGee <jeff.mcgee@intel.com> --- drivers/gpu/drm/i915/intel_huc_loader.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c index 6357c19..20526a4 100644 --- a/drivers/gpu/drm/i915/intel_huc_loader.c +++ b/drivers/gpu/drm/i915/intel_huc_loader.c @@ -48,6 +48,10 @@ #define SKL_FW_MINOR 07 #define SKL_BLD_NUM 1398 +#define KBL_FW_MAJOR 02 +#define KBL_FW_MINOR 00 +#define KBL_BLD_NUM 1810 + #define HUC_FW_PATH(platform, major, minor, bld_num) \ "i915/" __stringify(platform) "_huc_ver" __stringify(major) "_" \ __stringify(minor) "_" __stringify(bld_num) ".bin" @@ -59,6 +63,11 @@ MODULE_FIRMWARE(I915_SKL_HUC_UCODE); #define I915_BXT_HUC_UCODE HUC_FW_PATH(bxt, BXT_FW_MAJOR, \ BXT_FW_MINOR, BXT_BLD_NUM) MODULE_FIRMWARE(I915_BXT_HUC_UCODE); + +#define I915_KBL_HUC_UCODE HUC_FW_PATH(kbl, KBL_FW_MAJOR, \ + KBL_FW_MINOR, KBL_BLD_NUM) +MODULE_FIRMWARE(I915_KBL_HUC_UCODE); + /** * huc_ucode_xfer() - DMA's the firmware * @dev_priv: the drm device @@ -170,8 +179,15 @@ void intel_huc_init(struct drm_device *dev) fw_path = I915_BXT_HUC_UCODE; huc_fw->major_ver_wanted = BXT_FW_MAJOR; huc_fw->minor_ver_wanted = BXT_FW_MINOR; + } else if (IS_KABYLAKE(dev_priv)) { + fw_path = I915_KBL_HUC_UCODE; + huc_fw->major_ver_wanted = KBL_FW_MAJOR; + huc_fw->minor_ver_wanted = KBL_FW_MINOR; } + if (fw_path == NULL) + return; + huc_fw->uc_fw_path = fw_path; huc_fw->fetch_status = UC_FIRMWARE_PENDING; -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH 6/8] drm/i915/huc: Add debugfs for HuC loading status check 2016-11-30 23:31 [PATCH 0/8] HuC Loading Patches Anusha Srivatsa ` (4 preceding siblings ...) 2016-11-30 23:31 ` [PATCH 5/8] drm/i915/HuC: Add KBL huC loading Support Anusha Srivatsa @ 2016-11-30 23:31 ` Anusha Srivatsa 2016-11-30 23:31 ` [PATCH 7/8] drm/i915/huc: Support HuC authentication Anusha Srivatsa ` (2 subsequent siblings) 8 siblings, 0 replies; 43+ messages in thread From: Anusha Srivatsa @ 2016-11-30 23:31 UTC (permalink / raw) To: intel-gfx; +Cc: Alex Dai, Peter Antoine From: Peter Antoine <peter.antoine@intel.com> Add debugfs entry for HuC loading status check. v2: rebase on-top of drm-intel-nightly. v3: rebased again. v7: rebased. v8: rebased. v9: rebased. v10: rebased. v11: rebased on top of drm-tip Tested-by: Xiang Haihao <haihao.xiang@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Alex Dai <yu.dai@intel.com> Signed-off-by: Peter Antoine <peter.antoine@intel.com> Reviewed-by: Dave Gordon <david.s.gordon@intel.com> Reviewed-by: Jeff McGee <jeff.mcgee@intel.com> --- drivers/gpu/drm/i915/i915_debugfs.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index d6efda9..1cc4682 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -2334,6 +2334,36 @@ static int i915_llc(struct seq_file *m, void *data) return 0; } +static int i915_huc_load_status_info(struct seq_file *m, void *data) +{ + struct drm_i915_private *dev_priv = node_to_i915(m->private); + struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw; + + if (!HAS_HUC_UCODE(dev_priv)) + return 0; + + seq_puts(m, "HuC firmware status:\n"); + seq_printf(m, "\tpath: %s\n", huc_fw->uc_fw_path); + seq_printf(m, "\tfetch: %s\n", + intel_uc_fw_status_repr(huc_fw->fetch_status)); + seq_printf(m, "\tload: %s\n", + intel_uc_fw_status_repr(huc_fw->load_status)); + seq_printf(m, "\tversion wanted: %d.%d\n", + huc_fw->major_ver_wanted, huc_fw->minor_ver_wanted); + seq_printf(m, "\tversion found: %d.%d\n", + huc_fw->major_ver_found, huc_fw->minor_ver_found); + seq_printf(m, "\theader: offset is %d; size = %d\n", + huc_fw->header_offset, huc_fw->header_size); + seq_printf(m, "\tuCode: offset is %d; size = %d\n", + huc_fw->ucode_offset, huc_fw->ucode_size); + seq_printf(m, "\tRSA: offset is %d; size = %d\n", + huc_fw->rsa_offset, huc_fw->rsa_size); + + seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2)); + + return 0; +} + static int i915_guc_load_status_info(struct seq_file *m, void *data) { struct drm_i915_private *dev_priv = node_to_i915(m->private); @@ -5402,6 +5432,7 @@ static const struct drm_info_list i915_debugfs_list[] = { {"i915_guc_info", i915_guc_info, 0}, {"i915_guc_load_status", i915_guc_load_status_info, 0}, {"i915_guc_log_dump", i915_guc_log_dump, 0}, + {"i915_huc_load_status", i915_huc_load_status_info, 0}, {"i915_frequency_info", i915_frequency_info, 0}, {"i915_hangcheck_info", i915_hangcheck_info, 0}, {"i915_drpc_info", i915_drpc_info, 0}, -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH 7/8] drm/i915/huc: Support HuC authentication 2016-11-30 23:31 [PATCH 0/8] HuC Loading Patches Anusha Srivatsa ` (5 preceding siblings ...) 2016-11-30 23:31 ` [PATCH 6/8] drm/i915/huc: Add debugfs for HuC loading status check Anusha Srivatsa @ 2016-11-30 23:31 ` Anusha Srivatsa 2016-12-01 13:05 ` Arkadiusz Hiler 2016-11-30 23:31 ` [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams Anusha Srivatsa 2016-12-01 5:31 ` ✗ Fi.CI.BAT: failure for HuC Loading Patches Patchwork 8 siblings, 1 reply; 43+ messages in thread From: Anusha Srivatsa @ 2016-11-30 23:31 UTC (permalink / raw) To: intel-gfx; +Cc: Alex Dai, Peter Antoine From: Peter Antoine <peter.antoine@intel.com> The HuC authentication is done by host2guc call. The HuC RSA keys are sent to GuC for authentication. v2: rebased on top of drm-intel-nightly. changed name format and upped version 1.7. v3: rebased on top of drm-intel-nightly. v4: changed wait_for_automic to wait_for v5: rebased. v7: rebased. v8: rebased. v9: rebased. Rename intel_huc_auh() to intel_guc_auth_huc() and place the prototype in intel_guc.h,correct the comments. v10: rebased. v11: rebased. v12: rebased on top of drm-tip Tested-by: Xiang Haihao <haihao.xiang@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Alex Dai <yu.dai@intel.com> Signed-off-by: Peter Antoine <peter.antoine@intel.com> Reviewed-by: Dave Gordon <david.s.gordon@intel.com> Reviewed-by: Jeff McGee <jeff.mcgee@intel.com> --- drivers/gpu/drm/i915/i915_guc_submission.c | 63 ++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_guc_fwif.h | 1 + drivers/gpu/drm/i915/intel_guc_loader.c | 2 + 3 files changed, 66 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c index 4bae8e4..d5c205d 100644 --- a/drivers/gpu/drm/i915/i915_guc_submission.c +++ b/drivers/gpu/drm/i915/i915_guc_submission.c @@ -26,6 +26,7 @@ #include <linux/relay.h> #include "i915_drv.h" #include "intel_uc.h" +#include "intel_huc.h" /** * DOC: GuC-based command submission @@ -1638,3 +1639,65 @@ int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val) return ret; } + +/** + * intel_guc_auth_huc() - authenticate ucode + * @dev: the drm device + * + * Triggers a HuC fw authentication request to the GuC via host-2-guc + * interface. + */ +void intel_guc_auth_huc(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + struct intel_guc *guc = &dev_priv->guc; + struct intel_huc *huc = &dev_priv->huc; + struct i915_vma *vma; + int ret; + u32 data[2]; + + /* Bypass the case where there is no HuC firmware */ + if (huc->huc_fw.fetch_status == UC_FIRMWARE_NONE || + huc->huc_fw.load_status == UC_FIRMWARE_NONE) + return; + + if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS) { + DRM_ERROR("HuC: GuC fw wasn't loaded. Can't authenticate"); + return; + } + + if (huc->huc_fw.load_status != UC_FIRMWARE_SUCCESS) { + DRM_ERROR("HuC: fw wasn't loaded. Nothing to authenticate"); + return; + } + + vma = i915_gem_object_ggtt_pin(huc->huc_fw.uc_fw_obj, NULL, 0, 0, 0); + if (IS_ERR(vma)) { + DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma)); + return; + } + + + /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */ + I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); + + /* Specify auth action and where public signature is. */ + data[0] = HOST2GUC_ACTION_AUTHENTICATE_HUC; + data[1] = i915_ggtt_offset(vma) + huc->huc_fw.rsa_offset; + + ret = host2guc_action(guc, data, ARRAY_SIZE(data)); + if (ret) { + DRM_ERROR("HuC: GuC did not ack Auth request\n"); + goto out; + } + + /* Check authentication status, it should be done by now */ + ret = wait_for((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) > 0, 50); + if (ret) { + DRM_ERROR("HuC: Authentication failed\n"); + goto out; + } + +out: + i915_vma_unpin(vma); +} diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h index c07d9da..e51e063 100644 --- a/drivers/gpu/drm/i915/intel_guc_fwif.h +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h @@ -513,6 +513,7 @@ enum intel_guc_action { INTEL_GUC_ACTION_EXIT_S_STATE = 0x502, INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003, INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000, + HOST2GUC_ACTION_AUTHENTICATE_HUC = 0x4000, INTEL_GUC_ACTION_LIMIT }; diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c index 7ca5556..31d09f8 100644 --- a/drivers/gpu/drm/i915/intel_guc_loader.c +++ b/drivers/gpu/drm/i915/intel_guc_loader.c @@ -529,6 +529,8 @@ int intel_guc_setup(struct drm_device *dev) intel_uc_fw_status_repr(guc_fw->fetch_status), intel_uc_fw_status_repr(guc_fw->load_status)); + intel_guc_auth_huc(dev); + if (i915.enable_guc_submission) { if (i915.guc_log_level >= 0) gen9_enable_guc_interrupts(dev_priv); -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 43+ messages in thread
* Re: [PATCH 7/8] drm/i915/huc: Support HuC authentication 2016-11-30 23:31 ` [PATCH 7/8] drm/i915/huc: Support HuC authentication Anusha Srivatsa @ 2016-12-01 13:05 ` Arkadiusz Hiler 0 siblings, 0 replies; 43+ messages in thread From: Arkadiusz Hiler @ 2016-12-01 13:05 UTC (permalink / raw) To: Anusha Srivatsa; +Cc: intel-gfx On Wed, Nov 30, 2016 at 03:31:33PM -0800, Anusha Srivatsa wrote: > From: Peter Antoine <peter.antoine@intel.com> > > The HuC authentication is done by host2guc call. The HuC RSA keys > are sent to GuC for authentication. > > v2: rebased on top of drm-intel-nightly. > changed name format and upped version 1.7. > v3: rebased on top of drm-intel-nightly. > v4: changed wait_for_automic to wait_for > v5: rebased. > v7: rebased. > v8: rebased. > v9: rebased. Rename intel_huc_auh() to intel_guc_auth_huc() > and place the prototype in intel_guc.h,correct the comments. > v10: rebased. > v11: rebased. > v12: rebased on top of drm-tip > > Tested-by: Xiang Haihao <haihao.xiang@intel.com> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> > Signed-off-by: Alex Dai <yu.dai@intel.com> > Signed-off-by: Peter Antoine <peter.antoine@intel.com> > Reviewed-by: Dave Gordon <david.s.gordon@intel.com> > Reviewed-by: Jeff McGee <jeff.mcgee@intel.com> > --- > drivers/gpu/drm/i915/i915_guc_submission.c | 63 ++++++++++++++++++++++++++++++ > drivers/gpu/drm/i915/intel_guc_fwif.h | 1 + > drivers/gpu/drm/i915/intel_guc_loader.c | 2 + > 3 files changed, 66 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c > index 4bae8e4..d5c205d 100644 > --- a/drivers/gpu/drm/i915/i915_guc_submission.c > +++ b/drivers/gpu/drm/i915/i915_guc_submission.c > @@ -26,6 +26,7 @@ > #include <linux/relay.h> > #include "i915_drv.h" > #include "intel_uc.h" > +#include "intel_huc.h" > > /** > * DOC: GuC-based command submission > @@ -1638,3 +1639,65 @@ int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val) > > return ret; > } > + > +/** > + * intel_guc_auth_huc() - authenticate ucode > + * @dev: the drm device > + * > + * Triggers a HuC fw authentication request to the GuC via host-2-guc > + * interface. > + */ > +void intel_guc_auth_huc(struct drm_device *dev) This should belong to intel_uc.c > +{ > + struct drm_i915_private *dev_priv = dev->dev_private; > + struct intel_guc *guc = &dev_priv->guc; > + struct intel_huc *huc = &dev_priv->huc; > + struct i915_vma *vma; > + int ret; > + u32 data[2]; > + > + /* Bypass the case where there is no HuC firmware */ > + if (huc->huc_fw.fetch_status == UC_FIRMWARE_NONE || > + huc->huc_fw.load_status == UC_FIRMWARE_NONE) > + return; > + > + if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS) { > + DRM_ERROR("HuC: GuC fw wasn't loaded. Can't authenticate"); > + return; > + } > + > + if (huc->huc_fw.load_status != UC_FIRMWARE_SUCCESS) { > + DRM_ERROR("HuC: fw wasn't loaded. Nothing to authenticate"); > + return; > + } > + > + vma = i915_gem_object_ggtt_pin(huc->huc_fw.uc_fw_obj, NULL, 0, 0, 0); > + if (IS_ERR(vma)) { > + DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma)); > + return; > + } > + > + > + /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */ > + I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); > + > + /* Specify auth action and where public signature is. */ > + data[0] = HOST2GUC_ACTION_AUTHENTICATE_HUC; s/HOST2GUC/INTEL_GUC/ > + data[1] = i915_ggtt_offset(vma) + huc->huc_fw.rsa_offset; > + > + ret = host2guc_action(guc, data, ARRAY_SIZE(data)); s/host2guc_action/intel_guc_send/ > + if (ret) { > + DRM_ERROR("HuC: GuC did not ack Auth request\n"); > + goto out; > + } > + > + /* Check authentication status, it should be done by now */ > + ret = wait_for((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) > 0, 50); > + if (ret) { > + DRM_ERROR("HuC: Authentication failed\n"); > + goto out; > + } > + > +out: > + i915_vma_unpin(vma); > +} > diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h > index c07d9da..e51e063 100644 > --- a/drivers/gpu/drm/i915/intel_guc_fwif.h > +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h > @@ -513,6 +513,7 @@ enum intel_guc_action { > INTEL_GUC_ACTION_EXIT_S_STATE = 0x502, > INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003, > INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000, > + HOST2GUC_ACTION_AUTHENTICATE_HUC = 0x4000, s/HOST2GUC/INTEL_GUC/ > INTEL_GUC_ACTION_LIMIT > }; > > diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c > index 7ca5556..31d09f8 100644 > --- a/drivers/gpu/drm/i915/intel_guc_loader.c > +++ b/drivers/gpu/drm/i915/intel_guc_loader.c > @@ -529,6 +529,8 @@ int intel_guc_setup(struct drm_device *dev) > intel_uc_fw_status_repr(guc_fw->fetch_status), > intel_uc_fw_status_repr(guc_fw->load_status)); > > + intel_guc_auth_huc(dev); > + You do not have this symbol declared in any header, it's not visible in this compilation unit. > if (i915.enable_guc_submission) { > if (i915.guc_log_level >= 0) > gen9_enable_guc_interrupts(dev_priv); > -- > 2.7.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Cheers, Arek _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams 2016-11-30 23:31 [PATCH 0/8] HuC Loading Patches Anusha Srivatsa ` (6 preceding siblings ...) 2016-11-30 23:31 ` [PATCH 7/8] drm/i915/huc: Support HuC authentication Anusha Srivatsa @ 2016-11-30 23:31 ` Anusha Srivatsa 2016-12-01 13:07 ` Arkadiusz Hiler 2016-12-01 5:31 ` ✗ Fi.CI.BAT: failure for HuC Loading Patches Patchwork 8 siblings, 1 reply; 43+ messages in thread From: Anusha Srivatsa @ 2016-11-30 23:31 UTC (permalink / raw) To: intel-gfx; +Cc: Peter Antoine From: Peter Antoine <peter.antoine@intel.com> This patch will allow for getparams to return the status of the HuC. As the HuC has to be validated by the GuC this patch uses the validated status to show when the HuC is loaded and ready for use. You cannot use the loaded status as with the GuC as the HuC is verified after it is loaded and is not usable until it is verified. v2: removed the forewakes as the registers are already force-woken. (T.Ursulin) v4: rebased. v5: rebased on top of drm-tip. Signed-off-by: Peter Antoine <peter.antoine@intel.com> --- drivers/gpu/drm/i915/i915_drv.c | 5 +++++ drivers/gpu/drm/i915/intel_huc.h | 1 + drivers/gpu/drm/i915/intel_huc_loader.c | 12 ++++++++++++ include/uapi/drm/i915_drm.h | 1 + 4 files changed, 19 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 075d9ce..75a3e24 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -49,6 +49,8 @@ #include "i915_trace.h" #include "i915_vgpu.h" #include "intel_drv.h" +#include "intel_uc.h" +#include "intel_huc.h" static struct drm_driver driver; @@ -350,6 +352,9 @@ static int i915_getparam(struct drm_device *dev, void *data, */ value = 1; break; + case I915_PARAM_HAS_HUC: + value = intel_is_huc_valid(dev_priv); + break; default: DRM_DEBUG("Unknown parameter %d\n", param->param); return -EINVAL; diff --git a/drivers/gpu/drm/i915/intel_huc.h b/drivers/gpu/drm/i915/intel_huc.h index 1dd18c5..1b67311 100644 --- a/drivers/gpu/drm/i915/intel_huc.h +++ b/drivers/gpu/drm/i915/intel_huc.h @@ -39,4 +39,5 @@ struct intel_huc { void intel_huc_init(struct drm_device *dev); void intel_huc_fini(struct drm_device *dev); int intel_huc_load(struct drm_device *dev); +int intel_is_huc_valid(struct drm_i915_private *dev_priv); #endif diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c index 20526a4..e18de0f6 100644 --- a/drivers/gpu/drm/i915/intel_huc_loader.c +++ b/drivers/gpu/drm/i915/intel_huc_loader.c @@ -292,3 +292,15 @@ void intel_huc_fini(struct drm_device *dev) huc_fw->fetch_status = UC_FIRMWARE_NONE; } +/** + * intel_is_huc_valid() - Check to see if the HuC is fully loaded. + * @dev_priv: drm device to check. + * + * This function will return true if the guc has been loaded and + * has valid firmware. The simplest way of doing this is to check + * if the HuC has been validated, if so it must have been loaded. + */ +int intel_is_huc_valid(struct drm_i915_private *dev_priv) +{ + return ((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) != 0); +} diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index bdfc688..397b47d 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -395,6 +395,7 @@ typedef struct drm_i915_irq_wait { * priorities and the driver will attempt to execute batches in priority order. */ #define I915_PARAM_HAS_SCHEDULER 41 +#define I915_PARAM_HAS_HUC 42 typedef struct drm_i915_getparam { __s32 param; -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 43+ messages in thread
* Re: [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams 2016-11-30 23:31 ` [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams Anusha Srivatsa @ 2016-12-01 13:07 ` Arkadiusz Hiler 0 siblings, 0 replies; 43+ messages in thread From: Arkadiusz Hiler @ 2016-12-01 13:07 UTC (permalink / raw) To: Anusha Srivatsa; +Cc: intel-gfx On Wed, Nov 30, 2016 at 03:31:34PM -0800, Anusha Srivatsa wrote: > From: Peter Antoine <peter.antoine@intel.com> > > This patch will allow for getparams to return the status of the HuC. > As the HuC has to be validated by the GuC this patch uses the validated > status to show when the HuC is loaded and ready for use. You cannot use > the loaded status as with the GuC as the HuC is verified after it is > loaded and is not usable until it is verified. > > v2: removed the forewakes as the registers are already force-woken. > (T.Ursulin) > v4: rebased. > v5: rebased on top of drm-tip. > > Signed-off-by: Peter Antoine <peter.antoine@intel.com> Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.c | 5 +++++ > drivers/gpu/drm/i915/intel_huc.h | 1 + > drivers/gpu/drm/i915/intel_huc_loader.c | 12 ++++++++++++ > include/uapi/drm/i915_drm.h | 1 + > 4 files changed, 19 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c > index 075d9ce..75a3e24 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -49,6 +49,8 @@ > #include "i915_trace.h" > #include "i915_vgpu.h" > #include "intel_drv.h" > +#include "intel_uc.h" > +#include "intel_huc.h" > > static struct drm_driver driver; > > @@ -350,6 +352,9 @@ static int i915_getparam(struct drm_device *dev, void *data, > */ > value = 1; > break; > + case I915_PARAM_HAS_HUC: > + value = intel_is_huc_valid(dev_priv); > + break; > default: > DRM_DEBUG("Unknown parameter %d\n", param->param); > return -EINVAL; > diff --git a/drivers/gpu/drm/i915/intel_huc.h b/drivers/gpu/drm/i915/intel_huc.h > index 1dd18c5..1b67311 100644 > --- a/drivers/gpu/drm/i915/intel_huc.h > +++ b/drivers/gpu/drm/i915/intel_huc.h > @@ -39,4 +39,5 @@ struct intel_huc { > void intel_huc_init(struct drm_device *dev); > void intel_huc_fini(struct drm_device *dev); > int intel_huc_load(struct drm_device *dev); > +int intel_is_huc_valid(struct drm_i915_private *dev_priv); > #endif > diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c > index 20526a4..e18de0f6 100644 > --- a/drivers/gpu/drm/i915/intel_huc_loader.c > +++ b/drivers/gpu/drm/i915/intel_huc_loader.c > @@ -292,3 +292,15 @@ void intel_huc_fini(struct drm_device *dev) > huc_fw->fetch_status = UC_FIRMWARE_NONE; > } > > +/** > + * intel_is_huc_valid() - Check to see if the HuC is fully loaded. > + * @dev_priv: drm device to check. > + * > + * This function will return true if the guc has been loaded and > + * has valid firmware. The simplest way of doing this is to check > + * if the HuC has been validated, if so it must have been loaded. > + */ > +int intel_is_huc_valid(struct drm_i915_private *dev_priv) > +{ > + return ((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) != 0); > +} > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h > index bdfc688..397b47d 100644 > --- a/include/uapi/drm/i915_drm.h > +++ b/include/uapi/drm/i915_drm.h > @@ -395,6 +395,7 @@ typedef struct drm_i915_irq_wait { > * priorities and the driver will attempt to execute batches in priority order. > */ > #define I915_PARAM_HAS_SCHEDULER 41 > +#define I915_PARAM_HAS_HUC 42 > > typedef struct drm_i915_getparam { > __s32 param; > -- > 2.7.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Cheers, Arek _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 43+ messages in thread
* ✗ Fi.CI.BAT: failure for HuC Loading Patches 2016-11-30 23:31 [PATCH 0/8] HuC Loading Patches Anusha Srivatsa ` (7 preceding siblings ...) 2016-11-30 23:31 ` [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams Anusha Srivatsa @ 2016-12-01 5:31 ` Patchwork 8 siblings, 0 replies; 43+ messages in thread From: Patchwork @ 2016-12-01 5:31 UTC (permalink / raw) To: Anusha Srivatsa; +Cc: intel-gfx == Series Details == Series: HuC Loading Patches URL : https://patchwork.freedesktop.org/series/16188/ State : failure == Summary == CC [M] drivers/gpu/drm/i915/gvt/opregion.o CC [M] drivers/gpu/drm/i915/gvt/mmio.o CC [M] drivers/gpu/drm/i915/gvt/display.o CC [M] drivers/gpu/drm/i915/gvt/edid.o CC [M] drivers/gpu/drm/i915/gvt/execlist.o CC [M] drivers/gpu/drm/i915/gvt/scheduler.o CC [M] drivers/gpu/drm/i915/gvt/sched_policy.o CC [M] drivers/gpu/drm/i915/gvt/render.o CC [M] drivers/gpu/drm/i915/gvt/cmd_parser.o LD [M] drivers/misc/mei/mei-me.o LD drivers/tty/serial/8250/8250.o LD drivers/usb/storage/usb-storage.o LD drivers/misc/built-in.o LD drivers/usb/storage/built-in.o LD net/ipv6/ipv6.o LD [M] sound/pci/hda/snd-hda-codec-generic.o LD sound/pci/built-in.o LD drivers/pci/pcie/aer/aerdriver.o LD drivers/md/dm-mod.o LD drivers/pci/pcie/aer/built-in.o LD drivers/pci/pcie/built-in.o LD net/ipv6/built-in.o LD [M] drivers/usb/serial/usbserial.o LD sound/built-in.o LD [M] drivers/gpu/drm/vgem/vgem.o drivers/gpu/drm/i915/intel_guc_loader.c: In function ‘intel_guc_setup’: drivers/gpu/drm/i915/intel_guc_loader.c:532:2: error: implicit declaration of function ‘intel_guc_auth_huc’ [-Werror=implicit-function-declaration] intel_guc_auth_huc(dev); ^ LD drivers/usb/gadget/libcomposite.o drivers/gpu/drm/i915/i915_guc_submission.c: In function ‘intel_guc_auth_huc’: drivers/gpu/drm/i915/i915_guc_submission.c:1688:8: error: implicit declaration of function ‘host2guc_action’ [-Werror=implicit-function-declaration] ret = host2guc_action(guc, data, ARRAY_SIZE(data)); ^ LD drivers/usb/gadget/udc/udc-core.o LD drivers/usb/gadget/udc/built-in.o LD drivers/usb/gadget/built-in.o LD drivers/scsi/scsi_mod.o LD drivers/thermal/thermal_sys.o LD drivers/video/fbdev/core/fb.o LD drivers/video/fbdev/core/built-in.o LD drivers/thermal/built-in.o LD [M] drivers/net/ethernet/broadcom/genet/genet.o LD drivers/video/fbdev/built-in.o LD drivers/iommu/built-in.o LD drivers/spi/built-in.o AR lib/lib.a LD drivers/tty/serial/8250/8250_base.o EXPORTS lib/lib-ksyms.o LD drivers/tty/serial/8250/built-in.o cc1: all warnings being treated as errors LD lib/built-in.o scripts/Makefile.build:293: recipe for target 'drivers/gpu/drm/i915/intel_guc_loader.o' failed make[4]: *** [drivers/gpu/drm/i915/intel_guc_loader.o] Error 1 make[4]: *** Waiting for unfinished jobs.... LD [M] drivers/net/ethernet/intel/igbvf/igbvf.o cc1: all warnings being treated as errors scripts/Makefile.build:293: recipe for target 'drivers/gpu/drm/i915/i915_guc_submission.o' failed make[4]: *** [drivers/gpu/drm/i915/i915_guc_submission.o] Error 1 LD drivers/tty/serial/built-in.o LD drivers/pci/built-in.o LD drivers/gpu/drm/drm.o LD drivers/usb/core/usbcore.o LD drivers/scsi/sd_mod.o LD drivers/scsi/built-in.o LD drivers/usb/core/built-in.o LD drivers/video/console/built-in.o LD drivers/video/built-in.o LD [M] drivers/net/ethernet/intel/e1000/e1000.o LD fs/btrfs/btrfs.o LD net/ipv4/built-in.o CC arch/x86/kernel/cpu/capflags.o LD arch/x86/kernel/cpu/built-in.o LD fs/btrfs/built-in.o LD arch/x86/kernel/built-in.o LD drivers/usb/host/xhci-hcd.o LD drivers/md/md-mod.o LD arch/x86/built-in.o LD drivers/md/built-in.o LD drivers/tty/vt/built-in.o LD drivers/tty/built-in.o LD net/core/built-in.o LD net/built-in.o LD drivers/usb/host/built-in.o LD drivers/usb/built-in.o LD [M] drivers/net/ethernet/intel/igb/igb.o LD fs/ext4/ext4.o LD fs/ext4/built-in.o LD fs/built-in.o LD [M] drivers/net/ethernet/intel/e1000e/e1000e.o LD drivers/net/ethernet/built-in.o LD drivers/net/built-in.o scripts/Makefile.build:544: recipe for target 'drivers/gpu/drm/i915' failed make[3]: *** [drivers/gpu/drm/i915] Error 2 scripts/Makefile.build:544: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:544: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 Makefile:986: recipe for target 'drivers' failed make: *** [drivers] Error 2 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH 0/8] HuC Loading Patches @ 2017-01-14 1:17 Anusha Srivatsa 2017-01-14 1:17 ` [PATCH 7/8] drm/i915/huc: Support HuC authentication Anusha Srivatsa 0 siblings, 1 reply; 43+ messages in thread From: Anusha Srivatsa @ 2017-01-14 1:17 UTC (permalink / raw) To: intel-gfx The patches add HuC loading support. The driver builds a frame level workload which is stored in the graphics memory. This workload is presented to HuC for processing. The driver, therefore should first determine if the HuC is enabled and also read the huC athentication status bit to determine if HuC was successfully loaded. The GuC is required to authenticate the HuC. The userspace patches that check for a fully loaded HuC firmware and use it can be found at: https://lists.freedesktop.org/archives/libva/2016-September/004554.html https://lists.freedesktop.org/archives/libva/2016-September/004555.html More information regarding the HuC, batch commands that configure the HuC etc can be found at- https://01.org/sites/default/files/documentation/intel-gfx-prm-osrc-skl-vol02a-commandreference-instructions-huc.pdf https://www.x.org/docs/intel/CHV/intel-gfx-prm-osrc-chv-bsw-vol10-hevc.pdf v2: rebased. Changed the code following the review comments. v3: rebased. Organize code. Move contents of intel_huc.h to intel_uc.h. Update function intel_huc_load(),intel_huc_init() and intel_uc_fw_fetch() to accept dev_priv instead of dev. v4: rebased. Remove intel_is_huc_valid() since it is called onoly once. Refactor the code to reduce redundency. Remove fiels like uc_dev which are no longer used. v5: rebased. Beautify the code- remove comments that no longer hold good, add newlines etc. v6: rebased. Remove further redundency. Correct comments. Replace wait_for with intel_wait_for_register() for optimisation purpose.Make fw_type an enum. v7: rebased. Rename intel_huc_loader() to intel_huc(). Move intel_guc_auth_huc() from intel_uc.c to intel_huc.c. Add return values to DRM_ERRORs. v8: Use DRM_INFO instead of DRM_ERROR in places that are non-erraneous. Remove invalidates that are no longer required. Anusha Srivatsa (8): drm/i915/guc: Make the GuC fw loading helper functions general drm/i915/huc: Unified css_header struct for GuC and HuC drm/i915/huc: Add HuC fw loading support drm/i915/huc: Add BXT HuC Loading Support drm/i915/HuC: Add KBL huC loading Support drm/i915/huc: Add debugfs for HuC loading status check drm/i915/huc: Support HuC authentication drm/i915/get_params: Add HuC status to getparams drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/i915_debugfs.c | 43 +++- drivers/gpu/drm/i915/i915_drv.c | 10 + drivers/gpu/drm/i915/i915_drv.h | 2 + drivers/gpu/drm/i915/i915_guc_reg.h | 6 + drivers/gpu/drm/i915/i915_guc_submission.c | 4 +- drivers/gpu/drm/i915/intel_guc_fwif.h | 24 +- drivers/gpu/drm/i915/intel_guc_loader.c | 196 +++++++++-------- drivers/gpu/drm/i915/intel_huc.c | 342 +++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_uc.h | 60 +++-- include/uapi/drm/i915_drm.h | 1 + 11 files changed, 569 insertions(+), 120 deletions(-) create mode 100644 drivers/gpu/drm/i915/intel_huc.c -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH 7/8] drm/i915/huc: Support HuC authentication 2017-01-14 1:17 [PATCH 0/8] " Anusha Srivatsa @ 2017-01-14 1:17 ` Anusha Srivatsa 0 siblings, 0 replies; 43+ messages in thread From: Anusha Srivatsa @ 2017-01-14 1:17 UTC (permalink / raw) To: intel-gfx The HuC authentication is done by host2guc call. The HuC RSA keys are sent to GuC for authentication. v2: rebased on top of drm-tip. Changed name format and upped version 1.7. v3: changed wait_for_atomic to wait_for v4: rebased. Rename intel_huc_auh() to intel_guc_auth_huc() and place the prototype in intel_guc.h,correct the comments. v5: rebased. Moved intel_guc_auth_huc from i915_guc_submission.c to intel_uc.c.Update dev to dev_priv in intel_guc_auth_huc(). Renamed HOST2GUC_ACTION_AUTHENTICATE_HUC TO INTEL_GUC_ACTION_ AUTHENTICATE_HUC v6: rebased. Add newline on DRM_ERRORs that already dont have one. v7: rebased. Replace wait_for with intel_wait_for_register() since the latter employs sleep optimisations for quick responses- as pointed out by Chris Wilson. v8: rebased. Cleanup the intel_guc_auth_huc() by removing checks already performed in earlier functions. Make comments more descriptive. v9: rebased. Changed the bias for pinning the HuC object. Move intel_guc_auth_huc() to intel_huc.c. Change DRM_DEBUGs to DRM_ERRORs in intel_guc_auth_huc(). Add return status to DRM_ERRORs. v10: Remove message not required for the user.. Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Tested-by: Xiang Haihao <haihao.xiang@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Alex Dai <yu.dai@intel.com> Signed-off-by: Peter Antoine <peter.antoine@intel.com> --- drivers/gpu/drm/i915/intel_guc_fwif.h | 1 + drivers/gpu/drm/i915/intel_guc_loader.c | 2 ++ drivers/gpu/drm/i915/intel_huc.c | 49 +++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_uc.h | 1 + 4 files changed, 53 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h index ed1ab40..25691f0 100644 --- a/drivers/gpu/drm/i915/intel_guc_fwif.h +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h @@ -505,6 +505,7 @@ enum intel_guc_action { INTEL_GUC_ACTION_ENTER_S_STATE = 0x501, INTEL_GUC_ACTION_EXIT_S_STATE = 0x502, INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003, + INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000, INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000, INTEL_GUC_ACTION_LIMIT }; diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c index 527558f..bb127a4 100644 --- a/drivers/gpu/drm/i915/intel_guc_loader.c +++ b/drivers/gpu/drm/i915/intel_guc_loader.c @@ -530,6 +530,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv) intel_uc_fw_status_repr(guc_fw->fetch_status), intel_uc_fw_status_repr(guc_fw->load_status)); + intel_guc_auth_huc(dev_priv); + if (i915.enable_guc_submission) { if (i915.guc_log_level >= 0) gen9_enable_guc_interrupts(dev_priv); diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c index 8b84ba8..897ef31 100644 --- a/drivers/gpu/drm/i915/intel_huc.c +++ b/drivers/gpu/drm/i915/intel_huc.c @@ -284,3 +284,52 @@ void intel_huc_fini(struct drm_i915_private *dev_priv) huc_fw->fetch_status = INTEL_UC_FIRMWARE_NONE; } +/** + * intel_guc_auth_huc() - authenticate ucode + * @dev_priv: the drm_i915_device + * + * Triggers a HuC fw authentication request to the GuC via intel_guc_action_ + * authenticate_huc interface. + */ +void intel_guc_auth_huc(struct drm_i915_private *dev_priv) +{ + struct intel_guc *guc = &dev_priv->guc; + struct intel_huc *huc = &dev_priv->huc; + struct i915_vma *vma; + int ret; + u32 data[2]; + + vma = i915_gem_object_ggtt_pin(huc->fw.obj, NULL, 0, 0, + PIN_OFFSET_BIAS | GUC_WOPCM_TOP); + if (IS_ERR(vma)) { + DRM_ERROR("failed to pin huc fw object %d\n", + (int)PTR_ERR(vma)); + return; + } + + /* Specify auth action and where public signature is. */ + data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC; + data[1] = i915_ggtt_offset(vma) + huc->fw.rsa_offset; + + ret = intel_guc_send(guc, data, ARRAY_SIZE(data)); + if (ret) { + DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret); + goto out; + } + + /* Check authentication status, it should be done by now */ + ret = intel_wait_for_register(dev_priv, + HUC_STATUS2, + HUC_FW_VERIFIED, + HUC_FW_VERIFIED, + 50); + + if (ret) { + DRM_ERROR("HuC: Authentication failed %d\n", ret); + goto out; + } + +out: + i915_vma_unpin(vma); +} + diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h index 65c7d6e..27f8b6f 100644 --- a/drivers/gpu/drm/i915/intel_uc.h +++ b/drivers/gpu/drm/i915/intel_uc.h @@ -227,5 +227,6 @@ static inline u32 guc_ggtt_offset(struct i915_vma *vma) void intel_huc_init(struct drm_i915_private *dev_priv); void intel_huc_fini(struct drm_i915_private *dev_priv); int intel_huc_load(struct drm_i915_private *dev_priv); +void intel_guc_auth_huc(struct drm_i915_private *dev_priv); #endif -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH 0/8] HuC Loading Patches @ 2017-01-13 18:08 Anusha Srivatsa 2017-01-13 18:08 ` [PATCH 7/8] drm/i915/huc: Support HuC authentication Anusha Srivatsa 0 siblings, 1 reply; 43+ messages in thread From: Anusha Srivatsa @ 2017-01-13 18:08 UTC (permalink / raw) To: intel-gfx The patches add HuC loading support. The driver builds a frame level workload which is stored in the graphics memory. This workload is presented to HuC for processing. The driver, therefore should first determine if the HuC is enabled and also read the huC athentication status bit to determine if HuC was successfully loaded. The GuC is required to authenticate the HuC. The userspace patches that check for a fully loaded HuC firmware and use it can be found at: https://lists.freedesktop.org/archives/libva/2016-September/004554.html https://lists.freedesktop.org/archives/libva/2016-September/004555.html More information regarding the HuC, batch commands that configure the HuC etc can be found at- https://01.org/sites/default/files/documentation/intel-gfx-prm-osrc-skl-vol02a-commandreference-instructions-huc.pdf https://www.x.org/docs/intel/CHV/intel-gfx-prm-osrc-chv-bsw-vol10-hevc.pdf v2: rebased. Changed the code following the review comments. v3: rebased. Organize code. Move contents of intel_huc.h to intel_uc.h. Update function intel_huc_load(),intel_huc_init() and intel_uc_fw_fetch() to accept dev_priv instead of dev. v4: rebased. Remove intel_is_huc_valid() since it is called onoly once. Refactor the code to reduce redundency. Remove fiels like uc_dev which are no longer used. v5: rebased. Beautify the code- remove comments that no longer hold good, add newlines etc. v6: rebased. Remove further redundency. Correct comments. Replace wait_for with intel_wait_for_register() for optimisation purpose.Make fw_type an enum. v7: rebased. Rename intel_huc_loader() to intel_huc(). Move intel_guc_auth_huc() from intel_uc.c to intel_huc.c. Add return values to DRM_ERRORs. v8: Use DRM_INFO instead of DRM_ERROR in places that are non-erraneous. Remove invalidates that are no longer required. Anusha Srivatsa (8): drm/i915/guc: Make the GuC fw loading helper functions general drm/i915/huc: Unified css_header struct for GuC and HuC drm/i915/huc: Add HuC fw loading support drm/i915/huc: Add BXT HuC Loading Support drm/i915/HuC: Add KBL huC loading Support drm/i915/huc: Add debugfs for HuC loading status check drm/i915/huc: Support HuC authentication drm/i915/get_params: Add HuC status to getparams drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/i915_debugfs.c | 43 +++- drivers/gpu/drm/i915/i915_drv.c | 10 + drivers/gpu/drm/i915/i915_drv.h | 2 + drivers/gpu/drm/i915/i915_guc_reg.h | 6 + drivers/gpu/drm/i915/i915_guc_submission.c | 4 +- drivers/gpu/drm/i915/intel_guc_fwif.h | 24 +- drivers/gpu/drm/i915/intel_guc_loader.c | 196 +++++++++-------- drivers/gpu/drm/i915/intel_huc.c | 342 +++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_uc.h | 60 +++-- include/uapi/drm/i915_drm.h | 1 + 11 files changed, 569 insertions(+), 120 deletions(-) create mode 100644 drivers/gpu/drm/i915/intel_huc.c -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH 7/8] drm/i915/huc: Support HuC authentication 2017-01-13 18:08 [PATCH 0/8] HuC Loading Patches Anusha Srivatsa @ 2017-01-13 18:08 ` Anusha Srivatsa 2017-01-13 18:18 ` Michal Wajdeczko 0 siblings, 1 reply; 43+ messages in thread From: Anusha Srivatsa @ 2017-01-13 18:08 UTC (permalink / raw) To: intel-gfx; +Cc: Peter Antoine, Alex Dai The HuC authentication is done by host2guc call. The HuC RSA keys are sent to GuC for authentication. v2: rebased on top of drm-tip. Changed name format and upped version 1.7. v3: changed wait_for_atomic to wait_for v4: rebased. Rename intel_huc_auh() to intel_guc_auth_huc() and place the prototype in intel_guc.h,correct the comments. v5: rebased. Moved intel_guc_auth_huc from i915_guc_submission.c to intel_uc.c.Update dev to dev_priv in intel_guc_auth_huc(). Renamed HOST2GUC_ACTION_AUTHENTICATE_HUC TO INTEL_GUC_ACTION_ AUTHENTICATE_HUC v6: rebased. Add newline on DRM_ERRORs that already dont have one. v7: rebased. Replace wait_for with intel_wait_for_register() since the latter employs sleep optimisations for quick responses- as pointed out by Chris Wilson. v8: rebased. Cleanup the intel_guc_auth_huc() by removing checks already performed in earlier functions. Make comments more descriptive. v9: rebased. Changed the bias for pinning the HuC object. Move intel_guc_auth_huc() to intel_huc.c. Change DRM_DEBUGs to DRM_ERRORs in intel_guc_auth_huc(). Add return status to DRM_ERRORs. v10: Replace DRM_ERROR with DRM_INFO for cases that are non- erroneous. Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Tested-by: Xiang Haihao <haihao.xiang@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Alex Dai <yu.dai@intel.com> Signed-off-by: Peter Antoine <peter.antoine@intel.com> --- drivers/gpu/drm/i915/intel_guc_fwif.h | 1 + drivers/gpu/drm/i915/intel_guc_loader.c | 2 ++ drivers/gpu/drm/i915/intel_huc.c | 53 +++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_uc.h | 1 + 4 files changed, 57 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h index ed1ab40..25691f0 100644 --- a/drivers/gpu/drm/i915/intel_guc_fwif.h +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h @@ -505,6 +505,7 @@ enum intel_guc_action { INTEL_GUC_ACTION_ENTER_S_STATE = 0x501, INTEL_GUC_ACTION_EXIT_S_STATE = 0x502, INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003, + INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000, INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000, INTEL_GUC_ACTION_LIMIT }; diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c index 527558f..bb127a4 100644 --- a/drivers/gpu/drm/i915/intel_guc_loader.c +++ b/drivers/gpu/drm/i915/intel_guc_loader.c @@ -530,6 +530,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv) intel_uc_fw_status_repr(guc_fw->fetch_status), intel_uc_fw_status_repr(guc_fw->load_status)); + intel_guc_auth_huc(dev_priv); + if (i915.enable_guc_submission) { if (i915.guc_log_level >= 0) gen9_enable_guc_interrupts(dev_priv); diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c index 8b84ba8..4ae34b5 100644 --- a/drivers/gpu/drm/i915/intel_huc.c +++ b/drivers/gpu/drm/i915/intel_huc.c @@ -284,3 +284,56 @@ void intel_huc_fini(struct drm_i915_private *dev_priv) huc_fw->fetch_status = INTEL_UC_FIRMWARE_NONE; } +/** + * intel_guc_auth_huc() - authenticate ucode + * @dev_priv: the drm_i915_device + * + * Triggers a HuC fw authentication request to the GuC via intel_guc_action_ + * authenticate_huc interface. + */ +void intel_guc_auth_huc(struct drm_i915_private *dev_priv) +{ + struct intel_guc *guc = &dev_priv->guc; + struct intel_huc *huc = &dev_priv->huc; + struct i915_vma *vma; + int ret; + u32 data[2]; + + vma = i915_gem_object_ggtt_pin(huc->fw.obj, NULL, 0, 0, + PIN_OFFSET_BIAS | GUC_WOPCM_TOP); + if (IS_ERR(vma)) { + DRM_ERROR("failed to pin huc fw object %d\n", + (int)PTR_ERR(vma)); + return; + } + + /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */ + I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); + + /* Specify auth action and where public signature is. */ + data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC; + data[1] = i915_ggtt_offset(vma) + huc->fw.rsa_offset; + + ret = intel_guc_send(guc, data, ARRAY_SIZE(data)); + if (ret) { + DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret); + goto out; + } + + /* Check authentication status, it should be done by now */ + ret = intel_wait_for_register(dev_priv, + HUC_STATUS2, + HUC_FW_VERIFIED, + HUC_FW_VERIFIED, + 50); + + if (ret) { + DRM_ERROR("HuC: Authentication failed %d\n", ret); + goto out; + } + + DRM_INFO("HuC Authentication Successful!\n"); +out: + i915_vma_unpin(vma); +} + diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h index 65c7d6e..27f8b6f 100644 --- a/drivers/gpu/drm/i915/intel_uc.h +++ b/drivers/gpu/drm/i915/intel_uc.h @@ -227,5 +227,6 @@ static inline u32 guc_ggtt_offset(struct i915_vma *vma) void intel_huc_init(struct drm_i915_private *dev_priv); void intel_huc_fini(struct drm_i915_private *dev_priv); int intel_huc_load(struct drm_i915_private *dev_priv); +void intel_guc_auth_huc(struct drm_i915_private *dev_priv); #endif -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 43+ messages in thread
* Re: [PATCH 7/8] drm/i915/huc: Support HuC authentication 2017-01-13 18:08 ` [PATCH 7/8] drm/i915/huc: Support HuC authentication Anusha Srivatsa @ 2017-01-13 18:18 ` Michal Wajdeczko 2017-01-13 18:19 ` Srivatsa, Anusha 0 siblings, 1 reply; 43+ messages in thread From: Michal Wajdeczko @ 2017-01-13 18:18 UTC (permalink / raw) To: Anusha Srivatsa; +Cc: Peter Antoine, intel-gfx, Alex Dai On Fri, Jan 13, 2017 at 10:08:42AM -0800, Anusha Srivatsa wrote: > The HuC authentication is done by host2guc call. The HuC RSA keys > are sent to GuC for authentication. > > v2: rebased on top of drm-tip. Changed name format and upped > version 1.7. > v3: changed wait_for_atomic to wait_for > v4: rebased. Rename intel_huc_auh() to intel_guc_auth_huc() > and place the prototype in intel_guc.h,correct the comments. > v5: rebased. Moved intel_guc_auth_huc from i915_guc_submission.c > to intel_uc.c.Update dev to dev_priv in intel_guc_auth_huc(). > Renamed HOST2GUC_ACTION_AUTHENTICATE_HUC TO INTEL_GUC_ACTION_ > AUTHENTICATE_HUC > v6: rebased. Add newline on DRM_ERRORs that already dont have one. > v7: rebased. Replace wait_for with intel_wait_for_register() since > the latter employs sleep optimisations for quick responses- as pointed > out by Chris Wilson. > v8: rebased. Cleanup the intel_guc_auth_huc() by removing checks > already performed in earlier functions. Make comments more descriptive. > v9: rebased. Changed the bias for pinning the HuC object. Move > intel_guc_auth_huc() to intel_huc.c. Change DRM_DEBUGs to DRM_ERRORs > in intel_guc_auth_huc(). Add return status to DRM_ERRORs. > v10: Replace DRM_ERROR with DRM_INFO for cases that are non- > erroneous. > > Cc: Chris Wilson <chris@chris-wilson.co.uk> > Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com> > Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> > Tested-by: Xiang Haihao <haihao.xiang@intel.com> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> > Signed-off-by: Alex Dai <yu.dai@intel.com> > Signed-off-by: Peter Antoine <peter.antoine@intel.com> > --- > drivers/gpu/drm/i915/intel_guc_fwif.h | 1 + > drivers/gpu/drm/i915/intel_guc_loader.c | 2 ++ > drivers/gpu/drm/i915/intel_huc.c | 53 +++++++++++++++++++++++++++++++++ > drivers/gpu/drm/i915/intel_uc.h | 1 + > 4 files changed, 57 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h > index ed1ab40..25691f0 100644 > --- a/drivers/gpu/drm/i915/intel_guc_fwif.h > +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h > @@ -505,6 +505,7 @@ enum intel_guc_action { > INTEL_GUC_ACTION_ENTER_S_STATE = 0x501, > INTEL_GUC_ACTION_EXIT_S_STATE = 0x502, > INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003, > + INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000, > INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000, > INTEL_GUC_ACTION_LIMIT > }; > diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c > index 527558f..bb127a4 100644 > --- a/drivers/gpu/drm/i915/intel_guc_loader.c > +++ b/drivers/gpu/drm/i915/intel_guc_loader.c > @@ -530,6 +530,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv) > intel_uc_fw_status_repr(guc_fw->fetch_status), > intel_uc_fw_status_repr(guc_fw->load_status)); > > + intel_guc_auth_huc(dev_priv); > + > if (i915.enable_guc_submission) { > if (i915.guc_log_level >= 0) > gen9_enable_guc_interrupts(dev_priv); > diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c > index 8b84ba8..4ae34b5 100644 > --- a/drivers/gpu/drm/i915/intel_huc.c > +++ b/drivers/gpu/drm/i915/intel_huc.c > @@ -284,3 +284,56 @@ void intel_huc_fini(struct drm_i915_private *dev_priv) > huc_fw->fetch_status = INTEL_UC_FIRMWARE_NONE; > } > > +/** > + * intel_guc_auth_huc() - authenticate ucode > + * @dev_priv: the drm_i915_device > + * > + * Triggers a HuC fw authentication request to the GuC via intel_guc_action_ > + * authenticate_huc interface. > + */ > +void intel_guc_auth_huc(struct drm_i915_private *dev_priv) > +{ > + struct intel_guc *guc = &dev_priv->guc; > + struct intel_huc *huc = &dev_priv->huc; > + struct i915_vma *vma; > + int ret; > + u32 data[2]; > + > + vma = i915_gem_object_ggtt_pin(huc->fw.obj, NULL, 0, 0, > + PIN_OFFSET_BIAS | GUC_WOPCM_TOP); > + if (IS_ERR(vma)) { > + DRM_ERROR("failed to pin huc fw object %d\n", Maybe this message should start with "HuC:" to match other error messages used below ? Anyway, Reviewed-by: Michal Wajdeczko <michal.wajdeczko.intel.com> Thanks, Michal > + (int)PTR_ERR(vma)); > + return; > + } > + > + /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */ > + I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); > + > + /* Specify auth action and where public signature is. */ > + data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC; > + data[1] = i915_ggtt_offset(vma) + huc->fw.rsa_offset; > + > + ret = intel_guc_send(guc, data, ARRAY_SIZE(data)); > + if (ret) { > + DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret); > + goto out; > + } > + > + /* Check authentication status, it should be done by now */ > + ret = intel_wait_for_register(dev_priv, > + HUC_STATUS2, > + HUC_FW_VERIFIED, > + HUC_FW_VERIFIED, > + 50); > + > + if (ret) { > + DRM_ERROR("HuC: Authentication failed %d\n", ret); > + goto out; > + } > + > + DRM_INFO("HuC Authentication Successful!\n"); > +out: > + i915_vma_unpin(vma); > +} > + > diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h > index 65c7d6e..27f8b6f 100644 > --- a/drivers/gpu/drm/i915/intel_uc.h > +++ b/drivers/gpu/drm/i915/intel_uc.h > @@ -227,5 +227,6 @@ static inline u32 guc_ggtt_offset(struct i915_vma *vma) > void intel_huc_init(struct drm_i915_private *dev_priv); > void intel_huc_fini(struct drm_i915_private *dev_priv); > int intel_huc_load(struct drm_i915_private *dev_priv); > +void intel_guc_auth_huc(struct drm_i915_private *dev_priv); > > #endif > -- > 2.7.4 > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH 7/8] drm/i915/huc: Support HuC authentication 2017-01-13 18:18 ` Michal Wajdeczko @ 2017-01-13 18:19 ` Srivatsa, Anusha 2017-01-13 18:47 ` Chris Wilson 0 siblings, 1 reply; 43+ messages in thread From: Srivatsa, Anusha @ 2017-01-13 18:19 UTC (permalink / raw) To: Wajdeczko, Michal; +Cc: Peter Antoine, intel-gfx, Alex Dai >-----Original Message----- >From: Wajdeczko, Michal >Sent: Friday, January 13, 2017 10:18 AM >To: Srivatsa, Anusha <anusha.srivatsa@intel.com> >Cc: intel-gfx@lists.freedesktop.org; Chris Wilson <chris@chris-wilson.co.uk>; >Hiler, Arkadiusz <arkadiusz.hiler@intel.com>; Alex Dai <yu.dai@intel.com>; Peter >Antoine <peter.antoine@intel.com> >Subject: Re: [PATCH 7/8] drm/i915/huc: Support HuC authentication > >On Fri, Jan 13, 2017 at 10:08:42AM -0800, Anusha Srivatsa wrote: >> The HuC authentication is done by host2guc call. The HuC RSA keys are >> sent to GuC for authentication. >> >> v2: rebased on top of drm-tip. Changed name format and upped version >> 1.7. >> v3: changed wait_for_atomic to wait_for >> v4: rebased. Rename intel_huc_auh() to intel_guc_auth_huc() and place >> the prototype in intel_guc.h,correct the comments. >> v5: rebased. Moved intel_guc_auth_huc from i915_guc_submission.c to >> intel_uc.c.Update dev to dev_priv in intel_guc_auth_huc(). >> Renamed HOST2GUC_ACTION_AUTHENTICATE_HUC TO INTEL_GUC_ACTION_ >> AUTHENTICATE_HUC >> v6: rebased. Add newline on DRM_ERRORs that already dont have one. >> v7: rebased. Replace wait_for with intel_wait_for_register() since the >> latter employs sleep optimisations for quick responses- as pointed out >> by Chris Wilson. >> v8: rebased. Cleanup the intel_guc_auth_huc() by removing checks >> already performed in earlier functions. Make comments more descriptive. >> v9: rebased. Changed the bias for pinning the HuC object. Move >> intel_guc_auth_huc() to intel_huc.c. Change DRM_DEBUGs to DRM_ERRORs >> in intel_guc_auth_huc(). Add return status to DRM_ERRORs. >> v10: Replace DRM_ERROR with DRM_INFO for cases that are non- >> erroneous. >> >> Cc: Chris Wilson <chris@chris-wilson.co.uk> >> Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com> >> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> >> Tested-by: Xiang Haihao <haihao.xiang@intel.com> >> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> >> Signed-off-by: Alex Dai <yu.dai@intel.com> >> Signed-off-by: Peter Antoine <peter.antoine@intel.com> >> --- >> drivers/gpu/drm/i915/intel_guc_fwif.h | 1 + >> drivers/gpu/drm/i915/intel_guc_loader.c | 2 ++ >> drivers/gpu/drm/i915/intel_huc.c | 53 >+++++++++++++++++++++++++++++++++ >> drivers/gpu/drm/i915/intel_uc.h | 1 + >> 4 files changed, 57 insertions(+) >> >> diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h >> b/drivers/gpu/drm/i915/intel_guc_fwif.h >> index ed1ab40..25691f0 100644 >> --- a/drivers/gpu/drm/i915/intel_guc_fwif.h >> +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h >> @@ -505,6 +505,7 @@ enum intel_guc_action { >> INTEL_GUC_ACTION_ENTER_S_STATE = 0x501, >> INTEL_GUC_ACTION_EXIT_S_STATE = 0x502, >> INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003, >> + INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000, >> INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000, >> INTEL_GUC_ACTION_LIMIT >> }; >> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c >> b/drivers/gpu/drm/i915/intel_guc_loader.c >> index 527558f..bb127a4 100644 >> --- a/drivers/gpu/drm/i915/intel_guc_loader.c >> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c >> @@ -530,6 +530,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv) >> intel_uc_fw_status_repr(guc_fw->fetch_status), >> intel_uc_fw_status_repr(guc_fw->load_status)); >> >> + intel_guc_auth_huc(dev_priv); >> + >> if (i915.enable_guc_submission) { >> if (i915.guc_log_level >= 0) >> gen9_enable_guc_interrupts(dev_priv); >> diff --git a/drivers/gpu/drm/i915/intel_huc.c >> b/drivers/gpu/drm/i915/intel_huc.c >> index 8b84ba8..4ae34b5 100644 >> --- a/drivers/gpu/drm/i915/intel_huc.c >> +++ b/drivers/gpu/drm/i915/intel_huc.c >> @@ -284,3 +284,56 @@ void intel_huc_fini(struct drm_i915_private *dev_priv) >> huc_fw->fetch_status = INTEL_UC_FIRMWARE_NONE; } >> >> +/** >> + * intel_guc_auth_huc() - authenticate ucode >> + * @dev_priv: the drm_i915_device >> + * >> + * Triggers a HuC fw authentication request to the GuC via >> +intel_guc_action_ >> + * authenticate_huc interface. >> + */ >> +void intel_guc_auth_huc(struct drm_i915_private *dev_priv) { >> + struct intel_guc *guc = &dev_priv->guc; >> + struct intel_huc *huc = &dev_priv->huc; >> + struct i915_vma *vma; >> + int ret; >> + u32 data[2]; >> + >> + vma = i915_gem_object_ggtt_pin(huc->fw.obj, NULL, 0, 0, >> + PIN_OFFSET_BIAS | GUC_WOPCM_TOP); >> + if (IS_ERR(vma)) { >> + DRM_ERROR("failed to pin huc fw object %d\n", > >Maybe this message should start with "HuC:" to match other error messages used >below ? Anyway, > >Reviewed-by: Michal Wajdeczko <michal.wajdeczko.intel.com> Thanks a lot Michal! >Thanks, >Michal > > >> + (int)PTR_ERR(vma)); >> + return; >> + } >> + >> + /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */ >> + I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); >> + >> + /* Specify auth action and where public signature is. */ >> + data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC; >> + data[1] = i915_ggtt_offset(vma) + huc->fw.rsa_offset; >> + >> + ret = intel_guc_send(guc, data, ARRAY_SIZE(data)); >> + if (ret) { >> + DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret); >> + goto out; >> + } >> + >> + /* Check authentication status, it should be done by now */ >> + ret = intel_wait_for_register(dev_priv, >> + HUC_STATUS2, >> + HUC_FW_VERIFIED, >> + HUC_FW_VERIFIED, >> + 50); >> + >> + if (ret) { >> + DRM_ERROR("HuC: Authentication failed %d\n", ret); >> + goto out; >> + } >> + >> + DRM_INFO("HuC Authentication Successful!\n"); >> +out: >> + i915_vma_unpin(vma); >> +} >> + >> diff --git a/drivers/gpu/drm/i915/intel_uc.h >> b/drivers/gpu/drm/i915/intel_uc.h index 65c7d6e..27f8b6f 100644 >> --- a/drivers/gpu/drm/i915/intel_uc.h >> +++ b/drivers/gpu/drm/i915/intel_uc.h >> @@ -227,5 +227,6 @@ static inline u32 guc_ggtt_offset(struct i915_vma >> *vma) void intel_huc_init(struct drm_i915_private *dev_priv); void >> intel_huc_fini(struct drm_i915_private *dev_priv); int >> intel_huc_load(struct drm_i915_private *dev_priv); >> +void intel_guc_auth_huc(struct drm_i915_private *dev_priv); >> >> #endif >> -- >> 2.7.4 >> _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH 7/8] drm/i915/huc: Support HuC authentication 2017-01-13 18:19 ` Srivatsa, Anusha @ 2017-01-13 18:47 ` Chris Wilson 0 siblings, 0 replies; 43+ messages in thread From: Chris Wilson @ 2017-01-13 18:47 UTC (permalink / raw) To: Srivatsa, Anusha; +Cc: Peter Antoine, intel-gfx, Alex Dai On Fri, Jan 13, 2017 at 06:19:53PM +0000, Srivatsa, Anusha wrote: > >> + /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */ > >> + I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); This is not required on drm-tip. > >> + /* Specify auth action and where public signature is. */ > >> + data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC; > >> + data[1] = i915_ggtt_offset(vma) + huc->fw.rsa_offset; > >> + > >> + ret = intel_guc_send(guc, data, ARRAY_SIZE(data)); > >> + if (ret) { > >> + DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret); > >> + goto out; > >> + } > >> + > >> + /* Check authentication status, it should be done by now */ > >> + ret = intel_wait_for_register(dev_priv, > >> + HUC_STATUS2, > >> + HUC_FW_VERIFIED, > >> + HUC_FW_VERIFIED, > >> + 50); > >> + > >> + if (ret) { > >> + DRM_ERROR("HuC: Authentication failed %d\n", ret); > >> + goto out; > >> + } > >> + > >> + DRM_INFO("HuC Authentication Successful!\n"); You still seem surprised. Is this a useful user message? What does it mean for the user? Avoid using jargon when talking to the user. -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH 7/8] drm/i915/huc: Support HuC authentication @ 2017-01-13 17:07 Anusha Srivatsa 2017-01-13 17:24 ` Chris Wilson 0 siblings, 1 reply; 43+ messages in thread From: Anusha Srivatsa @ 2017-01-13 17:07 UTC (permalink / raw) To: intel-gfx; +Cc: Peter Antoine, Alex Dai The HuC authentication is done by host2guc call. The HuC RSA keys are sent to GuC for authentication. v2: rebased on top of drm-tip. Changed name format and upped version 1.7. v3: changed wait_for_atomic to wait_for v4: rebased. Rename intel_huc_auh() to intel_guc_auth_huc() and place the prototype in intel_guc.h,correct the comments. v5: rebased. Moved intel_guc_auth_huc from i915_guc_submission.c to intel_uc.c.Update dev to dev_priv in intel_guc_auth_huc(). Renamed HOST2GUC_ACTION_AUTHENTICATE_HUC TO INTEL_GUC_ACTION_ AUTHENTICATE_HUC v6: rebased. Add newline on DRM_ERRORs that already dont have one. v7: rebased. Replace wait_for with intel_wait_for_register() since the latter employs sleep optimisations for quick responses- as pointed out by Chris Wilson. v8: rebased. Cleanup the intel_guc_auth_huc() by removing checks already performed in earlier functions. Make comments more descriptive. v9: rebased. Changed the bias for pinning the HuC object. Move intel_guc_auth_huc() to intel_huc.c. Change DRM_DEBUGs to DRM_ERRORs in intel_guc_auth_huc(). Add return status to DRM_ERRORs. Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Tested-by: Xiang Haihao <haihao.xiang@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Alex Dai <yu.dai@intel.com> Signed-off-by: Peter Antoine <peter.antoine@intel.com> --- drivers/gpu/drm/i915/intel_guc_fwif.h | 1 + drivers/gpu/drm/i915/intel_guc_loader.c | 2 ++ drivers/gpu/drm/i915/intel_huc.c | 53 +++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_uc.h | 1 + 4 files changed, 57 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h index ed1ab40..25691f0 100644 --- a/drivers/gpu/drm/i915/intel_guc_fwif.h +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h @@ -505,6 +505,7 @@ enum intel_guc_action { INTEL_GUC_ACTION_ENTER_S_STATE = 0x501, INTEL_GUC_ACTION_EXIT_S_STATE = 0x502, INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003, + INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000, INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000, INTEL_GUC_ACTION_LIMIT }; diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c index 861c157..c618d11 100644 --- a/drivers/gpu/drm/i915/intel_guc_loader.c +++ b/drivers/gpu/drm/i915/intel_guc_loader.c @@ -530,6 +530,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv) intel_uc_fw_status_repr(guc_fw->fetch_status), intel_uc_fw_status_repr(guc_fw->load_status)); + intel_guc_auth_huc(dev_priv); + if (i915.enable_guc_submission) { if (i915.guc_log_level >= 0) gen9_enable_guc_interrupts(dev_priv); diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c index 7f3774a..22f1207 100644 --- a/drivers/gpu/drm/i915/intel_huc.c +++ b/drivers/gpu/drm/i915/intel_huc.c @@ -287,3 +287,56 @@ void intel_huc_fini(struct drm_i915_private *dev_priv) huc_fw->fetch_status = INTEL_UC_FIRMWARE_NONE; } +/** + * intel_guc_auth_huc() - authenticate ucode + * @dev_priv: the drm_i915_device + * + * Triggers a HuC fw authentication request to the GuC via intel_guc_action_ + * authenticate_huc interface. + */ +void intel_guc_auth_huc(struct drm_i915_private *dev_priv) +{ + struct intel_guc *guc = &dev_priv->guc; + struct intel_huc *huc = &dev_priv->huc; + struct i915_vma *vma; + int ret; + u32 data[2]; + + vma = i915_gem_object_ggtt_pin(huc->fw.obj, NULL, 0, 0, + PIN_OFFSET_BIAS | GUC_WOPCM_TOP); + if (IS_ERR(vma)) { + DRM_ERROR("failed to pin huc fw object %d\n", + (int)PTR_ERR(vma)); + return; + } + + /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */ + I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); + + /* Specify auth action and where public signature is. */ + data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC; + data[1] = i915_ggtt_offset(vma) + huc->fw.rsa_offset; + + ret = intel_guc_send(guc, data, ARRAY_SIZE(data)); + if (ret) { + DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret); + goto out; + } + + /* Check authentication status, it should be done by now */ + ret = intel_wait_for_register(dev_priv, + HUC_STATUS2, + HUC_FW_VERIFIED, + HUC_FW_VERIFIED, + 50); + + if (ret) { + DRM_ERROR("HuC: Authentication failed %d\n", ret); + goto out; + } + + DRM_ERROR("HuC Authentication Successful!\n"); +out: + i915_vma_unpin(vma); +} + diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h index 65c7d6e..27f8b6f 100644 --- a/drivers/gpu/drm/i915/intel_uc.h +++ b/drivers/gpu/drm/i915/intel_uc.h @@ -227,5 +227,6 @@ static inline u32 guc_ggtt_offset(struct i915_vma *vma) void intel_huc_init(struct drm_i915_private *dev_priv); void intel_huc_fini(struct drm_i915_private *dev_priv); int intel_huc_load(struct drm_i915_private *dev_priv); +void intel_guc_auth_huc(struct drm_i915_private *dev_priv); #endif -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 43+ messages in thread
* Re: [PATCH 7/8] drm/i915/huc: Support HuC authentication 2017-01-13 17:07 Anusha Srivatsa @ 2017-01-13 17:24 ` Chris Wilson 2017-01-13 17:36 ` Srivatsa, Anusha 0 siblings, 1 reply; 43+ messages in thread From: Chris Wilson @ 2017-01-13 17:24 UTC (permalink / raw) To: Anusha Srivatsa; +Cc: Peter Antoine, intel-gfx, Alex Dai On Fri, Jan 13, 2017 at 09:07:08AM -0800, Anusha Srivatsa wrote: > +/** > + * intel_guc_auth_huc() - authenticate ucode > + * @dev_priv: the drm_i915_device > + * > + * Triggers a HuC fw authentication request to the GuC via intel_guc_action_ > + * authenticate_huc interface. > + */ > +void intel_guc_auth_huc(struct drm_i915_private *dev_priv) > +{ > + struct intel_guc *guc = &dev_priv->guc; > + struct intel_huc *huc = &dev_priv->huc; > + struct i915_vma *vma; > + int ret; > + u32 data[2]; > + > + vma = i915_gem_object_ggtt_pin(huc->fw.obj, NULL, 0, 0, > + PIN_OFFSET_BIAS | GUC_WOPCM_TOP); > + if (IS_ERR(vma)) { > + DRM_ERROR("failed to pin huc fw object %d\n", > + (int)PTR_ERR(vma)); > + return; > + } > + > + /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */ > + I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); > + > + /* Specify auth action and where public signature is. */ > + data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC; > + data[1] = i915_ggtt_offset(vma) + huc->fw.rsa_offset; > + > + ret = intel_guc_send(guc, data, ARRAY_SIZE(data)); > + if (ret) { > + DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret); > + goto out; > + } > + > + /* Check authentication status, it should be done by now */ > + ret = intel_wait_for_register(dev_priv, > + HUC_STATUS2, > + HUC_FW_VERIFIED, > + HUC_FW_VERIFIED, > + 50); > + > + if (ret) { > + DRM_ERROR("HuC: Authentication failed %d\n", ret); > + goto out; > + } > + > + DRM_ERROR("HuC Authentication Successful!\n"); Probably don't want to proclaim using the HuC as an error ;-) -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH 7/8] drm/i915/huc: Support HuC authentication 2017-01-13 17:24 ` Chris Wilson @ 2017-01-13 17:36 ` Srivatsa, Anusha 0 siblings, 0 replies; 43+ messages in thread From: Srivatsa, Anusha @ 2017-01-13 17:36 UTC (permalink / raw) To: Chris Wilson; +Cc: intel-gfx >-----Original Message----- >From: Chris Wilson [mailto:chris@chris-wilson.co.uk] >Sent: Friday, January 13, 2017 9:25 AM >To: Srivatsa, Anusha <anusha.srivatsa@intel.com> >Cc: intel-gfx@lists.freedesktop.org; Hiler, Arkadiusz <arkadiusz.hiler@intel.com>; >Wajdeczko, Michal <Michal.Wajdeczko@intel.com>; Alex Dai ><yu.dai@intel.com>; Peter Antoine <peter.antoine@intel.com> >Subject: Re: [PATCH 7/8] drm/i915/huc: Support HuC authentication > >On Fri, Jan 13, 2017 at 09:07:08AM -0800, Anusha Srivatsa wrote: >> +/** >> + * intel_guc_auth_huc() - authenticate ucode >> + * @dev_priv: the drm_i915_device >> + * >> + * Triggers a HuC fw authentication request to the GuC via >> +intel_guc_action_ >> + * authenticate_huc interface. >> + */ >> +void intel_guc_auth_huc(struct drm_i915_private *dev_priv) { >> + struct intel_guc *guc = &dev_priv->guc; >> + struct intel_huc *huc = &dev_priv->huc; >> + struct i915_vma *vma; >> + int ret; >> + u32 data[2]; >> + >> + vma = i915_gem_object_ggtt_pin(huc->fw.obj, NULL, 0, 0, >> + PIN_OFFSET_BIAS | GUC_WOPCM_TOP); >> + if (IS_ERR(vma)) { >> + DRM_ERROR("failed to pin huc fw object %d\n", >> + (int)PTR_ERR(vma)); >> + return; >> + } >> + >> + /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */ >> + I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); >> + >> + /* Specify auth action and where public signature is. */ >> + data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC; >> + data[1] = i915_ggtt_offset(vma) + huc->fw.rsa_offset; >> + >> + ret = intel_guc_send(guc, data, ARRAY_SIZE(data)); >> + if (ret) { >> + DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret); >> + goto out; >> + } >> + >> + /* Check authentication status, it should be done by now */ >> + ret = intel_wait_for_register(dev_priv, >> + HUC_STATUS2, >> + HUC_FW_VERIFIED, >> + HUC_FW_VERIFIED, >> + 50); >> + >> + if (ret) { >> + DRM_ERROR("HuC: Authentication failed %d\n", ret); >> + goto out; >> + } >> + >> + DRM_ERROR("HuC Authentication Successful!\n"); > >Probably don't want to proclaim using the HuC as an error ;-) -Chris Oh... I was actually thinking it is good if it proclaimed.... Wont it be useful message to know? Anusha >-- >Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH 0/8] HuC Loading Patches @ 2017-01-04 14:55 Anusha Srivatsa 2017-01-04 14:55 ` [PATCH 7/8] drm/i915/huc: Support HuC authentication Anusha Srivatsa 0 siblings, 1 reply; 43+ messages in thread From: Anusha Srivatsa @ 2017-01-04 14:55 UTC (permalink / raw) To: intel-gfx These patches add HuC loading support. The driver builds a frame level workload which is stored in the graphics memory. This workload is presented to HuC for processing. The driver, therefore should first determine if the HuC is enabled and also read the huC athentication status bit to determine if HuC was successfully loaded. The GuC is required to authenticate the HuC. The userspace patches that check for a fully loaded HuC firmware and use it can be found at: https://lists.freedesktop.org/archives/libva/2016-September/004554.html https://lists.freedesktop.org/archives/libva/2016-September/004555.html More information regarding the HuC, batch commands that configure the HuC etc can be found at- https://01.org/sites/default/files/documentation/intel-gfx-prm-osrc-skl-vol02a-commandreference-instructions-huc.pdf https://www.x.org/docs/intel/CHV/intel-gfx-prm-osrc-chv-bsw-vol10-hevc.pdf v2: rebased. v3: rebased. Changed the code following the review comments. v4: Added action_lock initialization fix provided by Arek (Hiler Arkadiusz) to the first patch in the series- Make the GuC fw loading helper functions general. v5: rebased on top of drm-tip. The patch series is now in sync with GuC code reorganization efforts by Arek- https://patchwork.freedesktop.org/series/15896/ v6:rebased. Organize code. Move contents of intel_huc.h to intel_uc.h. Update function intel_huc_load(),intel_huc_init() and intel_uc_fw_fetch() to accept dev_priv instead of dev. v7: rebased. Remove intel_is_huc_valid() since it is called onoly once. Refactor the code to reduce redundency. Remove fiels like uc_dev which are no longer used. v8: rebased. Beautify the code- remove comments that no longer hold good, add newlines etc. v9: rebased. Remove further redundency. Correct comments. Replace wait_for with intel_wait_for_register() for optimisation purpose.Make fw_type an enum. Anusha Srivatsa (3): drm/i915/huc: Add HuC fw loading support drm/i915/huc: Add BXT HuC Loading Support drm/i915/HuC: Add KBL huC loading Support Peter Antoine (5): drm/i915/guc: Make the GuC fw loading helper functions general drm/i915/huc: Unified css_header struct for GuC and HuC drm/i915/huc: Add debugfs for HuC loading status check drm/i915/huc: Support HuC authentication drm/i915/get_params: Add HuC status to getparams drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/i915_debugfs.c | 43 ++++- drivers/gpu/drm/i915/i915_drv.c | 11 +- drivers/gpu/drm/i915/i915_drv.h | 3 +- drivers/gpu/drm/i915/i915_guc_reg.h | 3 + drivers/gpu/drm/i915/i915_guc_submission.c | 4 +- drivers/gpu/drm/i915/intel_guc_fwif.h | 24 ++- drivers/gpu/drm/i915/intel_guc_loader.c | 200 ++++++++++---------- drivers/gpu/drm/i915/intel_huc_loader.c | 283 +++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_uc.c | 68 ++++++- drivers/gpu/drm/i915/intel_uc.h | 64 +++++-- include/uapi/drm/i915_drm.h | 1 + 12 files changed, 579 insertions(+), 126 deletions(-) create mode 100644 drivers/gpu/drm/i915/intel_huc_loader.c -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH 7/8] drm/i915/huc: Support HuC authentication 2017-01-04 14:55 [PATCH 0/8] HuC Loading Patches Anusha Srivatsa @ 2017-01-04 14:55 ` Anusha Srivatsa 2017-01-05 12:14 ` Arkadiusz Hiler ` (2 more replies) 0 siblings, 3 replies; 43+ messages in thread From: Anusha Srivatsa @ 2017-01-04 14:55 UTC (permalink / raw) To: intel-gfx; +Cc: Peter Antoine, Michal Wajdeczko, Alex Dai From: Peter Antoine <peter.antoine@intel.com> The HuC authentication is done by host2guc call. The HuC RSA keys are sent to GuC for authentication. v2: rebased on top of drm-intel-nightly. changed name format and upped version 1.7. v3: rebased on top of drm-intel-nightly. v4: changed wait_for_automic to wait_for v5: rebased. v7: rebased. v8: rebased. v9: rebased. Rename intel_huc_auh() to intel_guc_auth_huc() and place the prototype in intel_guc.h,correct the comments. v10: rebased. v11: rebased. v12: rebased on top of drm-tip v13: rebased. Moved intel_guc_auth_huc from i915_guc_submission.c to intel_uc.c.Update dev to dev_priv in intel_guc_auth_huc(). Renamed HOST2GUC_ACTION_AUTHENTICATE_HUC TO INTEL_GUC_ACTION_ AUTHENTICATE_HUC v14: rebased. v15: rebased. Add newline on DRM_ERRORs that already dont have one. v16: rebased. Replace wait_for with intel_wait_for_register() since the latter employs sleep optimisations for quick responses- as pointed out by Chris Wilson. Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com> Cc: Michal Wajdeczko <michal.wajdecko@intel.com> Tested-by: Xiang Haihao <haihao.xiang@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Alex Dai <yu.dai@intel.com> Signed-off-by: Peter Antoine <peter.antoine@intel.com> --- drivers/gpu/drm/i915/intel_guc_fwif.h | 1 + drivers/gpu/drm/i915/intel_guc_loader.c | 2 + drivers/gpu/drm/i915/intel_uc.c | 70 ++++++++++++++++++++++++++++++++- drivers/gpu/drm/i915/intel_uc.h | 1 + 4 files changed, 72 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h index ed1ab40..ce4e05e 100644 --- a/drivers/gpu/drm/i915/intel_guc_fwif.h +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h @@ -506,6 +506,7 @@ enum intel_guc_action { INTEL_GUC_ACTION_EXIT_S_STATE = 0x502, INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003, INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000, + INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000, INTEL_GUC_ACTION_LIMIT }; diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c index ed57ab3..0508054 100644 --- a/drivers/gpu/drm/i915/intel_guc_loader.c +++ b/drivers/gpu/drm/i915/intel_guc_loader.c @@ -529,6 +529,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv) intel_uc_fw_status_repr(guc_fw->fetch_status), intel_uc_fw_status_repr(guc_fw->load_status)); + intel_guc_auth_huc(dev_priv); + if (i915.enable_guc_submission) { if (i915.guc_log_level >= 0) gen9_enable_guc_interrupts(dev_priv); diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c index c6be352..d1a4d79 100644 --- a/drivers/gpu/drm/i915/intel_uc.c +++ b/drivers/gpu/drm/i915/intel_uc.c @@ -46,7 +46,7 @@ static bool intel_guc_recv(struct intel_guc *guc, u32 *status) int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len) { struct drm_i915_private *dev_priv = guc_to_i915(guc); - u32 status; + u32 status = 0; int i; int ret; @@ -71,7 +71,11 @@ int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len) * up to that length of time, then switch to a slower sleep-wait loop. * No inte_guc_send command should ever take longer than 10ms. */ - ret = wait_for_us(intel_guc_recv(guc, &status), 10); + ret = intel_wait_for_register(dev_priv, + HUC_STATUS2, + HUC_FW_VERIFIED, + HUC_FW_VERIFIED, + 50); if (ret) ret = wait_for(intel_guc_recv(guc, &status), 10); if (status != INTEL_GUC_STATUS_SUCCESS) { @@ -140,3 +144,65 @@ int intel_guc_log_control(struct intel_guc *guc, u32 control_val) return intel_guc_send(guc, action, ARRAY_SIZE(action)); } + +/** + * intel_guc_auth_huc() - authenticate ucode + * @dev_priv: the drm_i915_device + * + * Triggers a HuC fw authentication request to the GuC via intel_guc_action_ + * authenticate_huc interface. + * interface. + */ +void intel_guc_auth_huc(struct drm_i915_private *dev_priv) +{ + struct intel_guc *guc = &dev_priv->guc; + struct intel_huc *huc = &dev_priv->huc; + struct i915_vma *vma; + int ret; + u32 data[2]; + + /* Bypass the case where there is no HuC firmware */ + if (huc->fw.fetch_status == INTEL_UC_FIRMWARE_NONE || + huc->fw.load_status == INTEL_UC_FIRMWARE_NONE) + return; + + if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS) { + DRM_ERROR("HuC: GuC fw wasn't loaded. Can't authenticate\n"); + return; + } + + if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS) { + DRM_ERROR("HuC: fw wasn't loaded. Nothing to authenticate\n"); + return; + } + + vma = i915_gem_object_ggtt_pin(huc->fw.obj, NULL, 0, 0, 0); + if (IS_ERR(vma)) { + DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma)); + return; + } + + + /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */ + I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); + + /* Specify auth action and where public signature is. */ + data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC; + data[1] = i915_ggtt_offset(vma) + huc->fw.rsa_offset; + + ret = intel_guc_send(guc, data, ARRAY_SIZE(data)); + if (ret) { + DRM_ERROR("HuC: GuC did not ack Auth request\n"); + goto out; + } + + /* Check authentication status, it should be done by now */ + ret = wait_for((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) > 0, 50); + if (ret) { + DRM_ERROR("HuC: Authentication failed\n"); + goto out; + } + +out: + i915_vma_unpin(vma); +} diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h index 7df57c1..6ba56e18 100644 --- a/drivers/gpu/drm/i915/intel_uc.h +++ b/drivers/gpu/drm/i915/intel_uc.h @@ -193,6 +193,7 @@ int intel_guc_sample_forcewake(struct intel_guc *guc); int intel_guc_log_flush_complete(struct intel_guc *guc); int intel_guc_log_flush(struct intel_guc *guc); int intel_guc_log_control(struct intel_guc *guc, u32 control_val); +void intel_guc_auth_huc(struct drm_i915_private *dev_priv); /* intel_guc_loader.c */ extern void intel_guc_init(struct drm_i915_private *dev_priv); -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 43+ messages in thread
* Re: [PATCH 7/8] drm/i915/huc: Support HuC authentication 2017-01-04 14:55 ` [PATCH 7/8] drm/i915/huc: Support HuC authentication Anusha Srivatsa @ 2017-01-05 12:14 ` Arkadiusz Hiler 2017-01-05 12:18 ` Arkadiusz Hiler 2017-01-05 13:52 ` Michal Wajdeczko 2 siblings, 0 replies; 43+ messages in thread From: Arkadiusz Hiler @ 2017-01-05 12:14 UTC (permalink / raw) To: Anusha Srivatsa; +Cc: intel-gfx, Michal Wajdeczko On Wed, Jan 04, 2017 at 06:55:54AM -0800, Anusha Srivatsa wrote: > From: Peter Antoine <peter.antoine@intel.com> > > The HuC authentication is done by host2guc call. The HuC RSA keys > are sent to GuC for authentication. > > v2: rebased on top of drm-intel-nightly. > changed name format and upped version 1.7. > v3: rebased on top of drm-intel-nightly. > v4: changed wait_for_automic to wait_for > v5: rebased. > v7: rebased. > v8: rebased. > v9: rebased. Rename intel_huc_auh() to intel_guc_auth_huc() > and place the prototype in intel_guc.h,correct the comments. > v10: rebased. > v11: rebased. > v12: rebased on top of drm-tip > v13: rebased. Moved intel_guc_auth_huc from i915_guc_submission.c > to intel_uc.c.Update dev to dev_priv in intel_guc_auth_huc(). > Renamed HOST2GUC_ACTION_AUTHENTICATE_HUC TO INTEL_GUC_ACTION_ > AUTHENTICATE_HUC > v14: rebased. > v15: rebased. Add newline on DRM_ERRORs that already dont have one. > v16: rebased. Replace wait_for with intel_wait_for_register() since > the latter employs sleep optimisations for quick responses- as pointed > out by Chris Wilson. > > Cc: Chris Wilson <chris@chris-wilson.co.uk> > Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com> > Cc: Michal Wajdeczko <michal.wajdecko@intel.com> > Tested-by: Xiang Haihao <haihao.xiang@intel.com> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> > Signed-off-by: Alex Dai <yu.dai@intel.com> > Signed-off-by: Peter Antoine <peter.antoine@intel.com> > --- > drivers/gpu/drm/i915/intel_guc_fwif.h | 1 + > drivers/gpu/drm/i915/intel_guc_loader.c | 2 + > drivers/gpu/drm/i915/intel_uc.c | 70 ++++++++++++++++++++++++++++++++- > drivers/gpu/drm/i915/intel_uc.h | 1 + > 4 files changed, 72 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h > index ed1ab40..ce4e05e 100644 > --- a/drivers/gpu/drm/i915/intel_guc_fwif.h > +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h > @@ -506,6 +506,7 @@ enum intel_guc_action { > INTEL_GUC_ACTION_EXIT_S_STATE = 0x502, > INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003, > INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000, > + INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000, > INTEL_GUC_ACTION_LIMIT > }; > > diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c > index ed57ab3..0508054 100644 > --- a/drivers/gpu/drm/i915/intel_guc_loader.c > +++ b/drivers/gpu/drm/i915/intel_guc_loader.c > @@ -529,6 +529,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv) > intel_uc_fw_status_repr(guc_fw->fetch_status), > intel_uc_fw_status_repr(guc_fw->load_status)); > > + intel_guc_auth_huc(dev_priv); > + > if (i915.enable_guc_submission) { > if (i915.guc_log_level >= 0) > gen9_enable_guc_interrupts(dev_priv); > diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c > index c6be352..d1a4d79 100644 > --- a/drivers/gpu/drm/i915/intel_uc.c > +++ b/drivers/gpu/drm/i915/intel_uc.c > @@ -46,7 +46,7 @@ static bool intel_guc_recv(struct intel_guc *guc, u32 *status) > int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len) > { > struct drm_i915_private *dev_priv = guc_to_i915(guc); > - u32 status; > + u32 status = 0; > int i; > int ret; > > @@ -71,7 +71,11 @@ int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len) > * up to that length of time, then switch to a slower sleep-wait loop. > * No inte_guc_send command should ever take longer than 10ms. > */ > - ret = wait_for_us(intel_guc_recv(guc, &status), 10); > + ret = intel_wait_for_register(dev_priv, > + HUC_STATUS2, > + HUC_FW_VERIFIED, > + HUC_FW_VERIFIED, > + 50); Why do all suddenly intel_guc_send() starts caring about HUC? I think you've misplaced the check, missed that you were in the wrong place and "fixed" status not being set properly by initializing it with the 0. > if (ret) > ret = wait_for(intel_guc_recv(guc, &status), 10); > if (status != INTEL_GUC_STATUS_SUCCESS) { > @@ -140,3 +144,65 @@ int intel_guc_log_control(struct intel_guc *guc, u32 control_val) > > return intel_guc_send(guc, action, ARRAY_SIZE(action)); > } > + > +/** > + * intel_guc_auth_huc() - authenticate ucode > + * @dev_priv: the drm_i915_device > + * > + * Triggers a HuC fw authentication request to the GuC via intel_guc_action_ > + * authenticate_huc interface. > + * interface. > + */ > +void intel_guc_auth_huc(struct drm_i915_private *dev_priv) > +{ > + struct intel_guc *guc = &dev_priv->guc; > + struct intel_huc *huc = &dev_priv->huc; > + struct i915_vma *vma; > + int ret; > + u32 data[2]; > + > + /* Bypass the case where there is no HuC firmware */ > + if (huc->fw.fetch_status == INTEL_UC_FIRMWARE_NONE || > + huc->fw.load_status == INTEL_UC_FIRMWARE_NONE) > + return; > + > + if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS) { > + DRM_ERROR("HuC: GuC fw wasn't loaded. Can't authenticate\n"); > + return; > + } > + > + if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS) { > + DRM_ERROR("HuC: fw wasn't loaded. Nothing to authenticate\n"); > + return; > + } > + > + vma = i915_gem_object_ggtt_pin(huc->fw.obj, NULL, 0, 0, 0); > + if (IS_ERR(vma)) { > + DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma)); > + return; > + } > + > + > + /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */ > + I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); > + > + /* Specify auth action and where public signature is. */ > + data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC; > + data[1] = i915_ggtt_offset(vma) + huc->fw.rsa_offset; > + > + ret = intel_guc_send(guc, data, ARRAY_SIZE(data)); > + if (ret) { > + DRM_ERROR("HuC: GuC did not ack Auth request\n"); > + goto out; > + } > + > + /* Check authentication status, it should be done by now */ > + ret = wait_for((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) > 0, 50); That's probably the wait_for() you intended to change. > + if (ret) { > + DRM_ERROR("HuC: Authentication failed\n"); > + goto out; > + } > + > +out: > + i915_vma_unpin(vma); > +} > diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h > index 7df57c1..6ba56e18 100644 > --- a/drivers/gpu/drm/i915/intel_uc.h > +++ b/drivers/gpu/drm/i915/intel_uc.h > @@ -193,6 +193,7 @@ int intel_guc_sample_forcewake(struct intel_guc *guc); > int intel_guc_log_flush_complete(struct intel_guc *guc); > int intel_guc_log_flush(struct intel_guc *guc); > int intel_guc_log_control(struct intel_guc *guc, u32 control_val); > +void intel_guc_auth_huc(struct drm_i915_private *dev_priv); > > /* intel_guc_loader.c */ > extern void intel_guc_init(struct drm_i915_private *dev_priv); > -- > 2.7.4 > -- Cheers, Arek _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH 7/8] drm/i915/huc: Support HuC authentication 2017-01-04 14:55 ` [PATCH 7/8] drm/i915/huc: Support HuC authentication Anusha Srivatsa 2017-01-05 12:14 ` Arkadiusz Hiler @ 2017-01-05 12:18 ` Arkadiusz Hiler 2017-01-05 13:52 ` Michal Wajdeczko 2 siblings, 0 replies; 43+ messages in thread From: Arkadiusz Hiler @ 2017-01-05 12:18 UTC (permalink / raw) To: Anusha Srivatsa; +Cc: intel-gfx On Wed, Jan 04, 2017 at 06:55:54AM -0800, Anusha Srivatsa wrote: > From: Peter Antoine <peter.antoine@intel.com> > > The HuC authentication is done by host2guc call. The HuC RSA keys > are sent to GuC for authentication. > > v2: rebased on top of drm-intel-nightly. > changed name format and upped version 1.7. > v3: rebased on top of drm-intel-nightly. > v4: changed wait_for_automic to wait_for > v5: rebased. > v7: rebased. > v8: rebased. > v9: rebased. Rename intel_huc_auh() to intel_guc_auth_huc() > and place the prototype in intel_guc.h,correct the comments. > v10: rebased. > v11: rebased. > v12: rebased on top of drm-tip > v13: rebased. Moved intel_guc_auth_huc from i915_guc_submission.c > to intel_uc.c.Update dev to dev_priv in intel_guc_auth_huc(). > Renamed HOST2GUC_ACTION_AUTHENTICATE_HUC TO INTEL_GUC_ACTION_ > AUTHENTICATE_HUC > v14: rebased. > v15: rebased. Add newline on DRM_ERRORs that already dont have one. > v16: rebased. Replace wait_for with intel_wait_for_register() since > the latter employs sleep optimisations for quick responses- as pointed > out by Chris Wilson. > > Cc: Chris Wilson <chris@chris-wilson.co.uk> > Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com> > Cc: Michal Wajdeczko <michal.wajdecko@intel.com> Typo in Michal's address. > Tested-by: Xiang Haihao <haihao.xiang@intel.com> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> > Signed-off-by: Alex Dai <yu.dai@intel.com> > Signed-off-by: Peter Antoine <peter.antoine@intel.com> -- Cheers, Arek _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH 7/8] drm/i915/huc: Support HuC authentication 2017-01-04 14:55 ` [PATCH 7/8] drm/i915/huc: Support HuC authentication Anusha Srivatsa 2017-01-05 12:14 ` Arkadiusz Hiler 2017-01-05 12:18 ` Arkadiusz Hiler @ 2017-01-05 13:52 ` Michal Wajdeczko 2 siblings, 0 replies; 43+ messages in thread From: Michal Wajdeczko @ 2017-01-05 13:52 UTC (permalink / raw) To: Anusha Srivatsa; +Cc: intel-gfx On Wed, Jan 04, 2017 at 06:55:54AM -0800, Anusha Srivatsa wrote: > From: Peter Antoine <peter.antoine@intel.com> > > The HuC authentication is done by host2guc call. The HuC RSA keys > are sent to GuC for authentication. > > v2: rebased on top of drm-intel-nightly. > changed name format and upped version 1.7. > v3: rebased on top of drm-intel-nightly. > v4: changed wait_for_automic to wait_for > v5: rebased. > v7: rebased. > v8: rebased. > v9: rebased. Rename intel_huc_auh() to intel_guc_auth_huc() > and place the prototype in intel_guc.h,correct the comments. > v10: rebased. > v11: rebased. > v12: rebased on top of drm-tip > v13: rebased. Moved intel_guc_auth_huc from i915_guc_submission.c > to intel_uc.c.Update dev to dev_priv in intel_guc_auth_huc(). > Renamed HOST2GUC_ACTION_AUTHENTICATE_HUC TO INTEL_GUC_ACTION_ > AUTHENTICATE_HUC > v14: rebased. > v15: rebased. Add newline on DRM_ERRORs that already dont have one. > v16: rebased. Replace wait_for with intel_wait_for_register() since > the latter employs sleep optimisations for quick responses- as pointed > out by Chris Wilson. > > Cc: Chris Wilson <chris@chris-wilson.co.uk> > Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com> > Cc: Michal Wajdeczko <michal.wajdecko@intel.com> Typo in my email ;( > Tested-by: Xiang Haihao <haihao.xiang@intel.com> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> > Signed-off-by: Alex Dai <yu.dai@intel.com> > Signed-off-by: Peter Antoine <peter.antoine@intel.com> > --- > drivers/gpu/drm/i915/intel_guc_fwif.h | 1 + > drivers/gpu/drm/i915/intel_guc_loader.c | 2 + > drivers/gpu/drm/i915/intel_uc.c | 70 ++++++++++++++++++++++++++++++++- > drivers/gpu/drm/i915/intel_uc.h | 1 + > 4 files changed, 72 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h > index ed1ab40..ce4e05e 100644 > --- a/drivers/gpu/drm/i915/intel_guc_fwif.h > +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h > @@ -506,6 +506,7 @@ enum intel_guc_action { > INTEL_GUC_ACTION_EXIT_S_STATE = 0x502, > INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003, > INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000, > + INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000, Can we keep actions in order of their code values? > INTEL_GUC_ACTION_LIMIT > }; > > diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c > index ed57ab3..0508054 100644 > --- a/drivers/gpu/drm/i915/intel_guc_loader.c > +++ b/drivers/gpu/drm/i915/intel_guc_loader.c > @@ -529,6 +529,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv) > intel_uc_fw_status_repr(guc_fw->fetch_status), > intel_uc_fw_status_repr(guc_fw->load_status)); > > + intel_guc_auth_huc(dev_priv); > + > if (i915.enable_guc_submission) { > if (i915.guc_log_level >= 0) > gen9_enable_guc_interrupts(dev_priv); > diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c > index c6be352..d1a4d79 100644 > --- a/drivers/gpu/drm/i915/intel_uc.c > +++ b/drivers/gpu/drm/i915/intel_uc.c > @@ -46,7 +46,7 @@ static bool intel_guc_recv(struct intel_guc *guc, u32 *status) > int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len) > { > struct drm_i915_private *dev_priv = guc_to_i915(guc); > - u32 status; > + u32 status = 0; > int i; > int ret; > > @@ -71,7 +71,11 @@ int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len) > * up to that length of time, then switch to a slower sleep-wait loop. > * No inte_guc_send command should ever take longer than 10ms. > */ > - ret = wait_for_us(intel_guc_recv(guc, &status), 10); > + ret = intel_wait_for_register(dev_priv, > + HUC_STATUS2, > + HUC_FW_VERIFIED, > + HUC_FW_VERIFIED, > + 50); > if (ret) > ret = wait_for(intel_guc_recv(guc, &status), 10); > if (status != INTEL_GUC_STATUS_SUCCESS) { > @@ -140,3 +144,65 @@ int intel_guc_log_control(struct intel_guc *guc, u32 control_val) > > return intel_guc_send(guc, action, ARRAY_SIZE(action)); > } > + > +/** > + * intel_guc_auth_huc() - authenticate ucode > + * @dev_priv: the drm_i915_device > + * > + * Triggers a HuC fw authentication request to the GuC via intel_guc_action_ > + * authenticate_huc interface. > + * interface. > + */ > +void intel_guc_auth_huc(struct drm_i915_private *dev_priv) > +{ > + struct intel_guc *guc = &dev_priv->guc; > + struct intel_huc *huc = &dev_priv->huc; > + struct i915_vma *vma; > + int ret; > + u32 data[2]; > + > + /* Bypass the case where there is no HuC firmware */ > + if (huc->fw.fetch_status == INTEL_UC_FIRMWARE_NONE || > + huc->fw.load_status == INTEL_UC_FIRMWARE_NONE) To catch the case when there is no Huc fw, maybe only first check is needed as in intel_huc_load()? > + return; > + > + if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS) { > + DRM_ERROR("HuC: GuC fw wasn't loaded. Can't authenticate\n"); This shall never happen as this function is called from guc_setup() only after successful guc fw load. > + return; > + } > + > + if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS) { > + DRM_ERROR("HuC: fw wasn't loaded. Nothing to authenticate\n"); Hmm, we should already have error message about failed huc fw loading. Do we need to report other obvious failures? > + return; > + } > + > + vma = i915_gem_object_ggtt_pin(huc->fw.obj, NULL, 0, 0, 0); > + if (IS_ERR(vma)) { > + DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma)); Please be more descriptive, what about "failed to pin huc fw obj" ? > + return; > + } > + > + > + /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */ > + I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); > + > + /* Specify auth action and where public signature is. */ > + data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC; > + data[1] = i915_ggtt_offset(vma) + huc->fw.rsa_offset; > + > + ret = intel_guc_send(guc, data, ARRAY_SIZE(data)); > + if (ret) { > + DRM_ERROR("HuC: GuC did not ack Auth request\n"); > + goto out; > + } > + > + /* Check authentication status, it should be done by now */ > + ret = wait_for((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) > 0, 50); > + if (ret) { > + DRM_ERROR("HuC: Authentication failed\n"); > + goto out; > + } > + In other place you said: "I think we need a message for the case when there is no failure." What about adding message here that confirms Huc authentication? > +out: > + i915_vma_unpin(vma); > +} > diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h > index 7df57c1..6ba56e18 100644 > --- a/drivers/gpu/drm/i915/intel_uc.h > +++ b/drivers/gpu/drm/i915/intel_uc.h > @@ -193,6 +193,7 @@ int intel_guc_sample_forcewake(struct intel_guc *guc); > int intel_guc_log_flush_complete(struct intel_guc *guc); > int intel_guc_log_flush(struct intel_guc *guc); > int intel_guc_log_control(struct intel_guc *guc, u32 control_val); > +void intel_guc_auth_huc(struct drm_i915_private *dev_priv); > > /* intel_guc_loader.c */ > extern void intel_guc_init(struct drm_i915_private *dev_priv); > -- > 2.7.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH 0/8] HuC Loading Patches @ 2017-01-04 13:27 Anusha Srivatsa 2017-01-04 13:27 ` [PATCH 7/8] drm/i915/huc: Support HuC authentication Anusha Srivatsa 0 siblings, 1 reply; 43+ messages in thread From: Anusha Srivatsa @ 2017-01-04 13:27 UTC (permalink / raw) To: intel-gfx These patches add HuC loading support. The driver builds a frame level workload which is stored in the graphics memory. This workload is presented to HuC for processing. The driver, therefore should first determine if the HuC is enabled and also read the huC athentication status bit to determine if HuC was successfully loaded. The GuC is required to authenticate the HuC. The userspace patches that check for a fully loaded HuC firmware and use it can be found at: https://lists.freedesktop.org/archives/libva/2016-September/004554.html https://lists.freedesktop.org/archives/libva/2016-September/004555.html More information regarding the HuC, batch commands that configure the HuC etc can be found at- https://01.org/sites/default/files/documentation/intel-gfx-prm-osrc-skl-vol02a-commandreference-instructions-huc.pdf https://www.x.org/docs/intel/CHV/intel-gfx-prm-osrc-chv-bsw-vol10-hevc.pdf v2: rebased. v3: rebased. Changed the code following the review comments. v4: Added action_lock initialization fix provided by Arek (Hiler Arkadiusz) to the first patch in the series- Make the GuC fw loading helper functions general. v5: rebased on top of drm-tip. The patch series is now in sync with GuC code reorganization efforts by Arek- https://patchwork.freedesktop.org/series/15896/ v6:rebased. Organize code. Move contents of intel_huc.h to intel_uc.h. Update function intel_huc_load(),intel_huc_init() and intel_uc_fw_fetch() to accept dev_priv instead of dev. v7: rebased. Remove intel_is_huc_valid() since it is called onoly once. Refactor the code to reduce redundency. Remove fiels like uc_dev which are no longer used. v8: rebased. Beautify the code- remove comments that no longer hold good, add newlines etc. v9: rebased. Remove further redundency. Correct comments. Replace wait_for with intel_wait_for_register() for optimisation purpose.Make fw_type an enum. Anusha Srivatsa (3): drm/i915/huc: Add HuC fw loading support drm/i915/huc: Add BXT HuC Loading Support drm/i915/HuC: Add KBL huC loading Support Peter Antoine (5): drm/i915/guc: Make the GuC fw loading helper functions general drm/i915/huc: Unified css_header struct for GuC and HuC drm/i915/huc: Add debugfs for HuC loading status check drm/i915/huc: Support HuC authentication drm/i915/get_params: Add HuC status to getparams drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/i915_debugfs.c | 43 ++++- drivers/gpu/drm/i915/i915_drv.c | 11 +- drivers/gpu/drm/i915/i915_drv.h | 3 +- drivers/gpu/drm/i915/i915_guc_reg.h | 3 + drivers/gpu/drm/i915/i915_guc_submission.c | 4 +- drivers/gpu/drm/i915/intel_guc_fwif.h | 24 ++- drivers/gpu/drm/i915/intel_guc_loader.c | 200 ++++++++++---------- drivers/gpu/drm/i915/intel_huc_loader.c | 283 +++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_uc.c | 68 ++++++- drivers/gpu/drm/i915/intel_uc.h | 64 +++++-- include/uapi/drm/i915_drm.h | 1 + 12 files changed, 579 insertions(+), 126 deletions(-) create mode 100644 drivers/gpu/drm/i915/intel_huc_loader.c -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH 7/8] drm/i915/huc: Support HuC authentication 2017-01-04 13:27 [PATCH 0/8] HuC Loading Patches Anusha Srivatsa @ 2017-01-04 13:27 ` Anusha Srivatsa 0 siblings, 0 replies; 43+ messages in thread From: Anusha Srivatsa @ 2017-01-04 13:27 UTC (permalink / raw) To: intel-gfx; +Cc: Peter Antoine, Michal Wajdeczko, Alex Dai From: Peter Antoine <peter.antoine@intel.com> The HuC authentication is done by host2guc call. The HuC RSA keys are sent to GuC for authentication. v2: rebased on top of drm-intel-nightly. changed name format and upped version 1.7. v3: rebased on top of drm-intel-nightly. v4: changed wait_for_automic to wait_for v5: rebased. v7: rebased. v8: rebased. v9: rebased. Rename intel_huc_auh() to intel_guc_auth_huc() and place the prototype in intel_guc.h,correct the comments. v10: rebased. v11: rebased. v12: rebased on top of drm-tip v13: rebased. Moved intel_guc_auth_huc from i915_guc_submission.c to intel_uc.c.Update dev to dev_priv in intel_guc_auth_huc(). Renamed HOST2GUC_ACTION_AUTHENTICATE_HUC TO INTEL_GUC_ACTION_ AUTHENTICATE_HUC v14: rebased. v15: rebased. Add newline on DRM_ERRORs that already dont have one. v16: rebased. Replace wait_for with intel_wait_for_register() since the latter employs sleep optimisations for quick responses- as pointed out by Chris Wilson. Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com> Cc: Michal Wajdeczko <michal.wajdecko@intel.com> Tested-by: Xiang Haihao <haihao.xiang@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Alex Dai <yu.dai@intel.com> Signed-off-by: Peter Antoine <peter.antoine@intel.com> --- drivers/gpu/drm/i915/intel_guc_fwif.h | 1 + drivers/gpu/drm/i915/intel_guc_loader.c | 2 + drivers/gpu/drm/i915/intel_uc.c | 68 ++++++++++++++++++++++++++++++++- drivers/gpu/drm/i915/intel_uc.h | 1 + 4 files changed, 71 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h index ed1ab40..ce4e05e 100644 --- a/drivers/gpu/drm/i915/intel_guc_fwif.h +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h @@ -506,6 +506,7 @@ enum intel_guc_action { INTEL_GUC_ACTION_EXIT_S_STATE = 0x502, INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003, INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000, + INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000, INTEL_GUC_ACTION_LIMIT }; diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c index a6ac046..be76583 100644 --- a/drivers/gpu/drm/i915/intel_guc_loader.c +++ b/drivers/gpu/drm/i915/intel_guc_loader.c @@ -529,6 +529,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv) intel_uc_fw_status_repr(guc_fw->fetch_status), intel_uc_fw_status_repr(guc_fw->load_status)); + intel_guc_auth_huc(dev_priv); + if (i915.enable_guc_submission) { if (i915.guc_log_level >= 0) gen9_enable_guc_interrupts(dev_priv); diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c index c6be352..dccd39c 100644 --- a/drivers/gpu/drm/i915/intel_uc.c +++ b/drivers/gpu/drm/i915/intel_uc.c @@ -71,7 +71,11 @@ int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len) * up to that length of time, then switch to a slower sleep-wait loop. * No inte_guc_send command should ever take longer than 10ms. */ - ret = wait_for_us(intel_guc_recv(guc, &status), 10); + ret = intel_wait_for_register(dev_priv, + HUC_STATUS2, + HUC_FW_VERIFIED, + HUC_FW_VERIFIED, + 50); if (ret) ret = wait_for(intel_guc_recv(guc, &status), 10); if (status != INTEL_GUC_STATUS_SUCCESS) { @@ -140,3 +144,65 @@ int intel_guc_log_control(struct intel_guc *guc, u32 control_val) return intel_guc_send(guc, action, ARRAY_SIZE(action)); } + +/** + * intel_guc_auth_huc() - authenticate ucode + * @dev_priv: the drm_i915_device + * + * Triggers a HuC fw authentication request to the GuC via intel_guc_action_ + * authenticate_huc interface. + * interface. + */ +void intel_guc_auth_huc(struct drm_i915_private *dev_priv) +{ + struct intel_guc *guc = &dev_priv->guc; + struct intel_huc *huc = &dev_priv->huc; + struct i915_vma *vma; + int ret; + u32 data[2]; + + /* Bypass the case where there is no HuC firmware */ + if (huc->fw.fetch_status == INTEL_UC_FIRMWARE_NONE || + huc->fw.load_status == INTEL_UC_FIRMWARE_NONE) + return; + + if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS) { + DRM_ERROR("HuC: GuC fw wasn't loaded. Can't authenticate\n"); + return; + } + + if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS) { + DRM_ERROR("HuC: fw wasn't loaded. Nothing to authenticate\n"); + return; + } + + vma = i915_gem_object_ggtt_pin(huc->fw.uc_fw_obj, NULL, 0, 0, 0); + if (IS_ERR(vma)) { + DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma)); + return; + } + + + /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */ + I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); + + /* Specify auth action and where public signature is. */ + data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC; + data[1] = i915_ggtt_offset(vma) + huc->fw.rsa_offset; + + ret = intel_guc_send(guc, data, ARRAY_SIZE(data)); + if (ret) { + DRM_ERROR("HuC: GuC did not ack Auth request\n"); + goto out; + } + + /* Check authentication status, it should be done by now */ + ret = wait_for((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) > 0, 50); + if (ret) { + DRM_ERROR("HuC: Authentication failed\n"); + goto out; + } + +out: + i915_vma_unpin(vma); +} diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h index 00c0986..2aa0304 100644 --- a/drivers/gpu/drm/i915/intel_uc.h +++ b/drivers/gpu/drm/i915/intel_uc.h @@ -193,6 +193,7 @@ int intel_guc_sample_forcewake(struct intel_guc *guc); int intel_guc_log_flush_complete(struct intel_guc *guc); int intel_guc_log_flush(struct intel_guc *guc); int intel_guc_log_control(struct intel_guc *guc, u32 control_val); +void intel_guc_auth_huc(struct drm_i915_private *dev_priv); /* intel_guc_loader.c */ extern void intel_guc_init(struct drm_i915_private *dev_priv); -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH 0/8] HuC Loading Patches @ 2016-12-22 23:12 Anusha Srivatsa 2016-12-22 23:12 ` [PATCH 7/8] drm/i915/huc: Support HuC authentication Anusha Srivatsa 0 siblings, 1 reply; 43+ messages in thread From: Anusha Srivatsa @ 2016-12-22 23:12 UTC (permalink / raw) To: intel-gfx These patches add HuC loading support. The driver builds a frame level workload which is stored in the graphics memory. This workload is presented to HuC for processing. The driver, therefore should first determine if the HuC is enabled and also read the huC athentication status bit to determine if HuC was successfully loaded. The GuC is required to authenticate the HuC. The userspace patches that check for a fully loaded HuC firmware and use it can be found at: https://lists.freedesktop.org/archives/libva/2016-September/004554.html https://lists.freedesktop.org/archives/libva/2016-September/004555.html More information regarding the HuC, batch commands that configure the HuC etc can be found at- https://01.org/sites/default/files/documentation/intel-gfx-prm-osrc-skl-vol02a-commandreference-instructions-huc.pdf https://www.x.org/docs/intel/CHV/intel-gfx-prm-osrc-chv-bsw-vol10-hevc.pdf v2: rebased. v3: rebased. Changed the code following the review comments. v4: Added action_lock initialization fix provided by Arek (Hiler Arkadiusz) to the first patch in the series- Make the GuC fw loading helper functions general. v5: rebased on top of drm-tip. The patch series is now in sync with GuC code reorganization efforts by Arek- https://patchwork.freedesktop.org/series/15896/ v6:rebased. Organize code. Move contents of intel_huc.h to intel_uc.h. Update function intel_huc_load(),intel_huc_init() and intel_uc_fw_fetch() to accept dev_priv instead of dev. v7: rebased. Remove intel_is_huc_valid() since it is called onoly once. Refactor the code to reduce redundency. Remove fiels like uc_dev which are no longer used. v8: rebased. Beautify the code- remove comments that no longer hold good, add newlines etc. Anusha Srivatsa (3): drm/i915/huc: Add HuC fw loading support drm/i915/huc: Add BXT HuC Loading Support drm/i915/HuC: Add KBL huC loading Support Peter Antoine (5): drm/i915/guc: Make the GuC fw loading helper functions general drm/i915/huc: Unified css_header struct for GuC and HuC drm/i915/huc: Add debugfs for HuC loading status check drm/i915/huc: Support HuC authentication drm/i915/get_params: Add HuC status to getparams drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/i915_debugfs.c | 43 ++++- drivers/gpu/drm/i915/i915_drv.c | 11 +- drivers/gpu/drm/i915/i915_drv.h | 3 +- drivers/gpu/drm/i915/i915_guc_reg.h | 3 + drivers/gpu/drm/i915/i915_guc_submission.c | 4 +- drivers/gpu/drm/i915/intel_guc_fwif.h | 24 ++- drivers/gpu/drm/i915/intel_guc_loader.c | 200 +++++++++++--------- drivers/gpu/drm/i915/intel_huc_loader.c | 286 +++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_uc.c | 62 +++++++ drivers/gpu/drm/i915/intel_uc.h | 63 +++++-- include/uapi/drm/i915_drm.h | 1 + 12 files changed, 577 insertions(+), 124 deletions(-) create mode 100644 drivers/gpu/drm/i915/intel_huc_loader.c -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH 7/8] drm/i915/huc: Support HuC authentication 2016-12-22 23:12 [PATCH 0/8] HuC Loading Patches Anusha Srivatsa @ 2016-12-22 23:12 ` Anusha Srivatsa 2016-12-22 23:30 ` Chris Wilson 0 siblings, 1 reply; 43+ messages in thread From: Anusha Srivatsa @ 2016-12-22 23:12 UTC (permalink / raw) To: intel-gfx; +Cc: Alex Dai, Peter Antoine From: Peter Antoine <peter.antoine@intel.com> The HuC authentication is done by host2guc call. The HuC RSA keys are sent to GuC for authentication. v2: rebased on top of drm-intel-nightly. changed name format and upped version 1.7. v3: rebased on top of drm-intel-nightly. v4: changed wait_for_automic to wait_for v5: rebased. v7: rebased. v8: rebased. v9: rebased. Rename intel_huc_auh() to intel_guc_auth_huc() and place the prototype in intel_guc.h,correct the comments. v10: rebased. v11: rebased. v12: rebased on top of drm-tip v13: rebased. Moved intel_guc_auth_huc from i915_guc_submission.c to intel_uc.c.Update dev to dev_priv in intel_guc_auth_huc(). Renamed HOST2GUC_ACTION_AUTHENTICATE_HUC TO INTEL_GUC_ACTION_ AUTHENTICATE_HUC v14: rebased. v15: rebased. Add newline on DRM_ERRORs that already dont have one. Tested-by: Xiang Haihao <haihao.xiang@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Alex Dai <yu.dai@intel.com> Signed-off-by: Peter Antoine <peter.antoine@intel.com> --- drivers/gpu/drm/i915/intel_guc_fwif.h | 1 + drivers/gpu/drm/i915/intel_guc_loader.c | 2 ++ drivers/gpu/drm/i915/intel_uc.c | 62 +++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_uc.h | 1 + 4 files changed, 66 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h index ed1ab40..ce4e05e 100644 --- a/drivers/gpu/drm/i915/intel_guc_fwif.h +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h @@ -506,6 +506,7 @@ enum intel_guc_action { INTEL_GUC_ACTION_EXIT_S_STATE = 0x502, INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003, INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000, + INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000, INTEL_GUC_ACTION_LIMIT }; diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c index 8c77e94..85c0a2a 100644 --- a/drivers/gpu/drm/i915/intel_guc_loader.c +++ b/drivers/gpu/drm/i915/intel_guc_loader.c @@ -529,6 +529,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv) intel_uc_fw_status_repr(guc_fw->fetch_status), intel_uc_fw_status_repr(guc_fw->load_status)); + intel_guc_auth_huc(dev_priv); + if (i915.enable_guc_submission) { if (i915.guc_log_level >= 0) gen9_enable_guc_interrupts(dev_priv); diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c index 8ae6795..b858d36 100644 --- a/drivers/gpu/drm/i915/intel_uc.c +++ b/drivers/gpu/drm/i915/intel_uc.c @@ -138,3 +138,65 @@ int intel_guc_log_control(struct intel_guc *guc, u32 control_val) return intel_guc_send(guc, action, ARRAY_SIZE(action)); } + +/** + * intel_guc_auth_huc() - authenticate ucode + * @dev_priv: the drm_i915_device + * + * Triggers a HuC fw authentication request to the GuC via intel_guc_action_ + * authenticate_huc interface. + * interface. + */ +void intel_guc_auth_huc(struct drm_i915_private *dev_priv) +{ + struct intel_guc *guc = &dev_priv->guc; + struct intel_huc *huc = &dev_priv->huc; + struct i915_vma *vma; + int ret; + u32 data[2]; + + /* Bypass the case where there is no HuC firmware */ + if (huc->fw.fetch_status == INTEL_UC_FIRMWARE_NONE || + huc->fw.load_status == INTEL_UC_FIRMWARE_NONE) + return; + + if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS) { + DRM_ERROR("HuC: GuC fw wasn't loaded. Can't authenticate\n"); + return; + } + + if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS) { + DRM_ERROR("HuC: fw wasn't loaded. Nothing to authenticate\n"); + return; + } + + vma = i915_gem_object_ggtt_pin(huc->fw.uc_fw_obj, NULL, 0, 0, 0); + if (IS_ERR(vma)) { + DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma)); + return; + } + + + /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */ + I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); + + /* Specify auth action and where public signature is. */ + data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC; + data[1] = i915_ggtt_offset(vma) + huc->fw.rsa_offset; + + ret = intel_guc_send(guc, data, ARRAY_SIZE(data)); + if (ret) { + DRM_ERROR("HuC: GuC did not ack Auth request\n"); + goto out; + } + + /* Check authentication status, it should be done by now */ + ret = wait_for((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) > 0, 50); + if (ret) { + DRM_ERROR("HuC: Authentication failed\n"); + goto out; + } + +out: + i915_vma_unpin(vma); +} diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h index 57aef56..e69d47c 100644 --- a/drivers/gpu/drm/i915/intel_uc.h +++ b/drivers/gpu/drm/i915/intel_uc.h @@ -192,6 +192,7 @@ int intel_guc_sample_forcewake(struct intel_guc *guc); int intel_guc_log_flush_complete(struct intel_guc *guc); int intel_guc_log_flush(struct intel_guc *guc); int intel_guc_log_control(struct intel_guc *guc, u32 control_val); +void intel_guc_auth_huc(struct drm_i915_private *dev_priv); /* intel_guc_loader.c */ extern void intel_guc_init(struct drm_i915_private *dev_priv); -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 43+ messages in thread
* Re: [PATCH 7/8] drm/i915/huc: Support HuC authentication 2016-12-22 23:12 ` [PATCH 7/8] drm/i915/huc: Support HuC authentication Anusha Srivatsa @ 2016-12-22 23:30 ` Chris Wilson 2017-01-03 19:55 ` Srivatsa, Anusha 0 siblings, 1 reply; 43+ messages in thread From: Chris Wilson @ 2016-12-22 23:30 UTC (permalink / raw) To: Anusha Srivatsa; +Cc: intel-gfx, Alex Dai, Peter Antoine On Thu, Dec 22, 2016 at 03:12:23PM -0800, Anusha Srivatsa wrote: > +void intel_guc_auth_huc(struct drm_i915_private *dev_priv) > +{ > + struct intel_guc *guc = &dev_priv->guc; > + struct intel_huc *huc = &dev_priv->huc; > + struct i915_vma *vma; > + int ret; > + u32 data[2]; > + > + /* Bypass the case where there is no HuC firmware */ > + if (huc->fw.fetch_status == INTEL_UC_FIRMWARE_NONE || > + huc->fw.load_status == INTEL_UC_FIRMWARE_NONE) > + return; > + > + if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS) { > + DRM_ERROR("HuC: GuC fw wasn't loaded. Can't authenticate\n"); > + return; > + } > + > + if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS) { > + DRM_ERROR("HuC: fw wasn't loaded. Nothing to authenticate\n"); > + return; > + } > + > + vma = i915_gem_object_ggtt_pin(huc->fw.uc_fw_obj, NULL, 0, 0, 0); > + if (IS_ERR(vma)) { > + DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma)); > + return; > + } > + > + > + /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */ > + I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); Still working on stopping this from frequently popping up in code outside of the GTT routines. > + /* Specify auth action and where public signature is. */ > + data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC; > + data[1] = i915_ggtt_offset(vma) + huc->fw.rsa_offset; > + > + ret = intel_guc_send(guc, data, ARRAY_SIZE(data)); > + if (ret) { > + DRM_ERROR("HuC: GuC did not ack Auth request\n"); > + goto out; > + } > + > + /* Check authentication status, it should be done by now */ > + ret = wait_for((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) > 0, 50); ret = intel_wait_for_register(dev_priv, HUC_STATUS2, HUC_FW_VERIFIED, HUC_FW_VERIFIED, 50); wait_for() is a rather large macro, and intel_wait_for_register() employs the spin then sleep optimisation for quick responses. -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH 7/8] drm/i915/huc: Support HuC authentication 2016-12-22 23:30 ` Chris Wilson @ 2017-01-03 19:55 ` Srivatsa, Anusha 0 siblings, 0 replies; 43+ messages in thread From: Srivatsa, Anusha @ 2017-01-03 19:55 UTC (permalink / raw) To: Chris Wilson; +Cc: intel-gfx, Alex Dai, Peter Antoine >-----Original Message----- >From: Chris Wilson [mailto:chris@chris-wilson.co.uk] >Sent: Thursday, December 22, 2016 3:30 PM >To: Srivatsa, Anusha <anusha.srivatsa@intel.com> >Cc: intel-gfx@lists.freedesktop.org; Alex Dai <yu.dai@intel.com>; Peter Antoine ><peter.antoine@intel.com> >Subject: Re: [Intel-gfx] [PATCH 7/8] drm/i915/huc: Support HuC authentication > >On Thu, Dec 22, 2016 at 03:12:23PM -0800, Anusha Srivatsa wrote: >> +void intel_guc_auth_huc(struct drm_i915_private *dev_priv) { >> + struct intel_guc *guc = &dev_priv->guc; >> + struct intel_huc *huc = &dev_priv->huc; >> + struct i915_vma *vma; >> + int ret; >> + u32 data[2]; >> + >> + /* Bypass the case where there is no HuC firmware */ >> + if (huc->fw.fetch_status == INTEL_UC_FIRMWARE_NONE || >> + huc->fw.load_status == INTEL_UC_FIRMWARE_NONE) >> + return; >> + >> + if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS) { >> + DRM_ERROR("HuC: GuC fw wasn't loaded. Can't >authenticate\n"); >> + return; >> + } >> + >> + if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS) { >> + DRM_ERROR("HuC: fw wasn't loaded. Nothing to >authenticate\n"); >> + return; >> + } >> + >> + vma = i915_gem_object_ggtt_pin(huc->fw.uc_fw_obj, NULL, 0, 0, 0); >> + if (IS_ERR(vma)) { >> + DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma)); >> + return; >> + } >> + >> + >> + /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */ >> + I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); > >Still working on stopping this from frequently popping up in code outside of the >GTT routines. So, basically beautify the code such that the GTT routines do not pop out in non GTT parts of code. Correct? > >> + /* Specify auth action and where public signature is. */ >> + data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC; >> + data[1] = i915_ggtt_offset(vma) + huc->fw.rsa_offset; >> + >> + ret = intel_guc_send(guc, data, ARRAY_SIZE(data)); >> + if (ret) { >> + DRM_ERROR("HuC: GuC did not ack Auth request\n"); >> + goto out; >> + } >> + >> + /* Check authentication status, it should be done by now */ >> + ret = wait_for((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) > 0, >50); > >ret = intel_wait_for_register(dev_priv, > HUC_STATUS2, > HUC_FW_VERIFIED, > HUC_FW_VERIFIED, > 50); > >wait_for() is a rather large macro, and intel_wait_for_register() employs the spin >then sleep optimisation for quick responses. Thankyou for bringing this to my notice. Anusha >-Chris > >-- >Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH 0/8] HuC Loading Patches @ 2016-12-15 22:29 anushasr 2016-12-15 22:29 ` [PATCH 7/8] drm/i915/huc: Support HuC authentication anushasr 0 siblings, 1 reply; 43+ messages in thread From: anushasr @ 2016-12-15 22:29 UTC (permalink / raw) To: intel-gfx These patches add HuC loading support. The driver builds a frame level workload which is stored in the graphics memory. This workload is presented to HuC for processing. The driver, therefore should first determine if the HuC is enabled and also read the huC athentication status bit to determine if HuC was successfully loaded. The GuC is required to authenticate the HuC. The userspace patches that check for a fully loaded HuC firmware and use it can be found at: https://lists.freedesktop.org/archives/libva/2016-September/004554.html https://lists.freedesktop.org/archives/libva/2016-September/004555.html More information regarding the HuC, batch commands that configure the HuC etc can be found at- https://01.org/sites/default/files/documentation/intel-gfx-prm-osrc-skl-vol02a-commandreference-instructions-huc.pdf https://www.x.org/docs/intel/CHV/intel-gfx-prm-osrc-chv-bsw-vol10-hevc.pdf v2: rebased. v3: rebased. Changed the code following the review comments. v4: Added action_lock initialization fix provided by Arek (Hiler Arkadiusz) to the first patch in the series- Make the GuC fw loading helper functions general. v5: rebased on top of drm-tip. The patch series is now in sync with GuC code reorganization efforts by Arek- https://patchwork.freedesktop.org/series/15896/ v6:rebased. Organize code. Move contents of intel_huc.h to intel_uc.h. Update function intel_huc_load(),intel_huc_init() and intel_uc_fw_fetch() to accept dev_priv instead of dev. v7: rebased. Remove intel_is_huc_valid() since it is called onoly once. Refactor the code to reduce redundency. Remove fiels like uc_dev which are no longer used. Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Arek <arkadiusz.hiler@intel.com> Cc: Jeff Mcgee <jeff.mcgee@intel.com> BLURB HERE *** Cc: Chris Wilson <Chris@chris-wilson.co.uk> Anusha Srivatsa (3): drm/i915/huc: Add HuC fw loading support drm/i915/huc: Add BXT HuC Loading Support drm/i915/HuC: Add KBL huC loading Support Peter Antoine (5): drm/i915/guc: Make the GuC fw loading helper functions general drm/i915/huc: Unified css_header struct for GuC and HuC drm/i915/huc: Add debugfs for HuC loading status check drm/i915/huc: Support HuC authentication drm/i915/get_params: Add HuC status to getparams drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/i915_debugfs.c | 43 ++++- drivers/gpu/drm/i915/i915_drv.c | 8 +- drivers/gpu/drm/i915/i915_drv.h | 3 +- drivers/gpu/drm/i915/i915_guc_reg.h | 3 + drivers/gpu/drm/i915/i915_guc_submission.c | 4 +- drivers/gpu/drm/i915/intel_guc_fwif.h | 24 ++- drivers/gpu/drm/i915/intel_guc_loader.c | 201 +++++++++++--------- drivers/gpu/drm/i915/intel_huc_loader.c | 290 +++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_uc.c | 62 ++++++ drivers/gpu/drm/i915/intel_uc.h | 63 +++++-- include/uapi/drm/i915_drm.h | 1 + 12 files changed, 579 insertions(+), 124 deletions(-) create mode 100644 drivers/gpu/drm/i915/intel_huc_loader.c -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH 7/8] drm/i915/huc: Support HuC authentication 2016-12-15 22:29 [PATCH 0/8] HuC Loading Patches anushasr @ 2016-12-15 22:29 ` anushasr 2016-12-16 16:17 ` Arkadiusz Hiler 0 siblings, 1 reply; 43+ messages in thread From: anushasr @ 2016-12-15 22:29 UTC (permalink / raw) To: intel-gfx; +Cc: Alex Dai, Peter Antoine From: Peter Antoine <peter.antoine@intel.com> The HuC authentication is done by host2guc call. The HuC RSA keys are sent to GuC for authentication. v2: rebased on top of drm-intel-nightly. changed name format and upped version 1.7. v3: rebased on top of drm-intel-nightly. v4: changed wait_for_automic to wait_for v5: rebased. v7: rebased. v8: rebased. v9: rebased. Rename intel_huc_auh() to intel_guc_auth_huc() and place the prototype in intel_guc.h,correct the comments. v10: rebased. v11: rebased. v12: rebased on top of drm-tip v13: rebased. Moved intel_guc_auth_huc from i915_guc_submission.c to intel_uc.c.Update dev to dev_priv in intel_guc_auth_huc(). Renamed HOST2GUC_ACTION_AUTHENTICATE_HUC TO INTEL_GUC_ACTION_ AUTHENTICATE_HUC v14: rebased. Tested-by: Xiang Haihao <haihao.xiang@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Alex Dai <yu.dai@intel.com> Signed-off-by: Peter Antoine <peter.antoine@intel.com> --- drivers/gpu/drm/i915/intel_guc_fwif.h | 1 + drivers/gpu/drm/i915/intel_guc_loader.c | 2 ++ drivers/gpu/drm/i915/intel_uc.c | 62 +++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_uc.h | 1 + 4 files changed, 66 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h index ed1ab40..ce4e05e 100644 --- a/drivers/gpu/drm/i915/intel_guc_fwif.h +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h @@ -506,6 +506,7 @@ enum intel_guc_action { INTEL_GUC_ACTION_EXIT_S_STATE = 0x502, INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003, INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000, + INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000, INTEL_GUC_ACTION_LIMIT }; diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c index 2257495..7605f36 100644 --- a/drivers/gpu/drm/i915/intel_guc_loader.c +++ b/drivers/gpu/drm/i915/intel_guc_loader.c @@ -529,6 +529,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv) intel_uc_fw_status_repr(guc_fw->fetch_status), intel_uc_fw_status_repr(guc_fw->load_status)); + intel_guc_auth_huc(dev_priv); + if (i915.enable_guc_submission) { if (i915.guc_log_level >= 0) gen9_enable_guc_interrupts(dev_priv); diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c index 8ae6795..b90ac57 100644 --- a/drivers/gpu/drm/i915/intel_uc.c +++ b/drivers/gpu/drm/i915/intel_uc.c @@ -138,3 +138,65 @@ int intel_guc_log_control(struct intel_guc *guc, u32 control_val) return intel_guc_send(guc, action, ARRAY_SIZE(action)); } + +/** + * intel_guc_auth_huc() - authenticate ucode + * @dev_priv: the drm_i915_device + * + * Triggers a HuC fw authentication request to the GuC via intel_guc_action_ + * authenticate_huc interface. + * interface. + */ +void intel_guc_auth_huc(struct drm_i915_private *dev_priv) +{ + struct intel_guc *guc = &dev_priv->guc; + struct intel_huc *huc = &dev_priv->huc; + struct i915_vma *vma; + int ret; + u32 data[2]; + + /* Bypass the case where there is no HuC firmware */ + if (huc->fw.fetch_status == INTEL_UC_FIRMWARE_NONE || + huc->fw.load_status == INTEL_UC_FIRMWARE_NONE) + return; + + if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS) { + DRM_ERROR("HuC: GuC fw wasn't loaded. Can't authenticate"); + return; + } + + if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS) { + DRM_ERROR("HuC: fw wasn't loaded. Nothing to authenticate"); + return; + } + + vma = i915_gem_object_ggtt_pin(huc->fw.uc_fw_obj, NULL, 0, 0, 0); + if (IS_ERR(vma)) { + DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma)); + return; + } + + + /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */ + I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); + + /* Specify auth action and where public signature is. */ + data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC; + data[1] = i915_ggtt_offset(vma) + huc->fw.rsa_offset; + + ret = intel_guc_send(guc, data, ARRAY_SIZE(data)); + if (ret) { + DRM_ERROR("HuC: GuC did not ack Auth request\n"); + goto out; + } + + /* Check authentication status, it should be done by now */ + ret = wait_for((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) > 0, 50); + if (ret) { + DRM_ERROR("HuC: Authentication failed\n"); + goto out; + } + +out: + i915_vma_unpin(vma); +} diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h index 57aef56..e69d47c 100644 --- a/drivers/gpu/drm/i915/intel_uc.h +++ b/drivers/gpu/drm/i915/intel_uc.h @@ -192,6 +192,7 @@ int intel_guc_sample_forcewake(struct intel_guc *guc); int intel_guc_log_flush_complete(struct intel_guc *guc); int intel_guc_log_flush(struct intel_guc *guc); int intel_guc_log_control(struct intel_guc *guc, u32 control_val); +void intel_guc_auth_huc(struct drm_i915_private *dev_priv); /* intel_guc_loader.c */ extern void intel_guc_init(struct drm_i915_private *dev_priv); -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 43+ messages in thread
* Re: [PATCH 7/8] drm/i915/huc: Support HuC authentication 2016-12-15 22:29 ` [PATCH 7/8] drm/i915/huc: Support HuC authentication anushasr @ 2016-12-16 16:17 ` Arkadiusz Hiler 0 siblings, 0 replies; 43+ messages in thread From: Arkadiusz Hiler @ 2016-12-16 16:17 UTC (permalink / raw) To: anushasr; +Cc: intel-gfx, Alex Dai, Peter Antoine On Thu, Dec 15, 2016 at 02:29:49PM -0800, anushasr wrote: > From: Peter Antoine <peter.antoine@intel.com> > > The HuC authentication is done by host2guc call. The HuC RSA keys > are sent to GuC for authentication. > > v2: rebased on top of drm-intel-nightly. > changed name format and upped version 1.7. > v3: rebased on top of drm-intel-nightly. > v4: changed wait_for_automic to wait_for > v5: rebased. > v7: rebased. > v8: rebased. > v9: rebased. Rename intel_huc_auh() to intel_guc_auth_huc() > and place the prototype in intel_guc.h,correct the comments. > v10: rebased. > v11: rebased. > v12: rebased on top of drm-tip > v13: rebased. Moved intel_guc_auth_huc from i915_guc_submission.c > to intel_uc.c.Update dev to dev_priv in intel_guc_auth_huc(). > Renamed HOST2GUC_ACTION_AUTHENTICATE_HUC TO INTEL_GUC_ACTION_ > AUTHENTICATE_HUC > v14: rebased. > > Tested-by: Xiang Haihao <haihao.xiang@intel.com> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> > Signed-off-by: Alex Dai <yu.dai@intel.com> > Signed-off-by: Peter Antoine <peter.antoine@intel.com> > --- > drivers/gpu/drm/i915/intel_guc_fwif.h | 1 + > drivers/gpu/drm/i915/intel_guc_loader.c | 2 ++ > drivers/gpu/drm/i915/intel_uc.c | 62 +++++++++++++++++++++++++++++++++ > drivers/gpu/drm/i915/intel_uc.h | 1 + > 4 files changed, 66 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h > index ed1ab40..ce4e05e 100644 > --- a/drivers/gpu/drm/i915/intel_guc_fwif.h > +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h > @@ -506,6 +506,7 @@ enum intel_guc_action { > INTEL_GUC_ACTION_EXIT_S_STATE = 0x502, > INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003, > INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000, > + INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000, > INTEL_GUC_ACTION_LIMIT > }; > > diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c > index 2257495..7605f36 100644 > --- a/drivers/gpu/drm/i915/intel_guc_loader.c > +++ b/drivers/gpu/drm/i915/intel_guc_loader.c > @@ -529,6 +529,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv) > intel_uc_fw_status_repr(guc_fw->fetch_status), > intel_uc_fw_status_repr(guc_fw->load_status)); > > + intel_guc_auth_huc(dev_priv); > + > if (i915.enable_guc_submission) { > if (i915.guc_log_level >= 0) > gen9_enable_guc_interrupts(dev_priv); > diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c > index 8ae6795..b90ac57 100644 > --- a/drivers/gpu/drm/i915/intel_uc.c > +++ b/drivers/gpu/drm/i915/intel_uc.c > @@ -138,3 +138,65 @@ int intel_guc_log_control(struct intel_guc *guc, u32 control_val) > > return intel_guc_send(guc, action, ARRAY_SIZE(action)); > } > + > +/** > + * intel_guc_auth_huc() - authenticate ucode > + * @dev_priv: the drm_i915_device > + * > + * Triggers a HuC fw authentication request to the GuC via intel_guc_action_ > + * authenticate_huc interface. > + * interface. > + */ > +void intel_guc_auth_huc(struct drm_i915_private *dev_priv) > +{ > + struct intel_guc *guc = &dev_priv->guc; > + struct intel_huc *huc = &dev_priv->huc; > + struct i915_vma *vma; > + int ret; > + u32 data[2]; > + > + /* Bypass the case where there is no HuC firmware */ > + if (huc->fw.fetch_status == INTEL_UC_FIRMWARE_NONE || > + huc->fw.load_status == INTEL_UC_FIRMWARE_NONE) > + return; > + > + if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS) { > + DRM_ERROR("HuC: GuC fw wasn't loaded. Can't authenticate"); Why this DRM_ERROR does not have tailing "\n"? Same goes for couple more in here. > + return; > + } > + > + if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS) { > + DRM_ERROR("HuC: fw wasn't loaded. Nothing to authenticate"); > + return; > + } > + > + vma = i915_gem_object_ggtt_pin(huc->fw.uc_fw_obj, NULL, 0, 0, 0); > + if (IS_ERR(vma)) { > + DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma)); > + return; > + } > + > + > + /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */ > + I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); > + > + /* Specify auth action and where public signature is. */ > + data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC; > + data[1] = i915_ggtt_offset(vma) + huc->fw.rsa_offset; > + > + ret = intel_guc_send(guc, data, ARRAY_SIZE(data)); > + if (ret) { > + DRM_ERROR("HuC: GuC did not ack Auth request\n"); > + goto out; > + } > + > + /* Check authentication status, it should be done by now */ > + ret = wait_for((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) > 0, 50); > + if (ret) { > + DRM_ERROR("HuC: Authentication failed\n"); > + goto out; > + } > + > +out: > + i915_vma_unpin(vma); > +} > diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h > index 57aef56..e69d47c 100644 > --- a/drivers/gpu/drm/i915/intel_uc.h > +++ b/drivers/gpu/drm/i915/intel_uc.h > @@ -192,6 +192,7 @@ int intel_guc_sample_forcewake(struct intel_guc *guc); > int intel_guc_log_flush_complete(struct intel_guc *guc); > int intel_guc_log_flush(struct intel_guc *guc); > int intel_guc_log_control(struct intel_guc *guc, u32 control_val); > +void intel_guc_auth_huc(struct drm_i915_private *dev_priv); > > /* intel_guc_loader.c */ > extern void intel_guc_init(struct drm_i915_private *dev_priv); > -- > 2.7.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Cheers, Arek _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH 0/8]HuC Loading Patches @ 2016-12-08 23:02 anushasr 2016-12-08 23:02 ` [PATCH 7/8] drm/i915/huc: Support HuC authentication anushasr 0 siblings, 1 reply; 43+ messages in thread From: anushasr @ 2016-12-08 23:02 UTC (permalink / raw) To: intel-gfx These patches add HuC loading support. The GuC is required to authenticate the HuC. The userspace patches that check for a fully loaded HuC firmware and use it can be found at: https://lists.freedesktop.org/archives/libva/2016-September/004554.html https://lists.freedesktop.org/archives/libva/2016-September/004555.html More information regarding the HuC, batch commands that configure the HuC etc can be found at- https://01.org/sites/default/files/documentation/intel-gfx-prm-osrc-skl-vol02a-commandreference-instructions-huc.pdf https://www.x.org/docs/intel/CHV/intel-gfx-prm-osrc-chv-bsw-vol10-hevc.pdf v2: rebased. v3: rebased. Changed the code following the review comments. v4: Added action_lock initialization fix provided by Arek (Hiler Arkadiusz) to the first patch in the series- Make the GuC fw loading helper functions general. v5: rebased on top of drm-tip. The patch series is now in sync with GuC code reorganization efforts by Arek- https://patchwork.freedesktop.org/series/15896/ v6: rebased. Organize the code-move contents of intel_huc.h to intel_uc.h. Update functions intel_huc_load(),intel_huc_init() and intel_uc_fw_fetch() to accept dev_priv instead of dev. Anusha Srivatsa (3): drm/i915/huc: Add HuC fw loading support drm/i915/huc: Add BXT HuC Loading Support drm/i915/HuC: Add KBL huC loading Support Peter Antoine (5): drm/i915/guc: Make the GuC fw loading helper functions general drm/i915/huc: Unified css_header struct for GuC and HuC drm/i915/huc: Add debugfs for HuC loading status check drm/i915/huc: Support HuC authentication drm/i915/get_params: Add HuC status to getparams drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/i915_debugfs.c | 43 +++- drivers/gpu/drm/i915/i915_drv.c | 8 +- drivers/gpu/drm/i915/i915_drv.h | 3 +- drivers/gpu/drm/i915/i915_guc_reg.h | 3 + drivers/gpu/drm/i915/i915_guc_submission.c | 4 +- drivers/gpu/drm/i915/intel_guc_fwif.h | 22 ++- drivers/gpu/drm/i915/intel_guc_loader.c | 199 ++++++++++--------- drivers/gpu/drm/i915/intel_huc_loader.c | 303 +++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_uc.c | 61 ++++++ drivers/gpu/drm/i915/intel_uc.h | 68 +++++-- include/uapi/drm/i915_drm.h | 1 + 12 files changed, 593 insertions(+), 123 deletions(-) create mode 100644 drivers/gpu/drm/i915/intel_huc_loader.c -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH 7/8] drm/i915/huc: Support HuC authentication 2016-12-08 23:02 [PATCH 0/8]HuC Loading Patches anushasr @ 2016-12-08 23:02 ` anushasr 2016-12-09 10:22 ` Arkadiusz Hiler 2016-12-09 12:36 ` Michal Wajdeczko 0 siblings, 2 replies; 43+ messages in thread From: anushasr @ 2016-12-08 23:02 UTC (permalink / raw) To: intel-gfx; +Cc: Alex Dai, Peter Antoine From: Peter Antoine <peter.antoine@intel.com> The HuC authentication is done by host2guc call. The HuC RSA keys are sent to GuC for authentication. v2: rebased on top of drm-intel-nightly. changed name format and upped version 1.7. v3: rebased on top of drm-intel-nightly. v4: changed wait_for_automic to wait_for v5: rebased. v7: rebased. v8: rebased. v9: rebased. Rename intel_huc_auh() to intel_guc_auth_huc() and place the prototype in intel_guc.h,correct the comments. v10: rebased. v11: rebased. v12: rebased on top of drm-tip v13: rebased. Moved intel_guc_auth_huc from i915_guc_submission.c to intel_uc.c.Update dev to dev_priv in intel_guc_auth_huc(). Renamed HOST2GUC_ACTION_AUTHENTICATE_HUC TO INTEL_GUC_ACTION_ AUTHENTICATE_HUC Tested-by: Xiang Haihao <haihao.xiang@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Alex Dai <yu.dai@intel.com> Signed-off-by: Peter Antoine <peter.antoine@intel.com> --- drivers/gpu/drm/i915/intel_guc_fwif.h | 1 + drivers/gpu/drm/i915/intel_guc_loader.c | 2 ++ drivers/gpu/drm/i915/intel_uc.c | 61 +++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_uc.h | 1 + 4 files changed, 65 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h index c1e7faf..94a974d 100644 --- a/drivers/gpu/drm/i915/intel_guc_fwif.h +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h @@ -504,6 +504,7 @@ enum intel_guc_action { INTEL_GUC_ACTION_EXIT_S_STATE = 0x502, INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003, INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000, + INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000, INTEL_GUC_ACTION_LIMIT }; diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c index b971351..89d092b 100644 --- a/drivers/gpu/drm/i915/intel_guc_loader.c +++ b/drivers/gpu/drm/i915/intel_guc_loader.c @@ -529,6 +529,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv) intel_uc_fw_status_repr(guc_fw->fetch_status), intel_uc_fw_status_repr(guc_fw->load_status)); + intel_guc_auth_huc(dev_priv); + if (i915.enable_guc_submission) { if (i915.guc_log_level >= 0) gen9_enable_guc_interrupts(dev_priv); diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c index 8ae6795..445b9ad 100644 --- a/drivers/gpu/drm/i915/intel_uc.c +++ b/drivers/gpu/drm/i915/intel_uc.c @@ -138,3 +138,64 @@ int intel_guc_log_control(struct intel_guc *guc, u32 control_val) return intel_guc_send(guc, action, ARRAY_SIZE(action)); } + +/** + * intel_guc_auth_huc() - authenticate ucode + * @dev: the drm device + * + * Triggers a HuC fw authentication request to the GuC via host-2-guc + * interface. + */ +void intel_guc_auth_huc(struct drm_i915_private *dev_priv) +{ + struct intel_guc *guc = &dev_priv->guc; + struct intel_huc *huc = &dev_priv->huc; + struct i915_vma *vma; + int ret; + u32 data[2]; + + /* Bypass the case where there is no HuC firmware */ + if (huc->huc_fw.fetch_status == UC_FIRMWARE_NONE || + huc->huc_fw.load_status == UC_FIRMWARE_NONE) + return; + + if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS) { + DRM_ERROR("HuC: GuC fw wasn't loaded. Can't authenticate"); + return; + } + + if (huc->huc_fw.load_status != UC_FIRMWARE_SUCCESS) { + DRM_ERROR("HuC: fw wasn't loaded. Nothing to authenticate"); + return; + } + + vma = i915_gem_object_ggtt_pin(huc->huc_fw.uc_fw_obj, NULL, 0, 0, 0); + if (IS_ERR(vma)) { + DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma)); + return; + } + + + /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */ + I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); + + /* Specify auth action and where public signature is. */ + data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC; + data[1] = i915_ggtt_offset(vma) + huc->huc_fw.rsa_offset; + + ret = intel_guc_send(guc, data, ARRAY_SIZE(data)); + if (ret) { + DRM_ERROR("HuC: GuC did not ack Auth request\n"); + goto out; + } + + /* Check authentication status, it should be done by now */ + ret = wait_for((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) > 0, 50); + if (ret) { + DRM_ERROR("HuC: Authentication failed\n"); + goto out; + } + +out: + i915_vma_unpin(vma); +} diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h index ac92946..1db8bc2 100644 --- a/drivers/gpu/drm/i915/intel_uc.h +++ b/drivers/gpu/drm/i915/intel_uc.h @@ -196,6 +196,7 @@ int intel_guc_sample_forcewake(struct intel_guc *guc); int intel_guc_log_flush_complete(struct intel_guc *guc); int intel_guc_log_flush(struct intel_guc *guc); int intel_guc_log_control(struct intel_guc *guc, u32 control_val); +void intel_guc_auth_huc(struct drm_i915_private *dev_priv); /* intel_guc_loader.c */ extern void intel_guc_init(struct drm_i915_private *dev_priv); -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 43+ messages in thread
* Re: [PATCH 7/8] drm/i915/huc: Support HuC authentication 2016-12-08 23:02 ` [PATCH 7/8] drm/i915/huc: Support HuC authentication anushasr @ 2016-12-09 10:22 ` Arkadiusz Hiler 2016-12-09 12:36 ` Michal Wajdeczko 1 sibling, 0 replies; 43+ messages in thread From: Arkadiusz Hiler @ 2016-12-09 10:22 UTC (permalink / raw) To: anushasr; +Cc: intel-gfx On Thu, Dec 08, 2016 at 03:02:18PM -0800, anushasr wrote: > From: Peter Antoine <peter.antoine@intel.com> > > The HuC authentication is done by host2guc call. The HuC RSA keys > are sent to GuC for authentication. > > v2: rebased on top of drm-intel-nightly. > changed name format and upped version 1.7. > v3: rebased on top of drm-intel-nightly. > v4: changed wait_for_automic to wait_for > v5: rebased. > v7: rebased. > v8: rebased. > v9: rebased. Rename intel_huc_auh() to intel_guc_auth_huc() > and place the prototype in intel_guc.h,correct the comments. > v10: rebased. > v11: rebased. > v12: rebased on top of drm-tip > v13: rebased. Moved intel_guc_auth_huc from i915_guc_submission.c > to intel_uc.c.Update dev to dev_priv in intel_guc_auth_huc(). > Renamed HOST2GUC_ACTION_AUTHENTICATE_HUC TO INTEL_GUC_ACTION_ > AUTHENTICATE_HUC > > Tested-by: Xiang Haihao <haihao.xiang@intel.com> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> > Signed-off-by: Alex Dai <yu.dai@intel.com> > Signed-off-by: Peter Antoine <peter.antoine@intel.com> Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com> > --- > drivers/gpu/drm/i915/intel_guc_fwif.h | 1 + > drivers/gpu/drm/i915/intel_guc_loader.c | 2 ++ > drivers/gpu/drm/i915/intel_uc.c | 61 +++++++++++++++++++++++++++++++++ > drivers/gpu/drm/i915/intel_uc.h | 1 + > 4 files changed, 65 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h > index c1e7faf..94a974d 100644 > --- a/drivers/gpu/drm/i915/intel_guc_fwif.h > +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h > @@ -504,6 +504,7 @@ enum intel_guc_action { > INTEL_GUC_ACTION_EXIT_S_STATE = 0x502, > INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003, > INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000, > + INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000, > INTEL_GUC_ACTION_LIMIT > }; > > diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c > index b971351..89d092b 100644 > --- a/drivers/gpu/drm/i915/intel_guc_loader.c > +++ b/drivers/gpu/drm/i915/intel_guc_loader.c > @@ -529,6 +529,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv) > intel_uc_fw_status_repr(guc_fw->fetch_status), > intel_uc_fw_status_repr(guc_fw->load_status)); > > + intel_guc_auth_huc(dev_priv); > + > if (i915.enable_guc_submission) { > if (i915.guc_log_level >= 0) > gen9_enable_guc_interrupts(dev_priv); > diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c > index 8ae6795..445b9ad 100644 > --- a/drivers/gpu/drm/i915/intel_uc.c > +++ b/drivers/gpu/drm/i915/intel_uc.c > @@ -138,3 +138,64 @@ int intel_guc_log_control(struct intel_guc *guc, u32 control_val) > > return intel_guc_send(guc, action, ARRAY_SIZE(action)); > } > + > +/** > + * intel_guc_auth_huc() - authenticate ucode > + * @dev: the drm device > + * > + * Triggers a HuC fw authentication request to the GuC via host-2-guc > + * interface. > + */ > +void intel_guc_auth_huc(struct drm_i915_private *dev_priv) > +{ > + struct intel_guc *guc = &dev_priv->guc; > + struct intel_huc *huc = &dev_priv->huc; > + struct i915_vma *vma; > + int ret; > + u32 data[2]; > + > + /* Bypass the case where there is no HuC firmware */ > + if (huc->huc_fw.fetch_status == UC_FIRMWARE_NONE || > + huc->huc_fw.load_status == UC_FIRMWARE_NONE) > + return; > + > + if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS) { > + DRM_ERROR("HuC: GuC fw wasn't loaded. Can't authenticate"); > + return; > + } > + > + if (huc->huc_fw.load_status != UC_FIRMWARE_SUCCESS) { > + DRM_ERROR("HuC: fw wasn't loaded. Nothing to authenticate"); > + return; > + } > + > + vma = i915_gem_object_ggtt_pin(huc->huc_fw.uc_fw_obj, NULL, 0, 0, 0); > + if (IS_ERR(vma)) { > + DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma)); > + return; > + } > + > + > + /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */ > + I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); > + > + /* Specify auth action and where public signature is. */ > + data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC; > + data[1] = i915_ggtt_offset(vma) + huc->huc_fw.rsa_offset; > + > + ret = intel_guc_send(guc, data, ARRAY_SIZE(data)); > + if (ret) { > + DRM_ERROR("HuC: GuC did not ack Auth request\n"); > + goto out; > + } > + > + /* Check authentication status, it should be done by now */ > + ret = wait_for((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) > 0, 50); > + if (ret) { > + DRM_ERROR("HuC: Authentication failed\n"); > + goto out; > + } > + > +out: > + i915_vma_unpin(vma); > +} > diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h > index ac92946..1db8bc2 100644 > --- a/drivers/gpu/drm/i915/intel_uc.h > +++ b/drivers/gpu/drm/i915/intel_uc.h > @@ -196,6 +196,7 @@ int intel_guc_sample_forcewake(struct intel_guc *guc); > int intel_guc_log_flush_complete(struct intel_guc *guc); > int intel_guc_log_flush(struct intel_guc *guc); > int intel_guc_log_control(struct intel_guc *guc, u32 control_val); > +void intel_guc_auth_huc(struct drm_i915_private *dev_priv); > > /* intel_guc_loader.c */ > extern void intel_guc_init(struct drm_i915_private *dev_priv); > -- > 2.7.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Cheers, Arek _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH 7/8] drm/i915/huc: Support HuC authentication 2016-12-08 23:02 ` [PATCH 7/8] drm/i915/huc: Support HuC authentication anushasr 2016-12-09 10:22 ` Arkadiusz Hiler @ 2016-12-09 12:36 ` Michal Wajdeczko 2016-12-11 0:03 ` Srivatsa, Anusha 1 sibling, 1 reply; 43+ messages in thread From: Michal Wajdeczko @ 2016-12-09 12:36 UTC (permalink / raw) To: anushasr; +Cc: intel-gfx, Alex Dai, Peter Antoine On Thu, Dec 08, 2016 at 03:02:18PM -0800, anushasr wrote: > From: Peter Antoine <peter.antoine@intel.com> > > The HuC authentication is done by host2guc call. The HuC RSA keys > are sent to GuC for authentication. > > v2: rebased on top of drm-intel-nightly. > changed name format and upped version 1.7. > v3: rebased on top of drm-intel-nightly. > v4: changed wait_for_automic to wait_for > v5: rebased. > v7: rebased. > v8: rebased. > v9: rebased. Rename intel_huc_auh() to intel_guc_auth_huc() > and place the prototype in intel_guc.h,correct the comments. > v10: rebased. > v11: rebased. > v12: rebased on top of drm-tip > v13: rebased. Moved intel_guc_auth_huc from i915_guc_submission.c > to intel_uc.c.Update dev to dev_priv in intel_guc_auth_huc(). > Renamed HOST2GUC_ACTION_AUTHENTICATE_HUC TO INTEL_GUC_ACTION_ > AUTHENTICATE_HUC > > Tested-by: Xiang Haihao <haihao.xiang@intel.com> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> > Signed-off-by: Alex Dai <yu.dai@intel.com> > Signed-off-by: Peter Antoine <peter.antoine@intel.com> > --- > drivers/gpu/drm/i915/intel_guc_fwif.h | 1 + > drivers/gpu/drm/i915/intel_guc_loader.c | 2 ++ > drivers/gpu/drm/i915/intel_uc.c | 61 +++++++++++++++++++++++++++++++++ > drivers/gpu/drm/i915/intel_uc.h | 1 + > 4 files changed, 65 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h > index c1e7faf..94a974d 100644 > --- a/drivers/gpu/drm/i915/intel_guc_fwif.h > +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h > @@ -504,6 +504,7 @@ enum intel_guc_action { > INTEL_GUC_ACTION_EXIT_S_STATE = 0x502, > INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003, > INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000, > + INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000, > INTEL_GUC_ACTION_LIMIT > }; > > diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c > index b971351..89d092b 100644 > --- a/drivers/gpu/drm/i915/intel_guc_loader.c > +++ b/drivers/gpu/drm/i915/intel_guc_loader.c > @@ -529,6 +529,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv) > intel_uc_fw_status_repr(guc_fw->fetch_status), > intel_uc_fw_status_repr(guc_fw->load_status)); > > + intel_guc_auth_huc(dev_priv); > + > if (i915.enable_guc_submission) { > if (i915.guc_log_level >= 0) > gen9_enable_guc_interrupts(dev_priv); > diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c > index 8ae6795..445b9ad 100644 > --- a/drivers/gpu/drm/i915/intel_uc.c > +++ b/drivers/gpu/drm/i915/intel_uc.c > @@ -138,3 +138,64 @@ int intel_guc_log_control(struct intel_guc *guc, u32 control_val) > > return intel_guc_send(guc, action, ARRAY_SIZE(action)); > } > + > +/** > + * intel_guc_auth_huc() - authenticate ucode > + * @dev: the drm device Mismatched param name. > + * > + * Triggers a HuC fw authentication request to the GuC via host-2-guc > + * interface. > + */ > +void intel_guc_auth_huc(struct drm_i915_private *dev_priv) Can we use *guc as the first param to match other intel_guc functions? > +{ > + struct intel_guc *guc = &dev_priv->guc; > + struct intel_huc *huc = &dev_priv->huc; > + struct i915_vma *vma; > + int ret; > + u32 data[2]; > + > + /* Bypass the case where there is no HuC firmware */ > + if (huc->huc_fw.fetch_status == UC_FIRMWARE_NONE || > + huc->huc_fw.load_status == UC_FIRMWARE_NONE) > + return; > + > + if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS) { > + DRM_ERROR("HuC: GuC fw wasn't loaded. Can't authenticate"); Hmm, this looks like late handling of earlier error. Note that other functions in this file assume that Guc is working fine. > + return; > + } > + > + if (huc->huc_fw.load_status != UC_FIRMWARE_SUCCESS) { > + DRM_ERROR("HuC: fw wasn't loaded. Nothing to authenticate"); > + return; > + } > + > + vma = i915_gem_object_ggtt_pin(huc->huc_fw.uc_fw_obj, NULL, 0, 0, 0); > + if (IS_ERR(vma)) { > + DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma)); > + return; > + } > + > + > + /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */ > + I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); > + > + /* Specify auth action and where public signature is. */ > + data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC; > + data[1] = i915_ggtt_offset(vma) + huc->huc_fw.rsa_offset; > + > + ret = intel_guc_send(guc, data, ARRAY_SIZE(data)); Hmm, maybe this function shall be split into two parts: intel_huc_auth() in intel_huc_loader.c that contains most of the logic from current function, but calls intel_guc_auth_huc() from this file that just sends action to the guc (similar to other simple functions in this file. > + if (ret) { > + DRM_ERROR("HuC: GuC did not ack Auth request\n"); > + goto out; > + } > + > + /* Check authentication status, it should be done by now */ > + ret = wait_for((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) > 0, 50); > + if (ret) { > + DRM_ERROR("HuC: Authentication failed\n"); > + goto out; > + } > + > +out: > + i915_vma_unpin(vma); > +} > diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h > index ac92946..1db8bc2 100644 > --- a/drivers/gpu/drm/i915/intel_uc.h > +++ b/drivers/gpu/drm/i915/intel_uc.h > @@ -196,6 +196,7 @@ int intel_guc_sample_forcewake(struct intel_guc *guc); > int intel_guc_log_flush_complete(struct intel_guc *guc); > int intel_guc_log_flush(struct intel_guc *guc); > int intel_guc_log_control(struct intel_guc *guc, u32 control_val); > +void intel_guc_auth_huc(struct drm_i915_private *dev_priv); > > /* intel_guc_loader.c */ > extern void intel_guc_init(struct drm_i915_private *dev_priv); > -- > 2.7.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH 7/8] drm/i915/huc: Support HuC authentication 2016-12-09 12:36 ` Michal Wajdeczko @ 2016-12-11 0:03 ` Srivatsa, Anusha 0 siblings, 0 replies; 43+ messages in thread From: Srivatsa, Anusha @ 2016-12-11 0:03 UTC (permalink / raw) To: Michal Wajdeczko; +Cc: intel-gfx >-----Original Message----- >From: Michal Wajdeczko [mailto:michal.wajdeczko@linux.intel.com] >Sent: Friday, December 9, 2016 4:37 AM >To: Srivatsa, Anusha <anusha.srivatsa@intel.com> >Cc: intel-gfx@lists.freedesktop.org; Alex Dai <yu.dai@intel.com>; Peter Antoine ><peter.antoine@intel.com> >Subject: Re: [Intel-gfx] [PATCH 7/8] drm/i915/huc: Support HuC authentication > >On Thu, Dec 08, 2016 at 03:02:18PM -0800, anushasr wrote: >> From: Peter Antoine <peter.antoine@intel.com> >> >> The HuC authentication is done by host2guc call. The HuC RSA keys are >> sent to GuC for authentication. >> >> v2: rebased on top of drm-intel-nightly. >> changed name format and upped version 1.7. >> v3: rebased on top of drm-intel-nightly. >> v4: changed wait_for_automic to wait_for >> v5: rebased. >> v7: rebased. >> v8: rebased. >> v9: rebased. Rename intel_huc_auh() to intel_guc_auth_huc() and place >> the prototype in intel_guc.h,correct the comments. >> v10: rebased. >> v11: rebased. >> v12: rebased on top of drm-tip >> v13: rebased. Moved intel_guc_auth_huc from i915_guc_submission.c to >> intel_uc.c.Update dev to dev_priv in intel_guc_auth_huc(). >> Renamed HOST2GUC_ACTION_AUTHENTICATE_HUC TO INTEL_GUC_ACTION_ >> AUTHENTICATE_HUC >> >> Tested-by: Xiang Haihao <haihao.xiang@intel.com> >> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> >> Signed-off-by: Alex Dai <yu.dai@intel.com> >> Signed-off-by: Peter Antoine <peter.antoine@intel.com> >> --- >> drivers/gpu/drm/i915/intel_guc_fwif.h | 1 + >> drivers/gpu/drm/i915/intel_guc_loader.c | 2 ++ >> drivers/gpu/drm/i915/intel_uc.c | 61 >+++++++++++++++++++++++++++++++++ >> drivers/gpu/drm/i915/intel_uc.h | 1 + >> 4 files changed, 65 insertions(+) >> >> diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h >> b/drivers/gpu/drm/i915/intel_guc_fwif.h >> index c1e7faf..94a974d 100644 >> --- a/drivers/gpu/drm/i915/intel_guc_fwif.h >> +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h >> @@ -504,6 +504,7 @@ enum intel_guc_action { >> INTEL_GUC_ACTION_EXIT_S_STATE = 0x502, >> INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003, >> INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000, >> + INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000, >> INTEL_GUC_ACTION_LIMIT >> }; >> >> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c >> b/drivers/gpu/drm/i915/intel_guc_loader.c >> index b971351..89d092b 100644 >> --- a/drivers/gpu/drm/i915/intel_guc_loader.c >> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c >> @@ -529,6 +529,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv) >> intel_uc_fw_status_repr(guc_fw->fetch_status), >> intel_uc_fw_status_repr(guc_fw->load_status)); >> >> + intel_guc_auth_huc(dev_priv); >> + >> if (i915.enable_guc_submission) { >> if (i915.guc_log_level >= 0) >> gen9_enable_guc_interrupts(dev_priv); >> diff --git a/drivers/gpu/drm/i915/intel_uc.c >> b/drivers/gpu/drm/i915/intel_uc.c index 8ae6795..445b9ad 100644 >> --- a/drivers/gpu/drm/i915/intel_uc.c >> +++ b/drivers/gpu/drm/i915/intel_uc.c >> @@ -138,3 +138,64 @@ int intel_guc_log_control(struct intel_guc *guc, >> u32 control_val) >> >> return intel_guc_send(guc, action, ARRAY_SIZE(action)); } >> + >> +/** >> + * intel_guc_auth_huc() - authenticate ucode >> + * @dev: the drm device > >Mismatched param name. > > >> + * >> + * Triggers a HuC fw authentication request to the GuC via host-2-guc >> + * interface. >> + */ >> +void intel_guc_auth_huc(struct drm_i915_private *dev_priv) > >Can we use *guc as the first param to match other intel_guc functions? > In function intel_guc_init() and intel_guc_load() we are using dev_priv as the first parameter..... >> +{ >> + struct intel_guc *guc = &dev_priv->guc; >> + struct intel_huc *huc = &dev_priv->huc; >> + struct i915_vma *vma; >> + int ret; >> + u32 data[2]; >> + >> + /* Bypass the case where there is no HuC firmware */ >> + if (huc->huc_fw.fetch_status == UC_FIRMWARE_NONE || >> + huc->huc_fw.load_status == UC_FIRMWARE_NONE) >> + return; >> + >> + if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS) { >> + DRM_ERROR("HuC: GuC fw wasn't loaded. Can't authenticate"); > >Hmm, this looks like late handling of earlier error. >Note that other functions in this file assume that Guc is working fine. Michal, after intel_uc_init_early() which initializes a mutex lock, intel_guc_auth_huc() is the first function that the control goes to and hence all checking happens here. If anything is wrong a suitable error message is displayed and we return out immediately. If on the other hand things are proper, as expected post error checking, the other functions are called.... Hope this clears your concern. -Anusha > >> + return; >> + } >> + >> + if (huc->huc_fw.load_status != UC_FIRMWARE_SUCCESS) { >> + DRM_ERROR("HuC: fw wasn't loaded. Nothing to authenticate"); >> + return; >> + } >> + >> + vma = i915_gem_object_ggtt_pin(huc->huc_fw.uc_fw_obj, NULL, 0, 0, >0); >> + if (IS_ERR(vma)) { >> + DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma)); >> + return; >> + } >> + >> + >> + /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */ >> + I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); >> + >> + /* Specify auth action and where public signature is. */ >> + data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC; >> + data[1] = i915_ggtt_offset(vma) + huc->huc_fw.rsa_offset; >> + >> + ret = intel_guc_send(guc, data, ARRAY_SIZE(data)); > >Hmm, maybe this function shall be split into two parts: > >intel_huc_auth() in intel_huc_loader.c that contains most of the logic from >current function, but calls intel_guc_auth_huc() from this file that just sends >action to the guc (similar to other simple functions in this file. > The intention is to make intel_guc_auth_huc() as simple as other functions in the file? Two points on my mind- 1. Wont splitting into intel_huc_auth() and intel_guc_auth_huc() be more confusing than just intel_guc_auth_huc? 2.Even on splitting we will have only the preliminary check - check if guc is loaded, check if huc is loaded in intel_huc_Auth. The actual specification of authentication action, sending it to guc, checking if that is a success or not has to happen in intel_huc_auth_guc(). Am I correct? >> + if (ret) { >> + DRM_ERROR("HuC: GuC did not ack Auth request\n"); >> + goto out; >> + } >> + >> + /* Check authentication status, it should be done by now */ >> + ret = wait_for((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) > 0, >50); >> + if (ret) { >> + DRM_ERROR("HuC: Authentication failed\n"); >> + goto out; >> + } >> + >> +out: >> + i915_vma_unpin(vma); >> +} >> diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h >> index ac92946..1db8bc2 100644 >> --- a/drivers/gpu/drm/i915/intel_uc.h >> +++ b/drivers/gpu/drm/i915/intel_uc.h >> @@ -196,6 +196,7 @@ int intel_guc_sample_forcewake(struct intel_guc *guc); >> int intel_guc_log_flush_complete(struct intel_guc *guc); >> int intel_guc_log_flush(struct intel_guc *guc); >> int intel_guc_log_control(struct intel_guc *guc, u32 control_val); >> +void intel_guc_auth_huc(struct drm_i915_private *dev_priv); >> >> /* intel_guc_loader.c */ >> extern void intel_guc_init(struct drm_i915_private *dev_priv); >> -- >> 2.7.4 >> Cheers, Anusha >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx@lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH 0/8] HuC Loading Patches @ 2016-11-23 22:27 Anusha Srivatsa 2016-11-23 22:27 ` [PATCH 7/8] drm/i915/huc: Support HuC authentication Anusha Srivatsa 0 siblings, 1 reply; 43+ messages in thread From: Anusha Srivatsa @ 2016-11-23 22:27 UTC (permalink / raw) To: intel-gfx These patches add HuC loading support. The userspace patches that check for a fully loaded HuC firmware and use it can be found at: https://lists.freedesktop.org/archives/libva/2016-September/004554.html https://lists.freedesktop.org/archives/libva/2016-September/004555.html v2: rebased. v3: rebased. Changed the code following the review comments. v4: Added action_lock initialization fix provided by Arick (Hiler Arkadiusz) to the first patch in the series- Make the GuC fw loading helper functions general. Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Anusha Srivatsa (2): drm/i915/huc: Add BXT HuC Loading Support drm/i915/HuC: Add KBL huC loading Support Peter Antoine (6): drm/i915/guc: Make the GuC fw loading helper functions general. Always initialize action_lock drm/i915/huc: Unified css_header struct for GuC and HuC drm/i915/huc: Add HuC fw loading support drm/i915/huc: Add debugfs for HuC loading status check drm/i915/huc: Support HuC authentication drm/i915/get_params: Add HuC status to getparams drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/i915_debugfs.c | 43 +++- drivers/gpu/drm/i915/i915_drv.c | 8 + drivers/gpu/drm/i915/i915_drv.h | 3 + drivers/gpu/drm/i915/i915_guc_reg.h | 3 + drivers/gpu/drm/i915/i915_guc_submission.c | 70 ++++++- drivers/gpu/drm/i915/intel_guc.h | 49 +++-- drivers/gpu/drm/i915/intel_guc_fwif.h | 22 ++- drivers/gpu/drm/i915/intel_guc_loader.c | 196 +++++++++--------- drivers/gpu/drm/i915/intel_huc.h | 43 ++++ drivers/gpu/drm/i915/intel_huc_loader.c | 306 +++++++++++++++++++++++++++++ include/uapi/drm/i915_drm.h | 1 + 12 files changed, 624 insertions(+), 121 deletions(-) create mode 100644 drivers/gpu/drm/i915/intel_huc.h create mode 100644 drivers/gpu/drm/i915/intel_huc_loader.c -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH 7/8] drm/i915/huc: Support HuC authentication 2016-11-23 22:27 [PATCH 0/8] HuC Loading Patches Anusha Srivatsa @ 2016-11-23 22:27 ` Anusha Srivatsa 0 siblings, 0 replies; 43+ messages in thread From: Anusha Srivatsa @ 2016-11-23 22:27 UTC (permalink / raw) To: intel-gfx; +Cc: Alex Dai, Peter Antoine From: Peter Antoine <peter.antoine@intel.com> The HuC authentication is done by host2guc call. The HuC RSA keys are sent to GuC for authentication. v2: rebased on top of drm-intel-nightly. changed name format and upped version 1.7. v3: rebased on top of drm-intel-nightly. v4: changed wait_for_automic to wait_for v5: rebased. v7: rebased. v8: rebased. v9: rebased. Rename intel_huc_auh() to intel_guc_auth_huc() and place the prototype in intel_guc.h,correct the comments. v10: rebased. v11: rebased. Tested-by: Xiang Haihao <haihao.xiang@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Alex Dai <yu.dai@intel.com> Signed-off-by: Peter Antoine <peter.antoine@intel.com> Reviewed-by: Dave Gordon <david.s.gordon@intel.com> Reviewed-by: Jeff McGee <jeff.mcgee@intel.com> --- drivers/gpu/drm/i915/i915_guc_submission.c | 63 ++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_guc.h | 2 +- drivers/gpu/drm/i915/intel_guc_fwif.h | 1 + drivers/gpu/drm/i915/intel_guc_loader.c | 2 + 4 files changed, 67 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c index 9947a6d..704c2a0 100644 --- a/drivers/gpu/drm/i915/i915_guc_submission.c +++ b/drivers/gpu/drm/i915/i915_guc_submission.c @@ -27,6 +27,7 @@ #include <linux/relay.h> #include "i915_drv.h" #include "intel_guc.h" +#include "intel_huc.h" /** * DOC: GuC-based command submission @@ -1728,3 +1729,65 @@ int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val) return ret; } + +/** + * intel_guc_auth_huc() - authenticate ucode + * @dev: the drm device + * + * Triggers a HuC fw authentication request to the GuC via host-2-guc + * interface. + */ +void intel_guc_auth_huc(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + struct intel_guc *guc = &dev_priv->guc; + struct intel_huc *huc = &dev_priv->huc; + struct i915_vma *vma; + int ret; + u32 data[2]; + + /* Bypass the case where there is no HuC firmware */ + if (huc->huc_fw.fetch_status == UC_FIRMWARE_NONE || + huc->huc_fw.load_status == UC_FIRMWARE_NONE) + return; + + if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS) { + DRM_ERROR("HuC: GuC fw wasn't loaded. Can't authenticate"); + return; + } + + if (huc->huc_fw.load_status != UC_FIRMWARE_SUCCESS) { + DRM_ERROR("HuC: fw wasn't loaded. Nothing to authenticate"); + return; + } + + vma = i915_gem_object_ggtt_pin(huc->huc_fw.uc_fw_obj, NULL, 0, 0, 0); + if (IS_ERR(vma)) { + DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma)); + return; + } + + + /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */ + I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); + + /* Specify auth action and where public signature is. */ + data[0] = HOST2GUC_ACTION_AUTHENTICATE_HUC; + data[1] = i915_ggtt_offset(vma) + huc->huc_fw.rsa_offset; + + ret = host2guc_action(guc, data, ARRAY_SIZE(data)); + if (ret) { + DRM_ERROR("HuC: GuC did not ack Auth request\n"); + goto out; + } + + /* Check authentication status, it should be done by now */ + ret = wait_for((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) > 0, 50); + if (ret) { + DRM_ERROR("HuC: Authentication failed\n"); + goto out; + } + +out: + i915_vma_unpin(vma); +} diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h index ff6aba6..67a500c 100644 --- a/drivers/gpu/drm/i915/intel_guc.h +++ b/drivers/gpu/drm/i915/intel_guc.h @@ -197,5 +197,5 @@ void i915_guc_flush_logs(struct drm_i915_private *dev_priv); void i915_guc_register(struct drm_i915_private *dev_priv); void i915_guc_unregister(struct drm_i915_private *dev_priv); int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val); - +void intel_guc_auth_huc(struct drm_device *dev); #endif diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h index c2a7fdd..99a092d 100644 --- a/drivers/gpu/drm/i915/intel_guc_fwif.h +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h @@ -513,6 +513,7 @@ enum host2guc_action { HOST2GUC_ACTION_EXIT_S_STATE = 0x502, HOST2GUC_ACTION_SLPC_REQUEST = 0x3003, HOST2GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000, + HOST2GUC_ACTION_AUTHENTICATE_HUC = 0x4000, HOST2GUC_ACTION_LIMIT }; diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c index 090c727..6946311 100644 --- a/drivers/gpu/drm/i915/intel_guc_loader.c +++ b/drivers/gpu/drm/i915/intel_guc_loader.c @@ -531,6 +531,8 @@ int intel_guc_setup(struct drm_device *dev) intel_uc_fw_status_repr(guc_fw->fetch_status), intel_uc_fw_status_repr(guc_fw->load_status)); + intel_guc_auth_huc(dev); + if (i915.enable_guc_submission) { if (i915.guc_log_level >= 0) gen9_enable_guc_interrupts(dev_priv); -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v4 0/8] HuC Loading Patches @ 2016-11-11 0:15 Anusha Srivatsa 2016-11-11 0:15 ` [PATCH 7/8] drm/i915/huc: Support HuC authentication Anusha Srivatsa 0 siblings, 1 reply; 43+ messages in thread From: Anusha Srivatsa @ 2016-11-11 0:15 UTC (permalink / raw) To: intel-gfx These patches add HuC loading support. The userspace patches that check for a fully loaded HuC firmware and use it can be found at: https://lists.freedesktop.org/archives/libva/2016-September/004554.html https://lists.freedesktop.org/archives/libva/2016-September/004555.html v2: rebased. v3: rebased. Changed the code following the review comments. Changed mainly include renaming certain functions, correcting comments and changing the yesr in the copyright message. Removed one patch from original series: Add guC status to getparams. v4: Added the file construction method which the HuC follows. This is on similar lines to that of GuC. Rewrote the BXT HuC loading patch and wrote a new patch for HuC loading on KBL. Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Anusha Srivatsa (2): drm/i915/huc: Add BXT HuC Loading Support drm/i915/HuC: Add KBL huC loading Support Peter Antoine (6): drm/i915/guc: Make the GuC fw loading helper functions general drm/i915/huc: Unified css_header struct for GuC and HuC drm/i915/huc: Add HuC fw loading support drm/i915/huc: Add debugfs for HuC loading status check drm/i915/huc: Support HuC authentication drm/i915/get_params: Add HuC status to getparams drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/i915_debugfs.c | 43 +++- drivers/gpu/drm/i915/i915_drv.c | 8 + drivers/gpu/drm/i915/i915_drv.h | 3 + drivers/gpu/drm/i915/i915_guc_reg.h | 3 + drivers/gpu/drm/i915/i915_guc_submission.c | 67 ++++++- drivers/gpu/drm/i915/intel_guc.h | 50 +++-- drivers/gpu/drm/i915/intel_guc_fwif.h | 22 ++- drivers/gpu/drm/i915/intel_guc_loader.c | 197 +++++++++--------- drivers/gpu/drm/i915/intel_huc.h | 43 ++++ drivers/gpu/drm/i915/intel_huc_loader.c | 308 +++++++++++++++++++++++++++++ include/uapi/drm/i915_drm.h | 1 + 12 files changed, 624 insertions(+), 122 deletions(-) create mode 100644 drivers/gpu/drm/i915/intel_huc.h create mode 100644 drivers/gpu/drm/i915/intel_huc_loader.c -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH 7/8] drm/i915/huc: Support HuC authentication 2016-11-11 0:15 [PATCH v4 0/8] HuC Loading Patches Anusha Srivatsa @ 2016-11-11 0:15 ` Anusha Srivatsa 0 siblings, 0 replies; 43+ messages in thread From: Anusha Srivatsa @ 2016-11-11 0:15 UTC (permalink / raw) To: intel-gfx; +Cc: Alex Dai, Peter Antoine From: Peter Antoine <peter.antoine@intel.com> The HuC authentication is done by host2guc call. The HuC RSA keys are sent to GuC for authentication. v2: rebased on top of drm-intel-nightly. changed name format and upped version 1.7. v3: rebased on top of drm-intel-nightly. v4: changed wait_for_automic to wait_for v5: rebased. v7: rebased. v8: rebased. v9: rebased. Rename intel_huc_auh() to intel_guc_auth_huc() and place the prototype in intel_guc.h,correct the comments. v10: rebased. Tested-by: Xiang Haihao <haihao.xiang@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Alex Dai <yu.dai@intel.com> Signed-off-by: Peter Antoine <peter.antoine@intel.com> Reviewed-by: Dave Gordon <david.s.gordon@intel.com> Reviewed-by: Jeff McGee <jeff.mcgee@intel.com> --- drivers/gpu/drm/i915/i915_guc_submission.c | 63 ++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_guc.h | 2 +- drivers/gpu/drm/i915/intel_guc_fwif.h | 1 + drivers/gpu/drm/i915/intel_guc_loader.c | 2 + 4 files changed, 67 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c index fb59e44..7809acf 100644 --- a/drivers/gpu/drm/i915/i915_guc_submission.c +++ b/drivers/gpu/drm/i915/i915_guc_submission.c @@ -27,6 +27,7 @@ #include <linux/relay.h> #include "i915_drv.h" #include "intel_guc.h" +#include "intel_huc.h" /** * DOC: GuC-based command submission @@ -1714,3 +1715,65 @@ int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val) return ret; } + +/** + * intel_guc_auth_huc() - authenticate ucode + * @dev: the drm device + * + * Triggers a HuC fw authentication request to the GuC via host-2-guc + * interface. + */ +void intel_guc_auth_huc(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + struct intel_guc *guc = &dev_priv->guc; + struct intel_huc *huc = &dev_priv->huc; + struct i915_vma *vma; + int ret; + u32 data[2]; + + /* Bypass the case where there is no HuC firmware */ + if (huc->huc_fw.fetch_status == UC_FIRMWARE_NONE || + huc->huc_fw.load_status == UC_FIRMWARE_NONE) + return; + + if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS) { + DRM_ERROR("HuC: GuC fw wasn't loaded. Can't authenticate"); + return; + } + + if (huc->huc_fw.load_status != UC_FIRMWARE_SUCCESS) { + DRM_ERROR("HuC: fw wasn't loaded. Nothing to authenticate"); + return; + } + + vma = i915_gem_object_ggtt_pin(huc->huc_fw.uc_fw_obj, NULL, 0, 0, 0); + if (IS_ERR(vma)) { + DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma)); + return; + } + + + /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */ + I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); + + /* Specify auth action and where public signature is. */ + data[0] = HOST2GUC_ACTION_AUTHENTICATE_HUC; + data[1] = i915_ggtt_offset(vma) + huc->huc_fw.rsa_offset; + + ret = host2guc_action(guc, data, ARRAY_SIZE(data)); + if (ret) { + DRM_ERROR("HuC: GuC did not ack Auth request\n"); + goto out; + } + + /* Check authentication status, it should be done by now */ + ret = wait_for((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) > 0, 50); + if (ret) { + DRM_ERROR("HuC: Authentication failed\n"); + goto out; + } + +out: + i915_vma_unpin(vma); +} diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h index ff6aba6..67a500c 100644 --- a/drivers/gpu/drm/i915/intel_guc.h +++ b/drivers/gpu/drm/i915/intel_guc.h @@ -197,5 +197,5 @@ void i915_guc_flush_logs(struct drm_i915_private *dev_priv); void i915_guc_register(struct drm_i915_private *dev_priv); void i915_guc_unregister(struct drm_i915_private *dev_priv); int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val); - +void intel_guc_auth_huc(struct drm_device *dev); #endif diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h index c2a7fdd..99a092d 100644 --- a/drivers/gpu/drm/i915/intel_guc_fwif.h +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h @@ -513,6 +513,7 @@ enum host2guc_action { HOST2GUC_ACTION_EXIT_S_STATE = 0x502, HOST2GUC_ACTION_SLPC_REQUEST = 0x3003, HOST2GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000, + HOST2GUC_ACTION_AUTHENTICATE_HUC = 0x4000, HOST2GUC_ACTION_LIMIT }; diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c index dc79968..11e3bbb 100644 --- a/drivers/gpu/drm/i915/intel_guc_loader.c +++ b/drivers/gpu/drm/i915/intel_guc_loader.c @@ -531,6 +531,8 @@ int intel_guc_setup(struct drm_device *dev) intel_uc_fw_status_repr(guc_fw->fetch_status), intel_uc_fw_status_repr(guc_fw->load_status)); + intel_guc_auth_huc(dev); + if (i915.enable_guc_submission) { if (i915.guc_log_level >= 0) gen9_enable_guc_interrupts(dev_priv); -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 43+ messages in thread
end of thread, other threads:[~2017-01-14 1:20 UTC | newest] Thread overview: 43+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2016-11-30 23:31 [PATCH 0/8] HuC Loading Patches Anusha Srivatsa 2016-11-30 23:31 ` [PATCH 1/8] drm/i915/guc: Make the GuC fw loading helper functions general Anusha Srivatsa 2016-11-30 23:31 ` [PATCH 2/8] drm/i915/huc: Unified css_header struct for GuC and HuC Anusha Srivatsa 2016-12-01 12:22 ` Arkadiusz Hiler 2016-12-01 18:22 ` Srivatsa, Anusha 2016-11-30 23:31 ` [PATCH 3/8] drm/i915/huc: Add HuC fw loading support Anusha Srivatsa 2016-12-01 13:24 ` Tvrtko Ursulin 2016-12-01 17:18 ` Srivatsa, Anusha 2016-11-30 23:31 ` [PATCH 4/8] drm/i915/huc: Add BXT HuC Loading Support Anusha Srivatsa 2016-12-01 13:10 ` Tvrtko Ursulin 2016-12-05 20:42 ` Srivatsa, Anusha 2016-12-08 15:43 ` Jeff McGee 2016-11-30 23:31 ` [PATCH 5/8] drm/i915/HuC: Add KBL huC loading Support Anusha Srivatsa 2016-11-30 23:31 ` [PATCH 6/8] drm/i915/huc: Add debugfs for HuC loading status check Anusha Srivatsa 2016-11-30 23:31 ` [PATCH 7/8] drm/i915/huc: Support HuC authentication Anusha Srivatsa 2016-12-01 13:05 ` Arkadiusz Hiler 2016-11-30 23:31 ` [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams Anusha Srivatsa 2016-12-01 13:07 ` Arkadiusz Hiler 2016-12-01 5:31 ` ✗ Fi.CI.BAT: failure for HuC Loading Patches Patchwork -- strict thread matches above, loose matches on Subject: below -- 2017-01-14 1:17 [PATCH 0/8] " Anusha Srivatsa 2017-01-14 1:17 ` [PATCH 7/8] drm/i915/huc: Support HuC authentication Anusha Srivatsa 2017-01-13 18:08 [PATCH 0/8] HuC Loading Patches Anusha Srivatsa 2017-01-13 18:08 ` [PATCH 7/8] drm/i915/huc: Support HuC authentication Anusha Srivatsa 2017-01-13 18:18 ` Michal Wajdeczko 2017-01-13 18:19 ` Srivatsa, Anusha 2017-01-13 18:47 ` Chris Wilson 2017-01-13 17:07 Anusha Srivatsa 2017-01-13 17:24 ` Chris Wilson 2017-01-13 17:36 ` Srivatsa, Anusha 2017-01-04 14:55 [PATCH 0/8] HuC Loading Patches Anusha Srivatsa 2017-01-04 14:55 ` [PATCH 7/8] drm/i915/huc: Support HuC authentication Anusha Srivatsa 2017-01-05 12:14 ` Arkadiusz Hiler 2017-01-05 12:18 ` Arkadiusz Hiler 2017-01-05 13:52 ` Michal Wajdeczko 2017-01-04 13:27 [PATCH 0/8] HuC Loading Patches Anusha Srivatsa 2017-01-04 13:27 ` [PATCH 7/8] drm/i915/huc: Support HuC authentication Anusha Srivatsa 2016-12-22 23:12 [PATCH 0/8] HuC Loading Patches Anusha Srivatsa 2016-12-22 23:12 ` [PATCH 7/8] drm/i915/huc: Support HuC authentication Anusha Srivatsa 2016-12-22 23:30 ` Chris Wilson 2017-01-03 19:55 ` Srivatsa, Anusha 2016-12-15 22:29 [PATCH 0/8] HuC Loading Patches anushasr 2016-12-15 22:29 ` [PATCH 7/8] drm/i915/huc: Support HuC authentication anushasr 2016-12-16 16:17 ` Arkadiusz Hiler 2016-12-08 23:02 [PATCH 0/8]HuC Loading Patches anushasr 2016-12-08 23:02 ` [PATCH 7/8] drm/i915/huc: Support HuC authentication anushasr 2016-12-09 10:22 ` Arkadiusz Hiler 2016-12-09 12:36 ` Michal Wajdeczko 2016-12-11 0:03 ` Srivatsa, Anusha 2016-11-23 22:27 [PATCH 0/8] HuC Loading Patches Anusha Srivatsa 2016-11-23 22:27 ` [PATCH 7/8] drm/i915/huc: Support HuC authentication Anusha Srivatsa 2016-11-11 0:15 [PATCH v4 0/8] HuC Loading Patches Anusha Srivatsa 2016-11-11 0:15 ` [PATCH 7/8] drm/i915/huc: Support HuC authentication Anusha Srivatsa
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