[PATCH 0/8] HuC Loading Patches

[PATCH 0/8] HuC Loading Patches

[Anusha Srivatsa]

These patches add HuC loading support. The driver builds a frame level
workload which is stored in the graphics memory. This workload is presented
to HuC for processing. The driver, therefore should first determine if the
HuC is enabled and also read the huC athentication status bit to determine
if HuC was successfully loaded. The GuC is required to authenticate the HuC.
The userspace patches that check for a fully loaded HuC firmware and use it
can be found at:

https://lists.freedesktop.org/archives/libva/2016-September/004554.html
https://lists.freedesktop.org/archives/libva/2016-September/004555.html
 
More information regarding the HuC, batch commands that configure the 
HuC etc can be found at-
https://01.org/sites/default/files/documentation/intel-gfx-prm-osrc-skl-vol02a-commandreference-instructions-huc.pdf
https://www.x.org/docs/intel/CHV/intel-gfx-prm-osrc-chv-bsw-vol10-hevc.pdf

v2: rebased.
v3: rebased. Changed the code following the review comments.
v4: Added action_lock initialization fix provided by Arek
(Hiler Arkadiusz) to the first patch in the series- Make the
GuC fw loading helper functions general. 
v5: rebased on top of drm-tip. The patch series is now in sync with GuC 
code reorganization efforts by Arek-
https://patchwork.freedesktop.org/series/15896/
v6:rebased. Organize code. Move contents of intel_huc.h to intel_uc.h.
Update function intel_huc_load(),intel_huc_init() and intel_uc_fw_fetch()
to accept dev_priv instead of dev.
v7: rebased. Remove intel_is_huc_valid() since it is called onoly once.
Refactor the code to reduce redundency. Remove fiels like uc_dev which
are no longer used.
v8: rebased. Beautify the code- remove comments that no longer hold
good, add newlines etc. 

Anusha Srivatsa (3):
  drm/i915/huc: Add HuC fw loading support
  drm/i915/huc: Add BXT HuC Loading Support
  drm/i915/HuC: Add KBL huC loading Support

Peter Antoine (5):
  drm/i915/guc: Make the GuC fw loading helper functions general
  drm/i915/huc: Unified css_header struct for GuC and HuC
  drm/i915/huc: Add debugfs for HuC loading status check
  drm/i915/huc: Support HuC authentication
  drm/i915/get_params: Add HuC status to getparams

 drivers/gpu/drm/i915/Makefile              |   1 +
 drivers/gpu/drm/i915/i915_debugfs.c        |  43 ++++-
 drivers/gpu/drm/i915/i915_drv.c            |  11 +-
 drivers/gpu/drm/i915/i915_drv.h            |   3 +-
 drivers/gpu/drm/i915/i915_guc_reg.h        |   3 +
 drivers/gpu/drm/i915/i915_guc_submission.c |   4 +-
 drivers/gpu/drm/i915/intel_guc_fwif.h      |  24 ++-
 drivers/gpu/drm/i915/intel_guc_loader.c    | 200 +++++++++++---------
 drivers/gpu/drm/i915/intel_huc_loader.c    | 286 +++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_uc.c            |  62 +++++++
 drivers/gpu/drm/i915/intel_uc.h            |  63 +++++--
 include/uapi/drm/i915_drm.h                |   1 +
 12 files changed, 577 insertions(+), 124 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_huc_loader.c

-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 1/8] drm/i915/guc: Make the GuC fw loading helper functions general

[Anusha Srivatsa]

From: Peter Antoine <peter.antoine@intel.com>

Rename some of the GuC fw loading code to make them more general. We
will utilise them for HuC loading as well.
     s/intel_guc_fw/intel_uc_fw/g
     s/GUC_FIRMWARE/UC_FIRMWARE/g

Struct intel_guc_fw is renamed to intel_uc_fw. Prefix of tts members,
such as 'guc' or 'guc_fw' either is renamed to 'uc' or removed for
same purpose.

v2: rebased on top of nightly.
    reapplied the search/replace as upstream code as changed.
v3: rebased again on drm-nightly.
v4: removed G from messages in shared fw fetch function.
v5: rebased.
v7: rebased.
v8: rebased.
v9: rebased.
v10: rebased.
v11: rebased.
v12: rebased on top of drm-tip
v13: rebased.Updated dev to dev_priv in intel_guc_setup(), guc_fw_getch()
and intel_guc_init().
v14: rebased. Remove uint32_t fw_type to patch 2. Add INTEL_ prefix for
fields in enum intel_uc_fw_status. Remove uc_dev field since its never
used.Rename uc_fw to just fw and guc_fw to fw to avoid redundency.
v15: rebased. Remove sections of code that were commented and no longer
required.

Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c        |  12 +--
 drivers/gpu/drm/i915/i915_guc_submission.c |   4 +-
 drivers/gpu/drm/i915/intel_guc_loader.c    | 156 ++++++++++++++---------------
 drivers/gpu/drm/i915/intel_uc.h            |  36 +++----
 4 files changed, 104 insertions(+), 104 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index a5552a1..0a3c575 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2328,7 +2328,7 @@ static int i915_llc(struct seq_file *m, void *data)
 static int i915_guc_load_status_info(struct seq_file *m, void *data)
 {
 	struct drm_i915_private *dev_priv = node_to_i915(m->private);
-	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
+	struct intel_uc_fw *guc_fw = &dev_priv->guc.fw;
 	u32 tmp, i;
 
 	if (!HAS_GUC_UCODE(dev_priv))
@@ -2336,15 +2336,15 @@ static int i915_guc_load_status_info(struct seq_file *m, void *data)
 
 	seq_printf(m, "GuC firmware status:\n");
 	seq_printf(m, "\tpath: %s\n",
-		guc_fw->guc_fw_path);
+		guc_fw->uc_fw_path);
 	seq_printf(m, "\tfetch: %s\n",
-		intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
+		intel_uc_fw_status_repr(guc_fw->fetch_status));
 	seq_printf(m, "\tload: %s\n",
-		intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
+		intel_uc_fw_status_repr(guc_fw->load_status));
 	seq_printf(m, "\tversion wanted: %d.%d\n",
-		guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
+		guc_fw->major_ver_wanted, guc_fw->minor_ver_wanted);
 	seq_printf(m, "\tversion found: %d.%d\n",
-		guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
+		guc_fw->major_ver_found, guc_fw->minor_ver_found);
 	seq_printf(m, "\theader: offset is %d; size = %d\n",
 		guc_fw->header_offset, guc_fw->header_size);
 	seq_printf(m, "\tuCode: offset is %d; size = %d\n",
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
index 3e20fe2..6e2d403 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -1484,7 +1484,7 @@ int intel_guc_suspend(struct drm_i915_private *dev_priv)
 	struct i915_gem_context *ctx;
 	u32 data[3];
 
-	if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
+	if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
 		return 0;
 
 	gen9_disable_guc_interrupts(dev_priv);
@@ -1511,7 +1511,7 @@ int intel_guc_resume(struct drm_i915_private *dev_priv)
 	struct i915_gem_context *ctx;
 	u32 data[3];
 
-	if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
+	if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
 		return 0;
 
 	if (i915.guc_log_level >= 0)
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 21db697..ffe53dd7 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -81,16 +81,16 @@ MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
 MODULE_FIRMWARE(I915_KBL_GUC_UCODE);
 
 /* User-friendly representation of an enum */
-const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status)
+const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status)
 {
 	switch (status) {
-	case GUC_FIRMWARE_FAIL:
+	case INTEL_UC_FIRMWARE_FAIL:
 		return "FAIL";
-	case GUC_FIRMWARE_NONE:
+	case INTEL_UC_FIRMWARE_NONE:
 		return "NONE";
-	case GUC_FIRMWARE_PENDING:
+	case INTEL_UC_FIRMWARE_PENDING:
 		return "PENDING";
-	case GUC_FIRMWARE_SUCCESS:
+	case INTEL_UC_FIRMWARE_SUCCESS:
 		return "SUCCESS";
 	default:
 		return "UNKNOWN!";
@@ -278,7 +278,7 @@ static inline bool guc_ucode_response(struct drm_i915_private *dev_priv,
 static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv,
 			      struct i915_vma *vma)
 {
-	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
+	struct intel_uc_fw *guc_fw = &dev_priv->guc.fw;
 	unsigned long offset;
 	struct sg_table *sg = vma->pages;
 	u32 status, rsa[UOS_RSA_SCRATCH_MAX_COUNT];
@@ -350,17 +350,17 @@ static u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
  */
 static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
 {
-	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
+	struct intel_uc_fw *guc_fw = &dev_priv->guc.fw;
 	struct i915_vma *vma;
 	int ret;
 
-	ret = i915_gem_object_set_to_gtt_domain(guc_fw->guc_fw_obj, false);
+	ret = i915_gem_object_set_to_gtt_domain(guc_fw->uc_fw_obj, false);
 	if (ret) {
 		DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
 		return ret;
 	}
 
-	vma = i915_gem_object_ggtt_pin(guc_fw->guc_fw_obj, NULL, 0, 0, 0);
+	vma = i915_gem_object_ggtt_pin(guc_fw->uc_fw_obj, NULL, 0, 0, 0);
 	if (IS_ERR(vma)) {
 		DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
 		return PTR_ERR(vma);
@@ -450,14 +450,14 @@ static int guc_hw_reset(struct drm_i915_private *dev_priv)
  */
 int intel_guc_setup(struct drm_i915_private *dev_priv)
 {
-	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
-	const char *fw_path = guc_fw->guc_fw_path;
+	struct intel_uc_fw *guc_fw = &dev_priv->guc.fw;
+	const char *fw_path = guc_fw->uc_fw_path;
 	int retries, ret, err;
 
 	DRM_DEBUG_DRIVER("GuC fw status: path %s, fetch %s, load %s\n",
 		fw_path,
-		intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
-		intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
+		intel_uc_fw_status_repr(guc_fw->fetch_status),
+		intel_uc_fw_status_repr(guc_fw->load_status));
 
 	/* Loading forbidden, or no firmware to load? */
 	if (!i915.enable_guc_loading) {
@@ -475,10 +475,10 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
 	}
 
 	/* Fetch failed, or already fetched but failed to load? */
-	if (guc_fw->guc_fw_fetch_status != GUC_FIRMWARE_SUCCESS) {
+	if (guc_fw->fetch_status != INTEL_UC_FIRMWARE_SUCCESS) {
 		err = -EIO;
 		goto fail;
-	} else if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_FAIL) {
+	} else if (guc_fw->load_status == INTEL_UC_FIRMWARE_FAIL) {
 		err = -ENOEXEC;
 		goto fail;
 	}
@@ -486,11 +486,11 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
 	guc_interrupts_release(dev_priv);
 	gen9_reset_guc_interrupts(dev_priv);
 
-	guc_fw->guc_fw_load_status = GUC_FIRMWARE_PENDING;
+	guc_fw->load_status = INTEL_UC_FIRMWARE_PENDING;
 
 	DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
-		intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
-		intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
+		intel_uc_fw_status_repr(guc_fw->fetch_status),
+		intel_uc_fw_status_repr(guc_fw->load_status));
 
 	err = i915_guc_submission_init(dev_priv);
 	if (err)
@@ -522,11 +522,11 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
 			 "retry %d more time(s)\n", err, retries);
 	}
 
-	guc_fw->guc_fw_load_status = GUC_FIRMWARE_SUCCESS;
+	guc_fw->load_status = INTEL_UC_FIRMWARE_SUCCESS;
 
 	DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
-		intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
-		intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
+		intel_uc_fw_status_repr(guc_fw->fetch_status),
+		intel_uc_fw_status_repr(guc_fw->load_status));
 
 	if (i915.enable_guc_submission) {
 		if (i915.guc_log_level >= 0)
@@ -541,8 +541,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
 	return 0;
 
 fail:
-	if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_PENDING)
-		guc_fw->guc_fw_load_status = GUC_FIRMWARE_FAIL;
+	if (guc_fw->load_status == INTEL_UC_FIRMWARE_PENDING)
+		guc_fw->load_status = INTEL_UC_FIRMWARE_FAIL;
 
 	guc_interrupts_release(dev_priv);
 	i915_guc_submission_disable(dev_priv);
@@ -587,8 +587,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
 	return ret;
 }
 
-static void guc_fw_fetch(struct drm_i915_private *dev_priv,
-			 struct intel_guc_fw *guc_fw)
+void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
+			 struct intel_uc_fw *uc_fw)
 {
 	struct pci_dev *pdev = dev_priv->drm.pdev;
 	struct drm_i915_gem_object *obj;
@@ -597,17 +597,17 @@ static void guc_fw_fetch(struct drm_i915_private *dev_priv,
 	size_t size;
 	int err;
 
-	DRM_DEBUG_DRIVER("before requesting firmware: GuC fw fetch status %s\n",
-		intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
+	DRM_DEBUG_DRIVER("before requesting firmware: uC fw fetch status %s\n",
+		intel_uc_fw_status_repr(uc_fw->fetch_status));
 
-	err = request_firmware(&fw, guc_fw->guc_fw_path, &pdev->dev);
+	err = request_firmware(&fw, uc_fw->uc_fw_path, &pdev->dev);
 	if (err)
 		goto fail;
 	if (!fw)
 		goto fail;
 
-	DRM_DEBUG_DRIVER("fetch GuC fw from %s succeeded, fw %p\n",
-		guc_fw->guc_fw_path, fw);
+	DRM_DEBUG_DRIVER("fetch uC fw from %s succeeded, fw %p\n",
+		uc_fw->uc_fw_path, fw);
 
 	/* Check the size of the blob before examining buffer contents */
 	if (fw->size < sizeof(struct guc_css_header)) {
@@ -618,36 +618,36 @@ static void guc_fw_fetch(struct drm_i915_private *dev_priv,
 	css = (struct guc_css_header *)fw->data;
 
 	/* Firmware bits always start from header */
-	guc_fw->header_offset = 0;
-	guc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
+	uc_fw->header_offset = 0;
+	uc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
 		css->key_size_dw - css->exponent_size_dw) * sizeof(u32);
 
-	if (guc_fw->header_size != sizeof(struct guc_css_header)) {
+	if (uc_fw->header_size != sizeof(struct guc_css_header)) {
 		DRM_NOTE("CSS header definition mismatch\n");
 		goto fail;
 	}
 
 	/* then, uCode */
-	guc_fw->ucode_offset = guc_fw->header_offset + guc_fw->header_size;
-	guc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
+	uc_fw->ucode_offset = uc_fw->header_offset + uc_fw->header_size;
+	uc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
 
 	/* now RSA */
 	if (css->key_size_dw != UOS_RSA_SCRATCH_MAX_COUNT) {
 		DRM_NOTE("RSA key size is bad\n");
 		goto fail;
 	}
-	guc_fw->rsa_offset = guc_fw->ucode_offset + guc_fw->ucode_size;
-	guc_fw->rsa_size = css->key_size_dw * sizeof(u32);
+	uc_fw->rsa_offset = uc_fw->ucode_offset + uc_fw->ucode_size;
+	uc_fw->rsa_size = css->key_size_dw * sizeof(u32);
 
 	/* At least, it should have header, uCode and RSA. Size of all three. */
-	size = guc_fw->header_size + guc_fw->ucode_size + guc_fw->rsa_size;
+	size = uc_fw->header_size + uc_fw->ucode_size + uc_fw->rsa_size;
 	if (fw->size < size) {
 		DRM_NOTE("Missing firmware components\n");
 		goto fail;
 	}
 
 	/* Header and uCode will be loaded to WOPCM. Size of the two. */
-	size = guc_fw->header_size + guc_fw->ucode_size;
+	size = uc_fw->header_size + uc_fw->ucode_size;
 	if (size > guc_wopcm_size(dev_priv)) {
 		DRM_NOTE("Firmware is too large to fit in WOPCM\n");
 		goto fail;
@@ -659,21 +659,21 @@ static void guc_fw_fetch(struct drm_i915_private *dev_priv,
 	 * TWO bytes each (i.e. u16), although all pointers and offsets are defined
 	 * in terms of bytes (u8).
 	 */
-	guc_fw->guc_fw_major_found = css->guc_sw_version >> 16;
-	guc_fw->guc_fw_minor_found = css->guc_sw_version & 0xFFFF;
-
-	if (guc_fw->guc_fw_major_found != guc_fw->guc_fw_major_wanted ||
-	    guc_fw->guc_fw_minor_found < guc_fw->guc_fw_minor_wanted) {
-		DRM_NOTE("GuC firmware version %d.%d, required %d.%d\n",
-			guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
-			guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
+	uc_fw->major_ver_found = css->guc_sw_version >> 16;
+	uc_fw->minor_ver_found = css->guc_sw_version & 0xFFFF;
+
+	if (uc_fw->major_ver_found != uc_fw->major_ver_wanted ||
+	    uc_fw->minor_ver_found < uc_fw->minor_ver_wanted) {
+		DRM_NOTE("uC firmware version %d.%d, required %d.%d\n",
+			uc_fw->major_ver_found, uc_fw->minor_ver_found,
+			uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted);
 		err = -ENOEXEC;
 		goto fail;
 	}
 
 	DRM_DEBUG_DRIVER("firmware version %d.%d OK (minimum %d.%d)\n",
-			guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
-			guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
+			uc_fw->major_ver_found, uc_fw->minor_ver_found,
+			uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted);
 
 	mutex_lock(&dev_priv->drm.struct_mutex);
 	obj = i915_gem_object_create_from_data(dev_priv, fw->data, fw->size);
@@ -683,31 +683,31 @@ static void guc_fw_fetch(struct drm_i915_private *dev_priv,
 		goto fail;
 	}
 
-	guc_fw->guc_fw_obj = obj;
-	guc_fw->guc_fw_size = fw->size;
+	uc_fw->uc_fw_obj = obj;
+	uc_fw->size = fw->size;
 
-	DRM_DEBUG_DRIVER("GuC fw fetch status SUCCESS, obj %p\n",
-			guc_fw->guc_fw_obj);
+	DRM_DEBUG_DRIVER("uC fw fetch status SUCCESS, obj %p\n",
+			uc_fw->uc_fw_obj);
 
 	release_firmware(fw);
-	guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_SUCCESS;
+	uc_fw->fetch_status = INTEL_UC_FIRMWARE_SUCCESS;
 	return;
 
 fail:
-	DRM_WARN("Failed to fetch valid GuC firmware from %s (error %d)\n",
-		 guc_fw->guc_fw_path, err);
-	DRM_DEBUG_DRIVER("GuC fw fetch status FAIL; err %d, fw %p, obj %p\n",
-		err, fw, guc_fw->guc_fw_obj);
+	DRM_WARN("Failed to fetch valid uC firmware from %s (error %d)\n",
+		 uc_fw->uc_fw_path, err);
+	DRM_DEBUG_DRIVER("uC fw fetch status FAIL; err %d, fw %p, obj %p\n",
+		err, fw, uc_fw->uc_fw_obj);
 
 	mutex_lock(&dev_priv->drm.struct_mutex);
-	obj = guc_fw->guc_fw_obj;
+	obj = uc_fw->uc_fw_obj;
 	if (obj)
 		i915_gem_object_put(obj);
-	guc_fw->guc_fw_obj = NULL;
+	uc_fw->uc_fw_obj = NULL;
 	mutex_unlock(&dev_priv->drm.struct_mutex);
 
 	release_firmware(fw);		/* OK even if fw is NULL */
-	guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL;
+	uc_fw->fetch_status = INTEL_UC_FIRMWARE_FAIL;
 }
 
 /**
@@ -721,7 +721,7 @@ static void guc_fw_fetch(struct drm_i915_private *dev_priv,
  */
 void intel_guc_init(struct drm_i915_private *dev_priv)
 {
-	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
+	struct intel_uc_fw *guc_fw = &dev_priv->guc.fw;
 	const char *fw_path;
 
 	if (!HAS_GUC(dev_priv)) {
@@ -739,23 +739,23 @@ void intel_guc_init(struct drm_i915_private *dev_priv)
 		fw_path = NULL;
 	} else if (IS_SKYLAKE(dev_priv)) {
 		fw_path = I915_SKL_GUC_UCODE;
-		guc_fw->guc_fw_major_wanted = SKL_FW_MAJOR;
-		guc_fw->guc_fw_minor_wanted = SKL_FW_MINOR;
+		guc_fw->major_ver_wanted = SKL_FW_MAJOR;
+		guc_fw->minor_ver_wanted = SKL_FW_MINOR;
 	} else if (IS_BROXTON(dev_priv)) {
 		fw_path = I915_BXT_GUC_UCODE;
-		guc_fw->guc_fw_major_wanted = BXT_FW_MAJOR;
-		guc_fw->guc_fw_minor_wanted = BXT_FW_MINOR;
+		guc_fw->major_ver_wanted = BXT_FW_MAJOR;
+		guc_fw->minor_ver_wanted = BXT_FW_MINOR;
 	} else if (IS_KABYLAKE(dev_priv)) {
 		fw_path = I915_KBL_GUC_UCODE;
-		guc_fw->guc_fw_major_wanted = KBL_FW_MAJOR;
-		guc_fw->guc_fw_minor_wanted = KBL_FW_MINOR;
+		guc_fw->major_ver_wanted = KBL_FW_MAJOR;
+		guc_fw->minor_ver_wanted = KBL_FW_MINOR;
 	} else {
 		fw_path = "";	/* unknown device */
 	}
 
-	guc_fw->guc_fw_path = fw_path;
-	guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
-	guc_fw->guc_fw_load_status = GUC_FIRMWARE_NONE;
+	guc_fw->uc_fw_path = fw_path;
+	guc_fw->fetch_status = INTEL_UC_FIRMWARE_NONE;
+	guc_fw->load_status = INTEL_UC_FIRMWARE_NONE;
 
 	/* Early (and silent) return if GuC loading is disabled */
 	if (!i915.enable_guc_loading)
@@ -765,9 +765,9 @@ void intel_guc_init(struct drm_i915_private *dev_priv)
 	if (*fw_path == '\0')
 		return;
 
-	guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_PENDING;
+	guc_fw->fetch_status = INTEL_UC_FIRMWARE_PENDING;
 	DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path);
-	guc_fw_fetch(dev_priv, guc_fw);
+	intel_uc_fw_fetch(dev_priv, guc_fw);
 	/* status must now be FAIL or SUCCESS */
 }
 
@@ -777,17 +777,17 @@ void intel_guc_init(struct drm_i915_private *dev_priv)
  */
 void intel_guc_fini(struct drm_i915_private *dev_priv)
 {
-	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
+	struct intel_uc_fw *guc_fw = &dev_priv->guc.fw;
 
 	mutex_lock(&dev_priv->drm.struct_mutex);
 	guc_interrupts_release(dev_priv);
 	i915_guc_submission_disable(dev_priv);
 	i915_guc_submission_fini(dev_priv);
 
-	if (guc_fw->guc_fw_obj)
-		i915_gem_object_put(guc_fw->guc_fw_obj);
-	guc_fw->guc_fw_obj = NULL;
+	if (guc_fw->uc_fw_obj)
+		i915_gem_object_put(guc_fw->uc_fw_obj);
+	guc_fw->uc_fw_obj = NULL;
 	mutex_unlock(&dev_priv->drm.struct_mutex);
 
-	guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
+	guc_fw->fetch_status = INTEL_UC_FIRMWARE_NONE;
 }
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index 11f5608..893bcec 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -91,28 +91,28 @@ struct i915_guc_client {
 	uint64_t submissions[I915_NUM_ENGINES];
 };
 
-enum intel_guc_fw_status {
-	GUC_FIRMWARE_FAIL = -1,
-	GUC_FIRMWARE_NONE = 0,
-	GUC_FIRMWARE_PENDING,
-	GUC_FIRMWARE_SUCCESS
+enum intel_uc_fw_status {
+	INTEL_UC_FIRMWARE_FAIL = -1,
+	INTEL_UC_FIRMWARE_NONE = 0,
+	INTEL_UC_FIRMWARE_PENDING,
+	INTEL_UC_FIRMWARE_SUCCESS
 };
 
 /*
  * This structure encapsulates all the data needed during the process
  * of fetching, caching, and loading the firmware image into the GuC.
  */
-struct intel_guc_fw {
-	const char *			guc_fw_path;
-	size_t				guc_fw_size;
-	struct drm_i915_gem_object *	guc_fw_obj;
-	enum intel_guc_fw_status	guc_fw_fetch_status;
-	enum intel_guc_fw_status	guc_fw_load_status;
-
-	uint16_t			guc_fw_major_wanted;
-	uint16_t			guc_fw_minor_wanted;
-	uint16_t			guc_fw_major_found;
-	uint16_t			guc_fw_minor_found;
+struct intel_uc_fw {
+	const char *uc_fw_path;
+	size_t size;
+	struct drm_i915_gem_object *uc_fw_obj;
+	enum intel_uc_fw_status fetch_status;
+	enum intel_uc_fw_status load_status;
+
+	uint16_t major_ver_wanted;
+	uint16_t minor_ver_wanted;
+	uint16_t major_ver_found;
+	uint16_t minor_ver_found;
 
 	uint32_t header_size;
 	uint32_t header_offset;
@@ -139,7 +139,7 @@ struct intel_guc_log {
 };
 
 struct intel_guc {
-	struct intel_guc_fw guc_fw;
+	struct intel_uc_fw fw;
 	struct intel_guc_log log;
 
 	/* intel_guc_recv interrupt related state */
@@ -181,7 +181,7 @@ int intel_guc_log_control(struct intel_guc *guc, u32 control_val);
 extern void intel_guc_init(struct drm_i915_private *dev_priv);
 extern int intel_guc_setup(struct drm_i915_private *dev_priv);
 extern void intel_guc_fini(struct drm_i915_private *dev_priv);
-extern const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status);
+extern const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status);
 extern int intel_guc_suspend(struct drm_i915_private *dev_priv);
 extern int intel_guc_resume(struct drm_i915_private *dev_priv);
 
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 2/8] drm/i915/huc: Unified css_header struct for GuC and HuC

[Anusha Srivatsa]

From: Peter Antoine <peter.antoine@intel.com>

HuC firmware css header has almost exactly same definition as GuC
firmware except for the sw_version. Also, add a new member fw_type
into intel_uc_fw to indicate what kind of fw it is. So, the loader
will pull right sw_version from header.

v2: rebased on-top of drm-intel-nightly
v3: rebased on-top of drm-intel-nightly (again).
v4: rebased + spaces.
v7: rebased.
v8: rebased.
v9: rebased. Rename device_id to guc_branch_client_version,
make guc_sw_version a union. <Jeff Mcgee>. Put UC_FW_TYPE_GUC
and UC_FW_TYPE_HUC into an enum.
v10: rebased.
v11: rebased.
v12: rebased on top of drm-tip.
v13: rebased.Update dev to dev_priv in intel_uc_fw_fetch
v14: rebased. Add INTEL_ prefix to an enum. Add fw_type declaration
from patch 1.Combine two different unions for huc and guc version,
reserved etc into one union with two structs.
v15: rebased.

Tested-by: Xiang Haihao <haihao.xiang@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
---
 drivers/gpu/drm/i915/intel_guc_fwif.h   | 23 ++++++++++++++----
 drivers/gpu/drm/i915/intel_guc_loader.c | 41 ++++++++++++++++++++++-----------
 drivers/gpu/drm/i915/intel_uc.h         |  6 +++++
 3 files changed, 53 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 3202b32..ed1ab40 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -145,7 +145,7 @@
  * The GuC firmware layout looks like this:
  *
  *     +-------------------------------+
- *     |        guc_css_header         |
+ *     |         uc_css_header         |
  *     |                               |
  *     | contains major/minor version  |
  *     +-------------------------------+
@@ -172,9 +172,16 @@
  * 3. Length info of each component can be found in header, in dwords.
  * 4. Modulus and exponent key are not required by driver. They may not appear
  *    in fw. So driver will load a truncated firmware in this case.
+ *
+ * HuC firmware layout is same as GuC firmware.
+ *
+ * HuC firmware css header is different. However, the only difference is where
+ * the version information is saved. The uc_css_header is unified to support
+ * both. Driver should get HuC version from uc_css_header.huc_sw_version, while
+ * uc_css_header.guc_sw_version for GuC.
  */
 
-struct guc_css_header {
+struct uc_css_header {
 	uint32_t module_type;
 	/* header_size includes all non-uCode bits, including css_header, rsa
 	 * key, modulus key and exponent data. */
@@ -205,8 +212,16 @@ struct guc_css_header {
 
 	char username[8];
 	char buildnumber[12];
-	uint32_t device_id;
-	uint32_t guc_sw_version;
+	union {
+		struct {
+			uint32_t branch_client_version;
+			uint32_t sw_version;
+	} guc;
+		struct {
+			uint32_t sw_version;
+			uint32_t reserved;
+	} huc;
+	};
 	uint32_t prod_preprod_fw;
 	uint32_t reserved[12];
 	uint32_t header_info;
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index ffe53dd7..06e3e5c 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -593,7 +593,7 @@ void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
 	struct pci_dev *pdev = dev_priv->drm.pdev;
 	struct drm_i915_gem_object *obj;
 	const struct firmware *fw = NULL;
-	struct guc_css_header *css;
+	struct uc_css_header *css;
 	size_t size;
 	int err;
 
@@ -610,19 +610,19 @@ void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
 		uc_fw->uc_fw_path, fw);
 
 	/* Check the size of the blob before examining buffer contents */
-	if (fw->size < sizeof(struct guc_css_header)) {
+	if (fw->size < sizeof(struct uc_css_header)) {
 		DRM_NOTE("Firmware header is missing\n");
 		goto fail;
 	}
 
-	css = (struct guc_css_header *)fw->data;
+	css = (struct uc_css_header *)fw->data;
 
 	/* Firmware bits always start from header */
 	uc_fw->header_offset = 0;
 	uc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
 		css->key_size_dw - css->exponent_size_dw) * sizeof(u32);
 
-	if (uc_fw->header_size != sizeof(struct guc_css_header)) {
+	if (uc_fw->header_size != sizeof(struct uc_css_header)) {
 		DRM_NOTE("CSS header definition mismatch\n");
 		goto fail;
 	}
@@ -646,21 +646,36 @@ void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
 		goto fail;
 	}
 
-	/* Header and uCode will be loaded to WOPCM. Size of the two. */
-	size = uc_fw->header_size + uc_fw->ucode_size;
-	if (size > guc_wopcm_size(dev_priv)) {
-		DRM_NOTE("Firmware is too large to fit in WOPCM\n");
-		goto fail;
-	}
-
 	/*
 	 * The GuC firmware image has the version number embedded at a well-known
 	 * offset within the firmware blob; note that major / minor version are
 	 * TWO bytes each (i.e. u16), although all pointers and offsets are defined
 	 * in terms of bytes (u8).
 	 */
-	uc_fw->major_ver_found = css->guc_sw_version >> 16;
-	uc_fw->minor_ver_found = css->guc_sw_version & 0xFFFF;
+	switch (uc_fw->fw_type) {
+	case INTEL_UC_FW_TYPE_GUC:
+		/* Header and uCode will be loaded to WOPCM. Size of the two. */
+		size = uc_fw->header_size + uc_fw->ucode_size;
+
+		/* Top 32k of WOPCM is reserved (8K stack + 24k RC6 context). */
+		if (size > guc_wopcm_size(dev_priv)) {
+			DRM_ERROR("Firmware is too large to fit in WOPCM\n");
+			goto fail;
+		}
+		uc_fw->major_ver_found = css->guc.sw_version >> 16;
+		uc_fw->minor_ver_found = css->guc.sw_version & 0xFFFF;
+		break;
+
+	case INTEL_UC_FW_TYPE_HUC:
+		uc_fw->major_ver_found = css->huc.sw_version >> 16;
+		uc_fw->minor_ver_found = css->huc.sw_version & 0xFFFF;
+		break;
+
+	default:
+		DRM_ERROR("Unknown firmware type %d\n", uc_fw->fw_type);
+		err = -ENOEXEC;
+		goto fail;
+	}
 
 	if (uc_fw->major_ver_found != uc_fw->major_ver_wanted ||
 	    uc_fw->minor_ver_found < uc_fw->minor_ver_wanted) {
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index 893bcec..ad140e2 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -98,6 +98,11 @@ enum intel_uc_fw_status {
 	INTEL_UC_FIRMWARE_SUCCESS
 };
 
+enum {
+	INTEL_UC_FW_TYPE_GUC,
+	INTEL_UC_FW_TYPE_HUC
+};
+
 /*
  * This structure encapsulates all the data needed during the process
  * of fetching, caching, and loading the firmware image into the GuC.
@@ -114,6 +119,7 @@ struct intel_uc_fw {
 	uint16_t major_ver_found;
 	uint16_t minor_ver_found;
 
+	uint32_t fw_type;
 	uint32_t header_size;
 	uint32_t header_offset;
 	uint32_t rsa_size;
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 3/8] drm/i915/huc: Add HuC fw loading support

[Anusha Srivatsa]

The HuC loading process is similar to GuC. The intel_uc_fw_fetch()
is used for both cases.

HuC loading needs to be before GuC loading. The WOPCM setting must
be done early before loading any of them.

v2: rebased on-top of drm-intel-nightly.
    removed if(HAS_GUC()) before the guc call. (D.Gordon)
    update huc_version number of format.
v3: rebased to drm-intel-nightly, changed the file name format to
    match the one in the huc package.
    Changed dev->dev_private to to_i915()
v4: moved function back to where it was.
    change wait_for_atomic to wait_for.
v5: rebased + comment changes.
v7: rebased.
v8: rebased.
v9: rebased. Changed the year in the copyright message to reflect
the right year.Correct the comments,remove the unwanted WARN message,
replace drm_gem_object_unreference() with i915_gem_object_put().Make the
prototypes in intel_huc.h non-extern.
v10: rebased. Update the file construction done by HuC. It is similar to
GuC.Adopted the approach used in-
https://patchwork.freedesktop.org/patch/104355/ <Tvrtko Ursulin>
v11: Fix warnings remove old declaration
v12: Change dev to dev_priv in macro definition.
Corrected comments.
v13: rebased.
v14: rebased on top of drm-tip
v15: rebased. Updated functions intel_huc_load(),intel_huc_init() and
intel_uc_fw_fetch() to accept dev_priv instead of dev. Moved contents
of intel_huc.h to intel_uc.h
v16: change SKL_FW_ to SKL_HUC_FW_. Add intel_ prefix to guc_wopcm_size().
Remove unwanted checks in intel_uc.h. Rename huc_fw in struct intel_huc to
simply fw to avoid redundency.
v17: rebased.

Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Tested-by: Xiang Haihao <haihao.xiang@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
---
 drivers/gpu/drm/i915/Makefile           |   1 +
 drivers/gpu/drm/i915/i915_drv.c         |   4 +-
 drivers/gpu/drm/i915/i915_drv.h         |   3 +-
 drivers/gpu/drm/i915/i915_guc_reg.h     |   3 +
 drivers/gpu/drm/i915/intel_guc_loader.c |  11 +-
 drivers/gpu/drm/i915/intel_huc_loader.c | 263 ++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_uc.h         |  18 +++
 7 files changed, 296 insertions(+), 7 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_huc_loader.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 5196509..45ae124 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -57,6 +57,7 @@ i915-y += i915_cmd_parser.o \
 # general-purpose microcontroller (GuC) support
 i915-y += intel_uc.o \
 	  intel_guc_loader.o \
+	  intel_huc_loader.o \
 	  i915_guc_submission.o
 
 # autogenerated null render state
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 6428588..85a47c2 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -600,6 +600,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
 	if (ret)
 		goto cleanup_irq;
 
+	intel_huc_init(dev_priv);
 	intel_guc_init(dev_priv);
 
 	ret = i915_gem_init(dev_priv);
@@ -627,6 +628,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
 		DRM_ERROR("failed to idle hardware; continuing to unload!\n");
 	i915_gem_fini(dev_priv);
 cleanup_irq:
+	intel_huc_fini(dev);
 	intel_guc_fini(dev_priv);
 	drm_irq_uninstall(dev);
 	intel_teardown_gmbus(dev_priv);
@@ -1313,7 +1315,7 @@ void i915_driver_unload(struct drm_device *dev)
 
 	/* Flush any outstanding unpin_work. */
 	drain_workqueue(dev_priv->wq);
-
+	intel_huc_fini(dev);
 	intel_guc_fini(dev_priv);
 	i915_gem_fini(dev_priv);
 	intel_fbc_cleanup_cfb(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1a91409..7ac7730 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2147,6 +2147,7 @@ struct drm_i915_private {
 
 	struct intel_gvt *gvt;
 
+	struct intel_huc huc;
 	struct intel_guc guc;
 
 	struct intel_csr csr;
@@ -2921,7 +2922,7 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define HAS_GUC(dev_priv)	((dev_priv)->info.has_guc)
 #define HAS_GUC_UCODE(dev_priv)	(HAS_GUC(dev_priv))
 #define HAS_GUC_SCHED(dev_priv)	(HAS_GUC(dev_priv))
-
+#define HAS_HUC_UCODE(dev_priv)	(HAS_GUC(dev_priv))
 #define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
 
 #define HAS_POOLED_EU(dev_priv)	((dev_priv)->info.has_pooled_eu)
diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h b/drivers/gpu/drm/i915/i915_guc_reg.h
index 5e638fc..f9829f6 100644
--- a/drivers/gpu/drm/i915/i915_guc_reg.h
+++ b/drivers/gpu/drm/i915/i915_guc_reg.h
@@ -61,9 +61,12 @@
 #define   DMA_ADDRESS_SPACE_GTT		  (8 << 16)
 #define DMA_COPY_SIZE			_MMIO(0xc310)
 #define DMA_CTRL			_MMIO(0xc314)
+#define   HUC_UKERNEL			  (1<<9)
 #define   UOS_MOVE			  (1<<4)
 #define   START_DMA			  (1<<0)
 #define DMA_GUC_WOPCM_OFFSET		_MMIO(0xc340)
+#define   HUC_LOADING_AGENT_VCR		  (0<<1)
+#define   HUC_LOADING_AGENT_GUC		  (1<<1)
 #define   GUC_WOPCM_OFFSET_VALUE	  0x80000	/* 512KB */
 #define GUC_MAX_IDLE_COUNT		_MMIO(0xC3E4)
 
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 06e3e5c..8c77e94 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -309,8 +309,8 @@ static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv,
 	I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
 
 	/* Finally start the DMA */
-	I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));
-
+	I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA) |
+		_MASKED_BIT_DISABLE(HUC_UKERNEL));
 	/*
 	 * Wait for the DMA to complete & the GuC to start up.
 	 * NB: Docs recommend not using the interrupt for completion.
@@ -334,7 +334,7 @@ static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv,
 	return ret;
 }
 
-static u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
+u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv)
 {
 	u32 wopcm_size = GUC_WOPCM_TOP;
 
@@ -372,7 +372,7 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
 	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 
 	/* init WOPCM */
-	I915_WRITE(GUC_WOPCM_SIZE, guc_wopcm_size(dev_priv));
+	I915_WRITE(GUC_WOPCM_SIZE, intel_guc_wopcm_size(dev_priv));
 	I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE);
 
 	/* Enable MIA caching. GuC clock gating is disabled. */
@@ -511,6 +511,7 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
 		if (err)
 			goto fail;
 
+		intel_huc_load(dev_priv);
 		err = guc_ucode_xfer(dev_priv);
 		if (!err)
 			break;
@@ -658,7 +659,7 @@ void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
 		size = uc_fw->header_size + uc_fw->ucode_size;
 
 		/* Top 32k of WOPCM is reserved (8K stack + 24k RC6 context). */
-		if (size > guc_wopcm_size(dev_priv)) {
+		if (size > intel_guc_wopcm_size(dev_priv)) {
 			DRM_ERROR("Firmware is too large to fit in WOPCM\n");
 			goto fail;
 		}
diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c
new file mode 100644
index 0000000..98d631c
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_huc_loader.c
@@ -0,0 +1,263 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+#include <linux/firmware.h>
+#include "i915_drv.h"
+#include "intel_uc.h"
+
+/**
+ * DOC: HuC Firmware
+ *
+ * Motivation:
+ * GEN9 introduces a new dedicated firmware for usage in media HEVC (High
+ * Efficiency Video Coding) operations. Userspace can use the firmware
+ * capabilities by adding HuC specific commands to batch buffers.
+ *
+ * Implementation:
+ * The same firmware loader is used as the GuC. However, the actual
+ * loading to HW is deferred until GEM initialization is done.
+ *
+ * Note that HuC firmware loading must be done before GuC loading.
+ */
+
+#define SKL_HUC_FW_MAJOR 01
+#define SKL_HUC_FW_MINOR 07
+#define SKL_BLD_NUM 1398
+
+#define HUC_FW_PATH(platform, major, minor, bld_num) \
+	"i915/" __stringify(platform) "_huc_ver" __stringify(major) "_" \
+	__stringify(minor) "_" __stringify(bld_num) ".bin"
+
+#define I915_SKL_HUC_UCODE HUC_FW_PATH(skl, SKL_HUC_FW_MAJOR, \
+	SKL_HUC_FW_MINOR, SKL_BLD_NUM)
+MODULE_FIRMWARE(I915_SKL_HUC_UCODE);
+
+/**
+ * huc_ucode_xfer() - DMA's the firmware
+ * @dev_priv: the drm device
+ *
+ * This function takes the gem object containing the firmware, sets up the DMA
+ * engine MMIO, triggers the DMA operation and waits for it to finish.
+ *
+ * Transfer the firmware image to RAM for execution by the microcontroller.
+ *
+ * Return: 0 on success, non-zero on failure
+ */
+static int huc_ucode_xfer(struct drm_i915_private *dev_priv)
+{
+	struct intel_uc_fw *huc_fw = &dev_priv->huc.fw;
+	struct i915_vma *vma;
+	unsigned long offset = 0;
+	u32 size;
+	int ret;
+
+	ret = i915_gem_object_set_to_gtt_domain(huc_fw->uc_fw_obj, false);
+	if (ret) {
+		DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
+		return ret;
+	}
+
+	vma = i915_gem_object_ggtt_pin(huc_fw->uc_fw_obj, NULL, 0, 0, 0);
+	if (IS_ERR(vma)) {
+		DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
+		return PTR_ERR(vma);
+	}
+
+	/* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
+	I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
+
+	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+
+	/* init WOPCM */
+	I915_WRITE(GUC_WOPCM_SIZE, intel_guc_wopcm_size(dev_priv));
+	I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE |
+			HUC_LOADING_AGENT_GUC);
+
+	/* Set the source address for the uCode */
+	offset = i915_ggtt_offset(vma) + huc_fw->header_offset;
+	I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
+	I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
+
+	/* Hardware doesn't look at destination address for HuC. Set it to 0,
+	 * but still program the correct address space.
+	 */
+	I915_WRITE(DMA_ADDR_1_LOW, 0);
+	I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
+
+	size = huc_fw->header_size + huc_fw->ucode_size;
+	I915_WRITE(DMA_COPY_SIZE, size);
+
+	/* Start the DMA */
+	I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(HUC_UKERNEL | START_DMA));
+
+	/* Wait for DMA to finish */
+	ret = wait_for((I915_READ(DMA_CTRL) & START_DMA) == 0, 100);
+
+	DRM_DEBUG_DRIVER("HuC DMA transfer wait over with ret %d\n", ret);
+
+	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+	/*
+	 * We keep the object pages for reuse during resume. But we can unpin it
+	 * now that DMA has completed, so it doesn't continue to take up space.
+	 */
+	i915_vma_unpin(vma);
+
+	return ret;
+}
+
+/**
+ * intel_huc_init() - initiate HuC firmware loading request
+ * @dev_priv: the drm_i915_private device
+ *
+ * Called early during driver load, but after GEM is initialised. The loading
+ * will continue only when driver explicitly specify firmware name and version.
+ * All other cases are considered as INTEL_UC_FIRMWARE_NONE either because HW
+ * is not capable or driver yet support it. And there will be no error message
+ * for INTEL_UC_FIRMWARE_NONE cases.
+ *
+ * The DMA-copying to HW is done later when intel_huc_load() is called.
+ */
+void intel_huc_init(struct drm_i915_private *dev_priv)
+{
+	struct intel_huc *huc = &dev_priv->huc;
+	struct intel_uc_fw *huc_fw = &huc->fw;
+	const char *fw_path = NULL;
+
+	huc_fw->uc_fw_path = NULL;
+	huc_fw->fetch_status = INTEL_UC_FIRMWARE_NONE;
+	huc_fw->load_status = INTEL_UC_FIRMWARE_NONE;
+	huc_fw->fw_type = INTEL_UC_FW_TYPE_HUC;
+
+	if (!HAS_HUC_UCODE(dev_priv))
+		return;
+
+	if (IS_SKYLAKE(dev_priv)) {
+		fw_path = I915_SKL_HUC_UCODE;
+		huc_fw->major_ver_wanted = SKL_HUC_FW_MAJOR;
+		huc_fw->minor_ver_wanted = SKL_HUC_FW_MINOR;
+	}
+
+	huc_fw->uc_fw_path = fw_path;
+	huc_fw->fetch_status = INTEL_UC_FIRMWARE_PENDING;
+
+	DRM_DEBUG_DRIVER("HuC firmware pending, path %s\n", fw_path);
+
+	intel_uc_fw_fetch(dev_priv, huc_fw);
+}
+
+/**
+ * intel_huc_load() - load HuC uCode to device
+ * @dev_priv: the drm_i915_private device
+ *
+ * Called from gem_init_hw() during driver loading and also after a GPU reset.
+ * Be note that HuC loading must be done before GuC loading.
+ *
+ * The firmware image should have already been fetched into memory by the
+ * earlier call to intel_huc_init(), so here we need only check that
+ * is succeeded, and then transfer the image to the h/w.
+ *
+ * Return:	non-zero code on error
+ */
+int intel_huc_load(struct drm_i915_private *dev_priv)
+{
+	struct intel_uc_fw *huc_fw = &dev_priv->huc.fw;
+	int err;
+
+	if (huc_fw->fetch_status == INTEL_UC_FIRMWARE_NONE)
+		return 0;
+
+	DRM_DEBUG_DRIVER("%s fw status: fetch %s, load %s\n",
+		huc_fw->uc_fw_path,
+		intel_uc_fw_status_repr(huc_fw->fetch_status),
+		intel_uc_fw_status_repr(huc_fw->load_status));
+
+	if (huc_fw->fetch_status == INTEL_UC_FIRMWARE_SUCCESS &&
+	    huc_fw->load_status == INTEL_UC_FIRMWARE_FAIL)
+		return -ENOEXEC;
+
+	huc_fw->load_status = INTEL_UC_FIRMWARE_PENDING;
+
+	switch (huc_fw->fetch_status) {
+	case INTEL_UC_FIRMWARE_FAIL:
+		/* something went wrong :( */
+		err = -EIO;
+		goto fail;
+
+	case INTEL_UC_FIRMWARE_NONE:
+	case INTEL_UC_FIRMWARE_PENDING:
+	default:
+		/* "can't happen" */
+		WARN_ONCE(1, "HuC fw %s invalid fetch_status %s [%d]\n",
+			huc_fw->uc_fw_path,
+			intel_uc_fw_status_repr(huc_fw->fetch_status),
+			huc_fw->fetch_status);
+		err = -ENXIO;
+		goto fail;
+
+	case INTEL_UC_FIRMWARE_SUCCESS:
+		break;
+	}
+
+	err = huc_ucode_xfer(dev_priv);
+	if (err)
+		goto fail;
+
+	huc_fw->load_status = INTEL_UC_FIRMWARE_SUCCESS;
+
+	DRM_DEBUG_DRIVER("%s fw status: fetch %s, load %s\n",
+		huc_fw->uc_fw_path,
+		intel_uc_fw_status_repr(huc_fw->fetch_status),
+		intel_uc_fw_status_repr(huc_fw->load_status));
+
+	return 0;
+
+fail:
+	if (huc_fw->load_status == INTEL_UC_FIRMWARE_PENDING)
+		huc_fw->load_status = INTEL_UC_FIRMWARE_FAIL;
+
+	DRM_ERROR("Failed to complete HuC uCode load with ret %d\n", err);
+
+	return err;
+}
+
+/**
+ * intel_huc_fini() - clean up resources allocated for HuC
+ * @dev: the drm device
+ *
+ * Cleans up by releasing the huc firmware GEM obj.
+ */
+void intel_huc_fini(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct intel_uc_fw *huc_fw = &dev_priv->huc.fw;
+
+	mutex_lock(&dev->struct_mutex);
+	if (huc_fw->uc_fw_obj)
+		i915_gem_object_put(huc_fw->uc_fw_obj);
+	huc_fw->uc_fw_obj = NULL;
+	mutex_unlock(&dev->struct_mutex);
+
+	huc_fw->fetch_status = INTEL_UC_FIRMWARE_NONE;
+}
+
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index ad140e2..57aef56 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -24,6 +24,9 @@
 #ifndef _INTEL_UC_H_
 #define _INTEL_UC_H_
 
+#define HUC_STATUS2             _MMIO(0xD3B0)
+#define   HUC_FW_VERIFIED       (1<<7)
+
 #include "intel_guc_fwif.h"
 #include "i915_guc_reg.h"
 #include "intel_ringbuffer.h"
@@ -174,6 +177,13 @@ struct intel_guc {
 	struct mutex send_mutex;
 };
 
+struct intel_huc {
+	/* Generic uC firmware management */
+	struct intel_uc_fw fw;
+
+	/* HuC-specific additions */
+};
+
 /* intel_uc.c */
 void intel_uc_init_early(struct drm_i915_private *dev_priv);
 bool intel_guc_recv(struct drm_i915_private *dev_priv, u32 *status);
@@ -190,6 +200,9 @@ extern void intel_guc_fini(struct drm_i915_private *dev_priv);
 extern const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status);
 extern int intel_guc_suspend(struct drm_i915_private *dev_priv);
 extern int intel_guc_resume(struct drm_i915_private *dev_priv);
+void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
+	struct intel_uc_fw *uc_fw);
+u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv);
 
 /* i915_guc_submission.c */
 int i915_guc_submission_init(struct drm_i915_private *dev_priv);
@@ -204,4 +217,9 @@ void i915_guc_register(struct drm_i915_private *dev_priv);
 void i915_guc_unregister(struct drm_i915_private *dev_priv);
 int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val);
 
+/* intel_huc_loader.c */
+void intel_huc_init(struct drm_i915_private *dev_priv);
+void intel_huc_fini(struct drm_device *dev);
+int intel_huc_load(struct drm_i915_private *dev_priv);
+
 #endif
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 4/8] drm/i915/huc: Add BXT HuC Loading Support

[Anusha Srivatsa]

This patch adds the HuC Loading for the BXT by using
the updated file construction.

Version 1.7 of the HuC firmware.

v2: rebased.
v3: rebased on top of drm-tip
v4: rebased.
v5: rebased. Rename BXT_FW_MAJOR to BXT_HUC_FW_
v6: rebased.

Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/intel_huc_loader.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c
index 98d631c..c525f41 100644
--- a/drivers/gpu/drm/i915/intel_huc_loader.c
+++ b/drivers/gpu/drm/i915/intel_huc_loader.c
@@ -40,6 +40,10 @@
  * Note that HuC firmware loading must be done before GuC loading.
  */
 
+#define BXT_HUC_FW_MAJOR 01
+#define BXT_HUC_FW_MINOR 07
+#define BXT_BLD_NUM 1398
+
 #define SKL_HUC_FW_MAJOR 01
 #define SKL_HUC_FW_MINOR 07
 #define SKL_BLD_NUM 1398
@@ -52,6 +56,9 @@
 	SKL_HUC_FW_MINOR, SKL_BLD_NUM)
 MODULE_FIRMWARE(I915_SKL_HUC_UCODE);
 
+#define I915_BXT_HUC_UCODE HUC_FW_PATH(bxt, BXT_HUC_FW_MAJOR, \
+	BXT_HUC_FW_MINOR, BXT_BLD_NUM)
+MODULE_FIRMWARE(I915_BXT_HUC_UCODE);
 /**
  * huc_ucode_xfer() - DMA's the firmware
  * @dev_priv: the drm device
@@ -156,6 +163,10 @@ void intel_huc_init(struct drm_i915_private *dev_priv)
 		fw_path = I915_SKL_HUC_UCODE;
 		huc_fw->major_ver_wanted = SKL_HUC_FW_MAJOR;
 		huc_fw->minor_ver_wanted = SKL_HUC_FW_MINOR;
+	} else if (IS_BROXTON(dev_priv)) {
+		fw_path = I915_BXT_HUC_UCODE;
+		huc_fw->major_ver_wanted = BXT_HUC_FW_MAJOR;
+		huc_fw->minor_ver_wanted = BXT_HUC_FW_MINOR;
 	}
 
 	huc_fw->uc_fw_path = fw_path;
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 5/8] drm/i915/HuC: Add KBL huC loading Support

[Anusha Srivatsa]

This patch adds the support to load HuC on KBL
Version 2.0

v2: rebased.
v3: rebased on top of drm-tip
v4: rebased.
v5: rebased. Rename KBL_FW_ to KBL_HUC_FW_
v6: rebased. Remove old checks.

Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/intel_huc_loader.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c
index c525f41..75f3dc5 100644
--- a/drivers/gpu/drm/i915/intel_huc_loader.c
+++ b/drivers/gpu/drm/i915/intel_huc_loader.c
@@ -48,6 +48,10 @@
 #define SKL_HUC_FW_MINOR 07
 #define SKL_BLD_NUM 1398
 
+#define KBL_HUC_FW_MAJOR 02
+#define KBL_HUC_FW_MINOR 00
+#define KBL_BLD_NUM 1810
+
 #define HUC_FW_PATH(platform, major, minor, bld_num) \
 	"i915/" __stringify(platform) "_huc_ver" __stringify(major) "_" \
 	__stringify(minor) "_" __stringify(bld_num) ".bin"
@@ -59,6 +63,11 @@ MODULE_FIRMWARE(I915_SKL_HUC_UCODE);
 #define I915_BXT_HUC_UCODE HUC_FW_PATH(bxt, BXT_HUC_FW_MAJOR, \
 	BXT_HUC_FW_MINOR, BXT_BLD_NUM)
 MODULE_FIRMWARE(I915_BXT_HUC_UCODE);
+
+#define I915_KBL_HUC_UCODE HUC_FW_PATH(kbl, KBL_HUC_FW_MAJOR, \
+	KBL_HUC_FW_MINOR, KBL_BLD_NUM)
+MODULE_FIRMWARE(I915_KBL_HUC_UCODE);
+
 /**
  * huc_ucode_xfer() - DMA's the firmware
  * @dev_priv: the drm device
@@ -167,6 +176,10 @@ void intel_huc_init(struct drm_i915_private *dev_priv)
 		fw_path = I915_BXT_HUC_UCODE;
 		huc_fw->major_ver_wanted = BXT_HUC_FW_MAJOR;
 		huc_fw->minor_ver_wanted = BXT_HUC_FW_MINOR;
+	} else if (IS_KABYLAKE(dev_priv)) {
+		fw_path = I915_KBL_HUC_UCODE;
+		huc_fw->major_ver_wanted = KBL_HUC_FW_MAJOR;
+		huc_fw->minor_ver_wanted = KBL_HUC_FW_MINOR;
 	}
 
 	huc_fw->uc_fw_path = fw_path;
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 6/8] drm/i915/huc: Add debugfs for HuC loading status check

[Anusha Srivatsa]

From: Peter Antoine <peter.antoine@intel.com>

Add debugfs entry for HuC loading status check.

v2: rebase on-top of drm-intel-nightly.
v3: rebased again.
v7: rebased.
v8: rebased.
v9: rebased.
v10: rebased.
v11: rebased on top of drm-tip
v12: rebased.
v13: rebased.

Tested-by: Xiang Haihao <haihao.xiang@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
Reviewed-by: Jeff McGee <jeff.mcgee@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 0a3c575..f43b41e 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2325,6 +2325,36 @@ static int i915_llc(struct seq_file *m, void *data)
 	return 0;
 }
 
+static int i915_huc_load_status_info(struct seq_file *m, void *data)
+{
+	struct drm_i915_private *dev_priv = node_to_i915(m->private);
+	struct intel_uc_fw *huc_fw = &dev_priv->huc.fw;
+
+	if (!HAS_HUC_UCODE(dev_priv))
+		return 0;
+
+	seq_puts(m, "HuC firmware status:\n");
+	seq_printf(m, "\tpath: %s\n", huc_fw->uc_fw_path);
+	seq_printf(m, "\tfetch: %s\n",
+		intel_uc_fw_status_repr(huc_fw->fetch_status));
+	seq_printf(m, "\tload: %s\n",
+		intel_uc_fw_status_repr(huc_fw->load_status));
+	seq_printf(m, "\tversion wanted: %d.%d\n",
+		huc_fw->major_ver_wanted, huc_fw->minor_ver_wanted);
+	seq_printf(m, "\tversion found: %d.%d\n",
+		huc_fw->major_ver_found, huc_fw->minor_ver_found);
+	seq_printf(m, "\theader: offset is %d; size = %d\n",
+		huc_fw->header_offset, huc_fw->header_size);
+	seq_printf(m, "\tuCode: offset is %d; size = %d\n",
+		huc_fw->ucode_offset, huc_fw->ucode_size);
+	seq_printf(m, "\tRSA: offset is %d; size = %d\n",
+		huc_fw->rsa_offset, huc_fw->rsa_size);
+
+	seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2));
+
+	return 0;
+}
+
 static int i915_guc_load_status_info(struct seq_file *m, void *data)
 {
 	struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -4553,6 +4583,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
 	{"i915_guc_info", i915_guc_info, 0},
 	{"i915_guc_load_status", i915_guc_load_status_info, 0},
 	{"i915_guc_log_dump", i915_guc_log_dump, 0},
+	{"i915_huc_load_status", i915_huc_load_status_info, 0},
 	{"i915_frequency_info", i915_frequency_info, 0},
 	{"i915_hangcheck_info", i915_hangcheck_info, 0},
 	{"i915_drpc_info", i915_drpc_info, 0},
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 7/8] drm/i915/huc: Support HuC authentication

[Anusha Srivatsa]

From: Peter Antoine <peter.antoine@intel.com>

The HuC authentication is done by host2guc call. The HuC RSA keys
are sent to GuC for authentication.

v2: rebased on top of drm-intel-nightly.
    changed name format and upped version 1.7.
v3: rebased on top of drm-intel-nightly.
v4: changed wait_for_automic to wait_for
v5: rebased.
v7: rebased.
v8: rebased.
v9: rebased. Rename intel_huc_auh() to intel_guc_auth_huc()
and place the prototype in intel_guc.h,correct the comments.
v10: rebased.
v11: rebased.
v12: rebased on top of drm-tip
v13: rebased. Moved intel_guc_auth_huc from i915_guc_submission.c
to intel_uc.c.Update dev to dev_priv in intel_guc_auth_huc().
Renamed HOST2GUC_ACTION_AUTHENTICATE_HUC TO INTEL_GUC_ACTION_
AUTHENTICATE_HUC
v14: rebased.
v15: rebased. Add newline on DRM_ERRORs that already dont have one.

Tested-by: Xiang Haihao <haihao.xiang@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
---
 drivers/gpu/drm/i915/intel_guc_fwif.h   |  1 +
 drivers/gpu/drm/i915/intel_guc_loader.c |  2 ++
 drivers/gpu/drm/i915/intel_uc.c         | 62 +++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_uc.h         |  1 +
 4 files changed, 66 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
index ed1ab40..ce4e05e 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -506,6 +506,7 @@ enum intel_guc_action {
 	INTEL_GUC_ACTION_EXIT_S_STATE = 0x502,
 	INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003,
 	INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000,
+	INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
 	INTEL_GUC_ACTION_LIMIT
 };
 
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 8c77e94..85c0a2a 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -529,6 +529,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
 		intel_uc_fw_status_repr(guc_fw->fetch_status),
 		intel_uc_fw_status_repr(guc_fw->load_status));
 
+	intel_guc_auth_huc(dev_priv);
+
 	if (i915.enable_guc_submission) {
 		if (i915.guc_log_level >= 0)
 			gen9_enable_guc_interrupts(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 8ae6795..b858d36 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -138,3 +138,65 @@ int intel_guc_log_control(struct intel_guc *guc, u32 control_val)
 
 	return intel_guc_send(guc, action, ARRAY_SIZE(action));
 }
+
+/**
+ * intel_guc_auth_huc() - authenticate ucode
+ * @dev_priv: the drm_i915_device
+ *
+ * Triggers a HuC fw authentication request to the GuC via intel_guc_action_
+ * authenticate_huc interface.
+ * interface.
+ */
+void intel_guc_auth_huc(struct drm_i915_private *dev_priv)
+{
+	struct intel_guc *guc = &dev_priv->guc;
+	struct intel_huc *huc = &dev_priv->huc;
+	struct i915_vma *vma;
+	int ret;
+	u32 data[2];
+
+	/* Bypass the case where there is no HuC firmware */
+	if (huc->fw.fetch_status == INTEL_UC_FIRMWARE_NONE ||
+		huc->fw.load_status == INTEL_UC_FIRMWARE_NONE)
+		return;
+
+	if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS) {
+		DRM_ERROR("HuC: GuC fw wasn't loaded. Can't authenticate\n");
+		return;
+	}
+
+	if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS) {
+		DRM_ERROR("HuC: fw wasn't loaded. Nothing to authenticate\n");
+		return;
+	}
+
+	vma = i915_gem_object_ggtt_pin(huc->fw.uc_fw_obj, NULL, 0, 0, 0);
+	if (IS_ERR(vma)) {
+		DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
+		return;
+	}
+
+
+	/* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
+	I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
+
+	/* Specify auth action and where public signature is. */
+	data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC;
+	data[1] = i915_ggtt_offset(vma) + huc->fw.rsa_offset;
+
+	ret = intel_guc_send(guc, data, ARRAY_SIZE(data));
+	if (ret) {
+		DRM_ERROR("HuC: GuC did not ack Auth request\n");
+		goto out;
+	}
+
+	/* Check authentication status, it should be done by now */
+	ret = wait_for((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) > 0, 50);
+	if (ret) {
+		DRM_ERROR("HuC: Authentication failed\n");
+		goto out;
+	}
+
+out:
+	i915_vma_unpin(vma);
+}
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index 57aef56..e69d47c 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -192,6 +192,7 @@ int intel_guc_sample_forcewake(struct intel_guc *guc);
 int intel_guc_log_flush_complete(struct intel_guc *guc);
 int intel_guc_log_flush(struct intel_guc *guc);
 int intel_guc_log_control(struct intel_guc *guc, u32 control_val);
+void intel_guc_auth_huc(struct drm_i915_private *dev_priv);
 
 /* intel_guc_loader.c */
 extern void intel_guc_init(struct drm_i915_private *dev_priv);
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 8/8] drm/i915/get_params: Add HuC status to getparams

[Anusha Srivatsa]

From: Peter Antoine <peter.antoine@intel.com>

This patch will allow for getparams to return the status of the HuC.
As the HuC has to be validated by the GuC this patch uses the validated
status to show when the HuC is loaded and ready for use. You cannot use
the loaded status as with the GuC as the HuC is verified after it is
loaded and is not usable until it is verified.

v2: removed the forewakes as the registers are already force-woken.
     (T.Ursulin)
v4: rebased.
v5: rebased on top of drm-tip.
v6: rebased. Removed any reference to intel_huc.h
v7: rebased. Rename I915_PARAM_HAS_HUC to I915_PARAM_HUC_STATUS.
Remove intel_is_huc_valid() since it is used only in one place.
Put the case of I915_PARAM_HAS_HUC() in the right place.
v8: rebased. Add a comment to specify that I915_READ(reg)
does not read garbage value. The register HUC_STATUS2 is force
woken and no rpm is needed.

Signed-off-by: Peter Antoine <peter.antoine@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c         | 7 +++++++
 drivers/gpu/drm/i915/intel_huc_loader.c | 1 -
 include/uapi/drm/i915_drm.h             | 1 +
 3 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 85a47c2..c4f0620 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -49,6 +49,7 @@
 #include "i915_trace.h"
 #include "i915_vgpu.h"
 #include "intel_drv.h"
+#include "intel_uc.h"
 
 static struct drm_driver driver;
 
@@ -315,6 +316,12 @@ static int i915_getparam(struct drm_device *dev, void *data,
 	case I915_PARAM_MIN_EU_IN_POOL:
 		value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
 		break;
+	case I915_PARAM_HUC_STATUS:
+		/* The register is already force-woken. We dont need
+		 * any rpm here
+		 */
+		value = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
+		break;
 	case I915_PARAM_MMAP_GTT_VERSION:
 		/* Though we've started our numbering from 1, and so class all
 		 * earlier versions as 0, in effect their value is undefined as
diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c
index 75f3dc5..dd42676 100644
--- a/drivers/gpu/drm/i915/intel_huc_loader.c
+++ b/drivers/gpu/drm/i915/intel_huc_loader.c
@@ -284,4 +284,3 @@ void intel_huc_fini(struct drm_device *dev)
 
 	huc_fw->fetch_status = INTEL_UC_FIRMWARE_NONE;
 }
-
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index da32c2f..57093b4 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -395,6 +395,7 @@ typedef struct drm_i915_irq_wait {
  * priorities and the driver will attempt to execute batches in priority order.
  */
 #define I915_PARAM_HAS_SCHEDULER	 41
+#define I915_PARAM_HUC_STATUS		 42
 
 typedef struct drm_i915_getparam {
 	__s32 param;
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 7/8] drm/i915/huc: Support HuC authentication

[Chris Wilson]

On Thu, Dec 22, 2016 at 03:12:23PM -0800, Anusha Srivatsa wrote:
> +void intel_guc_auth_huc(struct drm_i915_private *dev_priv)
> +{
> +	struct intel_guc *guc = &dev_priv->guc;
> +	struct intel_huc *huc = &dev_priv->huc;
> +	struct i915_vma *vma;
> +	int ret;
> +	u32 data[2];
> +
> +	/* Bypass the case where there is no HuC firmware */
> +	if (huc->fw.fetch_status == INTEL_UC_FIRMWARE_NONE ||
> +		huc->fw.load_status == INTEL_UC_FIRMWARE_NONE)
> +		return;
> +
> +	if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS) {
> +		DRM_ERROR("HuC: GuC fw wasn't loaded. Can't authenticate\n");
> +		return;
> +	}
> +
> +	if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS) {
> +		DRM_ERROR("HuC: fw wasn't loaded. Nothing to authenticate\n");
> +		return;
> +	}
> +
> +	vma = i915_gem_object_ggtt_pin(huc->fw.uc_fw_obj, NULL, 0, 0, 0);
> +	if (IS_ERR(vma)) {
> +		DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
> +		return;
> +	}
> +
> +
> +	/* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
> +	I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);

Still working on stopping this from frequently popping up in code
outside of the GTT routines.

> +	/* Specify auth action and where public signature is. */
> +	data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC;
> +	data[1] = i915_ggtt_offset(vma) + huc->fw.rsa_offset;
> +
> +	ret = intel_guc_send(guc, data, ARRAY_SIZE(data));
> +	if (ret) {
> +		DRM_ERROR("HuC: GuC did not ack Auth request\n");
> +		goto out;
> +	}
> +
> +	/* Check authentication status, it should be done by now */
> +	ret = wait_for((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) > 0, 50);

ret = intel_wait_for_register(dev_priv,
			      HUC_STATUS2,
			      HUC_FW_VERIFIED,
			      HUC_FW_VERIFIED,
			      50);

wait_for() is a rather large macro, and intel_wait_for_register()
employs the spin then sleep optimisation for quick responses.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.BAT: success for HuC Loading Patches

[Patchwork]

== Series Details ==

Series: HuC Loading Patches
URL   : https://patchwork.freedesktop.org/series/17150/
State : success

== Summary ==

Series 17150v1 HuC Loading Patches
https://patchwork.freedesktop.org/api/1.0/series/17150/revisions/1/mbox/


fi-bdw-5557u     total:246  pass:232  dwarn:0   dfail:0   fail:0   skip:14 
fi-bsw-n3050     total:246  pass:207  dwarn:0   dfail:0   fail:0   skip:39 
fi-bxt-j4205     total:246  pass:224  dwarn:0   dfail:0   fail:0   skip:22 
fi-bxt-t5700     total:82   pass:69   dwarn:0   dfail:0   fail:0   skip:12 
fi-byt-j1900     total:246  pass:219  dwarn:0   dfail:0   fail:0   skip:27 
fi-byt-n2820     total:246  pass:215  dwarn:0   dfail:0   fail:0   skip:31 
fi-hsw-4770      total:246  pass:227  dwarn:0   dfail:0   fail:0   skip:19 
fi-hsw-4770r     total:246  pass:227  dwarn:0   dfail:0   fail:0   skip:19 
fi-ivb-3520m     total:246  pass:225  dwarn:0   dfail:0   fail:0   skip:21 
fi-ivb-3770      total:246  pass:225  dwarn:0   dfail:0   fail:0   skip:21 
fi-kbl-7500u     total:246  pass:225  dwarn:0   dfail:0   fail:0   skip:21 
fi-skl-6260u     total:246  pass:233  dwarn:0   dfail:0   fail:0   skip:13 
fi-skl-6700hq    total:246  pass:226  dwarn:0   dfail:0   fail:0   skip:20 
fi-skl-6700k     total:246  pass:222  dwarn:3   dfail:0   fail:0   skip:21 
fi-skl-6770hq    total:246  pass:233  dwarn:0   dfail:0   fail:0   skip:13 
fi-snb-2600      total:246  pass:214  dwarn:0   dfail:0   fail:0   skip:32 

7165fdc7f0b0b536557fcd0a222d083a901be57c drm-tip: 2016y-12m-22d-19h-42m-25s UTC integration manifest
e8b433c drm/i915/get_params: Add HuC status to getparams
6ffbe20 drm/i915/huc: Support HuC authentication
8cb202b drm/i915/huc: Add debugfs for HuC loading status check
b1bbca7 drm/i915/HuC: Add KBL huC loading Support
6a3c405 drm/i915/huc: Add BXT HuC Loading Support
97fad48 drm/i915/huc: Add HuC fw loading support
b2a545d drm/i915/huc: Unified css_header struct for GuC and HuC
170ce27 drm/i915/guc: Make the GuC fw loading helper functions general

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3381/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 1/8] drm/i915/guc: Make the GuC fw loading helper functions general

[Arkadiusz Hiler]

On Thu, Dec 22, 2016 at 03:12:17PM -0800, Anusha Srivatsa wrote:
> From: Peter Antoine <peter.antoine@intel.com>
> 
> Rename some of the GuC fw loading code to make them more general. We
> will utilise them for HuC loading as well.
>      s/intel_guc_fw/intel_uc_fw/g
>      s/GUC_FIRMWARE/UC_FIRMWARE/g
> 
> Struct intel_guc_fw is renamed to intel_uc_fw. Prefix of tts members,
> such as 'guc' or 'guc_fw' either is renamed to 'uc' or removed for
> same purpose.
> 
> v2: rebased on top of nightly.
>     reapplied the search/replace as upstream code as changed.
> v3: rebased again on drm-nightly.
> v4: removed G from messages in shared fw fetch function.
> v5: rebased.
> v7: rebased.
> v8: rebased.
> v9: rebased.
> v10: rebased.
> v11: rebased.
> v12: rebased on top of drm-tip
> v13: rebased.Updated dev to dev_priv in intel_guc_setup(), guc_fw_getch()
> and intel_guc_init().
> v14: rebased. Remove uint32_t fw_type to patch 2. Add INTEL_ prefix for
> fields in enum intel_uc_fw_status. Remove uc_dev field since its never
> used.Rename uc_fw to just fw and guc_fw to fw to avoid redundency.
> v15: rebased. Remove sections of code that were commented and no longer
> required.
> 
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Alex Dai <yu.dai@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>

-- 
Cheers,
Arek
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 2/8] drm/i915/huc: Unified css_header struct for GuC and HuC

[Arkadiusz Hiler]

On Thu, Dec 22, 2016 at 03:12:18PM -0800, Anusha Srivatsa wrote:
> From: Peter Antoine <peter.antoine@intel.com>
> 
> HuC firmware css header has almost exactly same definition as GuC
> firmware except for the sw_version. Also, add a new member fw_type
> into intel_uc_fw to indicate what kind of fw it is. So, the loader
> will pull right sw_version from header.
> 
> v2: rebased on-top of drm-intel-nightly
> v3: rebased on-top of drm-intel-nightly (again).
> v4: rebased + spaces.
> v7: rebased.
> v8: rebased.
> v9: rebased. Rename device_id to guc_branch_client_version,
> make guc_sw_version a union. <Jeff Mcgee>. Put UC_FW_TYPE_GUC
> and UC_FW_TYPE_HUC into an enum.
> v10: rebased.
> v11: rebased.
> v12: rebased on top of drm-tip.
> v13: rebased.Update dev to dev_priv in intel_uc_fw_fetch
> v14: rebased. Add INTEL_ prefix to an enum. Add fw_type declaration
> from patch 1.Combine two different unions for huc and guc version,
> reserved etc into one union with two structs.
> v15: rebased.
> 
> Tested-by: Xiang Haihao <haihao.xiang@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Alex Dai <yu.dai@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_guc_fwif.h   | 23 ++++++++++++++----
>  drivers/gpu/drm/i915/intel_guc_loader.c | 41 ++++++++++++++++++++++-----------
>  drivers/gpu/drm/i915/intel_uc.h         |  6 +++++
>  3 files changed, 53 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
> index 3202b32..ed1ab40 100644
> --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
> @@ -145,7 +145,7 @@
>   * The GuC firmware layout looks like this:
>   *
>   *     +-------------------------------+
> - *     |        guc_css_header         |
> + *     |         uc_css_header         |
>   *     |                               |
>   *     | contains major/minor version  |
>   *     +-------------------------------+
> @@ -172,9 +172,16 @@
>   * 3. Length info of each component can be found in header, in dwords.
>   * 4. Modulus and exponent key are not required by driver. They may not appear
>   *    in fw. So driver will load a truncated firmware in this case.
> + *
> + * HuC firmware layout is same as GuC firmware.
> + *
> + * HuC firmware css header is different. However, the only difference is where
> + * the version information is saved. The uc_css_header is unified to support
> + * both. Driver should get HuC version from uc_css_header.huc_sw_version, while
> + * uc_css_header.guc_sw_version for GuC.
>   */
>  
> -struct guc_css_header {
> +struct uc_css_header {
>  	uint32_t module_type;
>  	/* header_size includes all non-uCode bits, including css_header, rsa
>  	 * key, modulus key and exponent data. */
> @@ -205,8 +212,16 @@ struct guc_css_header {
>  
>  	char username[8];
>  	char buildnumber[12];
> -	uint32_t device_id;
> -	uint32_t guc_sw_version;
> +	union {
> +		struct {
> +			uint32_t branch_client_version;
> +			uint32_t sw_version;
> +	} guc;
> +		struct {
> +			uint32_t sw_version;
> +			uint32_t reserved;
> +	} huc;
> +	};
>  	uint32_t prod_preprod_fw;
>  	uint32_t reserved[12];
>  	uint32_t header_info;
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> index ffe53dd7..06e3e5c 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -593,7 +593,7 @@ void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
>  	struct pci_dev *pdev = dev_priv->drm.pdev;
>  	struct drm_i915_gem_object *obj;
>  	const struct firmware *fw = NULL;
> -	struct guc_css_header *css;
> +	struct uc_css_header *css;
>  	size_t size;
>  	int err;
>  
> @@ -610,19 +610,19 @@ void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
>  		uc_fw->uc_fw_path, fw);
>  
>  	/* Check the size of the blob before examining buffer contents */
> -	if (fw->size < sizeof(struct guc_css_header)) {
> +	if (fw->size < sizeof(struct uc_css_header)) {
>  		DRM_NOTE("Firmware header is missing\n");
>  		goto fail;
>  	}
>  
> -	css = (struct guc_css_header *)fw->data;
> +	css = (struct uc_css_header *)fw->data;
>  
>  	/* Firmware bits always start from header */
>  	uc_fw->header_offset = 0;
>  	uc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
>  		css->key_size_dw - css->exponent_size_dw) * sizeof(u32);
>  
> -	if (uc_fw->header_size != sizeof(struct guc_css_header)) {
> +	if (uc_fw->header_size != sizeof(struct uc_css_header)) {
>  		DRM_NOTE("CSS header definition mismatch\n");
>  		goto fail;
>  	}
> @@ -646,21 +646,36 @@ void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
>  		goto fail;
>  	}
>  
> -	/* Header and uCode will be loaded to WOPCM. Size of the two. */
> -	size = uc_fw->header_size + uc_fw->ucode_size;
> -	if (size > guc_wopcm_size(dev_priv)) {
> -		DRM_NOTE("Firmware is too large to fit in WOPCM\n");
> -		goto fail;
> -	}
> -
>  	/*
>  	 * The GuC firmware image has the version number embedded at a well-known
>  	 * offset within the firmware blob; note that major / minor version are
>  	 * TWO bytes each (i.e. u16), although all pointers and offsets are defined
>  	 * in terms of bytes (u8).
>  	 */
> -	uc_fw->major_ver_found = css->guc_sw_version >> 16;
> -	uc_fw->minor_ver_found = css->guc_sw_version & 0xFFFF;
> +	switch (uc_fw->fw_type) {
> +	case INTEL_UC_FW_TYPE_GUC:
> +		/* Header and uCode will be loaded to WOPCM. Size of the two. */
> +		size = uc_fw->header_size + uc_fw->ucode_size;
> +
> +		/* Top 32k of WOPCM is reserved (8K stack + 24k RC6 context). */
> +		if (size > guc_wopcm_size(dev_priv)) {
> +			DRM_ERROR("Firmware is too large to fit in WOPCM\n");
> +			goto fail;
> +		}
> +		uc_fw->major_ver_found = css->guc.sw_version >> 16;
> +		uc_fw->minor_ver_found = css->guc.sw_version & 0xFFFF;
> +		break;
> +
> +	case INTEL_UC_FW_TYPE_HUC:
> +		uc_fw->major_ver_found = css->huc.sw_version >> 16;
> +		uc_fw->minor_ver_found = css->huc.sw_version & 0xFFFF;
> +		break;
> +
> +	default:
> +		DRM_ERROR("Unknown firmware type %d\n", uc_fw->fw_type);
> +		err = -ENOEXEC;
> +		goto fail;
> +	}
>  
>  	if (uc_fw->major_ver_found != uc_fw->major_ver_wanted ||
>  	    uc_fw->minor_ver_found < uc_fw->minor_ver_wanted) {
> diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
> index 893bcec..ad140e2 100644
> --- a/drivers/gpu/drm/i915/intel_uc.h
> +++ b/drivers/gpu/drm/i915/intel_uc.h
> @@ -98,6 +98,11 @@ enum intel_uc_fw_status {
>  	INTEL_UC_FIRMWARE_SUCCESS
>  };
>  
> +enum {
> +	INTEL_UC_FW_TYPE_GUC,
> +	INTEL_UC_FW_TYPE_HUC
> +};
> +
>  /*
>   * This structure encapsulates all the data needed during the process
>   * of fetching, caching, and loading the firmware image into the GuC.
> @@ -114,6 +119,7 @@ struct intel_uc_fw {
>  	uint16_t major_ver_found;
>  	uint16_t minor_ver_found;
>  
> +	uint32_t fw_type;

Any reason why we use uint32_t instead of a named enum type here?

>  	uint32_t header_size;
>  	uint32_t header_offset;
>  	uint32_t rsa_size;
> -- 
> 2.7.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Cheers,
Arek
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams

[Arkadiusz Hiler]

On Thu, Dec 22, 2016 at 03:12:24PM -0800, Anusha Srivatsa wrote:
> From: Peter Antoine <peter.antoine@intel.com>
> 
> This patch will allow for getparams to return the status of the HuC.
> As the HuC has to be validated by the GuC this patch uses the validated
> status to show when the HuC is loaded and ready for use. You cannot use
> the loaded status as with the GuC as the HuC is verified after it is
> loaded and is not usable until it is verified.
> 
> v2: removed the forewakes as the registers are already force-woken.
>      (T.Ursulin)
> v4: rebased.
> v5: rebased on top of drm-tip.
> v6: rebased. Removed any reference to intel_huc.h
> v7: rebased. Rename I915_PARAM_HAS_HUC to I915_PARAM_HUC_STATUS.
> Remove intel_is_huc_valid() since it is used only in one place.
> Put the case of I915_PARAM_HAS_HUC() in the right place.
> v8: rebased. Add a comment to specify that I915_READ(reg)
> does not read garbage value. The register HUC_STATUS2 is force
> woken and no rpm is needed.
> 
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>

Where is your s-o-b?

other than that:
Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>

-- 
Cheers,
Arek
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 4/8] drm/i915/huc: Add BXT HuC Loading Support

[Arkadiusz Hiler]

On Thu, Dec 22, 2016 at 03:12:20PM -0800, Anusha Srivatsa wrote:
> This patch adds the HuC Loading for the BXT by using
> the updated file construction.
> 
> Version 1.7 of the HuC firmware.
> 
> v2: rebased.
> v3: rebased on top of drm-tip
> v4: rebased.
> v5: rebased. Rename BXT_FW_MAJOR to BXT_HUC_FW_
> v6: rebased.
> 
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>

-- 
Cheers,
Arek
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 5/8] drm/i915/HuC: Add KBL huC loading Support

[Arkadiusz Hiler]

On Thu, Dec 22, 2016 at 03:12:21PM -0800, Anusha Srivatsa wrote:
> This patch adds the support to load HuC on KBL
> Version 2.0
> 
> v2: rebased.
> v3: rebased on top of drm-tip
> v4: rebased.
> v5: rebased. Rename KBL_FW_ to KBL_HUC_FW_
> v6: rebased. Remove old checks.
> 
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>

-- 
Cheers,
Arek
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 2/8] drm/i915/huc: Unified css_header struct for GuC and HuC

[Srivatsa, Anusha]

>-----Original Message-----
>From: Hiler, Arkadiusz
>Sent: Friday, December 23, 2016 6:22 AM
>To: Srivatsa, Anusha <anusha.srivatsa@intel.com>
>Cc: intel-gfx@lists.freedesktop.org; Alex Dai <yu.dai@intel.com>; Peter Antoine
><peter.antoine@intel.com>
>Subject: Re: [Intel-gfx] [PATCH 2/8] drm/i915/huc: Unified css_header struct for
>GuC and HuC
>
>On Thu, Dec 22, 2016 at 03:12:18PM -0800, Anusha Srivatsa wrote:
>> From: Peter Antoine <peter.antoine@intel.com>
>>
>> HuC firmware css header has almost exactly same definition as GuC
>> firmware except for the sw_version. Also, add a new member fw_type
>> into intel_uc_fw to indicate what kind of fw it is. So, the loader
>> will pull right sw_version from header.
>>
>> v2: rebased on-top of drm-intel-nightly
>> v3: rebased on-top of drm-intel-nightly (again).
>> v4: rebased + spaces.
>> v7: rebased.
>> v8: rebased.
>> v9: rebased. Rename device_id to guc_branch_client_version, make
>> guc_sw_version a union. <Jeff Mcgee>. Put UC_FW_TYPE_GUC and
>> UC_FW_TYPE_HUC into an enum.
>> v10: rebased.
>> v11: rebased.
>> v12: rebased on top of drm-tip.
>> v13: rebased.Update dev to dev_priv in intel_uc_fw_fetch
>> v14: rebased. Add INTEL_ prefix to an enum. Add fw_type declaration
>> from patch 1.Combine two different unions for huc and guc version,
>> reserved etc into one union with two structs.
>> v15: rebased.
>>
>> Tested-by: Xiang Haihao <haihao.xiang@intel.com>
>> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>> Signed-off-by: Alex Dai <yu.dai@intel.com>
>> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
>> ---
>>  drivers/gpu/drm/i915/intel_guc_fwif.h   | 23 ++++++++++++++----
>>  drivers/gpu/drm/i915/intel_guc_loader.c | 41 ++++++++++++++++++++++-------
>----
>>  drivers/gpu/drm/i915/intel_uc.h         |  6 +++++
>>  3 files changed, 53 insertions(+), 17 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h
>> b/drivers/gpu/drm/i915/intel_guc_fwif.h
>> index 3202b32..ed1ab40 100644
>> --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
>> +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
>> @@ -145,7 +145,7 @@
>>   * The GuC firmware layout looks like this:
>>   *
>>   *     +-------------------------------+
>> - *     |        guc_css_header         |
>> + *     |         uc_css_header         |
>>   *     |                               |
>>   *     | contains major/minor version  |
>>   *     +-------------------------------+
>> @@ -172,9 +172,16 @@
>>   * 3. Length info of each component can be found in header, in dwords.
>>   * 4. Modulus and exponent key are not required by driver. They may not
>appear
>>   *    in fw. So driver will load a truncated firmware in this case.
>> + *
>> + * HuC firmware layout is same as GuC firmware.
>> + *
>> + * HuC firmware css header is different. However, the only difference
>> + is where
>> + * the version information is saved. The uc_css_header is unified to
>> + support
>> + * both. Driver should get HuC version from
>> + uc_css_header.huc_sw_version, while
>> + * uc_css_header.guc_sw_version for GuC.
>>   */
>>
>> -struct guc_css_header {
>> +struct uc_css_header {
>>  	uint32_t module_type;
>>  	/* header_size includes all non-uCode bits, including css_header, rsa
>>  	 * key, modulus key and exponent data. */ @@ -205,8 +212,16 @@
>> struct guc_css_header {
>>
>>  	char username[8];
>>  	char buildnumber[12];
>> -	uint32_t device_id;
>> -	uint32_t guc_sw_version;
>> +	union {
>> +		struct {
>> +			uint32_t branch_client_version;
>> +			uint32_t sw_version;
>> +	} guc;
>> +		struct {
>> +			uint32_t sw_version;
>> +			uint32_t reserved;
>> +	} huc;
>> +	};
>>  	uint32_t prod_preprod_fw;
>>  	uint32_t reserved[12];
>>  	uint32_t header_info;
>> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
>> b/drivers/gpu/drm/i915/intel_guc_loader.c
>> index ffe53dd7..06e3e5c 100644
>> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
>> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
>> @@ -593,7 +593,7 @@ void intel_uc_fw_fetch(struct drm_i915_private
>*dev_priv,
>>  	struct pci_dev *pdev = dev_priv->drm.pdev;
>>  	struct drm_i915_gem_object *obj;
>>  	const struct firmware *fw = NULL;
>> -	struct guc_css_header *css;
>> +	struct uc_css_header *css;
>>  	size_t size;
>>  	int err;
>>
>> @@ -610,19 +610,19 @@ void intel_uc_fw_fetch(struct drm_i915_private
>*dev_priv,
>>  		uc_fw->uc_fw_path, fw);
>>
>>  	/* Check the size of the blob before examining buffer contents */
>> -	if (fw->size < sizeof(struct guc_css_header)) {
>> +	if (fw->size < sizeof(struct uc_css_header)) {
>>  		DRM_NOTE("Firmware header is missing\n");
>>  		goto fail;
>>  	}
>>
>> -	css = (struct guc_css_header *)fw->data;
>> +	css = (struct uc_css_header *)fw->data;
>>
>>  	/* Firmware bits always start from header */
>>  	uc_fw->header_offset = 0;
>>  	uc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
>>  		css->key_size_dw - css->exponent_size_dw) * sizeof(u32);
>>
>> -	if (uc_fw->header_size != sizeof(struct guc_css_header)) {
>> +	if (uc_fw->header_size != sizeof(struct uc_css_header)) {
>>  		DRM_NOTE("CSS header definition mismatch\n");
>>  		goto fail;
>>  	}
>> @@ -646,21 +646,36 @@ void intel_uc_fw_fetch(struct drm_i915_private
>*dev_priv,
>>  		goto fail;
>>  	}
>>
>> -	/* Header and uCode will be loaded to WOPCM. Size of the two. */
>> -	size = uc_fw->header_size + uc_fw->ucode_size;
>> -	if (size > guc_wopcm_size(dev_priv)) {
>> -		DRM_NOTE("Firmware is too large to fit in WOPCM\n");
>> -		goto fail;
>> -	}
>> -
>>  	/*
>>  	 * The GuC firmware image has the version number embedded at a well-
>known
>>  	 * offset within the firmware blob; note that major / minor version are
>>  	 * TWO bytes each (i.e. u16), although all pointers and offsets are defined
>>  	 * in terms of bytes (u8).
>>  	 */
>> -	uc_fw->major_ver_found = css->guc_sw_version >> 16;
>> -	uc_fw->minor_ver_found = css->guc_sw_version & 0xFFFF;
>> +	switch (uc_fw->fw_type) {
>> +	case INTEL_UC_FW_TYPE_GUC:
>> +		/* Header and uCode will be loaded to WOPCM. Size of the two.
>*/
>> +		size = uc_fw->header_size + uc_fw->ucode_size;
>> +
>> +		/* Top 32k of WOPCM is reserved (8K stack + 24k RC6 context).
>*/
>> +		if (size > guc_wopcm_size(dev_priv)) {
>> +			DRM_ERROR("Firmware is too large to fit in
>WOPCM\n");
>> +			goto fail;
>> +		}
>> +		uc_fw->major_ver_found = css->guc.sw_version >> 16;
>> +		uc_fw->minor_ver_found = css->guc.sw_version & 0xFFFF;
>> +		break;
>> +
>> +	case INTEL_UC_FW_TYPE_HUC:
>> +		uc_fw->major_ver_found = css->huc.sw_version >> 16;
>> +		uc_fw->minor_ver_found = css->huc.sw_version & 0xFFFF;
>> +		break;
>> +
>> +	default:
>> +		DRM_ERROR("Unknown firmware type %d\n", uc_fw->fw_type);
>> +		err = -ENOEXEC;
>> +		goto fail;
>> +	}
>>
>>  	if (uc_fw->major_ver_found != uc_fw->major_ver_wanted ||
>>  	    uc_fw->minor_ver_found < uc_fw->minor_ver_wanted) { diff --git
>> a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
>> index 893bcec..ad140e2 100644
>> --- a/drivers/gpu/drm/i915/intel_uc.h
>> +++ b/drivers/gpu/drm/i915/intel_uc.h
>> @@ -98,6 +98,11 @@ enum intel_uc_fw_status {
>>  	INTEL_UC_FIRMWARE_SUCCESS
>>  };
>>
>> +enum {
>> +	INTEL_UC_FW_TYPE_GUC,
>> +	INTEL_UC_FW_TYPE_HUC
>> +};
>> +
>>  /*
>>   * This structure encapsulates all the data needed during the process
>>   * of fetching, caching, and loading the firmware image into the GuC.
>> @@ -114,6 +119,7 @@ struct intel_uc_fw {
>>  	uint16_t major_ver_found;
>>  	uint16_t minor_ver_found;
>>
>> +	uint32_t fw_type;
>
>Any reason why we use uint32_t instead of a named enum type here?

Maintains the uniformity of the struct intel_uc_fw...... every field is either uint32_t or uint16_t.

Anusha
>>  	uint32_t header_size;
>>  	uint32_t header_offset;
>>  	uint32_t rsa_size;
>> --
>> 2.7.4
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>--
>Cheers,
>Arek
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 3/8] drm/i915/huc: Add HuC fw loading support

[Arkadiusz Hiler]

On Thu, Dec 22, 2016 at 03:12:19PM -0800, Anusha Srivatsa wrote:
> The HuC loading process is similar to GuC. The intel_uc_fw_fetch()
> is used for both cases.
> 
> HuC loading needs to be before GuC loading. The WOPCM setting must
> be done early before loading any of them.
> 
> v2: rebased on-top of drm-intel-nightly.
>     removed if(HAS_GUC()) before the guc call. (D.Gordon)
>     update huc_version number of format.
> v3: rebased to drm-intel-nightly, changed the file name format to
>     match the one in the huc package.
>     Changed dev->dev_private to to_i915()
> v4: moved function back to where it was.
>     change wait_for_atomic to wait_for.
> v5: rebased + comment changes.
> v7: rebased.
> v8: rebased.
> v9: rebased. Changed the year in the copyright message to reflect
> the right year.Correct the comments,remove the unwanted WARN message,
> replace drm_gem_object_unreference() with i915_gem_object_put().Make the
> prototypes in intel_huc.h non-extern.
> v10: rebased. Update the file construction done by HuC. It is similar to
> GuC.Adopted the approach used in-
> https://patchwork.freedesktop.org/patch/104355/ <Tvrtko Ursulin>
> v11: Fix warnings remove old declaration
> v12: Change dev to dev_priv in macro definition.
> Corrected comments.
> v13: rebased.
> v14: rebased on top of drm-tip
> v15: rebased. Updated functions intel_huc_load(),intel_huc_init() and
> intel_uc_fw_fetch() to accept dev_priv instead of dev. Moved contents
> of intel_huc.h to intel_uc.h
> v16: change SKL_FW_ to SKL_HUC_FW_. Add intel_ prefix to guc_wopcm_size().
> Remove unwanted checks in intel_uc.h. Rename huc_fw in struct intel_huc to
> simply fw to avoid redundency.
> v17: rebased.
> 
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Tested-by: Xiang Haihao <haihao.xiang@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Alex Dai <yu.dai@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>

-- 
Cheers,
Arek
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 1/8] drm/i915/guc: Make the GuC fw loading helper functions general

[Michal Wajdeczko]

On Thu, Dec 22, 2016 at 03:12:17PM -0800, Anusha Srivatsa wrote:
> From: Peter Antoine <peter.antoine@intel.com>
> 
> Rename some of the GuC fw loading code to make them more general. We
> will utilise them for HuC loading as well.
>      s/intel_guc_fw/intel_uc_fw/g
>      s/GUC_FIRMWARE/UC_FIRMWARE/g
> 
> Struct intel_guc_fw is renamed to intel_uc_fw. Prefix of tts members,
> such as 'guc' or 'guc_fw' either is renamed to 'uc' or removed for
> same purpose.
> 
> v2: rebased on top of nightly.
>     reapplied the search/replace as upstream code as changed.
> v3: rebased again on drm-nightly.
> v4: removed G from messages in shared fw fetch function.
> v5: rebased.
> v7: rebased.
> v8: rebased.
> v9: rebased.
> v10: rebased.
> v11: rebased.
> v12: rebased on top of drm-tip
> v13: rebased.Updated dev to dev_priv in intel_guc_setup(), guc_fw_getch()
> and intel_guc_init().
> v14: rebased. Remove uint32_t fw_type to patch 2. Add INTEL_ prefix for
> fields in enum intel_uc_fw_status. Remove uc_dev field since its never
> used.Rename uc_fw to just fw and guc_fw to fw to avoid redundency.
> v15: rebased. Remove sections of code that were commented and no longer
> required.
> 
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Alex Dai <yu.dai@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c        |  12 +--
>  drivers/gpu/drm/i915/i915_guc_submission.c |   4 +-
>  drivers/gpu/drm/i915/intel_guc_loader.c    | 156 ++++++++++++++---------------
>  drivers/gpu/drm/i915/intel_uc.h            |  36 +++----
>  4 files changed, 104 insertions(+), 104 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index a5552a1..0a3c575 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2328,7 +2328,7 @@ static int i915_llc(struct seq_file *m, void *data)
>  static int i915_guc_load_status_info(struct seq_file *m, void *data)
>  {
>  	struct drm_i915_private *dev_priv = node_to_i915(m->private);
> -	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> +	struct intel_uc_fw *guc_fw = &dev_priv->guc.fw;
>  	u32 tmp, i;
>  
>  	if (!HAS_GUC_UCODE(dev_priv))
> @@ -2336,15 +2336,15 @@ static int i915_guc_load_status_info(struct seq_file *m, void *data)
>  
>  	seq_printf(m, "GuC firmware status:\n");
>  	seq_printf(m, "\tpath: %s\n",
> -		guc_fw->guc_fw_path);
> +		guc_fw->uc_fw_path);
>  	seq_printf(m, "\tfetch: %s\n",
> -		intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
> +		intel_uc_fw_status_repr(guc_fw->fetch_status));
>  	seq_printf(m, "\tload: %s\n",
> -		intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
> +		intel_uc_fw_status_repr(guc_fw->load_status));
>  	seq_printf(m, "\tversion wanted: %d.%d\n",
> -		guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
> +		guc_fw->major_ver_wanted, guc_fw->minor_ver_wanted);
>  	seq_printf(m, "\tversion found: %d.%d\n",
> -		guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
> +		guc_fw->major_ver_found, guc_fw->minor_ver_found);
>  	seq_printf(m, "\theader: offset is %d; size = %d\n",
>  		guc_fw->header_offset, guc_fw->header_size);
>  	seq_printf(m, "\tuCode: offset is %d; size = %d\n",
> diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
> index 3e20fe2..6e2d403 100644
> --- a/drivers/gpu/drm/i915/i915_guc_submission.c
> +++ b/drivers/gpu/drm/i915/i915_guc_submission.c
> @@ -1484,7 +1484,7 @@ int intel_guc_suspend(struct drm_i915_private *dev_priv)
>  	struct i915_gem_context *ctx;
>  	u32 data[3];
>  
> -	if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
> +	if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
>  		return 0;
>  
>  	gen9_disable_guc_interrupts(dev_priv);
> @@ -1511,7 +1511,7 @@ int intel_guc_resume(struct drm_i915_private *dev_priv)
>  	struct i915_gem_context *ctx;
>  	u32 data[3];
>  
> -	if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
> +	if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
>  		return 0;
>  
>  	if (i915.guc_log_level >= 0)
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> index 21db697..ffe53dd7 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -81,16 +81,16 @@ MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
>  MODULE_FIRMWARE(I915_KBL_GUC_UCODE);
>  
>  /* User-friendly representation of an enum */
> -const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status)
> +const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status)
>  {
>  	switch (status) {
> -	case GUC_FIRMWARE_FAIL:
> +	case INTEL_UC_FIRMWARE_FAIL:
>  		return "FAIL";
> -	case GUC_FIRMWARE_NONE:
> +	case INTEL_UC_FIRMWARE_NONE:
>  		return "NONE";
> -	case GUC_FIRMWARE_PENDING:
> +	case INTEL_UC_FIRMWARE_PENDING:
>  		return "PENDING";
> -	case GUC_FIRMWARE_SUCCESS:
> +	case INTEL_UC_FIRMWARE_SUCCESS:
>  		return "SUCCESS";
>  	default:
>  		return "UNKNOWN!";
> @@ -278,7 +278,7 @@ static inline bool guc_ucode_response(struct drm_i915_private *dev_priv,
>  static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv,
>  			      struct i915_vma *vma)
>  {
> -	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> +	struct intel_uc_fw *guc_fw = &dev_priv->guc.fw;
>  	unsigned long offset;
>  	struct sg_table *sg = vma->pages;
>  	u32 status, rsa[UOS_RSA_SCRATCH_MAX_COUNT];
> @@ -350,17 +350,17 @@ static u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
>   */
>  static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
>  {
> -	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> +	struct intel_uc_fw *guc_fw = &dev_priv->guc.fw;
>  	struct i915_vma *vma;
>  	int ret;
>  
> -	ret = i915_gem_object_set_to_gtt_domain(guc_fw->guc_fw_obj, false);
> +	ret = i915_gem_object_set_to_gtt_domain(guc_fw->uc_fw_obj, false);
>  	if (ret) {
>  		DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
>  		return ret;
>  	}
>  
> -	vma = i915_gem_object_ggtt_pin(guc_fw->guc_fw_obj, NULL, 0, 0, 0);
> +	vma = i915_gem_object_ggtt_pin(guc_fw->uc_fw_obj, NULL, 0, 0, 0);
>  	if (IS_ERR(vma)) {
>  		DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
>  		return PTR_ERR(vma);
> @@ -450,14 +450,14 @@ static int guc_hw_reset(struct drm_i915_private *dev_priv)
>   */
>  int intel_guc_setup(struct drm_i915_private *dev_priv)
>  {
> -	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> -	const char *fw_path = guc_fw->guc_fw_path;
> +	struct intel_uc_fw *guc_fw = &dev_priv->guc.fw;
> +	const char *fw_path = guc_fw->uc_fw_path;
>  	int retries, ret, err;
>  
>  	DRM_DEBUG_DRIVER("GuC fw status: path %s, fetch %s, load %s\n",
>  		fw_path,
> -		intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
> -		intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
> +		intel_uc_fw_status_repr(guc_fw->fetch_status),
> +		intel_uc_fw_status_repr(guc_fw->load_status));
>  
>  	/* Loading forbidden, or no firmware to load? */
>  	if (!i915.enable_guc_loading) {
> @@ -475,10 +475,10 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
>  	}
>  
>  	/* Fetch failed, or already fetched but failed to load? */
> -	if (guc_fw->guc_fw_fetch_status != GUC_FIRMWARE_SUCCESS) {
> +	if (guc_fw->fetch_status != INTEL_UC_FIRMWARE_SUCCESS) {
>  		err = -EIO;
>  		goto fail;
> -	} else if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_FAIL) {
> +	} else if (guc_fw->load_status == INTEL_UC_FIRMWARE_FAIL) {
>  		err = -ENOEXEC;
>  		goto fail;
>  	}
> @@ -486,11 +486,11 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
>  	guc_interrupts_release(dev_priv);
>  	gen9_reset_guc_interrupts(dev_priv);
>  
> -	guc_fw->guc_fw_load_status = GUC_FIRMWARE_PENDING;
> +	guc_fw->load_status = INTEL_UC_FIRMWARE_PENDING;
>  
>  	DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
> -		intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
> -		intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
> +		intel_uc_fw_status_repr(guc_fw->fetch_status),
> +		intel_uc_fw_status_repr(guc_fw->load_status));
>  
>  	err = i915_guc_submission_init(dev_priv);
>  	if (err)
> @@ -522,11 +522,11 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
>  			 "retry %d more time(s)\n", err, retries);
>  	}
>  
> -	guc_fw->guc_fw_load_status = GUC_FIRMWARE_SUCCESS;
> +	guc_fw->load_status = INTEL_UC_FIRMWARE_SUCCESS;
>  
>  	DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
> -		intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
> -		intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
> +		intel_uc_fw_status_repr(guc_fw->fetch_status),
> +		intel_uc_fw_status_repr(guc_fw->load_status));
>  
>  	if (i915.enable_guc_submission) {
>  		if (i915.guc_log_level >= 0)
> @@ -541,8 +541,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
>  	return 0;
>  
>  fail:
> -	if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_PENDING)
> -		guc_fw->guc_fw_load_status = GUC_FIRMWARE_FAIL;
> +	if (guc_fw->load_status == INTEL_UC_FIRMWARE_PENDING)
> +		guc_fw->load_status = INTEL_UC_FIRMWARE_FAIL;
>  
>  	guc_interrupts_release(dev_priv);
>  	i915_guc_submission_disable(dev_priv);
> @@ -587,8 +587,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
>  	return ret;
>  }
>  
> -static void guc_fw_fetch(struct drm_i915_private *dev_priv,
> -			 struct intel_guc_fw *guc_fw)
> +void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
> +			 struct intel_uc_fw *uc_fw)
>  {
>  	struct pci_dev *pdev = dev_priv->drm.pdev;
>  	struct drm_i915_gem_object *obj;
> @@ -597,17 +597,17 @@ static void guc_fw_fetch(struct drm_i915_private *dev_priv,
>  	size_t size;
>  	int err;
>  
> -	DRM_DEBUG_DRIVER("before requesting firmware: GuC fw fetch status %s\n",
> -		intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
> +	DRM_DEBUG_DRIVER("before requesting firmware: uC fw fetch status %s\n",
> +		intel_uc_fw_status_repr(uc_fw->fetch_status));
>  
> -	err = request_firmware(&fw, guc_fw->guc_fw_path, &pdev->dev);
> +	err = request_firmware(&fw, uc_fw->uc_fw_path, &pdev->dev);
>  	if (err)
>  		goto fail;
>  	if (!fw)
>  		goto fail;
>  
> -	DRM_DEBUG_DRIVER("fetch GuC fw from %s succeeded, fw %p\n",
> -		guc_fw->guc_fw_path, fw);
> +	DRM_DEBUG_DRIVER("fetch uC fw from %s succeeded, fw %p\n",
> +		uc_fw->uc_fw_path, fw);
>  
>  	/* Check the size of the blob before examining buffer contents */
>  	if (fw->size < sizeof(struct guc_css_header)) {
> @@ -618,36 +618,36 @@ static void guc_fw_fetch(struct drm_i915_private *dev_priv,
>  	css = (struct guc_css_header *)fw->data;
>  
>  	/* Firmware bits always start from header */
> -	guc_fw->header_offset = 0;
> -	guc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
> +	uc_fw->header_offset = 0;
> +	uc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
>  		css->key_size_dw - css->exponent_size_dw) * sizeof(u32);
>  
> -	if (guc_fw->header_size != sizeof(struct guc_css_header)) {
> +	if (uc_fw->header_size != sizeof(struct guc_css_header)) {
>  		DRM_NOTE("CSS header definition mismatch\n");
>  		goto fail;
>  	}
>  
>  	/* then, uCode */
> -	guc_fw->ucode_offset = guc_fw->header_offset + guc_fw->header_size;
> -	guc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
> +	uc_fw->ucode_offset = uc_fw->header_offset + uc_fw->header_size;
> +	uc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
>  
>  	/* now RSA */
>  	if (css->key_size_dw != UOS_RSA_SCRATCH_MAX_COUNT) {
>  		DRM_NOTE("RSA key size is bad\n");
>  		goto fail;
>  	}
> -	guc_fw->rsa_offset = guc_fw->ucode_offset + guc_fw->ucode_size;
> -	guc_fw->rsa_size = css->key_size_dw * sizeof(u32);
> +	uc_fw->rsa_offset = uc_fw->ucode_offset + uc_fw->ucode_size;
> +	uc_fw->rsa_size = css->key_size_dw * sizeof(u32);
>  
>  	/* At least, it should have header, uCode and RSA. Size of all three. */
> -	size = guc_fw->header_size + guc_fw->ucode_size + guc_fw->rsa_size;
> +	size = uc_fw->header_size + uc_fw->ucode_size + uc_fw->rsa_size;
>  	if (fw->size < size) {
>  		DRM_NOTE("Missing firmware components\n");
>  		goto fail;
>  	}
>  
>  	/* Header and uCode will be loaded to WOPCM. Size of the two. */
> -	size = guc_fw->header_size + guc_fw->ucode_size;
> +	size = uc_fw->header_size + uc_fw->ucode_size;
>  	if (size > guc_wopcm_size(dev_priv)) {
>  		DRM_NOTE("Firmware is too large to fit in WOPCM\n");
>  		goto fail;
> @@ -659,21 +659,21 @@ static void guc_fw_fetch(struct drm_i915_private *dev_priv,
>  	 * TWO bytes each (i.e. u16), although all pointers and offsets are defined
>  	 * in terms of bytes (u8).
>  	 */
> -	guc_fw->guc_fw_major_found = css->guc_sw_version >> 16;
> -	guc_fw->guc_fw_minor_found = css->guc_sw_version & 0xFFFF;
> -
> -	if (guc_fw->guc_fw_major_found != guc_fw->guc_fw_major_wanted ||
> -	    guc_fw->guc_fw_minor_found < guc_fw->guc_fw_minor_wanted) {
> -		DRM_NOTE("GuC firmware version %d.%d, required %d.%d\n",
> -			guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
> -			guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
> +	uc_fw->major_ver_found = css->guc_sw_version >> 16;
> +	uc_fw->minor_ver_found = css->guc_sw_version & 0xFFFF;
> +
> +	if (uc_fw->major_ver_found != uc_fw->major_ver_wanted ||
> +	    uc_fw->minor_ver_found < uc_fw->minor_ver_wanted) {
> +		DRM_NOTE("uC firmware version %d.%d, required %d.%d\n",
> +			uc_fw->major_ver_found, uc_fw->minor_ver_found,
> +			uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted);
>  		err = -ENOEXEC;
>  		goto fail;
>  	}
>  
>  	DRM_DEBUG_DRIVER("firmware version %d.%d OK (minimum %d.%d)\n",
> -			guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
> -			guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
> +			uc_fw->major_ver_found, uc_fw->minor_ver_found,
> +			uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted);
>  
>  	mutex_lock(&dev_priv->drm.struct_mutex);
>  	obj = i915_gem_object_create_from_data(dev_priv, fw->data, fw->size);
> @@ -683,31 +683,31 @@ static void guc_fw_fetch(struct drm_i915_private *dev_priv,
>  		goto fail;
>  	}
>  
> -	guc_fw->guc_fw_obj = obj;
> -	guc_fw->guc_fw_size = fw->size;
> +	uc_fw->uc_fw_obj = obj;
> +	uc_fw->size = fw->size;
>  
> -	DRM_DEBUG_DRIVER("GuC fw fetch status SUCCESS, obj %p\n",
> -			guc_fw->guc_fw_obj);
> +	DRM_DEBUG_DRIVER("uC fw fetch status SUCCESS, obj %p\n",
> +			uc_fw->uc_fw_obj);
>  
>  	release_firmware(fw);
> -	guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_SUCCESS;
> +	uc_fw->fetch_status = INTEL_UC_FIRMWARE_SUCCESS;
>  	return;
>  
>  fail:
> -	DRM_WARN("Failed to fetch valid GuC firmware from %s (error %d)\n",
> -		 guc_fw->guc_fw_path, err);
> -	DRM_DEBUG_DRIVER("GuC fw fetch status FAIL; err %d, fw %p, obj %p\n",
> -		err, fw, guc_fw->guc_fw_obj);
> +	DRM_WARN("Failed to fetch valid uC firmware from %s (error %d)\n",
> +		 uc_fw->uc_fw_path, err);
> +	DRM_DEBUG_DRIVER("uC fw fetch status FAIL; err %d, fw %p, obj %p\n",
> +		err, fw, uc_fw->uc_fw_obj);
>  
>  	mutex_lock(&dev_priv->drm.struct_mutex);
> -	obj = guc_fw->guc_fw_obj;
> +	obj = uc_fw->uc_fw_obj;
>  	if (obj)
>  		i915_gem_object_put(obj);
> -	guc_fw->guc_fw_obj = NULL;
> +	uc_fw->uc_fw_obj = NULL;
>  	mutex_unlock(&dev_priv->drm.struct_mutex);
>  
>  	release_firmware(fw);		/* OK even if fw is NULL */
> -	guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL;
> +	uc_fw->fetch_status = INTEL_UC_FIRMWARE_FAIL;
>  }
>  
>  /**
> @@ -721,7 +721,7 @@ static void guc_fw_fetch(struct drm_i915_private *dev_priv,
>   */
>  void intel_guc_init(struct drm_i915_private *dev_priv)
>  {
> -	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> +	struct intel_uc_fw *guc_fw = &dev_priv->guc.fw;
>  	const char *fw_path;
>  
>  	if (!HAS_GUC(dev_priv)) {
> @@ -739,23 +739,23 @@ void intel_guc_init(struct drm_i915_private *dev_priv)
>  		fw_path = NULL;
>  	} else if (IS_SKYLAKE(dev_priv)) {
>  		fw_path = I915_SKL_GUC_UCODE;
> -		guc_fw->guc_fw_major_wanted = SKL_FW_MAJOR;
> -		guc_fw->guc_fw_minor_wanted = SKL_FW_MINOR;
> +		guc_fw->major_ver_wanted = SKL_FW_MAJOR;
> +		guc_fw->minor_ver_wanted = SKL_FW_MINOR;
>  	} else if (IS_BROXTON(dev_priv)) {
>  		fw_path = I915_BXT_GUC_UCODE;
> -		guc_fw->guc_fw_major_wanted = BXT_FW_MAJOR;
> -		guc_fw->guc_fw_minor_wanted = BXT_FW_MINOR;
> +		guc_fw->major_ver_wanted = BXT_FW_MAJOR;
> +		guc_fw->minor_ver_wanted = BXT_FW_MINOR;
>  	} else if (IS_KABYLAKE(dev_priv)) {
>  		fw_path = I915_KBL_GUC_UCODE;
> -		guc_fw->guc_fw_major_wanted = KBL_FW_MAJOR;
> -		guc_fw->guc_fw_minor_wanted = KBL_FW_MINOR;
> +		guc_fw->major_ver_wanted = KBL_FW_MAJOR;
> +		guc_fw->minor_ver_wanted = KBL_FW_MINOR;
>  	} else {
>  		fw_path = "";	/* unknown device */
>  	}
>  
> -	guc_fw->guc_fw_path = fw_path;
> -	guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
> -	guc_fw->guc_fw_load_status = GUC_FIRMWARE_NONE;
> +	guc_fw->uc_fw_path = fw_path;
> +	guc_fw->fetch_status = INTEL_UC_FIRMWARE_NONE;
> +	guc_fw->load_status = INTEL_UC_FIRMWARE_NONE;
>  
>  	/* Early (and silent) return if GuC loading is disabled */
>  	if (!i915.enable_guc_loading)
> @@ -765,9 +765,9 @@ void intel_guc_init(struct drm_i915_private *dev_priv)
>  	if (*fw_path == '\0')
>  		return;
>  
> -	guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_PENDING;
> +	guc_fw->fetch_status = INTEL_UC_FIRMWARE_PENDING;
>  	DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path);
> -	guc_fw_fetch(dev_priv, guc_fw);
> +	intel_uc_fw_fetch(dev_priv, guc_fw);
>  	/* status must now be FAIL or SUCCESS */
>  }
>  
> @@ -777,17 +777,17 @@ void intel_guc_init(struct drm_i915_private *dev_priv)
>   */
>  void intel_guc_fini(struct drm_i915_private *dev_priv)
>  {
> -	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> +	struct intel_uc_fw *guc_fw = &dev_priv->guc.fw;
>  
>  	mutex_lock(&dev_priv->drm.struct_mutex);
>  	guc_interrupts_release(dev_priv);
>  	i915_guc_submission_disable(dev_priv);
>  	i915_guc_submission_fini(dev_priv);
>  
> -	if (guc_fw->guc_fw_obj)
> -		i915_gem_object_put(guc_fw->guc_fw_obj);
> -	guc_fw->guc_fw_obj = NULL;
> +	if (guc_fw->uc_fw_obj)
> +		i915_gem_object_put(guc_fw->uc_fw_obj);
> +	guc_fw->uc_fw_obj = NULL;
>  	mutex_unlock(&dev_priv->drm.struct_mutex);
>  
> -	guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
> +	guc_fw->fetch_status = INTEL_UC_FIRMWARE_NONE;
>  }
> diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
> index 11f5608..893bcec 100644
> --- a/drivers/gpu/drm/i915/intel_uc.h
> +++ b/drivers/gpu/drm/i915/intel_uc.h
> @@ -91,28 +91,28 @@ struct i915_guc_client {
>  	uint64_t submissions[I915_NUM_ENGINES];
>  };
>  
> -enum intel_guc_fw_status {
> -	GUC_FIRMWARE_FAIL = -1,
> -	GUC_FIRMWARE_NONE = 0,
> -	GUC_FIRMWARE_PENDING,
> -	GUC_FIRMWARE_SUCCESS
> +enum intel_uc_fw_status {
> +	INTEL_UC_FIRMWARE_FAIL = -1,
> +	INTEL_UC_FIRMWARE_NONE = 0,
> +	INTEL_UC_FIRMWARE_PENDING,
> +	INTEL_UC_FIRMWARE_SUCCESS
>  };
>  
>  /*
>   * This structure encapsulates all the data needed during the process
>   * of fetching, caching, and loading the firmware image into the GuC.
>   */
> -struct intel_guc_fw {
> -	const char *			guc_fw_path;
> -	size_t				guc_fw_size;
> -	struct drm_i915_gem_object *	guc_fw_obj;
> -	enum intel_guc_fw_status	guc_fw_fetch_status;
> -	enum intel_guc_fw_status	guc_fw_load_status;
> -
> -	uint16_t			guc_fw_major_wanted;
> -	uint16_t			guc_fw_minor_wanted;
> -	uint16_t			guc_fw_major_found;
> -	uint16_t			guc_fw_minor_found;
> +struct intel_uc_fw {
> +	const char *uc_fw_path;

Can we drop "uc_fw_" prefix also from path and obj members?

Michal

> +	size_t size;
> +	struct drm_i915_gem_object *uc_fw_obj;
> +	enum intel_uc_fw_status fetch_status;
> +	enum intel_uc_fw_status load_status;
> +
> +	uint16_t major_ver_wanted;
> +	uint16_t minor_ver_wanted;
> +	uint16_t major_ver_found;
> +	uint16_t minor_ver_found;
>  
>  	uint32_t header_size;
>  	uint32_t header_offset;
> @@ -139,7 +139,7 @@ struct intel_guc_log {
>  };
>  
>  struct intel_guc {
> -	struct intel_guc_fw guc_fw;
> +	struct intel_uc_fw fw;
>  	struct intel_guc_log log;
>  
>  	/* intel_guc_recv interrupt related state */
> @@ -181,7 +181,7 @@ int intel_guc_log_control(struct intel_guc *guc, u32 control_val);
>  extern void intel_guc_init(struct drm_i915_private *dev_priv);
>  extern int intel_guc_setup(struct drm_i915_private *dev_priv);
>  extern void intel_guc_fini(struct drm_i915_private *dev_priv);
> -extern const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status);
> +extern const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status);
>  extern int intel_guc_suspend(struct drm_i915_private *dev_priv);
>  extern int intel_guc_resume(struct drm_i915_private *dev_priv);
>  
> -- 
> 2.7.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 3/8] drm/i915/huc: Add HuC fw loading support

[Michal Wajdeczko]

On Thu, Dec 22, 2016 at 03:12:19PM -0800, Anusha Srivatsa wrote:
> The HuC loading process is similar to GuC. The intel_uc_fw_fetch()
> is used for both cases.
> 
> HuC loading needs to be before GuC loading. The WOPCM setting must
> be done early before loading any of them.
> 
> v2: rebased on-top of drm-intel-nightly.
>     removed if(HAS_GUC()) before the guc call. (D.Gordon)
>     update huc_version number of format.
> v3: rebased to drm-intel-nightly, changed the file name format to
>     match the one in the huc package.
>     Changed dev->dev_private to to_i915()
> v4: moved function back to where it was.
>     change wait_for_atomic to wait_for.
> v5: rebased + comment changes.
> v7: rebased.
> v8: rebased.
> v9: rebased. Changed the year in the copyright message to reflect
> the right year.Correct the comments,remove the unwanted WARN message,
> replace drm_gem_object_unreference() with i915_gem_object_put().Make the
> prototypes in intel_huc.h non-extern.
> v10: rebased. Update the file construction done by HuC. It is similar to
> GuC.Adopted the approach used in-
> https://patchwork.freedesktop.org/patch/104355/ <Tvrtko Ursulin>
> v11: Fix warnings remove old declaration
> v12: Change dev to dev_priv in macro definition.
> Corrected comments.
> v13: rebased.
> v14: rebased on top of drm-tip
> v15: rebased. Updated functions intel_huc_load(),intel_huc_init() and
> intel_uc_fw_fetch() to accept dev_priv instead of dev. Moved contents
> of intel_huc.h to intel_uc.h
> v16: change SKL_FW_ to SKL_HUC_FW_. Add intel_ prefix to guc_wopcm_size().
> Remove unwanted checks in intel_uc.h. Rename huc_fw in struct intel_huc to
> simply fw to avoid redundency.
> v17: rebased.
> 
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Tested-by: Xiang Haihao <haihao.xiang@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Alex Dai <yu.dai@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> ---
>  drivers/gpu/drm/i915/Makefile           |   1 +
>  drivers/gpu/drm/i915/i915_drv.c         |   4 +-
>  drivers/gpu/drm/i915/i915_drv.h         |   3 +-
>  drivers/gpu/drm/i915/i915_guc_reg.h     |   3 +
>  drivers/gpu/drm/i915/intel_guc_loader.c |  11 +-
>  drivers/gpu/drm/i915/intel_huc_loader.c | 263 ++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_uc.h         |  18 +++
>  7 files changed, 296 insertions(+), 7 deletions(-)
>  create mode 100644 drivers/gpu/drm/i915/intel_huc_loader.c
> 
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 5196509..45ae124 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -57,6 +57,7 @@ i915-y += i915_cmd_parser.o \
>  # general-purpose microcontroller (GuC) support
>  i915-y += intel_uc.o \
>  	  intel_guc_loader.o \
> +	  intel_huc_loader.o \
>  	  i915_guc_submission.o
>  
>  # autogenerated null render state
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 6428588..85a47c2 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -600,6 +600,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
>  	if (ret)
>  		goto cleanup_irq;
>  
> +	intel_huc_init(dev_priv);
>  	intel_guc_init(dev_priv);
>  
>  	ret = i915_gem_init(dev_priv);
> @@ -627,6 +628,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
>  		DRM_ERROR("failed to idle hardware; continuing to unload!\n");
>  	i915_gem_fini(dev_priv);
>  cleanup_irq:
> +	intel_huc_fini(dev);
>  	intel_guc_fini(dev_priv);
>  	drm_irq_uninstall(dev);
>  	intel_teardown_gmbus(dev_priv);
> @@ -1313,7 +1315,7 @@ void i915_driver_unload(struct drm_device *dev)
>  
>  	/* Flush any outstanding unpin_work. */
>  	drain_workqueue(dev_priv->wq);
> -
> +	intel_huc_fini(dev);
>  	intel_guc_fini(dev_priv);
>  	i915_gem_fini(dev_priv);
>  	intel_fbc_cleanup_cfb(dev_priv);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 1a91409..7ac7730 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2147,6 +2147,7 @@ struct drm_i915_private {
>  
>  	struct intel_gvt *gvt;
>  
> +	struct intel_huc huc;
>  	struct intel_guc guc;
>  
>  	struct intel_csr csr;
> @@ -2921,7 +2922,7 @@ intel_info(const struct drm_i915_private *dev_priv)
>  #define HAS_GUC(dev_priv)	((dev_priv)->info.has_guc)
>  #define HAS_GUC_UCODE(dev_priv)	(HAS_GUC(dev_priv))
>  #define HAS_GUC_SCHED(dev_priv)	(HAS_GUC(dev_priv))
> -
> +#define HAS_HUC_UCODE(dev_priv)	(HAS_GUC(dev_priv))
>  #define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
>  
>  #define HAS_POOLED_EU(dev_priv)	((dev_priv)->info.has_pooled_eu)
> diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h b/drivers/gpu/drm/i915/i915_guc_reg.h
> index 5e638fc..f9829f6 100644
> --- a/drivers/gpu/drm/i915/i915_guc_reg.h
> +++ b/drivers/gpu/drm/i915/i915_guc_reg.h
> @@ -61,9 +61,12 @@
>  #define   DMA_ADDRESS_SPACE_GTT		  (8 << 16)
>  #define DMA_COPY_SIZE			_MMIO(0xc310)
>  #define DMA_CTRL			_MMIO(0xc314)
> +#define   HUC_UKERNEL			  (1<<9)
>  #define   UOS_MOVE			  (1<<4)
>  #define   START_DMA			  (1<<0)
>  #define DMA_GUC_WOPCM_OFFSET		_MMIO(0xc340)
> +#define   HUC_LOADING_AGENT_VCR		  (0<<1)
> +#define   HUC_LOADING_AGENT_GUC		  (1<<1)
>  #define   GUC_WOPCM_OFFSET_VALUE	  0x80000	/* 512KB */
>  #define GUC_MAX_IDLE_COUNT		_MMIO(0xC3E4)
>  
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> index 06e3e5c..8c77e94 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -309,8 +309,8 @@ static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv,
>  	I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
>  
>  	/* Finally start the DMA */
> -	I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));
> -
> +	I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA) |
> +		_MASKED_BIT_DISABLE(HUC_UKERNEL));
>  	/*
>  	 * Wait for the DMA to complete & the GuC to start up.
>  	 * NB: Docs recommend not using the interrupt for completion.
> @@ -334,7 +334,7 @@ static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv,
>  	return ret;
>  }
>  
> -static u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
> +u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv)
>  {
>  	u32 wopcm_size = GUC_WOPCM_TOP;
>  
> @@ -372,7 +372,7 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
>  	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
>  
>  	/* init WOPCM */
> -	I915_WRITE(GUC_WOPCM_SIZE, guc_wopcm_size(dev_priv));
> +	I915_WRITE(GUC_WOPCM_SIZE, intel_guc_wopcm_size(dev_priv));
>  	I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE);
>  
>  	/* Enable MIA caching. GuC clock gating is disabled. */
> @@ -511,6 +511,7 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
>  		if (err)
>  			goto fail;
>  
> +		intel_huc_load(dev_priv);
>  		err = guc_ucode_xfer(dev_priv);
>  		if (!err)
>  			break;
> @@ -658,7 +659,7 @@ void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
>  		size = uc_fw->header_size + uc_fw->ucode_size;
>  
>  		/* Top 32k of WOPCM is reserved (8K stack + 24k RC6 context). */
> -		if (size > guc_wopcm_size(dev_priv)) {
> +		if (size > intel_guc_wopcm_size(dev_priv)) {
>  			DRM_ERROR("Firmware is too large to fit in WOPCM\n");
>  			goto fail;
>  		}
> diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c
> new file mode 100644
> index 0000000..98d631c
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_huc_loader.c
> @@ -0,0 +1,263 @@
> +/*
> + * Copyright © 2016 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + *
> + */
> +#include <linux/firmware.h>
> +#include "i915_drv.h"
> +#include "intel_uc.h"
> +
> +/**
> + * DOC: HuC Firmware
> + *
> + * Motivation:
> + * GEN9 introduces a new dedicated firmware for usage in media HEVC (High
> + * Efficiency Video Coding) operations. Userspace can use the firmware
> + * capabilities by adding HuC specific commands to batch buffers.
> + *
> + * Implementation:
> + * The same firmware loader is used as the GuC. However, the actual
> + * loading to HW is deferred until GEM initialization is done.
> + *
> + * Note that HuC firmware loading must be done before GuC loading.
> + */
> +
> +#define SKL_HUC_FW_MAJOR 01
> +#define SKL_HUC_FW_MINOR 07
> +#define SKL_BLD_NUM 1398
> +
> +#define HUC_FW_PATH(platform, major, minor, bld_num) \
> +	"i915/" __stringify(platform) "_huc_ver" __stringify(major) "_" \
> +	__stringify(minor) "_" __stringify(bld_num) ".bin"
> +
> +#define I915_SKL_HUC_UCODE HUC_FW_PATH(skl, SKL_HUC_FW_MAJOR, \
> +	SKL_HUC_FW_MINOR, SKL_BLD_NUM)
> +MODULE_FIRMWARE(I915_SKL_HUC_UCODE);
> +
> +/**
> + * huc_ucode_xfer() - DMA's the firmware
> + * @dev_priv: the drm device
> + *
> + * This function takes the gem object containing the firmware, sets up the DMA

Hmm, this function takes just dev_priv...


> + * engine MMIO, triggers the DMA operation and waits for it to finish.
> + *
> + * Transfer the firmware image to RAM for execution by the microcontroller.
> + *
> + * Return: 0 on success, non-zero on failure
> + */
> +static int huc_ucode_xfer(struct drm_i915_private *dev_priv)
> +{
> +	struct intel_uc_fw *huc_fw = &dev_priv->huc.fw;
> +	struct i915_vma *vma;
> +	unsigned long offset = 0;
> +	u32 size;
> +	int ret;
> +
> +	ret = i915_gem_object_set_to_gtt_domain(huc_fw->uc_fw_obj, false);
> +	if (ret) {
> +		DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
> +		return ret;
> +	}
> +
> +	vma = i915_gem_object_ggtt_pin(huc_fw->uc_fw_obj, NULL, 0, 0, 0);
> +	if (IS_ERR(vma)) {
> +		DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
> +		return PTR_ERR(vma);
> +	}
> +
> +	/* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
> +	I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
> +
> +	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> +
> +	/* init WOPCM */
> +	I915_WRITE(GUC_WOPCM_SIZE, intel_guc_wopcm_size(dev_priv));
> +	I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE |
> +			HUC_LOADING_AGENT_GUC);
> +
> +	/* Set the source address for the uCode */
> +	offset = i915_ggtt_offset(vma) + huc_fw->header_offset;
> +	I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
> +	I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
> +
> +	/* Hardware doesn't look at destination address for HuC. Set it to 0,
> +	 * but still program the correct address space.
> +	 */
> +	I915_WRITE(DMA_ADDR_1_LOW, 0);
> +	I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
> +
> +	size = huc_fw->header_size + huc_fw->ucode_size;
> +	I915_WRITE(DMA_COPY_SIZE, size);
> +
> +	/* Start the DMA */
> +	I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(HUC_UKERNEL | START_DMA));
> +
> +	/* Wait for DMA to finish */
> +	ret = wait_for((I915_READ(DMA_CTRL) & START_DMA) == 0, 100);
> +
> +	DRM_DEBUG_DRIVER("HuC DMA transfer wait over with ret %d\n", ret);
> +
> +	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> +
> +	/*
> +	 * We keep the object pages for reuse during resume. But we can unpin it
> +	 * now that DMA has completed, so it doesn't continue to take up space.
> +	 */
> +	i915_vma_unpin(vma);
> +
> +	return ret;
> +}
> +
> +/**
> + * intel_huc_init() - initiate HuC firmware loading request
> + * @dev_priv: the drm_i915_private device
> + *
> + * Called early during driver load, but after GEM is initialised. The loading
> + * will continue only when driver explicitly specify firmware name and version.
> + * All other cases are considered as INTEL_UC_FIRMWARE_NONE either because HW
> + * is not capable or driver yet support it. And there will be no error message
> + * for INTEL_UC_FIRMWARE_NONE cases.
> + *
> + * The DMA-copying to HW is done later when intel_huc_load() is called.
> + */
> +void intel_huc_init(struct drm_i915_private *dev_priv)
> +{
> +	struct intel_huc *huc = &dev_priv->huc;
> +	struct intel_uc_fw *huc_fw = &huc->fw;
> +	const char *fw_path = NULL;
> +
> +	huc_fw->uc_fw_path = NULL;
> +	huc_fw->fetch_status = INTEL_UC_FIRMWARE_NONE;
> +	huc_fw->load_status = INTEL_UC_FIRMWARE_NONE;
> +	huc_fw->fw_type = INTEL_UC_FW_TYPE_HUC;
> +
> +	if (!HAS_HUC_UCODE(dev_priv))
> +		return;
> +
> +	if (IS_SKYLAKE(dev_priv)) {
> +		fw_path = I915_SKL_HUC_UCODE;
> +		huc_fw->major_ver_wanted = SKL_HUC_FW_MAJOR;
> +		huc_fw->minor_ver_wanted = SKL_HUC_FW_MINOR;
> +	}
> +
> +	huc_fw->uc_fw_path = fw_path;
> +	huc_fw->fetch_status = INTEL_UC_FIRMWARE_PENDING;
> +
> +	DRM_DEBUG_DRIVER("HuC firmware pending, path %s\n", fw_path);
> +
> +	intel_uc_fw_fetch(dev_priv, huc_fw);
> +}
> +
> +/**
> + * intel_huc_load() - load HuC uCode to device
> + * @dev_priv: the drm_i915_private device
> + *
> + * Called from gem_init_hw() during driver loading and also after a GPU reset.
> + * Be note that HuC loading must be done before GuC loading.
> + *
> + * The firmware image should have already been fetched into memory by the
> + * earlier call to intel_huc_init(), so here we need only check that
> + * is succeeded, and then transfer the image to the h/w.
> + *
> + * Return:	non-zero code on error
> + */
> +int intel_huc_load(struct drm_i915_private *dev_priv)
> +{
> +	struct intel_uc_fw *huc_fw = &dev_priv->huc.fw;
> +	int err;
> +
> +	if (huc_fw->fetch_status == INTEL_UC_FIRMWARE_NONE)
> +		return 0;
> +
> +	DRM_DEBUG_DRIVER("%s fw status: fetch %s, load %s\n",
> +		huc_fw->uc_fw_path,
> +		intel_uc_fw_status_repr(huc_fw->fetch_status),
> +		intel_uc_fw_status_repr(huc_fw->load_status));
> +
> +	if (huc_fw->fetch_status == INTEL_UC_FIRMWARE_SUCCESS &&
> +	    huc_fw->load_status == INTEL_UC_FIRMWARE_FAIL)
> +		return -ENOEXEC;
> +
> +	huc_fw->load_status = INTEL_UC_FIRMWARE_PENDING;
> +
> +	switch (huc_fw->fetch_status) {
> +	case INTEL_UC_FIRMWARE_FAIL:
> +		/* something went wrong :( */
> +		err = -EIO;
> +		goto fail;
> +
> +	case INTEL_UC_FIRMWARE_NONE:
> +	case INTEL_UC_FIRMWARE_PENDING:
> +	default:
> +		/* "can't happen" */
> +		WARN_ONCE(1, "HuC fw %s invalid fetch_status %s [%d]\n",
> +			huc_fw->uc_fw_path,
> +			intel_uc_fw_status_repr(huc_fw->fetch_status),
> +			huc_fw->fetch_status);
> +		err = -ENXIO;
> +		goto fail;
> +
> +	case INTEL_UC_FIRMWARE_SUCCESS:
> +		break;
> +	}
> +
> +	err = huc_ucode_xfer(dev_priv);
> +	if (err)
> +		goto fail;
> +
> +	huc_fw->load_status = INTEL_UC_FIRMWARE_SUCCESS;
> +
> +	DRM_DEBUG_DRIVER("%s fw status: fetch %s, load %s\n",
> +		huc_fw->uc_fw_path,
> +		intel_uc_fw_status_repr(huc_fw->fetch_status),
> +		intel_uc_fw_status_repr(huc_fw->load_status));

Hmm, this message will always display "fetch SUCCESS load SUCCESS"
as all other cases all handled as fail below... is it expected ? 

> +
> +	return 0;
> +
> +fail:
> +	if (huc_fw->load_status == INTEL_UC_FIRMWARE_PENDING)
> +		huc_fw->load_status = INTEL_UC_FIRMWARE_FAIL;
> +
> +	DRM_ERROR("Failed to complete HuC uCode load with ret %d\n", err);
> +
> +	return err;
> +}
> +
> +/**
> + * intel_huc_fini() - clean up resources allocated for HuC
> + * @dev: the drm device
> + *
> + * Cleans up by releasing the huc firmware GEM obj.
> + */
> +void intel_huc_fini(struct drm_device *dev)

Why this function takes dev? All other functions take dev_priv.

Michal

> +{
> +	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct intel_uc_fw *huc_fw = &dev_priv->huc.fw;
> +
> +	mutex_lock(&dev->struct_mutex);
> +	if (huc_fw->uc_fw_obj)
> +		i915_gem_object_put(huc_fw->uc_fw_obj);
> +	huc_fw->uc_fw_obj = NULL;
> +	mutex_unlock(&dev->struct_mutex);
> +
> +	huc_fw->fetch_status = INTEL_UC_FIRMWARE_NONE;
> +}
> +
> diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
> index ad140e2..57aef56 100644
> --- a/drivers/gpu/drm/i915/intel_uc.h
> +++ b/drivers/gpu/drm/i915/intel_uc.h
> @@ -24,6 +24,9 @@
>  #ifndef _INTEL_UC_H_
>  #define _INTEL_UC_H_
>  
> +#define HUC_STATUS2             _MMIO(0xD3B0)
> +#define   HUC_FW_VERIFIED       (1<<7)
> +
>  #include "intel_guc_fwif.h"
>  #include "i915_guc_reg.h"
>  #include "intel_ringbuffer.h"
> @@ -174,6 +177,13 @@ struct intel_guc {
>  	struct mutex send_mutex;
>  };
>  
> +struct intel_huc {
> +	/* Generic uC firmware management */
> +	struct intel_uc_fw fw;
> +
> +	/* HuC-specific additions */
> +};
> +
>  /* intel_uc.c */
>  void intel_uc_init_early(struct drm_i915_private *dev_priv);
>  bool intel_guc_recv(struct drm_i915_private *dev_priv, u32 *status);
> @@ -190,6 +200,9 @@ extern void intel_guc_fini(struct drm_i915_private *dev_priv);
>  extern const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status);
>  extern int intel_guc_suspend(struct drm_i915_private *dev_priv);
>  extern int intel_guc_resume(struct drm_i915_private *dev_priv);
> +void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
> +	struct intel_uc_fw *uc_fw);
> +u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv);
>  
>  /* i915_guc_submission.c */
>  int i915_guc_submission_init(struct drm_i915_private *dev_priv);
> @@ -204,4 +217,9 @@ void i915_guc_register(struct drm_i915_private *dev_priv);
>  void i915_guc_unregister(struct drm_i915_private *dev_priv);
>  int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val);
>  
> +/* intel_huc_loader.c */
> +void intel_huc_init(struct drm_i915_private *dev_priv);
> +void intel_huc_fini(struct drm_device *dev);
> +int intel_huc_load(struct drm_i915_private *dev_priv);
> +
>  #endif
> -- 
> 2.7.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 1/8] drm/i915/guc: Make the GuC fw loading helper functions general

[Srivatsa, Anusha]

>-----Original Message-----
>From: Wajdeczko, Michal
>Sent: Tuesday, December 27, 2016 9:28 AM
>To: Srivatsa, Anusha <anusha.srivatsa@intel.com>
>Cc: intel-gfx@lists.freedesktop.org; Alex Dai <yu.dai@intel.com>; Peter Antoine
><peter.antoine@intel.com>
>Subject: Re: [Intel-gfx] [PATCH 1/8] drm/i915/guc: Make the GuC fw loading
>helper functions general
>
>On Thu, Dec 22, 2016 at 03:12:17PM -0800, Anusha Srivatsa wrote:
>> From: Peter Antoine <peter.antoine@intel.com>
>>
>> Rename some of the GuC fw loading code to make them more general. We
>> will utilise them for HuC loading as well.
>>      s/intel_guc_fw/intel_uc_fw/g
>>      s/GUC_FIRMWARE/UC_FIRMWARE/g
>>
>> Struct intel_guc_fw is renamed to intel_uc_fw. Prefix of tts members,
>> such as 'guc' or 'guc_fw' either is renamed to 'uc' or removed for
>> same purpose.
>>
>> v2: rebased on top of nightly.
>>     reapplied the search/replace as upstream code as changed.
>> v3: rebased again on drm-nightly.
>> v4: removed G from messages in shared fw fetch function.
>> v5: rebased.
>> v7: rebased.
>> v8: rebased.
>> v9: rebased.
>> v10: rebased.
>> v11: rebased.
>> v12: rebased on top of drm-tip
>> v13: rebased.Updated dev to dev_priv in intel_guc_setup(),
>> guc_fw_getch() and intel_guc_init().
>> v14: rebased. Remove uint32_t fw_type to patch 2. Add INTEL_ prefix
>> for fields in enum intel_uc_fw_status. Remove uc_dev field since its
>> never used.Rename uc_fw to just fw and guc_fw to fw to avoid redundency.
>> v15: rebased. Remove sections of code that were commented and no
>> longer required.
>>
>> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>> Signed-off-by: Alex Dai <yu.dai@intel.com>
>> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_debugfs.c        |  12 +--
>>  drivers/gpu/drm/i915/i915_guc_submission.c |   4 +-
>>  drivers/gpu/drm/i915/intel_guc_loader.c    | 156 ++++++++++++++---------------
>>  drivers/gpu/drm/i915/intel_uc.h            |  36 +++----
>>  4 files changed, 104 insertions(+), 104 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
>> b/drivers/gpu/drm/i915/i915_debugfs.c
>> index a5552a1..0a3c575 100644
>> --- a/drivers/gpu/drm/i915/i915_debugfs.c
>> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
>> @@ -2328,7 +2328,7 @@ static int i915_llc(struct seq_file *m, void
>> *data)  static int i915_guc_load_status_info(struct seq_file *m, void
>> *data)  {
>>  	struct drm_i915_private *dev_priv = node_to_i915(m->private);
>> -	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
>> +	struct intel_uc_fw *guc_fw = &dev_priv->guc.fw;
>>  	u32 tmp, i;
>>
>>  	if (!HAS_GUC_UCODE(dev_priv))
>> @@ -2336,15 +2336,15 @@ static int i915_guc_load_status_info(struct
>> seq_file *m, void *data)
>>
>>  	seq_printf(m, "GuC firmware status:\n");
>>  	seq_printf(m, "\tpath: %s\n",
>> -		guc_fw->guc_fw_path);
>> +		guc_fw->uc_fw_path);
>>  	seq_printf(m, "\tfetch: %s\n",
>> -		intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
>> +		intel_uc_fw_status_repr(guc_fw->fetch_status));
>>  	seq_printf(m, "\tload: %s\n",
>> -		intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
>> +		intel_uc_fw_status_repr(guc_fw->load_status));
>>  	seq_printf(m, "\tversion wanted: %d.%d\n",
>> -		guc_fw->guc_fw_major_wanted, guc_fw-
>>guc_fw_minor_wanted);
>> +		guc_fw->major_ver_wanted, guc_fw->minor_ver_wanted);
>>  	seq_printf(m, "\tversion found: %d.%d\n",
>> -		guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
>> +		guc_fw->major_ver_found, guc_fw->minor_ver_found);
>>  	seq_printf(m, "\theader: offset is %d; size = %d\n",
>>  		guc_fw->header_offset, guc_fw->header_size);
>>  	seq_printf(m, "\tuCode: offset is %d; size = %d\n", diff --git
>> a/drivers/gpu/drm/i915/i915_guc_submission.c
>> b/drivers/gpu/drm/i915/i915_guc_submission.c
>> index 3e20fe2..6e2d403 100644
>> --- a/drivers/gpu/drm/i915/i915_guc_submission.c
>> +++ b/drivers/gpu/drm/i915/i915_guc_submission.c
>> @@ -1484,7 +1484,7 @@ int intel_guc_suspend(struct drm_i915_private
>*dev_priv)
>>  	struct i915_gem_context *ctx;
>>  	u32 data[3];
>>
>> -	if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
>> +	if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
>>  		return 0;
>>
>>  	gen9_disable_guc_interrupts(dev_priv);
>> @@ -1511,7 +1511,7 @@ int intel_guc_resume(struct drm_i915_private
>*dev_priv)
>>  	struct i915_gem_context *ctx;
>>  	u32 data[3];
>>
>> -	if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
>> +	if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
>>  		return 0;
>>
>>  	if (i915.guc_log_level >= 0)
>> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
>> b/drivers/gpu/drm/i915/intel_guc_loader.c
>> index 21db697..ffe53dd7 100644
>> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
>> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
>> @@ -81,16 +81,16 @@ MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
>>  MODULE_FIRMWARE(I915_KBL_GUC_UCODE);
>>
>>  /* User-friendly representation of an enum */ -const char
>> *intel_guc_fw_status_repr(enum intel_guc_fw_status status)
>> +const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status)
>>  {
>>  	switch (status) {
>> -	case GUC_FIRMWARE_FAIL:
>> +	case INTEL_UC_FIRMWARE_FAIL:
>>  		return "FAIL";
>> -	case GUC_FIRMWARE_NONE:
>> +	case INTEL_UC_FIRMWARE_NONE:
>>  		return "NONE";
>> -	case GUC_FIRMWARE_PENDING:
>> +	case INTEL_UC_FIRMWARE_PENDING:
>>  		return "PENDING";
>> -	case GUC_FIRMWARE_SUCCESS:
>> +	case INTEL_UC_FIRMWARE_SUCCESS:
>>  		return "SUCCESS";
>>  	default:
>>  		return "UNKNOWN!";
>> @@ -278,7 +278,7 @@ static inline bool guc_ucode_response(struct
>> drm_i915_private *dev_priv,  static int guc_ucode_xfer_dma(struct
>drm_i915_private *dev_priv,
>>  			      struct i915_vma *vma)
>>  {
>> -	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
>> +	struct intel_uc_fw *guc_fw = &dev_priv->guc.fw;
>>  	unsigned long offset;
>>  	struct sg_table *sg = vma->pages;
>>  	u32 status, rsa[UOS_RSA_SCRATCH_MAX_COUNT]; @@ -350,17 +350,17
>@@
>> static u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
>>   */
>>  static int guc_ucode_xfer(struct drm_i915_private *dev_priv)  {
>> -	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
>> +	struct intel_uc_fw *guc_fw = &dev_priv->guc.fw;
>>  	struct i915_vma *vma;
>>  	int ret;
>>
>> -	ret = i915_gem_object_set_to_gtt_domain(guc_fw->guc_fw_obj, false);
>> +	ret = i915_gem_object_set_to_gtt_domain(guc_fw->uc_fw_obj, false);
>>  	if (ret) {
>>  		DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
>>  		return ret;
>>  	}
>>
>> -	vma = i915_gem_object_ggtt_pin(guc_fw->guc_fw_obj, NULL, 0, 0, 0);
>> +	vma = i915_gem_object_ggtt_pin(guc_fw->uc_fw_obj, NULL, 0, 0, 0);
>>  	if (IS_ERR(vma)) {
>>  		DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
>>  		return PTR_ERR(vma);
>> @@ -450,14 +450,14 @@ static int guc_hw_reset(struct drm_i915_private
>*dev_priv)
>>   */
>>  int intel_guc_setup(struct drm_i915_private *dev_priv)  {
>> -	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
>> -	const char *fw_path = guc_fw->guc_fw_path;
>> +	struct intel_uc_fw *guc_fw = &dev_priv->guc.fw;
>> +	const char *fw_path = guc_fw->uc_fw_path;
>>  	int retries, ret, err;
>>
>>  	DRM_DEBUG_DRIVER("GuC fw status: path %s, fetch %s, load %s\n",
>>  		fw_path,
>> -		intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
>> -		intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
>> +		intel_uc_fw_status_repr(guc_fw->fetch_status),
>> +		intel_uc_fw_status_repr(guc_fw->load_status));
>>
>>  	/* Loading forbidden, or no firmware to load? */
>>  	if (!i915.enable_guc_loading) {
>> @@ -475,10 +475,10 @@ int intel_guc_setup(struct drm_i915_private
>*dev_priv)
>>  	}
>>
>>  	/* Fetch failed, or already fetched but failed to load? */
>> -	if (guc_fw->guc_fw_fetch_status != GUC_FIRMWARE_SUCCESS) {
>> +	if (guc_fw->fetch_status != INTEL_UC_FIRMWARE_SUCCESS) {
>>  		err = -EIO;
>>  		goto fail;
>> -	} else if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_FAIL) {
>> +	} else if (guc_fw->load_status == INTEL_UC_FIRMWARE_FAIL) {
>>  		err = -ENOEXEC;
>>  		goto fail;
>>  	}
>> @@ -486,11 +486,11 @@ int intel_guc_setup(struct drm_i915_private
>*dev_priv)
>>  	guc_interrupts_release(dev_priv);
>>  	gen9_reset_guc_interrupts(dev_priv);
>>
>> -	guc_fw->guc_fw_load_status = GUC_FIRMWARE_PENDING;
>> +	guc_fw->load_status = INTEL_UC_FIRMWARE_PENDING;
>>
>>  	DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
>> -		intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
>> -		intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
>> +		intel_uc_fw_status_repr(guc_fw->fetch_status),
>> +		intel_uc_fw_status_repr(guc_fw->load_status));
>>
>>  	err = i915_guc_submission_init(dev_priv);
>>  	if (err)
>> @@ -522,11 +522,11 @@ int intel_guc_setup(struct drm_i915_private
>*dev_priv)
>>  			 "retry %d more time(s)\n", err, retries);
>>  	}
>>
>> -	guc_fw->guc_fw_load_status = GUC_FIRMWARE_SUCCESS;
>> +	guc_fw->load_status = INTEL_UC_FIRMWARE_SUCCESS;
>>
>>  	DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
>> -		intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
>> -		intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
>> +		intel_uc_fw_status_repr(guc_fw->fetch_status),
>> +		intel_uc_fw_status_repr(guc_fw->load_status));
>>
>>  	if (i915.enable_guc_submission) {
>>  		if (i915.guc_log_level >= 0)
>> @@ -541,8 +541,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
>>  	return 0;
>>
>>  fail:
>> -	if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_PENDING)
>> -		guc_fw->guc_fw_load_status = GUC_FIRMWARE_FAIL;
>> +	if (guc_fw->load_status == INTEL_UC_FIRMWARE_PENDING)
>> +		guc_fw->load_status = INTEL_UC_FIRMWARE_FAIL;
>>
>>  	guc_interrupts_release(dev_priv);
>>  	i915_guc_submission_disable(dev_priv);
>> @@ -587,8 +587,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
>>  	return ret;
>>  }
>>
>> -static void guc_fw_fetch(struct drm_i915_private *dev_priv,
>> -			 struct intel_guc_fw *guc_fw)
>> +void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
>> +			 struct intel_uc_fw *uc_fw)
>>  {
>>  	struct pci_dev *pdev = dev_priv->drm.pdev;
>>  	struct drm_i915_gem_object *obj;
>> @@ -597,17 +597,17 @@ static void guc_fw_fetch(struct drm_i915_private
>*dev_priv,
>>  	size_t size;
>>  	int err;
>>
>> -	DRM_DEBUG_DRIVER("before requesting firmware: GuC fw fetch status
>%s\n",
>> -		intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
>> +	DRM_DEBUG_DRIVER("before requesting firmware: uC fw fetch status
>%s\n",
>> +		intel_uc_fw_status_repr(uc_fw->fetch_status));
>>
>> -	err = request_firmware(&fw, guc_fw->guc_fw_path, &pdev->dev);
>> +	err = request_firmware(&fw, uc_fw->uc_fw_path, &pdev->dev);
>>  	if (err)
>>  		goto fail;
>>  	if (!fw)
>>  		goto fail;
>>
>> -	DRM_DEBUG_DRIVER("fetch GuC fw from %s succeeded, fw %p\n",
>> -		guc_fw->guc_fw_path, fw);
>> +	DRM_DEBUG_DRIVER("fetch uC fw from %s succeeded, fw %p\n",
>> +		uc_fw->uc_fw_path, fw);
>>
>>  	/* Check the size of the blob before examining buffer contents */
>>  	if (fw->size < sizeof(struct guc_css_header)) { @@ -618,36 +618,36
>> @@ static void guc_fw_fetch(struct drm_i915_private *dev_priv,
>>  	css = (struct guc_css_header *)fw->data;
>>
>>  	/* Firmware bits always start from header */
>> -	guc_fw->header_offset = 0;
>> -	guc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
>> +	uc_fw->header_offset = 0;
>> +	uc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
>>  		css->key_size_dw - css->exponent_size_dw) * sizeof(u32);
>>
>> -	if (guc_fw->header_size != sizeof(struct guc_css_header)) {
>> +	if (uc_fw->header_size != sizeof(struct guc_css_header)) {
>>  		DRM_NOTE("CSS header definition mismatch\n");
>>  		goto fail;
>>  	}
>>
>>  	/* then, uCode */
>> -	guc_fw->ucode_offset = guc_fw->header_offset + guc_fw->header_size;
>> -	guc_fw->ucode_size = (css->size_dw - css->header_size_dw) *
>sizeof(u32);
>> +	uc_fw->ucode_offset = uc_fw->header_offset + uc_fw->header_size;
>> +	uc_fw->ucode_size = (css->size_dw - css->header_size_dw) *
>> +sizeof(u32);
>>
>>  	/* now RSA */
>>  	if (css->key_size_dw != UOS_RSA_SCRATCH_MAX_COUNT) {
>>  		DRM_NOTE("RSA key size is bad\n");
>>  		goto fail;
>>  	}
>> -	guc_fw->rsa_offset = guc_fw->ucode_offset + guc_fw->ucode_size;
>> -	guc_fw->rsa_size = css->key_size_dw * sizeof(u32);
>> +	uc_fw->rsa_offset = uc_fw->ucode_offset + uc_fw->ucode_size;
>> +	uc_fw->rsa_size = css->key_size_dw * sizeof(u32);
>>
>>  	/* At least, it should have header, uCode and RSA. Size of all three. */
>> -	size = guc_fw->header_size + guc_fw->ucode_size + guc_fw->rsa_size;
>> +	size = uc_fw->header_size + uc_fw->ucode_size + uc_fw->rsa_size;
>>  	if (fw->size < size) {
>>  		DRM_NOTE("Missing firmware components\n");
>>  		goto fail;
>>  	}
>>
>>  	/* Header and uCode will be loaded to WOPCM. Size of the two. */
>> -	size = guc_fw->header_size + guc_fw->ucode_size;
>> +	size = uc_fw->header_size + uc_fw->ucode_size;
>>  	if (size > guc_wopcm_size(dev_priv)) {
>>  		DRM_NOTE("Firmware is too large to fit in WOPCM\n");
>>  		goto fail;
>> @@ -659,21 +659,21 @@ static void guc_fw_fetch(struct drm_i915_private
>*dev_priv,
>>  	 * TWO bytes each (i.e. u16), although all pointers and offsets are defined
>>  	 * in terms of bytes (u8).
>>  	 */
>> -	guc_fw->guc_fw_major_found = css->guc_sw_version >> 16;
>> -	guc_fw->guc_fw_minor_found = css->guc_sw_version & 0xFFFF;
>> -
>> -	if (guc_fw->guc_fw_major_found != guc_fw->guc_fw_major_wanted ||
>> -	    guc_fw->guc_fw_minor_found < guc_fw->guc_fw_minor_wanted) {
>> -		DRM_NOTE("GuC firmware version %d.%d, required %d.%d\n",
>> -			guc_fw->guc_fw_major_found, guc_fw-
>>guc_fw_minor_found,
>> -			guc_fw->guc_fw_major_wanted, guc_fw-
>>guc_fw_minor_wanted);
>> +	uc_fw->major_ver_found = css->guc_sw_version >> 16;
>> +	uc_fw->minor_ver_found = css->guc_sw_version & 0xFFFF;
>> +
>> +	if (uc_fw->major_ver_found != uc_fw->major_ver_wanted ||
>> +	    uc_fw->minor_ver_found < uc_fw->minor_ver_wanted) {
>> +		DRM_NOTE("uC firmware version %d.%d, required %d.%d\n",
>> +			uc_fw->major_ver_found, uc_fw->minor_ver_found,
>> +			uc_fw->major_ver_wanted, uc_fw-
>>minor_ver_wanted);
>>  		err = -ENOEXEC;
>>  		goto fail;
>>  	}
>>
>>  	DRM_DEBUG_DRIVER("firmware version %d.%d OK (minimum
>%d.%d)\n",
>> -			guc_fw->guc_fw_major_found, guc_fw-
>>guc_fw_minor_found,
>> -			guc_fw->guc_fw_major_wanted, guc_fw-
>>guc_fw_minor_wanted);
>> +			uc_fw->major_ver_found, uc_fw->minor_ver_found,
>> +			uc_fw->major_ver_wanted, uc_fw-
>>minor_ver_wanted);
>>
>>  	mutex_lock(&dev_priv->drm.struct_mutex);
>>  	obj = i915_gem_object_create_from_data(dev_priv, fw->data,
>> fw->size); @@ -683,31 +683,31 @@ static void guc_fw_fetch(struct
>drm_i915_private *dev_priv,
>>  		goto fail;
>>  	}
>>
>> -	guc_fw->guc_fw_obj = obj;
>> -	guc_fw->guc_fw_size = fw->size;
>> +	uc_fw->uc_fw_obj = obj;
>> +	uc_fw->size = fw->size;
>>
>> -	DRM_DEBUG_DRIVER("GuC fw fetch status SUCCESS, obj %p\n",
>> -			guc_fw->guc_fw_obj);
>> +	DRM_DEBUG_DRIVER("uC fw fetch status SUCCESS, obj %p\n",
>> +			uc_fw->uc_fw_obj);
>>
>>  	release_firmware(fw);
>> -	guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_SUCCESS;
>> +	uc_fw->fetch_status = INTEL_UC_FIRMWARE_SUCCESS;
>>  	return;
>>
>>  fail:
>> -	DRM_WARN("Failed to fetch valid GuC firmware from %s (error %d)\n",
>> -		 guc_fw->guc_fw_path, err);
>> -	DRM_DEBUG_DRIVER("GuC fw fetch status FAIL; err %d, fw %p, obj
>%p\n",
>> -		err, fw, guc_fw->guc_fw_obj);
>> +	DRM_WARN("Failed to fetch valid uC firmware from %s (error %d)\n",
>> +		 uc_fw->uc_fw_path, err);
>> +	DRM_DEBUG_DRIVER("uC fw fetch status FAIL; err %d, fw %p, obj
>%p\n",
>> +		err, fw, uc_fw->uc_fw_obj);
>>
>>  	mutex_lock(&dev_priv->drm.struct_mutex);
>> -	obj = guc_fw->guc_fw_obj;
>> +	obj = uc_fw->uc_fw_obj;
>>  	if (obj)
>>  		i915_gem_object_put(obj);
>> -	guc_fw->guc_fw_obj = NULL;
>> +	uc_fw->uc_fw_obj = NULL;
>>  	mutex_unlock(&dev_priv->drm.struct_mutex);
>>
>>  	release_firmware(fw);		/* OK even if fw is NULL */
>> -	guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL;
>> +	uc_fw->fetch_status = INTEL_UC_FIRMWARE_FAIL;
>>  }
>>
>>  /**
>> @@ -721,7 +721,7 @@ static void guc_fw_fetch(struct drm_i915_private
>*dev_priv,
>>   */
>>  void intel_guc_init(struct drm_i915_private *dev_priv)  {
>> -	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
>> +	struct intel_uc_fw *guc_fw = &dev_priv->guc.fw;
>>  	const char *fw_path;
>>
>>  	if (!HAS_GUC(dev_priv)) {
>> @@ -739,23 +739,23 @@ void intel_guc_init(struct drm_i915_private
>*dev_priv)
>>  		fw_path = NULL;
>>  	} else if (IS_SKYLAKE(dev_priv)) {
>>  		fw_path = I915_SKL_GUC_UCODE;
>> -		guc_fw->guc_fw_major_wanted = SKL_FW_MAJOR;
>> -		guc_fw->guc_fw_minor_wanted = SKL_FW_MINOR;
>> +		guc_fw->major_ver_wanted = SKL_FW_MAJOR;
>> +		guc_fw->minor_ver_wanted = SKL_FW_MINOR;
>>  	} else if (IS_BROXTON(dev_priv)) {
>>  		fw_path = I915_BXT_GUC_UCODE;
>> -		guc_fw->guc_fw_major_wanted = BXT_FW_MAJOR;
>> -		guc_fw->guc_fw_minor_wanted = BXT_FW_MINOR;
>> +		guc_fw->major_ver_wanted = BXT_FW_MAJOR;
>> +		guc_fw->minor_ver_wanted = BXT_FW_MINOR;
>>  	} else if (IS_KABYLAKE(dev_priv)) {
>>  		fw_path = I915_KBL_GUC_UCODE;
>> -		guc_fw->guc_fw_major_wanted = KBL_FW_MAJOR;
>> -		guc_fw->guc_fw_minor_wanted = KBL_FW_MINOR;
>> +		guc_fw->major_ver_wanted = KBL_FW_MAJOR;
>> +		guc_fw->minor_ver_wanted = KBL_FW_MINOR;
>>  	} else {
>>  		fw_path = "";	/* unknown device */
>>  	}
>>
>> -	guc_fw->guc_fw_path = fw_path;
>> -	guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
>> -	guc_fw->guc_fw_load_status = GUC_FIRMWARE_NONE;
>> +	guc_fw->uc_fw_path = fw_path;
>> +	guc_fw->fetch_status = INTEL_UC_FIRMWARE_NONE;
>> +	guc_fw->load_status = INTEL_UC_FIRMWARE_NONE;
>>
>>  	/* Early (and silent) return if GuC loading is disabled */
>>  	if (!i915.enable_guc_loading)
>> @@ -765,9 +765,9 @@ void intel_guc_init(struct drm_i915_private *dev_priv)
>>  	if (*fw_path == '\0')
>>  		return;
>>
>> -	guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_PENDING;
>> +	guc_fw->fetch_status = INTEL_UC_FIRMWARE_PENDING;
>>  	DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path);
>> -	guc_fw_fetch(dev_priv, guc_fw);
>> +	intel_uc_fw_fetch(dev_priv, guc_fw);
>>  	/* status must now be FAIL or SUCCESS */  }
>>
>> @@ -777,17 +777,17 @@ void intel_guc_init(struct drm_i915_private
>*dev_priv)
>>   */
>>  void intel_guc_fini(struct drm_i915_private *dev_priv)  {
>> -	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
>> +	struct intel_uc_fw *guc_fw = &dev_priv->guc.fw;
>>
>>  	mutex_lock(&dev_priv->drm.struct_mutex);
>>  	guc_interrupts_release(dev_priv);
>>  	i915_guc_submission_disable(dev_priv);
>>  	i915_guc_submission_fini(dev_priv);
>>
>> -	if (guc_fw->guc_fw_obj)
>> -		i915_gem_object_put(guc_fw->guc_fw_obj);
>> -	guc_fw->guc_fw_obj = NULL;
>> +	if (guc_fw->uc_fw_obj)
>> +		i915_gem_object_put(guc_fw->uc_fw_obj);
>> +	guc_fw->uc_fw_obj = NULL;
>>  	mutex_unlock(&dev_priv->drm.struct_mutex);
>>
>> -	guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
>> +	guc_fw->fetch_status = INTEL_UC_FIRMWARE_NONE;
>>  }
>> diff --git a/drivers/gpu/drm/i915/intel_uc.h
>> b/drivers/gpu/drm/i915/intel_uc.h index 11f5608..893bcec 100644
>> --- a/drivers/gpu/drm/i915/intel_uc.h
>> +++ b/drivers/gpu/drm/i915/intel_uc.h
>> @@ -91,28 +91,28 @@ struct i915_guc_client {
>>  	uint64_t submissions[I915_NUM_ENGINES];  };
>>
>> -enum intel_guc_fw_status {
>> -	GUC_FIRMWARE_FAIL = -1,
>> -	GUC_FIRMWARE_NONE = 0,
>> -	GUC_FIRMWARE_PENDING,
>> -	GUC_FIRMWARE_SUCCESS
>> +enum intel_uc_fw_status {
>> +	INTEL_UC_FIRMWARE_FAIL = -1,
>> +	INTEL_UC_FIRMWARE_NONE = 0,
>> +	INTEL_UC_FIRMWARE_PENDING,
>> +	INTEL_UC_FIRMWARE_SUCCESS
>>  };
>>
>>  /*
>>   * This structure encapsulates all the data needed during the process
>>   * of fetching, caching, and loading the firmware image into the GuC.
>>   */
>> -struct intel_guc_fw {
>> -	const char *			guc_fw_path;
>> -	size_t				guc_fw_size;
>> -	struct drm_i915_gem_object *	guc_fw_obj;
>> -	enum intel_guc_fw_status	guc_fw_fetch_status;
>> -	enum intel_guc_fw_status	guc_fw_load_status;
>> -
>> -	uint16_t			guc_fw_major_wanted;
>> -	uint16_t			guc_fw_minor_wanted;
>> -	uint16_t			guc_fw_major_found;
>> -	uint16_t			guc_fw_minor_found;
>> +struct intel_uc_fw {
>> +	const char *uc_fw_path;
>
>Can we drop "uc_fw_" prefix also from path and obj members?

Michal, you think we can do this change as a part of the guc refactor effort which will happen post this series gets merged? Or do you feel its makes more sense to that we have this change in this series....

Anusha
>Michal
>
>> +	size_t size;
>> +	struct drm_i915_gem_object *uc_fw_obj;
>> +	enum intel_uc_fw_status fetch_status;
>> +	enum intel_uc_fw_status load_status;
>> +
>> +	uint16_t major_ver_wanted;
>> +	uint16_t minor_ver_wanted;
>> +	uint16_t major_ver_found;
>> +	uint16_t minor_ver_found;
>>
>>  	uint32_t header_size;
>>  	uint32_t header_offset;
>> @@ -139,7 +139,7 @@ struct intel_guc_log {  };
>>
>>  struct intel_guc {
>> -	struct intel_guc_fw guc_fw;
>> +	struct intel_uc_fw fw;
>>  	struct intel_guc_log log;
>>
>>  	/* intel_guc_recv interrupt related state */ @@ -181,7 +181,7 @@ int
>> intel_guc_log_control(struct intel_guc *guc, u32 control_val);  extern
>> void intel_guc_init(struct drm_i915_private *dev_priv);  extern int
>> intel_guc_setup(struct drm_i915_private *dev_priv);  extern void
>> intel_guc_fini(struct drm_i915_private *dev_priv); -extern const char
>> *intel_guc_fw_status_repr(enum intel_guc_fw_status status);
>> +extern const char *intel_uc_fw_status_repr(enum intel_uc_fw_status
>> +status);
>>  extern int intel_guc_suspend(struct drm_i915_private *dev_priv);
>> extern int intel_guc_resume(struct drm_i915_private *dev_priv);
>>
>> --
>> 2.7.4
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 3/8] drm/i915/huc: Add HuC fw loading support

[Srivatsa, Anusha]

>-----Original Message-----
>From: Wajdeczko, Michal
>Sent: Tuesday, December 27, 2016 9:51 AM
>To: Srivatsa, Anusha <anusha.srivatsa@intel.com>
>Cc: intel-gfx@lists.freedesktop.org; Alex Dai <yu.dai@intel.com>; Peter Antoine
><peter.antoine@intel.com>
>Subject: Re: [Intel-gfx] [PATCH 3/8] drm/i915/huc: Add HuC fw loading support
>
>On Thu, Dec 22, 2016 at 03:12:19PM -0800, Anusha Srivatsa wrote:
>> The HuC loading process is similar to GuC. The intel_uc_fw_fetch() is
>> used for both cases.
>>
>> HuC loading needs to be before GuC loading. The WOPCM setting must be
>> done early before loading any of them.
>>
>> v2: rebased on-top of drm-intel-nightly.
>>     removed if(HAS_GUC()) before the guc call. (D.Gordon)
>>     update huc_version number of format.
>> v3: rebased to drm-intel-nightly, changed the file name format to
>>     match the one in the huc package.
>>     Changed dev->dev_private to to_i915()
>> v4: moved function back to where it was.
>>     change wait_for_atomic to wait_for.
>> v5: rebased + comment changes.
>> v7: rebased.
>> v8: rebased.
>> v9: rebased. Changed the year in the copyright message to reflect the
>> right year.Correct the comments,remove the unwanted WARN message,
>> replace drm_gem_object_unreference() with i915_gem_object_put().Make
>> the prototypes in intel_huc.h non-extern.
>> v10: rebased. Update the file construction done by HuC. It is similar
>> to GuC.Adopted the approach used in-
>> https://patchwork.freedesktop.org/patch/104355/ <Tvrtko Ursulin>
>> v11: Fix warnings remove old declaration
>> v12: Change dev to dev_priv in macro definition.
>> Corrected comments.
>> v13: rebased.
>> v14: rebased on top of drm-tip
>> v15: rebased. Updated functions intel_huc_load(),intel_huc_init() and
>> intel_uc_fw_fetch() to accept dev_priv instead of dev. Moved contents
>> of intel_huc.h to intel_uc.h
>> v16: change SKL_FW_ to SKL_HUC_FW_. Add intel_ prefix to
>guc_wopcm_size().
>> Remove unwanted checks in intel_uc.h. Rename huc_fw in struct
>> intel_huc to simply fw to avoid redundency.
>> v17: rebased.
>>
>> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> Tested-by: Xiang Haihao <haihao.xiang@intel.com>
>> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>> Signed-off-by: Alex Dai <yu.dai@intel.com>
>> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
>> ---
>>  drivers/gpu/drm/i915/Makefile           |   1 +
>>  drivers/gpu/drm/i915/i915_drv.c         |   4 +-
>>  drivers/gpu/drm/i915/i915_drv.h         |   3 +-
>>  drivers/gpu/drm/i915/i915_guc_reg.h     |   3 +
>>  drivers/gpu/drm/i915/intel_guc_loader.c |  11 +-
>> drivers/gpu/drm/i915/intel_huc_loader.c | 263
>++++++++++++++++++++++++++++++++
>>  drivers/gpu/drm/i915/intel_uc.h         |  18 +++
>>  7 files changed, 296 insertions(+), 7 deletions(-)  create mode
>> 100644 drivers/gpu/drm/i915/intel_huc_loader.c
>>
>> diff --git a/drivers/gpu/drm/i915/Makefile
>> b/drivers/gpu/drm/i915/Makefile index 5196509..45ae124 100644
>> --- a/drivers/gpu/drm/i915/Makefile
>> +++ b/drivers/gpu/drm/i915/Makefile
>> @@ -57,6 +57,7 @@ i915-y += i915_cmd_parser.o \  # general-purpose
>> microcontroller (GuC) support  i915-y += intel_uc.o \
>>  	  intel_guc_loader.o \
>> +	  intel_huc_loader.o \
>>  	  i915_guc_submission.o
>>
>>  # autogenerated null render state
>> diff --git a/drivers/gpu/drm/i915/i915_drv.c
>> b/drivers/gpu/drm/i915/i915_drv.c index 6428588..85a47c2 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.c
>> +++ b/drivers/gpu/drm/i915/i915_drv.c
>> @@ -600,6 +600,7 @@ static int i915_load_modeset_init(struct drm_device
>*dev)
>>  	if (ret)
>>  		goto cleanup_irq;
>>
>> +	intel_huc_init(dev_priv);
>>  	intel_guc_init(dev_priv);
>>
>>  	ret = i915_gem_init(dev_priv);
>> @@ -627,6 +628,7 @@ static int i915_load_modeset_init(struct drm_device
>*dev)
>>  		DRM_ERROR("failed to idle hardware; continuing to unload!\n");
>>  	i915_gem_fini(dev_priv);
>>  cleanup_irq:
>> +	intel_huc_fini(dev);
>>  	intel_guc_fini(dev_priv);
>>  	drm_irq_uninstall(dev);
>>  	intel_teardown_gmbus(dev_priv);
>> @@ -1313,7 +1315,7 @@ void i915_driver_unload(struct drm_device *dev)
>>
>>  	/* Flush any outstanding unpin_work. */
>>  	drain_workqueue(dev_priv->wq);
>> -
>> +	intel_huc_fini(dev);
>>  	intel_guc_fini(dev_priv);
>>  	i915_gem_fini(dev_priv);
>>  	intel_fbc_cleanup_cfb(dev_priv);
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>> b/drivers/gpu/drm/i915/i915_drv.h index 1a91409..7ac7730 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -2147,6 +2147,7 @@ struct drm_i915_private {
>>
>>  	struct intel_gvt *gvt;
>>
>> +	struct intel_huc huc;
>>  	struct intel_guc guc;
>>
>>  	struct intel_csr csr;
>> @@ -2921,7 +2922,7 @@ intel_info(const struct drm_i915_private *dev_priv)
>>  #define HAS_GUC(dev_priv)	((dev_priv)->info.has_guc)
>>  #define HAS_GUC_UCODE(dev_priv)	(HAS_GUC(dev_priv))
>>  #define HAS_GUC_SCHED(dev_priv)	(HAS_GUC(dev_priv))
>> -
>> +#define HAS_HUC_UCODE(dev_priv)	(HAS_GUC(dev_priv))
>>  #define HAS_RESOURCE_STREAMER(dev_priv)
>> ((dev_priv)->info.has_resource_streamer)
>>
>>  #define HAS_POOLED_EU(dev_priv)	((dev_priv)->info.has_pooled_eu)
>> diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h
>> b/drivers/gpu/drm/i915/i915_guc_reg.h
>> index 5e638fc..f9829f6 100644
>> --- a/drivers/gpu/drm/i915/i915_guc_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_guc_reg.h
>> @@ -61,9 +61,12 @@
>>  #define   DMA_ADDRESS_SPACE_GTT		  (8 << 16)
>>  #define DMA_COPY_SIZE			_MMIO(0xc310)
>>  #define DMA_CTRL			_MMIO(0xc314)
>> +#define   HUC_UKERNEL			  (1<<9)
>>  #define   UOS_MOVE			  (1<<4)
>>  #define   START_DMA			  (1<<0)
>>  #define DMA_GUC_WOPCM_OFFSET		_MMIO(0xc340)
>> +#define   HUC_LOADING_AGENT_VCR		  (0<<1)
>> +#define   HUC_LOADING_AGENT_GUC		  (1<<1)
>>  #define   GUC_WOPCM_OFFSET_VALUE	  0x80000	/* 512KB */
>>  #define GUC_MAX_IDLE_COUNT		_MMIO(0xC3E4)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
>> b/drivers/gpu/drm/i915/intel_guc_loader.c
>> index 06e3e5c..8c77e94 100644
>> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
>> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
>> @@ -309,8 +309,8 @@ static int guc_ucode_xfer_dma(struct drm_i915_private
>*dev_priv,
>>  	I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
>>
>>  	/* Finally start the DMA */
>> -	I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE |
>START_DMA));
>> -
>> +	I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE |
>START_DMA) |
>> +		_MASKED_BIT_DISABLE(HUC_UKERNEL));
>>  	/*
>>  	 * Wait for the DMA to complete & the GuC to start up.
>>  	 * NB: Docs recommend not using the interrupt for completion.
>> @@ -334,7 +334,7 @@ static int guc_ucode_xfer_dma(struct drm_i915_private
>*dev_priv,
>>  	return ret;
>>  }
>>
>> -static u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
>> +u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv)
>>  {
>>  	u32 wopcm_size = GUC_WOPCM_TOP;
>>
>> @@ -372,7 +372,7 @@ static int guc_ucode_xfer(struct drm_i915_private
>*dev_priv)
>>  	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
>>
>>  	/* init WOPCM */
>> -	I915_WRITE(GUC_WOPCM_SIZE, guc_wopcm_size(dev_priv));
>> +	I915_WRITE(GUC_WOPCM_SIZE, intel_guc_wopcm_size(dev_priv));
>>  	I915_WRITE(DMA_GUC_WOPCM_OFFSET,
>GUC_WOPCM_OFFSET_VALUE);
>>
>>  	/* Enable MIA caching. GuC clock gating is disabled. */ @@ -511,6
>> +511,7 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
>>  		if (err)
>>  			goto fail;
>>
>> +		intel_huc_load(dev_priv);
>>  		err = guc_ucode_xfer(dev_priv);
>>  		if (!err)
>>  			break;
>> @@ -658,7 +659,7 @@ void intel_uc_fw_fetch(struct drm_i915_private
>*dev_priv,
>>  		size = uc_fw->header_size + uc_fw->ucode_size;
>>
>>  		/* Top 32k of WOPCM is reserved (8K stack + 24k RC6 context).
>*/
>> -		if (size > guc_wopcm_size(dev_priv)) {
>> +		if (size > intel_guc_wopcm_size(dev_priv)) {
>>  			DRM_ERROR("Firmware is too large to fit in
>WOPCM\n");
>>  			goto fail;
>>  		}
>> diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c
>> b/drivers/gpu/drm/i915/intel_huc_loader.c
>> new file mode 100644
>> index 0000000..98d631c
>> --- /dev/null
>> +++ b/drivers/gpu/drm/i915/intel_huc_loader.c
>> @@ -0,0 +1,263 @@
>> +/*
>> + * Copyright (c) 2016 Intel Corporation
>> + *
>> + * Permission is hereby granted, free of charge, to any person
>> +obtaining a
>> + * copy of this software and associated documentation files (the
>> +"Software"),
>> + * to deal in the Software without restriction, including without
>> +limitation
>> + * the rights to use, copy, modify, merge, publish, distribute,
>> +sublicense,
>> + * and/or sell copies of the Software, and to permit persons to whom
>> +the
>> + * Software is furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice (including
>> +the next
>> + * paragraph) shall be included in all copies or substantial portions
>> +of the
>> + * Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> +EXPRESS OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
>> +MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO
>EVENT
>> +SHALL
>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
>DAMAGES
>> +OR OTHER
>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>> +ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> +OTHER DEALINGS
>> + * IN THE SOFTWARE.
>> + *
>> + */
>> +#include <linux/firmware.h>
>> +#include "i915_drv.h"
>> +#include "intel_uc.h"
>> +
>> +/**
>> + * DOC: HuC Firmware
>> + *
>> + * Motivation:
>> + * GEN9 introduces a new dedicated firmware for usage in media HEVC
>> +(High
>> + * Efficiency Video Coding) operations. Userspace can use the
>> +firmware
>> + * capabilities by adding HuC specific commands to batch buffers.
>> + *
>> + * Implementation:
>> + * The same firmware loader is used as the GuC. However, the actual
>> + * loading to HW is deferred until GEM initialization is done.
>> + *
>> + * Note that HuC firmware loading must be done before GuC loading.
>> + */
>> +
>> +#define SKL_HUC_FW_MAJOR 01
>> +#define SKL_HUC_FW_MINOR 07
>> +#define SKL_BLD_NUM 1398
>> +
>> +#define HUC_FW_PATH(platform, major, minor, bld_num) \
>> +	"i915/" __stringify(platform) "_huc_ver" __stringify(major) "_" \
>> +	__stringify(minor) "_" __stringify(bld_num) ".bin"
>> +
>> +#define I915_SKL_HUC_UCODE HUC_FW_PATH(skl, SKL_HUC_FW_MAJOR, \
>> +	SKL_HUC_FW_MINOR, SKL_BLD_NUM)
>> +MODULE_FIRMWARE(I915_SKL_HUC_UCODE);
>> +
>> +/**
>> + * huc_ucode_xfer() - DMA's the firmware
>> + * @dev_priv: the drm device
>> + *
>> + * This function takes the gem object containing the firmware, sets
>> +up the DMA
>
>Hmm, this function takes just dev_priv...

Oops.... will change the comment.

Anusha
>
>> + * engine MMIO, triggers the DMA operation and waits for it to finish.
>> + *
>> + * Transfer the firmware image to RAM for execution by the microcontroller.
>> + *
>> + * Return: 0 on success, non-zero on failure  */ static int
>> +huc_ucode_xfer(struct drm_i915_private *dev_priv) {
>> +	struct intel_uc_fw *huc_fw = &dev_priv->huc.fw;
>> +	struct i915_vma *vma;
>> +	unsigned long offset = 0;
>> +	u32 size;
>> +	int ret;
>> +
>> +	ret = i915_gem_object_set_to_gtt_domain(huc_fw->uc_fw_obj, false);
>> +	if (ret) {
>> +		DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
>> +		return ret;
>> +	}
>> +
>> +	vma = i915_gem_object_ggtt_pin(huc_fw->uc_fw_obj, NULL, 0, 0, 0);
>> +	if (IS_ERR(vma)) {
>> +		DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
>> +		return PTR_ERR(vma);
>> +	}
>> +
>> +	/* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
>> +	I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
>> +
>> +	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
>> +
>> +	/* init WOPCM */
>> +	I915_WRITE(GUC_WOPCM_SIZE, intel_guc_wopcm_size(dev_priv));
>> +	I915_WRITE(DMA_GUC_WOPCM_OFFSET,
>GUC_WOPCM_OFFSET_VALUE |
>> +			HUC_LOADING_AGENT_GUC);
>> +
>> +	/* Set the source address for the uCode */
>> +	offset = i915_ggtt_offset(vma) + huc_fw->header_offset;
>> +	I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
>> +	I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
>> +
>> +	/* Hardware doesn't look at destination address for HuC. Set it to 0,
>> +	 * but still program the correct address space.
>> +	 */
>> +	I915_WRITE(DMA_ADDR_1_LOW, 0);
>> +	I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
>> +
>> +	size = huc_fw->header_size + huc_fw->ucode_size;
>> +	I915_WRITE(DMA_COPY_SIZE, size);
>> +
>> +	/* Start the DMA */
>> +	I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(HUC_UKERNEL |
>START_DMA));
>> +
>> +	/* Wait for DMA to finish */
>> +	ret = wait_for((I915_READ(DMA_CTRL) & START_DMA) == 0, 100);
>> +
>> +	DRM_DEBUG_DRIVER("HuC DMA transfer wait over with ret %d\n", ret);
>> +
>> +	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
>> +
>> +	/*
>> +	 * We keep the object pages for reuse during resume. But we can unpin it
>> +	 * now that DMA has completed, so it doesn't continue to take up space.
>> +	 */
>> +	i915_vma_unpin(vma);
>> +
>> +	return ret;
>> +}
>> +
>> +/**
>> + * intel_huc_init() - initiate HuC firmware loading request
>> + * @dev_priv: the drm_i915_private device
>> + *
>> + * Called early during driver load, but after GEM is initialised. The
>> +loading
>> + * will continue only when driver explicitly specify firmware name and version.
>> + * All other cases are considered as INTEL_UC_FIRMWARE_NONE either
>> +because HW
>> + * is not capable or driver yet support it. And there will be no
>> +error message
>> + * for INTEL_UC_FIRMWARE_NONE cases.
>> + *
>> + * The DMA-copying to HW is done later when intel_huc_load() is called.
>> + */
>> +void intel_huc_init(struct drm_i915_private *dev_priv) {
>> +	struct intel_huc *huc = &dev_priv->huc;
>> +	struct intel_uc_fw *huc_fw = &huc->fw;
>> +	const char *fw_path = NULL;
>> +
>> +	huc_fw->uc_fw_path = NULL;
>> +	huc_fw->fetch_status = INTEL_UC_FIRMWARE_NONE;
>> +	huc_fw->load_status = INTEL_UC_FIRMWARE_NONE;
>> +	huc_fw->fw_type = INTEL_UC_FW_TYPE_HUC;
>> +
>> +	if (!HAS_HUC_UCODE(dev_priv))
>> +		return;
>> +
>> +	if (IS_SKYLAKE(dev_priv)) {
>> +		fw_path = I915_SKL_HUC_UCODE;
>> +		huc_fw->major_ver_wanted = SKL_HUC_FW_MAJOR;
>> +		huc_fw->minor_ver_wanted = SKL_HUC_FW_MINOR;
>> +	}
>> +
>> +	huc_fw->uc_fw_path = fw_path;
>> +	huc_fw->fetch_status = INTEL_UC_FIRMWARE_PENDING;
>> +
>> +	DRM_DEBUG_DRIVER("HuC firmware pending, path %s\n", fw_path);
>> +
>> +	intel_uc_fw_fetch(dev_priv, huc_fw); }
>> +
>> +/**
>> + * intel_huc_load() - load HuC uCode to device
>> + * @dev_priv: the drm_i915_private device
>> + *
>> + * Called from gem_init_hw() during driver loading and also after a GPU reset.
>> + * Be note that HuC loading must be done before GuC loading.
>> + *
>> + * The firmware image should have already been fetched into memory by
>> +the
>> + * earlier call to intel_huc_init(), so here we need only check that
>> + * is succeeded, and then transfer the image to the h/w.
>> + *
>> + * Return:	non-zero code on error
>> + */
>> +int intel_huc_load(struct drm_i915_private *dev_priv) {
>> +	struct intel_uc_fw *huc_fw = &dev_priv->huc.fw;
>> +	int err;
>> +
>> +	if (huc_fw->fetch_status == INTEL_UC_FIRMWARE_NONE)
>> +		return 0;
>> +
>> +	DRM_DEBUG_DRIVER("%s fw status: fetch %s, load %s\n",
>> +		huc_fw->uc_fw_path,
>> +		intel_uc_fw_status_repr(huc_fw->fetch_status),
>> +		intel_uc_fw_status_repr(huc_fw->load_status));
>> +
>> +	if (huc_fw->fetch_status == INTEL_UC_FIRMWARE_SUCCESS &&
>> +	    huc_fw->load_status == INTEL_UC_FIRMWARE_FAIL)
>> +		return -ENOEXEC;
>> +
>> +	huc_fw->load_status = INTEL_UC_FIRMWARE_PENDING;
>> +
>> +	switch (huc_fw->fetch_status) {
>> +	case INTEL_UC_FIRMWARE_FAIL:
>> +		/* something went wrong :( */
>> +		err = -EIO;
>> +		goto fail;
>> +
>> +	case INTEL_UC_FIRMWARE_NONE:
>> +	case INTEL_UC_FIRMWARE_PENDING:
>> +	default:
>> +		/* "can't happen" */
>> +		WARN_ONCE(1, "HuC fw %s invalid fetch_status %s [%d]\n",
>> +			huc_fw->uc_fw_path,
>> +			intel_uc_fw_status_repr(huc_fw->fetch_status),
>> +			huc_fw->fetch_status);
>> +		err = -ENXIO;
>> +		goto fail;
>> +
>> +	case INTEL_UC_FIRMWARE_SUCCESS:
>> +		break;
>> +	}
>> +
>> +	err = huc_ucode_xfer(dev_priv);
>> +	if (err)
>> +		goto fail;
>> +
>> +	huc_fw->load_status = INTEL_UC_FIRMWARE_SUCCESS;
>> +
>> +	DRM_DEBUG_DRIVER("%s fw status: fetch %s, load %s\n",
>> +		huc_fw->uc_fw_path,
>> +		intel_uc_fw_status_repr(huc_fw->fetch_status),
>> +		intel_uc_fw_status_repr(huc_fw->load_status));
>
>Hmm, this message will always display "fetch SUCCESS load SUCCESS"
>as all other cases all handled as fail below... is it expected ?
>
>> +
>> +	return 0;
>> +
>> +fail:
>> +	if (huc_fw->load_status == INTEL_UC_FIRMWARE_PENDING)
>> +		huc_fw->load_status = INTEL_UC_FIRMWARE_FAIL;
>> +
>> +	DRM_ERROR("Failed to complete HuC uCode load with ret %d\n", err);
>> +
>> +	return err;
>> +}
>> +
>> +/**
>> + * intel_huc_fini() - clean up resources allocated for HuC
>> + * @dev: the drm device
>> + *
>> + * Cleans up by releasing the huc firmware GEM obj.
>> + */
>> +void intel_huc_fini(struct drm_device *dev)
>
>Why this function takes dev? All other functions take dev_priv.
>
>Michal
>
>> +{
>> +	struct drm_i915_private *dev_priv = to_i915(dev);
>> +	struct intel_uc_fw *huc_fw = &dev_priv->huc.fw;
>> +
>> +	mutex_lock(&dev->struct_mutex);
>> +	if (huc_fw->uc_fw_obj)
>> +		i915_gem_object_put(huc_fw->uc_fw_obj);
>> +	huc_fw->uc_fw_obj = NULL;
>> +	mutex_unlock(&dev->struct_mutex);
>> +
>> +	huc_fw->fetch_status = INTEL_UC_FIRMWARE_NONE; }
>> +
>> diff --git a/drivers/gpu/drm/i915/intel_uc.h
>> b/drivers/gpu/drm/i915/intel_uc.h index ad140e2..57aef56 100644
>> --- a/drivers/gpu/drm/i915/intel_uc.h
>> +++ b/drivers/gpu/drm/i915/intel_uc.h
>> @@ -24,6 +24,9 @@
>>  #ifndef _INTEL_UC_H_
>>  #define _INTEL_UC_H_
>>
>> +#define HUC_STATUS2             _MMIO(0xD3B0)
>> +#define   HUC_FW_VERIFIED       (1<<7)
>> +
>>  #include "intel_guc_fwif.h"
>>  #include "i915_guc_reg.h"
>>  #include "intel_ringbuffer.h"
>> @@ -174,6 +177,13 @@ struct intel_guc {
>>  	struct mutex send_mutex;
>>  };
>>
>> +struct intel_huc {
>> +	/* Generic uC firmware management */
>> +	struct intel_uc_fw fw;
>> +
>> +	/* HuC-specific additions */
>> +};
>> +
>>  /* intel_uc.c */
>>  void intel_uc_init_early(struct drm_i915_private *dev_priv);  bool
>> intel_guc_recv(struct drm_i915_private *dev_priv, u32 *status); @@
>> -190,6 +200,9 @@ extern void intel_guc_fini(struct drm_i915_private
>> *dev_priv);  extern const char *intel_uc_fw_status_repr(enum
>> intel_uc_fw_status status);  extern int intel_guc_suspend(struct
>> drm_i915_private *dev_priv);  extern int intel_guc_resume(struct
>> drm_i915_private *dev_priv);
>> +void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
>> +	struct intel_uc_fw *uc_fw);
>> +u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv);
>>
>>  /* i915_guc_submission.c */
>>  int i915_guc_submission_init(struct drm_i915_private *dev_priv); @@
>> -204,4 +217,9 @@ void i915_guc_register(struct drm_i915_private
>> *dev_priv);  void i915_guc_unregister(struct drm_i915_private
>> *dev_priv);  int i915_guc_log_control(struct drm_i915_private
>> *dev_priv, u64 control_val);
>>
>> +/* intel_huc_loader.c */
>> +void intel_huc_init(struct drm_i915_private *dev_priv); void
>> +intel_huc_fini(struct drm_device *dev); int intel_huc_load(struct
>> +drm_i915_private *dev_priv);
>> +
>>  #endif
>> --
>> 2.7.4
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 1/8] drm/i915/guc: Make the GuC fw loading helper functions general

[Michal Wajdeczko]

On Tue, Jan 03, 2017 at 01:07:14AM +0100, Srivatsa, Anusha wrote:
> 
> 
> >-----Original Message-----
> >From: Wajdeczko, Michal
> >Sent: Tuesday, December 27, 2016 9:28 AM
> >To: Srivatsa, Anusha <anusha.srivatsa@intel.com>
> >Cc: intel-gfx@lists.freedesktop.org; Alex Dai <yu.dai@intel.com>; Peter Antoine
> ><peter.antoine@intel.com>
> >Subject: Re: [Intel-gfx] [PATCH 1/8] drm/i915/guc: Make the GuC fw loading
> >helper functions general
> >
> >On Thu, Dec 22, 2016 at 03:12:17PM -0800, Anusha Srivatsa wrote:
> >> From: Peter Antoine <peter.antoine@intel.com>
> >>
> >> Rename some of the GuC fw loading code to make them more general. We
> >> will utilise them for HuC loading as well.
> >>      s/intel_guc_fw/intel_uc_fw/g
> >>      s/GUC_FIRMWARE/UC_FIRMWARE/g
> >>
> >> Struct intel_guc_fw is renamed to intel_uc_fw. Prefix of tts members,
> >> such as 'guc' or 'guc_fw' either is renamed to 'uc' or removed for
> >> same purpose.
> >>
> >> v2: rebased on top of nightly.
> >>     reapplied the search/replace as upstream code as changed.
> >> v3: rebased again on drm-nightly.
> >> v4: removed G from messages in shared fw fetch function.
> >> v5: rebased.
> >> v7: rebased.
> >> v8: rebased.
> >> v9: rebased.
> >> v10: rebased.
> >> v11: rebased.
> >> v12: rebased on top of drm-tip
> >> v13: rebased.Updated dev to dev_priv in intel_guc_setup(),
> >> guc_fw_getch() and intel_guc_init().
> >> v14: rebased. Remove uint32_t fw_type to patch 2. Add INTEL_ prefix
> >> for fields in enum intel_uc_fw_status. Remove uc_dev field since its
> >> never used.Rename uc_fw to just fw and guc_fw to fw to avoid redundency.
> >> v15: rebased. Remove sections of code that were commented and no
> >> longer required.
> >>
> >> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> >> Signed-off-by: Alex Dai <yu.dai@intel.com>
> >> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> >> ---
> >>  drivers/gpu/drm/i915/i915_debugfs.c        |  12 +--
> >>  drivers/gpu/drm/i915/i915_guc_submission.c |   4 +-
> >>  drivers/gpu/drm/i915/intel_guc_loader.c    | 156 ++++++++++++++---------------
> >>  drivers/gpu/drm/i915/intel_uc.h            |  36 +++----
> >>  4 files changed, 104 insertions(+), 104 deletions(-)
> >>

... CUT ...

> >> diff --git a/drivers/gpu/drm/i915/intel_uc.h
> >> b/drivers/gpu/drm/i915/intel_uc.h index 11f5608..893bcec 100644
> >> --- a/drivers/gpu/drm/i915/intel_uc.h
> >> +++ b/drivers/gpu/drm/i915/intel_uc.h
> >> @@ -91,28 +91,28 @@ struct i915_guc_client {
> >>  	uint64_t submissions[I915_NUM_ENGINES];  };
> >>
> >> -enum intel_guc_fw_status {
> >> -	GUC_FIRMWARE_FAIL = -1,
> >> -	GUC_FIRMWARE_NONE = 0,
> >> -	GUC_FIRMWARE_PENDING,
> >> -	GUC_FIRMWARE_SUCCESS
> >> +enum intel_uc_fw_status {
> >> +	INTEL_UC_FIRMWARE_FAIL = -1,
> >> +	INTEL_UC_FIRMWARE_NONE = 0,
> >> +	INTEL_UC_FIRMWARE_PENDING,
> >> +	INTEL_UC_FIRMWARE_SUCCESS
> >>  };
> >>
> >>  /*
> >>   * This structure encapsulates all the data needed during the process
> >>   * of fetching, caching, and loading the firmware image into the GuC.
> >>   */
> >> -struct intel_guc_fw {
> >> -	const char *			guc_fw_path;
> >> -	size_t				guc_fw_size;
> >> -	struct drm_i915_gem_object *	guc_fw_obj;
> >> -	enum intel_guc_fw_status	guc_fw_fetch_status;
> >> -	enum intel_guc_fw_status	guc_fw_load_status;
> >> -
> >> -	uint16_t			guc_fw_major_wanted;
> >> -	uint16_t			guc_fw_minor_wanted;
> >> -	uint16_t			guc_fw_major_found;
> >> -	uint16_t			guc_fw_minor_found;
> >> +struct intel_uc_fw {
> >> +	const char *uc_fw_path;
> >
> >Can we drop "uc_fw_" prefix also from path and obj members?
> 
> Michal, you think we can do this change as a part of the guc refactor effort which will happen post this series gets merged? Or do you feel its makes more sense to that we have this change in this series....
> 

IMHO we should avoid introducing changes that we already know they are bad and easy to fix.
Number of changes in names shall be minimized to avoid confusion and merge conflicts.
Also relaying on the future refactor effort (that has no known ETA) is not good option, as one can forget to fix it ;)

Thanks,
Michal
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 1/8] drm/i915/guc: Make the GuC fw loading helper functions general

[Srivatsa, Anusha]

>-----Original Message-----
>From: Wajdeczko, Michal
>Sent: Tuesday, January 3, 2017 6:15 AM
>To: Srivatsa, Anusha <anusha.srivatsa@intel.com>
>Cc: intel-gfx@lists.freedesktop.org
>Subject: Re: [Intel-gfx] [PATCH 1/8] drm/i915/guc: Make the GuC fw loading
>helper functions general
>
>On Tue, Jan 03, 2017 at 01:07:14AM +0100, Srivatsa, Anusha wrote:
>>
>>
>> >-----Original Message-----
>> >From: Wajdeczko, Michal
>> >Sent: Tuesday, December 27, 2016 9:28 AM
>> >To: Srivatsa, Anusha <anusha.srivatsa@intel.com>
>> >Cc: intel-gfx@lists.freedesktop.org; Alex Dai <yu.dai@intel.com>;
>> >Peter Antoine <peter.antoine@intel.com>
>> >Subject: Re: [Intel-gfx] [PATCH 1/8] drm/i915/guc: Make the GuC fw
>> >loading helper functions general
>> >
>> >On Thu, Dec 22, 2016 at 03:12:17PM -0800, Anusha Srivatsa wrote:
>> >> From: Peter Antoine <peter.antoine@intel.com>
>> >>
>> >> Rename some of the GuC fw loading code to make them more general.
>> >> We will utilise them for HuC loading as well.
>> >>      s/intel_guc_fw/intel_uc_fw/g
>> >>      s/GUC_FIRMWARE/UC_FIRMWARE/g
>> >>
>> >> Struct intel_guc_fw is renamed to intel_uc_fw. Prefix of tts
>> >> members, such as 'guc' or 'guc_fw' either is renamed to 'uc' or
>> >> removed for same purpose.
>> >>
>> >> v2: rebased on top of nightly.
>> >>     reapplied the search/replace as upstream code as changed.
>> >> v3: rebased again on drm-nightly.
>> >> v4: removed G from messages in shared fw fetch function.
>> >> v5: rebased.
>> >> v7: rebased.
>> >> v8: rebased.
>> >> v9: rebased.
>> >> v10: rebased.
>> >> v11: rebased.
>> >> v12: rebased on top of drm-tip
>> >> v13: rebased.Updated dev to dev_priv in intel_guc_setup(),
>> >> guc_fw_getch() and intel_guc_init().
>> >> v14: rebased. Remove uint32_t fw_type to patch 2. Add INTEL_ prefix
>> >> for fields in enum intel_uc_fw_status. Remove uc_dev field since
>> >> its never used.Rename uc_fw to just fw and guc_fw to fw to avoid
>redundency.
>> >> v15: rebased. Remove sections of code that were commented and no
>> >> longer required.
>> >>
>> >> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>> >> Signed-off-by: Alex Dai <yu.dai@intel.com>
>> >> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
>> >> ---
>> >>  drivers/gpu/drm/i915/i915_debugfs.c        |  12 +--
>> >>  drivers/gpu/drm/i915/i915_guc_submission.c |   4 +-
>> >>  drivers/gpu/drm/i915/intel_guc_loader.c    | 156 ++++++++++++++------------
>---
>> >>  drivers/gpu/drm/i915/intel_uc.h            |  36 +++----
>> >>  4 files changed, 104 insertions(+), 104 deletions(-)
>> >>
>
>... CUT ...
>
>> >> diff --git a/drivers/gpu/drm/i915/intel_uc.h
>> >> b/drivers/gpu/drm/i915/intel_uc.h index 11f5608..893bcec 100644
>> >> --- a/drivers/gpu/drm/i915/intel_uc.h
>> >> +++ b/drivers/gpu/drm/i915/intel_uc.h
>> >> @@ -91,28 +91,28 @@ struct i915_guc_client {
>> >>  	uint64_t submissions[I915_NUM_ENGINES];  };
>> >>
>> >> -enum intel_guc_fw_status {
>> >> -	GUC_FIRMWARE_FAIL = -1,
>> >> -	GUC_FIRMWARE_NONE = 0,
>> >> -	GUC_FIRMWARE_PENDING,
>> >> -	GUC_FIRMWARE_SUCCESS
>> >> +enum intel_uc_fw_status {
>> >> +	INTEL_UC_FIRMWARE_FAIL = -1,
>> >> +	INTEL_UC_FIRMWARE_NONE = 0,
>> >> +	INTEL_UC_FIRMWARE_PENDING,
>> >> +	INTEL_UC_FIRMWARE_SUCCESS
>> >>  };
>> >>
>> >>  /*
>> >>   * This structure encapsulates all the data needed during the process
>> >>   * of fetching, caching, and loading the firmware image into the GuC.
>> >>   */
>> >> -struct intel_guc_fw {
>> >> -	const char *			guc_fw_path;
>> >> -	size_t				guc_fw_size;
>> >> -	struct drm_i915_gem_object *	guc_fw_obj;
>> >> -	enum intel_guc_fw_status	guc_fw_fetch_status;
>> >> -	enum intel_guc_fw_status	guc_fw_load_status;
>> >> -
>> >> -	uint16_t			guc_fw_major_wanted;
>> >> -	uint16_t			guc_fw_minor_wanted;
>> >> -	uint16_t			guc_fw_major_found;
>> >> -	uint16_t			guc_fw_minor_found;
>> >> +struct intel_uc_fw {
>> >> +	const char *uc_fw_path;
>> >
>> >Can we drop "uc_fw_" prefix also from path and obj members?
>>
>> Michal, you think we can do this change as a part of the guc refactor effort
>which will happen post this series gets merged? Or do you feel its makes more
>sense to that we have this change in this series....
>>
>
>IMHO we should avoid introducing changes that we already know they are bad
>and easy to fix.
>Number of changes in names shall be minimized to avoid confusion and merge
>conflicts.
>Also relaying on the future refactor effort (that has no known ETA) is not good
>option, as one can forget to fix it ;)

Sure. :)

Anusha
>Thanks,
>Michal
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 3/8] drm/i915/huc: Add HuC fw loading support

[Srivatsa, Anusha]

>-----Original Message-----
>From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of
>Srivatsa, Anusha
>Sent: Monday, January 2, 2017 4:09 PM
>To: Wajdeczko, Michal <Michal.Wajdeczko@intel.com>
>Cc: intel-gfx@lists.freedesktop.org; Alex Dai <yu.dai@intel.com>; Peter Antoine
><peter.antoine@intel.com>
>Subject: Re: [Intel-gfx] [PATCH 3/8] drm/i915/huc: Add HuC fw loading support
>
>
>
>>-----Original Message-----
>>From: Wajdeczko, Michal
>>Sent: Tuesday, December 27, 2016 9:51 AM
>>To: Srivatsa, Anusha <anusha.srivatsa@intel.com>
>>Cc: intel-gfx@lists.freedesktop.org; Alex Dai <yu.dai@intel.com>; Peter
>>Antoine <peter.antoine@intel.com>
>>Subject: Re: [Intel-gfx] [PATCH 3/8] drm/i915/huc: Add HuC fw loading
>>support
>>
>>On Thu, Dec 22, 2016 at 03:12:19PM -0800, Anusha Srivatsa wrote:
>>> The HuC loading process is similar to GuC. The intel_uc_fw_fetch() is
>>> used for both cases.
>>>
>>> HuC loading needs to be before GuC loading. The WOPCM setting must be
>>> done early before loading any of them.
>>>
>>> v2: rebased on-top of drm-intel-nightly.
>>>     removed if(HAS_GUC()) before the guc call. (D.Gordon)
>>>     update huc_version number of format.
>>> v3: rebased to drm-intel-nightly, changed the file name format to
>>>     match the one in the huc package.
>>>     Changed dev->dev_private to to_i915()
>>> v4: moved function back to where it was.
>>>     change wait_for_atomic to wait_for.
>>> v5: rebased + comment changes.
>>> v7: rebased.
>>> v8: rebased.
>>> v9: rebased. Changed the year in the copyright message to reflect the
>>> right year.Correct the comments,remove the unwanted WARN message,
>>> replace drm_gem_object_unreference() with i915_gem_object_put().Make
>>> the prototypes in intel_huc.h non-extern.
>>> v10: rebased. Update the file construction done by HuC. It is similar
>>> to GuC.Adopted the approach used in-
>>> https://patchwork.freedesktop.org/patch/104355/ <Tvrtko Ursulin>
>>> v11: Fix warnings remove old declaration
>>> v12: Change dev to dev_priv in macro definition.
>>> Corrected comments.
>>> v13: rebased.
>>> v14: rebased on top of drm-tip
>>> v15: rebased. Updated functions intel_huc_load(),intel_huc_init() and
>>> intel_uc_fw_fetch() to accept dev_priv instead of dev. Moved contents
>>> of intel_huc.h to intel_uc.h
>>> v16: change SKL_FW_ to SKL_HUC_FW_. Add intel_ prefix to
>>guc_wopcm_size().
>>> Remove unwanted checks in intel_uc.h. Rename huc_fw in struct
>>> intel_huc to simply fw to avoid redundency.
>>> v17: rebased.
>>>
>>> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>> Tested-by: Xiang Haihao <haihao.xiang@intel.com>
>>> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>>> Signed-off-by: Alex Dai <yu.dai@intel.com>
>>> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
>>> ---
>>>  drivers/gpu/drm/i915/Makefile           |   1 +
>>>  drivers/gpu/drm/i915/i915_drv.c         |   4 +-
>>>  drivers/gpu/drm/i915/i915_drv.h         |   3 +-
>>>  drivers/gpu/drm/i915/i915_guc_reg.h     |   3 +
>>>  drivers/gpu/drm/i915/intel_guc_loader.c |  11 +-
>>> drivers/gpu/drm/i915/intel_huc_loader.c | 263
>>++++++++++++++++++++++++++++++++
>>>  drivers/gpu/drm/i915/intel_uc.h         |  18 +++
>>>  7 files changed, 296 insertions(+), 7 deletions(-)  create mode
>>> 100644 drivers/gpu/drm/i915/intel_huc_loader.c
>>>
>>> diff --git a/drivers/gpu/drm/i915/Makefile
>>> b/drivers/gpu/drm/i915/Makefile index 5196509..45ae124 100644
>>> --- a/drivers/gpu/drm/i915/Makefile
>>> +++ b/drivers/gpu/drm/i915/Makefile
>>> @@ -57,6 +57,7 @@ i915-y += i915_cmd_parser.o \  # general-purpose
>>> microcontroller (GuC) support  i915-y += intel_uc.o \
>>>  	  intel_guc_loader.o \
>>> +	  intel_huc_loader.o \
>>>  	  i915_guc_submission.o
>>>
>>>  # autogenerated null render state
>>> diff --git a/drivers/gpu/drm/i915/i915_drv.c
>>> b/drivers/gpu/drm/i915/i915_drv.c index 6428588..85a47c2 100644
>>> --- a/drivers/gpu/drm/i915/i915_drv.c
>>> +++ b/drivers/gpu/drm/i915/i915_drv.c
>>> @@ -600,6 +600,7 @@ static int i915_load_modeset_init(struct
>>> drm_device
>>*dev)
>>>  	if (ret)
>>>  		goto cleanup_irq;
>>>
>>> +	intel_huc_init(dev_priv);
>>>  	intel_guc_init(dev_priv);
>>>
>>>  	ret = i915_gem_init(dev_priv);
>>> @@ -627,6 +628,7 @@ static int i915_load_modeset_init(struct
>>> drm_device
>>*dev)
>>>  		DRM_ERROR("failed to idle hardware; continuing to unload!\n");
>>>  	i915_gem_fini(dev_priv);
>>>  cleanup_irq:
>>> +	intel_huc_fini(dev);
>>>  	intel_guc_fini(dev_priv);
>>>  	drm_irq_uninstall(dev);
>>>  	intel_teardown_gmbus(dev_priv);
>>> @@ -1313,7 +1315,7 @@ void i915_driver_unload(struct drm_device *dev)
>>>
>>>  	/* Flush any outstanding unpin_work. */
>>>  	drain_workqueue(dev_priv->wq);
>>> -
>>> +	intel_huc_fini(dev);
>>>  	intel_guc_fini(dev_priv);
>>>  	i915_gem_fini(dev_priv);
>>>  	intel_fbc_cleanup_cfb(dev_priv);
>>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>>> b/drivers/gpu/drm/i915/i915_drv.h index 1a91409..7ac7730 100644
>>> --- a/drivers/gpu/drm/i915/i915_drv.h
>>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>>> @@ -2147,6 +2147,7 @@ struct drm_i915_private {
>>>
>>>  	struct intel_gvt *gvt;
>>>
>>> +	struct intel_huc huc;
>>>  	struct intel_guc guc;
>>>
>>>  	struct intel_csr csr;
>>> @@ -2921,7 +2922,7 @@ intel_info(const struct drm_i915_private *dev_priv)
>>>  #define HAS_GUC(dev_priv)	((dev_priv)->info.has_guc)
>>>  #define HAS_GUC_UCODE(dev_priv)	(HAS_GUC(dev_priv))
>>>  #define HAS_GUC_SCHED(dev_priv)	(HAS_GUC(dev_priv))
>>> -
>>> +#define HAS_HUC_UCODE(dev_priv)	(HAS_GUC(dev_priv))
>>>  #define HAS_RESOURCE_STREAMER(dev_priv)
>>> ((dev_priv)->info.has_resource_streamer)
>>>
>>>  #define HAS_POOLED_EU(dev_priv)	((dev_priv)->info.has_pooled_eu)
>>> diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h
>>> b/drivers/gpu/drm/i915/i915_guc_reg.h
>>> index 5e638fc..f9829f6 100644
>>> --- a/drivers/gpu/drm/i915/i915_guc_reg.h
>>> +++ b/drivers/gpu/drm/i915/i915_guc_reg.h
>>> @@ -61,9 +61,12 @@
>>>  #define   DMA_ADDRESS_SPACE_GTT		  (8 << 16)
>>>  #define DMA_COPY_SIZE			_MMIO(0xc310)
>>>  #define DMA_CTRL			_MMIO(0xc314)
>>> +#define   HUC_UKERNEL			  (1<<9)
>>>  #define   UOS_MOVE			  (1<<4)
>>>  #define   START_DMA			  (1<<0)
>>>  #define DMA_GUC_WOPCM_OFFSET		_MMIO(0xc340)
>>> +#define   HUC_LOADING_AGENT_VCR		  (0<<1)
>>> +#define   HUC_LOADING_AGENT_GUC		  (1<<1)
>>>  #define   GUC_WOPCM_OFFSET_VALUE	  0x80000	/* 512KB */
>>>  #define GUC_MAX_IDLE_COUNT		_MMIO(0xC3E4)
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
>>> b/drivers/gpu/drm/i915/intel_guc_loader.c
>>> index 06e3e5c..8c77e94 100644
>>> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
>>> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
>>> @@ -309,8 +309,8 @@ static int guc_ucode_xfer_dma(struct
>>> drm_i915_private
>>*dev_priv,
>>>  	I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
>>>
>>>  	/* Finally start the DMA */
>>> -	I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE |
>>START_DMA));
>>> -
>>> +	I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE |
>>START_DMA) |
>>> +		_MASKED_BIT_DISABLE(HUC_UKERNEL));
>>>  	/*
>>>  	 * Wait for the DMA to complete & the GuC to start up.
>>>  	 * NB: Docs recommend not using the interrupt for completion.
>>> @@ -334,7 +334,7 @@ static int guc_ucode_xfer_dma(struct
>>> drm_i915_private
>>*dev_priv,
>>>  	return ret;
>>>  }
>>>
>>> -static u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
>>> +u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv)
>>>  {
>>>  	u32 wopcm_size = GUC_WOPCM_TOP;
>>>
>>> @@ -372,7 +372,7 @@ static int guc_ucode_xfer(struct drm_i915_private
>>*dev_priv)
>>>  	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
>>>
>>>  	/* init WOPCM */
>>> -	I915_WRITE(GUC_WOPCM_SIZE, guc_wopcm_size(dev_priv));
>>> +	I915_WRITE(GUC_WOPCM_SIZE, intel_guc_wopcm_size(dev_priv));
>>>  	I915_WRITE(DMA_GUC_WOPCM_OFFSET,
>>GUC_WOPCM_OFFSET_VALUE);
>>>
>>>  	/* Enable MIA caching. GuC clock gating is disabled. */ @@ -511,6
>>> +511,7 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
>>>  		if (err)
>>>  			goto fail;
>>>
>>> +		intel_huc_load(dev_priv);
>>>  		err = guc_ucode_xfer(dev_priv);
>>>  		if (!err)
>>>  			break;
>>> @@ -658,7 +659,7 @@ void intel_uc_fw_fetch(struct drm_i915_private
>>*dev_priv,
>>>  		size = uc_fw->header_size + uc_fw->ucode_size;
>>>
>>>  		/* Top 32k of WOPCM is reserved (8K stack + 24k RC6 context).
>>*/
>>> -		if (size > guc_wopcm_size(dev_priv)) {
>>> +		if (size > intel_guc_wopcm_size(dev_priv)) {
>>>  			DRM_ERROR("Firmware is too large to fit in
>>WOPCM\n");
>>>  			goto fail;
>>>  		}
>>> diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c
>>> b/drivers/gpu/drm/i915/intel_huc_loader.c
>>> new file mode 100644
>>> index 0000000..98d631c
>>> --- /dev/null
>>> +++ b/drivers/gpu/drm/i915/intel_huc_loader.c
>>> @@ -0,0 +1,263 @@
>>> +/*
>>> + * Copyright (c) 2016 Intel Corporation
>>> + *
>>> + * Permission is hereby granted, free of charge, to any person
>>> +obtaining a
>>> + * copy of this software and associated documentation files (the
>>> +"Software"),
>>> + * to deal in the Software without restriction, including without
>>> +limitation
>>> + * the rights to use, copy, modify, merge, publish, distribute,
>>> +sublicense,
>>> + * and/or sell copies of the Software, and to permit persons to whom
>>> +the
>>> + * Software is furnished to do so, subject to the following conditions:
>>> + *
>>> + * The above copyright notice and this permission notice (including
>>> +the next
>>> + * paragraph) shall be included in all copies or substantial
>>> +portions of the
>>> + * Software.
>>> + *
>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>>> +EXPRESS OR
>>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
>>> +MERCHANTABILITY,
>>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO
>>EVENT
>>> +SHALL
>>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
>>DAMAGES
>>> +OR OTHER
>>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>>> +ARISING
>>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>>> +OTHER DEALINGS
>>> + * IN THE SOFTWARE.
>>> + *
>>> + */
>>> +#include <linux/firmware.h>
>>> +#include "i915_drv.h"
>>> +#include "intel_uc.h"
>>> +
>>> +/**
>>> + * DOC: HuC Firmware
>>> + *
>>> + * Motivation:
>>> + * GEN9 introduces a new dedicated firmware for usage in media HEVC
>>> +(High
>>> + * Efficiency Video Coding) operations. Userspace can use the
>>> +firmware
>>> + * capabilities by adding HuC specific commands to batch buffers.
>>> + *
>>> + * Implementation:
>>> + * The same firmware loader is used as the GuC. However, the actual
>>> + * loading to HW is deferred until GEM initialization is done.
>>> + *
>>> + * Note that HuC firmware loading must be done before GuC loading.
>>> + */
>>> +
>>> +#define SKL_HUC_FW_MAJOR 01
>>> +#define SKL_HUC_FW_MINOR 07
>>> +#define SKL_BLD_NUM 1398
>>> +
>>> +#define HUC_FW_PATH(platform, major, minor, bld_num) \
>>> +	"i915/" __stringify(platform) "_huc_ver" __stringify(major) "_" \
>>> +	__stringify(minor) "_" __stringify(bld_num) ".bin"
>>> +
>>> +#define I915_SKL_HUC_UCODE HUC_FW_PATH(skl, SKL_HUC_FW_MAJOR, \
>>> +	SKL_HUC_FW_MINOR, SKL_BLD_NUM)
>>> +MODULE_FIRMWARE(I915_SKL_HUC_UCODE);
>>> +
>>> +/**
>>> + * huc_ucode_xfer() - DMA's the firmware
>>> + * @dev_priv: the drm device
>>> + *
>>> + * This function takes the gem object containing the firmware, sets
>>> +up the DMA
>>
>>Hmm, this function takes just dev_priv...
>
>Oops.... will change the comment.
>
>Anusha
>>
>>> + * engine MMIO, triggers the DMA operation and waits for it to finish.
>>> + *
>>> + * Transfer the firmware image to RAM for execution by the microcontroller.
>>> + *
>>> + * Return: 0 on success, non-zero on failure  */ static int
>>> +huc_ucode_xfer(struct drm_i915_private *dev_priv) {
>>> +	struct intel_uc_fw *huc_fw = &dev_priv->huc.fw;
>>> +	struct i915_vma *vma;
>>> +	unsigned long offset = 0;
>>> +	u32 size;
>>> +	int ret;
>>> +
>>> +	ret = i915_gem_object_set_to_gtt_domain(huc_fw->uc_fw_obj, false);
>>> +	if (ret) {
>>> +		DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
>>> +		return ret;
>>> +	}
>>> +
>>> +	vma = i915_gem_object_ggtt_pin(huc_fw->uc_fw_obj, NULL, 0, 0, 0);
>>> +	if (IS_ERR(vma)) {
>>> +		DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
>>> +		return PTR_ERR(vma);
>>> +	}
>>> +
>>> +	/* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
>>> +	I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
>>> +
>>> +	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
>>> +
>>> +	/* init WOPCM */
>>> +	I915_WRITE(GUC_WOPCM_SIZE, intel_guc_wopcm_size(dev_priv));
>>> +	I915_WRITE(DMA_GUC_WOPCM_OFFSET,
>>GUC_WOPCM_OFFSET_VALUE |
>>> +			HUC_LOADING_AGENT_GUC);
>>> +
>>> +	/* Set the source address for the uCode */
>>> +	offset = i915_ggtt_offset(vma) + huc_fw->header_offset;
>>> +	I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
>>> +	I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
>>> +
>>> +	/* Hardware doesn't look at destination address for HuC. Set it to 0,
>>> +	 * but still program the correct address space.
>>> +	 */
>>> +	I915_WRITE(DMA_ADDR_1_LOW, 0);
>>> +	I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
>>> +
>>> +	size = huc_fw->header_size + huc_fw->ucode_size;
>>> +	I915_WRITE(DMA_COPY_SIZE, size);
>>> +
>>> +	/* Start the DMA */
>>> +	I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(HUC_UKERNEL |
>>START_DMA));
>>> +
>>> +	/* Wait for DMA to finish */
>>> +	ret = wait_for((I915_READ(DMA_CTRL) & START_DMA) == 0, 100);
>>> +
>>> +	DRM_DEBUG_DRIVER("HuC DMA transfer wait over with ret %d\n", ret);
>>> +
>>> +	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
>>> +
>>> +	/*
>>> +	 * We keep the object pages for reuse during resume. But we can unpin it
>>> +	 * now that DMA has completed, so it doesn't continue to take up space.
>>> +	 */
>>> +	i915_vma_unpin(vma);
>>> +
>>> +	return ret;
>>> +}
>>> +
>>> +/**
>>> + * intel_huc_init() - initiate HuC firmware loading request
>>> + * @dev_priv: the drm_i915_private device
>>> + *
>>> + * Called early during driver load, but after GEM is initialised.
>>> +The loading
>>> + * will continue only when driver explicitly specify firmware name and
>version.
>>> + * All other cases are considered as INTEL_UC_FIRMWARE_NONE either
>>> +because HW
>>> + * is not capable or driver yet support it. And there will be no
>>> +error message
>>> + * for INTEL_UC_FIRMWARE_NONE cases.
>>> + *
>>> + * The DMA-copying to HW is done later when intel_huc_load() is called.
>>> + */
>>> +void intel_huc_init(struct drm_i915_private *dev_priv) {
>>> +	struct intel_huc *huc = &dev_priv->huc;
>>> +	struct intel_uc_fw *huc_fw = &huc->fw;
>>> +	const char *fw_path = NULL;
>>> +
>>> +	huc_fw->uc_fw_path = NULL;
>>> +	huc_fw->fetch_status = INTEL_UC_FIRMWARE_NONE;
>>> +	huc_fw->load_status = INTEL_UC_FIRMWARE_NONE;
>>> +	huc_fw->fw_type = INTEL_UC_FW_TYPE_HUC;
>>> +
>>> +	if (!HAS_HUC_UCODE(dev_priv))
>>> +		return;
>>> +
>>> +	if (IS_SKYLAKE(dev_priv)) {
>>> +		fw_path = I915_SKL_HUC_UCODE;
>>> +		huc_fw->major_ver_wanted = SKL_HUC_FW_MAJOR;
>>> +		huc_fw->minor_ver_wanted = SKL_HUC_FW_MINOR;
>>> +	}
>>> +
>>> +	huc_fw->uc_fw_path = fw_path;
>>> +	huc_fw->fetch_status = INTEL_UC_FIRMWARE_PENDING;
>>> +
>>> +	DRM_DEBUG_DRIVER("HuC firmware pending, path %s\n", fw_path);
>>> +
>>> +	intel_uc_fw_fetch(dev_priv, huc_fw); }
>>> +
>>> +/**
>>> + * intel_huc_load() - load HuC uCode to device
>>> + * @dev_priv: the drm_i915_private device
>>> + *
>>> + * Called from gem_init_hw() during driver loading and also after a GPU reset.
>>> + * Be note that HuC loading must be done before GuC loading.
>>> + *
>>> + * The firmware image should have already been fetched into memory
>>> +by the
>>> + * earlier call to intel_huc_init(), so here we need only check that
>>> + * is succeeded, and then transfer the image to the h/w.
>>> + *
>>> + * Return:	non-zero code on error
>>> + */
>>> +int intel_huc_load(struct drm_i915_private *dev_priv) {
>>> +	struct intel_uc_fw *huc_fw = &dev_priv->huc.fw;
>>> +	int err;
>>> +
>>> +	if (huc_fw->fetch_status == INTEL_UC_FIRMWARE_NONE)
>>> +		return 0;
>>> +
>>> +	DRM_DEBUG_DRIVER("%s fw status: fetch %s, load %s\n",
>>> +		huc_fw->uc_fw_path,
>>> +		intel_uc_fw_status_repr(huc_fw->fetch_status),
>>> +		intel_uc_fw_status_repr(huc_fw->load_status));
>>> +
>>> +	if (huc_fw->fetch_status == INTEL_UC_FIRMWARE_SUCCESS &&
>>> +	    huc_fw->load_status == INTEL_UC_FIRMWARE_FAIL)
>>> +		return -ENOEXEC;
>>> +
>>> +	huc_fw->load_status = INTEL_UC_FIRMWARE_PENDING;
>>> +
>>> +	switch (huc_fw->fetch_status) {
>>> +	case INTEL_UC_FIRMWARE_FAIL:
>>> +		/* something went wrong :( */
>>> +		err = -EIO;
>>> +		goto fail;
>>> +
>>> +	case INTEL_UC_FIRMWARE_NONE:
>>> +	case INTEL_UC_FIRMWARE_PENDING:
>>> +	default:
>>> +		/* "can't happen" */
>>> +		WARN_ONCE(1, "HuC fw %s invalid fetch_status %s [%d]\n",
>>> +			huc_fw->uc_fw_path,
>>> +			intel_uc_fw_status_repr(huc_fw->fetch_status),
>>> +			huc_fw->fetch_status);
>>> +		err = -ENXIO;
>>> +		goto fail;
>>> +
>>> +	case INTEL_UC_FIRMWARE_SUCCESS:
>>> +		break;
>>> +	}
>>> +
>>> +	err = huc_ucode_xfer(dev_priv);
>>> +	if (err)
>>> +		goto fail;
>>> +
>>> +	huc_fw->load_status = INTEL_UC_FIRMWARE_SUCCESS;
>>> +
>>> +	DRM_DEBUG_DRIVER("%s fw status: fetch %s, load %s\n",
>>> +		huc_fw->uc_fw_path,
>>> +		intel_uc_fw_status_repr(huc_fw->fetch_status),
>>> +		intel_uc_fw_status_repr(huc_fw->load_status));
>>
>>Hmm, this message will always display "fetch SUCCESS load SUCCESS"
>>as all other cases all handled as fail below... is it expected ?

Yes. I think we need a message for the case when there is no failure.

>>> +
>>> +	return 0;
>>> +
>>> +fail:
>>> +	if (huc_fw->load_status == INTEL_UC_FIRMWARE_PENDING)
>>> +		huc_fw->load_status = INTEL_UC_FIRMWARE_FAIL;
>>> +
>>> +	DRM_ERROR("Failed to complete HuC uCode load with ret %d\n", err);
>>> +
>>> +	return err;
>>> +}
>>> +
>>> +/**
>>> + * intel_huc_fini() - clean up resources allocated for HuC
>>> + * @dev: the drm device
>>> + *
>>> + * Cleans up by releasing the huc firmware GEM obj.
>>> + */
>>> +void intel_huc_fini(struct drm_device *dev)
>>
>>Why this function takes dev? All other functions take dev_priv.

Last I heard this was the only function that took dev and there some WIP before we make it take dev_priv.
Arek, can we change this now?

>>Michal
>>
>>> +{
>>> +	struct drm_i915_private *dev_priv = to_i915(dev);
>>> +	struct intel_uc_fw *huc_fw = &dev_priv->huc.fw;
>>> +
>>> +	mutex_lock(&dev->struct_mutex);
>>> +	if (huc_fw->uc_fw_obj)
>>> +		i915_gem_object_put(huc_fw->uc_fw_obj);
>>> +	huc_fw->uc_fw_obj = NULL;
>>> +	mutex_unlock(&dev->struct_mutex);
>>> +
>>> +	huc_fw->fetch_status = INTEL_UC_FIRMWARE_NONE; }
>>> +
>>> diff --git a/drivers/gpu/drm/i915/intel_uc.h
>>> b/drivers/gpu/drm/i915/intel_uc.h index ad140e2..57aef56 100644
>>> --- a/drivers/gpu/drm/i915/intel_uc.h
>>> +++ b/drivers/gpu/drm/i915/intel_uc.h
>>> @@ -24,6 +24,9 @@
>>>  #ifndef _INTEL_UC_H_
>>>  #define _INTEL_UC_H_
>>>
>>> +#define HUC_STATUS2             _MMIO(0xD3B0)
>>> +#define   HUC_FW_VERIFIED       (1<<7)
>>> +
>>>  #include "intel_guc_fwif.h"
>>>  #include "i915_guc_reg.h"
>>>  #include "intel_ringbuffer.h"
>>> @@ -174,6 +177,13 @@ struct intel_guc {
>>>  	struct mutex send_mutex;
>>>  };
>>>
>>> +struct intel_huc {
>>> +	/* Generic uC firmware management */
>>> +	struct intel_uc_fw fw;
>>> +
>>> +	/* HuC-specific additions */
>>> +};
>>> +
>>>  /* intel_uc.c */
>>>  void intel_uc_init_early(struct drm_i915_private *dev_priv);  bool
>>> intel_guc_recv(struct drm_i915_private *dev_priv, u32 *status); @@
>>> -190,6 +200,9 @@ extern void intel_guc_fini(struct drm_i915_private
>>> *dev_priv);  extern const char *intel_uc_fw_status_repr(enum
>>> intel_uc_fw_status status);  extern int intel_guc_suspend(struct
>>> drm_i915_private *dev_priv);  extern int intel_guc_resume(struct
>>> drm_i915_private *dev_priv);
>>> +void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
>>> +	struct intel_uc_fw *uc_fw);
>>> +u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv);
>>>
>>>  /* i915_guc_submission.c */
>>>  int i915_guc_submission_init(struct drm_i915_private *dev_priv); @@
>>> -204,4 +217,9 @@ void i915_guc_register(struct drm_i915_private
>>> *dev_priv);  void i915_guc_unregister(struct drm_i915_private
>>> *dev_priv);  int i915_guc_log_control(struct drm_i915_private
>>> *dev_priv, u64 control_val);
>>>
>>> +/* intel_huc_loader.c */
>>> +void intel_huc_init(struct drm_i915_private *dev_priv); void
>>> +intel_huc_fini(struct drm_device *dev); int intel_huc_load(struct
>>> +drm_i915_private *dev_priv);
>>> +
>>>  #endif
>>> --
>>> 2.7.4
>>>
>>> _______________________________________________
>>> Intel-gfx mailing list
>>> Intel-gfx@lists.freedesktop.org
>>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 7/8] drm/i915/huc: Support HuC authentication

[Srivatsa, Anusha]

>-----Original Message-----
>From: Chris Wilson [mailto:chris@chris-wilson.co.uk]
>Sent: Thursday, December 22, 2016 3:30 PM
>To: Srivatsa, Anusha <anusha.srivatsa@intel.com>
>Cc: intel-gfx@lists.freedesktop.org; Alex Dai <yu.dai@intel.com>; Peter Antoine
><peter.antoine@intel.com>
>Subject: Re: [Intel-gfx] [PATCH 7/8] drm/i915/huc: Support HuC authentication
>
>On Thu, Dec 22, 2016 at 03:12:23PM -0800, Anusha Srivatsa wrote:
>> +void intel_guc_auth_huc(struct drm_i915_private *dev_priv) {
>> +	struct intel_guc *guc = &dev_priv->guc;
>> +	struct intel_huc *huc = &dev_priv->huc;
>> +	struct i915_vma *vma;
>> +	int ret;
>> +	u32 data[2];
>> +
>> +	/* Bypass the case where there is no HuC firmware */
>> +	if (huc->fw.fetch_status == INTEL_UC_FIRMWARE_NONE ||
>> +		huc->fw.load_status == INTEL_UC_FIRMWARE_NONE)
>> +		return;
>> +
>> +	if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS) {
>> +		DRM_ERROR("HuC: GuC fw wasn't loaded. Can't
>authenticate\n");
>> +		return;
>> +	}
>> +
>> +	if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS) {
>> +		DRM_ERROR("HuC: fw wasn't loaded. Nothing to
>authenticate\n");
>> +		return;
>> +	}
>> +
>> +	vma = i915_gem_object_ggtt_pin(huc->fw.uc_fw_obj, NULL, 0, 0, 0);
>> +	if (IS_ERR(vma)) {
>> +		DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
>> +		return;
>> +	}
>> +
>> +
>> +	/* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
>> +	I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
>
>Still working on stopping this from frequently popping up in code outside of the
>GTT routines.
So, basically beautify the code such that the GTT routines do not pop out in non GTT parts of code. Correct? 
>
>> +	/* Specify auth action and where public signature is. */
>> +	data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC;
>> +	data[1] = i915_ggtt_offset(vma) + huc->fw.rsa_offset;
>> +
>> +	ret = intel_guc_send(guc, data, ARRAY_SIZE(data));
>> +	if (ret) {
>> +		DRM_ERROR("HuC: GuC did not ack Auth request\n");
>> +		goto out;
>> +	}
>> +
>> +	/* Check authentication status, it should be done by now */
>> +	ret = wait_for((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) > 0,
>50);
>
>ret = intel_wait_for_register(dev_priv,
>			      HUC_STATUS2,
>			      HUC_FW_VERIFIED,
>			      HUC_FW_VERIFIED,
>			      50);
>
>wait_for() is a rather large macro, and intel_wait_for_register() employs the spin
>then sleep optimisation for quick responses.

Thankyou for bringing this to my notice. 

Anusha

>-Chris
>
>--
>Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 3/8] drm/i915/huc: Add HuC fw loading support

[Arkadiusz Hiler]

On Tue, Jan 03, 2017 at 06:59:11PM +0000, Srivatsa, Anusha wrote:
> 
> 
> >-----Original Message-----
> >From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of
> >Srivatsa, Anusha
> >Sent: Monday, January 2, 2017 4:09 PM
> >To: Wajdeczko, Michal <Michal.Wajdeczko@intel.com>
> >Cc: intel-gfx@lists.freedesktop.org; Alex Dai <yu.dai@intel.com>; Peter Antoine
> ><peter.antoine@intel.com>
> >Subject: Re: [Intel-gfx] [PATCH 3/8] drm/i915/huc: Add HuC fw loading support
> >
> >
> >
> >>-----Original Message-----
> >>From: Wajdeczko, Michal
> >>Sent: Tuesday, December 27, 2016 9:51 AM
> >>To: Srivatsa, Anusha <anusha.srivatsa@intel.com>
> >>Cc: intel-gfx@lists.freedesktop.org; Alex Dai <yu.dai@intel.com>; Peter
> >>Antoine <peter.antoine@intel.com>
> >>Subject: Re: [Intel-gfx] [PATCH 3/8] drm/i915/huc: Add HuC fw loading
> >>support
> >>
> >>On Thu, Dec 22, 2016 at 03:12:19PM -0800, Anusha Srivatsa wrote:
> >>> The HuC loading process is similar to GuC. The intel_uc_fw_fetch() is
> >>> used for both cases.
> >>>
> >>> HuC loading needs to be before GuC loading. The WOPCM setting must be
> >>> done early before loading any of them.
> >>>
> >>> v2: rebased on-top of drm-intel-nightly.
> >>>     removed if(HAS_GUC()) before the guc call. (D.Gordon)
> >>>     update huc_version number of format.
> >>> v3: rebased to drm-intel-nightly, changed the file name format to
> >>>     match the one in the huc package.
> >>>     Changed dev->dev_private to to_i915()
> >>> v4: moved function back to where it was.
> >>>     change wait_for_atomic to wait_for.
> >>> v5: rebased + comment changes.
> >>> v7: rebased.
> >>> v8: rebased.
> >>> v9: rebased. Changed the year in the copyright message to reflect the
> >>> right year.Correct the comments,remove the unwanted WARN message,
> >>> replace drm_gem_object_unreference() with i915_gem_object_put().Make
> >>> the prototypes in intel_huc.h non-extern.
> >>> v10: rebased. Update the file construction done by HuC. It is similar
> >>> to GuC.Adopted the approach used in-
> >>> https://patchwork.freedesktop.org/patch/104355/ <Tvrtko Ursulin>
> >>> v11: Fix warnings remove old declaration
> >>> v12: Change dev to dev_priv in macro definition.
> >>> Corrected comments.
> >>> v13: rebased.
> >>> v14: rebased on top of drm-tip
> >>> v15: rebased. Updated functions intel_huc_load(),intel_huc_init() and
> >>> intel_uc_fw_fetch() to accept dev_priv instead of dev. Moved contents
> >>> of intel_huc.h to intel_uc.h
> >>> v16: change SKL_FW_ to SKL_HUC_FW_. Add intel_ prefix to
> >>guc_wopcm_size().
> >>> Remove unwanted checks in intel_uc.h. Rename huc_fw in struct
> >>> intel_huc to simply fw to avoid redundency.
> >>> v17: rebased.
> >>>
> >>> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >>> Tested-by: Xiang Haihao <haihao.xiang@intel.com>
> >>> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> >>> Signed-off-by: Alex Dai <yu.dai@intel.com>
> >>> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> >>> ---
> >>>  drivers/gpu/drm/i915/Makefile           |   1 +
> >>>  drivers/gpu/drm/i915/i915_drv.c         |   4 +-
> >>>  drivers/gpu/drm/i915/i915_drv.h         |   3 +-
> >>>  drivers/gpu/drm/i915/i915_guc_reg.h     |   3 +
> >>>  drivers/gpu/drm/i915/intel_guc_loader.c |  11 +-
> >>> drivers/gpu/drm/i915/intel_huc_loader.c | 263
> >>++++++++++++++++++++++++++++++++
> >>>  drivers/gpu/drm/i915/intel_uc.h         |  18 +++
> >>>  7 files changed, 296 insertions(+), 7 deletions(-)  create mode
> >>> 100644 drivers/gpu/drm/i915/intel_huc_loader.c
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/Makefile
> >>> b/drivers/gpu/drm/i915/Makefile index 5196509..45ae124 100644
> >>> --- a/drivers/gpu/drm/i915/Makefile
> >>> +++ b/drivers/gpu/drm/i915/Makefile
> >>> @@ -57,6 +57,7 @@ i915-y += i915_cmd_parser.o \  # general-purpose
> >>> microcontroller (GuC) support  i915-y += intel_uc.o \
> >>>  	  intel_guc_loader.o \
> >>> +	  intel_huc_loader.o \
> >>>  	  i915_guc_submission.o
> >>>
> >>>  # autogenerated null render state
> >>> diff --git a/drivers/gpu/drm/i915/i915_drv.c
> >>> b/drivers/gpu/drm/i915/i915_drv.c index 6428588..85a47c2 100644
> >>> --- a/drivers/gpu/drm/i915/i915_drv.c
> >>> +++ b/drivers/gpu/drm/i915/i915_drv.c
> >>> @@ -600,6 +600,7 @@ static int i915_load_modeset_init(struct
> >>> drm_device
> >>*dev)
> >>>  	if (ret)
> >>>  		goto cleanup_irq;
> >>>
> >>> +	intel_huc_init(dev_priv);
> >>>  	intel_guc_init(dev_priv);
> >>>
> >>>  	ret = i915_gem_init(dev_priv);
> >>> @@ -627,6 +628,7 @@ static int i915_load_modeset_init(struct
> >>> drm_device
> >>*dev)
> >>>  		DRM_ERROR("failed to idle hardware; continuing to unload!\n");
> >>>  	i915_gem_fini(dev_priv);
> >>>  cleanup_irq:
> >>> +	intel_huc_fini(dev);
> >>>  	intel_guc_fini(dev_priv);
> >>>  	drm_irq_uninstall(dev);
> >>>  	intel_teardown_gmbus(dev_priv);
> >>> @@ -1313,7 +1315,7 @@ void i915_driver_unload(struct drm_device *dev)
> >>>
> >>>  	/* Flush any outstanding unpin_work. */
> >>>  	drain_workqueue(dev_priv->wq);
> >>> -
> >>> +	intel_huc_fini(dev);
> >>>  	intel_guc_fini(dev_priv);
> >>>  	i915_gem_fini(dev_priv);
> >>>  	intel_fbc_cleanup_cfb(dev_priv);
> >>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> >>> b/drivers/gpu/drm/i915/i915_drv.h index 1a91409..7ac7730 100644
> >>> --- a/drivers/gpu/drm/i915/i915_drv.h
> >>> +++ b/drivers/gpu/drm/i915/i915_drv.h
> >>> @@ -2147,6 +2147,7 @@ struct drm_i915_private {
> >>>
> >>>  	struct intel_gvt *gvt;
> >>>
> >>> +	struct intel_huc huc;
> >>>  	struct intel_guc guc;
> >>>
> >>>  	struct intel_csr csr;
> >>> @@ -2921,7 +2922,7 @@ intel_info(const struct drm_i915_private *dev_priv)
> >>>  #define HAS_GUC(dev_priv)	((dev_priv)->info.has_guc)
> >>>  #define HAS_GUC_UCODE(dev_priv)	(HAS_GUC(dev_priv))
> >>>  #define HAS_GUC_SCHED(dev_priv)	(HAS_GUC(dev_priv))
> >>> -
> >>> +#define HAS_HUC_UCODE(dev_priv)	(HAS_GUC(dev_priv))
> >>>  #define HAS_RESOURCE_STREAMER(dev_priv)
> >>> ((dev_priv)->info.has_resource_streamer)
> >>>
> >>>  #define HAS_POOLED_EU(dev_priv)	((dev_priv)->info.has_pooled_eu)
> >>> diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h
> >>> b/drivers/gpu/drm/i915/i915_guc_reg.h
> >>> index 5e638fc..f9829f6 100644
> >>> --- a/drivers/gpu/drm/i915/i915_guc_reg.h
> >>> +++ b/drivers/gpu/drm/i915/i915_guc_reg.h
> >>> @@ -61,9 +61,12 @@
> >>>  #define   DMA_ADDRESS_SPACE_GTT		  (8 << 16)
> >>>  #define DMA_COPY_SIZE			_MMIO(0xc310)
> >>>  #define DMA_CTRL			_MMIO(0xc314)
> >>> +#define   HUC_UKERNEL			  (1<<9)
> >>>  #define   UOS_MOVE			  (1<<4)
> >>>  #define   START_DMA			  (1<<0)
> >>>  #define DMA_GUC_WOPCM_OFFSET		_MMIO(0xc340)
> >>> +#define   HUC_LOADING_AGENT_VCR		  (0<<1)
> >>> +#define   HUC_LOADING_AGENT_GUC		  (1<<1)
> >>>  #define   GUC_WOPCM_OFFSET_VALUE	  0x80000	/* 512KB */
> >>>  #define GUC_MAX_IDLE_COUNT		_MMIO(0xC3E4)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
> >>> b/drivers/gpu/drm/i915/intel_guc_loader.c
> >>> index 06e3e5c..8c77e94 100644
> >>> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> >>> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> >>> @@ -309,8 +309,8 @@ static int guc_ucode_xfer_dma(struct
> >>> drm_i915_private
> >>*dev_priv,
> >>>  	I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
> >>>
> >>>  	/* Finally start the DMA */
> >>> -	I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE |
> >>START_DMA));
> >>> -
> >>> +	I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE |
> >>START_DMA) |
> >>> +		_MASKED_BIT_DISABLE(HUC_UKERNEL));
> >>>  	/*
> >>>  	 * Wait for the DMA to complete & the GuC to start up.
> >>>  	 * NB: Docs recommend not using the interrupt for completion.
> >>> @@ -334,7 +334,7 @@ static int guc_ucode_xfer_dma(struct
> >>> drm_i915_private
> >>*dev_priv,
> >>>  	return ret;
> >>>  }
> >>>
> >>> -static u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
> >>> +u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv)
> >>>  {
> >>>  	u32 wopcm_size = GUC_WOPCM_TOP;
> >>>
> >>> @@ -372,7 +372,7 @@ static int guc_ucode_xfer(struct drm_i915_private
> >>*dev_priv)
> >>>  	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> >>>
> >>>  	/* init WOPCM */
> >>> -	I915_WRITE(GUC_WOPCM_SIZE, guc_wopcm_size(dev_priv));
> >>> +	I915_WRITE(GUC_WOPCM_SIZE, intel_guc_wopcm_size(dev_priv));
> >>>  	I915_WRITE(DMA_GUC_WOPCM_OFFSET,
> >>GUC_WOPCM_OFFSET_VALUE);
> >>>
> >>>  	/* Enable MIA caching. GuC clock gating is disabled. */ @@ -511,6
> >>> +511,7 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
> >>>  		if (err)
> >>>  			goto fail;
> >>>
> >>> +		intel_huc_load(dev_priv);
> >>>  		err = guc_ucode_xfer(dev_priv);
> >>>  		if (!err)
> >>>  			break;
> >>> @@ -658,7 +659,7 @@ void intel_uc_fw_fetch(struct drm_i915_private
> >>*dev_priv,
> >>>  		size = uc_fw->header_size + uc_fw->ucode_size;
> >>>
> >>>  		/* Top 32k of WOPCM is reserved (8K stack + 24k RC6 context).
> >>*/
> >>> -		if (size > guc_wopcm_size(dev_priv)) {
> >>> +		if (size > intel_guc_wopcm_size(dev_priv)) {
> >>>  			DRM_ERROR("Firmware is too large to fit in
> >>WOPCM\n");
> >>>  			goto fail;
> >>>  		}
> >>> diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c
> >>> b/drivers/gpu/drm/i915/intel_huc_loader.c
> >>> new file mode 100644
> >>> index 0000000..98d631c
> >>> --- /dev/null
> >>> +++ b/drivers/gpu/drm/i915/intel_huc_loader.c
> >>> @@ -0,0 +1,263 @@
> >>> +/*
> >>> + * Copyright (c) 2016 Intel Corporation
> >>> + *
> >>> + * Permission is hereby granted, free of charge, to any person
> >>> +obtaining a
> >>> + * copy of this software and associated documentation files (the
> >>> +"Software"),
> >>> + * to deal in the Software without restriction, including without
> >>> +limitation
> >>> + * the rights to use, copy, modify, merge, publish, distribute,
> >>> +sublicense,
> >>> + * and/or sell copies of the Software, and to permit persons to whom
> >>> +the
> >>> + * Software is furnished to do so, subject to the following conditions:
> >>> + *
> >>> + * The above copyright notice and this permission notice (including
> >>> +the next
> >>> + * paragraph) shall be included in all copies or substantial
> >>> +portions of the
> >>> + * Software.
> >>> + *
> >>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> >>> +EXPRESS OR
> >>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> >>> +MERCHANTABILITY,
> >>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO
> >>EVENT
> >>> +SHALL
> >>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
> >>DAMAGES
> >>> +OR OTHER
> >>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> >>> +ARISING
> >>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> >>> +OTHER DEALINGS
> >>> + * IN THE SOFTWARE.
> >>> + *
> >>> + */
> >>> +#include <linux/firmware.h>
> >>> +#include "i915_drv.h"
> >>> +#include "intel_uc.h"
> >>> +
> >>> +/**
> >>> + * DOC: HuC Firmware
> >>> + *
> >>> + * Motivation:
> >>> + * GEN9 introduces a new dedicated firmware for usage in media HEVC
> >>> +(High
> >>> + * Efficiency Video Coding) operations. Userspace can use the
> >>> +firmware
> >>> + * capabilities by adding HuC specific commands to batch buffers.
> >>> + *
> >>> + * Implementation:
> >>> + * The same firmware loader is used as the GuC. However, the actual
> >>> + * loading to HW is deferred until GEM initialization is done.
> >>> + *
> >>> + * Note that HuC firmware loading must be done before GuC loading.
> >>> + */
> >>> +
> >>> +#define SKL_HUC_FW_MAJOR 01
> >>> +#define SKL_HUC_FW_MINOR 07
> >>> +#define SKL_BLD_NUM 1398
> >>> +
> >>> +#define HUC_FW_PATH(platform, major, minor, bld_num) \
> >>> +	"i915/" __stringify(platform) "_huc_ver" __stringify(major) "_" \
> >>> +	__stringify(minor) "_" __stringify(bld_num) ".bin"
> >>> +
> >>> +#define I915_SKL_HUC_UCODE HUC_FW_PATH(skl, SKL_HUC_FW_MAJOR, \
> >>> +	SKL_HUC_FW_MINOR, SKL_BLD_NUM)
> >>> +MODULE_FIRMWARE(I915_SKL_HUC_UCODE);
> >>> +
> >>> +/**
> >>> + * huc_ucode_xfer() - DMA's the firmware
> >>> + * @dev_priv: the drm device
> >>> + *
> >>> + * This function takes the gem object containing the firmware, sets
> >>> +up the DMA
> >>
> >>Hmm, this function takes just dev_priv...
> >
> >Oops.... will change the comment.
> >
> >Anusha
> >>
> >>> + * engine MMIO, triggers the DMA operation and waits for it to finish.
> >>> + *
> >>> + * Transfer the firmware image to RAM for execution by the microcontroller.
> >>> + *
> >>> + * Return: 0 on success, non-zero on failure  */ static int
> >>> +huc_ucode_xfer(struct drm_i915_private *dev_priv) {
> >>> +	struct intel_uc_fw *huc_fw = &dev_priv->huc.fw;
> >>> +	struct i915_vma *vma;
> >>> +	unsigned long offset = 0;
> >>> +	u32 size;
> >>> +	int ret;
> >>> +
> >>> +	ret = i915_gem_object_set_to_gtt_domain(huc_fw->uc_fw_obj, false);
> >>> +	if (ret) {
> >>> +		DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
> >>> +		return ret;
> >>> +	}
> >>> +
> >>> +	vma = i915_gem_object_ggtt_pin(huc_fw->uc_fw_obj, NULL, 0, 0, 0);
> >>> +	if (IS_ERR(vma)) {
> >>> +		DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
> >>> +		return PTR_ERR(vma);
> >>> +	}
> >>> +
> >>> +	/* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
> >>> +	I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
> >>> +
> >>> +	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> >>> +
> >>> +	/* init WOPCM */
> >>> +	I915_WRITE(GUC_WOPCM_SIZE, intel_guc_wopcm_size(dev_priv));
> >>> +	I915_WRITE(DMA_GUC_WOPCM_OFFSET,
> >>GUC_WOPCM_OFFSET_VALUE |
> >>> +			HUC_LOADING_AGENT_GUC);
> >>> +
> >>> +	/* Set the source address for the uCode */
> >>> +	offset = i915_ggtt_offset(vma) + huc_fw->header_offset;
> >>> +	I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
> >>> +	I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
> >>> +
> >>> +	/* Hardware doesn't look at destination address for HuC. Set it to 0,
> >>> +	 * but still program the correct address space.
> >>> +	 */
> >>> +	I915_WRITE(DMA_ADDR_1_LOW, 0);
> >>> +	I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
> >>> +
> >>> +	size = huc_fw->header_size + huc_fw->ucode_size;
> >>> +	I915_WRITE(DMA_COPY_SIZE, size);
> >>> +
> >>> +	/* Start the DMA */
> >>> +	I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(HUC_UKERNEL |
> >>START_DMA));
> >>> +
> >>> +	/* Wait for DMA to finish */
> >>> +	ret = wait_for((I915_READ(DMA_CTRL) & START_DMA) == 0, 100);
> >>> +
> >>> +	DRM_DEBUG_DRIVER("HuC DMA transfer wait over with ret %d\n", ret);
> >>> +
> >>> +	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> >>> +
> >>> +	/*
> >>> +	 * We keep the object pages for reuse during resume. But we can unpin it
> >>> +	 * now that DMA has completed, so it doesn't continue to take up space.
> >>> +	 */
> >>> +	i915_vma_unpin(vma);
> >>> +
> >>> +	return ret;
> >>> +}
> >>> +
> >>> +/**
> >>> + * intel_huc_init() - initiate HuC firmware loading request
> >>> + * @dev_priv: the drm_i915_private device
> >>> + *
> >>> + * Called early during driver load, but after GEM is initialised.
> >>> +The loading
> >>> + * will continue only when driver explicitly specify firmware name and
> >version.
> >>> + * All other cases are considered as INTEL_UC_FIRMWARE_NONE either
> >>> +because HW
> >>> + * is not capable or driver yet support it. And there will be no
> >>> +error message
> >>> + * for INTEL_UC_FIRMWARE_NONE cases.
> >>> + *
> >>> + * The DMA-copying to HW is done later when intel_huc_load() is called.
> >>> + */
> >>> +void intel_huc_init(struct drm_i915_private *dev_priv) {
> >>> +	struct intel_huc *huc = &dev_priv->huc;
> >>> +	struct intel_uc_fw *huc_fw = &huc->fw;
> >>> +	const char *fw_path = NULL;
> >>> +
> >>> +	huc_fw->uc_fw_path = NULL;
> >>> +	huc_fw->fetch_status = INTEL_UC_FIRMWARE_NONE;
> >>> +	huc_fw->load_status = INTEL_UC_FIRMWARE_NONE;
> >>> +	huc_fw->fw_type = INTEL_UC_FW_TYPE_HUC;
> >>> +
> >>> +	if (!HAS_HUC_UCODE(dev_priv))
> >>> +		return;
> >>> +
> >>> +	if (IS_SKYLAKE(dev_priv)) {
> >>> +		fw_path = I915_SKL_HUC_UCODE;
> >>> +		huc_fw->major_ver_wanted = SKL_HUC_FW_MAJOR;
> >>> +		huc_fw->minor_ver_wanted = SKL_HUC_FW_MINOR;
> >>> +	}
> >>> +
> >>> +	huc_fw->uc_fw_path = fw_path;
> >>> +	huc_fw->fetch_status = INTEL_UC_FIRMWARE_PENDING;
> >>> +
> >>> +	DRM_DEBUG_DRIVER("HuC firmware pending, path %s\n", fw_path);
> >>> +
> >>> +	intel_uc_fw_fetch(dev_priv, huc_fw); }
> >>> +
> >>> +/**
> >>> + * intel_huc_load() - load HuC uCode to device
> >>> + * @dev_priv: the drm_i915_private device
> >>> + *
> >>> + * Called from gem_init_hw() during driver loading and also after a GPU reset.
> >>> + * Be note that HuC loading must be done before GuC loading.
> >>> + *
> >>> + * The firmware image should have already been fetched into memory
> >>> +by the
> >>> + * earlier call to intel_huc_init(), so here we need only check that
> >>> + * is succeeded, and then transfer the image to the h/w.
> >>> + *
> >>> + * Return:	non-zero code on error
> >>> + */
> >>> +int intel_huc_load(struct drm_i915_private *dev_priv) {
> >>> +	struct intel_uc_fw *huc_fw = &dev_priv->huc.fw;
> >>> +	int err;
> >>> +
> >>> +	if (huc_fw->fetch_status == INTEL_UC_FIRMWARE_NONE)
> >>> +		return 0;
> >>> +
> >>> +	DRM_DEBUG_DRIVER("%s fw status: fetch %s, load %s\n",
> >>> +		huc_fw->uc_fw_path,
> >>> +		intel_uc_fw_status_repr(huc_fw->fetch_status),
> >>> +		intel_uc_fw_status_repr(huc_fw->load_status));
> >>> +
> >>> +	if (huc_fw->fetch_status == INTEL_UC_FIRMWARE_SUCCESS &&
> >>> +	    huc_fw->load_status == INTEL_UC_FIRMWARE_FAIL)
> >>> +		return -ENOEXEC;
> >>> +
> >>> +	huc_fw->load_status = INTEL_UC_FIRMWARE_PENDING;
> >>> +
> >>> +	switch (huc_fw->fetch_status) {
> >>> +	case INTEL_UC_FIRMWARE_FAIL:
> >>> +		/* something went wrong :( */
> >>> +		err = -EIO;
> >>> +		goto fail;
> >>> +
> >>> +	case INTEL_UC_FIRMWARE_NONE:
> >>> +	case INTEL_UC_FIRMWARE_PENDING:
> >>> +	default:
> >>> +		/* "can't happen" */
> >>> +		WARN_ONCE(1, "HuC fw %s invalid fetch_status %s [%d]\n",
> >>> +			huc_fw->uc_fw_path,
> >>> +			intel_uc_fw_status_repr(huc_fw->fetch_status),
> >>> +			huc_fw->fetch_status);
> >>> +		err = -ENXIO;
> >>> +		goto fail;
> >>> +
> >>> +	case INTEL_UC_FIRMWARE_SUCCESS:
> >>> +		break;
> >>> +	}
> >>> +
> >>> +	err = huc_ucode_xfer(dev_priv);
> >>> +	if (err)
> >>> +		goto fail;
> >>> +
> >>> +	huc_fw->load_status = INTEL_UC_FIRMWARE_SUCCESS;
> >>> +
> >>> +	DRM_DEBUG_DRIVER("%s fw status: fetch %s, load %s\n",
> >>> +		huc_fw->uc_fw_path,
> >>> +		intel_uc_fw_status_repr(huc_fw->fetch_status),
> >>> +		intel_uc_fw_status_repr(huc_fw->load_status));
> >>
> >>Hmm, this message will always display "fetch SUCCESS load SUCCESS"
> >>as all other cases all handled as fail below... is it expected ?
> 
> Yes. I think we need a message for the case when there is no failure.
> 
> >>> +
> >>> +	return 0;
> >>> +
> >>> +fail:
> >>> +	if (huc_fw->load_status == INTEL_UC_FIRMWARE_PENDING)
> >>> +		huc_fw->load_status = INTEL_UC_FIRMWARE_FAIL;
> >>> +
> >>> +	DRM_ERROR("Failed to complete HuC uCode load with ret %d\n", err);
> >>> +
> >>> +	return err;
> >>> +}
> >>> +
> >>> +/**
> >>> + * intel_huc_fini() - clean up resources allocated for HuC
> >>> + * @dev: the drm device
> >>> + *
> >>> + * Cleans up by releasing the huc firmware GEM obj.
> >>> + */
> >>> +void intel_huc_fini(struct drm_device *dev)
> >>
> >>Why this function takes dev? All other functions take dev_priv.
> 
> Last I heard this was the only function that took dev and there some WIP before we make it take dev_priv.
> Arek, can we change this now?

IIRC the refactoring that happened changed dev to dev_priv everywhere
where the latter was used exclusively. This patchset was changed
accordingly and this function was left with dev, as it uses it for lock
access.

But I see your point with being consistent.

> >>Michal
> >>
> >>> +{
> >>> +	struct drm_i915_private *dev_priv = to_i915(dev);
> >>> +	struct intel_uc_fw *huc_fw = &dev_priv->huc.fw;
> >>> +
> >>> +	mutex_lock(&dev->struct_mutex);
> >>> +	if (huc_fw->uc_fw_obj)
> >>> +		i915_gem_object_put(huc_fw->uc_fw_obj);
> >>> +	huc_fw->uc_fw_obj = NULL;
> >>> +	mutex_unlock(&dev->struct_mutex);
> >>> +
> >>> +	huc_fw->fetch_status = INTEL_UC_FIRMWARE_NONE; }
> >>> +
> >>> diff --git a/drivers/gpu/drm/i915/intel_uc.h
> >>> b/drivers/gpu/drm/i915/intel_uc.h index ad140e2..57aef56 100644
> >>> --- a/drivers/gpu/drm/i915/intel_uc.h
> >>> +++ b/drivers/gpu/drm/i915/intel_uc.h
> >>> @@ -24,6 +24,9 @@
> >>>  #ifndef _INTEL_UC_H_
> >>>  #define _INTEL_UC_H_
> >>>
> >>> +#define HUC_STATUS2             _MMIO(0xD3B0)
> >>> +#define   HUC_FW_VERIFIED       (1<<7)
> >>> +
> >>>  #include "intel_guc_fwif.h"
> >>>  #include "i915_guc_reg.h"
> >>>  #include "intel_ringbuffer.h"
> >>> @@ -174,6 +177,13 @@ struct intel_guc {
> >>>  	struct mutex send_mutex;
> >>>  };
> >>>
> >>> +struct intel_huc {
> >>> +	/* Generic uC firmware management */
> >>> +	struct intel_uc_fw fw;
> >>> +
> >>> +	/* HuC-specific additions */
> >>> +};
> >>> +
> >>>  /* intel_uc.c */
> >>>  void intel_uc_init_early(struct drm_i915_private *dev_priv);  bool
> >>> intel_guc_recv(struct drm_i915_private *dev_priv, u32 *status); @@
> >>> -190,6 +200,9 @@ extern void intel_guc_fini(struct drm_i915_private
> >>> *dev_priv);  extern const char *intel_uc_fw_status_repr(enum
> >>> intel_uc_fw_status status);  extern int intel_guc_suspend(struct
> >>> drm_i915_private *dev_priv);  extern int intel_guc_resume(struct
> >>> drm_i915_private *dev_priv);
> >>> +void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
> >>> +	struct intel_uc_fw *uc_fw);
> >>> +u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv);
> >>>
> >>>  /* i915_guc_submission.c */
> >>>  int i915_guc_submission_init(struct drm_i915_private *dev_priv); @@
> >>> -204,4 +217,9 @@ void i915_guc_register(struct drm_i915_private
> >>> *dev_priv);  void i915_guc_unregister(struct drm_i915_private
> >>> *dev_priv);  int i915_guc_log_control(struct drm_i915_private
> >>> *dev_priv, u64 control_val);
> >>>
> >>> +/* intel_huc_loader.c */
> >>> +void intel_huc_init(struct drm_i915_private *dev_priv); void
> >>> +intel_huc_fini(struct drm_device *dev); int intel_huc_load(struct
> >>> +drm_i915_private *dev_priv);
> >>> +
> >>>  #endif
> >>> --
> >>> 2.7.4
> >>>
> >>> _______________________________________________
> >>> Intel-gfx mailing list
> >>> Intel-gfx@lists.freedesktop.org
> >>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >_______________________________________________
> >Intel-gfx mailing list
> >Intel-gfx@lists.freedesktop.org
> >https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Cheers,
Arek
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 7/8] drm/i915/huc: Support HuC authentication

[Anusha Srivatsa]

The HuC authentication is done by host2guc call. The HuC RSA keys
are sent to GuC for authentication.

v2: rebased on top of drm-tip. Changed name format and upped
version 1.7.
v3: changed wait_for_atomic to wait_for
v4: rebased. Rename intel_huc_auh() to intel_guc_auth_huc()
and place the prototype in intel_guc.h,correct the comments.
v5: rebased. Moved intel_guc_auth_huc from i915_guc_submission.c
to intel_uc.c.Update dev to dev_priv in intel_guc_auth_huc().
Renamed HOST2GUC_ACTION_AUTHENTICATE_HUC TO INTEL_GUC_ACTION_
AUTHENTICATE_HUC
v6: rebased. Add newline on DRM_ERRORs that already dont have one.
v7: rebased. Replace wait_for with intel_wait_for_register() since
the latter employs sleep optimisations for quick responses- as pointed
out by Chris Wilson.
v8: rebased. Cleanup the intel_guc_auth_huc() by removing checks
already performed in earlier functions. Make comments more descriptive.
v9: rebased. Changed the bias for pinning the HuC object. Move
intel_guc_auth_huc() to intel_huc.c. Change DRM_DEBUGs to DRM_ERRORs
in intel_guc_auth_huc(). Add return status to DRM_ERRORs.
v10: Remove message not required for the user..

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Tested-by: Xiang Haihao <haihao.xiang@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
---
 drivers/gpu/drm/i915/intel_guc_fwif.h   |  1 +
 drivers/gpu/drm/i915/intel_guc_loader.c |  2 ++
 drivers/gpu/drm/i915/intel_huc.c        | 49 +++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_uc.h         |  1 +
 4 files changed, 53 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
index ed1ab40..25691f0 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -505,6 +505,7 @@ enum intel_guc_action {
 	INTEL_GUC_ACTION_ENTER_S_STATE = 0x501,
 	INTEL_GUC_ACTION_EXIT_S_STATE = 0x502,
 	INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003,
+	INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
 	INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000,
 	INTEL_GUC_ACTION_LIMIT
 };
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 527558f..bb127a4 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -530,6 +530,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
 		intel_uc_fw_status_repr(guc_fw->fetch_status),
 		intel_uc_fw_status_repr(guc_fw->load_status));
 
+	intel_guc_auth_huc(dev_priv);
+
 	if (i915.enable_guc_submission) {
 		if (i915.guc_log_level >= 0)
 			gen9_enable_guc_interrupts(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
index 8b84ba8..897ef31 100644
--- a/drivers/gpu/drm/i915/intel_huc.c
+++ b/drivers/gpu/drm/i915/intel_huc.c
@@ -284,3 +284,52 @@ void intel_huc_fini(struct drm_i915_private *dev_priv)
 	huc_fw->fetch_status = INTEL_UC_FIRMWARE_NONE;
 }
 
+/**
+ * intel_guc_auth_huc() - authenticate ucode
+ * @dev_priv: the drm_i915_device
+ *
+ * Triggers a HuC fw authentication request to the GuC via intel_guc_action_
+ * authenticate_huc interface.
+ */
+void intel_guc_auth_huc(struct drm_i915_private *dev_priv)
+{
+	struct intel_guc *guc = &dev_priv->guc;
+	struct intel_huc *huc = &dev_priv->huc;
+	struct i915_vma *vma;
+	int ret;
+	u32 data[2];
+
+	vma = i915_gem_object_ggtt_pin(huc->fw.obj, NULL, 0, 0,
+				PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
+	if (IS_ERR(vma)) {
+		DRM_ERROR("failed to pin huc fw object %d\n",
+				(int)PTR_ERR(vma));
+		return;
+	}
+
+	/* Specify auth action and where public signature is. */
+	data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC;
+	data[1] = i915_ggtt_offset(vma) + huc->fw.rsa_offset;
+
+	ret = intel_guc_send(guc, data, ARRAY_SIZE(data));
+	if (ret) {
+		DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret);
+		goto out;
+	}
+
+	/* Check authentication status, it should be done by now */
+	ret = intel_wait_for_register(dev_priv,
+				HUC_STATUS2,
+				HUC_FW_VERIFIED,
+				HUC_FW_VERIFIED,
+				50);
+
+	if (ret) {
+		DRM_ERROR("HuC: Authentication failed %d\n", ret);
+		goto out;
+	}
+
+out:
+	i915_vma_unpin(vma);
+}
+
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index 65c7d6e..27f8b6f 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -227,5 +227,6 @@ static inline u32 guc_ggtt_offset(struct i915_vma *vma)
 void intel_huc_init(struct drm_i915_private *dev_priv);
 void intel_huc_fini(struct drm_i915_private  *dev_priv);
 int intel_huc_load(struct drm_i915_private *dev_priv);
+void intel_guc_auth_huc(struct drm_i915_private *dev_priv);
 
 #endif
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 7/8] drm/i915/huc: Support HuC authentication

[Chris Wilson]

On Fri, Jan 13, 2017 at 06:19:53PM +0000, Srivatsa, Anusha wrote:
> >> +	/* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
> >> +	I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);

This is not required on drm-tip.

> >> +	/* Specify auth action and where public signature is. */
> >> +	data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC;
> >> +	data[1] = i915_ggtt_offset(vma) + huc->fw.rsa_offset;
> >> +
> >> +	ret = intel_guc_send(guc, data, ARRAY_SIZE(data));
> >> +	if (ret) {
> >> +		DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret);
> >> +		goto out;
> >> +	}
> >> +
> >> +	/* Check authentication status, it should be done by now */
> >> +	ret = intel_wait_for_register(dev_priv,
> >> +				HUC_STATUS2,
> >> +				HUC_FW_VERIFIED,
> >> +				HUC_FW_VERIFIED,
> >> +				50);
> >> +
> >> +	if (ret) {
> >> +		DRM_ERROR("HuC: Authentication failed %d\n", ret);
> >> +		goto out;
> >> +	}
> >> +
> >> +	DRM_INFO("HuC Authentication Successful!\n");

You still seem surprised. Is this a useful user message? What does it
mean for the user? Avoid using jargon when talking to the user.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 7/8] drm/i915/huc: Support HuC authentication

[Srivatsa, Anusha]

>-----Original Message-----
>From: Wajdeczko, Michal
>Sent: Friday, January 13, 2017 10:18 AM
>To: Srivatsa, Anusha <anusha.srivatsa@intel.com>
>Cc: intel-gfx@lists.freedesktop.org; Chris Wilson <chris@chris-wilson.co.uk>;
>Hiler, Arkadiusz <arkadiusz.hiler@intel.com>; Alex Dai <yu.dai@intel.com>; Peter
>Antoine <peter.antoine@intel.com>
>Subject: Re: [PATCH 7/8] drm/i915/huc: Support HuC authentication
>
>On Fri, Jan 13, 2017 at 10:08:42AM -0800, Anusha Srivatsa wrote:
>> The HuC authentication is done by host2guc call. The HuC RSA keys are
>> sent to GuC for authentication.
>>
>> v2: rebased on top of drm-tip. Changed name format and upped version
>> 1.7.
>> v3: changed wait_for_atomic to wait_for
>> v4: rebased. Rename intel_huc_auh() to intel_guc_auth_huc() and place
>> the prototype in intel_guc.h,correct the comments.
>> v5: rebased. Moved intel_guc_auth_huc from i915_guc_submission.c to
>> intel_uc.c.Update dev to dev_priv in intel_guc_auth_huc().
>> Renamed HOST2GUC_ACTION_AUTHENTICATE_HUC TO INTEL_GUC_ACTION_
>> AUTHENTICATE_HUC
>> v6: rebased. Add newline on DRM_ERRORs that already dont have one.
>> v7: rebased. Replace wait_for with intel_wait_for_register() since the
>> latter employs sleep optimisations for quick responses- as pointed out
>> by Chris Wilson.
>> v8: rebased. Cleanup the intel_guc_auth_huc() by removing checks
>> already performed in earlier functions. Make comments more descriptive.
>> v9: rebased. Changed the bias for pinning the HuC object. Move
>> intel_guc_auth_huc() to intel_huc.c. Change DRM_DEBUGs to DRM_ERRORs
>> in intel_guc_auth_huc(). Add return status to DRM_ERRORs.
>> v10: Replace DRM_ERROR with DRM_INFO for cases that are non-
>> erroneous.
>>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
>> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
>> Tested-by: Xiang Haihao <haihao.xiang@intel.com>
>> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>> Signed-off-by: Alex Dai <yu.dai@intel.com>
>> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
>> ---
>>  drivers/gpu/drm/i915/intel_guc_fwif.h   |  1 +
>>  drivers/gpu/drm/i915/intel_guc_loader.c |  2 ++
>>  drivers/gpu/drm/i915/intel_huc.c        | 53
>+++++++++++++++++++++++++++++++++
>>  drivers/gpu/drm/i915/intel_uc.h         |  1 +
>>  4 files changed, 57 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h
>> b/drivers/gpu/drm/i915/intel_guc_fwif.h
>> index ed1ab40..25691f0 100644
>> --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
>> +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
>> @@ -505,6 +505,7 @@ enum intel_guc_action {
>>  	INTEL_GUC_ACTION_ENTER_S_STATE = 0x501,
>>  	INTEL_GUC_ACTION_EXIT_S_STATE = 0x502,
>>  	INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003,
>> +	INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
>>  	INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000,
>>  	INTEL_GUC_ACTION_LIMIT
>>  };
>> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
>> b/drivers/gpu/drm/i915/intel_guc_loader.c
>> index 527558f..bb127a4 100644
>> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
>> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
>> @@ -530,6 +530,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
>>  		intel_uc_fw_status_repr(guc_fw->fetch_status),
>>  		intel_uc_fw_status_repr(guc_fw->load_status));
>>
>> +	intel_guc_auth_huc(dev_priv);
>> +
>>  	if (i915.enable_guc_submission) {
>>  		if (i915.guc_log_level >= 0)
>>  			gen9_enable_guc_interrupts(dev_priv);
>> diff --git a/drivers/gpu/drm/i915/intel_huc.c
>> b/drivers/gpu/drm/i915/intel_huc.c
>> index 8b84ba8..4ae34b5 100644
>> --- a/drivers/gpu/drm/i915/intel_huc.c
>> +++ b/drivers/gpu/drm/i915/intel_huc.c
>> @@ -284,3 +284,56 @@ void intel_huc_fini(struct drm_i915_private *dev_priv)
>>  	huc_fw->fetch_status = INTEL_UC_FIRMWARE_NONE;  }
>>
>> +/**
>> + * intel_guc_auth_huc() - authenticate ucode
>> + * @dev_priv: the drm_i915_device
>> + *
>> + * Triggers a HuC fw authentication request to the GuC via
>> +intel_guc_action_
>> + * authenticate_huc interface.
>> + */
>> +void intel_guc_auth_huc(struct drm_i915_private *dev_priv) {
>> +	struct intel_guc *guc = &dev_priv->guc;
>> +	struct intel_huc *huc = &dev_priv->huc;
>> +	struct i915_vma *vma;
>> +	int ret;
>> +	u32 data[2];
>> +
>> +	vma = i915_gem_object_ggtt_pin(huc->fw.obj, NULL, 0, 0,
>> +				PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
>> +	if (IS_ERR(vma)) {
>> +		DRM_ERROR("failed to pin huc fw object %d\n",
>
>Maybe this message should start with "HuC:" to match other error messages used
>below ? Anyway,
>
>Reviewed-by: Michal Wajdeczko <michal.wajdeczko.intel.com>

Thanks a lot Michal!

>Thanks,
>Michal
>
>
>> +				(int)PTR_ERR(vma));
>> +		return;
>> +	}
>> +
>> +	/* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
>> +	I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
>> +
>> +	/* Specify auth action and where public signature is. */
>> +	data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC;
>> +	data[1] = i915_ggtt_offset(vma) + huc->fw.rsa_offset;
>> +
>> +	ret = intel_guc_send(guc, data, ARRAY_SIZE(data));
>> +	if (ret) {
>> +		DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret);
>> +		goto out;
>> +	}
>> +
>> +	/* Check authentication status, it should be done by now */
>> +	ret = intel_wait_for_register(dev_priv,
>> +				HUC_STATUS2,
>> +				HUC_FW_VERIFIED,
>> +				HUC_FW_VERIFIED,
>> +				50);
>> +
>> +	if (ret) {
>> +		DRM_ERROR("HuC: Authentication failed %d\n", ret);
>> +		goto out;
>> +	}
>> +
>> +	DRM_INFO("HuC Authentication Successful!\n");
>> +out:
>> +	i915_vma_unpin(vma);
>> +}
>> +
>> diff --git a/drivers/gpu/drm/i915/intel_uc.h
>> b/drivers/gpu/drm/i915/intel_uc.h index 65c7d6e..27f8b6f 100644
>> --- a/drivers/gpu/drm/i915/intel_uc.h
>> +++ b/drivers/gpu/drm/i915/intel_uc.h
>> @@ -227,5 +227,6 @@ static inline u32 guc_ggtt_offset(struct i915_vma
>> *vma)  void intel_huc_init(struct drm_i915_private *dev_priv);  void
>> intel_huc_fini(struct drm_i915_private  *dev_priv);  int
>> intel_huc_load(struct drm_i915_private *dev_priv);
>> +void intel_guc_auth_huc(struct drm_i915_private *dev_priv);
>>
>>  #endif
>> --
>> 2.7.4
>>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 7/8] drm/i915/huc: Support HuC authentication

[Michal Wajdeczko]

On Fri, Jan 13, 2017 at 10:08:42AM -0800, Anusha Srivatsa wrote:
> The HuC authentication is done by host2guc call. The HuC RSA keys
> are sent to GuC for authentication.
> 
> v2: rebased on top of drm-tip. Changed name format and upped
> version 1.7.
> v3: changed wait_for_atomic to wait_for
> v4: rebased. Rename intel_huc_auh() to intel_guc_auth_huc()
> and place the prototype in intel_guc.h,correct the comments.
> v5: rebased. Moved intel_guc_auth_huc from i915_guc_submission.c
> to intel_uc.c.Update dev to dev_priv in intel_guc_auth_huc().
> Renamed HOST2GUC_ACTION_AUTHENTICATE_HUC TO INTEL_GUC_ACTION_
> AUTHENTICATE_HUC
> v6: rebased. Add newline on DRM_ERRORs that already dont have one.
> v7: rebased. Replace wait_for with intel_wait_for_register() since
> the latter employs sleep optimisations for quick responses- as pointed
> out by Chris Wilson.
> v8: rebased. Cleanup the intel_guc_auth_huc() by removing checks
> already performed in earlier functions. Make comments more descriptive.
> v9: rebased. Changed the bias for pinning the HuC object. Move
> intel_guc_auth_huc() to intel_huc.c. Change DRM_DEBUGs to DRM_ERRORs
> in intel_guc_auth_huc(). Add return status to DRM_ERRORs.
> v10: Replace DRM_ERROR with DRM_INFO for cases that are non-
> erroneous.
> 
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Tested-by: Xiang Haihao <haihao.xiang@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Alex Dai <yu.dai@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_guc_fwif.h   |  1 +
>  drivers/gpu/drm/i915/intel_guc_loader.c |  2 ++
>  drivers/gpu/drm/i915/intel_huc.c        | 53 +++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_uc.h         |  1 +
>  4 files changed, 57 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
> index ed1ab40..25691f0 100644
> --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
> @@ -505,6 +505,7 @@ enum intel_guc_action {
>  	INTEL_GUC_ACTION_ENTER_S_STATE = 0x501,
>  	INTEL_GUC_ACTION_EXIT_S_STATE = 0x502,
>  	INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003,
> +	INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
>  	INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000,
>  	INTEL_GUC_ACTION_LIMIT
>  };
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> index 527558f..bb127a4 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -530,6 +530,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
>  		intel_uc_fw_status_repr(guc_fw->fetch_status),
>  		intel_uc_fw_status_repr(guc_fw->load_status));
>  
> +	intel_guc_auth_huc(dev_priv);
> +
>  	if (i915.enable_guc_submission) {
>  		if (i915.guc_log_level >= 0)
>  			gen9_enable_guc_interrupts(dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
> index 8b84ba8..4ae34b5 100644
> --- a/drivers/gpu/drm/i915/intel_huc.c
> +++ b/drivers/gpu/drm/i915/intel_huc.c
> @@ -284,3 +284,56 @@ void intel_huc_fini(struct drm_i915_private *dev_priv)
>  	huc_fw->fetch_status = INTEL_UC_FIRMWARE_NONE;
>  }
>  
> +/**
> + * intel_guc_auth_huc() - authenticate ucode
> + * @dev_priv: the drm_i915_device
> + *
> + * Triggers a HuC fw authentication request to the GuC via intel_guc_action_
> + * authenticate_huc interface.
> + */
> +void intel_guc_auth_huc(struct drm_i915_private *dev_priv)
> +{
> +	struct intel_guc *guc = &dev_priv->guc;
> +	struct intel_huc *huc = &dev_priv->huc;
> +	struct i915_vma *vma;
> +	int ret;
> +	u32 data[2];
> +
> +	vma = i915_gem_object_ggtt_pin(huc->fw.obj, NULL, 0, 0,
> +				PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
> +	if (IS_ERR(vma)) {
> +		DRM_ERROR("failed to pin huc fw object %d\n",

Maybe this message should start with "HuC:" to match other error
messages used below ? Anyway,

Reviewed-by: Michal Wajdeczko <michal.wajdeczko.intel.com>

Thanks,
Michal


> +				(int)PTR_ERR(vma));
> +		return;
> +	}
> +
> +	/* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
> +	I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
> +
> +	/* Specify auth action and where public signature is. */
> +	data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC;
> +	data[1] = i915_ggtt_offset(vma) + huc->fw.rsa_offset;
> +
> +	ret = intel_guc_send(guc, data, ARRAY_SIZE(data));
> +	if (ret) {
> +		DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret);
> +		goto out;
> +	}
> +
> +	/* Check authentication status, it should be done by now */
> +	ret = intel_wait_for_register(dev_priv,
> +				HUC_STATUS2,
> +				HUC_FW_VERIFIED,
> +				HUC_FW_VERIFIED,
> +				50);
> +
> +	if (ret) {
> +		DRM_ERROR("HuC: Authentication failed %d\n", ret);
> +		goto out;
> +	}
> +
> +	DRM_INFO("HuC Authentication Successful!\n");
> +out:
> +	i915_vma_unpin(vma);
> +}
> +
> diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
> index 65c7d6e..27f8b6f 100644
> --- a/drivers/gpu/drm/i915/intel_uc.h
> +++ b/drivers/gpu/drm/i915/intel_uc.h
> @@ -227,5 +227,6 @@ static inline u32 guc_ggtt_offset(struct i915_vma *vma)
>  void intel_huc_init(struct drm_i915_private *dev_priv);
>  void intel_huc_fini(struct drm_i915_private  *dev_priv);
>  int intel_huc_load(struct drm_i915_private *dev_priv);
> +void intel_guc_auth_huc(struct drm_i915_private *dev_priv);
>  
>  #endif
> -- 
> 2.7.4
> 
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 7/8] drm/i915/huc: Support HuC authentication

[Anusha Srivatsa]

The HuC authentication is done by host2guc call. The HuC RSA keys
are sent to GuC for authentication.

v2: rebased on top of drm-tip. Changed name format and upped
version 1.7.
v3: changed wait_for_atomic to wait_for
v4: rebased. Rename intel_huc_auh() to intel_guc_auth_huc()
and place the prototype in intel_guc.h,correct the comments.
v5: rebased. Moved intel_guc_auth_huc from i915_guc_submission.c
to intel_uc.c.Update dev to dev_priv in intel_guc_auth_huc().
Renamed HOST2GUC_ACTION_AUTHENTICATE_HUC TO INTEL_GUC_ACTION_
AUTHENTICATE_HUC
v6: rebased. Add newline on DRM_ERRORs that already dont have one.
v7: rebased. Replace wait_for with intel_wait_for_register() since
the latter employs sleep optimisations for quick responses- as pointed
out by Chris Wilson.
v8: rebased. Cleanup the intel_guc_auth_huc() by removing checks
already performed in earlier functions. Make comments more descriptive.
v9: rebased. Changed the bias for pinning the HuC object. Move
intel_guc_auth_huc() to intel_huc.c. Change DRM_DEBUGs to DRM_ERRORs
in intel_guc_auth_huc(). Add return status to DRM_ERRORs.
v10: Replace DRM_ERROR with DRM_INFO for cases that are non-
erroneous.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Tested-by: Xiang Haihao <haihao.xiang@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
---
 drivers/gpu/drm/i915/intel_guc_fwif.h   |  1 +
 drivers/gpu/drm/i915/intel_guc_loader.c |  2 ++
 drivers/gpu/drm/i915/intel_huc.c        | 53 +++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_uc.h         |  1 +
 4 files changed, 57 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
index ed1ab40..25691f0 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -505,6 +505,7 @@ enum intel_guc_action {
 	INTEL_GUC_ACTION_ENTER_S_STATE = 0x501,
 	INTEL_GUC_ACTION_EXIT_S_STATE = 0x502,
 	INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003,
+	INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
 	INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000,
 	INTEL_GUC_ACTION_LIMIT
 };
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 527558f..bb127a4 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -530,6 +530,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
 		intel_uc_fw_status_repr(guc_fw->fetch_status),
 		intel_uc_fw_status_repr(guc_fw->load_status));
 
+	intel_guc_auth_huc(dev_priv);
+
 	if (i915.enable_guc_submission) {
 		if (i915.guc_log_level >= 0)
 			gen9_enable_guc_interrupts(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
index 8b84ba8..4ae34b5 100644
--- a/drivers/gpu/drm/i915/intel_huc.c
+++ b/drivers/gpu/drm/i915/intel_huc.c
@@ -284,3 +284,56 @@ void intel_huc_fini(struct drm_i915_private *dev_priv)
 	huc_fw->fetch_status = INTEL_UC_FIRMWARE_NONE;
 }
 
+/**
+ * intel_guc_auth_huc() - authenticate ucode
+ * @dev_priv: the drm_i915_device
+ *
+ * Triggers a HuC fw authentication request to the GuC via intel_guc_action_
+ * authenticate_huc interface.
+ */
+void intel_guc_auth_huc(struct drm_i915_private *dev_priv)
+{
+	struct intel_guc *guc = &dev_priv->guc;
+	struct intel_huc *huc = &dev_priv->huc;
+	struct i915_vma *vma;
+	int ret;
+	u32 data[2];
+
+	vma = i915_gem_object_ggtt_pin(huc->fw.obj, NULL, 0, 0,
+				PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
+	if (IS_ERR(vma)) {
+		DRM_ERROR("failed to pin huc fw object %d\n",
+				(int)PTR_ERR(vma));
+		return;
+	}
+
+	/* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
+	I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
+
+	/* Specify auth action and where public signature is. */
+	data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC;
+	data[1] = i915_ggtt_offset(vma) + huc->fw.rsa_offset;
+
+	ret = intel_guc_send(guc, data, ARRAY_SIZE(data));
+	if (ret) {
+		DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret);
+		goto out;
+	}
+
+	/* Check authentication status, it should be done by now */
+	ret = intel_wait_for_register(dev_priv,
+				HUC_STATUS2,
+				HUC_FW_VERIFIED,
+				HUC_FW_VERIFIED,
+				50);
+
+	if (ret) {
+		DRM_ERROR("HuC: Authentication failed %d\n", ret);
+		goto out;
+	}
+
+	DRM_INFO("HuC Authentication Successful!\n");
+out:
+	i915_vma_unpin(vma);
+}
+
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index 65c7d6e..27f8b6f 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -227,5 +227,6 @@ static inline u32 guc_ggtt_offset(struct i915_vma *vma)
 void intel_huc_init(struct drm_i915_private *dev_priv);
 void intel_huc_fini(struct drm_i915_private  *dev_priv);
 int intel_huc_load(struct drm_i915_private *dev_priv);
+void intel_guc_auth_huc(struct drm_i915_private *dev_priv);
 
 #endif
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 7/8] drm/i915/huc: Support HuC authentication

[Srivatsa, Anusha]

>-----Original Message-----
>From: Chris Wilson [mailto:chris@chris-wilson.co.uk]
>Sent: Friday, January 13, 2017 9:25 AM
>To: Srivatsa, Anusha <anusha.srivatsa@intel.com>
>Cc: intel-gfx@lists.freedesktop.org; Hiler, Arkadiusz <arkadiusz.hiler@intel.com>;
>Wajdeczko, Michal <Michal.Wajdeczko@intel.com>; Alex Dai
><yu.dai@intel.com>; Peter Antoine <peter.antoine@intel.com>
>Subject: Re: [PATCH 7/8] drm/i915/huc: Support HuC authentication
>
>On Fri, Jan 13, 2017 at 09:07:08AM -0800, Anusha Srivatsa wrote:
>> +/**
>> + * intel_guc_auth_huc() - authenticate ucode
>> + * @dev_priv: the drm_i915_device
>> + *
>> + * Triggers a HuC fw authentication request to the GuC via
>> +intel_guc_action_
>> + * authenticate_huc interface.
>> + */
>> +void intel_guc_auth_huc(struct drm_i915_private *dev_priv) {
>> +	struct intel_guc *guc = &dev_priv->guc;
>> +	struct intel_huc *huc = &dev_priv->huc;
>> +	struct i915_vma *vma;
>> +	int ret;
>> +	u32 data[2];
>> +
>> +	vma = i915_gem_object_ggtt_pin(huc->fw.obj, NULL, 0, 0,
>> +				PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
>> +	if (IS_ERR(vma)) {
>> +		DRM_ERROR("failed to pin huc fw object %d\n",
>> +				(int)PTR_ERR(vma));
>> +		return;
>> +	}
>> +
>> +	/* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
>> +	I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
>> +
>> +	/* Specify auth action and where public signature is. */
>> +	data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC;
>> +	data[1] = i915_ggtt_offset(vma) + huc->fw.rsa_offset;
>> +
>> +	ret = intel_guc_send(guc, data, ARRAY_SIZE(data));
>> +	if (ret) {
>> +		DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret);
>> +		goto out;
>> +	}
>> +
>> +	/* Check authentication status, it should be done by now */
>> +	ret = intel_wait_for_register(dev_priv,
>> +				HUC_STATUS2,
>> +				HUC_FW_VERIFIED,
>> +				HUC_FW_VERIFIED,
>> +				50);
>> +
>> +	if (ret) {
>> +		DRM_ERROR("HuC: Authentication failed %d\n", ret);
>> +		goto out;
>> +	}
>> +
>> +	DRM_ERROR("HuC Authentication Successful!\n");
>
>Probably don't want to proclaim using the HuC as an error ;-) -Chris

Oh... I was actually thinking it is good if it proclaimed....
Wont it be useful message to know?

Anusha 
>--
>Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 7/8] drm/i915/huc: Support HuC authentication

[Chris Wilson]

On Fri, Jan 13, 2017 at 09:07:08AM -0800, Anusha Srivatsa wrote:
> +/**
> + * intel_guc_auth_huc() - authenticate ucode
> + * @dev_priv: the drm_i915_device
> + *
> + * Triggers a HuC fw authentication request to the GuC via intel_guc_action_
> + * authenticate_huc interface.
> + */
> +void intel_guc_auth_huc(struct drm_i915_private *dev_priv)
> +{
> +	struct intel_guc *guc = &dev_priv->guc;
> +	struct intel_huc *huc = &dev_priv->huc;
> +	struct i915_vma *vma;
> +	int ret;
> +	u32 data[2];
> +
> +	vma = i915_gem_object_ggtt_pin(huc->fw.obj, NULL, 0, 0,
> +				PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
> +	if (IS_ERR(vma)) {
> +		DRM_ERROR("failed to pin huc fw object %d\n",
> +				(int)PTR_ERR(vma));
> +		return;
> +	}
> +
> +	/* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
> +	I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
> +
> +	/* Specify auth action and where public signature is. */
> +	data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC;
> +	data[1] = i915_ggtt_offset(vma) + huc->fw.rsa_offset;
> +
> +	ret = intel_guc_send(guc, data, ARRAY_SIZE(data));
> +	if (ret) {
> +		DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret);
> +		goto out;
> +	}
> +
> +	/* Check authentication status, it should be done by now */
> +	ret = intel_wait_for_register(dev_priv,
> +				HUC_STATUS2,
> +				HUC_FW_VERIFIED,
> +				HUC_FW_VERIFIED,
> +				50);
> +
> +	if (ret) {
> +		DRM_ERROR("HuC: Authentication failed %d\n", ret);
> +		goto out;
> +	}
> +
> +	DRM_ERROR("HuC Authentication Successful!\n");

Probably don't want to proclaim using the HuC as an error ;-)
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 7/8] drm/i915/huc: Support HuC authentication

[Anusha Srivatsa]

The HuC authentication is done by host2guc call. The HuC RSA keys
are sent to GuC for authentication.

v2: rebased on top of drm-tip. Changed name format and upped
version 1.7.
v3: changed wait_for_atomic to wait_for
v4: rebased. Rename intel_huc_auh() to intel_guc_auth_huc()
and place the prototype in intel_guc.h,correct the comments.
v5: rebased. Moved intel_guc_auth_huc from i915_guc_submission.c
to intel_uc.c.Update dev to dev_priv in intel_guc_auth_huc().
Renamed HOST2GUC_ACTION_AUTHENTICATE_HUC TO INTEL_GUC_ACTION_
AUTHENTICATE_HUC
v6: rebased. Add newline on DRM_ERRORs that already dont have one.
v7: rebased. Replace wait_for with intel_wait_for_register() since
the latter employs sleep optimisations for quick responses- as pointed
out by Chris Wilson.
v8: rebased. Cleanup the intel_guc_auth_huc() by removing checks
already performed in earlier functions. Make comments more descriptive.
v9: rebased. Changed the bias for pinning the HuC object. Move
intel_guc_auth_huc() to intel_huc.c. Change DRM_DEBUGs to DRM_ERRORs
in intel_guc_auth_huc(). Add return status to DRM_ERRORs.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Tested-by: Xiang Haihao <haihao.xiang@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
---
 drivers/gpu/drm/i915/intel_guc_fwif.h   |  1 +
 drivers/gpu/drm/i915/intel_guc_loader.c |  2 ++
 drivers/gpu/drm/i915/intel_huc.c        | 53 +++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_uc.h         |  1 +
 4 files changed, 57 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
index ed1ab40..25691f0 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -505,6 +505,7 @@ enum intel_guc_action {
 	INTEL_GUC_ACTION_ENTER_S_STATE = 0x501,
 	INTEL_GUC_ACTION_EXIT_S_STATE = 0x502,
 	INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003,
+	INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
 	INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000,
 	INTEL_GUC_ACTION_LIMIT
 };
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 861c157..c618d11 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -530,6 +530,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
 		intel_uc_fw_status_repr(guc_fw->fetch_status),
 		intel_uc_fw_status_repr(guc_fw->load_status));
 
+	intel_guc_auth_huc(dev_priv);
+
 	if (i915.enable_guc_submission) {
 		if (i915.guc_log_level >= 0)
 			gen9_enable_guc_interrupts(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
index 7f3774a..22f1207 100644
--- a/drivers/gpu/drm/i915/intel_huc.c
+++ b/drivers/gpu/drm/i915/intel_huc.c
@@ -287,3 +287,56 @@ void intel_huc_fini(struct drm_i915_private *dev_priv)
 	huc_fw->fetch_status = INTEL_UC_FIRMWARE_NONE;
 }
 
+/**
+ * intel_guc_auth_huc() - authenticate ucode
+ * @dev_priv: the drm_i915_device
+ *
+ * Triggers a HuC fw authentication request to the GuC via intel_guc_action_
+ * authenticate_huc interface.
+ */
+void intel_guc_auth_huc(struct drm_i915_private *dev_priv)
+{
+	struct intel_guc *guc = &dev_priv->guc;
+	struct intel_huc *huc = &dev_priv->huc;
+	struct i915_vma *vma;
+	int ret;
+	u32 data[2];
+
+	vma = i915_gem_object_ggtt_pin(huc->fw.obj, NULL, 0, 0,
+				PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
+	if (IS_ERR(vma)) {
+		DRM_ERROR("failed to pin huc fw object %d\n",
+				(int)PTR_ERR(vma));
+		return;
+	}
+
+	/* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
+	I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
+
+	/* Specify auth action and where public signature is. */
+	data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC;
+	data[1] = i915_ggtt_offset(vma) + huc->fw.rsa_offset;
+
+	ret = intel_guc_send(guc, data, ARRAY_SIZE(data));
+	if (ret) {
+		DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret);
+		goto out;
+	}
+
+	/* Check authentication status, it should be done by now */
+	ret = intel_wait_for_register(dev_priv,
+				HUC_STATUS2,
+				HUC_FW_VERIFIED,
+				HUC_FW_VERIFIED,
+				50);
+
+	if (ret) {
+		DRM_ERROR("HuC: Authentication failed %d\n", ret);
+		goto out;
+	}
+
+	DRM_ERROR("HuC Authentication Successful!\n");
+out:
+	i915_vma_unpin(vma);
+}
+
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index 65c7d6e..27f8b6f 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -227,5 +227,6 @@ static inline u32 guc_ggtt_offset(struct i915_vma *vma)
 void intel_huc_init(struct drm_i915_private *dev_priv);
 void intel_huc_fini(struct drm_i915_private  *dev_priv);
 int intel_huc_load(struct drm_i915_private *dev_priv);
+void intel_guc_auth_huc(struct drm_i915_private *dev_priv);
 
 #endif
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 7/8] drm/i915/huc: Support HuC authentication

[Michal Wajdeczko]

On Wed, Jan 04, 2017 at 06:55:54AM -0800, Anusha Srivatsa wrote:
> From: Peter Antoine <peter.antoine@intel.com>
> 
> The HuC authentication is done by host2guc call. The HuC RSA keys
> are sent to GuC for authentication.
> 
> v2: rebased on top of drm-intel-nightly.
>     changed name format and upped version 1.7.
> v3: rebased on top of drm-intel-nightly.
> v4: changed wait_for_automic to wait_for
> v5: rebased.
> v7: rebased.
> v8: rebased.
> v9: rebased. Rename intel_huc_auh() to intel_guc_auth_huc()
> and place the prototype in intel_guc.h,correct the comments.
> v10: rebased.
> v11: rebased.
> v12: rebased on top of drm-tip
> v13: rebased. Moved intel_guc_auth_huc from i915_guc_submission.c
> to intel_uc.c.Update dev to dev_priv in intel_guc_auth_huc().
> Renamed HOST2GUC_ACTION_AUTHENTICATE_HUC TO INTEL_GUC_ACTION_
> AUTHENTICATE_HUC
> v14: rebased.
> v15: rebased. Add newline on DRM_ERRORs that already dont have one.
> v16: rebased. Replace wait_for with intel_wait_for_register() since
> the latter employs sleep optimisations for quick responses- as pointed
> out by Chris Wilson.
> 
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
> Cc: Michal Wajdeczko <michal.wajdecko@intel.com>

Typo in my email ;(

> Tested-by: Xiang Haihao <haihao.xiang@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Alex Dai <yu.dai@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_guc_fwif.h   |  1 +
>  drivers/gpu/drm/i915/intel_guc_loader.c |  2 +
>  drivers/gpu/drm/i915/intel_uc.c         | 70 ++++++++++++++++++++++++++++++++-
>  drivers/gpu/drm/i915/intel_uc.h         |  1 +
>  4 files changed, 72 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
> index ed1ab40..ce4e05e 100644
> --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
> @@ -506,6 +506,7 @@ enum intel_guc_action {
>  	INTEL_GUC_ACTION_EXIT_S_STATE = 0x502,
>  	INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003,
>  	INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000,
> +	INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,

Can we keep actions in order of their code values?


>  	INTEL_GUC_ACTION_LIMIT
>  };
>  
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> index ed57ab3..0508054 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -529,6 +529,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
>  		intel_uc_fw_status_repr(guc_fw->fetch_status),
>  		intel_uc_fw_status_repr(guc_fw->load_status));
>  
> +	intel_guc_auth_huc(dev_priv);
> +
>  	if (i915.enable_guc_submission) {
>  		if (i915.guc_log_level >= 0)
>  			gen9_enable_guc_interrupts(dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
> index c6be352..d1a4d79 100644
> --- a/drivers/gpu/drm/i915/intel_uc.c
> +++ b/drivers/gpu/drm/i915/intel_uc.c
> @@ -46,7 +46,7 @@ static bool intel_guc_recv(struct intel_guc *guc, u32 *status)
>  int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len)
>  {
>  	struct drm_i915_private *dev_priv = guc_to_i915(guc);
> -	u32 status;
> +	u32 status = 0;
>  	int i;
>  	int ret;
>  
> @@ -71,7 +71,11 @@ int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len)
>  	 * up to that length of time, then switch to a slower sleep-wait loop.
>  	 * No inte_guc_send command should ever take longer than 10ms.
>  	 */
> -	ret = wait_for_us(intel_guc_recv(guc, &status), 10);
> +	ret = intel_wait_for_register(dev_priv,
> +					HUC_STATUS2,
> +					HUC_FW_VERIFIED,
> +					HUC_FW_VERIFIED,
> +					50);
>  	if (ret)
>  		ret = wait_for(intel_guc_recv(guc, &status), 10);
>  	if (status != INTEL_GUC_STATUS_SUCCESS) {
> @@ -140,3 +144,65 @@ int intel_guc_log_control(struct intel_guc *guc, u32 control_val)
>  
>  	return intel_guc_send(guc, action, ARRAY_SIZE(action));
>  }
> +
> +/**
> + * intel_guc_auth_huc() - authenticate ucode
> + * @dev_priv: the drm_i915_device
> + *
> + * Triggers a HuC fw authentication request to the GuC via intel_guc_action_
> + * authenticate_huc interface.
> + * interface.
> + */
> +void intel_guc_auth_huc(struct drm_i915_private *dev_priv)
> +{
> +	struct intel_guc *guc = &dev_priv->guc;
> +	struct intel_huc *huc = &dev_priv->huc;
> +	struct i915_vma *vma;
> +	int ret;
> +	u32 data[2];
> +
> +	/* Bypass the case where there is no HuC firmware */
> +	if (huc->fw.fetch_status == INTEL_UC_FIRMWARE_NONE ||
> +		huc->fw.load_status == INTEL_UC_FIRMWARE_NONE)

To catch the case when there is no Huc fw, maybe only first check is needed
as in intel_huc_load()?


> +		return;
> +
> +	if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS) {
> +		DRM_ERROR("HuC: GuC fw wasn't loaded. Can't authenticate\n");

This shall never happen as this function is called from guc_setup() only after
successful guc fw load.


> +		return;
> +	}
> +
> +	if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS) {
> +		DRM_ERROR("HuC: fw wasn't loaded. Nothing to authenticate\n");

Hmm, we should already have error message about failed huc fw loading.
Do we need to report other obvious failures?


> +		return;
> +	}
> +
> +	vma = i915_gem_object_ggtt_pin(huc->fw.obj, NULL, 0, 0, 0);
> +	if (IS_ERR(vma)) {
> +		DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));

Please be more descriptive, what about "failed to pin huc fw obj" ?


> +		return;
> +	}
> +
> +
> +	/* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
> +	I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
> +
> +	/* Specify auth action and where public signature is. */
> +	data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC;
> +	data[1] = i915_ggtt_offset(vma) + huc->fw.rsa_offset;
> +
> +	ret = intel_guc_send(guc, data, ARRAY_SIZE(data));
> +	if (ret) {
> +		DRM_ERROR("HuC: GuC did not ack Auth request\n");
> +		goto out;
> +	}
> +
> +	/* Check authentication status, it should be done by now */
> +	ret = wait_for((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) > 0, 50);
> +	if (ret) {
> +		DRM_ERROR("HuC: Authentication failed\n");
> +		goto out;
> +	}
> +

In other place you said:
  "I think we need a message for the case when there is no failure."
What about adding message here that confirms Huc authentication?


> +out:
> +	i915_vma_unpin(vma);
> +}
> diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
> index 7df57c1..6ba56e18 100644
> --- a/drivers/gpu/drm/i915/intel_uc.h
> +++ b/drivers/gpu/drm/i915/intel_uc.h
> @@ -193,6 +193,7 @@ int intel_guc_sample_forcewake(struct intel_guc *guc);
>  int intel_guc_log_flush_complete(struct intel_guc *guc);
>  int intel_guc_log_flush(struct intel_guc *guc);
>  int intel_guc_log_control(struct intel_guc *guc, u32 control_val);
> +void intel_guc_auth_huc(struct drm_i915_private *dev_priv);
>  
>  /* intel_guc_loader.c */
>  extern void intel_guc_init(struct drm_i915_private *dev_priv);
> -- 
> 2.7.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 7/8] drm/i915/huc: Support HuC authentication

[Arkadiusz Hiler]

On Wed, Jan 04, 2017 at 06:55:54AM -0800, Anusha Srivatsa wrote:
> From: Peter Antoine <peter.antoine@intel.com>
> 
> The HuC authentication is done by host2guc call. The HuC RSA keys
> are sent to GuC for authentication.
> 
> v2: rebased on top of drm-intel-nightly.
>     changed name format and upped version 1.7.
> v3: rebased on top of drm-intel-nightly.
> v4: changed wait_for_automic to wait_for
> v5: rebased.
> v7: rebased.
> v8: rebased.
> v9: rebased. Rename intel_huc_auh() to intel_guc_auth_huc()
> and place the prototype in intel_guc.h,correct the comments.
> v10: rebased.
> v11: rebased.
> v12: rebased on top of drm-tip
> v13: rebased. Moved intel_guc_auth_huc from i915_guc_submission.c
> to intel_uc.c.Update dev to dev_priv in intel_guc_auth_huc().
> Renamed HOST2GUC_ACTION_AUTHENTICATE_HUC TO INTEL_GUC_ACTION_
> AUTHENTICATE_HUC
> v14: rebased.
> v15: rebased. Add newline on DRM_ERRORs that already dont have one.
> v16: rebased. Replace wait_for with intel_wait_for_register() since
> the latter employs sleep optimisations for quick responses- as pointed
> out by Chris Wilson.
> 
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
> Cc: Michal Wajdeczko <michal.wajdecko@intel.com>

Typo in Michal's address.

> Tested-by: Xiang Haihao <haihao.xiang@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Alex Dai <yu.dai@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>

-- 
Cheers,
Arek
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 7/8] drm/i915/huc: Support HuC authentication

[Arkadiusz Hiler]

On Wed, Jan 04, 2017 at 06:55:54AM -0800, Anusha Srivatsa wrote:
> From: Peter Antoine <peter.antoine@intel.com>
> 
> The HuC authentication is done by host2guc call. The HuC RSA keys
> are sent to GuC for authentication.
> 
> v2: rebased on top of drm-intel-nightly.
>     changed name format and upped version 1.7.
> v3: rebased on top of drm-intel-nightly.
> v4: changed wait_for_automic to wait_for
> v5: rebased.
> v7: rebased.
> v8: rebased.
> v9: rebased. Rename intel_huc_auh() to intel_guc_auth_huc()
> and place the prototype in intel_guc.h,correct the comments.
> v10: rebased.
> v11: rebased.
> v12: rebased on top of drm-tip
> v13: rebased. Moved intel_guc_auth_huc from i915_guc_submission.c
> to intel_uc.c.Update dev to dev_priv in intel_guc_auth_huc().
> Renamed HOST2GUC_ACTION_AUTHENTICATE_HUC TO INTEL_GUC_ACTION_
> AUTHENTICATE_HUC
> v14: rebased.
> v15: rebased. Add newline on DRM_ERRORs that already dont have one.
> v16: rebased. Replace wait_for with intel_wait_for_register() since
> the latter employs sleep optimisations for quick responses- as pointed
> out by Chris Wilson.
> 
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
> Cc: Michal Wajdeczko <michal.wajdecko@intel.com>
> Tested-by: Xiang Haihao <haihao.xiang@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Alex Dai <yu.dai@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_guc_fwif.h   |  1 +
>  drivers/gpu/drm/i915/intel_guc_loader.c |  2 +
>  drivers/gpu/drm/i915/intel_uc.c         | 70 ++++++++++++++++++++++++++++++++-
>  drivers/gpu/drm/i915/intel_uc.h         |  1 +
>  4 files changed, 72 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
> index ed1ab40..ce4e05e 100644
> --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
> @@ -506,6 +506,7 @@ enum intel_guc_action {
>  	INTEL_GUC_ACTION_EXIT_S_STATE = 0x502,
>  	INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003,
>  	INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000,
> +	INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
>  	INTEL_GUC_ACTION_LIMIT
>  };
>  
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> index ed57ab3..0508054 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -529,6 +529,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
>  		intel_uc_fw_status_repr(guc_fw->fetch_status),
>  		intel_uc_fw_status_repr(guc_fw->load_status));
>  
> +	intel_guc_auth_huc(dev_priv);
> +
>  	if (i915.enable_guc_submission) {
>  		if (i915.guc_log_level >= 0)
>  			gen9_enable_guc_interrupts(dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
> index c6be352..d1a4d79 100644
> --- a/drivers/gpu/drm/i915/intel_uc.c
> +++ b/drivers/gpu/drm/i915/intel_uc.c
> @@ -46,7 +46,7 @@ static bool intel_guc_recv(struct intel_guc *guc, u32 *status)
>  int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len)
>  {
>  	struct drm_i915_private *dev_priv = guc_to_i915(guc);
> -	u32 status;
> +	u32 status = 0;
>  	int i;
>  	int ret;
>  
> @@ -71,7 +71,11 @@ int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len)
>  	 * up to that length of time, then switch to a slower sleep-wait loop.
>  	 * No inte_guc_send command should ever take longer than 10ms.
>  	 */
> -	ret = wait_for_us(intel_guc_recv(guc, &status), 10);
> +	ret = intel_wait_for_register(dev_priv,
> +					HUC_STATUS2,
> +					HUC_FW_VERIFIED,
> +					HUC_FW_VERIFIED,
> +					50);

Why do all suddenly intel_guc_send() starts caring about HUC?

I think you've misplaced the check, missed that you were in the wrong
place and "fixed" status not being set properly by initializing it with
the 0.

>  	if (ret)
>  		ret = wait_for(intel_guc_recv(guc, &status), 10);
>  	if (status != INTEL_GUC_STATUS_SUCCESS) {
> @@ -140,3 +144,65 @@ int intel_guc_log_control(struct intel_guc *guc, u32 control_val)
>  
>  	return intel_guc_send(guc, action, ARRAY_SIZE(action));
>  }
> +
> +/**
> + * intel_guc_auth_huc() - authenticate ucode
> + * @dev_priv: the drm_i915_device
> + *
> + * Triggers a HuC fw authentication request to the GuC via intel_guc_action_
> + * authenticate_huc interface.
> + * interface.
> + */
> +void intel_guc_auth_huc(struct drm_i915_private *dev_priv)
> +{
> +	struct intel_guc *guc = &dev_priv->guc;
> +	struct intel_huc *huc = &dev_priv->huc;
> +	struct i915_vma *vma;
> +	int ret;
> +	u32 data[2];
> +
> +	/* Bypass the case where there is no HuC firmware */
> +	if (huc->fw.fetch_status == INTEL_UC_FIRMWARE_NONE ||
> +		huc->fw.load_status == INTEL_UC_FIRMWARE_NONE)
> +		return;
> +
> +	if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS) {
> +		DRM_ERROR("HuC: GuC fw wasn't loaded. Can't authenticate\n");
> +		return;
> +	}
> +
> +	if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS) {
> +		DRM_ERROR("HuC: fw wasn't loaded. Nothing to authenticate\n");
> +		return;
> +	}
> +
> +	vma = i915_gem_object_ggtt_pin(huc->fw.obj, NULL, 0, 0, 0);
> +	if (IS_ERR(vma)) {
> +		DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
> +		return;
> +	}
> +
> +
> +	/* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
> +	I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
> +
> +	/* Specify auth action and where public signature is. */
> +	data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC;
> +	data[1] = i915_ggtt_offset(vma) + huc->fw.rsa_offset;
> +
> +	ret = intel_guc_send(guc, data, ARRAY_SIZE(data));
> +	if (ret) {
> +		DRM_ERROR("HuC: GuC did not ack Auth request\n");
> +		goto out;
> +	}
> +
> +	/* Check authentication status, it should be done by now */
> +	ret = wait_for((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) > 0, 50);

That's probably the wait_for() you intended to change.

> +	if (ret) {
> +		DRM_ERROR("HuC: Authentication failed\n");
> +		goto out;
> +	}
> +
> +out:
> +	i915_vma_unpin(vma);
> +}
> diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
> index 7df57c1..6ba56e18 100644
> --- a/drivers/gpu/drm/i915/intel_uc.h
> +++ b/drivers/gpu/drm/i915/intel_uc.h
> @@ -193,6 +193,7 @@ int intel_guc_sample_forcewake(struct intel_guc *guc);
>  int intel_guc_log_flush_complete(struct intel_guc *guc);
>  int intel_guc_log_flush(struct intel_guc *guc);
>  int intel_guc_log_control(struct intel_guc *guc, u32 control_val);
> +void intel_guc_auth_huc(struct drm_i915_private *dev_priv);
>  
>  /* intel_guc_loader.c */
>  extern void intel_guc_init(struct drm_i915_private *dev_priv);
> -- 
> 2.7.4
> 

-- 
Cheers,
Arek
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 7/8] drm/i915/huc: Support HuC authentication

[Anusha Srivatsa]

From: Peter Antoine <peter.antoine@intel.com>

The HuC authentication is done by host2guc call. The HuC RSA keys
are sent to GuC for authentication.

v2: rebased on top of drm-intel-nightly.
    changed name format and upped version 1.7.
v3: rebased on top of drm-intel-nightly.
v4: changed wait_for_automic to wait_for
v5: rebased.
v7: rebased.
v8: rebased.
v9: rebased. Rename intel_huc_auh() to intel_guc_auth_huc()
and place the prototype in intel_guc.h,correct the comments.
v10: rebased.
v11: rebased.
v12: rebased on top of drm-tip
v13: rebased. Moved intel_guc_auth_huc from i915_guc_submission.c
to intel_uc.c.Update dev to dev_priv in intel_guc_auth_huc().
Renamed HOST2GUC_ACTION_AUTHENTICATE_HUC TO INTEL_GUC_ACTION_
AUTHENTICATE_HUC
v14: rebased.
v15: rebased. Add newline on DRM_ERRORs that already dont have one.
v16: rebased. Replace wait_for with intel_wait_for_register() since
the latter employs sleep optimisations for quick responses- as pointed
out by Chris Wilson.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
Cc: Michal Wajdeczko <michal.wajdecko@intel.com>
Tested-by: Xiang Haihao <haihao.xiang@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
---
 drivers/gpu/drm/i915/intel_guc_fwif.h   |  1 +
 drivers/gpu/drm/i915/intel_guc_loader.c |  2 +
 drivers/gpu/drm/i915/intel_uc.c         | 70 ++++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_uc.h         |  1 +
 4 files changed, 72 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
index ed1ab40..ce4e05e 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -506,6 +506,7 @@ enum intel_guc_action {
 	INTEL_GUC_ACTION_EXIT_S_STATE = 0x502,
 	INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003,
 	INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000,
+	INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
 	INTEL_GUC_ACTION_LIMIT
 };
 
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index ed57ab3..0508054 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -529,6 +529,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
 		intel_uc_fw_status_repr(guc_fw->fetch_status),
 		intel_uc_fw_status_repr(guc_fw->load_status));
 
+	intel_guc_auth_huc(dev_priv);
+
 	if (i915.enable_guc_submission) {
 		if (i915.guc_log_level >= 0)
 			gen9_enable_guc_interrupts(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index c6be352..d1a4d79 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -46,7 +46,7 @@ static bool intel_guc_recv(struct intel_guc *guc, u32 *status)
 int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len)
 {
 	struct drm_i915_private *dev_priv = guc_to_i915(guc);
-	u32 status;
+	u32 status = 0;
 	int i;
 	int ret;
 
@@ -71,7 +71,11 @@ int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len)
 	 * up to that length of time, then switch to a slower sleep-wait loop.
 	 * No inte_guc_send command should ever take longer than 10ms.
 	 */
-	ret = wait_for_us(intel_guc_recv(guc, &status), 10);
+	ret = intel_wait_for_register(dev_priv,
+					HUC_STATUS2,
+					HUC_FW_VERIFIED,
+					HUC_FW_VERIFIED,
+					50);
 	if (ret)
 		ret = wait_for(intel_guc_recv(guc, &status), 10);
 	if (status != INTEL_GUC_STATUS_SUCCESS) {
@@ -140,3 +144,65 @@ int intel_guc_log_control(struct intel_guc *guc, u32 control_val)
 
 	return intel_guc_send(guc, action, ARRAY_SIZE(action));
 }
+
+/**
+ * intel_guc_auth_huc() - authenticate ucode
+ * @dev_priv: the drm_i915_device
+ *
+ * Triggers a HuC fw authentication request to the GuC via intel_guc_action_
+ * authenticate_huc interface.
+ * interface.
+ */
+void intel_guc_auth_huc(struct drm_i915_private *dev_priv)
+{
+	struct intel_guc *guc = &dev_priv->guc;
+	struct intel_huc *huc = &dev_priv->huc;
+	struct i915_vma *vma;
+	int ret;
+	u32 data[2];
+
+	/* Bypass the case where there is no HuC firmware */
+	if (huc->fw.fetch_status == INTEL_UC_FIRMWARE_NONE ||
+		huc->fw.load_status == INTEL_UC_FIRMWARE_NONE)
+		return;
+
+	if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS) {
+		DRM_ERROR("HuC: GuC fw wasn't loaded. Can't authenticate\n");
+		return;
+	}
+
+	if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS) {
+		DRM_ERROR("HuC: fw wasn't loaded. Nothing to authenticate\n");
+		return;
+	}
+
+	vma = i915_gem_object_ggtt_pin(huc->fw.obj, NULL, 0, 0, 0);
+	if (IS_ERR(vma)) {
+		DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
+		return;
+	}
+
+
+	/* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
+	I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
+
+	/* Specify auth action and where public signature is. */
+	data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC;
+	data[1] = i915_ggtt_offset(vma) + huc->fw.rsa_offset;
+
+	ret = intel_guc_send(guc, data, ARRAY_SIZE(data));
+	if (ret) {
+		DRM_ERROR("HuC: GuC did not ack Auth request\n");
+		goto out;
+	}
+
+	/* Check authentication status, it should be done by now */
+	ret = wait_for((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) > 0, 50);
+	if (ret) {
+		DRM_ERROR("HuC: Authentication failed\n");
+		goto out;
+	}
+
+out:
+	i915_vma_unpin(vma);
+}
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index 7df57c1..6ba56e18 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -193,6 +193,7 @@ int intel_guc_sample_forcewake(struct intel_guc *guc);
 int intel_guc_log_flush_complete(struct intel_guc *guc);
 int intel_guc_log_flush(struct intel_guc *guc);
 int intel_guc_log_control(struct intel_guc *guc, u32 control_val);
+void intel_guc_auth_huc(struct drm_i915_private *dev_priv);
 
 /* intel_guc_loader.c */
 extern void intel_guc_init(struct drm_i915_private *dev_priv);
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 7/8] drm/i915/huc: Support HuC authentication

[Anusha Srivatsa]

From: Peter Antoine <peter.antoine@intel.com>

The HuC authentication is done by host2guc call. The HuC RSA keys
are sent to GuC for authentication.

v2: rebased on top of drm-intel-nightly.
    changed name format and upped version 1.7.
v3: rebased on top of drm-intel-nightly.
v4: changed wait_for_automic to wait_for
v5: rebased.
v7: rebased.
v8: rebased.
v9: rebased. Rename intel_huc_auh() to intel_guc_auth_huc()
and place the prototype in intel_guc.h,correct the comments.
v10: rebased.
v11: rebased.
v12: rebased on top of drm-tip
v13: rebased. Moved intel_guc_auth_huc from i915_guc_submission.c
to intel_uc.c.Update dev to dev_priv in intel_guc_auth_huc().
Renamed HOST2GUC_ACTION_AUTHENTICATE_HUC TO INTEL_GUC_ACTION_
AUTHENTICATE_HUC
v14: rebased.
v15: rebased. Add newline on DRM_ERRORs that already dont have one.
v16: rebased. Replace wait_for with intel_wait_for_register() since
the latter employs sleep optimisations for quick responses- as pointed
out by Chris Wilson.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
Cc: Michal Wajdeczko <michal.wajdecko@intel.com>
Tested-by: Xiang Haihao <haihao.xiang@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
---
 drivers/gpu/drm/i915/intel_guc_fwif.h   |  1 +
 drivers/gpu/drm/i915/intel_guc_loader.c |  2 +
 drivers/gpu/drm/i915/intel_uc.c         | 68 ++++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_uc.h         |  1 +
 4 files changed, 71 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
index ed1ab40..ce4e05e 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -506,6 +506,7 @@ enum intel_guc_action {
 	INTEL_GUC_ACTION_EXIT_S_STATE = 0x502,
 	INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003,
 	INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000,
+	INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
 	INTEL_GUC_ACTION_LIMIT
 };
 
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index a6ac046..be76583 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -529,6 +529,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
 		intel_uc_fw_status_repr(guc_fw->fetch_status),
 		intel_uc_fw_status_repr(guc_fw->load_status));
 
+	intel_guc_auth_huc(dev_priv);
+
 	if (i915.enable_guc_submission) {
 		if (i915.guc_log_level >= 0)
 			gen9_enable_guc_interrupts(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index c6be352..dccd39c 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -71,7 +71,11 @@ int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len)
 	 * up to that length of time, then switch to a slower sleep-wait loop.
 	 * No inte_guc_send command should ever take longer than 10ms.
 	 */
-	ret = wait_for_us(intel_guc_recv(guc, &status), 10);
+	ret = intel_wait_for_register(dev_priv,
+					HUC_STATUS2,
+					HUC_FW_VERIFIED,
+					HUC_FW_VERIFIED,
+					50);
 	if (ret)
 		ret = wait_for(intel_guc_recv(guc, &status), 10);
 	if (status != INTEL_GUC_STATUS_SUCCESS) {
@@ -140,3 +144,65 @@ int intel_guc_log_control(struct intel_guc *guc, u32 control_val)
 
 	return intel_guc_send(guc, action, ARRAY_SIZE(action));
 }
+
+/**
+ * intel_guc_auth_huc() - authenticate ucode
+ * @dev_priv: the drm_i915_device
+ *
+ * Triggers a HuC fw authentication request to the GuC via intel_guc_action_
+ * authenticate_huc interface.
+ * interface.
+ */
+void intel_guc_auth_huc(struct drm_i915_private *dev_priv)
+{
+	struct intel_guc *guc = &dev_priv->guc;
+	struct intel_huc *huc = &dev_priv->huc;
+	struct i915_vma *vma;
+	int ret;
+	u32 data[2];
+
+	/* Bypass the case where there is no HuC firmware */
+	if (huc->fw.fetch_status == INTEL_UC_FIRMWARE_NONE ||
+		huc->fw.load_status == INTEL_UC_FIRMWARE_NONE)
+		return;
+
+	if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS) {
+		DRM_ERROR("HuC: GuC fw wasn't loaded. Can't authenticate\n");
+		return;
+	}
+
+	if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS) {
+		DRM_ERROR("HuC: fw wasn't loaded. Nothing to authenticate\n");
+		return;
+	}
+
+	vma = i915_gem_object_ggtt_pin(huc->fw.uc_fw_obj, NULL, 0, 0, 0);
+	if (IS_ERR(vma)) {
+		DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
+		return;
+	}
+
+
+	/* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
+	I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
+
+	/* Specify auth action and where public signature is. */
+	data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC;
+	data[1] = i915_ggtt_offset(vma) + huc->fw.rsa_offset;
+
+	ret = intel_guc_send(guc, data, ARRAY_SIZE(data));
+	if (ret) {
+		DRM_ERROR("HuC: GuC did not ack Auth request\n");
+		goto out;
+	}
+
+	/* Check authentication status, it should be done by now */
+	ret = wait_for((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) > 0, 50);
+	if (ret) {
+		DRM_ERROR("HuC: Authentication failed\n");
+		goto out;
+	}
+
+out:
+	i915_vma_unpin(vma);
+}
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index 00c0986..2aa0304 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -193,6 +193,7 @@ int intel_guc_sample_forcewake(struct intel_guc *guc);
 int intel_guc_log_flush_complete(struct intel_guc *guc);
 int intel_guc_log_flush(struct intel_guc *guc);
 int intel_guc_log_control(struct intel_guc *guc, u32 control_val);
+void intel_guc_auth_huc(struct drm_i915_private *dev_priv);
 
 /* intel_guc_loader.c */
 extern void intel_guc_init(struct drm_i915_private *dev_priv);
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 7/8] drm/i915/huc: Support HuC authentication

[Arkadiusz Hiler]

On Thu, Dec 15, 2016 at 02:29:49PM -0800, anushasr wrote:
> From: Peter Antoine <peter.antoine@intel.com>
> 
> The HuC authentication is done by host2guc call. The HuC RSA keys
> are sent to GuC for authentication.
> 
> v2: rebased on top of drm-intel-nightly.
>     changed name format and upped version 1.7.
> v3: rebased on top of drm-intel-nightly.
> v4: changed wait_for_automic to wait_for
> v5: rebased.
> v7: rebased.
> v8: rebased.
> v9: rebased. Rename intel_huc_auh() to intel_guc_auth_huc()
> and place the prototype in intel_guc.h,correct the comments.
> v10: rebased.
> v11: rebased.
> v12: rebased on top of drm-tip
> v13: rebased. Moved intel_guc_auth_huc from i915_guc_submission.c
> to intel_uc.c.Update dev to dev_priv in intel_guc_auth_huc().
> Renamed HOST2GUC_ACTION_AUTHENTICATE_HUC TO INTEL_GUC_ACTION_
> AUTHENTICATE_HUC
> v14: rebased.
> 
> Tested-by: Xiang Haihao <haihao.xiang@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Alex Dai <yu.dai@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_guc_fwif.h   |  1 +
>  drivers/gpu/drm/i915/intel_guc_loader.c |  2 ++
>  drivers/gpu/drm/i915/intel_uc.c         | 62 +++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_uc.h         |  1 +
>  4 files changed, 66 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
> index ed1ab40..ce4e05e 100644
> --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
> @@ -506,6 +506,7 @@ enum intel_guc_action {
>  	INTEL_GUC_ACTION_EXIT_S_STATE = 0x502,
>  	INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003,
>  	INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000,
> +	INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
>  	INTEL_GUC_ACTION_LIMIT
>  };
>  
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> index 2257495..7605f36 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -529,6 +529,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
>  		intel_uc_fw_status_repr(guc_fw->fetch_status),
>  		intel_uc_fw_status_repr(guc_fw->load_status));
>  
> +	intel_guc_auth_huc(dev_priv);
> +
>  	if (i915.enable_guc_submission) {
>  		if (i915.guc_log_level >= 0)
>  			gen9_enable_guc_interrupts(dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
> index 8ae6795..b90ac57 100644
> --- a/drivers/gpu/drm/i915/intel_uc.c
> +++ b/drivers/gpu/drm/i915/intel_uc.c
> @@ -138,3 +138,65 @@ int intel_guc_log_control(struct intel_guc *guc, u32 control_val)
>  
>  	return intel_guc_send(guc, action, ARRAY_SIZE(action));
>  }
> +
> +/**
> + * intel_guc_auth_huc() - authenticate ucode
> + * @dev_priv: the drm_i915_device
> + *
> + * Triggers a HuC fw authentication request to the GuC via intel_guc_action_
> + * authenticate_huc interface.
> + * interface.
> + */
> +void intel_guc_auth_huc(struct drm_i915_private *dev_priv)
> +{
> +	struct intel_guc *guc = &dev_priv->guc;
> +	struct intel_huc *huc = &dev_priv->huc;
> +	struct i915_vma *vma;
> +	int ret;
> +	u32 data[2];
> +
> +	/* Bypass the case where there is no HuC firmware */
> +	if (huc->fw.fetch_status == INTEL_UC_FIRMWARE_NONE ||
> +		huc->fw.load_status == INTEL_UC_FIRMWARE_NONE)
> +		return;
> +
> +	if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS) {
> +		DRM_ERROR("HuC: GuC fw wasn't loaded. Can't authenticate");

Why this DRM_ERROR does not have tailing "\n"?
Same goes for couple more in here.

> +		return;
> +	}
> +
> +	if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS) {
> +		DRM_ERROR("HuC: fw wasn't loaded. Nothing to authenticate");
> +		return;
> +	}
> +
> +	vma = i915_gem_object_ggtt_pin(huc->fw.uc_fw_obj, NULL, 0, 0, 0);
> +	if (IS_ERR(vma)) {
> +		DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
> +		return;
> +	}
> +
> +
> +	/* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
> +	I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
> +
> +	/* Specify auth action and where public signature is. */
> +	data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC;
> +	data[1] = i915_ggtt_offset(vma) + huc->fw.rsa_offset;
> +
> +	ret = intel_guc_send(guc, data, ARRAY_SIZE(data));
> +	if (ret) {
> +		DRM_ERROR("HuC: GuC did not ack Auth request\n");
> +		goto out;
> +	}
> +
> +	/* Check authentication status, it should be done by now */
> +	ret = wait_for((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) > 0, 50);
> +	if (ret) {
> +		DRM_ERROR("HuC: Authentication failed\n");
> +		goto out;
> +	}
> +
> +out:
> +	i915_vma_unpin(vma);
> +}
> diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
> index 57aef56..e69d47c 100644
> --- a/drivers/gpu/drm/i915/intel_uc.h
> +++ b/drivers/gpu/drm/i915/intel_uc.h
> @@ -192,6 +192,7 @@ int intel_guc_sample_forcewake(struct intel_guc *guc);
>  int intel_guc_log_flush_complete(struct intel_guc *guc);
>  int intel_guc_log_flush(struct intel_guc *guc);
>  int intel_guc_log_control(struct intel_guc *guc, u32 control_val);
> +void intel_guc_auth_huc(struct drm_i915_private *dev_priv);
>  
>  /* intel_guc_loader.c */
>  extern void intel_guc_init(struct drm_i915_private *dev_priv);
> -- 
> 2.7.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Cheers,
Arek
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 7/8] drm/i915/huc: Support HuC authentication

[anushasr]

From: Peter Antoine <peter.antoine@intel.com>

The HuC authentication is done by host2guc call. The HuC RSA keys
are sent to GuC for authentication.

v2: rebased on top of drm-intel-nightly.
    changed name format and upped version 1.7.
v3: rebased on top of drm-intel-nightly.
v4: changed wait_for_automic to wait_for
v5: rebased.
v7: rebased.
v8: rebased.
v9: rebased. Rename intel_huc_auh() to intel_guc_auth_huc()
and place the prototype in intel_guc.h,correct the comments.
v10: rebased.
v11: rebased.
v12: rebased on top of drm-tip
v13: rebased. Moved intel_guc_auth_huc from i915_guc_submission.c
to intel_uc.c.Update dev to dev_priv in intel_guc_auth_huc().
Renamed HOST2GUC_ACTION_AUTHENTICATE_HUC TO INTEL_GUC_ACTION_
AUTHENTICATE_HUC
v14: rebased.

Tested-by: Xiang Haihao <haihao.xiang@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
---
 drivers/gpu/drm/i915/intel_guc_fwif.h   |  1 +
 drivers/gpu/drm/i915/intel_guc_loader.c |  2 ++
 drivers/gpu/drm/i915/intel_uc.c         | 62 +++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_uc.h         |  1 +
 4 files changed, 66 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
index ed1ab40..ce4e05e 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -506,6 +506,7 @@ enum intel_guc_action {
 	INTEL_GUC_ACTION_EXIT_S_STATE = 0x502,
 	INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003,
 	INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000,
+	INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
 	INTEL_GUC_ACTION_LIMIT
 };
 
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 2257495..7605f36 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -529,6 +529,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
 		intel_uc_fw_status_repr(guc_fw->fetch_status),
 		intel_uc_fw_status_repr(guc_fw->load_status));
 
+	intel_guc_auth_huc(dev_priv);
+
 	if (i915.enable_guc_submission) {
 		if (i915.guc_log_level >= 0)
 			gen9_enable_guc_interrupts(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 8ae6795..b90ac57 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -138,3 +138,65 @@ int intel_guc_log_control(struct intel_guc *guc, u32 control_val)
 
 	return intel_guc_send(guc, action, ARRAY_SIZE(action));
 }
+
+/**
+ * intel_guc_auth_huc() - authenticate ucode
+ * @dev_priv: the drm_i915_device
+ *
+ * Triggers a HuC fw authentication request to the GuC via intel_guc_action_
+ * authenticate_huc interface.
+ * interface.
+ */
+void intel_guc_auth_huc(struct drm_i915_private *dev_priv)
+{
+	struct intel_guc *guc = &dev_priv->guc;
+	struct intel_huc *huc = &dev_priv->huc;
+	struct i915_vma *vma;
+	int ret;
+	u32 data[2];
+
+	/* Bypass the case where there is no HuC firmware */
+	if (huc->fw.fetch_status == INTEL_UC_FIRMWARE_NONE ||
+		huc->fw.load_status == INTEL_UC_FIRMWARE_NONE)
+		return;
+
+	if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS) {
+		DRM_ERROR("HuC: GuC fw wasn't loaded. Can't authenticate");
+		return;
+	}
+
+	if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS) {
+		DRM_ERROR("HuC: fw wasn't loaded. Nothing to authenticate");
+		return;
+	}
+
+	vma = i915_gem_object_ggtt_pin(huc->fw.uc_fw_obj, NULL, 0, 0, 0);
+	if (IS_ERR(vma)) {
+		DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
+		return;
+	}
+
+
+	/* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
+	I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
+
+	/* Specify auth action and where public signature is. */
+	data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC;
+	data[1] = i915_ggtt_offset(vma) + huc->fw.rsa_offset;
+
+	ret = intel_guc_send(guc, data, ARRAY_SIZE(data));
+	if (ret) {
+		DRM_ERROR("HuC: GuC did not ack Auth request\n");
+		goto out;
+	}
+
+	/* Check authentication status, it should be done by now */
+	ret = wait_for((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) > 0, 50);
+	if (ret) {
+		DRM_ERROR("HuC: Authentication failed\n");
+		goto out;
+	}
+
+out:
+	i915_vma_unpin(vma);
+}
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index 57aef56..e69d47c 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -192,6 +192,7 @@ int intel_guc_sample_forcewake(struct intel_guc *guc);
 int intel_guc_log_flush_complete(struct intel_guc *guc);
 int intel_guc_log_flush(struct intel_guc *guc);
 int intel_guc_log_control(struct intel_guc *guc, u32 control_val);
+void intel_guc_auth_huc(struct drm_i915_private *dev_priv);
 
 /* intel_guc_loader.c */
 extern void intel_guc_init(struct drm_i915_private *dev_priv);
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 7/8] drm/i915/huc: Support HuC authentication

[Srivatsa, Anusha]

>-----Original Message-----
>From: Michal Wajdeczko [mailto:michal.wajdeczko@linux.intel.com]
>Sent: Friday, December 9, 2016 4:37 AM
>To: Srivatsa, Anusha <anusha.srivatsa@intel.com>
>Cc: intel-gfx@lists.freedesktop.org; Alex Dai <yu.dai@intel.com>; Peter Antoine
><peter.antoine@intel.com>
>Subject: Re: [Intel-gfx] [PATCH 7/8] drm/i915/huc: Support HuC authentication
>
>On Thu, Dec 08, 2016 at 03:02:18PM -0800, anushasr wrote:
>> From: Peter Antoine <peter.antoine@intel.com>
>>
>> The HuC authentication is done by host2guc call. The HuC RSA keys are
>> sent to GuC for authentication.
>>
>> v2: rebased on top of drm-intel-nightly.
>>     changed name format and upped version 1.7.
>> v3: rebased on top of drm-intel-nightly.
>> v4: changed wait_for_automic to wait_for
>> v5: rebased.
>> v7: rebased.
>> v8: rebased.
>> v9: rebased. Rename intel_huc_auh() to intel_guc_auth_huc() and place
>> the prototype in intel_guc.h,correct the comments.
>> v10: rebased.
>> v11: rebased.
>> v12: rebased on top of drm-tip
>> v13: rebased. Moved intel_guc_auth_huc from i915_guc_submission.c to
>> intel_uc.c.Update dev to dev_priv in intel_guc_auth_huc().
>> Renamed HOST2GUC_ACTION_AUTHENTICATE_HUC TO INTEL_GUC_ACTION_
>> AUTHENTICATE_HUC
>>
>> Tested-by: Xiang Haihao <haihao.xiang@intel.com>
>> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>> Signed-off-by: Alex Dai <yu.dai@intel.com>
>> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
>> ---
>>  drivers/gpu/drm/i915/intel_guc_fwif.h   |  1 +
>>  drivers/gpu/drm/i915/intel_guc_loader.c |  2 ++
>>  drivers/gpu/drm/i915/intel_uc.c         | 61
>+++++++++++++++++++++++++++++++++
>>  drivers/gpu/drm/i915/intel_uc.h         |  1 +
>>  4 files changed, 65 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h
>> b/drivers/gpu/drm/i915/intel_guc_fwif.h
>> index c1e7faf..94a974d 100644
>> --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
>> +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
>> @@ -504,6 +504,7 @@ enum intel_guc_action {
>>  	INTEL_GUC_ACTION_EXIT_S_STATE = 0x502,
>>  	INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003,
>>  	INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000,
>> +	INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
>>  	INTEL_GUC_ACTION_LIMIT
>>  };
>>
>> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
>> b/drivers/gpu/drm/i915/intel_guc_loader.c
>> index b971351..89d092b 100644
>> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
>> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
>> @@ -529,6 +529,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
>>  		intel_uc_fw_status_repr(guc_fw->fetch_status),
>>  		intel_uc_fw_status_repr(guc_fw->load_status));
>>
>> +	intel_guc_auth_huc(dev_priv);
>> +
>>  	if (i915.enable_guc_submission) {
>>  		if (i915.guc_log_level >= 0)
>>  			gen9_enable_guc_interrupts(dev_priv);
>> diff --git a/drivers/gpu/drm/i915/intel_uc.c
>> b/drivers/gpu/drm/i915/intel_uc.c index 8ae6795..445b9ad 100644
>> --- a/drivers/gpu/drm/i915/intel_uc.c
>> +++ b/drivers/gpu/drm/i915/intel_uc.c
>> @@ -138,3 +138,64 @@ int intel_guc_log_control(struct intel_guc *guc,
>> u32 control_val)
>>
>>  	return intel_guc_send(guc, action, ARRAY_SIZE(action));  }
>> +
>> +/**
>> + * intel_guc_auth_huc() - authenticate ucode
>> + * @dev: the drm device
>
>Mismatched param name.
>
>
>> + *
>> + * Triggers a HuC fw authentication request to the GuC via host-2-guc
>> + * interface.
>> + */
>> +void intel_guc_auth_huc(struct drm_i915_private *dev_priv)
>
>Can we use *guc as the first param to match other intel_guc functions?
>
In function intel_guc_init() and intel_guc_load() we are using dev_priv as the first parameter..... 

>> +{
>> +	struct intel_guc *guc = &dev_priv->guc;
>> +	struct intel_huc *huc = &dev_priv->huc;
>> +	struct i915_vma *vma;
>> +	int ret;
>> +	u32 data[2];
>> +
>> +	/* Bypass the case where there is no HuC firmware */
>> +	if (huc->huc_fw.fetch_status == UC_FIRMWARE_NONE ||
>> +		huc->huc_fw.load_status == UC_FIRMWARE_NONE)
>> +		return;
>> +
>> +	if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS) {
>> +		DRM_ERROR("HuC: GuC fw wasn't loaded. Can't authenticate");
>
>Hmm, this looks like late handling of earlier error.
>Note that other functions in this file assume that Guc is working fine.
Michal, after intel_uc_init_early() which initializes a mutex lock, intel_guc_auth_huc() is the first function that the control goes to and hence all checking happens here. If anything is wrong a suitable error message is displayed and we return out immediately. If on the other hand things are proper, as expected post error checking, the other functions are called....

Hope this clears your concern.

-Anusha
>
>> +		return;
>> +	}
>> +
>> +	if (huc->huc_fw.load_status != UC_FIRMWARE_SUCCESS) {
>> +		DRM_ERROR("HuC: fw wasn't loaded. Nothing to authenticate");
>> +		return;
>> +	}
>> +
>> +	vma = i915_gem_object_ggtt_pin(huc->huc_fw.uc_fw_obj, NULL, 0, 0,
>0);
>> +	if (IS_ERR(vma)) {
>> +		DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
>> +		return;
>> +	}
>> +
>> +
>> +	/* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
>> +	I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
>> +
>> +	/* Specify auth action and where public signature is. */
>> +	data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC;
>> +	data[1] = i915_ggtt_offset(vma) + huc->huc_fw.rsa_offset;
>> +
>> +	ret = intel_guc_send(guc, data, ARRAY_SIZE(data));
>
>Hmm, maybe this function shall be split into two parts:
>
>intel_huc_auth() in intel_huc_loader.c that contains most of the logic from
>current function, but calls intel_guc_auth_huc() from this file that just sends
>action to the guc (similar to other simple functions in this file.
>
The intention is to make intel_guc_auth_huc() as simple as other functions in the file?
Two points on my mind-
1. Wont splitting into intel_huc_auth() and intel_guc_auth_huc() be more confusing than just intel_guc_auth_huc?
2.Even on splitting we will have only the preliminary check - check if guc is loaded, check if huc is loaded in intel_huc_Auth. The actual specification of authentication action, sending it to guc, checking if that is a success or not has to happen in intel_huc_auth_guc().
Am I correct?  

>> +	if (ret) {
>> +		DRM_ERROR("HuC: GuC did not ack Auth request\n");
>> +		goto out;
>> +	}
>> +
>> +	/* Check authentication status, it should be done by now */
>> +	ret = wait_for((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) > 0,
>50);
>> +	if (ret) {
>> +		DRM_ERROR("HuC: Authentication failed\n");
>> +		goto out;
>> +	}
>> +
>> +out:
>> +	i915_vma_unpin(vma);
>> +}
>> diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
>> index ac92946..1db8bc2 100644
>> --- a/drivers/gpu/drm/i915/intel_uc.h
>> +++ b/drivers/gpu/drm/i915/intel_uc.h
>> @@ -196,6 +196,7 @@ int intel_guc_sample_forcewake(struct intel_guc *guc);
>>  int intel_guc_log_flush_complete(struct intel_guc *guc);
>>  int intel_guc_log_flush(struct intel_guc *guc);
>>  int intel_guc_log_control(struct intel_guc *guc, u32 control_val);
>> +void intel_guc_auth_huc(struct drm_i915_private *dev_priv);
>>
>>  /* intel_guc_loader.c */
>>  extern void intel_guc_init(struct drm_i915_private *dev_priv);
>> --
>> 2.7.4
>>
Cheers,
Anusha 
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 7/8] drm/i915/huc: Support HuC authentication

[Michal Wajdeczko]

On Thu, Dec 08, 2016 at 03:02:18PM -0800, anushasr wrote:
> From: Peter Antoine <peter.antoine@intel.com>
> 
> The HuC authentication is done by host2guc call. The HuC RSA keys
> are sent to GuC for authentication.
> 
> v2: rebased on top of drm-intel-nightly.
>     changed name format and upped version 1.7.
> v3: rebased on top of drm-intel-nightly.
> v4: changed wait_for_automic to wait_for
> v5: rebased.
> v7: rebased.
> v8: rebased.
> v9: rebased. Rename intel_huc_auh() to intel_guc_auth_huc()
> and place the prototype in intel_guc.h,correct the comments.
> v10: rebased.
> v11: rebased.
> v12: rebased on top of drm-tip
> v13: rebased. Moved intel_guc_auth_huc from i915_guc_submission.c
> to intel_uc.c.Update dev to dev_priv in intel_guc_auth_huc().
> Renamed HOST2GUC_ACTION_AUTHENTICATE_HUC TO INTEL_GUC_ACTION_
> AUTHENTICATE_HUC
> 
> Tested-by: Xiang Haihao <haihao.xiang@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Alex Dai <yu.dai@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_guc_fwif.h   |  1 +
>  drivers/gpu/drm/i915/intel_guc_loader.c |  2 ++
>  drivers/gpu/drm/i915/intel_uc.c         | 61 +++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_uc.h         |  1 +
>  4 files changed, 65 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
> index c1e7faf..94a974d 100644
> --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
> @@ -504,6 +504,7 @@ enum intel_guc_action {
>  	INTEL_GUC_ACTION_EXIT_S_STATE = 0x502,
>  	INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003,
>  	INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000,
> +	INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
>  	INTEL_GUC_ACTION_LIMIT
>  };
>  
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> index b971351..89d092b 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -529,6 +529,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
>  		intel_uc_fw_status_repr(guc_fw->fetch_status),
>  		intel_uc_fw_status_repr(guc_fw->load_status));
>  
> +	intel_guc_auth_huc(dev_priv);
> +
>  	if (i915.enable_guc_submission) {
>  		if (i915.guc_log_level >= 0)
>  			gen9_enable_guc_interrupts(dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
> index 8ae6795..445b9ad 100644
> --- a/drivers/gpu/drm/i915/intel_uc.c
> +++ b/drivers/gpu/drm/i915/intel_uc.c
> @@ -138,3 +138,64 @@ int intel_guc_log_control(struct intel_guc *guc, u32 control_val)
>  
>  	return intel_guc_send(guc, action, ARRAY_SIZE(action));
>  }
> +
> +/**
> + * intel_guc_auth_huc() - authenticate ucode
> + * @dev: the drm device

Mismatched param name.


> + *
> + * Triggers a HuC fw authentication request to the GuC via host-2-guc
> + * interface.
> + */
> +void intel_guc_auth_huc(struct drm_i915_private *dev_priv)

Can we use *guc as the first param to match other intel_guc functions?


> +{
> +	struct intel_guc *guc = &dev_priv->guc;
> +	struct intel_huc *huc = &dev_priv->huc;
> +	struct i915_vma *vma;
> +	int ret;
> +	u32 data[2];
> +
> +	/* Bypass the case where there is no HuC firmware */
> +	if (huc->huc_fw.fetch_status == UC_FIRMWARE_NONE ||
> +		huc->huc_fw.load_status == UC_FIRMWARE_NONE)
> +		return;
> +
> +	if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS) {
> +		DRM_ERROR("HuC: GuC fw wasn't loaded. Can't authenticate");

Hmm, this looks like late handling of earlier error.
Note that other functions in this file assume that Guc is working fine.


> +		return;
> +	}
> +
> +	if (huc->huc_fw.load_status != UC_FIRMWARE_SUCCESS) {
> +		DRM_ERROR("HuC: fw wasn't loaded. Nothing to authenticate");
> +		return;
> +	}
> +
> +	vma = i915_gem_object_ggtt_pin(huc->huc_fw.uc_fw_obj, NULL, 0, 0, 0);
> +	if (IS_ERR(vma)) {
> +		DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
> +		return;
> +	}
> +
> +
> +	/* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
> +	I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
> +
> +	/* Specify auth action and where public signature is. */
> +	data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC;
> +	data[1] = i915_ggtt_offset(vma) + huc->huc_fw.rsa_offset;
> +
> +	ret = intel_guc_send(guc, data, ARRAY_SIZE(data));

Hmm, maybe this function shall be split into two parts:

intel_huc_auth() in intel_huc_loader.c that contains most of the logic
from current function, but calls intel_guc_auth_huc() from this file that 
just sends action to the guc (similar to other simple functions in this file.


> +	if (ret) {
> +		DRM_ERROR("HuC: GuC did not ack Auth request\n");
> +		goto out;
> +	}
> +
> +	/* Check authentication status, it should be done by now */
> +	ret = wait_for((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) > 0, 50);
> +	if (ret) {
> +		DRM_ERROR("HuC: Authentication failed\n");
> +		goto out;
> +	}
> +
> +out:
> +	i915_vma_unpin(vma);
> +}
> diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
> index ac92946..1db8bc2 100644
> --- a/drivers/gpu/drm/i915/intel_uc.h
> +++ b/drivers/gpu/drm/i915/intel_uc.h
> @@ -196,6 +196,7 @@ int intel_guc_sample_forcewake(struct intel_guc *guc);
>  int intel_guc_log_flush_complete(struct intel_guc *guc);
>  int intel_guc_log_flush(struct intel_guc *guc);
>  int intel_guc_log_control(struct intel_guc *guc, u32 control_val);
> +void intel_guc_auth_huc(struct drm_i915_private *dev_priv);
>  
>  /* intel_guc_loader.c */
>  extern void intel_guc_init(struct drm_i915_private *dev_priv);
> -- 
> 2.7.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 7/8] drm/i915/huc: Support HuC authentication

[Arkadiusz Hiler]

On Thu, Dec 08, 2016 at 03:02:18PM -0800, anushasr wrote:
> From: Peter Antoine <peter.antoine@intel.com>
> 
> The HuC authentication is done by host2guc call. The HuC RSA keys
> are sent to GuC for authentication.
> 
> v2: rebased on top of drm-intel-nightly.
>     changed name format and upped version 1.7.
> v3: rebased on top of drm-intel-nightly.
> v4: changed wait_for_automic to wait_for
> v5: rebased.
> v7: rebased.
> v8: rebased.
> v9: rebased. Rename intel_huc_auh() to intel_guc_auth_huc()
> and place the prototype in intel_guc.h,correct the comments.
> v10: rebased.
> v11: rebased.
> v12: rebased on top of drm-tip
> v13: rebased. Moved intel_guc_auth_huc from i915_guc_submission.c
> to intel_uc.c.Update dev to dev_priv in intel_guc_auth_huc().
> Renamed HOST2GUC_ACTION_AUTHENTICATE_HUC TO INTEL_GUC_ACTION_
> AUTHENTICATE_HUC
> 
> Tested-by: Xiang Haihao <haihao.xiang@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Alex Dai <yu.dai@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_guc_fwif.h   |  1 +
>  drivers/gpu/drm/i915/intel_guc_loader.c |  2 ++
>  drivers/gpu/drm/i915/intel_uc.c         | 61 +++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_uc.h         |  1 +
>  4 files changed, 65 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
> index c1e7faf..94a974d 100644
> --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
> @@ -504,6 +504,7 @@ enum intel_guc_action {
>  	INTEL_GUC_ACTION_EXIT_S_STATE = 0x502,
>  	INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003,
>  	INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000,
> +	INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
>  	INTEL_GUC_ACTION_LIMIT
>  };
>  
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> index b971351..89d092b 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -529,6 +529,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
>  		intel_uc_fw_status_repr(guc_fw->fetch_status),
>  		intel_uc_fw_status_repr(guc_fw->load_status));
>  
> +	intel_guc_auth_huc(dev_priv);
> +
>  	if (i915.enable_guc_submission) {
>  		if (i915.guc_log_level >= 0)
>  			gen9_enable_guc_interrupts(dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
> index 8ae6795..445b9ad 100644
> --- a/drivers/gpu/drm/i915/intel_uc.c
> +++ b/drivers/gpu/drm/i915/intel_uc.c
> @@ -138,3 +138,64 @@ int intel_guc_log_control(struct intel_guc *guc, u32 control_val)
>  
>  	return intel_guc_send(guc, action, ARRAY_SIZE(action));
>  }
> +
> +/**
> + * intel_guc_auth_huc() - authenticate ucode
> + * @dev: the drm device
> + *
> + * Triggers a HuC fw authentication request to the GuC via host-2-guc
> + * interface.
> + */
> +void intel_guc_auth_huc(struct drm_i915_private *dev_priv)
> +{
> +	struct intel_guc *guc = &dev_priv->guc;
> +	struct intel_huc *huc = &dev_priv->huc;
> +	struct i915_vma *vma;
> +	int ret;
> +	u32 data[2];
> +
> +	/* Bypass the case where there is no HuC firmware */
> +	if (huc->huc_fw.fetch_status == UC_FIRMWARE_NONE ||
> +		huc->huc_fw.load_status == UC_FIRMWARE_NONE)
> +		return;
> +
> +	if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS) {
> +		DRM_ERROR("HuC: GuC fw wasn't loaded. Can't authenticate");
> +		return;
> +	}
> +
> +	if (huc->huc_fw.load_status != UC_FIRMWARE_SUCCESS) {
> +		DRM_ERROR("HuC: fw wasn't loaded. Nothing to authenticate");
> +		return;
> +	}
> +
> +	vma = i915_gem_object_ggtt_pin(huc->huc_fw.uc_fw_obj, NULL, 0, 0, 0);
> +	if (IS_ERR(vma)) {
> +		DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
> +		return;
> +	}
> +
> +
> +	/* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
> +	I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
> +
> +	/* Specify auth action and where public signature is. */
> +	data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC;
> +	data[1] = i915_ggtt_offset(vma) + huc->huc_fw.rsa_offset;
> +
> +	ret = intel_guc_send(guc, data, ARRAY_SIZE(data));
> +	if (ret) {
> +		DRM_ERROR("HuC: GuC did not ack Auth request\n");
> +		goto out;
> +	}
> +
> +	/* Check authentication status, it should be done by now */
> +	ret = wait_for((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) > 0, 50);
> +	if (ret) {
> +		DRM_ERROR("HuC: Authentication failed\n");
> +		goto out;
> +	}
> +
> +out:
> +	i915_vma_unpin(vma);
> +}
> diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
> index ac92946..1db8bc2 100644
> --- a/drivers/gpu/drm/i915/intel_uc.h
> +++ b/drivers/gpu/drm/i915/intel_uc.h
> @@ -196,6 +196,7 @@ int intel_guc_sample_forcewake(struct intel_guc *guc);
>  int intel_guc_log_flush_complete(struct intel_guc *guc);
>  int intel_guc_log_flush(struct intel_guc *guc);
>  int intel_guc_log_control(struct intel_guc *guc, u32 control_val);
> +void intel_guc_auth_huc(struct drm_i915_private *dev_priv);
>  
>  /* intel_guc_loader.c */
>  extern void intel_guc_init(struct drm_i915_private *dev_priv);
> -- 
> 2.7.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Cheers,
Arek
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 7/8] drm/i915/huc: Support HuC authentication

[anushasr]

From: Peter Antoine <peter.antoine@intel.com>

The HuC authentication is done by host2guc call. The HuC RSA keys
are sent to GuC for authentication.

v2: rebased on top of drm-intel-nightly.
    changed name format and upped version 1.7.
v3: rebased on top of drm-intel-nightly.
v4: changed wait_for_automic to wait_for
v5: rebased.
v7: rebased.
v8: rebased.
v9: rebased. Rename intel_huc_auh() to intel_guc_auth_huc()
and place the prototype in intel_guc.h,correct the comments.
v10: rebased.
v11: rebased.
v12: rebased on top of drm-tip
v13: rebased. Moved intel_guc_auth_huc from i915_guc_submission.c
to intel_uc.c.Update dev to dev_priv in intel_guc_auth_huc().
Renamed HOST2GUC_ACTION_AUTHENTICATE_HUC TO INTEL_GUC_ACTION_
AUTHENTICATE_HUC

Tested-by: Xiang Haihao <haihao.xiang@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
---
 drivers/gpu/drm/i915/intel_guc_fwif.h   |  1 +
 drivers/gpu/drm/i915/intel_guc_loader.c |  2 ++
 drivers/gpu/drm/i915/intel_uc.c         | 61 +++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_uc.h         |  1 +
 4 files changed, 65 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
index c1e7faf..94a974d 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -504,6 +504,7 @@ enum intel_guc_action {
 	INTEL_GUC_ACTION_EXIT_S_STATE = 0x502,
 	INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003,
 	INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000,
+	INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
 	INTEL_GUC_ACTION_LIMIT
 };
 
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index b971351..89d092b 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -529,6 +529,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
 		intel_uc_fw_status_repr(guc_fw->fetch_status),
 		intel_uc_fw_status_repr(guc_fw->load_status));
 
+	intel_guc_auth_huc(dev_priv);
+
 	if (i915.enable_guc_submission) {
 		if (i915.guc_log_level >= 0)
 			gen9_enable_guc_interrupts(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 8ae6795..445b9ad 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -138,3 +138,64 @@ int intel_guc_log_control(struct intel_guc *guc, u32 control_val)
 
 	return intel_guc_send(guc, action, ARRAY_SIZE(action));
 }
+
+/**
+ * intel_guc_auth_huc() - authenticate ucode
+ * @dev: the drm device
+ *
+ * Triggers a HuC fw authentication request to the GuC via host-2-guc
+ * interface.
+ */
+void intel_guc_auth_huc(struct drm_i915_private *dev_priv)
+{
+	struct intel_guc *guc = &dev_priv->guc;
+	struct intel_huc *huc = &dev_priv->huc;
+	struct i915_vma *vma;
+	int ret;
+	u32 data[2];
+
+	/* Bypass the case where there is no HuC firmware */
+	if (huc->huc_fw.fetch_status == UC_FIRMWARE_NONE ||
+		huc->huc_fw.load_status == UC_FIRMWARE_NONE)
+		return;
+
+	if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS) {
+		DRM_ERROR("HuC: GuC fw wasn't loaded. Can't authenticate");
+		return;
+	}
+
+	if (huc->huc_fw.load_status != UC_FIRMWARE_SUCCESS) {
+		DRM_ERROR("HuC: fw wasn't loaded. Nothing to authenticate");
+		return;
+	}
+
+	vma = i915_gem_object_ggtt_pin(huc->huc_fw.uc_fw_obj, NULL, 0, 0, 0);
+	if (IS_ERR(vma)) {
+		DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
+		return;
+	}
+
+
+	/* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
+	I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
+
+	/* Specify auth action and where public signature is. */
+	data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC;
+	data[1] = i915_ggtt_offset(vma) + huc->huc_fw.rsa_offset;
+
+	ret = intel_guc_send(guc, data, ARRAY_SIZE(data));
+	if (ret) {
+		DRM_ERROR("HuC: GuC did not ack Auth request\n");
+		goto out;
+	}
+
+	/* Check authentication status, it should be done by now */
+	ret = wait_for((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) > 0, 50);
+	if (ret) {
+		DRM_ERROR("HuC: Authentication failed\n");
+		goto out;
+	}
+
+out:
+	i915_vma_unpin(vma);
+}
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index ac92946..1db8bc2 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -196,6 +196,7 @@ int intel_guc_sample_forcewake(struct intel_guc *guc);
 int intel_guc_log_flush_complete(struct intel_guc *guc);
 int intel_guc_log_flush(struct intel_guc *guc);
 int intel_guc_log_control(struct intel_guc *guc, u32 control_val);
+void intel_guc_auth_huc(struct drm_i915_private *dev_priv);
 
 /* intel_guc_loader.c */
 extern void intel_guc_init(struct drm_i915_private *dev_priv);
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 7/8] drm/i915/huc: Support HuC authentication

[Arkadiusz Hiler]

On Wed, Nov 30, 2016 at 03:31:33PM -0800, Anusha Srivatsa wrote:
> From: Peter Antoine <peter.antoine@intel.com>
> 
> The HuC authentication is done by host2guc call. The HuC RSA keys
> are sent to GuC for authentication.
> 
> v2: rebased on top of drm-intel-nightly.
>     changed name format and upped version 1.7.
> v3: rebased on top of drm-intel-nightly.
> v4: changed wait_for_automic to wait_for
> v5: rebased.
> v7: rebased.
> v8: rebased.
> v9: rebased. Rename intel_huc_auh() to intel_guc_auth_huc()
> and place the prototype in intel_guc.h,correct the comments.
> v10: rebased.
> v11: rebased.
> v12: rebased on top of drm-tip
> 
> Tested-by: Xiang Haihao <haihao.xiang@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Alex Dai <yu.dai@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
> Reviewed-by: Jeff McGee <jeff.mcgee@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_guc_submission.c | 63 ++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_guc_fwif.h      |  1 +
>  drivers/gpu/drm/i915/intel_guc_loader.c    |  2 +
>  3 files changed, 66 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
> index 4bae8e4..d5c205d 100644
> --- a/drivers/gpu/drm/i915/i915_guc_submission.c
> +++ b/drivers/gpu/drm/i915/i915_guc_submission.c
> @@ -26,6 +26,7 @@
>  #include <linux/relay.h>
>  #include "i915_drv.h"
>  #include "intel_uc.h"
> +#include "intel_huc.h"
>  
>  /**
>   * DOC: GuC-based command submission
> @@ -1638,3 +1639,65 @@ int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val)
>  
>  	return ret;
>  }
> +
> +/**
> + * intel_guc_auth_huc() - authenticate ucode
> + * @dev: the drm device
> + *
> + * Triggers a HuC fw authentication request to the GuC via host-2-guc
> + * interface.
> + */
> +void intel_guc_auth_huc(struct drm_device *dev)

This should belong to intel_uc.c

> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_guc *guc = &dev_priv->guc;
> +	struct intel_huc *huc = &dev_priv->huc;
> +	struct i915_vma *vma;
> +	int ret;
> +	u32 data[2];
> +
> +	/* Bypass the case where there is no HuC firmware */
> +	if (huc->huc_fw.fetch_status == UC_FIRMWARE_NONE ||
> +	    huc->huc_fw.load_status == UC_FIRMWARE_NONE)
> +		return;
> +
> +	if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS) {
> +		DRM_ERROR("HuC: GuC fw wasn't loaded. Can't authenticate");
> +		return;
> +	}
> +
> +	if (huc->huc_fw.load_status != UC_FIRMWARE_SUCCESS) {
> +		DRM_ERROR("HuC: fw wasn't loaded. Nothing to authenticate");
> +		return;
> +	}
> +
> +	vma = i915_gem_object_ggtt_pin(huc->huc_fw.uc_fw_obj, NULL, 0, 0, 0);
> +	if (IS_ERR(vma)) {
> +		DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
> +		return;
> +	}
> +
> +
> +	/* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
> +	I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
> +
> +	/* Specify auth action and where public signature is. */
> +	data[0] = HOST2GUC_ACTION_AUTHENTICATE_HUC;

s/HOST2GUC/INTEL_GUC/

> +	data[1] = i915_ggtt_offset(vma) + huc->huc_fw.rsa_offset;
> +
> +	ret = host2guc_action(guc, data, ARRAY_SIZE(data));

s/host2guc_action/intel_guc_send/

> +	if (ret) {
> +		DRM_ERROR("HuC: GuC did not ack Auth request\n");
> +		goto out;
> +	}
> +
> +	/* Check authentication status, it should be done by now */
> +	ret = wait_for((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) > 0, 50);
> +	if (ret) {
> +		DRM_ERROR("HuC: Authentication failed\n");
> +		goto out;
> +	}
> +
> +out:
> +	i915_vma_unpin(vma);
> +}
> diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
> index c07d9da..e51e063 100644
> --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
> @@ -513,6 +513,7 @@ enum intel_guc_action {
>  	INTEL_GUC_ACTION_EXIT_S_STATE = 0x502,
>  	INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003,
>  	INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000,
> +	HOST2GUC_ACTION_AUTHENTICATE_HUC = 0x4000,

s/HOST2GUC/INTEL_GUC/

>  	INTEL_GUC_ACTION_LIMIT
>  };
>  
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> index 7ca5556..31d09f8 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -529,6 +529,8 @@ int intel_guc_setup(struct drm_device *dev)
>  		intel_uc_fw_status_repr(guc_fw->fetch_status),
>  		intel_uc_fw_status_repr(guc_fw->load_status));
>  
> +	intel_guc_auth_huc(dev);
> +

You do not have this symbol declared in any header, it's not visible in
this compilation unit.

>  	if (i915.enable_guc_submission) {
>  		if (i915.guc_log_level >= 0)
>  			gen9_enable_guc_interrupts(dev_priv);
> -- 
> 2.7.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Cheers,
Arek
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 7/8] drm/i915/huc: Support HuC authentication

[Anusha Srivatsa]

From: Peter Antoine <peter.antoine@intel.com>

The HuC authentication is done by host2guc call. The HuC RSA keys
are sent to GuC for authentication.

v2: rebased on top of drm-intel-nightly.
    changed name format and upped version 1.7.
v3: rebased on top of drm-intel-nightly.
v4: changed wait_for_automic to wait_for
v5: rebased.
v7: rebased.
v8: rebased.
v9: rebased. Rename intel_huc_auh() to intel_guc_auth_huc()
and place the prototype in intel_guc.h,correct the comments.
v10: rebased.
v11: rebased.
v12: rebased on top of drm-tip

Tested-by: Xiang Haihao <haihao.xiang@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Jeff McGee <jeff.mcgee@intel.com>
---
 drivers/gpu/drm/i915/i915_guc_submission.c | 63 ++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_guc_fwif.h      |  1 +
 drivers/gpu/drm/i915/intel_guc_loader.c    |  2 +
 3 files changed, 66 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
index 4bae8e4..d5c205d 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -26,6 +26,7 @@
 #include <linux/relay.h>
 #include "i915_drv.h"
 #include "intel_uc.h"
+#include "intel_huc.h"
 
 /**
  * DOC: GuC-based command submission
@@ -1638,3 +1639,65 @@ int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val)
 
 	return ret;
 }
+
+/**
+ * intel_guc_auth_huc() - authenticate ucode
+ * @dev: the drm device
+ *
+ * Triggers a HuC fw authentication request to the GuC via host-2-guc
+ * interface.
+ */
+void intel_guc_auth_huc(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_guc *guc = &dev_priv->guc;
+	struct intel_huc *huc = &dev_priv->huc;
+	struct i915_vma *vma;
+	int ret;
+	u32 data[2];
+
+	/* Bypass the case where there is no HuC firmware */
+	if (huc->huc_fw.fetch_status == UC_FIRMWARE_NONE ||
+	    huc->huc_fw.load_status == UC_FIRMWARE_NONE)
+		return;
+
+	if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS) {
+		DRM_ERROR("HuC: GuC fw wasn't loaded. Can't authenticate");
+		return;
+	}
+
+	if (huc->huc_fw.load_status != UC_FIRMWARE_SUCCESS) {
+		DRM_ERROR("HuC: fw wasn't loaded. Nothing to authenticate");
+		return;
+	}
+
+	vma = i915_gem_object_ggtt_pin(huc->huc_fw.uc_fw_obj, NULL, 0, 0, 0);
+	if (IS_ERR(vma)) {
+		DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
+		return;
+	}
+
+
+	/* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
+	I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
+
+	/* Specify auth action and where public signature is. */
+	data[0] = HOST2GUC_ACTION_AUTHENTICATE_HUC;
+	data[1] = i915_ggtt_offset(vma) + huc->huc_fw.rsa_offset;
+
+	ret = host2guc_action(guc, data, ARRAY_SIZE(data));
+	if (ret) {
+		DRM_ERROR("HuC: GuC did not ack Auth request\n");
+		goto out;
+	}
+
+	/* Check authentication status, it should be done by now */
+	ret = wait_for((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) > 0, 50);
+	if (ret) {
+		DRM_ERROR("HuC: Authentication failed\n");
+		goto out;
+	}
+
+out:
+	i915_vma_unpin(vma);
+}
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
index c07d9da..e51e063 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -513,6 +513,7 @@ enum intel_guc_action {
 	INTEL_GUC_ACTION_EXIT_S_STATE = 0x502,
 	INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003,
 	INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000,
+	HOST2GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
 	INTEL_GUC_ACTION_LIMIT
 };
 
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 7ca5556..31d09f8 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -529,6 +529,8 @@ int intel_guc_setup(struct drm_device *dev)
 		intel_uc_fw_status_repr(guc_fw->fetch_status),
 		intel_uc_fw_status_repr(guc_fw->load_status));
 
+	intel_guc_auth_huc(dev);
+
 	if (i915.enable_guc_submission) {
 		if (i915.guc_log_level >= 0)
 			gen9_enable_guc_interrupts(dev_priv);
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 7/8] drm/i915/huc: Support HuC authentication

[Anusha Srivatsa]

From: Peter Antoine <peter.antoine@intel.com>

The HuC authentication is done by host2guc call. The HuC RSA keys
are sent to GuC for authentication.

v2: rebased on top of drm-intel-nightly.
    changed name format and upped version 1.7.
v3: rebased on top of drm-intel-nightly.
v4: changed wait_for_automic to wait_for
v5: rebased.
v7: rebased.
v8: rebased.
v9: rebased. Rename intel_huc_auh() to intel_guc_auth_huc()
and place the prototype in intel_guc.h,correct the comments.
v10: rebased.
v11: rebased.

Tested-by: Xiang Haihao <haihao.xiang@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Jeff McGee <jeff.mcgee@intel.com>
---
 drivers/gpu/drm/i915/i915_guc_submission.c | 63 ++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_guc.h           |  2 +-
 drivers/gpu/drm/i915/intel_guc_fwif.h      |  1 +
 drivers/gpu/drm/i915/intel_guc_loader.c    |  2 +
 4 files changed, 67 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
index 9947a6d..704c2a0 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -27,6 +27,7 @@
 #include <linux/relay.h>
 #include "i915_drv.h"
 #include "intel_guc.h"
+#include "intel_huc.h"
 
 /**
  * DOC: GuC-based command submission
@@ -1728,3 +1729,65 @@ int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val)
 
 	return ret;
 }
+
+/**
+ * intel_guc_auth_huc() - authenticate ucode
+ * @dev: the drm device
+ *
+ * Triggers a HuC fw authentication request to the GuC via host-2-guc
+ * interface.
+ */
+void intel_guc_auth_huc(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_guc *guc = &dev_priv->guc;
+	struct intel_huc *huc = &dev_priv->huc;
+	struct i915_vma *vma;
+	int ret;
+	u32 data[2];
+
+	/* Bypass the case where there is no HuC firmware */
+	if (huc->huc_fw.fetch_status == UC_FIRMWARE_NONE ||
+	    huc->huc_fw.load_status == UC_FIRMWARE_NONE)
+		return;
+
+	if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS) {
+		DRM_ERROR("HuC: GuC fw wasn't loaded. Can't authenticate");
+		return;
+	}
+
+	if (huc->huc_fw.load_status != UC_FIRMWARE_SUCCESS) {
+		DRM_ERROR("HuC: fw wasn't loaded. Nothing to authenticate");
+		return;
+	}
+
+	vma = i915_gem_object_ggtt_pin(huc->huc_fw.uc_fw_obj, NULL, 0, 0, 0);
+	if (IS_ERR(vma)) {
+		DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
+		return;
+	}
+
+
+	/* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
+	I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
+
+	/* Specify auth action and where public signature is. */
+	data[0] = HOST2GUC_ACTION_AUTHENTICATE_HUC;
+	data[1] = i915_ggtt_offset(vma) + huc->huc_fw.rsa_offset;
+
+	ret = host2guc_action(guc, data, ARRAY_SIZE(data));
+	if (ret) {
+		DRM_ERROR("HuC: GuC did not ack Auth request\n");
+		goto out;
+	}
+
+	/* Check authentication status, it should be done by now */
+	ret = wait_for((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) > 0, 50);
+	if (ret) {
+		DRM_ERROR("HuC: Authentication failed\n");
+		goto out;
+	}
+
+out:
+	i915_vma_unpin(vma);
+}
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index ff6aba6..67a500c 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -197,5 +197,5 @@ void i915_guc_flush_logs(struct drm_i915_private *dev_priv);
 void i915_guc_register(struct drm_i915_private *dev_priv);
 void i915_guc_unregister(struct drm_i915_private *dev_priv);
 int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val);
-
+void intel_guc_auth_huc(struct drm_device *dev);
 #endif
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
index c2a7fdd..99a092d 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -513,6 +513,7 @@ enum host2guc_action {
 	HOST2GUC_ACTION_EXIT_S_STATE = 0x502,
 	HOST2GUC_ACTION_SLPC_REQUEST = 0x3003,
 	HOST2GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000,
+	HOST2GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
 	HOST2GUC_ACTION_LIMIT
 };
 
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 090c727..6946311 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -531,6 +531,8 @@ int intel_guc_setup(struct drm_device *dev)
 		intel_uc_fw_status_repr(guc_fw->fetch_status),
 		intel_uc_fw_status_repr(guc_fw->load_status));
 
+	intel_guc_auth_huc(dev);
+
 	if (i915.enable_guc_submission) {
 		if (i915.guc_log_level >= 0)
 			gen9_enable_guc_interrupts(dev_priv);
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 7/8] drm/i915/huc: Support HuC authentication

[Anusha Srivatsa]

From: Peter Antoine <peter.antoine@intel.com>

The HuC authentication is done by host2guc call. The HuC RSA keys
are sent to GuC for authentication.

v2: rebased on top of drm-intel-nightly.
    changed name format and upped version 1.7.
v3: rebased on top of drm-intel-nightly.
v4: changed wait_for_automic to wait_for
v5: rebased.
v7: rebased.
v8: rebased.
v9: rebased. Rename intel_huc_auh() to intel_guc_auth_huc()
and place the prototype in intel_guc.h,correct the comments.
v10: rebased.

Tested-by: Xiang Haihao <haihao.xiang@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Jeff McGee <jeff.mcgee@intel.com>
---
 drivers/gpu/drm/i915/i915_guc_submission.c | 63 ++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_guc.h           |  2 +-
 drivers/gpu/drm/i915/intel_guc_fwif.h      |  1 +
 drivers/gpu/drm/i915/intel_guc_loader.c    |  2 +
 4 files changed, 67 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
index fb59e44..7809acf 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -27,6 +27,7 @@
 #include <linux/relay.h>
 #include "i915_drv.h"
 #include "intel_guc.h"
+#include "intel_huc.h"
 
 /**
  * DOC: GuC-based command submission
@@ -1714,3 +1715,65 @@ int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val)
 
 	return ret;
 }
+
+/**
+ * intel_guc_auth_huc() - authenticate ucode
+ * @dev: the drm device
+ *
+ * Triggers a HuC fw authentication request to the GuC via host-2-guc
+ * interface.
+ */
+void intel_guc_auth_huc(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_guc *guc = &dev_priv->guc;
+	struct intel_huc *huc = &dev_priv->huc;
+	struct i915_vma *vma;
+	int ret;
+	u32 data[2];
+
+	/* Bypass the case where there is no HuC firmware */
+	if (huc->huc_fw.fetch_status == UC_FIRMWARE_NONE ||
+	    huc->huc_fw.load_status == UC_FIRMWARE_NONE)
+		return;
+
+	if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS) {
+		DRM_ERROR("HuC: GuC fw wasn't loaded. Can't authenticate");
+		return;
+	}
+
+	if (huc->huc_fw.load_status != UC_FIRMWARE_SUCCESS) {
+		DRM_ERROR("HuC: fw wasn't loaded. Nothing to authenticate");
+		return;
+	}
+
+	vma = i915_gem_object_ggtt_pin(huc->huc_fw.uc_fw_obj, NULL, 0, 0, 0);
+	if (IS_ERR(vma)) {
+		DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
+		return;
+	}
+
+
+	/* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
+	I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
+
+	/* Specify auth action and where public signature is. */
+	data[0] = HOST2GUC_ACTION_AUTHENTICATE_HUC;
+	data[1] = i915_ggtt_offset(vma) + huc->huc_fw.rsa_offset;
+
+	ret = host2guc_action(guc, data, ARRAY_SIZE(data));
+	if (ret) {
+		DRM_ERROR("HuC: GuC did not ack Auth request\n");
+		goto out;
+	}
+
+	/* Check authentication status, it should be done by now */
+	ret = wait_for((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) > 0, 50);
+	if (ret) {
+		DRM_ERROR("HuC: Authentication failed\n");
+		goto out;
+	}
+
+out:
+	i915_vma_unpin(vma);
+}
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index ff6aba6..67a500c 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -197,5 +197,5 @@ void i915_guc_flush_logs(struct drm_i915_private *dev_priv);
 void i915_guc_register(struct drm_i915_private *dev_priv);
 void i915_guc_unregister(struct drm_i915_private *dev_priv);
 int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val);
-
+void intel_guc_auth_huc(struct drm_device *dev);
 #endif
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
index c2a7fdd..99a092d 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -513,6 +513,7 @@ enum host2guc_action {
 	HOST2GUC_ACTION_EXIT_S_STATE = 0x502,
 	HOST2GUC_ACTION_SLPC_REQUEST = 0x3003,
 	HOST2GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000,
+	HOST2GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
 	HOST2GUC_ACTION_LIMIT
 };
 
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index dc79968..11e3bbb 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -531,6 +531,8 @@ int intel_guc_setup(struct drm_device *dev)
 		intel_uc_fw_status_repr(guc_fw->fetch_status),
 		intel_uc_fw_status_repr(guc_fw->load_status));
 
+	intel_guc_auth_huc(dev);
+
 	if (i915.enable_guc_submission) {
 		if (i915.guc_log_level >= 0)
 			gen9_enable_guc_interrupts(dev_priv);
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx