* [Qemu-devel] [PATCH v2 ppc-for-2.9 0/6] POWER9 TCG enablements - part9
@ 2016-12-09 12:17 Nikunj A Dadhania
2016-12-09 12:17 ` [Qemu-devel] [PATCH v2 1/6] target-ppc: implement lxvl instruction Nikunj A Dadhania
` (6 more replies)
0 siblings, 7 replies; 14+ messages in thread
From: Nikunj A Dadhania @ 2016-12-09 12:17 UTC (permalink / raw)
To: qemu-ppc, david, rth; +Cc: qemu-devel, bharata, nikunj
This series contains 6 new instructions for POWER9 ISA3.0
VSX Vector Insert/Extract Word
VSX Load/Store with length
Although, lxvl/lxvll and stxvl/stxvll can be combined as single patch,
have left it for detailed commit log for instruction explanation.
Changelog:
v1:
* Combine helpers of lxvl and lxvll
* Combine helpers of stxvl and stxvll
* Rework xxextractuw and xxinsertw to simplify helper
v0:
* Fixed lxvl/lxvll and stxvl/stxvll as suggested by Richard
* Dropped mask_u128, which is not needed anymore
* Prevent UIMM > 12 in xxextractuw
* Drop xori from xsnegqp
* Rewrite xxperm/xxpermr without double copy
Nikunj A Dadhania (6):
target-ppc: implement lxvl instruction
target-ppc: implement lxvll instruction
target-ppc: implement stxvl instruction
target-ppc: implement stxvll instructions
target-ppc: implement xxextractuw instruction
target-ppc: implement xxinsertw instruction
target-ppc/helper.h | 8 +++++
target-ppc/int_helper.c | 42 +++++++++++++++++++++++
target-ppc/mem_helper.c | 66 +++++++++++++++++++++++++++++++++++++
target-ppc/translate/vsx-impl.inc.c | 60 +++++++++++++++++++++++++++++++++
target-ppc/translate/vsx-ops.inc.c | 14 ++++++++
5 files changed, 190 insertions(+)
--
2.7.4
^ permalink raw reply [flat|nested] 14+ messages in thread
* [Qemu-devel] [PATCH v2 1/6] target-ppc: implement lxvl instruction
2016-12-09 12:17 [Qemu-devel] [PATCH v2 ppc-for-2.9 0/6] POWER9 TCG enablements - part9 Nikunj A Dadhania
@ 2016-12-09 12:17 ` Nikunj A Dadhania
2016-12-09 12:17 ` [Qemu-devel] [PATCH v2 2/6] target-ppc: implement lxvll instruction Nikunj A Dadhania
` (5 subsequent siblings)
6 siblings, 0 replies; 14+ messages in thread
From: Nikunj A Dadhania @ 2016-12-09 12:17 UTC (permalink / raw)
To: qemu-ppc, david, rth; +Cc: qemu-devel, bharata, nikunj
lxvl: Load VSX Vector with Length
Little/Big-endian Storage:
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
|“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|FF|FF|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
Loading 14 bytes results in:
Vector (8-bit elements) in BE:
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
|“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|00|00|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
Vector (8-bit elements) in LE:
+--+--+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
|00|00|“T”|“S”|“E”|“T”|“ ”|“a”|“ ”|“s”|“i”|“ ”|“s”|“i”|"h"|"T"|
+--+--+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
target-ppc/helper.h | 3 +++
target-ppc/mem_helper.c | 35 +++++++++++++++++++++++++++++++++++
target-ppc/translate/vsx-impl.inc.c | 29 +++++++++++++++++++++++++++++
target-ppc/translate/vsx-ops.inc.c | 3 +++
4 files changed, 70 insertions(+)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index c3df982..16ed2c1 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -317,6 +317,9 @@ DEF_HELPER_3(lvewx, void, env, avr, tl)
DEF_HELPER_3(stvebx, void, env, avr, tl)
DEF_HELPER_3(stvehx, void, env, avr, tl)
DEF_HELPER_3(stvewx, void, env, avr, tl)
+#if defined(TARGET_PPC64)
+DEF_HELPER_4(lxvl, void, env, tl, tl, tl)
+#endif
DEF_HELPER_4(vsumsws, void, env, avr, avr, avr)
DEF_HELPER_4(vsum2sws, void, env, avr, avr, avr)
DEF_HELPER_4(vsum4sbs, void, env, avr, avr, avr)
diff --git a/target-ppc/mem_helper.c b/target-ppc/mem_helper.c
index 1ab8a6e..c4ddc5b 100644
--- a/target-ppc/mem_helper.c
+++ b/target-ppc/mem_helper.c
@@ -24,6 +24,7 @@
#include "helper_regs.h"
#include "exec/cpu_ldst.h"
+#include "internal.h"
//#define DEBUG_OP
@@ -284,6 +285,40 @@ STVE(stvewx, cpu_stl_data_ra, bswap32, u32)
#undef I
#undef LVE
+#ifdef TARGET_PPC64
+#define GET_NB(rb) ((rb >> 56) & 0xFF)
+
+#define VSX_LXVL(name, lj) \
+void helper_##name(CPUPPCState *env, target_ulong addr, \
+ target_ulong xt_num, target_ulong rb) \
+{ \
+ int i; \
+ ppc_vsr_t xt; \
+ uint64_t nb = GET_NB(rb); \
+ \
+ xt.s128 = int128_zero(); \
+ if (nb) { \
+ nb = (nb >= 16) ? 16 : nb; \
+ if (msr_le && !lj) { \
+ for (i = 16; i > 16 - nb; i--) { \
+ xt.VsrB(i - 1) = cpu_ldub_data_ra(env, addr, GETPC()); \
+ addr = addr_add(env, addr, 1); \
+ } \
+ } else { \
+ for (i = 0; i < nb; i++) { \
+ xt.VsrB(i) = cpu_ldub_data_ra(env, addr, GETPC()); \
+ addr = addr_add(env, addr, 1); \
+ } \
+ } \
+ } \
+ putVSR(xt_num, &xt, env); \
+}
+
+VSX_LXVL(lxvl, 0)
+#undef VSX_LXVL
+#undef GET_NB
+#endif /* TARGET_PPC64 */
+
#undef HI_IDX
#undef LO_IDX
diff --git a/target-ppc/translate/vsx-impl.inc.c b/target-ppc/translate/vsx-impl.inc.c
index 7000035..1f64fb7 100644
--- a/target-ppc/translate/vsx-impl.inc.c
+++ b/target-ppc/translate/vsx-impl.inc.c
@@ -240,6 +240,35 @@ VSX_VECTOR_LOAD_STORE(stxv, st_i64, 0)
VSX_VECTOR_LOAD_STORE(lxvx, ld_i64, 1)
VSX_VECTOR_LOAD_STORE(stxvx, st_i64, 1)
+#ifdef TARGET_PPC64
+#define VSX_VECTOR_LOAD_STORE_LENGTH(name) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv EA, xt; \
+ \
+ if (xT(ctx->opcode) < 32) { \
+ if (unlikely(!ctx->vsx_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VSXU); \
+ return; \
+ } \
+ } else { \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ } \
+ EA = tcg_temp_new(); \
+ xt = tcg_const_tl(xT(ctx->opcode)); \
+ gen_set_access_type(ctx, ACCESS_INT); \
+ gen_addr_register(ctx, EA); \
+ gen_helper_##name(cpu_env, EA, xt, cpu_gpr[rB(ctx->opcode)]); \
+ tcg_temp_free(EA); \
+ tcg_temp_free(xt); \
+}
+
+VSX_VECTOR_LOAD_STORE_LENGTH(lxvl)
+#endif
+
#define VSX_LOAD_SCALAR_DS(name, operation) \
static void gen_##name(DisasContext *ctx) \
{ \
diff --git a/target-ppc/translate/vsx-ops.inc.c b/target-ppc/translate/vsx-ops.inc.c
index f684066..62a0afc 100644
--- a/target-ppc/translate/vsx-ops.inc.c
+++ b/target-ppc/translate/vsx-ops.inc.c
@@ -10,6 +10,9 @@ GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(lxvh8x, 0x1F, 0x0C, 0x19, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(lxvb16x, 0x1F, 0x0C, 0x1B, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(lxvx, 0x1F, 0x0C, 0x08, 0x00000040, PPC_NONE, PPC2_ISA300),
+#if defined(TARGET_PPC64)
+GEN_HANDLER_E(lxvl, 0x1F, 0x0D, 0x08, 0, PPC_NONE, PPC2_ISA300),
+#endif
GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(stxsibx, 0x1F, 0xD, 0x1C, 0, PPC_NONE, PPC2_ISA300),
--
2.7.4
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [Qemu-devel] [PATCH v2 2/6] target-ppc: implement lxvll instruction
2016-12-09 12:17 [Qemu-devel] [PATCH v2 ppc-for-2.9 0/6] POWER9 TCG enablements - part9 Nikunj A Dadhania
2016-12-09 12:17 ` [Qemu-devel] [PATCH v2 1/6] target-ppc: implement lxvl instruction Nikunj A Dadhania
@ 2016-12-09 12:17 ` Nikunj A Dadhania
2016-12-09 12:17 ` [Qemu-devel] [PATCH v2 3/6] target-ppc: implement stxvl instruction Nikunj A Dadhania
` (4 subsequent siblings)
6 siblings, 0 replies; 14+ messages in thread
From: Nikunj A Dadhania @ 2016-12-09 12:17 UTC (permalink / raw)
To: qemu-ppc, david, rth; +Cc: qemu-devel, bharata, nikunj
lxvll: Load VSX Vector Left-justified with Length
Little/Big-endian Storage:
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
|“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|FF|FF|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
Loading 14 bytes to vector (8-bit elements) in BE/LE:
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
|“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|00|00|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
target-ppc/helper.h | 1 +
target-ppc/mem_helper.c | 1 +
target-ppc/translate/vsx-impl.inc.c | 1 +
target-ppc/translate/vsx-ops.inc.c | 1 +
4 files changed, 4 insertions(+)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 16ed2c1..6c44731 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -319,6 +319,7 @@ DEF_HELPER_3(stvehx, void, env, avr, tl)
DEF_HELPER_3(stvewx, void, env, avr, tl)
#if defined(TARGET_PPC64)
DEF_HELPER_4(lxvl, void, env, tl, tl, tl)
+DEF_HELPER_4(lxvll, void, env, tl, tl, tl)
#endif
DEF_HELPER_4(vsumsws, void, env, avr, avr, avr)
DEF_HELPER_4(vsum2sws, void, env, avr, avr, avr)
diff --git a/target-ppc/mem_helper.c b/target-ppc/mem_helper.c
index c4ddc5b..da51465 100644
--- a/target-ppc/mem_helper.c
+++ b/target-ppc/mem_helper.c
@@ -315,6 +315,7 @@ void helper_##name(CPUPPCState *env, target_ulong addr, \
}
VSX_LXVL(lxvl, 0)
+VSX_LXVL(lxvll, 1)
#undef VSX_LXVL
#undef GET_NB
#endif /* TARGET_PPC64 */
diff --git a/target-ppc/translate/vsx-impl.inc.c b/target-ppc/translate/vsx-impl.inc.c
index 1f64fb7..ce20579 100644
--- a/target-ppc/translate/vsx-impl.inc.c
+++ b/target-ppc/translate/vsx-impl.inc.c
@@ -267,6 +267,7 @@ static void gen_##name(DisasContext *ctx) \
}
VSX_VECTOR_LOAD_STORE_LENGTH(lxvl)
+VSX_VECTOR_LOAD_STORE_LENGTH(lxvll)
#endif
#define VSX_LOAD_SCALAR_DS(name, operation) \
diff --git a/target-ppc/translate/vsx-ops.inc.c b/target-ppc/translate/vsx-ops.inc.c
index 62a0afc..c207804 100644
--- a/target-ppc/translate/vsx-ops.inc.c
+++ b/target-ppc/translate/vsx-ops.inc.c
@@ -12,6 +12,7 @@ GEN_HANDLER_E(lxvb16x, 0x1F, 0x0C, 0x1B, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(lxvx, 0x1F, 0x0C, 0x08, 0x00000040, PPC_NONE, PPC2_ISA300),
#if defined(TARGET_PPC64)
GEN_HANDLER_E(lxvl, 0x1F, 0x0D, 0x08, 0, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E(lxvll, 0x1F, 0x0D, 0x09, 0, PPC_NONE, PPC2_ISA300),
#endif
GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
--
2.7.4
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [Qemu-devel] [PATCH v2 3/6] target-ppc: implement stxvl instruction
2016-12-09 12:17 [Qemu-devel] [PATCH v2 ppc-for-2.9 0/6] POWER9 TCG enablements - part9 Nikunj A Dadhania
2016-12-09 12:17 ` [Qemu-devel] [PATCH v2 1/6] target-ppc: implement lxvl instruction Nikunj A Dadhania
2016-12-09 12:17 ` [Qemu-devel] [PATCH v2 2/6] target-ppc: implement lxvll instruction Nikunj A Dadhania
@ 2016-12-09 12:17 ` Nikunj A Dadhania
2016-12-09 12:17 ` [Qemu-devel] [PATCH v2 4/6] target-ppc: implement stxvll instructions Nikunj A Dadhania
` (3 subsequent siblings)
6 siblings, 0 replies; 14+ messages in thread
From: Nikunj A Dadhania @ 2016-12-09 12:17 UTC (permalink / raw)
To: qemu-ppc, david, rth; +Cc: qemu-devel, bharata, nikunj
stxvl: Store VSX Vector with Length
Vector (8-bit elements) in BE:
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
|“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|00|00|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
Vector (8-bit elements) in LE:
+--+--+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
|00|00|“T”|“S”|“E”|“T”|“ ”|“a”|“ ”|“s”|“i”|“ ”|“s”|“i”|"h"|"T"|
+--+--+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
Storing 14 bytes would result in following Little/Big-endian Storage:
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
|“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|FF|FF|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
target-ppc/helper.h | 1 +
target-ppc/mem_helper.c | 29 +++++++++++++++++++++++++++++
target-ppc/translate/vsx-impl.inc.c | 1 +
target-ppc/translate/vsx-ops.inc.c | 3 +++
4 files changed, 34 insertions(+)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 6c44731..211313d 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -320,6 +320,7 @@ DEF_HELPER_3(stvewx, void, env, avr, tl)
#if defined(TARGET_PPC64)
DEF_HELPER_4(lxvl, void, env, tl, tl, tl)
DEF_HELPER_4(lxvll, void, env, tl, tl, tl)
+DEF_HELPER_4(stxvl, void, env, tl, tl, tl)
#endif
DEF_HELPER_4(vsumsws, void, env, avr, avr, avr)
DEF_HELPER_4(vsum2sws, void, env, avr, avr, avr)
diff --git a/target-ppc/mem_helper.c b/target-ppc/mem_helper.c
index da51465..2427b49 100644
--- a/target-ppc/mem_helper.c
+++ b/target-ppc/mem_helper.c
@@ -317,6 +317,35 @@ void helper_##name(CPUPPCState *env, target_ulong addr, \
VSX_LXVL(lxvl, 0)
VSX_LXVL(lxvll, 1)
#undef VSX_LXVL
+
+#define VSX_STXVL(name, lj) \
+void helper_##name(CPUPPCState *env, target_ulong addr, \
+ target_ulong xt_num, target_ulong rb) \
+{ \
+ int i; \
+ ppc_vsr_t xt; \
+ target_ulong nb = GET_NB(rb); \
+ \
+ if (!nb) { \
+ return; \
+ } \
+ getVSR(xt_num, &xt, env); \
+ nb = (nb >= 16) ? 16 : nb; \
+ if (msr_le && !lj) { \
+ for (i = 16; i > 16 - nb; i--) { \
+ cpu_stb_data_ra(env, addr, xt.VsrB(i - 1), GETPC()); \
+ addr = addr_add(env, addr, 1); \
+ } \
+ } else { \
+ for (i = 0; i < nb; i++) { \
+ cpu_stb_data_ra(env, addr, xt.VsrB(i), GETPC()); \
+ addr = addr_add(env, addr, 1); \
+ } \
+ } \
+}
+
+VSX_STXVL(stxvl, 0)
+#undef VSX_STXVL
#undef GET_NB
#endif /* TARGET_PPC64 */
diff --git a/target-ppc/translate/vsx-impl.inc.c b/target-ppc/translate/vsx-impl.inc.c
index ce20579..5099d44 100644
--- a/target-ppc/translate/vsx-impl.inc.c
+++ b/target-ppc/translate/vsx-impl.inc.c
@@ -268,6 +268,7 @@ static void gen_##name(DisasContext *ctx) \
VSX_VECTOR_LOAD_STORE_LENGTH(lxvl)
VSX_VECTOR_LOAD_STORE_LENGTH(lxvll)
+VSX_VECTOR_LOAD_STORE_LENGTH(stxvl)
#endif
#define VSX_LOAD_SCALAR_DS(name, operation) \
diff --git a/target-ppc/translate/vsx-ops.inc.c b/target-ppc/translate/vsx-ops.inc.c
index c207804..3afded2 100644
--- a/target-ppc/translate/vsx-ops.inc.c
+++ b/target-ppc/translate/vsx-ops.inc.c
@@ -25,6 +25,9 @@ GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(stxvh8x, 0x1F, 0x0C, 0x1D, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(stxvb16x, 0x1F, 0x0C, 0x1F, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(stxvx, 0x1F, 0x0C, 0x0C, 0, PPC_NONE, PPC2_ISA300),
+#if defined(TARGET_PPC64)
+GEN_HANDLER_E(stxvl, 0x1F, 0x0D, 0x0C, 0, PPC_NONE, PPC2_ISA300),
+#endif
GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
--
2.7.4
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [Qemu-devel] [PATCH v2 4/6] target-ppc: implement stxvll instructions
2016-12-09 12:17 [Qemu-devel] [PATCH v2 ppc-for-2.9 0/6] POWER9 TCG enablements - part9 Nikunj A Dadhania
` (2 preceding siblings ...)
2016-12-09 12:17 ` [Qemu-devel] [PATCH v2 3/6] target-ppc: implement stxvl instruction Nikunj A Dadhania
@ 2016-12-09 12:17 ` Nikunj A Dadhania
2016-12-09 12:17 ` [Qemu-devel] [PATCH v2 5/6] target-ppc: implement xxextractuw instruction Nikunj A Dadhania
` (2 subsequent siblings)
6 siblings, 0 replies; 14+ messages in thread
From: Nikunj A Dadhania @ 2016-12-09 12:17 UTC (permalink / raw)
To: qemu-ppc, david, rth; +Cc: qemu-devel, bharata, nikunj
stxvll: Store VSX Vector Left-justified with Length
Vector (8-bit elements) in BE/LE:
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
|“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|00|00|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
Storing 14 bytes would result in following Little/Big-endian Storage:
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
|“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|FF|FF|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
target-ppc/helper.h | 1 +
target-ppc/mem_helper.c | 1 +
target-ppc/translate/vsx-impl.inc.c | 1 +
target-ppc/translate/vsx-ops.inc.c | 1 +
4 files changed, 4 insertions(+)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 211313d..4707db4 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -321,6 +321,7 @@ DEF_HELPER_3(stvewx, void, env, avr, tl)
DEF_HELPER_4(lxvl, void, env, tl, tl, tl)
DEF_HELPER_4(lxvll, void, env, tl, tl, tl)
DEF_HELPER_4(stxvl, void, env, tl, tl, tl)
+DEF_HELPER_4(stxvll, void, env, tl, tl, tl)
#endif
DEF_HELPER_4(vsumsws, void, env, avr, avr, avr)
DEF_HELPER_4(vsum2sws, void, env, avr, avr, avr)
diff --git a/target-ppc/mem_helper.c b/target-ppc/mem_helper.c
index 2427b49..e6383c6 100644
--- a/target-ppc/mem_helper.c
+++ b/target-ppc/mem_helper.c
@@ -345,6 +345,7 @@ void helper_##name(CPUPPCState *env, target_ulong addr, \
}
VSX_STXVL(stxvl, 0)
+VSX_STXVL(stxvll, 1)
#undef VSX_STXVL
#undef GET_NB
#endif /* TARGET_PPC64 */
diff --git a/target-ppc/translate/vsx-impl.inc.c b/target-ppc/translate/vsx-impl.inc.c
index 5099d44..2a17c35 100644
--- a/target-ppc/translate/vsx-impl.inc.c
+++ b/target-ppc/translate/vsx-impl.inc.c
@@ -269,6 +269,7 @@ static void gen_##name(DisasContext *ctx) \
VSX_VECTOR_LOAD_STORE_LENGTH(lxvl)
VSX_VECTOR_LOAD_STORE_LENGTH(lxvll)
VSX_VECTOR_LOAD_STORE_LENGTH(stxvl)
+VSX_VECTOR_LOAD_STORE_LENGTH(stxvll)
#endif
#define VSX_LOAD_SCALAR_DS(name, operation) \
diff --git a/target-ppc/translate/vsx-ops.inc.c b/target-ppc/translate/vsx-ops.inc.c
index 3afded2..46b95e3 100644
--- a/target-ppc/translate/vsx-ops.inc.c
+++ b/target-ppc/translate/vsx-ops.inc.c
@@ -27,6 +27,7 @@ GEN_HANDLER_E(stxvb16x, 0x1F, 0x0C, 0x1F, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(stxvx, 0x1F, 0x0C, 0x0C, 0, PPC_NONE, PPC2_ISA300),
#if defined(TARGET_PPC64)
GEN_HANDLER_E(stxvl, 0x1F, 0x0D, 0x0C, 0, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E(stxvll, 0x1F, 0x0D, 0x0D, 0, PPC_NONE, PPC2_ISA300),
#endif
GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
--
2.7.4
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [Qemu-devel] [PATCH v2 5/6] target-ppc: implement xxextractuw instruction
2016-12-09 12:17 [Qemu-devel] [PATCH v2 ppc-for-2.9 0/6] POWER9 TCG enablements - part9 Nikunj A Dadhania
` (3 preceding siblings ...)
2016-12-09 12:17 ` [Qemu-devel] [PATCH v2 4/6] target-ppc: implement stxvll instructions Nikunj A Dadhania
@ 2016-12-09 12:17 ` Nikunj A Dadhania
2016-12-12 0:30 ` David Gibson
2016-12-09 12:17 ` [Qemu-devel] [PATCH v2 6/6] target-ppc: implement xxinsertw instruction Nikunj A Dadhania
2016-12-12 0:32 ` [Qemu-devel] [PATCH v2 ppc-for-2.9 0/6] POWER9 TCG enablements - part9 David Gibson
6 siblings, 1 reply; 14+ messages in thread
From: Nikunj A Dadhania @ 2016-12-09 12:17 UTC (permalink / raw)
To: qemu-ppc, david, rth; +Cc: qemu-devel, bharata, nikunj
xxextractuw: VSX Vector Extract Unsigned Word
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 21 +++++++++++++++++++++
target-ppc/translate/vsx-impl.inc.c | 27 +++++++++++++++++++++++++++
target-ppc/translate/vsx-ops.inc.c | 5 +++++
4 files changed, 54 insertions(+)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 4707db4..8b30420 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -540,6 +540,7 @@ DEF_HELPER_2(xvrspip, void, env, i32)
DEF_HELPER_2(xvrspiz, void, env, i32)
DEF_HELPER_2(xxperm, void, env, i32)
DEF_HELPER_2(xxpermr, void, env, i32)
+DEF_HELPER_4(xxextractuw, void, env, tl, tl, i32)
DEF_HELPER_2(efscfsi, i32, env, i32)
DEF_HELPER_2(efscfui, i32, env, i32)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index 7989b1f..e3f66ac 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -2033,6 +2033,27 @@ VEXTRACT(uw, u32)
VEXTRACT(d, u64)
#undef VEXTRACT
+void helper_xxextractuw(CPUPPCState *env, target_ulong xtn,
+ target_ulong xbn, uint32_t index)
+{
+ ppc_vsr_t xt, xb;
+ size_t es = sizeof(uint32_t);
+ uint32_t ext_index;
+
+ getVSR(xbn, &xb, env);
+ memset(&xt, 0, sizeof(xt));
+
+#if defined(HOST_WORDS_BIGENDIAN)
+ ext_index = index;
+ memcpy(&xt.u8[8 - es], &xb.u8[ext_index], es);
+#else
+ ext_index = (16 - index) - es;
+ memcpy(&xt.u8[8], &xb.u8[ext_index], es);
+#endif
+
+ putVSR(xtn, &xt, env);
+}
+
#define VEXT_SIGNED(name, element, mask, cast, recast) \
void helper_##name(ppc_avr_t *r, ppc_avr_t *b) \
{ \
diff --git a/target-ppc/translate/vsx-impl.inc.c b/target-ppc/translate/vsx-impl.inc.c
index 2a17c35..1c40a35 100644
--- a/target-ppc/translate/vsx-impl.inc.c
+++ b/target-ppc/translate/vsx-impl.inc.c
@@ -1180,6 +1180,33 @@ static void gen_xxsldwi(DisasContext *ctx)
tcg_temp_free_i64(xtl);
}
+#define VSX_EXTRACT(name) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv xt, xb; \
+ TCGv_i32 t0 = tcg_temp_new_i32(); \
+ uint8_t uimm = UIMM4(ctx->opcode); \
+ \
+ if (unlikely(!ctx->vsx_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VSXU); \
+ return; \
+ } \
+ if (uimm > 12) { \
+ tcg_gen_movi_i64(cpu_vsrh(xT(ctx->opcode)), 0); \
+ tcg_gen_movi_i64(cpu_vsrl(xT(ctx->opcode)), 0); \
+ return; \
+ } \
+ xt = tcg_const_tl(xT(ctx->opcode)); \
+ xb = tcg_const_tl(xB(ctx->opcode)); \
+ tcg_gen_movi_i32(t0, uimm); \
+ gen_helper_##name(cpu_env, xt, xb, t0); \
+ tcg_temp_free(xb); \
+ tcg_temp_free(xt); \
+ tcg_temp_free_i32(t0); \
+}
+
+VSX_EXTRACT(xxextractuw)
+
#undef GEN_XX2FORM
#undef GEN_XX3FORM
#undef GEN_XX2IFORM
diff --git a/target-ppc/translate/vsx-ops.inc.c b/target-ppc/translate/vsx-ops.inc.c
index 46b95e3..473d925 100644
--- a/target-ppc/translate/vsx-ops.inc.c
+++ b/target-ppc/translate/vsx-ops.inc.c
@@ -49,6 +49,10 @@ GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
+#define GEN_XX2FORM_EXT(name, opc2, opc3, fl2) \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0x00100000, PPC_NONE, fl2), \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0x00100000, PPC_NONE, fl2)
+
#define GEN_XX2FORM_EO(name, opc2, opc3, opc4, fl2) \
GEN_HANDLER2_E_2(name, #name, 0x3C, opc2 | 0, opc3, opc4, 0, PPC_NONE, fl2), \
GEN_HANDLER2_E_2(name, #name, 0x3C, opc2 | 1, opc3, opc4, 0, PPC_NONE, fl2)
@@ -280,6 +284,7 @@ GEN_XX3FORM(xxpermr, 0x08, 0x07, PPC2_ISA300),
GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
GEN_XX1FORM(xxspltib, 0x08, 0x0B, PPC2_ISA300),
GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
+GEN_XX2FORM_EXT(xxextractuw, 0x0A, 0x0A, PPC2_ISA300),
#define GEN_XXSEL_ROW(opc3) \
GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
--
2.7.4
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [Qemu-devel] [PATCH v2 6/6] target-ppc: implement xxinsertw instruction
2016-12-09 12:17 [Qemu-devel] [PATCH v2 ppc-for-2.9 0/6] POWER9 TCG enablements - part9 Nikunj A Dadhania
` (4 preceding siblings ...)
2016-12-09 12:17 ` [Qemu-devel] [PATCH v2 5/6] target-ppc: implement xxextractuw instruction Nikunj A Dadhania
@ 2016-12-09 12:17 ` Nikunj A Dadhania
2016-12-12 0:32 ` [Qemu-devel] [PATCH v2 ppc-for-2.9 0/6] POWER9 TCG enablements - part9 David Gibson
6 siblings, 0 replies; 14+ messages in thread
From: Nikunj A Dadhania @ 2016-12-09 12:17 UTC (permalink / raw)
To: qemu-ppc, david, rth; +Cc: qemu-devel, bharata, nikunj
xxinsertw: VSX Vector Insert Word
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 21 +++++++++++++++++++++
target-ppc/translate/vsx-impl.inc.c | 5 +++--
target-ppc/translate/vsx-ops.inc.c | 1 +
4 files changed, 26 insertions(+), 2 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 8b30420..6c5b194 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -541,6 +541,7 @@ DEF_HELPER_2(xvrspiz, void, env, i32)
DEF_HELPER_2(xxperm, void, env, i32)
DEF_HELPER_2(xxpermr, void, env, i32)
DEF_HELPER_4(xxextractuw, void, env, tl, tl, i32)
+DEF_HELPER_4(xxinsertw, void, env, tl, tl, i32)
DEF_HELPER_2(efscfsi, i32, env, i32)
DEF_HELPER_2(efscfui, i32, env, i32)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index e3f66ac..4d7eab6 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -2054,6 +2054,27 @@ void helper_xxextractuw(CPUPPCState *env, target_ulong xtn,
putVSR(xtn, &xt, env);
}
+void helper_xxinsertw(CPUPPCState *env, target_ulong xtn,
+ target_ulong xbn, uint32_t index)
+{
+ ppc_vsr_t xt, xb;
+ size_t es = sizeof(uint32_t);
+ uint32_t ins_index;
+
+ getVSR(xbn, &xb, env);
+ getVSR(xtn, &xt, env);
+
+#if defined(HOST_WORDS_BIGENDIAN)
+ ins_index = index;
+ memcpy(&xt.u8[ins_index], &xb.u8[8 - es], es);
+#else
+ ins_index = (16 - index) - es;
+ memcpy(&xt.u8[ins_index], &xb.u8[8], es);
+#endif
+
+ putVSR(xtn, &xt, env);
+}
+
#define VEXT_SIGNED(name, element, mask, cast, recast) \
void helper_##name(ppc_avr_t *r, ppc_avr_t *b) \
{ \
diff --git a/target-ppc/translate/vsx-impl.inc.c b/target-ppc/translate/vsx-impl.inc.c
index 1c40a35..9124e99 100644
--- a/target-ppc/translate/vsx-impl.inc.c
+++ b/target-ppc/translate/vsx-impl.inc.c
@@ -1180,7 +1180,7 @@ static void gen_xxsldwi(DisasContext *ctx)
tcg_temp_free_i64(xtl);
}
-#define VSX_EXTRACT(name) \
+#define VSX_EXTRACT_INSERT(name) \
static void gen_##name(DisasContext *ctx) \
{ \
TCGv xt, xb; \
@@ -1205,7 +1205,8 @@ static void gen_##name(DisasContext *ctx) \
tcg_temp_free_i32(t0); \
}
-VSX_EXTRACT(xxextractuw)
+VSX_EXTRACT_INSERT(xxextractuw)
+VSX_EXTRACT_INSERT(xxinsertw)
#undef GEN_XX2FORM
#undef GEN_XX3FORM
diff --git a/target-ppc/translate/vsx-ops.inc.c b/target-ppc/translate/vsx-ops.inc.c
index 473d925..096d358 100644
--- a/target-ppc/translate/vsx-ops.inc.c
+++ b/target-ppc/translate/vsx-ops.inc.c
@@ -285,6 +285,7 @@ GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
GEN_XX1FORM(xxspltib, 0x08, 0x0B, PPC2_ISA300),
GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
GEN_XX2FORM_EXT(xxextractuw, 0x0A, 0x0A, PPC2_ISA300),
+GEN_XX2FORM_EXT(xxinsertw, 0x0A, 0x0B, PPC2_ISA300),
#define GEN_XXSEL_ROW(opc3) \
GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
--
2.7.4
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [Qemu-devel] [PATCH v2 5/6] target-ppc: implement xxextractuw instruction
2016-12-09 12:17 ` [Qemu-devel] [PATCH v2 5/6] target-ppc: implement xxextractuw instruction Nikunj A Dadhania
@ 2016-12-12 0:30 ` David Gibson
2016-12-12 4:01 ` [Qemu-devel] [Qemu-ppc] " Nikunj Dadhania
0 siblings, 1 reply; 14+ messages in thread
From: David Gibson @ 2016-12-12 0:30 UTC (permalink / raw)
To: Nikunj A Dadhania; +Cc: qemu-ppc, rth, qemu-devel, bharata
[-- Attachment #1: Type: text/plain, Size: 6286 bytes --]
On Fri, Dec 09, 2016 at 05:47:24PM +0530, Nikunj A Dadhania wrote:
> xxextractuw: VSX Vector Extract Unsigned Word
>
> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
> ---
> target-ppc/helper.h | 1 +
> target-ppc/int_helper.c | 21 +++++++++++++++++++++
> target-ppc/translate/vsx-impl.inc.c | 27 +++++++++++++++++++++++++++
> target-ppc/translate/vsx-ops.inc.c | 5 +++++
> 4 files changed, 54 insertions(+)
>
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index 4707db4..8b30420 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -540,6 +540,7 @@ DEF_HELPER_2(xvrspip, void, env, i32)
> DEF_HELPER_2(xvrspiz, void, env, i32)
> DEF_HELPER_2(xxperm, void, env, i32)
> DEF_HELPER_2(xxpermr, void, env, i32)
> +DEF_HELPER_4(xxextractuw, void, env, tl, tl, i32)
>
> DEF_HELPER_2(efscfsi, i32, env, i32)
> DEF_HELPER_2(efscfui, i32, env, i32)
> diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
> index 7989b1f..e3f66ac 100644
> --- a/target-ppc/int_helper.c
> +++ b/target-ppc/int_helper.c
> @@ -2033,6 +2033,27 @@ VEXTRACT(uw, u32)
> VEXTRACT(d, u64)
> #undef VEXTRACT
>
> +void helper_xxextractuw(CPUPPCState *env, target_ulong xtn,
> + target_ulong xbn, uint32_t index)
> +{
> + ppc_vsr_t xt, xb;
> + size_t es = sizeof(uint32_t);
> + uint32_t ext_index;
> +
> + getVSR(xbn, &xb, env);
> + memset(&xt, 0, sizeof(xt));
> +
> +#if defined(HOST_WORDS_BIGENDIAN)
> + ext_index = index;
> + memcpy(&xt.u8[8 - es], &xb.u8[ext_index], es);
> +#else
> + ext_index = (16 - index) - es;
> + memcpy(&xt.u8[8], &xb.u8[ext_index], es);
Hm. So, IIUC, ext_index is the byte element - in IBM numbering - to
start copying from. But I thought that when we have an LE host, the
IBM byte element ordering is reversed from the actual order in host
memory, so we'd need &xb.u8[16 - ext_index - es]
> +#endif
> +
> + putVSR(xtn, &xt, env);
> +}
> +
> #define VEXT_SIGNED(name, element, mask, cast, recast) \
> void helper_##name(ppc_avr_t *r, ppc_avr_t *b) \
> { \
> diff --git a/target-ppc/translate/vsx-impl.inc.c b/target-ppc/translate/vsx-impl.inc.c
> index 2a17c35..1c40a35 100644
> --- a/target-ppc/translate/vsx-impl.inc.c
> +++ b/target-ppc/translate/vsx-impl.inc.c
> @@ -1180,6 +1180,33 @@ static void gen_xxsldwi(DisasContext *ctx)
> tcg_temp_free_i64(xtl);
> }
>
> +#define VSX_EXTRACT(name) \
> +static void gen_##name(DisasContext *ctx) \
> +{ \
> + TCGv xt, xb; \
> + TCGv_i32 t0 = tcg_temp_new_i32(); \
> + uint8_t uimm = UIMM4(ctx->opcode); \
> + \
> + if (unlikely(!ctx->vsx_enabled)) { \
> + gen_exception(ctx, POWERPC_EXCP_VSXU); \
> + return; \
> + } \
> + if (uimm > 12) { \
Throughout the helper you use es == sizeof(uint32_t), but here you
hardcode the assumption of 4 bytes, seems a bit inconsistent.
> + tcg_gen_movi_i64(cpu_vsrh(xT(ctx->opcode)), 0); \
> + tcg_gen_movi_i64(cpu_vsrl(xT(ctx->opcode)), 0); \
> + return; \
So, I know the architecture says it is undefined. But since you're
testing for the bogus case anyway, why not turn this into an
exception. That seems like it would be more helpful for debugging the
guest than just setting the result to zero. Or is this done to match
actual hardware behaviour?
> + } \
> + xt = tcg_const_tl(xT(ctx->opcode)); \
> + xb = tcg_const_tl(xB(ctx->opcode)); \
> + tcg_gen_movi_i32(t0, uimm); \
> + gen_helper_##name(cpu_env, xt, xb, t0); \
> + tcg_temp_free(xb); \
> + tcg_temp_free(xt); \
> + tcg_temp_free_i32(t0); \
> +}
> +
> +VSX_EXTRACT(xxextractuw)
> +
> #undef GEN_XX2FORM
> #undef GEN_XX3FORM
> #undef GEN_XX2IFORM
> diff --git a/target-ppc/translate/vsx-ops.inc.c b/target-ppc/translate/vsx-ops.inc.c
> index 46b95e3..473d925 100644
> --- a/target-ppc/translate/vsx-ops.inc.c
> +++ b/target-ppc/translate/vsx-ops.inc.c
> @@ -49,6 +49,10 @@ GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
> GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
> GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
>
> +#define GEN_XX2FORM_EXT(name, opc2, opc3, fl2) \
> +GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0x00100000, PPC_NONE, fl2), \
> +GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0x00100000, PPC_NONE, fl2)
> +
> #define GEN_XX2FORM_EO(name, opc2, opc3, opc4, fl2) \
> GEN_HANDLER2_E_2(name, #name, 0x3C, opc2 | 0, opc3, opc4, 0, PPC_NONE, fl2), \
> GEN_HANDLER2_E_2(name, #name, 0x3C, opc2 | 1, opc3, opc4, 0, PPC_NONE, fl2)
> @@ -280,6 +284,7 @@ GEN_XX3FORM(xxpermr, 0x08, 0x07, PPC2_ISA300),
> GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
> GEN_XX1FORM(xxspltib, 0x08, 0x0B, PPC2_ISA300),
> GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
> +GEN_XX2FORM_EXT(xxextractuw, 0x0A, 0x0A, PPC2_ISA300),
>
> #define GEN_XXSEL_ROW(opc3) \
> GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Qemu-devel] [PATCH v2 ppc-for-2.9 0/6] POWER9 TCG enablements - part9
2016-12-09 12:17 [Qemu-devel] [PATCH v2 ppc-for-2.9 0/6] POWER9 TCG enablements - part9 Nikunj A Dadhania
` (5 preceding siblings ...)
2016-12-09 12:17 ` [Qemu-devel] [PATCH v2 6/6] target-ppc: implement xxinsertw instruction Nikunj A Dadhania
@ 2016-12-12 0:32 ` David Gibson
6 siblings, 0 replies; 14+ messages in thread
From: David Gibson @ 2016-12-12 0:32 UTC (permalink / raw)
To: Nikunj A Dadhania; +Cc: qemu-ppc, rth, qemu-devel, bharata
[-- Attachment #1: Type: text/plain, Size: 1729 bytes --]
On Fri, Dec 09, 2016 at 05:47:19PM +0530, Nikunj A Dadhania wrote:
> This series contains 6 new instructions for POWER9 ISA3.0
> VSX Vector Insert/Extract Word
> VSX Load/Store with length
>
> Although, lxvl/lxvll and stxvl/stxvll can be combined as single patch,
> have left it for detailed commit log for instruction explanation.
I've applied patches 1-4 to ppc-for-2.9. 5 & 6 I still have some
questions about.
>
> Changelog:
> v1:
> * Combine helpers of lxvl and lxvll
> * Combine helpers of stxvl and stxvll
> * Rework xxextractuw and xxinsertw to simplify helper
>
> v0:
> * Fixed lxvl/lxvll and stxvl/stxvll as suggested by Richard
> * Dropped mask_u128, which is not needed anymore
> * Prevent UIMM > 12 in xxextractuw
> * Drop xori from xsnegqp
> * Rewrite xxperm/xxpermr without double copy
>
> Nikunj A Dadhania (6):
> target-ppc: implement lxvl instruction
> target-ppc: implement lxvll instruction
> target-ppc: implement stxvl instruction
> target-ppc: implement stxvll instructions
> target-ppc: implement xxextractuw instruction
> target-ppc: implement xxinsertw instruction
>
> target-ppc/helper.h | 8 +++++
> target-ppc/int_helper.c | 42 +++++++++++++++++++++++
> target-ppc/mem_helper.c | 66 +++++++++++++++++++++++++++++++++++++
> target-ppc/translate/vsx-impl.inc.c | 60 +++++++++++++++++++++++++++++++++
> target-ppc/translate/vsx-ops.inc.c | 14 ++++++++
> 5 files changed, 190 insertions(+)
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Qemu-devel] [Qemu-ppc] [PATCH v2 5/6] target-ppc: implement xxextractuw instruction
2016-12-12 0:30 ` David Gibson
@ 2016-12-12 4:01 ` Nikunj Dadhania
2016-12-12 4:07 ` David Gibson
0 siblings, 1 reply; 14+ messages in thread
From: Nikunj Dadhania @ 2016-12-12 4:01 UTC (permalink / raw)
To: David Gibson
Cc: Nikunj A Dadhania, Bharata B Rao, qemu-ppc, qemu-devel,
Richard Henderson
On 12 December 2016 at 06:00, David Gibson <david@gibson.dropbear.id.au> wrote:
> On Fri, Dec 09, 2016 at 05:47:24PM +0530, Nikunj A Dadhania wrote:
>> xxextractuw: VSX Vector Extract Unsigned Word
>>
>> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
>> ---
>> target-ppc/helper.h | 1 +
>> target-ppc/int_helper.c | 21 +++++++++++++++++++++
>> target-ppc/translate/vsx-impl.inc.c | 27 +++++++++++++++++++++++++++
>> target-ppc/translate/vsx-ops.inc.c | 5 +++++
>> 4 files changed, 54 insertions(+)
>>
>> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
>> index 4707db4..8b30420 100644
>> --- a/target-ppc/helper.h
>> +++ b/target-ppc/helper.h
>> @@ -540,6 +540,7 @@ DEF_HELPER_2(xvrspip, void, env, i32)
>> DEF_HELPER_2(xvrspiz, void, env, i32)
>> DEF_HELPER_2(xxperm, void, env, i32)
>> DEF_HELPER_2(xxpermr, void, env, i32)
>> +DEF_HELPER_4(xxextractuw, void, env, tl, tl, i32)
>>
>> DEF_HELPER_2(efscfsi, i32, env, i32)
>> DEF_HELPER_2(efscfui, i32, env, i32)
>> diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
>> index 7989b1f..e3f66ac 100644
>> --- a/target-ppc/int_helper.c
>> +++ b/target-ppc/int_helper.c
>> @@ -2033,6 +2033,27 @@ VEXTRACT(uw, u32)
>> VEXTRACT(d, u64)
>> #undef VEXTRACT
>>
>> +void helper_xxextractuw(CPUPPCState *env, target_ulong xtn,
>> + target_ulong xbn, uint32_t index)
>> +{
>> + ppc_vsr_t xt, xb;
>> + size_t es = sizeof(uint32_t);
>> + uint32_t ext_index;
>> +
>> + getVSR(xbn, &xb, env);
>> + memset(&xt, 0, sizeof(xt));
>> +
>> +#if defined(HOST_WORDS_BIGENDIAN)
>> + ext_index = index;
>> + memcpy(&xt.u8[8 - es], &xb.u8[ext_index], es);
>> +#else
>> + ext_index = (16 - index) - es;
>> + memcpy(&xt.u8[8], &xb.u8[ext_index], es);
>
> Hm. So, IIUC, ext_index is the byte element - in IBM numbering - to
> start copying from. But I thought that when we have an LE host, the
> IBM byte element ordering is reversed from the actual order in host
> memory, so we'd need &xb.u8[16 - ext_index - es]
I am not getting you, I am getting index from user. So in case of BE host:
ext_index = index;
LE Host:
ext_index = (16 - index) - es;
I am already doing that. Am I missing something.
>
>> +#endif
>> +
>> + putVSR(xtn, &xt, env);
>> +}
>> +
>> #define VEXT_SIGNED(name, element, mask, cast, recast) \
>> void helper_##name(ppc_avr_t *r, ppc_avr_t *b) \
>> { \
>> diff --git a/target-ppc/translate/vsx-impl.inc.c b/target-ppc/translate/vsx-impl.inc.c
>> index 2a17c35..1c40a35 100644
>> --- a/target-ppc/translate/vsx-impl.inc.c
>> +++ b/target-ppc/translate/vsx-impl.inc.c
>> @@ -1180,6 +1180,33 @@ static void gen_xxsldwi(DisasContext *ctx)
>> tcg_temp_free_i64(xtl);
>> }
>>
>> +#define VSX_EXTRACT(name) \
>> +static void gen_##name(DisasContext *ctx) \
>> +{ \
>> + TCGv xt, xb; \
>> + TCGv_i32 t0 = tcg_temp_new_i32(); \
>> + uint8_t uimm = UIMM4(ctx->opcode); \
>> + \
>> + if (unlikely(!ctx->vsx_enabled)) { \
>> + gen_exception(ctx, POWERPC_EXCP_VSXU); \
>> + return; \
>> + } \
>> + if (uimm > 12) { \
>
> Throughout the helper you use es == sizeof(uint32_t), but here you
> hardcode the assumption of 4 bytes, seems a bit inconsistent.
>
>> + tcg_gen_movi_i64(cpu_vsrh(xT(ctx->opcode)), 0); \
>> + tcg_gen_movi_i64(cpu_vsrl(xT(ctx->opcode)), 0); \
>> + return; \
>
> So, I know the architecture says it is undefined. But since you're
> testing for the bogus case anyway, why not turn this into an
> exception. That seems like it would be more helpful for debugging the
> guest than just setting the result to zero. Or is this done to match
> actual hardware behaviour?
I havent had a change to run on the real hardware, but on the system
simulator, it happily
returns extracted content even if UIMM > 12.
Regards
Nikunj
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Qemu-devel] [Qemu-ppc] [PATCH v2 5/6] target-ppc: implement xxextractuw instruction
2016-12-12 4:01 ` [Qemu-devel] [Qemu-ppc] " Nikunj Dadhania
@ 2016-12-12 4:07 ` David Gibson
2016-12-14 8:44 ` Nikunj A Dadhania
0 siblings, 1 reply; 14+ messages in thread
From: David Gibson @ 2016-12-12 4:07 UTC (permalink / raw)
To: Nikunj Dadhania
Cc: Nikunj A Dadhania, Bharata B Rao, qemu-ppc, qemu-devel,
Richard Henderson
[-- Attachment #1: Type: text/plain, Size: 5163 bytes --]
On Mon, Dec 12, 2016 at 09:31:11AM +0530, Nikunj Dadhania wrote:
> On 12 December 2016 at 06:00, David Gibson <david@gibson.dropbear.id.au> wrote:
> > On Fri, Dec 09, 2016 at 05:47:24PM +0530, Nikunj A Dadhania wrote:
> >> xxextractuw: VSX Vector Extract Unsigned Word
> >>
> >> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
> >> ---
> >> target-ppc/helper.h | 1 +
> >> target-ppc/int_helper.c | 21 +++++++++++++++++++++
> >> target-ppc/translate/vsx-impl.inc.c | 27 +++++++++++++++++++++++++++
> >> target-ppc/translate/vsx-ops.inc.c | 5 +++++
> >> 4 files changed, 54 insertions(+)
> >>
> >> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> >> index 4707db4..8b30420 100644
> >> --- a/target-ppc/helper.h
> >> +++ b/target-ppc/helper.h
> >> @@ -540,6 +540,7 @@ DEF_HELPER_2(xvrspip, void, env, i32)
> >> DEF_HELPER_2(xvrspiz, void, env, i32)
> >> DEF_HELPER_2(xxperm, void, env, i32)
> >> DEF_HELPER_2(xxpermr, void, env, i32)
> >> +DEF_HELPER_4(xxextractuw, void, env, tl, tl, i32)
> >>
> >> DEF_HELPER_2(efscfsi, i32, env, i32)
> >> DEF_HELPER_2(efscfui, i32, env, i32)
> >> diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
> >> index 7989b1f..e3f66ac 100644
> >> --- a/target-ppc/int_helper.c
> >> +++ b/target-ppc/int_helper.c
> >> @@ -2033,6 +2033,27 @@ VEXTRACT(uw, u32)
> >> VEXTRACT(d, u64)
> >> #undef VEXTRACT
> >>
> >> +void helper_xxextractuw(CPUPPCState *env, target_ulong xtn,
> >> + target_ulong xbn, uint32_t index)
> >> +{
> >> + ppc_vsr_t xt, xb;
> >> + size_t es = sizeof(uint32_t);
> >> + uint32_t ext_index;
> >> +
> >> + getVSR(xbn, &xb, env);
> >> + memset(&xt, 0, sizeof(xt));
> >> +
> >> +#if defined(HOST_WORDS_BIGENDIAN)
> >> + ext_index = index;
> >> + memcpy(&xt.u8[8 - es], &xb.u8[ext_index], es);
> >> +#else
> >> + ext_index = (16 - index) - es;
> >> + memcpy(&xt.u8[8], &xb.u8[ext_index], es);
> >
> > Hm. So, IIUC, ext_index is the byte element - in IBM numbering - to
> > start copying from. But I thought that when we have an LE host, the
> > IBM byte element ordering is reversed from the actual order in host
> > memory, so we'd need &xb.u8[16 - ext_index - es]
>
> I am not getting you, I am getting index from user. So in case of BE host:
>
> ext_index = index;
>
> LE Host:
>
> ext_index = (16 - index) - es;
>
> I am already doing that. Am I missing something.
Duh, sorry, apparently I'm blind and missed that logic.
> >> +#endif
> >> +
> >> + putVSR(xtn, &xt, env);
> >> +}
> >> +
> >> #define VEXT_SIGNED(name, element, mask, cast, recast) \
> >> void helper_##name(ppc_avr_t *r, ppc_avr_t *b) \
> >> { \
> >> diff --git a/target-ppc/translate/vsx-impl.inc.c b/target-ppc/translate/vsx-impl.inc.c
> >> index 2a17c35..1c40a35 100644
> >> --- a/target-ppc/translate/vsx-impl.inc.c
> >> +++ b/target-ppc/translate/vsx-impl.inc.c
> >> @@ -1180,6 +1180,33 @@ static void gen_xxsldwi(DisasContext *ctx)
> >> tcg_temp_free_i64(xtl);
> >> }
> >>
> >> +#define VSX_EXTRACT(name) \
> >> +static void gen_##name(DisasContext *ctx) \
> >> +{ \
> >> + TCGv xt, xb; \
> >> + TCGv_i32 t0 = tcg_temp_new_i32(); \
> >> + uint8_t uimm = UIMM4(ctx->opcode); \
> >> + \
> >> + if (unlikely(!ctx->vsx_enabled)) { \
> >> + gen_exception(ctx, POWERPC_EXCP_VSXU); \
> >> + return; \
> >> + } \
> >> + if (uimm > 12) { \
> >
> > Throughout the helper you use es == sizeof(uint32_t), but here you
> > hardcode the assumption of 4 bytes, seems a bit inconsistent.
> >
> >> + tcg_gen_movi_i64(cpu_vsrh(xT(ctx->opcode)), 0); \
> >> + tcg_gen_movi_i64(cpu_vsrl(xT(ctx->opcode)), 0); \
> >> + return; \
> >
> > So, I know the architecture says it is undefined. But since you're
> > testing for the bogus case anyway, why not turn this into an
> > exception. That seems like it would be more helpful for debugging the
> > guest than just setting the result to zero. Or is this done to match
> > actual hardware behaviour?
>
> I havent had a change to run on the real hardware, but on the system
> simulator, it happily
> returns extracted content even if UIMM > 12.
Hm. Returns what exactly?
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Qemu-devel] [Qemu-ppc] [PATCH v2 5/6] target-ppc: implement xxextractuw instruction
2016-12-12 4:07 ` David Gibson
@ 2016-12-14 8:44 ` Nikunj A Dadhania
2016-12-16 4:19 ` David Gibson
0 siblings, 1 reply; 14+ messages in thread
From: Nikunj A Dadhania @ 2016-12-14 8:44 UTC (permalink / raw)
To: David Gibson, Nikunj Dadhania
Cc: Bharata B Rao, qemu-ppc, qemu-devel, Richard Henderson
David Gibson <david@gibson.dropbear.id.au> writes:
> [ Unknown signature status ]
> On Mon, Dec 12, 2016 at 09:31:11AM +0530, Nikunj Dadhania wrote:
>> On 12 December 2016 at 06:00, David Gibson <david@gibson.dropbear.id.au> wrote:
>> > On Fri, Dec 09, 2016 at 05:47:24PM +0530, Nikunj A Dadhania wrote:
>> >> xxextractuw: VSX Vector Extract Unsigned Word
>> >>
>> >> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
>> >> + tcg_gen_movi_i64(cpu_vsrh(xT(ctx->opcode)), 0); \
>> >> + tcg_gen_movi_i64(cpu_vsrl(xT(ctx->opcode)), 0); \
>> >> + return; \
>> >
>> > So, I know the architecture says it is undefined. But since you're
>> > testing for the bogus case anyway, why not turn this into an
>> > exception. That seems like it would be more helpful for debugging the
>> > guest than just setting the result to zero. Or is this done to match
>> > actual hardware behaviour?
>>
>> I havent had a change to run on the real hardware, but on the system
>> simulator, it happily
>> returns extracted content even if UIMM > 12.
>
> Hm. Returns what exactly?
So for LE case extracting from 15 returns following, basically its
rounding up to 0.
xxextractuw: 15 - ooTSET a si sihT
________ihTo____
Regards,
Nikunj
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Qemu-devel] [Qemu-ppc] [PATCH v2 5/6] target-ppc: implement xxextractuw instruction
2016-12-14 8:44 ` Nikunj A Dadhania
@ 2016-12-16 4:19 ` David Gibson
2016-12-19 4:25 ` Nikunj A Dadhania
0 siblings, 1 reply; 14+ messages in thread
From: David Gibson @ 2016-12-16 4:19 UTC (permalink / raw)
To: Nikunj A Dadhania
Cc: Nikunj Dadhania, Bharata B Rao, qemu-ppc, qemu-devel, Richard Henderson
[-- Attachment #1: Type: text/plain, Size: 1932 bytes --]
On Wed, Dec 14, 2016 at 02:14:26PM +0530, Nikunj A Dadhania wrote:
> David Gibson <david@gibson.dropbear.id.au> writes:
>
> > [ Unknown signature status ]
> > On Mon, Dec 12, 2016 at 09:31:11AM +0530, Nikunj Dadhania wrote:
> >> On 12 December 2016 at 06:00, David Gibson <david@gibson.dropbear.id.au> wrote:
> >> > On Fri, Dec 09, 2016 at 05:47:24PM +0530, Nikunj A Dadhania wrote:
> >> >> xxextractuw: VSX Vector Extract Unsigned Word
> >> >>
> >> >> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
> >> >> + tcg_gen_movi_i64(cpu_vsrh(xT(ctx->opcode)), 0); \
> >> >> + tcg_gen_movi_i64(cpu_vsrl(xT(ctx->opcode)), 0); \
> >> >> + return; \
> >> >
> >> > So, I know the architecture says it is undefined. But since you're
> >> > testing for the bogus case anyway, why not turn this into an
> >> > exception. That seems like it would be more helpful for debugging the
> >> > guest than just setting the result to zero. Or is this done to match
> >> > actual hardware behaviour?
> >>
> >> I havent had a change to run on the real hardware, but on the system
> >> simulator, it happily
> >> returns extracted content even if UIMM > 12.
> >
> > Hm. Returns what exactly?
>
> So for LE case extracting from 15 returns following, basically its
> rounding up to 0.
> xxextractuw: 15 - ooTSET a si sihT
> ________ihTo____
Ok. IIRC your implementation did not do this - it set the
"overflowed" bytes to 0 instead of wrapping round and taking them from
the other end of the input. If think we should either match hardware
behaviour or simply trap here, rather than do something else.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Qemu-devel] [Qemu-ppc] [PATCH v2 5/6] target-ppc: implement xxextractuw instruction
2016-12-16 4:19 ` David Gibson
@ 2016-12-19 4:25 ` Nikunj A Dadhania
0 siblings, 0 replies; 14+ messages in thread
From: Nikunj A Dadhania @ 2016-12-19 4:25 UTC (permalink / raw)
To: David Gibson
Cc: Nikunj Dadhania, Bharata B Rao, qemu-ppc, qemu-devel, Richard Henderson
David Gibson <david@gibson.dropbear.id.au> writes:
> [ Unknown signature status ]
> On Wed, Dec 14, 2016 at 02:14:26PM +0530, Nikunj A Dadhania wrote:
>> David Gibson <david@gibson.dropbear.id.au> writes:
>>
>> > [ Unknown signature status ]
>> > On Mon, Dec 12, 2016 at 09:31:11AM +0530, Nikunj Dadhania wrote:
>> >> On 12 December 2016 at 06:00, David Gibson <david@gibson.dropbear.id.au> wrote:
>> >> > On Fri, Dec 09, 2016 at 05:47:24PM +0530, Nikunj A Dadhania wrote:
>> >> >> xxextractuw: VSX Vector Extract Unsigned Word
>> >> >>
>> >> >> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
>> >> >> + tcg_gen_movi_i64(cpu_vsrh(xT(ctx->opcode)), 0); \
>> >> >> + tcg_gen_movi_i64(cpu_vsrl(xT(ctx->opcode)), 0); \
>> >> >> + return; \
>> >> >
>> >> > So, I know the architecture says it is undefined. But since you're
>> >> > testing for the bogus case anyway, why not turn this into an
>> >> > exception. That seems like it would be more helpful for debugging the
>> >> > guest than just setting the result to zero. Or is this done to match
>> >> > actual hardware behaviour?
>> >>
>> >> I havent had a change to run on the real hardware, but on the system
>> >> simulator, it happily
>> >> returns extracted content even if UIMM > 12.
>> >
>> > Hm. Returns what exactly?
>>
>> So for LE case extracting from 15 returns following, basically its
>> rounding up to 0.
>
>> xxextractuw: 15 - ooTSET a si sihT
>> ________ihTo____
>
> Ok. IIRC your implementation did not do this - it set the
> "overflowed" bytes to 0 instead of wrapping round and taking them from
> the other end of the input. If think we should either match hardware
> behaviour or simply trap here, rather than do something else.
Sure, will update and send the patch matching hardware behaviour.
Regards
Nikunj
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2016-12-19 4:25 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-12-09 12:17 [Qemu-devel] [PATCH v2 ppc-for-2.9 0/6] POWER9 TCG enablements - part9 Nikunj A Dadhania
2016-12-09 12:17 ` [Qemu-devel] [PATCH v2 1/6] target-ppc: implement lxvl instruction Nikunj A Dadhania
2016-12-09 12:17 ` [Qemu-devel] [PATCH v2 2/6] target-ppc: implement lxvll instruction Nikunj A Dadhania
2016-12-09 12:17 ` [Qemu-devel] [PATCH v2 3/6] target-ppc: implement stxvl instruction Nikunj A Dadhania
2016-12-09 12:17 ` [Qemu-devel] [PATCH v2 4/6] target-ppc: implement stxvll instructions Nikunj A Dadhania
2016-12-09 12:17 ` [Qemu-devel] [PATCH v2 5/6] target-ppc: implement xxextractuw instruction Nikunj A Dadhania
2016-12-12 0:30 ` David Gibson
2016-12-12 4:01 ` [Qemu-devel] [Qemu-ppc] " Nikunj Dadhania
2016-12-12 4:07 ` David Gibson
2016-12-14 8:44 ` Nikunj A Dadhania
2016-12-16 4:19 ` David Gibson
2016-12-19 4:25 ` Nikunj A Dadhania
2016-12-09 12:17 ` [Qemu-devel] [PATCH v2 6/6] target-ppc: implement xxinsertw instruction Nikunj A Dadhania
2016-12-12 0:32 ` [Qemu-devel] [PATCH v2 ppc-for-2.9 0/6] POWER9 TCG enablements - part9 David Gibson
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