* [PATCH 01/25] drm/amd/display: Null check clock source.
[not found] ` <20170123143613.15441-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
@ 2017-01-23 14:35 ` Harry Wentland
2017-01-23 14:35 ` [PATCH 02/25] drm/amd/display: Output Transfer Function Regamma Refactor Harry Wentland
` (23 subsequent siblings)
24 siblings, 0 replies; 27+ messages in thread
From: Harry Wentland @ 2017-01-23 14:35 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Yongqiang Sun
From: Yongqiang Sun <yongqiang.sun@amd.com>
Change-Id: Ifcec8c22d0df9434a470e2abc1bc77f503d9c0f7
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index 55d96656e54b..b0ac94d673c4 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -74,7 +74,8 @@ void dp_enable_link_phy(
if (pipes[i].stream != NULL &&
pipes[i].stream->sink != NULL &&
pipes[i].stream->sink->link == link) {
- if (pipes[i].clock_source->id != CLOCK_SOURCE_ID_DP_DTO) {
+ if (pipes[i].clock_source != NULL &&
+ pipes[i].clock_source->id != CLOCK_SOURCE_ID_DP_DTO) {
pipes[i].clock_source = dp_cs;
pipes[i].pix_clk_params.requested_pix_clk =
pipes[i].stream->public.timing.pix_clk_khz;
--
2.9.3
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 02/25] drm/amd/display: Output Transfer Function Regamma Refactor
[not found] ` <20170123143613.15441-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
2017-01-23 14:35 ` [PATCH 01/25] drm/amd/display: Null check clock source Harry Wentland
@ 2017-01-23 14:35 ` Harry Wentland
2017-01-23 14:35 ` [PATCH 03/25] drm/amd/display: Disable Modules at Runtime Harry Wentland
` (22 subsequent siblings)
24 siblings, 0 replies; 27+ messages in thread
From: Harry Wentland @ 2017-01-23 14:35 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Amy Zhang
From: Amy Zhang <Amy.Zhang@amd.com>
- Create translation function to translate logical format to hw format
- Refactor to use transfer function in dc instead of input gamma
Change-Id: If7ea756ea206c3776ab328f3b351ce546ae080a0
Signed-off-by: Amy Zhang <Amy.Zhang@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
---
drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c | 9 +
drivers/gpu/drm/amd/display/dc/calcs/Makefile | 2 +-
drivers/gpu/drm/amd/display/dc/calcs/gamma_calcs.c | 1481 --------------------
drivers/gpu/drm/amd/display/dc/core/dc.c | 10 +-
drivers/gpu/drm/amd/display/dc/dc.h | 11 +-
.../amd/display/dc/dce110/dce110_hw_sequencer.c | 440 +++++-
drivers/gpu/drm/amd/display/dc/inc/gamma_calcs.h | 20 -
drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 2 -
drivers/gpu/drm/amd/display/include/fixed31_32.h | 8 +
9 files changed, 466 insertions(+), 1517 deletions(-)
delete mode 100644 drivers/gpu/drm/amd/display/dc/calcs/gamma_calcs.c
delete mode 100644 drivers/gpu/drm/amd/display/dc/inc/gamma_calcs.h
diff --git a/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c b/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c
index 5a6e46843502..546ed67c6f83 100644
--- a/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c
+++ b/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c
@@ -246,6 +246,15 @@ struct fixed31_32 dal_fixed31_32_add(
return res;
}
+struct fixed31_32 dal_fixed31_32_add_int(
+ struct fixed31_32 arg1,
+ int32_t arg2)
+{
+ return dal_fixed31_32_add(
+ arg1,
+ dal_fixed31_32_from_int(arg2));
+}
+
struct fixed31_32 dal_fixed31_32_sub_int(
struct fixed31_32 arg1,
int32_t arg2)
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/Makefile b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
index 4001933e7808..4bb08aea6a03 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
@@ -3,7 +3,7 @@
# It calculates Bandwidth and Watermarks values for HW programming
#
-BW_CALCS = bandwidth_calcs.o bw_fixed.o gamma_calcs.o
+BW_CALCS = bandwidth_calcs.o bw_fixed.o
AMD_DAL_BW_CALCS = $(addprefix $(AMDDALPATH)/dc/calcs/,$(BW_CALCS))
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/gamma_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/gamma_calcs.c
deleted file mode 100644
index fd300db833c7..000000000000
--- a/drivers/gpu/drm/amd/display/dc/calcs/gamma_calcs.c
+++ /dev/null
@@ -1,1481 +0,0 @@
-/*
- * Copyright 2015 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-#include "gamma_calcs.h"
-
-struct curve_config {
- uint32_t offset;
- int8_t segments[16];
- int8_t begin;
-};
-
-static bool build_custom_float(
- struct fixed31_32 value,
- const struct custom_float_format *format,
- bool *negative,
- uint32_t *mantissa,
- uint32_t *exponenta)
-{
- uint32_t exp_offset = (1 << (format->exponenta_bits - 1)) - 1;
-
- const struct fixed31_32 mantissa_constant_plus_max_fraction =
- dal_fixed31_32_from_fraction(
- (1LL << (format->mantissa_bits + 1)) - 1,
- 1LL << format->mantissa_bits);
-
- struct fixed31_32 mantiss;
-
- if (dal_fixed31_32_eq(
- value,
- dal_fixed31_32_zero)) {
- *negative = false;
- *mantissa = 0;
- *exponenta = 0;
- return true;
- }
-
- if (dal_fixed31_32_lt(
- value,
- dal_fixed31_32_zero)) {
- *negative = format->sign;
- value = dal_fixed31_32_neg(value);
- } else {
- *negative = false;
- }
-
- if (dal_fixed31_32_lt(
- value,
- dal_fixed31_32_one)) {
- uint32_t i = 1;
-
- do {
- value = dal_fixed31_32_shl(value, 1);
- ++i;
- } while (dal_fixed31_32_lt(
- value,
- dal_fixed31_32_one));
-
- --i;
-
- if (exp_offset <= i) {
- *mantissa = 0;
- *exponenta = 0;
- return true;
- }
-
- *exponenta = exp_offset - i;
- } else if (dal_fixed31_32_le(
- mantissa_constant_plus_max_fraction,
- value)) {
- uint32_t i = 1;
-
- do {
- value = dal_fixed31_32_shr(value, 1);
- ++i;
- } while (dal_fixed31_32_lt(
- mantissa_constant_plus_max_fraction,
- value));
-
- *exponenta = exp_offset + i - 1;
- } else {
- *exponenta = exp_offset;
- }
-
- mantiss = dal_fixed31_32_sub(
- value,
- dal_fixed31_32_one);
-
- if (dal_fixed31_32_lt(
- mantiss,
- dal_fixed31_32_zero) ||
- dal_fixed31_32_lt(
- dal_fixed31_32_one,
- mantiss))
- mantiss = dal_fixed31_32_zero;
- else
- mantiss = dal_fixed31_32_shl(
- mantiss,
- format->mantissa_bits);
-
- *mantissa = dal_fixed31_32_floor(mantiss);
-
- return true;
-}
-
-static bool setup_custom_float(
- const struct custom_float_format *format,
- bool negative,
- uint32_t mantissa,
- uint32_t exponenta,
- uint32_t *result)
-{
- uint32_t i = 0;
- uint32_t j = 0;
-
- uint32_t value = 0;
-
- /* verification code:
- * once calculation is ok we can remove it
- */
-
- const uint32_t mantissa_mask =
- (1 << (format->mantissa_bits + 1)) - 1;
-
- const uint32_t exponenta_mask =
- (1 << (format->exponenta_bits + 1)) - 1;
-
- if (mantissa & ~mantissa_mask) {
- BREAK_TO_DEBUGGER();
- mantissa = mantissa_mask;
- }
-
- if (exponenta & ~exponenta_mask) {
- BREAK_TO_DEBUGGER();
- exponenta = exponenta_mask;
- }
-
- /* end of verification code */
-
- while (i < format->mantissa_bits) {
- uint32_t mask = 1 << i;
-
- if (mantissa & mask)
- value |= mask;
-
- ++i;
- }
-
- while (j < format->exponenta_bits) {
- uint32_t mask = 1 << j;
-
- if (exponenta & mask)
- value |= mask << i;
-
- ++j;
- }
-
- if (negative && format->sign)
- value |= 1 << (i + j);
-
- *result = value;
-
- return true;
-}
-
-static bool build_hw_curve_configuration(
- const struct curve_config *curve_config,
- struct gamma_curve *gamma_curve,
- struct curve_points *curve_points,
- struct hw_x_point *points,
- uint32_t *number_of_points)
-{
- const int8_t max_regions_number = ARRAY_SIZE(curve_config->segments);
-
- int8_t i;
-
- uint8_t segments_calculation[8] = { 0 };
-
- struct fixed31_32 region1 = dal_fixed31_32_zero;
- struct fixed31_32 region2;
- struct fixed31_32 increment;
-
- uint32_t index = 0;
- uint32_t segments = 0;
- uint32_t max_number;
-
- int8_t num_regions = 0;
-
- bool result = false;
-
- if (!number_of_points) {
- BREAK_TO_DEBUGGER();
- return false;
- }
-
- max_number = *number_of_points;
-
- i = 0;
-
- while (i != max_regions_number) {
- gamma_curve[i].offset = 0;
- gamma_curve[i].segments_num = 0;
-
- ++i;
- }
-
- i = 0;
-
- while (i != max_regions_number) {
- /* number should go in uninterruptible sequence */
- if (curve_config->segments[i] == -1)
- break;
-
- ASSERT(curve_config->segments[i] >= 0);
-
- segments += (1 << curve_config->segments[i]);
- ++num_regions;
-
- ++i;
- }
-
- if (segments > max_number) {
- BREAK_TO_DEBUGGER();
- } else {
- int32_t divisor;
- uint32_t offset = 0;
- int8_t begin = curve_config->begin;
- int32_t region_number = 0;
-
- i = begin;
-
- while ((index < max_number) &&
- (region_number < max_regions_number) &&
- (i < (begin + num_regions))) {
- int32_t j = 0;
-
- segments = curve_config->segments[region_number];
- divisor = 1 << segments;
-
- if (segments == -1) {
- if (i > 0) {
- region1 = dal_fixed31_32_shl(
- dal_fixed31_32_one,
- i - 1);
- region2 = dal_fixed31_32_shl(
- dal_fixed31_32_one,
- i);
- } else {
- region1 = dal_fixed31_32_shr(
- dal_fixed31_32_one,
- -(i - 1));
- region2 = dal_fixed31_32_shr(
- dal_fixed31_32_one,
- -i);
- }
-
- break;
- }
-
- if (i > -1) {
- region1 = dal_fixed31_32_shl(
- dal_fixed31_32_one,
- i);
- region2 = dal_fixed31_32_shl(
- dal_fixed31_32_one,
- i + 1);
- } else {
- region1 = dal_fixed31_32_shr(
- dal_fixed31_32_one,
- -i);
- region2 = dal_fixed31_32_shr(
- dal_fixed31_32_one,
- -(i + 1));
- }
-
- gamma_curve[region_number].offset = offset;
- gamma_curve[region_number].segments_num = segments;
-
- offset += divisor;
-
- ++segments_calculation[segments];
-
- increment = dal_fixed31_32_div_int(
- dal_fixed31_32_sub(
- region2,
- region1),
- divisor);
-
- points[index].x = region1;
- points[index].adjusted_x = region1;
-
- ++index;
- ++region_number;
-
- while ((index < max_number) && (j < divisor - 1)) {
- region1 = dal_fixed31_32_add(
- region1,
- increment);
-
- points[index].x = region1;
- points[index].adjusted_x = region1;
-
- ++index;
- ++j;
- }
-
- ++i;
- }
-
- points[index].x = region1;
- points[index].adjusted_x = region1;
-
- *number_of_points = index;
-
- result = true;
- }
-
- curve_points[0].x = points[0].adjusted_x;
- curve_points[0].offset = dal_fixed31_32_zero;
-
- curve_points[1].x = points[index - 1].adjusted_x;
- curve_points[1].offset = dal_fixed31_32_zero;
-
- curve_points[2].x = points[index].adjusted_x;
- curve_points[2].offset = dal_fixed31_32_zero;
-
- return result;
-}
-
-static bool setup_distribution_points_pq(
- struct gamma_curve *arr_curve_points,
- struct curve_points *arr_points,
- uint32_t *hw_points_num,
- struct hw_x_point *coordinates_x,
- enum surface_pixel_format format)
-{
- struct curve_config cfg;
-
- cfg.offset = 0;
- cfg.segments[0] = 2;
- cfg.segments[1] = 2;
- cfg.segments[2] = 2;
- cfg.segments[3] = 2;
- cfg.segments[4] = 2;
- cfg.segments[5] = 2;
- cfg.segments[6] = 3;
- cfg.segments[7] = 4;
- cfg.segments[8] = 4;
- cfg.segments[9] = 4;
- cfg.segments[10] = 4;
- cfg.segments[11] = 5;
- cfg.segments[12] = 5;
- cfg.segments[13] = 5;
- cfg.segments[14] = 5;
- cfg.segments[15] = 5;
-
- if (format == SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F ||
- format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F)
- cfg.begin = -11;
- else
- cfg.begin = -16;
-
- if (!build_hw_curve_configuration(
- &cfg, arr_curve_points,
- arr_points,
- coordinates_x, hw_points_num)) {
- ASSERT_CRITICAL(false);
- return false;
- }
- return true;
-}
-
-static bool setup_distribution_points(
- struct gamma_curve *arr_curve_points,
- struct curve_points *arr_points,
- uint32_t *hw_points_num,
- struct hw_x_point *coordinates_x)
-{
- struct curve_config cfg;
-
- cfg.offset = 0;
- cfg.segments[0] = 3;
- cfg.segments[1] = 4;
- cfg.segments[2] = 4;
- cfg.segments[3] = 4;
- cfg.segments[4] = 4;
- cfg.segments[5] = 4;
- cfg.segments[6] = 4;
- cfg.segments[7] = 4;
- cfg.segments[8] = 5;
- cfg.segments[9] = 5;
- cfg.segments[10] = 0;
- cfg.segments[11] = -1;
- cfg.segments[12] = -1;
- cfg.segments[13] = -1;
- cfg.segments[14] = -1;
- cfg.segments[15] = -1;
-
- cfg.begin = -10;
-
- if (!build_hw_curve_configuration(
- &cfg, arr_curve_points,
- arr_points,
- coordinates_x, hw_points_num)) {
- ASSERT_CRITICAL(false);
- return false;
- }
- return true;
-}
-
-struct dividers {
- struct fixed31_32 divider1;
- struct fixed31_32 divider2;
- struct fixed31_32 divider3;
-};
-
-static void build_regamma_coefficients(struct gamma_coefficients *coefficients)
-{
- /* sRGB should apply 2.4 */
- static const int32_t numerator01[3] = { 31308, 31308, 31308 };
- static const int32_t numerator02[3] = { 12920, 12920, 12920 };
- static const int32_t numerator03[3] = { 55, 55, 55 };
- static const int32_t numerator04[3] = { 55, 55, 55 };
- static const int32_t numerator05[3] = { 2400, 2400, 2400 };
-
- const int32_t *numerator1;
- const int32_t *numerator2;
- const int32_t *numerator3;
- const int32_t *numerator4;
- const int32_t *numerator5;
-
- uint32_t i = 0;
-
- numerator1 = numerator01;
- numerator2 = numerator02;
- numerator3 = numerator03;
- numerator4 = numerator04;
- numerator5 = numerator05;
-
- do {
- coefficients->a0[i] = dal_fixed31_32_from_fraction(
- numerator1[i], 10000000);
- coefficients->a1[i] = dal_fixed31_32_from_fraction(
- numerator2[i], 1000);
- coefficients->a2[i] = dal_fixed31_32_from_fraction(
- numerator3[i], 1000);
- coefficients->a3[i] = dal_fixed31_32_from_fraction(
- numerator4[i], 1000);
- coefficients->user_gamma[i] = dal_fixed31_32_from_fraction(
- numerator5[i], 1000);
-
- ++i;
- } while (i != ARRAY_SIZE(coefficients->a0));
-}
-
-static struct fixed31_32 translate_from_linear_space(
- struct fixed31_32 arg,
- struct fixed31_32 a0,
- struct fixed31_32 a1,
- struct fixed31_32 a2,
- struct fixed31_32 a3,
- struct fixed31_32 gamma)
-{
- const struct fixed31_32 one = dal_fixed31_32_from_int(1);
-
- if (dal_fixed31_32_le(arg, dal_fixed31_32_neg(a0)))
- return dal_fixed31_32_sub(
- a2,
- dal_fixed31_32_mul(
- dal_fixed31_32_add(
- one,
- a3),
- dal_fixed31_32_pow(
- dal_fixed31_32_neg(arg),
- dal_fixed31_32_recip(gamma))));
- else if (dal_fixed31_32_le(a0, arg))
- return dal_fixed31_32_sub(
- dal_fixed31_32_mul(
- dal_fixed31_32_add(
- one,
- a3),
- dal_fixed31_32_pow(
- arg,
- dal_fixed31_32_recip(gamma))),
- a2);
- else
- return dal_fixed31_32_mul(
- arg,
- a1);
-}
-
-static inline struct fixed31_32 translate_from_linear_space_ex(
- struct fixed31_32 arg,
- struct gamma_coefficients *coeff,
- uint32_t color_index)
-{
- return translate_from_linear_space(
- arg,
- coeff->a0[color_index],
- coeff->a1[color_index],
- coeff->a2[color_index],
- coeff->a3[color_index],
- coeff->user_gamma[color_index]);
-}
-
-static bool find_software_points(
- const struct gamma_pixel *axis_x_256,
- struct fixed31_32 hw_point,
- enum channel_name channel,
- uint32_t *index_to_start,
- uint32_t *index_left,
- uint32_t *index_right,
- enum hw_point_position *pos)
-{
- const uint32_t max_number = INPUT_LUT_ENTRIES + 3;
-
- struct fixed31_32 left, right;
-
- uint32_t i = *index_to_start;
-
- while (i < max_number) {
- if (channel == CHANNEL_NAME_RED) {
- left = axis_x_256[i].r;
-
- if (i < max_number - 1)
- right = axis_x_256[i + 1].r;
- else
- right = axis_x_256[max_number - 1].r;
- } else if (channel == CHANNEL_NAME_GREEN) {
- left = axis_x_256[i].g;
-
- if (i < max_number - 1)
- right = axis_x_256[i + 1].g;
- else
- right = axis_x_256[max_number - 1].g;
- } else {
- left = axis_x_256[i].b;
-
- if (i < max_number - 1)
- right = axis_x_256[i + 1].b;
- else
- right = axis_x_256[max_number - 1].b;
- }
-
- if (dal_fixed31_32_le(left, hw_point) &&
- dal_fixed31_32_le(hw_point, right)) {
- *index_to_start = i;
- *index_left = i;
-
- if (i < max_number - 1)
- *index_right = i + 1;
- else
- *index_right = max_number - 1;
-
- *pos = HW_POINT_POSITION_MIDDLE;
-
- return true;
- } else if ((i == *index_to_start) &&
- dal_fixed31_32_le(hw_point, left)) {
- *index_to_start = i;
- *index_left = i;
- *index_right = i;
-
- *pos = HW_POINT_POSITION_LEFT;
-
- return true;
- } else if ((i == max_number - 1) &&
- dal_fixed31_32_le(right, hw_point)) {
- *index_to_start = i;
- *index_left = i;
- *index_right = i;
-
- *pos = HW_POINT_POSITION_RIGHT;
-
- return true;
- }
-
- ++i;
- }
-
- return false;
-}
-
-static bool build_custom_gamma_mapping_coefficients_worker(
- struct pixel_gamma_point *coeff,
- const struct hw_x_point *coordinates_x,
- const struct gamma_pixel *axis_x_256,
- enum channel_name channel,
- uint32_t number_of_points,
- enum surface_pixel_format pixel_format)
-{
- uint32_t i = 0;
-
- while (i <= number_of_points) {
- struct fixed31_32 coord_x;
-
- uint32_t index_to_start = 0;
- uint32_t index_left = 0;
- uint32_t index_right = 0;
-
- enum hw_point_position hw_pos;
-
- struct gamma_point *point;
-
- struct fixed31_32 left_pos;
- struct fixed31_32 right_pos;
-
- /*
- * TODO: confirm enum in surface_pixel_format
- * if (pixel_format == PIXEL_FORMAT_FP16)
- *coord_x = coordinates_x[i].adjusted_x;
- *else
- */
- if (channel == CHANNEL_NAME_RED)
- coord_x = coordinates_x[i].regamma_y_red;
- else if (channel == CHANNEL_NAME_GREEN)
- coord_x = coordinates_x[i].regamma_y_green;
- else
- coord_x = coordinates_x[i].regamma_y_blue;
-
- if (!find_software_points(
- axis_x_256, coord_x, channel,
- &index_to_start, &index_left, &index_right, &hw_pos)) {
- BREAK_TO_DEBUGGER();
- return false;
- }
-
- if (index_left >= INPUT_LUT_ENTRIES + 3) {
- BREAK_TO_DEBUGGER();
- return false;
- }
-
- if (index_right >= INPUT_LUT_ENTRIES + 3) {
- BREAK_TO_DEBUGGER();
- return false;
- }
-
- if (channel == CHANNEL_NAME_RED) {
- point = &coeff[i].r;
-
- left_pos = axis_x_256[index_left].r;
- right_pos = axis_x_256[index_right].r;
- } else if (channel == CHANNEL_NAME_GREEN) {
- point = &coeff[i].g;
-
- left_pos = axis_x_256[index_left].g;
- right_pos = axis_x_256[index_right].g;
- } else {
- point = &coeff[i].b;
-
- left_pos = axis_x_256[index_left].b;
- right_pos = axis_x_256[index_right].b;
- }
-
- if (hw_pos == HW_POINT_POSITION_MIDDLE)
- point->coeff = dal_fixed31_32_div(
- dal_fixed31_32_sub(
- coord_x,
- left_pos),
- dal_fixed31_32_sub(
- right_pos,
- left_pos));
- else if (hw_pos == HW_POINT_POSITION_LEFT)
- point->coeff = dal_fixed31_32_zero;
- else if (hw_pos == HW_POINT_POSITION_RIGHT)
- point->coeff = dal_fixed31_32_from_int(2);
- else {
- BREAK_TO_DEBUGGER();
- return false;
- }
-
- point->left_index = index_left;
- point->right_index = index_right;
- point->pos = hw_pos;
-
- ++i;
- }
-
- return true;
-}
-
-static inline bool build_oem_custom_gamma_mapping_coefficients(
- struct pixel_gamma_point *coeff128_oem,
- const struct hw_x_point *coordinates_x,
- const struct gamma_pixel *axis_x_256,
- uint32_t number_of_points,
- enum surface_pixel_format pixel_format)
-{
- int i;
-
- for (i = 0; i < 3; i++) {
- if (!build_custom_gamma_mapping_coefficients_worker(
- coeff128_oem, coordinates_x, axis_x_256, i,
- number_of_points, pixel_format))
- return false;
- }
- return true;
-}
-
-static struct fixed31_32 calculate_mapped_value(
- struct pwl_float_data *rgb,
- const struct pixel_gamma_point *coeff,
- enum channel_name channel,
- uint32_t max_index)
-{
- const struct gamma_point *point;
-
- struct fixed31_32 result;
-
- if (channel == CHANNEL_NAME_RED)
- point = &coeff->r;
- else if (channel == CHANNEL_NAME_GREEN)
- point = &coeff->g;
- else
- point = &coeff->b;
-
- if ((point->left_index < 0) || (point->left_index > max_index)) {
- BREAK_TO_DEBUGGER();
- return dal_fixed31_32_zero;
- }
-
- if ((point->right_index < 0) || (point->right_index > max_index)) {
- BREAK_TO_DEBUGGER();
- return dal_fixed31_32_zero;
- }
-
- if (point->pos == HW_POINT_POSITION_MIDDLE)
- if (channel == CHANNEL_NAME_RED)
- result = dal_fixed31_32_add(
- dal_fixed31_32_mul(
- point->coeff,
- dal_fixed31_32_sub(
- rgb[point->right_index].r,
- rgb[point->left_index].r)),
- rgb[point->left_index].r);
- else if (channel == CHANNEL_NAME_GREEN)
- result = dal_fixed31_32_add(
- dal_fixed31_32_mul(
- point->coeff,
- dal_fixed31_32_sub(
- rgb[point->right_index].g,
- rgb[point->left_index].g)),
- rgb[point->left_index].g);
- else
- result = dal_fixed31_32_add(
- dal_fixed31_32_mul(
- point->coeff,
- dal_fixed31_32_sub(
- rgb[point->right_index].b,
- rgb[point->left_index].b)),
- rgb[point->left_index].b);
- else if (point->pos == HW_POINT_POSITION_LEFT) {
- BREAK_TO_DEBUGGER();
- result = dal_fixed31_32_zero;
- } else {
- BREAK_TO_DEBUGGER();
- result = dal_fixed31_32_one;
- }
-
- return result;
-}
-
-static inline struct fixed31_32 calculate_oem_mapped_value(
- struct pwl_float_data *rgb_oem,
- const struct pixel_gamma_point *coeff,
- uint32_t index,
- enum channel_name channel,
- uint32_t max_index)
-{
- return calculate_mapped_value(
- rgb_oem,
- coeff + index,
- channel,
- max_index);
-}
-
-static void compute_pq(struct fixed31_32 in_x, struct fixed31_32 *out_y)
-{
- /* consts for PQ gamma formula. */
- const struct fixed31_32 m1 =
- dal_fixed31_32_from_fraction(159301758, 1000000000);
- const struct fixed31_32 m2 =
- dal_fixed31_32_from_fraction(7884375, 100000);
- const struct fixed31_32 c1 =
- dal_fixed31_32_from_fraction(8359375, 10000000);
- const struct fixed31_32 c2 =
- dal_fixed31_32_from_fraction(188515625, 10000000);
- const struct fixed31_32 c3 =
- dal_fixed31_32_from_fraction(186875, 10000);
-
- struct fixed31_32 l_pow_m1;
- struct fixed31_32 base;
-
- if (dal_fixed31_32_lt(in_x, dal_fixed31_32_zero))
- in_x = dal_fixed31_32_zero;
-
- l_pow_m1 = dal_fixed31_32_pow(in_x, m1);
- base = dal_fixed31_32_div(
- dal_fixed31_32_add(c1,
- (dal_fixed31_32_mul(c2, l_pow_m1))),
- dal_fixed31_32_add(dal_fixed31_32_one,
- (dal_fixed31_32_mul(c3, l_pow_m1))));
- *out_y = dal_fixed31_32_pow(base, m2);
-}
-
-static void build_regamma_curve_pq(struct pwl_float_data_ex *rgb_regamma,
- struct pwl_float_data *rgb_oem,
- struct pixel_gamma_point *coeff128_oem,
- const struct core_gamma *ramp,
- const struct core_surface *surface,
- uint32_t hw_points_num,
- const struct hw_x_point *coordinate_x,
- const struct gamma_pixel *axis_x,
- struct dividers dividers)
-{
- uint32_t i;
-
- struct pwl_float_data_ex *rgb = rgb_regamma;
- const struct hw_x_point *coord_x = coordinate_x;
- struct fixed31_32 x;
- struct fixed31_32 output;
- struct fixed31_32 scaling_factor =
- dal_fixed31_32_from_fraction(8, 1000);
-
- /* use coord_x to retrieve coordinates chosen base on given user curve
- * the x values are exponentially distributed and currently it is hard
- * coded, the user curve shape is ignored. Need to recalculate coord_x
- * based on input curve, translation from 256/1025 to 128 PWL points.
- */
- for (i = 0; i <= hw_points_num; i++) {
- /* Multiply 0.008 as regamma is 0-1 and FP16 input is 0-125.
- * FP 1.0 = 80nits
- */
- x = dal_fixed31_32_mul(coord_x->adjusted_x, scaling_factor);
-
- compute_pq(x, &output);
-
- /* should really not happen? */
- if (dal_fixed31_32_lt(output, dal_fixed31_32_zero))
- output = dal_fixed31_32_zero;
- else if (dal_fixed31_32_lt(dal_fixed31_32_one, output))
- output = dal_fixed31_32_one;
-
- rgb->r = output;
- rgb->g = output;
- rgb->b = output;
-
- ++coord_x;
- ++rgb;
- }
-}
-
-static void build_regamma_curve(struct pwl_float_data_ex *rgb_regamma,
- struct pwl_float_data *rgb_oem,
- struct pixel_gamma_point *coeff128_oem,
- const struct core_gamma *ramp,
- const struct core_surface *surface,
- uint32_t hw_points_num,
- const struct hw_x_point *coordinate_x,
- const struct gamma_pixel *axis_x,
- struct dividers dividers)
-{
- uint32_t i;
-
- struct gamma_coefficients coeff;
- struct pwl_float_data_ex *rgb = rgb_regamma;
- const struct hw_x_point *coord_x = coordinate_x;
-
- build_regamma_coefficients(&coeff);
-
- /* Use opp110->regamma.coordinates_x to retrieve
- * coordinates chosen base on given user curve (future task).
- * The x values are exponentially distributed and currently
- * it is hard-coded, the user curve shape is ignored.
- * The future task is to recalculate opp110-
- * regamma.coordinates_x based on input/user curve,
- * translation from 256/1025 to 128 pwl points.
- */
-
- i = 0;
-
- while (i != hw_points_num + 1) {
- rgb->r = translate_from_linear_space_ex(
- coord_x->adjusted_x, &coeff, 0);
- rgb->g = translate_from_linear_space_ex(
- coord_x->adjusted_x, &coeff, 1);
- rgb->b = translate_from_linear_space_ex(
- coord_x->adjusted_x, &coeff, 2);
-
- ++coord_x;
- ++rgb;
- ++i;
- }
-}
-
-static bool scale_gamma(struct pwl_float_data *pwl_rgb,
- const struct core_gamma *ramp,
- struct dividers dividers)
-{
- const struct dc_gamma *gamma = &ramp->public;
- const uint16_t max_driver = 0xFFFF;
- const uint16_t max_os = 0xFF00;
- uint16_t scaler = max_os;
- uint32_t i = 0;
- struct pwl_float_data *rgb = pwl_rgb;
- struct pwl_float_data *rgb_last = rgb + INPUT_LUT_ENTRIES - 1;
-
- do {
- if ((gamma->red[i] > max_os) ||
- (gamma->green[i] > max_os) ||
- (gamma->blue[i] > max_os)) {
- scaler = max_driver;
- break;
- }
- ++i;
- } while (i != INPUT_LUT_ENTRIES);
-
- i = 0;
-
- do {
- rgb->r = dal_fixed31_32_from_fraction(
- gamma->red[i], scaler);
- rgb->g = dal_fixed31_32_from_fraction(
- gamma->green[i], scaler);
- rgb->b = dal_fixed31_32_from_fraction(
- gamma->blue[i], scaler);
-
- ++rgb;
- ++i;
- } while (i != INPUT_LUT_ENTRIES);
-
- rgb->r = dal_fixed31_32_mul(rgb_last->r,
- dividers.divider1);
- rgb->g = dal_fixed31_32_mul(rgb_last->g,
- dividers.divider1);
- rgb->b = dal_fixed31_32_mul(rgb_last->b,
- dividers.divider1);
-
- ++rgb;
-
- rgb->r = dal_fixed31_32_mul(rgb_last->r,
- dividers.divider2);
- rgb->g = dal_fixed31_32_mul(rgb_last->g,
- dividers.divider2);
- rgb->b = dal_fixed31_32_mul(rgb_last->b,
- dividers.divider2);
-
- ++rgb;
-
- rgb->r = dal_fixed31_32_mul(rgb_last->r,
- dividers.divider3);
- rgb->g = dal_fixed31_32_mul(rgb_last->g,
- dividers.divider3);
- rgb->b = dal_fixed31_32_mul(rgb_last->b,
- dividers.divider3);
-
- return true;
-}
-
-static void build_evenly_distributed_points(
- struct gamma_pixel *points,
- uint32_t numberof_points,
- struct fixed31_32 max_value,
- struct dividers dividers)
-{
- struct gamma_pixel *p = points;
- struct gamma_pixel *p_last = p + numberof_points - 1;
-
- uint32_t i = 0;
-
- do {
- struct fixed31_32 value = dal_fixed31_32_div_int(
- dal_fixed31_32_mul_int(max_value, i),
- numberof_points - 1);
-
- p->r = value;
- p->g = value;
- p->b = value;
-
- ++p;
- ++i;
- } while (i != numberof_points);
-
- p->r = dal_fixed31_32_div(p_last->r, dividers.divider1);
- p->g = dal_fixed31_32_div(p_last->g, dividers.divider1);
- p->b = dal_fixed31_32_div(p_last->b, dividers.divider1);
-
- ++p;
-
- p->r = dal_fixed31_32_div(p_last->r, dividers.divider2);
- p->g = dal_fixed31_32_div(p_last->g, dividers.divider2);
- p->b = dal_fixed31_32_div(p_last->b, dividers.divider2);
-
- ++p;
-
- p->r = dal_fixed31_32_div(p_last->r, dividers.divider3);
- p->g = dal_fixed31_32_div(p_last->g, dividers.divider3);
- p->b = dal_fixed31_32_div(p_last->b, dividers.divider3);
-}
-
-static inline void copy_rgb_regamma_to_coordinates_x(
- struct hw_x_point *coordinates_x,
- uint32_t hw_points_num,
- const struct pwl_float_data_ex *rgb_ex)
-{
- struct hw_x_point *coords = coordinates_x;
- uint32_t i = 0;
- const struct pwl_float_data_ex *rgb_regamma = rgb_ex;
-
- while (i <= hw_points_num) {
- coords->regamma_y_red = rgb_regamma->r;
- coords->regamma_y_green = rgb_regamma->g;
- coords->regamma_y_blue = rgb_regamma->b;
-
- ++coords;
- ++rgb_regamma;
- ++i;
- }
-}
-
-static bool calculate_interpolated_hardware_curve(
- struct pwl_result_data *rgb,
- struct pixel_gamma_point *coeff128,
- struct pwl_float_data *rgb_user,
- const struct hw_x_point *coordinates_x,
- const struct gamma_pixel *axis_x_256,
- uint32_t number_of_points,
- enum surface_pixel_format pixel_format)
-{
-
- const struct pixel_gamma_point *coeff;
- struct pixel_gamma_point *coeff_128 = coeff128;
- uint32_t max_entries = 3 - 1;
- struct pwl_result_data *rgb_resulted = rgb;
-
- uint32_t i = 0;
-
- if (!build_oem_custom_gamma_mapping_coefficients(
- coeff_128, coordinates_x, axis_x_256,
- number_of_points,
- pixel_format))
- return false;
-
- coeff = coeff128;
- max_entries += INPUT_LUT_ENTRIES;
-
- /* TODO: float point case */
-
- while (i <= number_of_points) {
- rgb_resulted->red = calculate_mapped_value(
- rgb_user, coeff, CHANNEL_NAME_RED, max_entries);
- rgb_resulted->green = calculate_mapped_value(
- rgb_user, coeff, CHANNEL_NAME_GREEN, max_entries);
- rgb_resulted->blue = calculate_mapped_value(
- rgb_user, coeff, CHANNEL_NAME_BLUE, max_entries);
-
- ++coeff;
- ++rgb_resulted;
- ++i;
- }
-
- return true;
-}
-
-static bool map_regamma_hw_to_x_user(
- struct pixel_gamma_point *coeff128,
- struct pwl_float_data *rgb_oem,
- struct pwl_result_data *rgb_resulted,
- struct pwl_float_data *rgb_user,
- struct hw_x_point *coords_x,
- const struct gamma_pixel *axis_x,
- const struct dc_gamma *gamma,
- const struct pwl_float_data_ex *rgb_regamma,
- struct dividers dividers,
- uint32_t hw_points_num,
- const struct core_surface *surface)
-{
- /* setup to spare calculated ideal regamma values */
-
- struct pixel_gamma_point *coeff = coeff128;
-
- struct hw_x_point *coords = coords_x;
-
- copy_rgb_regamma_to_coordinates_x(coords, hw_points_num, rgb_regamma);
-
- return calculate_interpolated_hardware_curve(
- rgb_resulted, coeff, rgb_user, coords, axis_x,
- hw_points_num, surface->public.format);
-}
-
-static void build_new_custom_resulted_curve(
- struct pwl_result_data *rgb_resulted,
- uint32_t hw_points_num)
-{
- struct pwl_result_data *rgb = rgb_resulted;
- struct pwl_result_data *rgb_plus_1 = rgb + 1;
-
- uint32_t i;
-
- i = 0;
-
- while (i != hw_points_num + 1) {
- rgb->red = dal_fixed31_32_clamp(
- rgb->red, dal_fixed31_32_zero,
- dal_fixed31_32_one);
- rgb->green = dal_fixed31_32_clamp(
- rgb->green, dal_fixed31_32_zero,
- dal_fixed31_32_one);
- rgb->blue = dal_fixed31_32_clamp(
- rgb->blue, dal_fixed31_32_zero,
- dal_fixed31_32_one);
-
- ++rgb;
- ++i;
- }
-
- rgb = rgb_resulted;
-
- i = 1;
-
- while (i != hw_points_num + 1) {
- if (dal_fixed31_32_lt(rgb_plus_1->red, rgb->red))
- rgb_plus_1->red = rgb->red;
- if (dal_fixed31_32_lt(rgb_plus_1->green, rgb->green))
- rgb_plus_1->green = rgb->green;
- if (dal_fixed31_32_lt(rgb_plus_1->blue, rgb->blue))
- rgb_plus_1->blue = rgb->blue;
-
- rgb->delta_red = dal_fixed31_32_sub(
- rgb_plus_1->red,
- rgb->red);
- rgb->delta_green = dal_fixed31_32_sub(
- rgb_plus_1->green,
- rgb->green);
- rgb->delta_blue = dal_fixed31_32_sub(
- rgb_plus_1->blue,
- rgb->blue);
-
- ++rgb_plus_1;
- ++rgb;
- ++i;
- }
-}
-
-static void rebuild_curve_configuration_magic(
- struct curve_points *arr_points,
- struct pwl_result_data *rgb_resulted,
- const struct hw_x_point *coordinates_x,
- uint32_t hw_points_num,
- enum dc_transfer_func_predefined tf)
-{
- struct fixed31_32 y_r;
- struct fixed31_32 y_g;
- struct fixed31_32 y_b;
-
- struct fixed31_32 y1_min;
- struct fixed31_32 y3_max;
-
- y_r = rgb_resulted[0].red;
- y_g = rgb_resulted[0].green;
- y_b = rgb_resulted[0].blue;
-
- y1_min = dal_fixed31_32_min(y_r, dal_fixed31_32_min(y_g, y_b));
-
- arr_points[0].x = coordinates_x[0].adjusted_x;
- arr_points[0].y = y1_min;
- arr_points[0].slope = dal_fixed31_32_div(
- arr_points[0].y,
- arr_points[0].x);
-
- /* this should be cleaned up as it's confusing my understanding (KK) is
- * that REGAMMA_CNTLA_EXP_REGION_END is the X value for the region end
- * REGAMMA_CNTLA_EXP_REGION_END_BASE is Y value for the above X
- * REGAMMA_CNTLA_EXP_REGION_END_SLOPE is the slope beyond (X,Y) above
- * currently when programming REGION_END = m_arrPoints[1].x,
- * REGION_END_BASE = m_arrPoints[1].y, REGION_END_SLOPE=1
- * we don't use m_arrPoints[2] at all after this function,
- * and its purpose isn't clear to me
- */
- arr_points[1].x = coordinates_x[hw_points_num].adjusted_x;
- arr_points[2].x = coordinates_x[hw_points_num].adjusted_x;
-
- y_r = rgb_resulted[hw_points_num].red;
- y_g = rgb_resulted[hw_points_num].green;
- y_b = rgb_resulted[hw_points_num].blue;
-
- /* see comment above, m_arrPoints[1].y should be the Y value for the
- * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1)
- */
- y3_max = dal_fixed31_32_max(y_r, dal_fixed31_32_max(y_g, y_b));
-
- arr_points[1].y = y3_max;
- arr_points[2].y = y3_max;
-
- arr_points[2].slope = dal_fixed31_32_zero;
-
- /* for PQ, we want to have a straight line from last HW X point, and the
- * slope to be such that we hit 1.0 at 10000 nits.
- */
- if (tf == TRANSFER_FUNCTION_PQ) {
- const struct fixed31_32 end_value =
- dal_fixed31_32_from_int(125);
-
- arr_points[2].slope = dal_fixed31_32_div(
- dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y),
- dal_fixed31_32_sub(end_value, arr_points[1].x));
- }
-}
-
-static bool convert_to_custom_float_format(
- struct fixed31_32 value,
- const struct custom_float_format *format,
- uint32_t *result)
-{
- uint32_t mantissa;
- uint32_t exponenta;
- bool negative;
-
- return build_custom_float(
- value, format, &negative, &mantissa, &exponenta) &&
- setup_custom_float(
- format, negative, mantissa, exponenta, result);
-}
-
-static bool convert_to_custom_float(
- struct pwl_result_data *rgb_resulted,
- struct curve_points *arr_points,
- uint32_t hw_points_num)
-{
- struct custom_float_format fmt;
-
- struct pwl_result_data *rgb = rgb_resulted;
-
- uint32_t i = 0;
-
- fmt.exponenta_bits = 6;
- fmt.mantissa_bits = 12;
- fmt.sign = true;
-
- if (!convert_to_custom_float_format(
- arr_points[0].x,
- &fmt,
- &arr_points[0].custom_float_x)) {
- BREAK_TO_DEBUGGER();
- return false;
- }
-
- if (!convert_to_custom_float_format(
- arr_points[0].offset,
- &fmt,
- &arr_points[0].custom_float_offset)) {
- BREAK_TO_DEBUGGER();
- return false;
- }
-
- if (!convert_to_custom_float_format(
- arr_points[0].slope,
- &fmt,
- &arr_points[0].custom_float_slope)) {
- BREAK_TO_DEBUGGER();
- return false;
- }
-
- fmt.mantissa_bits = 10;
- fmt.sign = false;
-
- if (!convert_to_custom_float_format(
- arr_points[1].x,
- &fmt,
- &arr_points[1].custom_float_x)) {
- BREAK_TO_DEBUGGER();
- return false;
- }
-
- if (!convert_to_custom_float_format(
- arr_points[1].y,
- &fmt,
- &arr_points[1].custom_float_y)) {
- BREAK_TO_DEBUGGER();
- return false;
- }
-
- if (!convert_to_custom_float_format(
- arr_points[2].slope,
- &fmt,
- &arr_points[2].custom_float_slope)) {
- BREAK_TO_DEBUGGER();
- return false;
- }
-
- fmt.mantissa_bits = 12;
- fmt.sign = true;
-
- while (i != hw_points_num) {
- if (!convert_to_custom_float_format(
- rgb->red,
- &fmt,
- &rgb->red_reg)) {
- BREAK_TO_DEBUGGER();
- return false;
- }
-
- if (!convert_to_custom_float_format(
- rgb->green,
- &fmt,
- &rgb->green_reg)) {
- BREAK_TO_DEBUGGER();
- return false;
- }
-
- if (!convert_to_custom_float_format(
- rgb->blue,
- &fmt,
- &rgb->blue_reg)) {
- BREAK_TO_DEBUGGER();
- return false;
- }
-
- if (!convert_to_custom_float_format(
- rgb->delta_red,
- &fmt,
- &rgb->delta_red_reg)) {
- BREAK_TO_DEBUGGER();
- return false;
- }
-
- if (!convert_to_custom_float_format(
- rgb->delta_green,
- &fmt,
- &rgb->delta_green_reg)) {
- BREAK_TO_DEBUGGER();
- return false;
- }
-
- if (!convert_to_custom_float_format(
- rgb->delta_blue,
- &fmt,
- &rgb->delta_blue_reg)) {
- BREAK_TO_DEBUGGER();
- return false;
- }
-
- ++rgb;
- ++i;
- }
-
- return true;
-}
-
-bool calculate_regamma_params(struct pwl_params *params,
- const struct core_gamma *ramp,
- const struct core_surface *surface,
- const struct core_stream *stream)
-{
- struct gamma_curve *arr_curve_points = params->arr_curve_points;
- struct curve_points *arr_points = params->arr_points;
- struct pwl_result_data *rgb_resulted = params->rgb_resulted;
- struct dividers dividers;
-
- struct hw_x_point *coordinates_x = NULL;
- struct pwl_float_data *rgb_user = NULL ;
- struct pwl_float_data_ex *rgb_regamma = NULL;
- struct pwl_float_data *rgb_oem = NULL;
- struct gamma_pixel *axix_x_256 = NULL;
- struct pixel_gamma_point *coeff128_oem = NULL;
- struct pixel_gamma_point *coeff128 = NULL;
-
- enum dc_transfer_func_predefined tf = TRANSFER_FUNCTION_SRGB;
-
- bool ret = false;
-
- coordinates_x = dm_alloc(sizeof(*coordinates_x)*(256 + 3));
- if (!coordinates_x)
- goto coordinates_x_alloc_fail;
- rgb_user = dm_alloc(sizeof(*rgb_user) * (TRANSFER_FUNC_POINTS + 3));
- if (!rgb_user)
- goto rgb_user_alloc_fail;
- rgb_regamma = dm_alloc(sizeof(*rgb_regamma) * (256 + 3));
- if (!rgb_regamma)
- goto rgb_regamma_alloc_fail;
- rgb_oem = dm_alloc(sizeof(*rgb_oem) * (TRANSFER_FUNC_POINTS + 3));
- if (!rgb_oem)
- goto rgb_oem_alloc_fail;
- axix_x_256 = dm_alloc(sizeof(*axix_x_256) * (256 + 3));
- if (!axix_x_256)
- goto axix_x_256_alloc_fail;
- coeff128_oem = dm_alloc(sizeof(*coeff128_oem) * (256 + 3));
- if (!coeff128_oem)
- goto coeff128_oem_alloc_fail;
- coeff128 = dm_alloc(sizeof(*coeff128) * (256 + 3));
- if (!coeff128)
- goto coeff128_alloc_fail;
-
- dividers.divider1 = dal_fixed31_32_from_fraction(3, 2);
- dividers.divider2 = dal_fixed31_32_from_int(2);
- dividers.divider3 = dal_fixed31_32_from_fraction(5, 2);
-
- if (stream->public.out_transfer_func)
- tf = stream->public.out_transfer_func->tf;
-
- build_evenly_distributed_points(
- axix_x_256,
- 256,
- dal_fixed31_32_one,
- dividers);
-
- scale_gamma(rgb_user, ramp, dividers);
-
- if (tf == TRANSFER_FUNCTION_PQ) {
- setup_distribution_points_pq(arr_curve_points, arr_points,
- ¶ms->hw_points_num, coordinates_x,
- surface->public.format);
- build_regamma_curve_pq(rgb_regamma, rgb_oem, coeff128_oem,
- ramp, surface, params->hw_points_num,
- coordinates_x, axix_x_256, dividers);
- } else {
- setup_distribution_points(arr_curve_points, arr_points,
- ¶ms->hw_points_num, coordinates_x);
- build_regamma_curve(rgb_regamma, rgb_oem, coeff128_oem,
- ramp, surface, params->hw_points_num,
- coordinates_x, axix_x_256, dividers);
- }
-
- map_regamma_hw_to_x_user(coeff128, rgb_oem, rgb_resulted, rgb_user,
- coordinates_x, axix_x_256, &ramp->public, rgb_regamma,
- dividers, params->hw_points_num, surface);
-
- build_new_custom_resulted_curve(rgb_resulted, params->hw_points_num);
-
- rebuild_curve_configuration_magic(
- arr_points,
- rgb_resulted,
- coordinates_x,
- params->hw_points_num,
- tf);
-
- convert_to_custom_float(rgb_resulted, arr_points,
- params->hw_points_num);
-
- ret = true;
-
- dm_free(coeff128);
-coeff128_alloc_fail:
- dm_free(coeff128_oem);
-coeff128_oem_alloc_fail:
- dm_free(axix_x_256);
-axix_x_256_alloc_fail:
- dm_free(rgb_oem);
-rgb_oem_alloc_fail:
- dm_free(rgb_regamma);
-rgb_regamma_alloc_fail:
- dm_free(rgb_user);
-rgb_user_alloc_fail:
- dm_free(coordinates_x);
-coordinates_x_alloc_fail:
- return ret;
-
-}
-
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 7d4299b9ee1f..948f82a56472 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1519,23 +1519,23 @@ void dc_update_surfaces_for_stream(struct dc *dc, struct dc_surface_update *upda
if (dc->debug.disable_color_module)
continue; /* skip below color updates */
- if (updates[i].hdr_static_metadata) {
- resource_build_info_frame(pipe_ctx);
- core_dc->hwss.update_info_frame(pipe_ctx);
- }
if (is_new_pipe_surface[j] ||
updates[i].in_transfer_func)
core_dc->hwss.set_input_transfer_func(
pipe_ctx, pipe_ctx->surface);
if (is_new_pipe_surface[j] ||
- updates[i].gamma ||
updates[i].out_transfer_func)
core_dc->hwss.set_output_transfer_func(
pipe_ctx,
pipe_ctx->surface,
pipe_ctx->stream);
+ if (updates[i].hdr_static_metadata) {
+ resource_build_info_frame(pipe_ctx);
+ core_dc->hwss.update_info_frame(pipe_ctx);
+ }
+
}
if (apply_ctx) {
core_dc->hwss.apply_ctx_for_surface(core_dc, surface, context);
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index b814e7b76bbc..f53b41339951 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -213,11 +213,14 @@ enum dc_transfer_func_type {
};
struct dc_transfer_func_distributed_points {
- uint16_t red[TRANSFER_FUNC_POINTS];
- uint16_t green[TRANSFER_FUNC_POINTS];
- uint16_t blue[TRANSFER_FUNC_POINTS];
+ struct fixed31_32 red[TRANSFER_FUNC_POINTS];
+ struct fixed31_32 green[TRANSFER_FUNC_POINTS];
+ struct fixed31_32 blue[TRANSFER_FUNC_POINTS];
+
uint16_t end_exponent;
- uint16_t x_point_at_y1;
+ uint16_t x_point_at_y1_red;
+ uint16_t x_point_at_y1_green;
+ uint16_t x_point_at_y1_blue;
};
enum dc_transfer_func_predefined {
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 415b12accd2c..6e70cf7b99ef 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -42,7 +42,6 @@
#include "stream_encoder.h"
#include "link_encoder.h"
#include "clock_source.h"
-#include "gamma_calcs.h"
#include "audio.h"
#include "dce/dce_hwseq.h"
@@ -286,6 +285,436 @@ static bool dce110_set_input_transfer_func(
return result;
}
+static bool build_custom_float(
+ struct fixed31_32 value,
+ const struct custom_float_format *format,
+ bool *negative,
+ uint32_t *mantissa,
+ uint32_t *exponenta)
+{
+ uint32_t exp_offset = (1 << (format->exponenta_bits - 1)) - 1;
+
+ const struct fixed31_32 mantissa_constant_plus_max_fraction =
+ dal_fixed31_32_from_fraction(
+ (1LL << (format->mantissa_bits + 1)) - 1,
+ 1LL << format->mantissa_bits);
+
+ struct fixed31_32 mantiss;
+
+ if (dal_fixed31_32_eq(
+ value,
+ dal_fixed31_32_zero)) {
+ *negative = false;
+ *mantissa = 0;
+ *exponenta = 0;
+ return true;
+ }
+
+ if (dal_fixed31_32_lt(
+ value,
+ dal_fixed31_32_zero)) {
+ *negative = format->sign;
+ value = dal_fixed31_32_neg(value);
+ } else {
+ *negative = false;
+ }
+
+ if (dal_fixed31_32_lt(
+ value,
+ dal_fixed31_32_one)) {
+ uint32_t i = 1;
+
+ do {
+ value = dal_fixed31_32_shl(value, 1);
+ ++i;
+ } while (dal_fixed31_32_lt(
+ value,
+ dal_fixed31_32_one));
+
+ --i;
+
+ if (exp_offset <= i) {
+ *mantissa = 0;
+ *exponenta = 0;
+ return true;
+ }
+
+ *exponenta = exp_offset - i;
+ } else if (dal_fixed31_32_le(
+ mantissa_constant_plus_max_fraction,
+ value)) {
+ uint32_t i = 1;
+
+ do {
+ value = dal_fixed31_32_shr(value, 1);
+ ++i;
+ } while (dal_fixed31_32_lt(
+ mantissa_constant_plus_max_fraction,
+ value));
+
+ *exponenta = exp_offset + i - 1;
+ } else {
+ *exponenta = exp_offset;
+ }
+
+ mantiss = dal_fixed31_32_sub(
+ value,
+ dal_fixed31_32_one);
+
+ if (dal_fixed31_32_lt(
+ mantiss,
+ dal_fixed31_32_zero) ||
+ dal_fixed31_32_lt(
+ dal_fixed31_32_one,
+ mantiss))
+ mantiss = dal_fixed31_32_zero;
+ else
+ mantiss = dal_fixed31_32_shl(
+ mantiss,
+ format->mantissa_bits);
+
+ *mantissa = dal_fixed31_32_floor(mantiss);
+
+ return true;
+}
+
+static bool setup_custom_float(
+ const struct custom_float_format *format,
+ bool negative,
+ uint32_t mantissa,
+ uint32_t exponenta,
+ uint32_t *result)
+{
+ uint32_t i = 0;
+ uint32_t j = 0;
+
+ uint32_t value = 0;
+
+ /* verification code:
+ * once calculation is ok we can remove it
+ */
+
+ const uint32_t mantissa_mask =
+ (1 << (format->mantissa_bits + 1)) - 1;
+
+ const uint32_t exponenta_mask =
+ (1 << (format->exponenta_bits + 1)) - 1;
+
+ if (mantissa & ~mantissa_mask) {
+ BREAK_TO_DEBUGGER();
+ mantissa = mantissa_mask;
+ }
+
+ if (exponenta & ~exponenta_mask) {
+ BREAK_TO_DEBUGGER();
+ exponenta = exponenta_mask;
+ }
+
+ /* end of verification code */
+
+ while (i < format->mantissa_bits) {
+ uint32_t mask = 1 << i;
+
+ if (mantissa & mask)
+ value |= mask;
+
+ ++i;
+ }
+
+ while (j < format->exponenta_bits) {
+ uint32_t mask = 1 << j;
+
+ if (exponenta & mask)
+ value |= mask << i;
+
+ ++j;
+ }
+
+ if (negative && format->sign)
+ value |= 1 << (i + j);
+
+ *result = value;
+
+ return true;
+}
+
+static bool convert_to_custom_float_format(
+ struct fixed31_32 value,
+ const struct custom_float_format *format,
+ uint32_t *result)
+{
+ uint32_t mantissa;
+ uint32_t exponenta;
+ bool negative;
+
+ return build_custom_float(
+ value, format, &negative, &mantissa, &exponenta) &&
+ setup_custom_float(
+ format, negative, mantissa, exponenta, result);
+}
+
+static bool convert_to_custom_float(
+ struct pwl_result_data *rgb_resulted,
+ struct curve_points *arr_points,
+ uint32_t hw_points_num)
+{
+ struct custom_float_format fmt;
+
+ struct pwl_result_data *rgb = rgb_resulted;
+
+ uint32_t i = 0;
+
+ fmt.exponenta_bits = 6;
+ fmt.mantissa_bits = 12;
+ fmt.sign = true;
+
+ if (!convert_to_custom_float_format(
+ arr_points[0].x,
+ &fmt,
+ &arr_points[0].custom_float_x)) {
+ BREAK_TO_DEBUGGER();
+ return false;
+ }
+
+ if (!convert_to_custom_float_format(
+ arr_points[0].offset,
+ &fmt,
+ &arr_points[0].custom_float_offset)) {
+ BREAK_TO_DEBUGGER();
+ return false;
+ }
+
+ if (!convert_to_custom_float_format(
+ arr_points[0].slope,
+ &fmt,
+ &arr_points[0].custom_float_slope)) {
+ BREAK_TO_DEBUGGER();
+ return false;
+ }
+
+ fmt.mantissa_bits = 10;
+ fmt.sign = false;
+
+ if (!convert_to_custom_float_format(
+ arr_points[1].x,
+ &fmt,
+ &arr_points[1].custom_float_x)) {
+ BREAK_TO_DEBUGGER();
+ return false;
+ }
+
+ if (!convert_to_custom_float_format(
+ arr_points[1].y,
+ &fmt,
+ &arr_points[1].custom_float_y)) {
+ BREAK_TO_DEBUGGER();
+ return false;
+ }
+
+ if (!convert_to_custom_float_format(
+ arr_points[2].slope,
+ &fmt,
+ &arr_points[2].custom_float_slope)) {
+ BREAK_TO_DEBUGGER();
+ return false;
+ }
+
+ fmt.mantissa_bits = 12;
+ fmt.sign = true;
+
+ while (i != hw_points_num) {
+ if (!convert_to_custom_float_format(
+ rgb->red,
+ &fmt,
+ &rgb->red_reg)) {
+ BREAK_TO_DEBUGGER();
+ return false;
+ }
+
+ if (!convert_to_custom_float_format(
+ rgb->green,
+ &fmt,
+ &rgb->green_reg)) {
+ BREAK_TO_DEBUGGER();
+ return false;
+ }
+
+ if (!convert_to_custom_float_format(
+ rgb->blue,
+ &fmt,
+ &rgb->blue_reg)) {
+ BREAK_TO_DEBUGGER();
+ return false;
+ }
+
+ if (!convert_to_custom_float_format(
+ rgb->delta_red,
+ &fmt,
+ &rgb->delta_red_reg)) {
+ BREAK_TO_DEBUGGER();
+ return false;
+ }
+
+ if (!convert_to_custom_float_format(
+ rgb->delta_green,
+ &fmt,
+ &rgb->delta_green_reg)) {
+ BREAK_TO_DEBUGGER();
+ return false;
+ }
+
+ if (!convert_to_custom_float_format(
+ rgb->delta_blue,
+ &fmt,
+ &rgb->delta_blue_reg)) {
+ BREAK_TO_DEBUGGER();
+ return false;
+ }
+
+ ++rgb;
+ ++i;
+ }
+
+ return true;
+}
+
+static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func
+ *output_tf, struct pwl_params *regamma_params)
+{
+ if (output_tf == NULL || regamma_params == NULL)
+ return false;
+
+ struct gamma_curve *arr_curve_points = regamma_params->arr_curve_points;
+ struct curve_points *arr_points = regamma_params->arr_points;
+ struct pwl_result_data *rgb_resulted = regamma_params->rgb_resulted;
+ struct fixed31_32 y_r;
+ struct fixed31_32 y_g;
+ struct fixed31_32 y_b;
+ struct fixed31_32 y1_min;
+ struct fixed31_32 y3_max;
+
+ int32_t segment_start, segment_end;
+ uint32_t hw_points, start_index;
+ uint32_t i, j;
+
+ memset(regamma_params, 0, sizeof(struct pwl_params));
+
+ if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
+ /* 16 segments x 16 points
+ * segments are from 2^-11 to 2^5
+ */
+ segment_start = -11;
+ segment_end = 5;
+
+ } else {
+ /* 10 segments x 16 points
+ * segment is from 2^-10 to 2^0
+ */
+ segment_start = -10;
+ segment_end = 0;
+ }
+
+ hw_points = (segment_end - segment_start) * 16;
+ j = 0;
+ /* (segment + 25) * 32, every 2nd point */
+ start_index = (segment_start + 25) * 32;
+ for (i = start_index; i <= 1025; i += 2) {
+ if (j > hw_points)
+ break;
+ rgb_resulted[j].red = output_tf->tf_pts.red[i];
+ rgb_resulted[j].green = output_tf->tf_pts.green[i];
+ rgb_resulted[j].blue = output_tf->tf_pts.blue[i];
+ j++;
+ }
+
+ arr_points[0].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
+ dal_fixed31_32_from_int(segment_start));
+ arr_points[1].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
+ dal_fixed31_32_from_int(segment_end));
+ arr_points[2].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
+ dal_fixed31_32_from_int(segment_end));
+
+ y_r = rgb_resulted[0].red;
+ y_g = rgb_resulted[0].green;
+ y_b = rgb_resulted[0].blue;
+
+ y1_min = dal_fixed31_32_min(y_r, dal_fixed31_32_min(y_g, y_b));
+
+ arr_points[0].y = y1_min;
+ arr_points[0].slope = dal_fixed31_32_div(
+ arr_points[0].y,
+ arr_points[0].x);
+
+ y_r = rgb_resulted[hw_points - 1].red;
+ y_g = rgb_resulted[hw_points - 1].green;
+ y_b = rgb_resulted[hw_points - 1].blue;
+
+ /* see comment above, m_arrPoints[1].y should be the Y value for the
+ * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1)
+ */
+ y3_max = dal_fixed31_32_max(y_r, dal_fixed31_32_max(y_g, y_b));
+
+ arr_points[1].y = y3_max;
+ arr_points[2].y = y3_max;
+
+ arr_points[1].slope = dal_fixed31_32_zero;
+ arr_points[2].slope = dal_fixed31_32_zero;
+
+ if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
+ /* for PQ, we want to have a straight line from last HW X point,
+ * and the slope to be such that we hit 1.0 at 10000 nits.
+ */
+ const struct fixed31_32 end_value =
+ dal_fixed31_32_from_int(125);
+
+ arr_points[1].slope = dal_fixed31_32_div(
+ dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y),
+ dal_fixed31_32_sub(end_value, arr_points[1].x));
+ arr_points[2].slope = dal_fixed31_32_div(
+ dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y),
+ dal_fixed31_32_sub(end_value, arr_points[1].x));
+ }
+
+ regamma_params->hw_points_num = hw_points;
+
+ for (i = 0; i < segment_end - segment_start; i++) {
+ regamma_params->arr_curve_points[i].offset = i * 16;
+ regamma_params->arr_curve_points[i].segments_num = 4;
+ }
+
+ struct pwl_result_data *rgb = rgb_resulted;
+ struct pwl_result_data *rgb_plus_1 = rgb_resulted + 1;
+
+ i = 1;
+
+ while (i != hw_points + 1) {
+ if (dal_fixed31_32_lt(rgb_plus_1->red, rgb->red))
+ rgb_plus_1->red = rgb->red;
+ if (dal_fixed31_32_lt(rgb_plus_1->green, rgb->green))
+ rgb_plus_1->green = rgb->green;
+ if (dal_fixed31_32_lt(rgb_plus_1->blue, rgb->blue))
+ rgb_plus_1->blue = rgb->blue;
+
+ rgb->delta_red = dal_fixed31_32_sub(
+ rgb_plus_1->red,
+ rgb->red);
+ rgb->delta_green = dal_fixed31_32_sub(
+ rgb_plus_1->green,
+ rgb->green);
+ rgb->delta_blue = dal_fixed31_32_sub(
+ rgb_plus_1->blue,
+ rgb->blue);
+
+ ++rgb_plus_1;
+ ++rgb;
+ ++i;
+ }
+
+ convert_to_custom_float(rgb_resulted, arr_points, hw_points);
+
+ return true;
+}
+
static bool dce110_set_output_transfer_func(
struct pipe_ctx *pipe_ctx,
const struct core_surface *surface, /* Surface - To be removed */
@@ -308,10 +737,13 @@ static bool dce110_set_output_transfer_func(
opp->funcs->opp_power_on_regamma_lut(opp, true);
if (stream->public.out_transfer_func &&
- stream->public.out_transfer_func->type == TF_TYPE_PREDEFINED &&
- stream->public.out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) {
+ stream->public.out_transfer_func->type ==
+ TF_TYPE_PREDEFINED &&
+ stream->public.out_transfer_func->tf ==
+ TRANSFER_FUNCTION_SRGB) {
opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_SRGB);
- } else if (ramp && calculate_regamma_params(regamma_params, ramp, surface, stream)) {
+ } else if (dce110_translate_regamma_to_hw_format(
+ stream->public.out_transfer_func, regamma_params)) {
opp->funcs->opp_program_regamma_pwl(opp, regamma_params);
opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_USER);
} else {
diff --git a/drivers/gpu/drm/amd/display/dc/inc/gamma_calcs.h b/drivers/gpu/drm/amd/display/dc/inc/gamma_calcs.h
deleted file mode 100644
index 0712268856c2..000000000000
--- a/drivers/gpu/drm/amd/display/dc/inc/gamma_calcs.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * gamma_calcs.h
- *
- * Created on: Feb 9, 2016
- * Author: yonsun
- */
-
-#ifndef DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_GAMMA_CALCS_H_
-#define DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_GAMMA_CALCS_H_
-
-#include "opp.h"
-#include "core_types.h"
-#include "dc.h"
-
-bool calculate_regamma_params(struct pwl_params *params,
- const struct core_gamma *ramp,
- const struct core_surface *surface,
- const struct core_stream *stream);
-
-#endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_GAMMA_CALCS_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
index a1f31a4410a3..bef5e2cacbe3 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
@@ -138,9 +138,7 @@ struct custom_float_value {
struct hw_x_point {
uint32_t custom_float_x;
- uint32_t custom_float_x_adjusted;
struct fixed31_32 x;
- struct fixed31_32 adjusted_x;
struct fixed31_32 regamma_y_red;
struct fixed31_32 regamma_y_green;
struct fixed31_32 regamma_y_blue;
diff --git a/drivers/gpu/drm/amd/display/include/fixed31_32.h b/drivers/gpu/drm/amd/display/include/fixed31_32.h
index c28de167250f..5a4364dfd2f7 100644
--- a/drivers/gpu/drm/amd/display/include/fixed31_32.h
+++ b/drivers/gpu/drm/amd/display/include/fixed31_32.h
@@ -192,6 +192,14 @@ struct fixed31_32 dal_fixed31_32_add(
/*
* @brief
+ * result = arg1 + arg2
+ */
+struct fixed31_32 dal_fixed31_32_add_int(
+ struct fixed31_32 arg1,
+ int32_t arg2);
+
+/*
+ * @brief
* result = arg1 - arg2
*/
struct fixed31_32 dal_fixed31_32_sub_int(
--
2.9.3
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 03/25] drm/amd/display: Disable Modules at Runtime
[not found] ` <20170123143613.15441-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
2017-01-23 14:35 ` [PATCH 01/25] drm/amd/display: Null check clock source Harry Wentland
2017-01-23 14:35 ` [PATCH 02/25] drm/amd/display: Output Transfer Function Regamma Refactor Harry Wentland
@ 2017-01-23 14:35 ` Harry Wentland
2017-01-23 14:35 ` [PATCH 04/25] drm/amd/display: Fixing some fallout from dc_target removal Harry Wentland
` (21 subsequent siblings)
24 siblings, 0 replies; 27+ messages in thread
From: Harry Wentland @ 2017-01-23 14:35 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Anthony Koo
From: Anthony Koo <Anthony.Koo@amd.com>
Add NULL check in modules
Change-Id: I3e668c93b16795c539ac790638694c2b4c4dab28
Signed-off-by: Anthony Koo <anthony.koo@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
.../drm/amd/display/modules/freesync/freesync.c | 94 +++++++++++++++-------
.../gpu/drm/amd/display/modules/inc/mod_freesync.h | 7 --
2 files changed, 65 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index 6f4d169f4e4e..e0703c588e47 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -205,11 +205,16 @@ static unsigned int map_index_from_stream(struct core_freesync *core_freesync,
bool mod_freesync_add_stream(struct mod_freesync *mod_freesync,
const struct dc_stream *stream, struct mod_freesync_caps *caps)
{
- struct core_freesync *core_freesync =
- MOD_FREESYNC_TO_CORE(mod_freesync);
- struct core_stream *core_stream =
- DC_STREAM_TO_CORE(stream);
- struct core_dc *core_dc = DC_TO_CORE(core_freesync->dc);
+ struct core_stream *core_stream = NULL;
+ struct core_dc *core_dc = NULL;
+ struct core_freesync *core_freesync = NULL;
+
+ if (mod_freesync == NULL)
+ return false;
+
+ core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
+ core_stream = DC_STREAM_TO_CORE(stream);
+ core_dc = DC_TO_CORE(core_freesync->dc);
int persistent_freesync_enable = 0;
struct persistent_data_flag flag;
@@ -270,11 +275,16 @@ bool mod_freesync_add_stream(struct mod_freesync *mod_freesync,
bool mod_freesync_remove_stream(struct mod_freesync *mod_freesync,
const struct dc_stream *stream)
{
- struct core_freesync *core_freesync =
- MOD_FREESYNC_TO_CORE(mod_freesync);
-
int i = 0;
- unsigned int index = map_index_from_stream(core_freesync, stream);
+ struct core_freesync *core_freesync = NULL;
+ unsigned int index = 0;
+
+ if (mod_freesync == NULL)
+ return false;
+
+ core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
+ index = map_index_from_stream(core_freesync, stream);
+
dc_stream_release(core_freesync->map[index].stream);
core_freesync->map[index].stream = NULL;
/* To remove this entity, shift everything after down */
@@ -621,11 +631,14 @@ static void set_static_ramp_variables(struct core_freesync *core_freesync,
void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync,
const struct dc_stream **streams, int num_streams)
{
- struct core_freesync *core_freesync =
- MOD_FREESYNC_TO_CORE(mod_freesync);
-
unsigned int index, v_total = 0;
struct freesync_state *state;
+ struct core_freesync *core_freesync = NULL;
+
+ if (mod_freesync == NULL)
+ return;
+
+ core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
if (core_freesync->num_entities == 0)
return;
@@ -691,11 +704,15 @@ void mod_freesync_update_state(struct mod_freesync *mod_freesync,
const struct dc_stream **streams, int num_streams,
struct mod_freesync_params *freesync_params)
{
- struct core_freesync *core_freesync =
- MOD_FREESYNC_TO_CORE(mod_freesync);
bool freesync_program_required = false;
unsigned int stream_index;
struct freesync_state *state;
+ struct core_freesync *core_freesync = NULL;
+
+ if (mod_freesync == NULL)
+ return;
+
+ core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
if (core_freesync->num_entities == 0)
return;
@@ -762,10 +779,14 @@ bool mod_freesync_get_state(struct mod_freesync *mod_freesync,
const struct dc_stream *stream,
struct mod_freesync_params *freesync_params)
{
- struct core_freesync *core_freesync =
- MOD_FREESYNC_TO_CORE(mod_freesync);
+ unsigned int index = NULL;
+ struct core_freesync *core_freesync = NULL;
- unsigned int index = map_index_from_stream(core_freesync, stream);
+ if (mod_freesync == NULL)
+ return false;
+
+ core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
+ index = map_index_from_stream(core_freesync, stream);
if (core_freesync->map[index].state.fullscreen) {
freesync_params->state = FREESYNC_STATE_FULLSCREEN;
@@ -794,13 +815,17 @@ bool mod_freesync_set_user_enable(struct mod_freesync *mod_freesync,
const struct dc_stream **streams, int num_streams,
struct mod_freesync_user_enable *user_enable)
{
- struct core_freesync *core_freesync =
- MOD_FREESYNC_TO_CORE(mod_freesync);
- struct core_dc *core_dc = DC_TO_CORE(core_freesync->dc);
-
unsigned int stream_index, map_index;
int persistent_data = 0;
struct persistent_data_flag flag;
+ struct core_dc *core_dc = NULL;
+ struct core_freesync *core_freesync = NULL;
+
+ if (mod_freesync == NULL)
+ return false;
+
+ core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
+ core_dc = DC_TO_CORE(core_freesync->dc);
flag.save_per_edid = true;
flag.save_per_link = false;
@@ -842,10 +867,14 @@ bool mod_freesync_get_user_enable(struct mod_freesync *mod_freesync,
const struct dc_stream *stream,
struct mod_freesync_user_enable *user_enable)
{
- struct core_freesync *core_freesync =
- MOD_FREESYNC_TO_CORE(mod_freesync);
+ unsigned int index = 0;
+ struct core_freesync *core_freesync = NULL;
- unsigned int index = map_index_from_stream(core_freesync, stream);
+ if (mod_freesync == NULL)
+ return false;
+
+ core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
+ index = map_index_from_stream(core_freesync, stream);
*user_enable = core_freesync->map[index].user_enable;
@@ -855,12 +884,15 @@ bool mod_freesync_get_user_enable(struct mod_freesync *mod_freesync,
void mod_freesync_notify_mode_change(struct mod_freesync *mod_freesync,
const struct dc_stream **streams, int num_streams)
{
- struct core_freesync *core_freesync =
- MOD_FREESYNC_TO_CORE(mod_freesync);
-
unsigned int stream_index, map_index;
unsigned min_frame_duration_in_ns, max_frame_duration_in_ns;
struct freesync_state *state;
+ struct core_freesync *core_freesync = NULL;
+
+ if (mod_freesync == NULL)
+ return;
+
+ core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
for (stream_index = 0; stream_index < num_streams; stream_index++) {
@@ -1121,8 +1153,12 @@ void mod_freesync_pre_update_plane_addresses(struct mod_freesync *mod_freesync,
unsigned int curr_time_stamp_in_us)
{
unsigned int stream_index, map_index, last_render_time_in_us = 0;
- struct core_freesync *core_freesync =
- MOD_FREESYNC_TO_CORE(mod_freesync);
+ struct core_freesync *core_freesync = NULL;
+
+ if (mod_freesync == NULL)
+ return;
+
+ core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
for (stream_index = 0; stream_index < num_streams; stream_index++) {
diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
index 7abfe34dc2d9..783ff2ef3bee 100644
--- a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
+++ b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
@@ -110,13 +110,6 @@ bool mod_freesync_remove_stream(struct mod_freesync *mod_freesync,
const struct dc_stream *stream);
/*
- * Build additional parameters for dc_stream when creating stream for
- * sink to support freesync
- */
-void mod_freesync_update_stream(struct mod_freesync *mod_freesync,
- struct dc_stream *stream);
-
-/*
* Update the freesync state flags for each display and program
* freesync accordingly
*/
--
2.9.3
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 04/25] drm/amd/display: Fixing some fallout from dc_target removal
[not found] ` <20170123143613.15441-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (2 preceding siblings ...)
2017-01-23 14:35 ` [PATCH 03/25] drm/amd/display: Disable Modules at Runtime Harry Wentland
@ 2017-01-23 14:35 ` Harry Wentland
2017-01-23 14:35 ` [PATCH 05/25] drm/amd/display: No audio output heard from DP panel Harry Wentland
` (20 subsequent siblings)
24 siblings, 0 replies; 27+ messages in thread
From: Harry Wentland @ 2017-01-23 14:35 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Leon Elazar
From: Leon Elazar <leon.elazar@amd.com>
Also avoid allocating memory dce110_set_output_transfer_func
if not needed
Change-Id: Ica29ab36d1bb47451550e2f6ee0cdf8617c44a48
Signed-off-by: Leon Elazar <leon.elazar@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 6 +++--
drivers/gpu/drm/amd/display/dc/dce/dce_opp.c | 7 +++++
.../amd/display/dc/dce110/dce110_hw_sequencer.c | 30 +++++-----------------
.../amd/display/dc/dce110/dce110_opp_regamma_v.c | 7 +++++
.../gpu/drm/amd/display/dc/dce110/dce110_opp_v.c | 6 ++++-
.../gpu/drm/amd/display/dc/dce110/dce110_opp_v.h | 4 +++
.../drm/amd/display/dc/dce110/dce110_resource.c | 17 +++++++++---
drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h | 1 -
drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 1 +
9 files changed, 49 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index bc1f387d1992..47816c5ee0e0 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -192,7 +192,8 @@ bool dc_stream_set_cursor_attributes(
for (i = 0; i < MAX_PIPES; i++) {
struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
- if (pipe_ctx->stream == stream) {
+ if ((pipe_ctx->stream == stream) &&
+ (pipe_ctx->ipp != NULL)) {
struct input_pixel_processor *ipp = pipe_ctx->ipp;
if (ipp->funcs->ipp_cursor_set_attributes(
@@ -231,7 +232,8 @@ bool dc_stream_set_cursor_position(
for (i = 0; i < MAX_PIPES; i++) {
struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
- if (pipe_ctx->stream == stream) {
+ if ((pipe_ctx->stream == stream) &&
+ (pipe_ctx->ipp != NULL)) {
struct input_pixel_processor *ipp = pipe_ctx->ipp;
struct dc_cursor_mi_param param = {
.pixel_clk_khz = dc_stream->timing.pix_clk_khz,
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
index 167f523df657..061de9e8249d 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
@@ -973,6 +973,10 @@ bool dce110_opp_construct(struct dce110_opp *opp110,
opp110->base.inst = inst;
+ opp110->base.regamma_params = dm_alloc(sizeof(struct pwl_params));
+ if (opp110->base.regamma_params == NULL)
+ return false;
+
opp110->regs = regs;
opp110->opp_shift = opp_shift;
opp110->opp_mask = opp_mask;
@@ -982,6 +986,9 @@ bool dce110_opp_construct(struct dce110_opp *opp110,
void dce110_opp_destroy(struct output_pixel_processor **opp)
{
+ dm_free((*opp)->regamma_params);
+ (*opp)->regamma_params = NULL;
+
dm_free(FROM_DCE11_OPP(*opp));
*opp = NULL;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 6e70cf7b99ef..1a9ba127b781 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -721,43 +721,27 @@ static bool dce110_set_output_transfer_func(
const struct core_stream *stream)
{
struct output_pixel_processor *opp = pipe_ctx->opp;
- const struct core_gamma *ramp = NULL;
- struct pwl_params *regamma_params;
- bool result = false;
-
- if (surface->public.gamma_correction)
- ramp = DC_GAMMA_TO_CORE(surface->public.gamma_correction);
-
- regamma_params = dm_alloc(sizeof(struct pwl_params));
- if (regamma_params == NULL)
- goto regamma_alloc_fail;
-
- regamma_params->hw_points_num = GAMMA_HW_POINTS_NUM;
opp->funcs->opp_power_on_regamma_lut(opp, true);
+ opp->regamma_params->hw_points_num = GAMMA_HW_POINTS_NUM;
if (stream->public.out_transfer_func &&
- stream->public.out_transfer_func->type ==
+ stream->public.out_transfer_func->type ==
TF_TYPE_PREDEFINED &&
- stream->public.out_transfer_func->tf ==
+ stream->public.out_transfer_func->tf ==
TRANSFER_FUNCTION_SRGB) {
opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_SRGB);
} else if (dce110_translate_regamma_to_hw_format(
- stream->public.out_transfer_func, regamma_params)) {
- opp->funcs->opp_program_regamma_pwl(opp, regamma_params);
- opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_USER);
+ stream->public.out_transfer_func, opp->regamma_params)) {
+ opp->funcs->opp_program_regamma_pwl(opp, opp->regamma_params);
+ opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_USER);
} else {
opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_BYPASS);
}
opp->funcs->opp_power_on_regamma_lut(opp, false);
- result = true;
-
- dm_free(regamma_params);
-
-regamma_alloc_fail:
- return result;
+ return true;
}
static enum dc_status bios_parser_crtc_source_select(
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c
index 8164aa6bcb00..876445f14c85 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c
@@ -548,3 +548,10 @@ void dce110_opp_power_on_regamma_lut_v(
dm_write_reg(opp->ctx, mmDCFEV_MEM_PWR_CTRL, value);
}
+
+void dce110_opp_set_regamma_mode_v(
+ struct output_pixel_processor *opp,
+ enum opp_regamma mode)
+{
+ // TODO: need to implement the function
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c
index 0a9b384303d0..95b3d2eb8428 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c
@@ -42,7 +42,7 @@ static const struct opp_funcs funcs = {
.opp_set_csc_default = dce110_opp_v_set_csc_default,
.opp_set_csc_adjustment = dce110_opp_v_set_csc_adjustment,
.opp_set_dyn_expansion = dce110_opp_set_dyn_expansion,
- .opp_set_regamma_mode = dce110_opp_set_regamma_mode,
+ .opp_set_regamma_mode = dce110_opp_set_regamma_mode_v,
.opp_destroy = dce110_opp_destroy,
.opp_program_fmt = dce110_opp_program_fmt,
.opp_program_bit_depth_reduction =
@@ -56,6 +56,10 @@ bool dce110_opp_v_construct(struct dce110_opp *opp110,
opp110->base.ctx = ctx;
+ opp110->base.regamma_params = dm_alloc(sizeof(struct pwl_params));
+ if (opp110->base.regamma_params == NULL)
+ return false;
+
return true;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.h
index ac5937786ce3..cb26c515d30f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.h
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.h
@@ -49,4 +49,8 @@ void dce110_opp_power_on_regamma_lut_v(
struct output_pixel_processor *opp,
bool power_on);
+void dce110_opp_set_regamma_mode_v(
+ struct output_pixel_processor *opp,
+ enum opp_regamma mode);
+
#endif /* __DC_OPP_DCE110_V_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
index cfbb4ef21f8b..82cddb6425a0 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
@@ -1114,14 +1114,22 @@ static const struct resource_funcs dce110_res_pool_funcs = {
dce110_resource_build_bit_depth_reduction_params
};
-static void underlay_create(struct dc_context *ctx, struct resource_pool *pool)
+static bool underlay_create(struct dc_context *ctx, struct resource_pool *pool)
{
struct dce110_timing_generator *dce110_tgv = dm_alloc(sizeof (*dce110_tgv));
struct dce_transform *dce110_xfmv = dm_alloc(sizeof (*dce110_xfmv));
struct dce110_mem_input *dce110_miv = dm_alloc(sizeof (*dce110_miv));
struct dce110_opp *dce110_oppv = dm_alloc(sizeof (*dce110_oppv));
- dce110_opp_v_construct(dce110_oppv, ctx);
+ if ((dce110_tgv == NULL) ||
+ (dce110_xfmv == NULL) ||
+ (dce110_miv == NULL) ||
+ (dce110_oppv == NULL))
+ return false;
+
+ if (!dce110_opp_v_construct(dce110_oppv, ctx))
+ return false;
+
dce110_timing_generator_v_construct(dce110_tgv, ctx);
dce110_mem_input_v_construct(dce110_miv, ctx);
dce110_transform_v_construct(dce110_xfmv, ctx);
@@ -1135,6 +1143,8 @@ static void underlay_create(struct dc_context *ctx, struct resource_pool *pool)
/* update the public caps to indicate an underlay is available */
ctx->dc->caps.max_slave_planes = 1;
ctx->dc->caps.max_slave_planes = 1;
+
+ return true;
}
static void bw_calcs_data_update_from_pplib(struct core_dc *dc)
@@ -1334,7 +1344,8 @@ static bool construct(
}
}
- underlay_create(ctx, &pool->base);
+ if (!underlay_create(ctx, &pool->base))
+ goto res_create_fail;
if (!resource_construct(num_virtual_links, dc, &pool->base,
&res_create_funcs))
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
index 3b0e616f7066..b8735b27e9bc 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
@@ -65,7 +65,6 @@ struct pwl_result_data {
};
struct pwl_params {
- uint32_t *data;
struct gamma_curve arr_curve_points[16];
struct curve_points arr_points[3];
struct pwl_result_data rgb_resulted[256 + 3];
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
index bef5e2cacbe3..a10c4e296960 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
@@ -202,6 +202,7 @@ enum opp_regamma {
struct output_pixel_processor {
struct dc_context *ctx;
uint32_t inst;
+ struct pwl_params *regamma_params;
const struct opp_funcs *funcs;
};
--
2.9.3
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^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 05/25] drm/amd/display: No audio output heard from DP panel
[not found] ` <20170123143613.15441-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (3 preceding siblings ...)
2017-01-23 14:35 ` [PATCH 04/25] drm/amd/display: Fixing some fallout from dc_target removal Harry Wentland
@ 2017-01-23 14:35 ` Harry Wentland
2017-01-23 14:35 ` [PATCH 06/25] drm/amd/display: Use pflip prepare and submit parts (v2) Harry Wentland
` (19 subsequent siblings)
24 siblings, 0 replies; 27+ messages in thread
From: Harry Wentland @ 2017-01-23 14:35 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Hersen Wu
From: Hersen Wu <hersenxs.wu@amd.com>
Change-Id: I36ffd7bb121067d85d43ab90c9abf62981d50ed7
Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Eagle Yeh <eagle.yeh@amd.com>
---
drivers/gpu/drm/amd/display/dc/dce/dce_audio.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.h b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.h
index bf97cd8c8221..c244887ba15e 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.h
@@ -50,8 +50,8 @@
SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\
SF(DCCG_AUDIO_DTO0_MODULE, DCCG_AUDIO_DTO0_MODULE, mask_sh),\
SF(DCCG_AUDIO_DTO0_PHASE, DCCG_AUDIO_DTO0_PHASE, mask_sh),\
- SF(DCCG_AUDIO_DTO0_MODULE, DCCG_AUDIO_DTO0_MODULE, mask_sh),\
- SF(DCCG_AUDIO_DTO0_PHASE, DCCG_AUDIO_DTO0_PHASE, mask_sh),\
+ SF(DCCG_AUDIO_DTO1_MODULE, DCCG_AUDIO_DTO1_MODULE, mask_sh),\
+ SF(DCCG_AUDIO_DTO1_PHASE, DCCG_AUDIO_DTO1_PHASE, mask_sh),\
SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES, AUDIO_RATE_CAPABILITIES, mask_sh),\
SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, CLKSTOP, mask_sh),\
SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, EPSS, mask_sh)
--
2.9.3
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^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 06/25] drm/amd/display: Use pflip prepare and submit parts (v2)
[not found] ` <20170123143613.15441-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (4 preceding siblings ...)
2017-01-23 14:35 ` [PATCH 05/25] drm/amd/display: No audio output heard from DP panel Harry Wentland
@ 2017-01-23 14:35 ` Harry Wentland
2017-01-23 14:35 ` [PATCH 07/25] drm/amd/display: mode change without breaking unaffected streams Harry Wentland
` (18 subsequent siblings)
24 siblings, 0 replies; 27+ messages in thread
From: Harry Wentland @ 2017-01-23 14:35 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Andrey Grodzovsky
From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Use new functions so flip failures can be gracefully handled
v2:
Avoid -EINVAL returned from amdgpu_crtc_prepare_flip in some
error cases, it is not allowed according to expected
return values for atomic_commit hook.
Change-Id: Ie04af6f0c56ee822ddb9f24fb77f367b4e31c620
Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 96 +++++++++++++++++++---
1 file changed, 83 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index d1a11d93af7a..a26749854ec7 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -1647,6 +1647,7 @@ static void clear_unrelated_fields(struct drm_plane_state *state)
static bool page_flip_needed(
const struct drm_plane_state *new_state,
const struct drm_plane_state *old_state,
+ struct drm_pending_vblank_event *event,
bool commit_surface_required)
{
struct drm_plane_state old_state_tmp;
@@ -1676,7 +1677,7 @@ static bool page_flip_needed(
old_state_tmp = *old_state;
new_state_tmp = *new_state;
- if (!new_state->crtc->state->event)
+ if (!event)
return false;
amdgpu_fb_old = to_amdgpu_framebuffer(old_state->fb);
@@ -2485,17 +2486,21 @@ int amdgpu_dm_atomic_commit(
struct amdgpu_device *adev = dev->dev_private;
struct amdgpu_display_manager *dm = &adev->dm;
struct drm_plane *plane;
+ struct drm_plane_state *new_plane_state;
struct drm_plane_state *old_plane_state;
uint32_t i;
int32_t ret = 0;
uint32_t commit_streams_count = 0;
uint32_t new_crtcs_count = 0;
+ uint32_t flip_crtcs_count = 0;
struct drm_crtc *crtc;
struct drm_crtc_state *old_crtc_state;
-
const struct dc_stream *commit_streams[MAX_STREAMS];
struct amdgpu_crtc *new_crtcs[MAX_STREAMS];
const struct dc_stream *new_stream;
+ struct drm_crtc *flip_crtcs[MAX_STREAMS];
+ struct amdgpu_flip_work *work[MAX_STREAMS] = {0};
+ struct amdgpu_bo *new_abo[MAX_STREAMS] = {0};
/* In this step all new fb would be pinned */
@@ -2511,6 +2516,61 @@ int amdgpu_dm_atomic_commit(
return ret;
}
+ /* Page flip if needed */
+ for_each_plane_in_state(state, plane, new_plane_state, i) {
+ struct drm_plane_state *old_plane_state = plane->state;
+ struct drm_crtc *crtc = new_plane_state->crtc;
+ struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
+ struct drm_framebuffer *fb = new_plane_state->fb;
+ struct drm_crtc_state *crtc_state;
+
+ if (!fb || !crtc)
+ continue;
+
+ crtc_state = drm_atomic_get_crtc_state(state, crtc);
+
+ if (!crtc_state->planes_changed || !crtc_state->active)
+ continue;
+
+ if (page_flip_needed(
+ new_plane_state,
+ old_plane_state,
+ crtc_state->event,
+ false)) {
+ ret = amdgpu_crtc_prepare_flip(crtc,
+ fb,
+ crtc_state->event,
+ acrtc->flip_flags,
+ drm_crtc_vblank_count(crtc),
+ &work[flip_crtcs_count],
+ &new_abo[flip_crtcs_count]);
+
+ if (ret) {
+ /* According to atomic_commit hook API, EINVAL is not allowed */
+ if (unlikely(ret == -EINVAL))
+ ret = -ENOMEM;
+
+ DRM_ERROR("Atomic commit: Flip for crtc id %d: [%p], "
+ "failed, errno = %d\n",
+ acrtc->crtc_id,
+ acrtc,
+ ret);
+ /* cleanup all flip configurations which
+ * succeeded in this commit
+ */
+ for (i = 0; i < flip_crtcs_count; i++)
+ amdgpu_crtc_cleanup_flip_ctx(
+ work[i],
+ new_abo[i]);
+
+ return ret;
+ }
+
+ flip_crtcs[flip_crtcs_count] = crtc;
+ flip_crtcs_count++;
+ }
+ }
+
/*
* This is the point of no return - everything below never fails except
* when the hw goes bonghits. Which means we can commit the new state on
@@ -2699,7 +2759,10 @@ int amdgpu_dm_atomic_commit(
* 1. This commit is not a page flip.
* 2. This commit is a page flip, and streams are created.
*/
- if (!page_flip_needed(plane_state, old_plane_state, true) ||
+ if (!page_flip_needed(
+ plane_state,
+ old_plane_state,
+ crtc->state->event, true) ||
action == DM_COMMIT_ACTION_DPMS_ON ||
action == DM_COMMIT_ACTION_SET) {
list_for_each_entry(connector,
@@ -2755,7 +2818,8 @@ int amdgpu_dm_atomic_commit(
}
- /* Page flip if needed */
+ /* Do actual flip */
+ flip_crtcs_count = 0;
for_each_plane_in_state(state, plane, old_plane_state, i) {
struct drm_plane_state *plane_state = plane->state;
struct drm_crtc *crtc = plane_state->crtc;
@@ -2766,16 +2830,19 @@ int amdgpu_dm_atomic_commit(
!crtc->state->active)
continue;
- if (page_flip_needed(plane_state, old_plane_state, false)) {
- ret = amdgpu_crtc_page_flip_target(crtc,
- fb,
- crtc->state->event,
- acrtc->flip_flags,
- drm_crtc_vblank_count(crtc));
+ if (page_flip_needed(
+ plane_state,
+ old_plane_state,
+ crtc->state->event,
+ false)) {
+ amdgpu_crtc_submit_flip(
+ crtc,
+ fb,
+ work[flip_crtcs_count],
+ new_abo[i]);
+ flip_crtcs_count++;
/*clean up the flags for next usage*/
acrtc->flip_flags = 0;
- if (ret)
- return ret;
}
}
@@ -3127,6 +3194,8 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
struct drm_connector *connector;
struct dm_connector_state *dm_state = NULL;
enum dm_commit_action action;
+ struct drm_crtc_state *crtc_state;
+
if (!fb || !crtc || crtc_set[i] != crtc ||
!crtc->state->planes_changed || !crtc->state->active)
@@ -3138,8 +3207,9 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
* 1. This commit is not a page flip.
* 2. This commit is a page flip, and streams are created.
*/
+ crtc_state = drm_atomic_get_crtc_state(state, crtc);
if (!page_flip_needed(plane_state, old_plane_state,
- true) ||
+ crtc_state->event, true) ||
action == DM_COMMIT_ACTION_DPMS_ON ||
action == DM_COMMIT_ACTION_SET) {
struct dc_surface *surface;
--
2.9.3
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 07/25] drm/amd/display: mode change without breaking unaffected streams
[not found] ` <20170123143613.15441-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (5 preceding siblings ...)
2017-01-23 14:35 ` [PATCH 06/25] drm/amd/display: Use pflip prepare and submit parts (v2) Harry Wentland
@ 2017-01-23 14:35 ` Harry Wentland
2017-01-23 14:35 ` [PATCH 08/25] drm/amd/display: assert if mask is 0 in set_reg_field_value_ex Harry Wentland
` (17 subsequent siblings)
24 siblings, 0 replies; 27+ messages in thread
From: Harry Wentland @ 2017-01-23 14:35 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Yongqiang Sun, Tony Cheng
From: Tony Cheng <tony.cheng@amd.com>
- include clock constraint logic in validate
- in dc_commit_streams, include surfaces of unaffected streams
Change-Id: I43488ffa9002bd00740a4edb39c362b0257bdb11
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 11 +++++++++--
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2 +-
drivers/gpu/drm/amd/display/dc/inc/core_status.h | 2 ++
3 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 948f82a56472..9deddc8ee2d1 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1007,7 +1007,7 @@ bool dc_commit_streams(
struct dc_bios *dcb = core_dc->ctx->dc_bios;
enum dc_status result = DC_ERROR_UNEXPECTED;
struct validate_context *context;
- struct dc_validation_set set[MAX_STREAMS];
+ struct dc_validation_set set[MAX_STREAMS] = { 0 };
int i, j, k;
if (false == streams_changed(core_dc, streams, stream_count))
@@ -1018,13 +1018,20 @@ bool dc_commit_streams(
for (i = 0; i < stream_count; i++) {
const struct dc_stream *stream = streams[i];
+ const struct dc_stream_status *status = dc_stream_get_status(stream);
+ int j;
dc_stream_log(stream,
core_dc->ctx->logger,
LOG_DC);
set[i].stream = stream;
- set[i].surface_count = 0;
+
+ if (status) {
+ set[i].surface_count = status->surface_count;
+ for (j = 0; j < status->surface_count; j++)
+ set[i].surfaces[j] = status->surfaces[j];
+ }
}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 1f87b948678b..6037ee25598c 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -585,7 +585,7 @@ enum dc_status resource_build_scaling_params_for_context(
if (!resource_build_scaling_params(
&context->res_ctx.pipe_ctx[i].surface->public,
&context->res_ctx.pipe_ctx[i]))
- return DC_FAIL_BANDWIDTH_VALIDATE;
+ return DC_FAIL_SCALING;
}
return DC_OK;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_status.h b/drivers/gpu/drm/amd/display/dc/inc/core_status.h
index 32a2cc712000..147eb7cac701 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_status.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_status.h
@@ -40,6 +40,8 @@ enum dc_status {
DC_EXCEED_DONGLE_MAX_CLK,
DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED,
DC_FAIL_BANDWIDTH_VALIDATE, /* BW and Watermark validation */
+ DC_FAIL_SCALING,
+ DC_FAIL_CLK_CONSTRAINT,
DC_ERROR_UNEXPECTED = -1
};
--
2.9.3
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^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 08/25] drm/amd/display: assert if mask is 0 in set_reg_field_value_ex
[not found] ` <20170123143613.15441-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (6 preceding siblings ...)
2017-01-23 14:35 ` [PATCH 07/25] drm/amd/display: mode change without breaking unaffected streams Harry Wentland
@ 2017-01-23 14:35 ` Harry Wentland
2017-01-23 14:35 ` [PATCH 09/25] drm/amd/display: remove un-used defines and dead code Harry Wentland
` (16 subsequent siblings)
24 siblings, 0 replies; 27+ messages in thread
From: Harry Wentland @ 2017-01-23 14:35 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tony Cheng
From: Tony Cheng <tony.cheng@amd.com>
- mask = 0 means something is wrong in caller and no register field will be updated
Change-Id: Ib30c28ca30f574c703cd3b6acc42e5a401a9aff0
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
---
drivers/gpu/drm/amd/display/dc/dm_services.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h
index 11a0abfd3418..052a43af1bd3 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_services.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_services.h
@@ -165,6 +165,7 @@ static inline uint32_t set_reg_field_value_ex(
uint32_t mask,
uint8_t shift)
{
+ ASSERT(mask != 0);
return (reg_value & ~mask) | (mask & (value << shift));
}
--
2.9.3
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^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 09/25] drm/amd/display: remove un-used defines and dead code
[not found] ` <20170123143613.15441-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (7 preceding siblings ...)
2017-01-23 14:35 ` [PATCH 08/25] drm/amd/display: assert if mask is 0 in set_reg_field_value_ex Harry Wentland
@ 2017-01-23 14:35 ` Harry Wentland
2017-01-23 14:35 ` [PATCH 10/25] drm/amd/display: remove hw_crtc_timing Harry Wentland
` (15 subsequent siblings)
24 siblings, 0 replies; 27+ messages in thread
From: Harry Wentland @ 2017-01-23 14:35 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tony Cheng
From: Tony Cheng <tony.cheng@amd.com>
Change-Id: Ib32be9d265062d862557568b19160d7a866bb454
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
---
.../gpu/drm/amd/display/dc/basics/signal_types.c | 35 -------
.../gpu/drm/amd/display/dc/bios/command_table.c | 55 ----------
.../gpu/drm/amd/display/dc/bios/command_table.h | 3 -
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 1 -
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +-
.../display/include/asic_capability_interface.h | 55 ----------
.../amd/display/include/asic_capability_types.h | 116 ---------------------
.../drm/amd/display/include/bios_parser_types.h | 8 --
.../drm/amd/display/include/ddc_service_types.h | 7 --
.../gpu/drm/amd/display/include/irq_interface.h | 31 ------
.../drm/amd/display/include/link_service_types.h | 75 -------------
drivers/gpu/drm/amd/display/include/signal_types.h | 3 -
12 files changed, 1 insertion(+), 390 deletions(-)
delete mode 100644 drivers/gpu/drm/amd/display/include/asic_capability_interface.h
delete mode 100644 drivers/gpu/drm/amd/display/include/asic_capability_types.h
delete mode 100644 drivers/gpu/drm/amd/display/include/irq_interface.h
diff --git a/drivers/gpu/drm/amd/display/dc/basics/signal_types.c b/drivers/gpu/drm/amd/display/dc/basics/signal_types.c
index 44447e07803a..247487c3db71 100644
--- a/drivers/gpu/drm/amd/display/dc/basics/signal_types.c
+++ b/drivers/gpu/drm/amd/display/dc/basics/signal_types.c
@@ -44,23 +44,6 @@ bool dc_is_dp_signal(enum signal_type signal)
signal == SIGNAL_TYPE_DISPLAY_PORT_MST);
}
-bool dc_is_dp_external_signal(enum signal_type signal)
-{
- return (signal == SIGNAL_TYPE_DISPLAY_PORT ||
- signal == SIGNAL_TYPE_DISPLAY_PORT_MST);
-}
-
-bool dc_is_analog_signal(enum signal_type signal)
-{
- switch (signal) {
- case SIGNAL_TYPE_RGB:
- return true;
- break;
- default:
- return false;
- }
-}
-
bool dc_is_embedded_signal(enum signal_type signal)
{
return (signal == SIGNAL_TYPE_EDP || signal == SIGNAL_TYPE_LVDS);
@@ -96,21 +79,3 @@ bool dc_is_audio_capable_signal(enum signal_type signal)
signal == SIGNAL_TYPE_WIRELESS);
}
-/*
- * @brief
- * Returns whether the signal is compatible
- * with other digital encoder signal types.
- * This is true for DVI, LVDS, and HDMI signal types.
- */
-bool dc_is_digital_encoder_compatible_signal(enum signal_type signal)
-{
- switch (signal) {
- case SIGNAL_TYPE_DVI_SINGLE_LINK:
- case SIGNAL_TYPE_DVI_DUAL_LINK:
- case SIGNAL_TYPE_HDMI_TYPE_A:
- case SIGNAL_TYPE_LVDS:
- return true;
- default:
- return false;
- }
-}
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table.c b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
index d0eedb6235fe..88aaf53cb8c4 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
@@ -56,7 +56,6 @@ static void init_dac_encoder_control(struct bios_parser *bp);
static void init_dac_output_control(struct bios_parser *bp);
static void init_blank_crtc(struct bios_parser *bp);
static void init_set_crtc_timing(struct bios_parser *bp);
-static void init_set_crtc_overscan(struct bios_parser *bp);
static void init_select_crtc_source(struct bios_parser *bp);
static void init_enable_crtc(struct bios_parser *bp);
static void init_enable_crtc_mem_req(struct bios_parser *bp);
@@ -77,7 +76,6 @@ void dal_bios_parser_init_cmd_tbl(struct bios_parser *bp)
init_dac_output_control(bp);
init_blank_crtc(bp);
init_set_crtc_timing(bp);
- init_set_crtc_overscan(bp);
init_select_crtc_source(bp);
init_enable_crtc(bp);
init_enable_crtc_mem_req(bp);
@@ -1934,59 +1932,6 @@ static enum bp_result set_crtc_using_dtd_timing_v3(
/*******************************************************************************
********************************************************************************
**
- ** SET CRTC OVERSCAN
- **
- ********************************************************************************
- *******************************************************************************/
-
-static enum bp_result set_crtc_overscan_v1(
- struct bios_parser *bp,
- struct bp_hw_crtc_overscan_parameters *bp_params);
-
-static void init_set_crtc_overscan(struct bios_parser *bp)
-{
- switch (BIOS_CMD_TABLE_PARA_REVISION(SetCRTC_OverScan)) {
- case 1:
- bp->cmd_tbl.set_crtc_overscan = set_crtc_overscan_v1;
- break;
- default:
- bp->cmd_tbl.set_crtc_overscan = NULL;
- break;
- }
-}
-
-static enum bp_result set_crtc_overscan_v1(
- struct bios_parser *bp,
- struct bp_hw_crtc_overscan_parameters *bp_params)
-{
- enum bp_result result = BP_RESULT_FAILURE;
- SET_CRTC_OVERSCAN_PARAMETERS params = {0};
- uint8_t atom_controller_id;
-
- if (bp->cmd_helper->controller_id_to_atom(
- bp_params->controller_id, &atom_controller_id))
- params.ucCRTC = atom_controller_id;
- else
- return BP_RESULT_BADINPUT;
-
- params.usOverscanRight =
- cpu_to_le16((uint16_t)bp_params->h_overscan_right);
- params.usOverscanLeft =
- cpu_to_le16((uint16_t)bp_params->h_overscan_left);
- params.usOverscanBottom =
- cpu_to_le16((uint16_t)bp_params->v_overscan_bottom);
- params.usOverscanTop =
- cpu_to_le16((uint16_t)bp_params->v_overscan_top);
-
- if (EXEC_BIOS_CMD_TABLE(SetCRTC_OverScan, params))
- result = BP_RESULT_OK;
-
- return result;
-}
-
-/*******************************************************************************
- ********************************************************************************
- **
** SELECT CRTC SOURCE
**
********************************************************************************
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table.h b/drivers/gpu/drm/amd/display/dc/bios/command_table.h
index e1cd21b6e968..b8e6ef06c0c7 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table.h
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table.h
@@ -75,9 +75,6 @@ struct cmd_tbl {
enum bp_result (*set_crtc_timing)(
struct bios_parser *bp,
struct bp_hw_crtc_timing_parameters *bp_params);
- enum bp_result (*set_crtc_overscan)(
- struct bios_parser *bp,
- struct bp_hw_crtc_overscan_parameters *bp_params);
enum bp_result (*select_crtc_source)(
struct bios_parser *bp,
struct bp_crtc_source_select *bp_params);
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index b0f316344e86..62cfc5cbe773 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -38,7 +38,6 @@
#include "hw_sequencer.h"
#include "resource.h"
#include "fixed31_32.h"
-#include "include/asic_capability_interface.h"
#include "dpcd_defs.h"
#include "dce/dce_11_0_d.h"
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 3d5871dfc8e6..bc0667d55cf0 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -1922,7 +1922,7 @@ static void get_active_converter_info(
break;
}
- if (link->dpcd_caps.dpcd_rev.raw >= DCS_DPCD_REV_11) {
+ if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_11) {
uint8_t det_caps[4];
union dwnstream_port_caps_byte0 *port_caps =
(union dwnstream_port_caps_byte0 *)det_caps;
diff --git a/drivers/gpu/drm/amd/display/include/asic_capability_interface.h b/drivers/gpu/drm/amd/display/include/asic_capability_interface.h
deleted file mode 100644
index 57cc72fdc560..000000000000
--- a/drivers/gpu/drm/amd/display/include/asic_capability_interface.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of enc software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and enc permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_ASIC_CAPABILITY_INTERFACE_H__
-#define __DAL_ASIC_CAPABILITY_INTERFACE_H__
-
-/* Include */
-#include "include/asic_capability_types.h"
-
-/* Forward declaration */
-struct hw_asic_id;
-
-/* ASIC capability */
-struct asic_capability {
- struct dc_context *ctx;
- struct asic_caps caps;
- struct asic_stereo_3d_caps stereo_3d_caps;
- struct asic_bugs bugs;
- uint32_t data[ASIC_DATA_MAX_NUMBER];
-};
-
-/**
- * Interfaces
- */
-
-/* Create and initialize ASIC capability */
-struct asic_capability *dal_asic_capability_create(struct hw_asic_id *init,
- struct dc_context *ctx);
-
-/* Destroy ASIC capability and free memory space */
-void dal_asic_capability_destroy(struct asic_capability **cap);
-
-#endif /* __DAL_ASIC_CAPABILITY_INTERFACE_H__ */
diff --git a/drivers/gpu/drm/amd/display/include/asic_capability_types.h b/drivers/gpu/drm/amd/display/include/asic_capability_types.h
deleted file mode 100644
index c44dae043599..000000000000
--- a/drivers/gpu/drm/amd/display/include/asic_capability_types.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-#ifndef __DAL_ASIC_CAPABILITY_TYPES_H__
-#define __DAL_ASIC_CAPABILITY_TYPES_H__
-
-/*
- * ASIC Capabilities
- */
-struct asic_caps {
- bool CONSUMER_SINGLE_SELECTED_TIMING:1;
- bool UNDERSCAN_ADJUST:1;
- bool DELTA_SIGMA_SUPPORT:1;
- bool PANEL_SELF_REFRESH_SUPPORTED:1;
- bool IS_FUSION:1;
- bool DP_MST_SUPPORTED:1;
- bool UNDERSCAN_FOR_HDMI_ONLY:1;
- bool DVI_CLOCK_SHARE_CAPABILITY:1;
- bool SUPPORT_CEA861E_FINAL:1;
- bool MIRABILIS_SUPPORTED:1;
- bool MIRABILIS_ENABLED_BY_DEFAULT:1;
- bool DEVICE_TAG_REMAP_SUPPORTED:1;
- bool HEADLESS_NO_OPM_SUPPORTED:1;
- bool WIRELESS_LIMIT_TO_720P:1;
- bool WIRELESS_FULL_TIMING_ADJUSTMENT:1;
- bool WIRELESS_TIMING_ADJUSTMENT:1;
- bool WIRELESS_COMPRESSED_AUDIO:1;
- bool VCE_SUPPORTED:1;
- bool HPD_CHECK_FOR_EDID:1;
- bool NEED_MC_TUNING:1;
- bool SKIP_PSR_WAIT_FOR_PLL_LOCK_BIT:1;
- bool DFSBYPASS_DYNAMIC_SUPPORT:1;
- bool SUPPORT_8BPP:1;
-};
-
-/*
- * ASIC Stereo 3D Caps
- */
-struct asic_stereo_3d_caps {
- bool SUPPORTED:1;
- bool DISPLAY_BASED_ON_WS:1;
- bool HDMI_FRAME_PACK:1;
- bool INTERLACE_FRAME_PACK:1;
- bool DISPLAYPORT_FRAME_PACK:1;
- bool DISPLAYPORT_FRAME_ALT:1;
- bool INTERLEAVE:1;
-};
-
-/*
- * ASIC Bugs
- */
-struct asic_bugs {
- bool MST_SYMBOL_MISALIGNMENT:1;
- bool PSR_2X_LANE_GANGING:1;
- bool LB_WA_IS_SUPPORTED:1;
- bool ROM_REGISTER_ACCESS:1;
- bool PSR_WA_OVERSCAN_CRC_ERROR:1;
-};
-
-/*
- * ASIC Data
- */
-enum asic_data {
- ASIC_DATA_FIRST = 0,
- ASIC_DATA_DCE_VERSION = ASIC_DATA_FIRST,
- ASIC_DATA_DCE_VERSION_MINOR,
- ASIC_DATA_LINEBUFFER_SIZE,
- ASIC_DATA_DRAM_BANDWIDTH_EFFICIENCY,
- ASIC_DATA_MC_LATENCY,
- ASIC_DATA_MC_LATENCY_SLOW,
- ASIC_DATA_MEMORYTYPE_MULTIPLIER,
- ASIC_DATA_PATH_NUM_PER_DPMST_CONNECTOR,
- ASIC_DATA_MAX_UNDERSCAN_PERCENTAGE,
- ASIC_DATA_VIEWPORT_PIXEL_GRANULARITY,
- ASIC_DATA_MIN_DISPCLK_FOR_UNDERSCAN,
- ASIC_DATA_DOWNSCALE_LIMIT,
- ASIC_DATA_MAX_NUMBER /* end of enum */
-};
-
-/*
- * ASIC Feature Flags
- */
-struct asic_feature_flags {
- union {
- uint32_t raw;
- struct {
- uint32_t LEGACY_CLIENT:1;
- uint32_t PACKED_PIXEL_FORMAT:1;
- uint32_t WORKSTATION_STEREO:1;
- uint32_t WORKSTATION:1;
- } bits;
- };
-};
-
-#endif /* __DAL_ASIC_CAPABILITY_TYPES_H__ */
diff --git a/drivers/gpu/drm/amd/display/include/bios_parser_types.h b/drivers/gpu/drm/amd/display/include/bios_parser_types.h
index 9ab9065735f7..7de4fa5a0726 100644
--- a/drivers/gpu/drm/amd/display/include/bios_parser_types.h
+++ b/drivers/gpu/drm/amd/display/include/bios_parser_types.h
@@ -190,14 +190,6 @@ struct bp_hw_crtc_timing_parameters {
} flags;
};
-struct bp_hw_crtc_overscan_parameters {
- enum controller_id controller_id;
- uint32_t h_overscan_left;
- uint32_t h_overscan_right;
- uint32_t v_overscan_top;
- uint32_t v_overscan_bottom;
-};
-
struct bp_adjust_pixel_clock_parameters {
/* Input: Signal Type - to be converted to Encoder mode */
enum signal_type signal_type;
diff --git a/drivers/gpu/drm/amd/display/include/ddc_service_types.h b/drivers/gpu/drm/amd/display/include/ddc_service_types.h
index 0a6ba91e3eba..effe03b8f418 100644
--- a/drivers/gpu/drm/amd/display/include/ddc_service_types.h
+++ b/drivers/gpu/drm/amd/display/include/ddc_service_types.h
@@ -52,12 +52,6 @@ enum ddc_service_type {
DDC_SERVICE_TYPE_DISPLAY_PORT_MST,
};
-enum dcs_dpcd_revision {
- DCS_DPCD_REV_10 = 0x10,
- DCS_DPCD_REV_11 = 0x11,
- DCS_DPCD_REV_12 = 0x12
-};
-
/**
* display sink capability
*/
@@ -97,7 +91,6 @@ struct display_sink_capability {
uint32_t dp_link_rate;
uint32_t dp_link_spead;
- enum dcs_dpcd_revision dpcd_revision;
/* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER,
indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
bool is_dp_hdmi_s3d_converter;
diff --git a/drivers/gpu/drm/amd/display/include/irq_interface.h b/drivers/gpu/drm/amd/display/include/irq_interface.h
deleted file mode 100644
index 077ded3fbedd..000000000000
--- a/drivers/gpu/drm/amd/display/include/irq_interface.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_IRQ_INTERFACE_H__
-#define __DAL_IRQ_INTERFACE_H__
-
-#include "gpio_types.h"
-
-#endif
diff --git a/drivers/gpu/drm/amd/display/include/link_service_types.h b/drivers/gpu/drm/amd/display/include/link_service_types.h
index 6160a467ba37..479e5fff8a00 100644
--- a/drivers/gpu/drm/amd/display/include/link_service_types.h
+++ b/drivers/gpu/drm/amd/display/include/link_service_types.h
@@ -38,34 +38,11 @@ enum {
MAX_CONTROLLER_NUM = 6
};
-enum link_service_type {
- LINK_SERVICE_TYPE_LEGACY = 0,
- LINK_SERVICE_TYPE_DP_SST,
- LINK_SERVICE_TYPE_DP_MST,
- LINK_SERVICE_TYPE_MAX
-};
-
-enum dpcd_value_mask {
- DPCD_VALUE_MASK_MAX_LANE_COUNT_LANE_COUNT = 0x1F,
- DPCD_VALUE_MASK_MAX_LANE_COUNT_TPS3_SUPPORTED = 0x40,
- DPCD_VALUE_MASK_MAX_LANE_COUNT_ENHANCED_FRAME_EN = 0x80,
- DPCD_VALUE_MASK_MAX_DOWNSPREAD = 0x01,
- DPCD_VALUE_MASK_LANE_ALIGN_STATUS_INTERLANE_ALIGN_DONE = 0x01
-};
-
enum dp_power_state {
DP_POWER_STATE_D0 = 1,
DP_POWER_STATE_D3
};
-enum dpcd_downstream_port_types {
- DPCD_DOWNSTREAM_DP,
- DPCD_DOWNSTREAM_VGA,
- DPCD_DOWNSTREAM_DVI_HDMI,
- /* has no EDID (TV, CV) */
- DPCD_DOWNSTREAM_NON_DDC
-};
-
enum edp_revision {
/* eDP version 1.1 or lower */
EDP_REVISION_11 = 0x00,
@@ -135,36 +112,6 @@ enum dp_panel_mode {
DP_PANEL_MODE_SPECIAL
};
-/**
- * @brief LinkServiceInitOptions to set certain bits
- */
-struct link_service_init_options {
- uint32_t APPLY_MISALIGNMENT_BUG_WORKAROUND:1;
-};
-
-/**
- * @brief data required to initialize LinkService
- */
-struct link_service_init_data {
- /* number of displays indices which the MST Mgr would manange*/
- uint32_t num_of_displays;
- enum link_service_type link_type;
- /*struct mst_mgr_callback_object*topology_change_callback;*/
- /* native aux access */
- struct ddc_service *dpcd_access_srv;
- /* for calling HWSS to program HW */
- struct hw_sequencer *hwss;
- /* the source which to register IRQ on */
- enum dc_irq_source irq_src_hpd_rx;
- enum dc_irq_source irq_src_dp_sink;
- /* other init options such as SW Workarounds */
- struct link_service_init_options init_options;
- uint32_t connector_enum_id;
- struct graphics_object_id connector_id;
- struct dc_context *ctx;
- struct topology_mgr *tm;
-};
-
/* DPCD_ADDR_TRAINING_LANEx_SET registers value */
union dpcd_training_lane_set {
struct {
@@ -189,28 +136,6 @@ union dpcd_training_lane_set {
uint8_t raw;
};
-/**
- * @brief represent the 16 byte
- * global unique identifier
- */
-struct mst_guid {
- uint8_t ids[16];
-};
-
-/**
- * @brief represents the relative address used
- * to identify a node in MST topology network
- */
-struct mst_rad {
- /* number of links. rad[0] up to
- * rad [linkCount - 1] are valid. */
- uint32_t rad_link_count;
- /* relative address. rad[0] is the
- * first device connected to the source. */
- uint8_t rad[15];
- /* extra 10 bytes for underscores; for e.g.:2_1_8*/
- int8_t rad_str[25];
-};
/* DP MST stream allocation (payload bandwidth number) */
struct dp_mst_stream_allocation {
diff --git a/drivers/gpu/drm/amd/display/include/signal_types.h b/drivers/gpu/drm/amd/display/include/signal_types.h
index a50f7ed74a33..d87f84a56fcc 100644
--- a/drivers/gpu/drm/amd/display/include/signal_types.h
+++ b/drivers/gpu/drm/amd/display/include/signal_types.h
@@ -47,13 +47,10 @@ enum signal_type {
bool dc_is_hdmi_signal(enum signal_type signal);
bool dc_is_dp_sst_signal(enum signal_type signal);
bool dc_is_dp_signal(enum signal_type signal);
-bool dc_is_dp_external_signal(enum signal_type signal);
-bool dc_is_analog_signal(enum signal_type signal);
bool dc_is_embedded_signal(enum signal_type signal);
bool dc_is_dvi_signal(enum signal_type signal);
bool dc_is_dvi_single_link_signal(enum signal_type signal);
bool dc_is_dual_link_signal(enum signal_type signal);
bool dc_is_audio_capable_signal(enum signal_type signal);
-bool dc_is_digital_encoder_compatible_signal(enum signal_type signal);
#endif
--
2.9.3
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 10/25] drm/amd/display: remove hw_crtc_timing
[not found] ` <20170123143613.15441-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (8 preceding siblings ...)
2017-01-23 14:35 ` [PATCH 09/25] drm/amd/display: remove un-used defines and dead code Harry Wentland
@ 2017-01-23 14:35 ` Harry Wentland
2017-01-23 14:35 ` [PATCH 11/25] drm/amd/display: remove hw_info_frame Harry Wentland
` (14 subsequent siblings)
24 siblings, 0 replies; 27+ messages in thread
From: Harry Wentland @ 2017-01-23 14:35 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tony Cheng
From: Tony Cheng <tony.cheng@amd.com>
Change-Id: Id5c632c474a1643825c0bedbaf8be9c12bb36dca
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
---
.../drm/amd/display/dc/dce/dce_stream_encoder.c | 2 +-
.../amd/display/dc/dce110/dce110_hw_sequencer.c | 2 +-
.../gpu/drm/amd/display/dc/inc/hw/stream_encoder.h | 2 +-
.../drm/amd/display/include/hw_sequencer_types.h | 40 ----------------------
4 files changed, 3 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
index c510e95eb948..7e6661bda970 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
@@ -681,7 +681,7 @@ static void dce110_stream_encoder_dp_unblank(
uint64_t m_vid_l = n_vid;
- m_vid_l *= param->crtc_timing.pixel_clock;
+ m_vid_l *= param->pixel_clk_khz;
m_vid_l = div_u64(m_vid_l,
param->link_settings.link_rate
* LINK_RATE_REF_FREQ_IN_KHZ);
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 1a9ba127b781..b51668e3bb52 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -886,7 +886,7 @@ void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
struct encoder_unblank_param params = { { 0 } };
/* only 3 items below are used by unblank */
- params.crtc_timing.pixel_clock =
+ params.pixel_clk_khz =
pipe_ctx->stream->public.timing.pix_clk_khz;
params.link_settings.link_rate = link_settings->link_rate;
pipe_ctx->stream_enc->funcs->dp_unblank(pipe_ctx->stream_enc, ¶ms);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
index cb369af29d69..674bebfe3bd2 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
@@ -36,8 +36,8 @@ struct encoder_info_frame {
};
struct encoder_unblank_param {
- struct hw_crtc_timing crtc_timing;
struct dc_link_settings link_settings;
+ unsigned int pixel_clk_khz;
};
struct encoder_set_dp_phy_pattern_param {
diff --git a/drivers/gpu/drm/amd/display/include/hw_sequencer_types.h b/drivers/gpu/drm/amd/display/include/hw_sequencer_types.h
index 6bbca1b4d736..f99a03266149 100644
--- a/drivers/gpu/drm/amd/display/include/hw_sequencer_types.h
+++ b/drivers/gpu/drm/amd/display/include/hw_sequencer_types.h
@@ -40,46 +40,6 @@ struct drr_params {
uint32_t vertical_total_max;
};
-/* CRTC timing structure */
-struct hw_crtc_timing {
- uint32_t h_total;
- uint32_t h_addressable;
- uint32_t h_overscan_left;
- uint32_t h_overscan_right;
- uint32_t h_sync_start;
- uint32_t h_sync_width;
-
- uint32_t v_total;
- uint32_t v_addressable;
- uint32_t v_overscan_top;
- uint32_t v_overscan_bottom;
- uint32_t v_sync_start;
- uint32_t v_sync_width;
-
- /* in KHz */
- uint32_t pixel_clock;
-
- struct {
- uint32_t INTERLACED:1;
- uint32_t DOUBLESCAN:1;
- uint32_t PIXEL_REPETITION:4; /* 1...10 */
- uint32_t HSYNC_POSITIVE_POLARITY:1;
- uint32_t VSYNC_POSITIVE_POLARITY:1;
- /* frame should be packed for 3D
- * (currently this refers to HDMI 1.4a FramePacking format */
- uint32_t HORZ_COUNT_BY_TWO:1;
- uint32_t PACK_3D_FRAME:1;
- /* 0 - left eye polarity, 1 - right eye polarity */
- uint32_t RIGHT_EYE_3D_POLARITY:1;
- /* DVI-DL High-Color mode */
- uint32_t HIGH_COLOR_DL_MODE:1;
- uint32_t Y_ONLY:1;
- /* HDMI 2.0 - Support scrambling for TMDS character
- * rates less than or equal to 340Mcsc */
- uint32_t LTE_340MCSC_SCRAMBLE:1;
- } flags;
-};
-
/* TODO hw_info_frame and hw_info_packet structures are same as in encoder
* merge it*/
struct hw_info_packet {
--
2.9.3
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^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 11/25] drm/amd/display: remove hw_info_frame
[not found] ` <20170123143613.15441-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (9 preceding siblings ...)
2017-01-23 14:35 ` [PATCH 10/25] drm/amd/display: remove hw_crtc_timing Harry Wentland
@ 2017-01-23 14:35 ` Harry Wentland
2017-01-23 14:36 ` [PATCH 12/25] drm/amd/display: remove SIGNAL_TYPE_WIRELESS Harry Wentland
` (13 subsequent siblings)
24 siblings, 0 replies; 27+ messages in thread
From: Harry Wentland @ 2017-01-23 14:35 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tony Cheng
From: Tony Cheng <tony.cheng@amd.com>
- construct using encoder_info_frame directly
Change-Id: I95a2cdb6cdeaccea8c87c9c3ff6be9673ba65afe
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 124 +++++++--------------
.../drm/amd/display/include/hw_sequencer_types.h | 23 ----
2 files changed, 40 insertions(+), 107 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 6037ee25598c..fe79a2890247 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1211,70 +1211,27 @@ void validate_guaranteed_copy_streams(
}
}
-static void translate_info_frame(const struct hw_info_frame *hw_info_frame,
- struct encoder_info_frame *encoder_info_frame)
+static void patch_gamut_packet_checksum(
+ struct encoder_info_packet *gamut_packet)
{
- memset(
- encoder_info_frame, 0, sizeof(struct encoder_info_frame));
-
/* For gamut we recalc checksum */
- if (hw_info_frame->gamut_packet.valid) {
+ if (gamut_packet->valid) {
uint8_t chk_sum = 0;
uint8_t *ptr;
uint8_t i;
- memmove(
- &encoder_info_frame->gamut,
- &hw_info_frame->gamut_packet,
- sizeof(struct hw_info_packet));
-
/*start of the Gamut data. */
- ptr = &encoder_info_frame->gamut.sb[3];
+ ptr = &gamut_packet->sb[3];
- for (i = 0; i <= encoder_info_frame->gamut.sb[1]; i++)
+ for (i = 0; i <= gamut_packet->sb[1]; i++)
chk_sum += ptr[i];
- encoder_info_frame->gamut.sb[2] = (uint8_t) (0x100 - chk_sum);
- }
-
- if (hw_info_frame->avi_info_packet.valid) {
- memmove(
- &encoder_info_frame->avi,
- &hw_info_frame->avi_info_packet,
- sizeof(struct hw_info_packet));
- }
-
- if (hw_info_frame->vendor_info_packet.valid) {
- memmove(
- &encoder_info_frame->vendor,
- &hw_info_frame->vendor_info_packet,
- sizeof(struct hw_info_packet));
- }
-
- if (hw_info_frame->spd_packet.valid) {
- memmove(
- &encoder_info_frame->spd,
- &hw_info_frame->spd_packet,
- sizeof(struct hw_info_packet));
- }
-
- if (hw_info_frame->vsc_packet.valid) {
- memmove(
- &encoder_info_frame->vsc,
- &hw_info_frame->vsc_packet,
- sizeof(struct hw_info_packet));
- }
-
- if (hw_info_frame->hdrsmd_packet.valid) {
- memmove(
- &encoder_info_frame->hdrsmd,
- &hw_info_frame->hdrsmd_packet,
- sizeof(struct hw_info_packet));
+ gamut_packet->sb[2] = (uint8_t) (0x100 - chk_sum);
}
}
static void set_avi_info_frame(
- struct hw_info_packet *info_packet,
+ struct encoder_info_packet *info_packet,
struct pipe_ctx *pipe_ctx)
{
struct core_stream *stream = pipe_ctx->stream;
@@ -1288,9 +1245,6 @@ static void set_avi_info_frame(
uint8_t *check_sum = NULL;
uint8_t byte_index = 0;
- if (info_packet == NULL)
- return;
-
color_space = pipe_ctx->stream->public.output_color_space;
/* Initialize header */
@@ -1458,8 +1412,9 @@ static void set_avi_info_frame(
info_packet->valid = true;
}
-static void set_vendor_info_packet(struct core_stream *stream,
- struct hw_info_packet *info_packet)
+static void set_vendor_info_packet(
+ struct encoder_info_packet *info_packet,
+ struct core_stream *stream)
{
uint32_t length = 0;
bool hdmi_vic_mode = false;
@@ -1467,9 +1422,6 @@ static void set_vendor_info_packet(struct core_stream *stream,
uint32_t i = 0;
enum dc_timing_3d_format format;
- ASSERT_CRITICAL(stream != NULL);
- ASSERT_CRITICAL(info_packet != NULL);
-
format = stream->public.timing.timing_3d_format;
/* Can be different depending on packet content */
@@ -1567,8 +1519,9 @@ static void set_vendor_info_packet(struct core_stream *stream,
info_packet->valid = true;
}
-static void set_spd_info_packet(struct core_stream *stream,
- struct hw_info_packet *info_packet)
+static void set_spd_info_packet(
+ struct encoder_info_packet *info_packet,
+ struct core_stream *stream)
{
/* SPD info packet for FreeSync */
@@ -1688,9 +1641,9 @@ static void set_spd_info_packet(struct core_stream *stream,
}
static void set_hdr_static_info_packet(
+ struct encoder_info_packet *info_packet,
struct core_surface *surface,
- struct core_stream *stream,
- struct hw_info_packet *info_packet)
+ struct core_stream *stream)
{
uint16_t i = 0;
enum signal_type signal = stream->signal;
@@ -1791,8 +1744,9 @@ static void set_hdr_static_info_packet(
}
}
-static void set_vsc_info_packet(struct core_stream *stream,
- struct hw_info_packet *info_packet)
+static void set_vsc_info_packet(
+ struct encoder_info_packet *info_packet,
+ struct core_stream *stream)
{
unsigned int vscPacketRevision = 0;
unsigned int i;
@@ -1894,36 +1848,38 @@ struct clock_source *dc_resource_find_first_free_pll(
void resource_build_info_frame(struct pipe_ctx *pipe_ctx)
{
enum signal_type signal = SIGNAL_TYPE_NONE;
- struct hw_info_frame info_frame = { { 0 } };
+ struct encoder_info_frame *info = &pipe_ctx->encoder_info_frame;
/* default all packets to invalid */
- info_frame.avi_info_packet.valid = false;
- info_frame.gamut_packet.valid = false;
- info_frame.vendor_info_packet.valid = false;
- info_frame.spd_packet.valid = false;
- info_frame.vsc_packet.valid = false;
- info_frame.hdrsmd_packet.valid = false;
+ info->avi.valid = false;
+ info->gamut.valid = false;
+ info->vendor.valid = false;
+ info->hdrsmd.valid = false;
+ info->vsc.valid = false;
signal = pipe_ctx->stream->signal;
/* HDMi and DP have different info packets*/
if (dc_is_hdmi_signal(signal)) {
- set_avi_info_frame(
- &info_frame.avi_info_packet, pipe_ctx);
- set_vendor_info_packet(
- pipe_ctx->stream, &info_frame.vendor_info_packet);
- set_spd_info_packet(pipe_ctx->stream, &info_frame.spd_packet);
- set_hdr_static_info_packet(pipe_ctx->surface,
- pipe_ctx->stream, &info_frame.hdrsmd_packet);
+ set_avi_info_frame(&info->avi, pipe_ctx);
+
+ set_vendor_info_packet(&info->vendor, pipe_ctx->stream);
+
+ set_spd_info_packet(&info->spd, pipe_ctx->stream);
+
+ set_hdr_static_info_packet(&info->hdrsmd,
+ pipe_ctx->surface, pipe_ctx->stream);
+
} else if (dc_is_dp_signal(signal)) {
- set_vsc_info_packet(pipe_ctx->stream, &info_frame.vsc_packet);
- set_spd_info_packet(pipe_ctx->stream, &info_frame.spd_packet);
- set_hdr_static_info_packet(pipe_ctx->surface,
- pipe_ctx->stream, &info_frame.hdrsmd_packet);
+ set_vsc_info_packet(&info->vsc, pipe_ctx->stream);
+
+ set_spd_info_packet(&info->spd, pipe_ctx->stream);
+
+ set_hdr_static_info_packet(&info->hdrsmd,
+ pipe_ctx->surface, pipe_ctx->stream);
}
- translate_info_frame(&info_frame,
- &pipe_ctx->encoder_info_frame);
+ patch_gamut_packet_checksum(&info->gamut);
}
enum dc_status resource_map_clock_resources(
diff --git a/drivers/gpu/drm/amd/display/include/hw_sequencer_types.h b/drivers/gpu/drm/amd/display/include/hw_sequencer_types.h
index f99a03266149..6f0475c25566 100644
--- a/drivers/gpu/drm/amd/display/include/hw_sequencer_types.h
+++ b/drivers/gpu/drm/amd/display/include/hw_sequencer_types.h
@@ -40,27 +40,4 @@ struct drr_params {
uint32_t vertical_total_max;
};
-/* TODO hw_info_frame and hw_info_packet structures are same as in encoder
- * merge it*/
-struct hw_info_packet {
- bool valid;
- uint8_t hb0;
- uint8_t hb1;
- uint8_t hb2;
- uint8_t hb3;
- uint8_t sb[32];
-};
-
-struct hw_info_frame {
- /* Auxiliary Video Information */
- struct hw_info_packet avi_info_packet;
- struct hw_info_packet gamut_packet;
- struct hw_info_packet vendor_info_packet;
- /* Source Product Description */
- struct hw_info_packet spd_packet;
- /* Video Stream Configuration */
- struct hw_info_packet vsc_packet;
- struct hw_info_packet hdrsmd_packet;
-};
-
#endif
--
2.9.3
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 12/25] drm/amd/display: remove SIGNAL_TYPE_WIRELESS
[not found] ` <20170123143613.15441-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (10 preceding siblings ...)
2017-01-23 14:35 ` [PATCH 11/25] drm/amd/display: remove hw_info_frame Harry Wentland
@ 2017-01-23 14:36 ` Harry Wentland
2017-01-23 14:36 ` [PATCH 13/25] drm/amd/display: remove dead code Harry Wentland
` (12 subsequent siblings)
24 siblings, 0 replies; 27+ messages in thread
From: Harry Wentland @ 2017-01-23 14:36 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tony Cheng
From: Tony Cheng <tony.cheng@amd.com>
Change-Id: I67199dfb44db442aee25ebc73dea50e5c935bb84
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
---
drivers/gpu/drm/amd/display/dc/basics/log_helpers.c | 1 -
drivers/gpu/drm/amd/display/dc/basics/signal_types.c | 3 +--
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 3 ---
drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c | 1 -
drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h | 1 -
drivers/gpu/drm/amd/display/include/signal_types.h | 4 ----
6 files changed, 1 insertion(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c b/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c
index 61f36a7f322b..c4eddee8de1b 100644
--- a/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c
+++ b/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c
@@ -44,7 +44,6 @@ static const struct dc_signal_type_info signal_type_info_tbl[] = {
{SIGNAL_TYPE_DISPLAY_PORT, "DP"},
{SIGNAL_TYPE_DISPLAY_PORT_MST, "MST"},
{SIGNAL_TYPE_EDP, "eDP"},
- {SIGNAL_TYPE_WIRELESS, "Wireless"},
{SIGNAL_TYPE_VIRTUAL, "Virtual"}
};
diff --git a/drivers/gpu/drm/amd/display/dc/basics/signal_types.c b/drivers/gpu/drm/amd/display/dc/basics/signal_types.c
index 247487c3db71..534c803e7091 100644
--- a/drivers/gpu/drm/amd/display/dc/basics/signal_types.c
+++ b/drivers/gpu/drm/amd/display/dc/basics/signal_types.c
@@ -75,7 +75,6 @@ bool dc_is_audio_capable_signal(enum signal_type signal)
{
return (signal == SIGNAL_TYPE_DISPLAY_PORT ||
signal == SIGNAL_TYPE_DISPLAY_PORT_MST ||
- dc_is_hdmi_signal(signal) ||
- signal == SIGNAL_TYPE_WIRELESS);
+ dc_is_hdmi_signal(signal));
}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 62cfc5cbe773..f4f46d4f0cf0 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1051,9 +1051,6 @@ static bool construct(
if (link->device_tag.dev_id.device_type == DEVICE_TYPE_LCD
&& link->public.connector_signal == SIGNAL_TYPE_RGB)
continue;
- if (link->device_tag.dev_id.device_type == DEVICE_TYPE_WIRELESS
- && link->public.connector_signal != SIGNAL_TYPE_WIRELESS)
- continue;
break;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
index 930ae1377ab6..e9d1a54bffd3 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
@@ -941,7 +941,6 @@ bool dce110_link_encoder_construct(
enc110->base.hpd_source = init_data->hpd_source;
enc110->base.connector = init_data->connector;
- enc110->base.input_signals = SIGNAL_TYPE_ALL;
enc110->base.preferred_engine = ENGINE_ID_UNKNOWN;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
index 49c4b6587456..ac4010b9c638 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
@@ -186,7 +186,6 @@ struct link_encoder {
struct dc_context *ctx;
struct graphics_object_id id;
struct graphics_object_id connector;
- uint32_t input_signals;
uint32_t output_signals;
enum engine_id preferred_engine;
struct encoder_feature_support features;
diff --git a/drivers/gpu/drm/amd/display/include/signal_types.h b/drivers/gpu/drm/amd/display/include/signal_types.h
index d87f84a56fcc..1a2ca53c68cd 100644
--- a/drivers/gpu/drm/amd/display/include/signal_types.h
+++ b/drivers/gpu/drm/amd/display/include/signal_types.h
@@ -36,11 +36,7 @@ enum signal_type {
SIGNAL_TYPE_DISPLAY_PORT = (1 << 5),
SIGNAL_TYPE_DISPLAY_PORT_MST = (1 << 6),
SIGNAL_TYPE_EDP = (1 << 7),
- SIGNAL_TYPE_WIRELESS = (1 << 8), /* Wireless Display */
SIGNAL_TYPE_VIRTUAL = (1 << 9), /* Virtual Display */
-
- SIGNAL_TYPE_COUNT = 10,
- SIGNAL_TYPE_ALL = (1 << SIGNAL_TYPE_COUNT) - 1
};
/* help functions for signal types manipulation */
--
2.9.3
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 13/25] drm/amd/display: remove dead code
[not found] ` <20170123143613.15441-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (11 preceding siblings ...)
2017-01-23 14:36 ` [PATCH 12/25] drm/amd/display: remove SIGNAL_TYPE_WIRELESS Harry Wentland
@ 2017-01-23 14:36 ` Harry Wentland
2017-01-23 14:36 ` [PATCH 14/25] drm/amd/display: remove calculate_adjustments in conversion.h Harry Wentland
` (11 subsequent siblings)
24 siblings, 0 replies; 27+ messages in thread
From: Harry Wentland @ 2017-01-23 14:36 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tony Cheng
From: Tony Cheng <tony.cheng@amd.com>
Change-Id: I8d7266d9542132b2a4406eb7591a75769998e984
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
---
drivers/gpu/drm/amd/display/dc/bios/bios_parser.c | 76 --------------
.../gpu/drm/amd/display/dc/bios/command_table.c | 114 ---------------------
.../gpu/drm/amd/display/dc/bios/command_table.h | 7 --
drivers/gpu/drm/amd/display/dc/dc_bios_types.h | 6 --
.../drm/amd/display/include/bios_parser_types.h | 20 ----
5 files changed, 223 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
index ebd2e419f8f2..656c39ac0256 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
@@ -545,80 +545,6 @@ static enum bp_result bios_parser_get_hpd_info(struct dc_bios *dcb,
return BP_RESULT_NORECORD;
}
-static uint32_t bios_parser_get_gpio_record(
- struct dc_bios *dcb,
- struct graphics_object_id id,
- struct bp_gpio_cntl_info *gpio_record,
- uint32_t record_size)
-{
- struct bios_parser *bp = BP_FROM_DCB(dcb);
- ATOM_COMMON_RECORD_HEADER *header = NULL;
- ATOM_OBJECT_GPIO_CNTL_RECORD *record = NULL;
- ATOM_OBJECT *object = get_bios_object(bp, id);
- uint32_t offset;
- uint32_t pins_number;
- uint32_t i;
-
- if (!object)
- return 0;
-
- /* Initialise offset */
- offset = le16_to_cpu(object->usRecordOffset)
- + bp->object_info_tbl_offset;
-
- for (;;) {
- /* Get record header */
- header = GET_IMAGE(ATOM_COMMON_RECORD_HEADER, offset);
- if (!header || header->ucRecordType == LAST_RECORD_TYPE ||
- !header->ucRecordSize)
- break;
-
- /* If this is gpio control record - stop. We found the record */
- if (header->ucRecordType == ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE
- && header->ucRecordSize
- >= sizeof(ATOM_OBJECT_GPIO_CNTL_RECORD)) {
- record = (ATOM_OBJECT_GPIO_CNTL_RECORD *) header;
- break;
- }
-
- /* Advance to next record */
- offset += header->ucRecordSize;
- }
-
- /* If we did not find a record - return */
- if (!record)
- return 0;
-
- /* Extract gpio IDs from bios record (make sure we do not exceed passed
- * array size) */
- pins_number = (record->ucNumberOfPins < record_size ?
- record->ucNumberOfPins : record_size);
- for (i = 0; i < pins_number; i++) {
- uint8_t output_state = ((record->asGpio[i].ucGPIO_PinState
- & GPIO_PIN_OUTPUT_STATE_MASK)
- >> GPIO_PIN_OUTPUT_STATE_SHIFT);
- gpio_record[i].id = record->asGpio[i].ucGPIOID;
-
- switch (output_state) {
- case GPIO_PIN_STATE_ACTIVE_LOW:
- gpio_record[i].state =
- GPIO_PIN_OUTPUT_STATE_ACTIVE_LOW;
- break;
-
- case GPIO_PIN_STATE_ACTIVE_HIGH:
- gpio_record[i].state =
- GPIO_PIN_OUTPUT_STATE_ACTIVE_HIGH;
- break;
-
- default:
- BREAK_TO_DEBUGGER(); /* Invalid Pin Output State */
- break;
- }
- }
-
- return pins_number;
-}
-
enum bp_result bios_parser_get_device_tag_record(
struct bios_parser *bp,
ATOM_OBJECT *object,
@@ -4064,8 +3990,6 @@ static const struct dc_vbios_funcs vbios_funcs = {
.get_dst_number = bios_parser_get_dst_number,
- .get_gpio_record = bios_parser_get_gpio_record,
-
.get_src_obj = bios_parser_get_src_obj,
.get_dst_obj = bios_parser_get_dst_obj,
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table.c b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
index 88aaf53cb8c4..3f7b2dabc2b0 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
@@ -54,12 +54,10 @@ static void init_enable_spread_spectrum_on_ppll(struct bios_parser *bp);
static void init_adjust_display_pll(struct bios_parser *bp);
static void init_dac_encoder_control(struct bios_parser *bp);
static void init_dac_output_control(struct bios_parser *bp);
-static void init_blank_crtc(struct bios_parser *bp);
static void init_set_crtc_timing(struct bios_parser *bp);
static void init_select_crtc_source(struct bios_parser *bp);
static void init_enable_crtc(struct bios_parser *bp);
static void init_enable_crtc_mem_req(struct bios_parser *bp);
-static void init_compute_memore_engine_pll(struct bios_parser *bp);
static void init_external_encoder_control(struct bios_parser *bp);
static void init_enable_disp_power_gating(struct bios_parser *bp);
static void init_program_clock(struct bios_parser *bp);
@@ -74,13 +72,11 @@ void dal_bios_parser_init_cmd_tbl(struct bios_parser *bp)
init_adjust_display_pll(bp);
init_dac_encoder_control(bp);
init_dac_output_control(bp);
- init_blank_crtc(bp);
init_set_crtc_timing(bp);
init_select_crtc_source(bp);
init_enable_crtc(bp);
init_enable_crtc_mem_req(bp);
init_program_clock(bp);
- init_compute_memore_engine_pll(bp);
init_external_encoder_control(bp);
init_enable_disp_power_gating(bp);
init_set_dce_clock(bp);
@@ -1676,66 +1672,6 @@ static enum bp_result dac2_output_control_v1(
/*******************************************************************************
********************************************************************************
**
- ** BLANK CRTC
- **
- ********************************************************************************
- *******************************************************************************/
-
-static enum bp_result blank_crtc_v1(
- struct bios_parser *bp,
- struct bp_blank_crtc_parameters *bp_params,
- bool blank);
-
-static void init_blank_crtc(struct bios_parser *bp)
-{
- switch (BIOS_CMD_TABLE_PARA_REVISION(BlankCRTC)) {
- case 1:
- bp->cmd_tbl.blank_crtc = blank_crtc_v1;
- break;
- default:
- bp->cmd_tbl.blank_crtc = NULL;
- break;
- }
-}
-
-static enum bp_result blank_crtc_v1(
- struct bios_parser *bp,
- struct bp_blank_crtc_parameters *bp_params,
- bool blank)
-{
- enum bp_result result = BP_RESULT_FAILURE;
- BLANK_CRTC_PARAMETERS params = {0};
- uint8_t atom_controller_id;
-
- if (bp->cmd_helper->controller_id_to_atom(bp_params->controller_id,
- &atom_controller_id)) {
- params.ucCRTC = (uint8_t)atom_controller_id;
-
- if (blank)
- params.ucBlanking = ATOM_BLANKING;
- else
- params.ucBlanking = ATOM_BLANKING_OFF;
- params.usBlackColorRCr =
- cpu_to_le16((uint16_t)bp_params->black_color_rcr);
- params.usBlackColorGY =
- cpu_to_le16((uint16_t)bp_params->black_color_gy);
- params.usBlackColorBCb =
- cpu_to_le16((uint16_t)bp_params->black_color_bcb);
-
- if (EXEC_BIOS_CMD_TABLE(BlankCRTC, params))
- result = BP_RESULT_OK;
- } else
- /* Not support more than two CRTC as current ASIC, update this
- * if needed.
- */
- result = BP_RESULT_BADINPUT;
-
- return result;
-}
-
-/*******************************************************************************
- ********************************************************************************
- **
** SET CRTC TIMING
**
********************************************************************************
@@ -2242,56 +2178,6 @@ static enum bp_result program_clock_v6(
/*******************************************************************************
********************************************************************************
**
- ** COMPUTE MEMORY ENGINE PLL
- **
- ********************************************************************************
- *******************************************************************************/
-
-static enum bp_result compute_memore_engine_pll_v4(
- struct bios_parser *bp,
- struct bp_display_clock_parameters *bp_params);
-
-static void init_compute_memore_engine_pll(struct bios_parser *bp)
-{
- switch (BIOS_CMD_TABLE_PARA_REVISION(ComputeMemoryEnginePLL)) {
- case 4:
- bp->cmd_tbl.compute_memore_engine_pll =
- compute_memore_engine_pll_v4;
- break;
- default:
- bp->cmd_tbl.compute_memore_engine_pll = NULL;
- break;
- }
-}
-
-static enum bp_result compute_memore_engine_pll_v4(
- struct bios_parser *bp,
- struct bp_display_clock_parameters *bp_params)
-{
- enum bp_result result = BP_RESULT_FAILURE;
- COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 params;
-
- memset(¶ms, 0, sizeof(params));
-
- params.ulClock = cpu_to_le32(bp_params->target_display_clock / 10);
-
- /* Initialize this to the target clock in case this call fails */
- bp_params->actual_display_clock = bp_params->target_display_clock;
-
- if (EXEC_BIOS_CMD_TABLE(ComputeMemoryEnginePLL, params)) {
- /* Convert from 10KHz units back to KHz */
- bp_params->actual_display_clock =
- le32_to_cpu(params.ulClock) * 10;
- bp_params->actual_post_divider_id = params.ucPostDiv;
- result = BP_RESULT_OK;
- }
-
- return result;
-}
-
-/*******************************************************************************
- ********************************************************************************
- **
** EXTERNAL ENCODER CONTROL
**
********************************************************************************
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table.h b/drivers/gpu/drm/amd/display/dc/bios/command_table.h
index b8e6ef06c0c7..94f3d43a7471 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table.h
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table.h
@@ -68,10 +68,6 @@ struct cmd_tbl {
enum bp_result (*dac2_output_control)(
struct bios_parser *bp,
bool enable);
- enum bp_result (*blank_crtc)(
- struct bios_parser *bp,
- struct bp_blank_crtc_parameters *bp_params,
- bool blank);
enum bp_result (*set_crtc_timing)(
struct bios_parser *bp,
struct bp_hw_crtc_timing_parameters *bp_params);
@@ -89,9 +85,6 @@ struct cmd_tbl {
enum bp_result (*program_clock)(
struct bios_parser *bp,
struct bp_pixel_clock_parameters *bp_params);
- enum bp_result (*compute_memore_engine_pll)(
- struct bios_parser *bp,
- struct bp_display_clock_parameters *bp_params);
enum bp_result (*external_encoder_control)(
struct bios_parser *bp,
struct bp_external_encoder_control *cntl);
diff --git a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h
index 790c5bd51cb9..6e1291d5f51d 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h
@@ -51,12 +51,6 @@ struct dc_vbios_funcs {
struct dc_bios *bios,
struct graphics_object_id id);
- uint32_t (*get_gpio_record)(
- struct dc_bios *dcb,
- struct graphics_object_id id,
- struct bp_gpio_cntl_info *gpio_record,
- uint32_t record_size);
-
enum bp_result (*get_src_obj)(
struct dc_bios *bios,
struct graphics_object_id object_id, uint32_t index,
diff --git a/drivers/gpu/drm/amd/display/include/bios_parser_types.h b/drivers/gpu/drm/amd/display/include/bios_parser_types.h
index 7de4fa5a0726..0840f69cde99 100644
--- a/drivers/gpu/drm/amd/display/include/bios_parser_types.h
+++ b/drivers/gpu/drm/amd/display/include/bios_parser_types.h
@@ -156,13 +156,6 @@ struct bp_transmitter_control {
bool single_pll_mode;
};
-struct bp_blank_crtc_parameters {
- enum controller_id controller_id;
- uint32_t black_color_rcr;
- uint32_t black_color_gy;
- uint32_t black_color_bcb;
-};
-
struct bp_hw_crtc_timing_parameters {
enum controller_id controller_id;
/* horizontal part */
@@ -252,14 +245,6 @@ struct bp_pixel_clock_parameters {
} flags;
};
-struct bp_display_clock_parameters {
- uint32_t target_display_clock; /* KHz */
- /* Actual Display Clock set due to clock divider granularity KHz */
- uint32_t actual_display_clock;
- /* Actual Post Divider ID used to generate the actual clock */
- uint32_t actual_post_divider_id;
-};
-
enum bp_dce_clock_type {
DCECLOCK_TYPE_DISPLAY_CLOCK = 0,
DCECLOCK_TYPE_DPREFCLK = 1
@@ -322,9 +307,4 @@ struct bp_encoder_cap_info {
uint32_t RESERVED:30;
};
-struct bp_gpio_cntl_info {
- uint32_t id;
- enum gpio_pin_output_state state;
-};
-
#endif /*__DAL_BIOS_PARSER_TYPES_H__ */
--
2.9.3
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 14/25] drm/amd/display: remove calculate_adjustments in conversion.h
[not found] ` <20170123143613.15441-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (12 preceding siblings ...)
2017-01-23 14:36 ` [PATCH 13/25] drm/amd/display: remove dead code Harry Wentland
@ 2017-01-23 14:36 ` Harry Wentland
2017-01-23 14:36 ` [PATCH 15/25] drm/amd/display: Set default degamma to sRGB instead of bypass Harry Wentland
` (10 subsequent siblings)
24 siblings, 0 replies; 27+ messages in thread
From: Harry Wentland @ 2017-01-23 14:36 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tony Cheng
From: Tony Cheng <tony.cheng@amd.com>
- these are moved to color module
Change-Id: I2131991772553893b91ba9b927d20306e846141b
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
---
drivers/gpu/drm/amd/display/dc/basics/conversion.c | 118 ---------------------
drivers/gpu/drm/amd/display/dc/basics/conversion.h | 10 --
2 files changed, 128 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/basics/conversion.c b/drivers/gpu/drm/amd/display/dc/basics/conversion.c
index 5682fea2080d..a2e22ae12adb 100644
--- a/drivers/gpu/drm/amd/display/dc/basics/conversion.c
+++ b/drivers/gpu/drm/amd/display/dc/basics/conversion.c
@@ -103,124 +103,6 @@ void convert_float_matrix(
}
}
-static void calculate_adjustments_common(
- const struct fixed31_32 *ideal_matrix,
- const struct dc_csc_adjustments *adjustments,
- struct fixed31_32 *matrix)
-{
- const struct fixed31_32 sin_hue =
- dal_fixed31_32_sin(adjustments->hue);
- const struct fixed31_32 cos_hue =
- dal_fixed31_32_cos(adjustments->hue);
-
- const struct fixed31_32 multiplier =
- dal_fixed31_32_mul(
- adjustments->contrast,
- adjustments->saturation);
-
- matrix[0] = dal_fixed31_32_mul(
- ideal_matrix[0],
- adjustments->contrast);
-
- matrix[1] = dal_fixed31_32_mul(
- ideal_matrix[1],
- adjustments->contrast);
-
- matrix[2] = dal_fixed31_32_mul(
- ideal_matrix[2],
- adjustments->contrast);
-
- matrix[4] = dal_fixed31_32_mul(
- multiplier,
- dal_fixed31_32_add(
- dal_fixed31_32_mul(
- ideal_matrix[8],
- sin_hue),
- dal_fixed31_32_mul(
- ideal_matrix[4],
- cos_hue)));
-
- matrix[5] = dal_fixed31_32_mul(
- multiplier,
- dal_fixed31_32_add(
- dal_fixed31_32_mul(
- ideal_matrix[9],
- sin_hue),
- dal_fixed31_32_mul(
- ideal_matrix[5],
- cos_hue)));
-
- matrix[6] = dal_fixed31_32_mul(
- multiplier,
- dal_fixed31_32_add(
- dal_fixed31_32_mul(
- ideal_matrix[10],
- sin_hue),
- dal_fixed31_32_mul(
- ideal_matrix[6],
- cos_hue)));
-
- matrix[7] = ideal_matrix[7];
-
- matrix[8] = dal_fixed31_32_mul(
- multiplier,
- dal_fixed31_32_sub(
- dal_fixed31_32_mul(
- ideal_matrix[8],
- cos_hue),
- dal_fixed31_32_mul(
- ideal_matrix[4],
- sin_hue)));
-
- matrix[9] = dal_fixed31_32_mul(
- multiplier,
- dal_fixed31_32_sub(
- dal_fixed31_32_mul(
- ideal_matrix[9],
- cos_hue),
- dal_fixed31_32_mul(
- ideal_matrix[5],
- sin_hue)));
-
- matrix[10] = dal_fixed31_32_mul(
- multiplier,
- dal_fixed31_32_sub(
- dal_fixed31_32_mul(
- ideal_matrix[10],
- cos_hue),
- dal_fixed31_32_mul(
- ideal_matrix[6],
- sin_hue)));
-
- matrix[11] = ideal_matrix[11];
-}
-
-void calculate_adjustments(
- const struct fixed31_32 *ideal_matrix,
- const struct dc_csc_adjustments *adjustments,
- struct fixed31_32 *matrix)
-{
- calculate_adjustments_common(ideal_matrix, adjustments, matrix);
-
- matrix[3] = dal_fixed31_32_add(
- ideal_matrix[3],
- dal_fixed31_32_mul(
- adjustments->brightness,
- dal_fixed31_32_from_fraction(86, 100)));
-}
-
-void calculate_adjustments_y_only(
- const struct fixed31_32 *ideal_matrix,
- const struct dc_csc_adjustments *adjustments,
- struct fixed31_32 *matrix)
-{
- calculate_adjustments_common(ideal_matrix, adjustments, matrix);
-
- matrix[3] = dal_fixed31_32_add(
- ideal_matrix[3],
- adjustments->brightness);
-}
-
unsigned int log_2(unsigned int num)
{
unsigned int result = 0;
diff --git a/drivers/gpu/drm/amd/display/dc/basics/conversion.h b/drivers/gpu/drm/amd/display/dc/basics/conversion.h
index b7fe431a7952..189325f68cfd 100644
--- a/drivers/gpu/drm/amd/display/dc/basics/conversion.h
+++ b/drivers/gpu/drm/amd/display/dc/basics/conversion.h
@@ -38,16 +38,6 @@ void convert_float_matrix(
struct fixed31_32 *flt,
uint32_t buffer_size);
-void calculate_adjustments(
- const struct fixed31_32 *ideal_matrix,
- const struct dc_csc_adjustments *adjustments,
- struct fixed31_32 *matrix);
-
-void calculate_adjustments_y_only(
- const struct fixed31_32 *ideal_matrix,
- const struct dc_csc_adjustments *adjustments,
- struct fixed31_32 *matrix);
-
unsigned int log_2(unsigned int num);
#endif
--
2.9.3
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 15/25] drm/amd/display: Set default degamma to sRGB instead of bypass
[not found] ` <20170123143613.15441-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (13 preceding siblings ...)
2017-01-23 14:36 ` [PATCH 14/25] drm/amd/display: remove calculate_adjustments in conversion.h Harry Wentland
@ 2017-01-23 14:36 ` Harry Wentland
2017-01-23 14:36 ` [PATCH 16/25] drm/amd/display: HDR Enablement For Applications Harry Wentland
` (9 subsequent siblings)
24 siblings, 0 replies; 27+ messages in thread
From: Harry Wentland @ 2017-01-23 14:36 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Amy Zhang
From: Amy Zhang <Amy.Zhang@amd.com>
Change-Id: I572a114be92e8d1e92780793ffdc0644c805c36e
Signed-off-by: Amy Zhang <Amy.Zhang@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
---
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index b51668e3bb52..ee393a168c84 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -255,7 +255,7 @@ static bool dce110_set_input_transfer_func(
if (tf == NULL) {
/* Default case if no input transfer function specified */
ipp->funcs->ipp_set_degamma(ipp,
- IPP_DEGAMMA_MODE_BYPASS);
+ IPP_DEGAMMA_MODE_HW_sRGB);
} else if (tf->public.type == TF_TYPE_PREDEFINED) {
switch (tf->public.tf) {
case TRANSFER_FUNCTION_SRGB:
--
2.9.3
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 16/25] drm/amd/display: HDR Enablement For Applications
[not found] ` <20170123143613.15441-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (14 preceding siblings ...)
2017-01-23 14:36 ` [PATCH 15/25] drm/amd/display: Set default degamma to sRGB instead of bypass Harry Wentland
@ 2017-01-23 14:36 ` Harry Wentland
2017-01-23 14:36 ` [PATCH 17/25] drm/amd/display: refactor clk_resync to avoid assertion Harry Wentland
` (8 subsequent siblings)
24 siblings, 0 replies; 27+ messages in thread
From: Harry Wentland @ 2017-01-23 14:36 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Amy Zhang
From: Amy Zhang <Amy.Zhang@amd.com>
- Made sure dest color space is updated in stream and info frame
- Optimized segment distribution algorithm for regamma mapping
Change-Id: Ia9bb4e56719e23a9827080194d89f715ee5fde29
Signed-off-by: Amy Zhang <Amy.Zhang@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 14 ++++
drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 6 +-
.../amd/display/dc/dce110/dce110_hw_sequencer.c | 94 ++++++++++++++++++----
drivers/gpu/drm/amd/display/dc/inc/hw/transform.h | 11 +++
4 files changed, 107 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index fe79a2890247..8b41c7708562 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1310,6 +1310,20 @@ static void set_avi_info_frame(
info_frame.avi_info_packet.info_packet_hdmi.bits.C0_C1 =
COLORIMETRY_NO_DATA;
+ if (color_space == COLOR_SPACE_2020_RGB_FULLRANGE ||
+ color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE ||
+ color_space == COLOR_SPACE_2020_YCBCR) {
+ info_frame.avi_info_packet.info_packet_hdmi.bits.EC0_EC2 =
+ COLORIMETRYEX_BT2020RGBYCBCR;
+ info_frame.avi_info_packet.info_packet_hdmi.bits.C0_C1 =
+ COLORIMETRY_EXTENDED;
+ } else if (color_space == COLOR_SPACE_ADOBERGB) {
+ info_frame.avi_info_packet.info_packet_hdmi.bits.EC0_EC2 =
+ COLORIMETRYEX_ADOBERGB;
+ info_frame.avi_info_packet.info_packet_hdmi.bits.C0_C1 =
+ COLORIMETRY_EXTENDED;
+ }
+
/* TODO: un-hardcode aspect ratio */
aspect = stream->public.timing.aspect_ratio;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index 00958bdbb417..a17e7bc96f9e 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -444,7 +444,11 @@ enum dc_color_space {
COLOR_SPACE_YCBCR601,
COLOR_SPACE_YCBCR709,
COLOR_SPACE_YCBCR601_LIMITED,
- COLOR_SPACE_YCBCR709_LIMITED
+ COLOR_SPACE_YCBCR709_LIMITED,
+ COLOR_SPACE_2020_RGB_FULLRANGE,
+ COLOR_SPACE_2020_RGB_LIMITEDRANGE,
+ COLOR_SPACE_2020_YCBCR,
+ COLOR_SPACE_ADOBERGB,
};
enum dc_quantization_range {
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index ee393a168c84..e9fd83e9af79 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -594,39 +594,88 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func
struct fixed31_32 y3_max;
int32_t segment_start, segment_end;
- uint32_t hw_points, start_index;
- uint32_t i, j;
+ uint32_t i, j, k, seg_distr[16], increment, start_index;
+ uint32_t hw_points = 0;
memset(regamma_params, 0, sizeof(struct pwl_params));
if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
- /* 16 segments x 16 points
+ /* 16 segments
* segments are from 2^-11 to 2^5
*/
segment_start = -11;
segment_end = 5;
+ seg_distr[0] = 2;
+ seg_distr[1] = 2;
+ seg_distr[2] = 2;
+ seg_distr[3] = 2;
+ seg_distr[4] = 2;
+ seg_distr[5] = 2;
+ seg_distr[6] = 3;
+ seg_distr[7] = 4;
+ seg_distr[8] = 4;
+ seg_distr[9] = 4;
+ seg_distr[10] = 4;
+ seg_distr[11] = 5;
+ seg_distr[12] = 5;
+ seg_distr[13] = 5;
+ seg_distr[14] = 5;
+ seg_distr[15] = 5;
+
} else {
- /* 10 segments x 16 points
+ /* 10 segments
* segment is from 2^-10 to 2^0
*/
segment_start = -10;
segment_end = 0;
+
+ seg_distr[0] = 3;
+ seg_distr[1] = 4;
+ seg_distr[2] = 4;
+ seg_distr[3] = 4;
+ seg_distr[4] = 4;
+ seg_distr[5] = 4;
+ seg_distr[6] = 4;
+ seg_distr[7] = 4;
+ seg_distr[8] = 5;
+ seg_distr[9] = 5;
+ seg_distr[10] = -1;
+ seg_distr[11] = -1;
+ seg_distr[12] = -1;
+ seg_distr[13] = -1;
+ seg_distr[14] = -1;
+ seg_distr[15] = -1;
+ }
+
+ for (k = 0; k < 16; k++) {
+ if (seg_distr[k] != -1)
+ hw_points += (1 << seg_distr[k]);
}
- hw_points = (segment_end - segment_start) * 16;
j = 0;
- /* (segment + 25) * 32, every 2nd point */
- start_index = (segment_start + 25) * 32;
- for (i = start_index; i <= 1025; i += 2) {
- if (j > hw_points)
- break;
- rgb_resulted[j].red = output_tf->tf_pts.red[i];
- rgb_resulted[j].green = output_tf->tf_pts.green[i];
- rgb_resulted[j].blue = output_tf->tf_pts.blue[i];
- j++;
+ for (k = 0; k < (segment_end - segment_start); k++) {
+ increment = 32 / (1 << seg_distr[k]);
+ start_index = (segment_start + k + 25) * 32;
+ for (i = start_index; i < start_index + 32; i += increment) {
+ if (j == hw_points - 1)
+ break;
+ rgb_resulted[j].red = output_tf->tf_pts.red[i];
+ rgb_resulted[j].green = output_tf->tf_pts.green[i];
+ rgb_resulted[j].blue = output_tf->tf_pts.blue[i];
+ j++;
+ }
}
+ /* last point */
+ start_index = (segment_end + 25) * 32;
+ rgb_resulted[hw_points - 1].red =
+ output_tf->tf_pts.red[start_index];
+ rgb_resulted[hw_points - 1].green =
+ output_tf->tf_pts.green[start_index];
+ rgb_resulted[hw_points - 1].blue =
+ output_tf->tf_pts.blue[start_index];
+
arr_points[0].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
dal_fixed31_32_from_int(segment_start));
arr_points[1].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
@@ -677,11 +726,22 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func
regamma_params->hw_points_num = hw_points;
- for (i = 0; i < segment_end - segment_start; i++) {
- regamma_params->arr_curve_points[i].offset = i * 16;
- regamma_params->arr_curve_points[i].segments_num = 4;
+ i = 1;
+ for (k = 0; k < 16 && i < 16; k++) {
+ if (seg_distr[k] != -1) {
+ regamma_params->arr_curve_points[k].segments_num =
+ seg_distr[k];
+ regamma_params->arr_curve_points[i].offset =
+ regamma_params->arr_curve_points[k].
+ offset + (1 << seg_distr[k]);
+ }
+ i++;
}
+ if (seg_distr[k] != -1)
+ regamma_params->arr_curve_points[k].segments_num =
+ seg_distr[k];
+
struct pwl_result_data *rgb = rgb_resulted;
struct pwl_result_data *rgb_plus_1 = rgb_resulted + 1;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h
index ef743b70b3e9..a510d3fe48ec 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h
@@ -47,6 +47,17 @@ enum colorimetry {
COLORIMETRY_EXTENDED = 3
};
+enum colorimetry_ext {
+ COLORIMETRYEX_XVYCC601 = 0,
+ COLORIMETRYEX_XVYCC709 = 1,
+ COLORIMETRYEX_SYCC601 = 2,
+ COLORIMETRYEX_ADOBEYCC601 = 3,
+ COLORIMETRYEX_ADOBERGB = 4,
+ COLORIMETRYEX_BT2020YCC = 5,
+ COLORIMETRYEX_BT2020RGBYCBCR = 6,
+ COLORIMETRYEX_RESERVED = 7
+};
+
enum active_format_info {
ACTIVE_FORMAT_NO_DATA = 0,
ACTIVE_FORMAT_VALID = 1
--
2.9.3
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 17/25] drm/amd/display: refactor clk_resync to avoid assertion
[not found] ` <20170123143613.15441-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (15 preceding siblings ...)
2017-01-23 14:36 ` [PATCH 16/25] drm/amd/display: HDR Enablement For Applications Harry Wentland
@ 2017-01-23 14:36 ` Harry Wentland
2017-01-23 14:36 ` [PATCH 18/25] drm/amd/display: Remove meta_pitch Harry Wentland
` (7 subsequent siblings)
24 siblings, 0 replies; 27+ messages in thread
From: Harry Wentland @ 2017-01-23 14:36 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tony Cheng
From: Tony Cheng <tony.cheng@amd.com>
- not all DCE has PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE bit defined.
Change-Id: I4bf25deb134637c713ac5ee1eac786bafdc9eb4a
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
---
.../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 57 ++++++++++++----------
1 file changed, 30 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
index a38172bdcb5e..78f43274a03a 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
@@ -767,41 +767,44 @@ static void dce112_program_pixel_clk_resync(
enum dc_color_depth colordepth,
bool enable_ycbcr420)
{
- REG_UPDATE(PIXCLK_RESYNC_CNTL,
- PHYPLLA_DCCG_DEEP_COLOR_CNTL, 0);
+ uint32_t deep_color_cntl = 0;
+ uint32_t double_rate_enable = 0;
+
/*
24 bit mode: TMDS clock = 1.0 x pixel clock (1:1)
30 bit mode: TMDS clock = 1.25 x pixel clock (5:4)
36 bit mode: TMDS clock = 1.5 x pixel clock (3:2)
48 bit mode: TMDS clock = 2 x pixel clock (2:1)
*/
- if (signal_type != SIGNAL_TYPE_HDMI_TYPE_A)
- return;
+ if (signal_type == SIGNAL_TYPE_HDMI_TYPE_A) {
+ double_rate_enable = enable_ycbcr420 ? 1 : 0;
- switch (colordepth) {
- case COLOR_DEPTH_888:
- REG_UPDATE_2(PIXCLK_RESYNC_CNTL,
- PHYPLLA_DCCG_DEEP_COLOR_CNTL, 0,
- PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, enable_ycbcr420);
- break;
- case COLOR_DEPTH_101010:
- REG_UPDATE_2(PIXCLK_RESYNC_CNTL,
- PHYPLLA_DCCG_DEEP_COLOR_CNTL, 1,
- PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, enable_ycbcr420);
- break;
- case COLOR_DEPTH_121212:
- REG_UPDATE_2(PIXCLK_RESYNC_CNTL,
- PHYPLLA_DCCG_DEEP_COLOR_CNTL, 2,
- PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, enable_ycbcr420);
- break;
- case COLOR_DEPTH_161616:
- REG_UPDATE_2(PIXCLK_RESYNC_CNTL,
- PHYPLLA_DCCG_DEEP_COLOR_CNTL, 3,
- PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, enable_ycbcr420);
- break;
- default:
- break;
+ switch (colordepth) {
+ case COLOR_DEPTH_888:
+ deep_color_cntl = 0;
+ break;
+ case COLOR_DEPTH_101010:
+ deep_color_cntl = 1;
+ break;
+ case COLOR_DEPTH_121212:
+ deep_color_cntl = 2;
+ break;
+ case COLOR_DEPTH_161616:
+ deep_color_cntl = 3;
+ break;
+ default:
+ break;
+ }
}
+
+ if (clk_src->cs_mask->PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE)
+ REG_UPDATE_2(PIXCLK_RESYNC_CNTL,
+ PHYPLLA_DCCG_DEEP_COLOR_CNTL, deep_color_cntl,
+ PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, double_rate_enable);
+ else
+ REG_UPDATE(PIXCLK_RESYNC_CNTL,
+ PHYPLLA_DCCG_DEEP_COLOR_CNTL, deep_color_cntl);
+
}
static bool dce110_program_pix_clk(
--
2.9.3
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^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 18/25] drm/amd/display: Remove meta_pitch
[not found] ` <20170123143613.15441-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (16 preceding siblings ...)
2017-01-23 14:36 ` [PATCH 17/25] drm/amd/display: refactor clk_resync to avoid assertion Harry Wentland
@ 2017-01-23 14:36 ` Harry Wentland
2017-01-23 14:36 ` [PATCH 19/25] drm/amd/display: rename BGRA8888 to ABGR8888 Harry Wentland
` (6 subsequent siblings)
24 siblings, 0 replies; 27+ messages in thread
From: Harry Wentland @ 2017-01-23 14:36 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Dmytro Laktyushkin
From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Change-Id: I2e7e1531259f1d58c2d4dc02817f0ad6e8104f19
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 8 ++------
drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 4 ----
2 files changed, 2 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
index 78b8e0c5b4e7..959c3f372e73 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
@@ -94,14 +94,12 @@ void pre_surface_trace(
"surface->plane_size.grph.surface_size.y = %d;\n"
"surface->plane_size.grph.surface_size.width = %d;\n"
"surface->plane_size.grph.surface_size.height = %d;\n"
- "surface->plane_size.grph.surface_pitch = %d;\n"
- "surface->plane_size.grph.meta_pitch = %d;\n",
+ "surface->plane_size.grph.surface_pitch = %d;\n",
surface->plane_size.grph.surface_size.x,
surface->plane_size.grph.surface_size.y,
surface->plane_size.grph.surface_size.width,
surface->plane_size.grph.surface_size.height,
- surface->plane_size.grph.surface_pitch,
- surface->plane_size.grph.meta_pitch);
+ surface->plane_size.grph.surface_pitch);
SURFACE_TRACE(
@@ -176,7 +174,6 @@ void update_surface_trace(
SURFACE_TRACE(
"plane_info->color_space = %d;\n"
"plane_info->format = %d;\n"
- "plane_info->plane_size.grph.meta_pitch = %d;\n"
"plane_info->plane_size.grph.surface_pitch = %d;\n"
"plane_info->plane_size.grph.surface_size.height = %d;\n"
"plane_info->plane_size.grph.surface_size.width = %d;\n"
@@ -185,7 +182,6 @@ void update_surface_trace(
"plane_info->rotation = %d;\n",
update->plane_info->color_space,
update->plane_info->format,
- update->plane_info->plane_size.grph.meta_pitch,
update->plane_info->plane_size.grph.surface_pitch,
update->plane_info->plane_size.grph.surface_size.height,
update->plane_info->plane_size.grph.surface_size.width,
diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index a17e7bc96f9e..5c1b2f833fe2 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -123,8 +123,6 @@ union plane_size {
* is 32 pixel aligned.
*/
uint32_t surface_pitch;
-
- uint32_t meta_pitch;
} grph;
struct {
@@ -134,7 +132,6 @@ union plane_size {
* 32 pixel aligned.
*/
uint32_t luma_pitch;
- uint32_t meta_luma_pitch;
struct rect chroma_size;
/* Graphic surface pitch in pixels.
@@ -142,7 +139,6 @@ union plane_size {
* 32 pixel aligned.
*/
uint32_t chroma_pitch;
- uint32_t meta_chroma_pitch;
} video;
};
--
2.9.3
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^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 19/25] drm/amd/display: rename BGRA8888 to ABGR8888
[not found] ` <20170123143613.15441-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (17 preceding siblings ...)
2017-01-23 14:36 ` [PATCH 18/25] drm/amd/display: Remove meta_pitch Harry Wentland
@ 2017-01-23 14:36 ` Harry Wentland
2017-01-23 14:36 ` [PATCH 20/25] drm/amd/display: Fix missing conditions in hw sequencer Harry Wentland
` (5 subsequent siblings)
24 siblings, 0 replies; 27+ messages in thread
From: Harry Wentland @ 2017-01-23 14:36 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tony Cheng
From: Tony Cheng <tony.cheng@amd.com>
DC actually support ABGR8888 instead of BGRA8888 (R/B swap rather than endian swap) ,
rename to avoid confusion
Change-Id: Ib0e30df605268b2d4567dd21e3e6a9db48471f92
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
---
drivers/gpu/drm/amd/display/dc/calcs/bandwidth_calcs.c | 4 ++--
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2 +-
drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 2 +-
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 4 ++--
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 2 +-
drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c | 2 +-
6 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/bandwidth_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/bandwidth_calcs.c
index 54388c0e29e0..946379852b2a 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/bandwidth_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/bandwidth_calcs.c
@@ -2530,7 +2530,7 @@ static void populate_initial_data(
data->bytes_per_pixel[num_displays + 4] = 2;
break;
case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
- case SURFACE_PIXEL_FORMAT_GRPH_BGRA8888:
+ case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
@@ -2626,7 +2626,7 @@ static void populate_initial_data(
data->bytes_per_pixel[num_displays + 4] = 2;
break;
case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
- case SURFACE_PIXEL_FORMAT_GRPH_BGRA8888:
+ case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 8b41c7708562..ee1c3b029394 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -341,7 +341,7 @@ static enum pixel_format convert_pixel_format_to_dalsurface(
case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
dal_pixel_format = PIXEL_FORMAT_ARGB8888;
break;
- case SURFACE_PIXEL_FORMAT_GRPH_BGRA8888:
+ case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
dal_pixel_format = PIXEL_FORMAT_ARGB8888;
break;
case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index 5c1b2f833fe2..53c73de75da9 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -174,7 +174,7 @@ enum surface_pixel_format {
/*32 bpp*/
SURFACE_PIXEL_FORMAT_GRPH_ARGB8888,
/*32 bpp swaped*/
- SURFACE_PIXEL_FORMAT_GRPH_BGRA8888,
+ SURFACE_PIXEL_FORMAT_GRPH_ABGR8888,
SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010,
/*swaped*/
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
index 130935fffba3..e14a21cedfd5 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
@@ -302,7 +302,7 @@ static void program_grph_pixel_format(
uint32_t grph_depth, grph_format;
uint32_t sign = 0, floating = 0;
- if (format == SURFACE_PIXEL_FORMAT_GRPH_BGRA8888 ||
+ if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR8888 ||
/*todo: doesn't look like we handle BGRA here,
* should problem swap endian*/
format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010 ||
@@ -331,7 +331,7 @@ static void program_grph_pixel_format(
grph_format = 1;
break;
case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
- case SURFACE_PIXEL_FORMAT_GRPH_BGRA8888:
+ case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
grph_depth = 2;
grph_format = 0;
break;
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index e9fd83e9af79..6dbfc570b8c6 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -214,7 +214,7 @@ static void build_prescale_params(struct ipp_prescale_params *prescale_params,
switch (surface->public.format) {
case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
- case SURFACE_PIXEL_FORMAT_GRPH_BGRA8888:
+ case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
prescale_params->scale = 0x2020;
break;
case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
index b12506adcba4..aac47955e9bf 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
@@ -405,7 +405,7 @@ static void program_pixel_format(
grph_format = 1;
break;
case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
- case SURFACE_PIXEL_FORMAT_GRPH_BGRA8888:
+ case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
grph_depth = 2;
grph_format = 0;
break;
--
2.9.3
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 20/25] drm/amd/display: Fix missing conditions in hw sequencer.
[not found] ` <20170123143613.15441-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (18 preceding siblings ...)
2017-01-23 14:36 ` [PATCH 19/25] drm/amd/display: rename BGRA8888 to ABGR8888 Harry Wentland
@ 2017-01-23 14:36 ` Harry Wentland
2017-01-23 14:36 ` [PATCH 21/25] drm/amd/display: Add missing MI masks Harry Wentland
` (4 subsequent siblings)
24 siblings, 0 replies; 27+ messages in thread
From: Harry Wentland @ 2017-01-23 14:36 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Zeyu Fan
From: Zeyu Fan <Zeyu.Fan@amd.com>
Change-Id: I621c2356319229c5e455d2fd6ccbedc4a74077ae
Signed-off-by: Zeyu Fan <Zeyu.Fan@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
index cd9a371ae237..0eee135bfa54 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
@@ -160,7 +160,7 @@ void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws,
struct clock_source *clk_src,
unsigned int tg_inst)
{
- if (clk_src->id == CLOCK_SOURCE_ID_DP_DTO) {
+ if (clk_src->id == CLOCK_SOURCE_ID_DP_DTO || clk_src->dp_clk_src) {
REG_UPDATE(PIXEL_RATE_CNTL[tg_inst],
DP_DTO0_ENABLE, 1);
--
2.9.3
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 21/25] drm/amd/display: Add missing MI masks
[not found] ` <20170123143613.15441-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (19 preceding siblings ...)
2017-01-23 14:36 ` [PATCH 20/25] drm/amd/display: Fix missing conditions in hw sequencer Harry Wentland
@ 2017-01-23 14:36 ` Harry Wentland
2017-01-23 14:36 ` [PATCH 22/25] drm/amd/display: Add interrupt entries for VBLANK isr Harry Wentland
` (3 subsequent siblings)
24 siblings, 0 replies; 27+ messages in thread
From: Harry Wentland @ 2017-01-23 14:36 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Leon Elazar
From: Leon Elazar <leon.elazar@amd.com>
This will fix the memory Input programing with MST tiled display.
This Fix should fix connectivity problems with MST tiled Display
Change-Id: I2cf36a325a44edd4198e30f9fc801208399e1a83
Signed-off-by: Leon Elazar <leon.elazar@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
index f90d586656ef..ec053c241901 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
@@ -92,6 +92,8 @@ struct dce_mem_input_registers {
.field_name = blk_name ## reg_name ## __ ## field_name ## post_fix
#define MI_GFX8_TILE_MASK_SH_LIST(mask_sh, blk)\
+ SFB(blk, GRPH_CONTROL, GRPH_NUM_BANKS, mask_sh),\
+ SFB(blk, GRPH_CONTROL, GRPH_BANK_WIDTH, mask_sh),\
SFB(blk, GRPH_CONTROL, GRPH_BANK_HEIGHT, mask_sh),\
SFB(blk, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT, mask_sh),\
SFB(blk, GRPH_CONTROL, GRPH_TILE_SPLIT, mask_sh),\
--
2.9.3
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^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 22/25] drm/amd/display: Add interrupt entries for VBLANK isr.
[not found] ` <20170123143613.15441-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (20 preceding siblings ...)
2017-01-23 14:36 ` [PATCH 21/25] drm/amd/display: Add missing MI masks Harry Wentland
@ 2017-01-23 14:36 ` Harry Wentland
[not found] ` <20170123143613.15441-23-harry.wentland-5C7GfCeVMHo@public.gmane.org>
2017-01-23 14:36 ` [PATCH 23/25] drm/amd/display: Register on VLBLANK ISR Harry Wentland
` (2 subsequent siblings)
24 siblings, 1 reply; 27+ messages in thread
From: Harry Wentland @ 2017-01-23 14:36 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Andrey Grodzovsky
From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Change-Id: Ia59c22ea5a78d5eecca6c62c7f50e651f29ef5f7
Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
.../amd/display/dc/irq/dce110/irq_service_dce110.c | 42 ++++++++++++++++++++++
.../amd/display/dc/irq/dce80/irq_service_dce80.c | 22 ++++++++++++
drivers/gpu/drm/amd/display/dc/irq_types.h | 8 +++++
3 files changed, 72 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
index f3eda1b4eebf..4c7c85d45518 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
@@ -33,6 +33,13 @@
#include "dce/dce_11_0_sh_mask.h"
#include "ivsrcid/ivsrcid_vislands30.h"
+#define VISLANDS30_IV_SRCID_D1_VBLANK 1
+#define VISLANDS30_IV_SRCID_D2_VBLANK 2
+#define VISLANDS30_IV_SRCID_D3_VBLANK 3
+#define VISLANDS30_IV_SRCID_D4_VBLANK 4
+#define VISLANDS30_IV_SRCID_D5_VBLANK 5
+#define VISLANDS30_IV_SRCID_D6_VBLANK 6
+
static bool hpd_ack(
struct irq_service *irq_service,
const struct irq_source_info *info)
@@ -139,6 +146,22 @@ static const struct irq_source_info_funcs vblank_irq_info_funcs = {
.funcs = &vblank_irq_info_funcs\
}
+#define vblank_int_entry(reg_num)\
+ [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
+ .enable_reg = mmLB ## reg_num ## _LB_INTERRUPT_MASK,\
+ .enable_mask =\
+ LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK,\
+ .enable_value = {\
+ LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK,\
+ ~LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK},\
+ .ack_reg = mmLB ## reg_num ## _LB_VBLANK_STATUS,\
+ .ack_mask =\
+ LB_VBLANK_STATUS__VBLANK_ACK_MASK,\
+ .ack_value =\
+ LB_VBLANK_STATUS__VBLANK_ACK_MASK,\
+ .funcs = &vblank_irq_info_funcs\
+ }
+
#define dummy_irq_entry() \
{\
.funcs = &dummy_irq_info_funcs\
@@ -264,6 +287,13 @@ irq_source_info_dce110[DAL_IRQ_SOURCES_NUMBER] = {
vupdate_int_entry(3),
vupdate_int_entry(4),
vupdate_int_entry(5),
+ vblank_int_entry(0),
+ vblank_int_entry(1),
+ vblank_int_entry(2),
+ vblank_int_entry(3),
+ vblank_int_entry(4),
+ vblank_int_entry(5),
+
};
enum dc_irq_source to_dal_irq_source_dce110(
@@ -272,6 +302,18 @@ enum dc_irq_source to_dal_irq_source_dce110(
uint32_t ext_id)
{
switch (src_id) {
+ case VISLANDS30_IV_SRCID_D1_VBLANK:
+ return DC_IRQ_SOURCE_VBLANK1;
+ case VISLANDS30_IV_SRCID_D2_VBLANK:
+ return DC_IRQ_SOURCE_VBLANK2;
+ case VISLANDS30_IV_SRCID_D3_VBLANK:
+ return DC_IRQ_SOURCE_VBLANK3;
+ case VISLANDS30_IV_SRCID_D4_VBLANK:
+ return DC_IRQ_SOURCE_VBLANK4;
+ case VISLANDS30_IV_SRCID_D5_VBLANK:
+ return DC_IRQ_SOURCE_VBLANK5;
+ case VISLANDS30_IV_SRCID_D6_VBLANK:
+ return DC_IRQ_SOURCE_VBLANK6;
case VISLANDS30_IV_SRCID_D1_V_UPDATE_INT:
return DC_IRQ_SOURCE_VUPDATE1;
case VISLANDS30_IV_SRCID_D2_V_UPDATE_INT:
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c b/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
index 8b4f45389783..dd09d2b6d4a7 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
@@ -143,6 +143,22 @@ static const struct irq_source_info_funcs vblank_irq_info_funcs = {
.funcs = &vblank_irq_info_funcs\
}
+#define vblank_int_entry(reg_num)\
+ [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
+ .enable_reg = mmLB ## reg_num ## _LB_INTERRUPT_MASK,\
+ .enable_mask =\
+ LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK,\
+ .enable_value = {\
+ LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK,\
+ ~LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK},\
+ .ack_reg = mmLB ## reg_num ## _LB_VBLANK_STATUS,\
+ .ack_mask =\
+ LB_VBLANK_STATUS__VBLANK_ACK_MASK,\
+ .ack_value =\
+ LB_VBLANK_STATUS__VBLANK_ACK_MASK,\
+ .funcs = &vblank_irq_info_funcs\
+ }
+
#define dummy_irq_entry() \
{\
.funcs = &dummy_irq_info_funcs\
@@ -246,6 +262,12 @@ irq_source_info_dce80[DAL_IRQ_SOURCES_NUMBER] = {
vupdate_int_entry(3),
vupdate_int_entry(4),
vupdate_int_entry(5),
+ vblank_int_entry(0),
+ vblank_int_entry(1),
+ vblank_int_entry(2),
+ vblank_int_entry(3),
+ vblank_int_entry(4),
+ vblank_int_entry(5),
};
static const struct irq_service_funcs irq_service_funcs_dce80 = {
diff --git a/drivers/gpu/drm/amd/display/dc/irq_types.h b/drivers/gpu/drm/amd/display/dc/irq_types.h
index e4b4b99a86fc..a506c2e939f5 100644
--- a/drivers/gpu/drm/amd/display/dc/irq_types.h
+++ b/drivers/gpu/drm/amd/display/dc/irq_types.h
@@ -128,6 +128,13 @@ enum dc_irq_source {
DC_IRQ_SOURCE_VUPDATE5,
DC_IRQ_SOURCE_VUPDATE6,
+ DC_IRQ_SOURCE_VBLANK1,
+ DC_IRQ_SOURCE_VBLANK2,
+ DC_IRQ_SOURCE_VBLANK3,
+ DC_IRQ_SOURCE_VBLANK4,
+ DC_IRQ_SOURCE_VBLANK5,
+ DC_IRQ_SOURCE_VBLANK6,
+
DAL_IRQ_SOURCES_NUMBER
};
@@ -135,6 +142,7 @@ enum irq_type
{
IRQ_TYPE_PFLIP = DC_IRQ_SOURCE_PFLIP1,
IRQ_TYPE_VUPDATE = DC_IRQ_SOURCE_VUPDATE1,
+ IRQ_TYPE_VBLANK = DC_IRQ_SOURCE_VBLANK1,
};
#define DAL_VALID_IRQ_SRC_NUM(src) \
--
2.9.3
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^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 23/25] drm/amd/display: Register on VLBLANK ISR.
[not found] ` <20170123143613.15441-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (21 preceding siblings ...)
2017-01-23 14:36 ` [PATCH 22/25] drm/amd/display: Add interrupt entries for VBLANK isr Harry Wentland
@ 2017-01-23 14:36 ` Harry Wentland
2017-01-23 14:36 ` [PATCH 24/25] drm/amd/display: Clean index in irq init loop Harry Wentland
2017-01-23 14:36 ` [PATCH 25/25] drm/amd/display: add missing dcc update on flip call Harry Wentland
24 siblings, 0 replies; 27+ messages in thread
From: Harry Wentland @ 2017-01-23 14:36 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Andrey Grodzovsky
From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Switch from VUPDATE to VBLANK.
Change-Id: I8652e01091efe91c3c7ad71004d170af412da9f5
Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 13 +++++++------
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 2 +-
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c | 2 +-
3 files changed, 9 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index be8fad24cedb..a33e339991ec 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -207,7 +207,7 @@ static void dm_crtc_high_irq(void *interrupt_params)
uint8_t crtc_index = 0;
struct amdgpu_crtc *acrtc;
- acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);
+ acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
if (acrtc)
crtc_index = acrtc->crtc_id;
@@ -1032,9 +1032,10 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev)
* amdgpu_dm_irq_handler() will re-direct the interrupt to DC
* for acknowledging and handling. */
- for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT;
- i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {
- r = amdgpu_irq_add_id(adev, i, &adev->crtc_irq);
+ /* Use VBLANK interrupt */
+ for (i = 0; i < adev->mode_info.num_crtc; i++) {
+ r = amdgpu_irq_add_id(adev, i+1, &adev->crtc_irq);
+
if (r) {
DRM_ERROR("Failed to add crtc irq id!\n");
return r;
@@ -1042,9 +1043,9 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev)
int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
int_params.irq_source =
- dc_interrupt_to_irq_source(dc, i, 0);
+ dc_interrupt_to_irq_source(dc, i+1, 0);
- c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
+ c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
c_irq_params->adev = adev;
c_irq_params->irq_src = int_params.irq_source;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index 1b54566f5da1..d6ebba012e15 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -105,7 +105,7 @@ struct amdgpu_display_manager {
pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1];
struct common_irq_params
- vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1];
+ vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1];
/* this spin lock synchronizes access to 'irq_handler_list_table' */
spinlock_t irq_handler_list_table_lock;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
index ff755a9752da..2d2972e232b6 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
@@ -736,7 +736,7 @@ static int amdgpu_dm_set_crtc_irq_state(struct amdgpu_device *adev,
source,
crtc_id,
state,
- IRQ_TYPE_VUPDATE,
+ IRQ_TYPE_VBLANK,
__func__);
}
--
2.9.3
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^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 24/25] drm/amd/display: Clean index in irq init loop
[not found] ` <20170123143613.15441-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (22 preceding siblings ...)
2017-01-23 14:36 ` [PATCH 23/25] drm/amd/display: Register on VLBLANK ISR Harry Wentland
@ 2017-01-23 14:36 ` Harry Wentland
2017-01-23 14:36 ` [PATCH 25/25] drm/amd/display: add missing dcc update on flip call Harry Wentland
24 siblings, 0 replies; 27+ messages in thread
From: Harry Wentland @ 2017-01-23 14:36 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Andrey Grodzovsky
From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Change-Id: Iaf1b717863c59810657e66835468628acf3aee4c
Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Reviewed-by: Jordan Lazare <Jordan.Lazare@amd.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index a33e339991ec..f066e2207b5e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1033,8 +1033,8 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev)
* for acknowledging and handling. */
/* Use VBLANK interrupt */
- for (i = 0; i < adev->mode_info.num_crtc; i++) {
- r = amdgpu_irq_add_id(adev, i+1, &adev->crtc_irq);
+ for (i = 1; i <= adev->mode_info.num_crtc; i++) {
+ r = amdgpu_irq_add_id(adev, i, &adev->crtc_irq);
if (r) {
DRM_ERROR("Failed to add crtc irq id!\n");
@@ -1043,7 +1043,7 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev)
int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
int_params.irq_source =
- dc_interrupt_to_irq_source(dc, i+1, 0);
+ dc_interrupt_to_irq_source(dc, i, 0);
c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
@@ -1054,6 +1054,7 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev)
dm_crtc_high_irq, c_irq_params);
}
+ /* Use GRPH_PFLIP interrupt */
for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
--
2.9.3
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^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 25/25] drm/amd/display: add missing dcc update on flip call
[not found] ` <20170123143613.15441-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (23 preceding siblings ...)
2017-01-23 14:36 ` [PATCH 24/25] drm/amd/display: Clean index in irq init loop Harry Wentland
@ 2017-01-23 14:36 ` Harry Wentland
24 siblings, 0 replies; 27+ messages in thread
From: Harry Wentland @ 2017-01-23 14:36 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Dmytro Laktyushkin
From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Change-Id: I4eb19bf87e3cee5fb51f572fc866f2e641021884
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 9deddc8ee2d1..f9b7fc85d71a 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1429,6 +1429,8 @@ void dc_update_surfaces_for_stream(struct dc *dc, struct dc_surface_update *upda
updates[i].plane_info->tiling_info;
surface->public.visible =
updates[i].plane_info->visible;
+ surface->public.dcc =
+ updates[i].plane_info->dcc;
}
if (updates[i].scaling_info) {
--
2.9.3
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^ permalink raw reply related [flat|nested] 27+ messages in thread