[PATCH 1/8] dt-bindings: fix for Allwinner H5 pinctrl's compatible

[PATCH 1/8] dt-bindings: fix for Allwinner H5 pinctrl's compatible

[Icenowy Zheng]

The compatible for Allwinner H5 pin controller is wrong written as
allwinner,sun50i-h5-r-pinctrl, however, it's really a generic pinctrl
rather than a "r" one.

Fix this compatible string.

Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
---
 Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index 2fd688c8dbdb..8177bb4d5f53 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -23,7 +23,7 @@ Required properties:
   "allwinner,sun8i-h3-pinctrl"
   "allwinner,sun8i-h3-r-pinctrl"
   "allwinner,sun50i-a64-pinctrl"
-  "allwinner,sun50i-h5-r-pinctrl"
+  "allwinner,sun50i-h5-pinctrl"
   "nextthing,gr8-pinctrl"
 
 - reg: Should contain the register physical address and length for the
-- 
2.11.0

[PATCH 1/8] dt-bindings: fix for Allwinner H5 pinctrl's compatible

[Icenowy Zheng]

The compatible for Allwinner H5 pin controller is wrong written as
allwinner,sun50i-h5-r-pinctrl, however, it's really a generic pinctrl
rather than a "r" one.

Fix this compatible string.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
 Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index 2fd688c8dbdb..8177bb4d5f53 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -23,7 +23,7 @@ Required properties:
   "allwinner,sun8i-h3-pinctrl"
   "allwinner,sun8i-h3-r-pinctrl"
   "allwinner,sun50i-a64-pinctrl"
-  "allwinner,sun50i-h5-r-pinctrl"
+  "allwinner,sun50i-h5-pinctrl"
   "nextthing,gr8-pinctrl"
 
 - reg: Should contain the register physical address and length for the
-- 
2.11.0

[PATCH 2/8] dt: bindings: add binding for Allwinner A64 R_PIO pinctrl

[Icenowy Zheng]

Allwinner A64 SoC has also a dedicated pin controller for Port L GPIOs,
which is called "Port Controller (CPUs-PORT)" in SoC User Manual.

Add a binding for this pin controller, like the ones in A23/33 and H3.

Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
---
 Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index 8177bb4d5f53..b53224473672 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -23,6 +23,7 @@ Required properties:
   "allwinner,sun8i-h3-pinctrl"
   "allwinner,sun8i-h3-r-pinctrl"
   "allwinner,sun50i-a64-pinctrl"
+  "allwinner,sun50i-a64-r-pinctrl"
   "allwinner,sun50i-h5-pinctrl"
   "nextthing,gr8-pinctrl"
 
-- 
2.11.0

[PATCH 2/8] dt: bindings: add binding for Allwinner A64 R_PIO pinctrl

[Icenowy Zheng]

Allwinner A64 SoC has also a dedicated pin controller for Port L GPIOs,
which is called "Port Controller (CPUs-PORT)" in SoC User Manual.

Add a binding for this pin controller, like the ones in A23/33 and H3.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
 Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index 8177bb4d5f53..b53224473672 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -23,6 +23,7 @@ Required properties:
   "allwinner,sun8i-h3-pinctrl"
   "allwinner,sun8i-h3-r-pinctrl"
   "allwinner,sun50i-a64-pinctrl"
+  "allwinner,sun50i-a64-r-pinctrl"
   "allwinner,sun50i-h5-pinctrl"
   "nextthing,gr8-pinctrl"
 
-- 
2.11.0

Re: [PATCH 2/8] dt: bindings: add binding for Allwinner A64 R_PIO pinctrl

[Chen-Yu Tsai]

On Wed, Feb 8, 2017 at 6:00 PM, Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org> wrote:
> Allwinner A64 SoC has also a dedicated pin controller for Port L GPIOs,
> which is called "Port Controller (CPUs-PORT)" in SoC User Manual.
>
> Add a binding for this pin controller, like the ones in A23/33 and H3.
>
> Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>

Acked-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>

[linux-sunxi] [PATCH 2/8] dt: bindings: add binding for Allwinner A64 R_PIO pinctrl

[Chen-Yu Tsai]

On Wed, Feb 8, 2017 at 6:00 PM, Icenowy Zheng <icenowy@aosc.xyz> wrote:
> Allwinner A64 SoC has also a dedicated pin controller for Port L GPIOs,
> which is called "Port Controller (CPUs-PORT)" in SoC User Manual.
>
> Add a binding for this pin controller, like the ones in A23/33 and H3.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>

Acked-by: Chen-Yu Tsai <wens@csie.org>

Re: [linux-sunxi] [PATCH 2/8] dt: bindings: add binding for Allwinner A64 R_PIO pinctrl

[Chen-Yu Tsai]

On Wed, Feb 8, 2017 at 6:00 PM, Icenowy Zheng <icenowy@aosc.xyz> wrote:
> Allwinner A64 SoC has also a dedicated pin controller for Port L GPIOs,
> which is called "Port Controller (CPUs-PORT)" in SoC User Manual.
>
> Add a binding for this pin controller, like the ones in A23/33 and H3.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>

Acked-by: Chen-Yu Tsai <wens@csie.org>

[PATCH 3/8] pinctrl: sunxi: Add A64 R_PIO controller support

[Icenowy Zheng]

The A64 has a R_PIO pin controller, similar to the one found on the H3 SoC.
Add support for the pins controlled by the R_PIO controller.

Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
---
 drivers/pinctrl/sunxi/Kconfig                |   5 +
 drivers/pinctrl/sunxi/Makefile               |   1 +
 drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c | 143 +++++++++++++++++++++++++++
 3 files changed, 149 insertions(+)
 create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c

diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index 92d845827577..df5089841c6e 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -72,6 +72,11 @@ config PINCTRL_SUN50I_A64
 	bool
 	select PINCTRL_SUNXI
 
+config PINCTRL_SUN50I_A64_R
+	bool
+	depends on RESET_CONTROLLER
+	select PINCTRL_SUNXI
+
 config PINCTRL_SUN50I_H5
 	bool
 	select PINCTRL_SUNXI
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index f9a3855c42f1..ce956258cc39 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_PINCTRL_SUN8I_A23)		+= pinctrl-sun8i-a23.o
 obj-$(CONFIG_PINCTRL_SUN8I_A23_R)	+= pinctrl-sun8i-a23-r.o
 obj-$(CONFIG_PINCTRL_SUN8I_A33)		+= pinctrl-sun8i-a33.o
 obj-$(CONFIG_PINCTRL_SUN50I_A64)	+= pinctrl-sun50i-a64.o
+obj-$(CONFIG_PINCTRL_SUN50I_A64_R)	+= pinctrl-sun50i-a64-r.o
 obj-$(CONFIG_PINCTRL_SUN8I_A83T)	+= pinctrl-sun8i-a83t.o
 obj-$(CONFIG_PINCTRL_SUN8I_H3)		+= pinctrl-sun8i-h3.o
 obj-$(CONFIG_PINCTRL_SUN8I_H3_R)	+= pinctrl-sun8i-h3-r.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c
new file mode 100644
index 000000000000..90996a63689b
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c
@@ -0,0 +1,143 @@
+/*
+ * Allwinner A64 SoCs special pins pinctrl driver.
+ *
+ * Based on pinctrl-sun8i-a23-r.c
+ *
+ * Copyright (C) 2016 Icenowy Zheng
+ * Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
+ *
+ * Copyright (C) 2014 Chen-Yu Tsai
+ * Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
+ *
+ * Copyright (C) 2014 Boris Brezillon
+ * Boris Brezillon <boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
+ *
+ * Copyright (C) 2014 Maxime Ripard
+ * Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+
+#include "pinctrl-sunxi.h"
+
+static const struct sunxi_desc_pin sun50i_a64_r_pins[] = {
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "s_rsb"),		/* SCK */
+		  SUNXI_FUNCTION(0x3, "s_i2c"),		/* SCK */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),	/* PL_EINT0 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "s_rsb"),		/* SDA */
+		  SUNXI_FUNCTION(0x3, "s_i2c"),		/* SDA */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),	/* PL_EINT1 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "s_uart"),	/* TX */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),	/* PL_EINT2 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "s_uart"),	/* RX */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),	/* PL_EINT3 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x3, "s_jtag"),	/* MS */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),	/* PL_EINT4 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x3, "s_jtag"),	/* CK */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),	/* PL_EINT5 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x3, "s_jtag"),	/* DO */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),	/* PL_EINT6 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x3, "s_jtag"),	/* DI */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),	/* PL_EINT7 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "s_i2c"),		/* SCK */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),	/* PL_EINT8 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "s_i2c"),		/* SDA */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),	/* PL_EINT9 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 10),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "s_pwm"),
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)),	/* PL_EINT10 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 11),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "s_cir_rx"),
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)),	/* PL_EINT11 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 12),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)),	/* PL_EINT12 */
+};
+
+static const struct sunxi_pinctrl_desc sun50i_a64_r_pinctrl_data = {
+	.pins = sun50i_a64_r_pins,
+	.npins = ARRAY_SIZE(sun50i_a64_r_pins),
+	.pin_base = PL_BASE,
+	.irq_banks = 1,
+};
+
+static int sun50i_a64_r_pinctrl_probe(struct platform_device *pdev)
+{
+	struct reset_control *rstc;
+	int ret;
+
+	rstc = devm_reset_control_get(&pdev->dev, NULL);
+	if (IS_ERR(rstc)) {
+		dev_err(&pdev->dev, "Reset controller missing\n");
+		return PTR_ERR(rstc);
+	}
+
+	ret = reset_control_deassert(rstc);
+	if (ret)
+		return ret;
+
+	ret = sunxi_pinctrl_init(pdev,
+				 &sun50i_a64_r_pinctrl_data);
+
+	if (ret)
+		reset_control_assert(rstc);
+
+	return ret;
+}
+
+static const struct of_device_id sun50i_a64_r_pinctrl_match[] = {
+	{ .compatible = "allwinner,sun50i-a64-r-pinctrl", },
+	{}
+};
+
+static struct platform_driver sun50i_a64_r_pinctrl_driver = {
+	.probe	= sun50i_a64_r_pinctrl_probe,
+	.driver	= {
+		.name		= "sun50i-a64-r-pinctrl",
+		.of_match_table	= sun50i_a64_r_pinctrl_match,
+	},
+};
+builtin_platform_driver(sun50i_a64_r_pinctrl_driver);
-- 
2.11.0

[PATCH 3/8] pinctrl: sunxi: Add A64 R_PIO controller support

[Icenowy Zheng]

The A64 has a R_PIO pin controller, similar to the one found on the H3 SoC.
Add support for the pins controlled by the R_PIO controller.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
 drivers/pinctrl/sunxi/Kconfig                |   5 +
 drivers/pinctrl/sunxi/Makefile               |   1 +
 drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c | 143 +++++++++++++++++++++++++++
 3 files changed, 149 insertions(+)
 create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c

diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index 92d845827577..df5089841c6e 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -72,6 +72,11 @@ config PINCTRL_SUN50I_A64
 	bool
 	select PINCTRL_SUNXI
 
+config PINCTRL_SUN50I_A64_R
+	bool
+	depends on RESET_CONTROLLER
+	select PINCTRL_SUNXI
+
 config PINCTRL_SUN50I_H5
 	bool
 	select PINCTRL_SUNXI
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index f9a3855c42f1..ce956258cc39 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_PINCTRL_SUN8I_A23)		+= pinctrl-sun8i-a23.o
 obj-$(CONFIG_PINCTRL_SUN8I_A23_R)	+= pinctrl-sun8i-a23-r.o
 obj-$(CONFIG_PINCTRL_SUN8I_A33)		+= pinctrl-sun8i-a33.o
 obj-$(CONFIG_PINCTRL_SUN50I_A64)	+= pinctrl-sun50i-a64.o
+obj-$(CONFIG_PINCTRL_SUN50I_A64_R)	+= pinctrl-sun50i-a64-r.o
 obj-$(CONFIG_PINCTRL_SUN8I_A83T)	+= pinctrl-sun8i-a83t.o
 obj-$(CONFIG_PINCTRL_SUN8I_H3)		+= pinctrl-sun8i-h3.o
 obj-$(CONFIG_PINCTRL_SUN8I_H3_R)	+= pinctrl-sun8i-h3-r.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c
new file mode 100644
index 000000000000..90996a63689b
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c
@@ -0,0 +1,143 @@
+/*
+ * Allwinner A64 SoCs special pins pinctrl driver.
+ *
+ * Based on pinctrl-sun8i-a23-r.c
+ *
+ * Copyright (C) 2016 Icenowy Zheng
+ * Icenowy Zheng <icenowy@aosc.xyz>
+ *
+ * Copyright (C) 2014 Chen-Yu Tsai
+ * Chen-Yu Tsai <wens@csie.org>
+ *
+ * Copyright (C) 2014 Boris Brezillon
+ * Boris Brezillon <boris.brezillon@free-electrons.com>
+ *
+ * Copyright (C) 2014 Maxime Ripard
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+
+#include "pinctrl-sunxi.h"
+
+static const struct sunxi_desc_pin sun50i_a64_r_pins[] = {
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "s_rsb"),		/* SCK */
+		  SUNXI_FUNCTION(0x3, "s_i2c"),		/* SCK */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),	/* PL_EINT0 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "s_rsb"),		/* SDA */
+		  SUNXI_FUNCTION(0x3, "s_i2c"),		/* SDA */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),	/* PL_EINT1 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "s_uart"),	/* TX */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),	/* PL_EINT2 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "s_uart"),	/* RX */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),	/* PL_EINT3 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x3, "s_jtag"),	/* MS */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),	/* PL_EINT4 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x3, "s_jtag"),	/* CK */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),	/* PL_EINT5 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x3, "s_jtag"),	/* DO */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),	/* PL_EINT6 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x3, "s_jtag"),	/* DI */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),	/* PL_EINT7 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "s_i2c"),		/* SCK */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),	/* PL_EINT8 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "s_i2c"),		/* SDA */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),	/* PL_EINT9 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 10),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "s_pwm"),
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)),	/* PL_EINT10 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 11),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "s_cir_rx"),
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)),	/* PL_EINT11 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 12),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)),	/* PL_EINT12 */
+};
+
+static const struct sunxi_pinctrl_desc sun50i_a64_r_pinctrl_data = {
+	.pins = sun50i_a64_r_pins,
+	.npins = ARRAY_SIZE(sun50i_a64_r_pins),
+	.pin_base = PL_BASE,
+	.irq_banks = 1,
+};
+
+static int sun50i_a64_r_pinctrl_probe(struct platform_device *pdev)
+{
+	struct reset_control *rstc;
+	int ret;
+
+	rstc = devm_reset_control_get(&pdev->dev, NULL);
+	if (IS_ERR(rstc)) {
+		dev_err(&pdev->dev, "Reset controller missing\n");
+		return PTR_ERR(rstc);
+	}
+
+	ret = reset_control_deassert(rstc);
+	if (ret)
+		return ret;
+
+	ret = sunxi_pinctrl_init(pdev,
+				 &sun50i_a64_r_pinctrl_data);
+
+	if (ret)
+		reset_control_assert(rstc);
+
+	return ret;
+}
+
+static const struct of_device_id sun50i_a64_r_pinctrl_match[] = {
+	{ .compatible = "allwinner,sun50i-a64-r-pinctrl", },
+	{}
+};
+
+static struct platform_driver sun50i_a64_r_pinctrl_driver = {
+	.probe	= sun50i_a64_r_pinctrl_probe,
+	.driver	= {
+		.name		= "sun50i-a64-r-pinctrl",
+		.of_match_table	= sun50i_a64_r_pinctrl_match,
+	},
+};
+builtin_platform_driver(sun50i_a64_r_pinctrl_driver);
-- 
2.11.0

Re: [PATCH 3/8] pinctrl: sunxi: Add A64 R_PIO controller support

[Linus Walleij]

On Wed, Feb 8, 2017 at 11:00 AM, Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org> wrote:

> The A64 has a R_PIO pin controller, similar to the one found on the H3 SoC.
> Add support for the pins controlled by the R_PIO controller.
>
> Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>

I'd be happy to merge patches 1,2 & 3 to the pinctrl tree but I need
a maintainer ACK on these three patches first.

Yours,
Linus Walleij

[PATCH 3/8] pinctrl: sunxi: Add A64 R_PIO controller support

[Linus Walleij]

On Wed, Feb 8, 2017 at 11:00 AM, Icenowy Zheng <icenowy@aosc.xyz> wrote:

> The A64 has a R_PIO pin controller, similar to the one found on the H3 SoC.
> Add support for the pins controlled by the R_PIO controller.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>

I'd be happy to merge patches 1,2 & 3 to the pinctrl tree but I need
a maintainer ACK on these three patches first.

Yours,
Linus Walleij

Re: [PATCH 3/8] pinctrl: sunxi: Add A64 R_PIO controller support

[Linus Walleij]

On Wed, Feb 8, 2017 at 11:00 AM, Icenowy Zheng <icenowy@aosc.xyz> wrote:

> The A64 has a R_PIO pin controller, similar to the one found on the H3 SoC.
> Add support for the pins controlled by the R_PIO controller.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>

I'd be happy to merge patches 1,2 & 3 to the pinctrl tree but I need
a maintainer ACK on these three patches first.

Yours,
Linus Walleij

Re: [PATCH 3/8] pinctrl: sunxi: Add A64 R_PIO controller support

[Chen-Yu Tsai]

On Wed, Feb 8, 2017 at 6:00 PM, Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org> wrote:
> The A64 has a R_PIO pin controller, similar to the one found on the H3 SoC.
> Add support for the pins controlled by the R_PIO controller.
>
> Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
> ---
>  drivers/pinctrl/sunxi/Kconfig                |   5 +
>  drivers/pinctrl/sunxi/Makefile               |   1 +
>  drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c | 143 +++++++++++++++++++++++++++
>  3 files changed, 149 insertions(+)
>  create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c
>
> diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
> index 92d845827577..df5089841c6e 100644
> --- a/drivers/pinctrl/sunxi/Kconfig
> +++ b/drivers/pinctrl/sunxi/Kconfig
> @@ -72,6 +72,11 @@ config PINCTRL_SUN50I_A64
>         bool
>         select PINCTRL_SUNXI
>
> +config PINCTRL_SUN50I_A64_R
> +       bool
> +       depends on RESET_CONTROLLER
> +       select PINCTRL_SUNXI
> +
>  config PINCTRL_SUN50I_H5
>         bool
>         select PINCTRL_SUNXI
> diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
> index f9a3855c42f1..ce956258cc39 100644
> --- a/drivers/pinctrl/sunxi/Makefile
> +++ b/drivers/pinctrl/sunxi/Makefile
> @@ -12,6 +12,7 @@ obj-$(CONFIG_PINCTRL_SUN8I_A23)               += pinctrl-sun8i-a23.o
>  obj-$(CONFIG_PINCTRL_SUN8I_A23_R)      += pinctrl-sun8i-a23-r.o
>  obj-$(CONFIG_PINCTRL_SUN8I_A33)                += pinctrl-sun8i-a33.o
>  obj-$(CONFIG_PINCTRL_SUN50I_A64)       += pinctrl-sun50i-a64.o
> +obj-$(CONFIG_PINCTRL_SUN50I_A64_R)     += pinctrl-sun50i-a64-r.o
>  obj-$(CONFIG_PINCTRL_SUN8I_A83T)       += pinctrl-sun8i-a83t.o
>  obj-$(CONFIG_PINCTRL_SUN8I_H3)         += pinctrl-sun8i-h3.o
>  obj-$(CONFIG_PINCTRL_SUN8I_H3_R)       += pinctrl-sun8i-h3-r.o
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c
> new file mode 100644
> index 000000000000..90996a63689b
> --- /dev/null
> +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c
> @@ -0,0 +1,143 @@
> +/*
> + * Allwinner A64 SoCs special pins pinctrl driver.
> + *
> + * Based on pinctrl-sun8i-a23-r.c
> + *
> + * Copyright (C) 2016 Icenowy Zheng
> + * Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
> + *
> + * Copyright (C) 2014 Chen-Yu Tsai
> + * Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
> + *
> + * Copyright (C) 2014 Boris Brezillon
> + * Boris Brezillon <boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
> + *
> + * Copyright (C) 2014 Maxime Ripard
> + * Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/pinctrl/pinctrl.h>
> +#include <linux/platform_device.h>
> +#include <linux/reset.h>
> +
> +#include "pinctrl-sunxi.h"
> +
> +static const struct sunxi_desc_pin sun50i_a64_r_pins[] = {
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "s_rsb"),         /* SCK */
> +                 SUNXI_FUNCTION(0x3, "s_i2c"),         /* SCK */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),  /* PL_EINT0 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "s_rsb"),         /* SDA */
> +                 SUNXI_FUNCTION(0x3, "s_i2c"),         /* SDA */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),  /* PL_EINT1 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "s_uart"),        /* TX */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),  /* PL_EINT2 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "s_uart"),        /* RX */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),  /* PL_EINT3 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x3, "s_jtag"),        /* MS */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),  /* PL_EINT4 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x3, "s_jtag"),        /* CK */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),  /* PL_EINT5 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x3, "s_jtag"),        /* DO */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),  /* PL_EINT6 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x3, "s_jtag"),        /* DI */

The function ID for JTAG on pins PL4 ~ PL7 should be 0x2, not 0x3.

Otherwise,

Acked-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>

> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),  /* PL_EINT7 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "s_i2c"),         /* SCK */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),  /* PL_EINT8 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "s_i2c"),         /* SDA */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),  /* PL_EINT9 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 10),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "s_pwm"),
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PL_EINT10 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 11),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "s_cir_rx"),
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PL_EINT11 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 12),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PL_EINT12 */
> +};
> +
> +static const struct sunxi_pinctrl_desc sun50i_a64_r_pinctrl_data = {
> +       .pins = sun50i_a64_r_pins,
> +       .npins = ARRAY_SIZE(sun50i_a64_r_pins),
> +       .pin_base = PL_BASE,
> +       .irq_banks = 1,
> +};
> +
> +static int sun50i_a64_r_pinctrl_probe(struct platform_device *pdev)
> +{
> +       struct reset_control *rstc;
> +       int ret;
> +
> +       rstc = devm_reset_control_get(&pdev->dev, NULL);
> +       if (IS_ERR(rstc)) {
> +               dev_err(&pdev->dev, "Reset controller missing\n");
> +               return PTR_ERR(rstc);
> +       }
> +
> +       ret = reset_control_deassert(rstc);
> +       if (ret)
> +               return ret;
> +
> +       ret = sunxi_pinctrl_init(pdev,
> +                                &sun50i_a64_r_pinctrl_data);
> +
> +       if (ret)
> +               reset_control_assert(rstc);
> +
> +       return ret;
> +}
> +
> +static const struct of_device_id sun50i_a64_r_pinctrl_match[] = {
> +       { .compatible = "allwinner,sun50i-a64-r-pinctrl", },
> +       {}
> +};
> +
> +static struct platform_driver sun50i_a64_r_pinctrl_driver = {
> +       .probe  = sun50i_a64_r_pinctrl_probe,
> +       .driver = {
> +               .name           = "sun50i-a64-r-pinctrl",
> +               .of_match_table = sun50i_a64_r_pinctrl_match,
> +       },
> +};
> +builtin_platform_driver(sun50i_a64_r_pinctrl_driver);
> --
> 2.11.0
>
> --
> You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
> To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org
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[linux-sunxi] [PATCH 3/8] pinctrl: sunxi: Add A64 R_PIO controller support

[Chen-Yu Tsai]

On Wed, Feb 8, 2017 at 6:00 PM, Icenowy Zheng <icenowy@aosc.xyz> wrote:
> The A64 has a R_PIO pin controller, similar to the one found on the H3 SoC.
> Add support for the pins controlled by the R_PIO controller.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> ---
>  drivers/pinctrl/sunxi/Kconfig                |   5 +
>  drivers/pinctrl/sunxi/Makefile               |   1 +
>  drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c | 143 +++++++++++++++++++++++++++
>  3 files changed, 149 insertions(+)
>  create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c
>
> diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
> index 92d845827577..df5089841c6e 100644
> --- a/drivers/pinctrl/sunxi/Kconfig
> +++ b/drivers/pinctrl/sunxi/Kconfig
> @@ -72,6 +72,11 @@ config PINCTRL_SUN50I_A64
>         bool
>         select PINCTRL_SUNXI
>
> +config PINCTRL_SUN50I_A64_R
> +       bool
> +       depends on RESET_CONTROLLER
> +       select PINCTRL_SUNXI
> +
>  config PINCTRL_SUN50I_H5
>         bool
>         select PINCTRL_SUNXI
> diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
> index f9a3855c42f1..ce956258cc39 100644
> --- a/drivers/pinctrl/sunxi/Makefile
> +++ b/drivers/pinctrl/sunxi/Makefile
> @@ -12,6 +12,7 @@ obj-$(CONFIG_PINCTRL_SUN8I_A23)               += pinctrl-sun8i-a23.o
>  obj-$(CONFIG_PINCTRL_SUN8I_A23_R)      += pinctrl-sun8i-a23-r.o
>  obj-$(CONFIG_PINCTRL_SUN8I_A33)                += pinctrl-sun8i-a33.o
>  obj-$(CONFIG_PINCTRL_SUN50I_A64)       += pinctrl-sun50i-a64.o
> +obj-$(CONFIG_PINCTRL_SUN50I_A64_R)     += pinctrl-sun50i-a64-r.o
>  obj-$(CONFIG_PINCTRL_SUN8I_A83T)       += pinctrl-sun8i-a83t.o
>  obj-$(CONFIG_PINCTRL_SUN8I_H3)         += pinctrl-sun8i-h3.o
>  obj-$(CONFIG_PINCTRL_SUN8I_H3_R)       += pinctrl-sun8i-h3-r.o
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c
> new file mode 100644
> index 000000000000..90996a63689b
> --- /dev/null
> +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c
> @@ -0,0 +1,143 @@
> +/*
> + * Allwinner A64 SoCs special pins pinctrl driver.
> + *
> + * Based on pinctrl-sun8i-a23-r.c
> + *
> + * Copyright (C) 2016 Icenowy Zheng
> + * Icenowy Zheng <icenowy@aosc.xyz>
> + *
> + * Copyright (C) 2014 Chen-Yu Tsai
> + * Chen-Yu Tsai <wens@csie.org>
> + *
> + * Copyright (C) 2014 Boris Brezillon
> + * Boris Brezillon <boris.brezillon@free-electrons.com>
> + *
> + * Copyright (C) 2014 Maxime Ripard
> + * Maxime Ripard <maxime.ripard@free-electrons.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/pinctrl/pinctrl.h>
> +#include <linux/platform_device.h>
> +#include <linux/reset.h>
> +
> +#include "pinctrl-sunxi.h"
> +
> +static const struct sunxi_desc_pin sun50i_a64_r_pins[] = {
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "s_rsb"),         /* SCK */
> +                 SUNXI_FUNCTION(0x3, "s_i2c"),         /* SCK */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),  /* PL_EINT0 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "s_rsb"),         /* SDA */
> +                 SUNXI_FUNCTION(0x3, "s_i2c"),         /* SDA */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),  /* PL_EINT1 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "s_uart"),        /* TX */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),  /* PL_EINT2 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "s_uart"),        /* RX */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),  /* PL_EINT3 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x3, "s_jtag"),        /* MS */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),  /* PL_EINT4 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x3, "s_jtag"),        /* CK */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),  /* PL_EINT5 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x3, "s_jtag"),        /* DO */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),  /* PL_EINT6 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x3, "s_jtag"),        /* DI */

The function ID for JTAG on pins PL4 ~ PL7 should be 0x2, not 0x3.

Otherwise,

Acked-by: Chen-Yu Tsai <wens@csie.org>

> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),  /* PL_EINT7 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "s_i2c"),         /* SCK */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),  /* PL_EINT8 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "s_i2c"),         /* SDA */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),  /* PL_EINT9 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 10),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "s_pwm"),
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PL_EINT10 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 11),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "s_cir_rx"),
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PL_EINT11 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 12),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PL_EINT12 */
> +};
> +
> +static const struct sunxi_pinctrl_desc sun50i_a64_r_pinctrl_data = {
> +       .pins = sun50i_a64_r_pins,
> +       .npins = ARRAY_SIZE(sun50i_a64_r_pins),
> +       .pin_base = PL_BASE,
> +       .irq_banks = 1,
> +};
> +
> +static int sun50i_a64_r_pinctrl_probe(struct platform_device *pdev)
> +{
> +       struct reset_control *rstc;
> +       int ret;
> +
> +       rstc = devm_reset_control_get(&pdev->dev, NULL);
> +       if (IS_ERR(rstc)) {
> +               dev_err(&pdev->dev, "Reset controller missing\n");
> +               return PTR_ERR(rstc);
> +       }
> +
> +       ret = reset_control_deassert(rstc);
> +       if (ret)
> +               return ret;
> +
> +       ret = sunxi_pinctrl_init(pdev,
> +                                &sun50i_a64_r_pinctrl_data);
> +
> +       if (ret)
> +               reset_control_assert(rstc);
> +
> +       return ret;
> +}
> +
> +static const struct of_device_id sun50i_a64_r_pinctrl_match[] = {
> +       { .compatible = "allwinner,sun50i-a64-r-pinctrl", },
> +       {}
> +};
> +
> +static struct platform_driver sun50i_a64_r_pinctrl_driver = {
> +       .probe  = sun50i_a64_r_pinctrl_probe,
> +       .driver = {
> +               .name           = "sun50i-a64-r-pinctrl",
> +               .of_match_table = sun50i_a64_r_pinctrl_match,
> +       },
> +};
> +builtin_platform_driver(sun50i_a64_r_pinctrl_driver);
> --
> 2.11.0
>
> --
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Re: [linux-sunxi] [PATCH 3/8] pinctrl: sunxi: Add A64 R_PIO controller support

[Chen-Yu Tsai]

On Wed, Feb 8, 2017 at 6:00 PM, Icenowy Zheng <icenowy@aosc.xyz> wrote:
> The A64 has a R_PIO pin controller, similar to the one found on the H3 SoC.
> Add support for the pins controlled by the R_PIO controller.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> ---
>  drivers/pinctrl/sunxi/Kconfig                |   5 +
>  drivers/pinctrl/sunxi/Makefile               |   1 +
>  drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c | 143 +++++++++++++++++++++++++++
>  3 files changed, 149 insertions(+)
>  create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c
>
> diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
> index 92d845827577..df5089841c6e 100644
> --- a/drivers/pinctrl/sunxi/Kconfig
> +++ b/drivers/pinctrl/sunxi/Kconfig
> @@ -72,6 +72,11 @@ config PINCTRL_SUN50I_A64
>         bool
>         select PINCTRL_SUNXI
>
> +config PINCTRL_SUN50I_A64_R
> +       bool
> +       depends on RESET_CONTROLLER
> +       select PINCTRL_SUNXI
> +
>  config PINCTRL_SUN50I_H5
>         bool
>         select PINCTRL_SUNXI
> diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
> index f9a3855c42f1..ce956258cc39 100644
> --- a/drivers/pinctrl/sunxi/Makefile
> +++ b/drivers/pinctrl/sunxi/Makefile
> @@ -12,6 +12,7 @@ obj-$(CONFIG_PINCTRL_SUN8I_A23)               += pinctrl-sun8i-a23.o
>  obj-$(CONFIG_PINCTRL_SUN8I_A23_R)      += pinctrl-sun8i-a23-r.o
>  obj-$(CONFIG_PINCTRL_SUN8I_A33)                += pinctrl-sun8i-a33.o
>  obj-$(CONFIG_PINCTRL_SUN50I_A64)       += pinctrl-sun50i-a64.o
> +obj-$(CONFIG_PINCTRL_SUN50I_A64_R)     += pinctrl-sun50i-a64-r.o
>  obj-$(CONFIG_PINCTRL_SUN8I_A83T)       += pinctrl-sun8i-a83t.o
>  obj-$(CONFIG_PINCTRL_SUN8I_H3)         += pinctrl-sun8i-h3.o
>  obj-$(CONFIG_PINCTRL_SUN8I_H3_R)       += pinctrl-sun8i-h3-r.o
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c
> new file mode 100644
> index 000000000000..90996a63689b
> --- /dev/null
> +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c
> @@ -0,0 +1,143 @@
> +/*
> + * Allwinner A64 SoCs special pins pinctrl driver.
> + *
> + * Based on pinctrl-sun8i-a23-r.c
> + *
> + * Copyright (C) 2016 Icenowy Zheng
> + * Icenowy Zheng <icenowy@aosc.xyz>
> + *
> + * Copyright (C) 2014 Chen-Yu Tsai
> + * Chen-Yu Tsai <wens@csie.org>
> + *
> + * Copyright (C) 2014 Boris Brezillon
> + * Boris Brezillon <boris.brezillon@free-electrons.com>
> + *
> + * Copyright (C) 2014 Maxime Ripard
> + * Maxime Ripard <maxime.ripard@free-electrons.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/pinctrl/pinctrl.h>
> +#include <linux/platform_device.h>
> +#include <linux/reset.h>
> +
> +#include "pinctrl-sunxi.h"
> +
> +static const struct sunxi_desc_pin sun50i_a64_r_pins[] = {
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "s_rsb"),         /* SCK */
> +                 SUNXI_FUNCTION(0x3, "s_i2c"),         /* SCK */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),  /* PL_EINT0 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "s_rsb"),         /* SDA */
> +                 SUNXI_FUNCTION(0x3, "s_i2c"),         /* SDA */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),  /* PL_EINT1 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "s_uart"),        /* TX */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),  /* PL_EINT2 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "s_uart"),        /* RX */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),  /* PL_EINT3 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x3, "s_jtag"),        /* MS */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),  /* PL_EINT4 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x3, "s_jtag"),        /* CK */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),  /* PL_EINT5 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x3, "s_jtag"),        /* DO */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),  /* PL_EINT6 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x3, "s_jtag"),        /* DI */

The function ID for JTAG on pins PL4 ~ PL7 should be 0x2, not 0x3.

Otherwise,

Acked-by: Chen-Yu Tsai <wens@csie.org>

> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),  /* PL_EINT7 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "s_i2c"),         /* SCK */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),  /* PL_EINT8 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "s_i2c"),         /* SDA */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),  /* PL_EINT9 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 10),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "s_pwm"),
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PL_EINT10 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 11),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "s_cir_rx"),
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PL_EINT11 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 12),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PL_EINT12 */
> +};
> +
> +static const struct sunxi_pinctrl_desc sun50i_a64_r_pinctrl_data = {
> +       .pins = sun50i_a64_r_pins,
> +       .npins = ARRAY_SIZE(sun50i_a64_r_pins),
> +       .pin_base = PL_BASE,
> +       .irq_banks = 1,
> +};
> +
> +static int sun50i_a64_r_pinctrl_probe(struct platform_device *pdev)
> +{
> +       struct reset_control *rstc;
> +       int ret;
> +
> +       rstc = devm_reset_control_get(&pdev->dev, NULL);
> +       if (IS_ERR(rstc)) {
> +               dev_err(&pdev->dev, "Reset controller missing\n");
> +               return PTR_ERR(rstc);
> +       }
> +
> +       ret = reset_control_deassert(rstc);
> +       if (ret)
> +               return ret;
> +
> +       ret = sunxi_pinctrl_init(pdev,
> +                                &sun50i_a64_r_pinctrl_data);
> +
> +       if (ret)
> +               reset_control_assert(rstc);
> +
> +       return ret;
> +}
> +
> +static const struct of_device_id sun50i_a64_r_pinctrl_match[] = {
> +       { .compatible = "allwinner,sun50i-a64-r-pinctrl", },
> +       {}
> +};
> +
> +static struct platform_driver sun50i_a64_r_pinctrl_driver = {
> +       .probe  = sun50i_a64_r_pinctrl_probe,
> +       .driver = {
> +               .name           = "sun50i-a64-r-pinctrl",
> +               .of_match_table = sun50i_a64_r_pinctrl_match,
> +       },
> +};
> +builtin_platform_driver(sun50i_a64_r_pinctrl_driver);
> --
> 2.11.0
>
> --
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[PATCH 4/8] arm64: allwinner: select A64 R_PIO driver

[Icenowy Zheng]

As the pinctrl drivers of ARM64 Allwinner SoCs do not have a way to
be explicitly enabled, it should be select by the platform option.

Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
---
 arch/arm64/Kconfig.platforms | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 715ef1256838..d539ac54a36a 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -5,6 +5,7 @@ config ARCH_SUNXI
 	select GENERIC_IRQ_CHIP
 	select PINCTRL
 	select PINCTRL_SUN50I_A64
+	select PINCTRL_SUN50I_A64_R
 	help
 	  This enables support for Allwinner sunxi based SoCs like the A64.
 
-- 
2.11.0

[PATCH 4/8] arm64: allwinner: select A64 R_PIO driver

[Icenowy Zheng]

As the pinctrl drivers of ARM64 Allwinner SoCs do not have a way to
be explicitly enabled, it should be select by the platform option.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
 arch/arm64/Kconfig.platforms | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 715ef1256838..d539ac54a36a 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -5,6 +5,7 @@ config ARCH_SUNXI
 	select GENERIC_IRQ_CHIP
 	select PINCTRL
 	select PINCTRL_SUN50I_A64
+	select PINCTRL_SUN50I_A64_R
 	help
 	  This enables support for Allwinner sunxi based SoCs like the A64.
 
-- 
2.11.0

[PATCH 5/8] arm64: dts: allwinner: add R_PIO node

[Icenowy Zheng]

Allwinner A64 SoC has a R_PIO node like the one in H3.

Add the node as well as needed clocks and resets.

As there's no document for apb0_gates, I only added the R_PIO bit here.

Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
---
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 40 +++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 1c64ea2d23f9..4b0baa79554c 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -98,6 +98,15 @@
 		clock-output-names = "osc32k";
 	};
 
+	apb0: apb0_clk {
+		compatible = "fixed-factor-clock";
+		#clock-cells = <0>;
+		clock-div = <1>;
+		clock-mult = <1>;
+		clocks = <&osc24M>;
+		clock-output-names = "apb0";
+	};
+
 	psci {
 		compatible = "arm,psci-0.2";
 		method = "smc";
@@ -392,5 +401,36 @@
 			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 		};
+
+		apb0_gates: clk@1f01428 {
+			compatible = "allwinner,sun50i-a64-apb0-gates-clk",
+				     "allwinner,sun4i-a10-gates-clk";
+			reg = <0x01f01428 0x4>;
+			#clock-cells = <1>;
+			clocks = <&apb0>;
+			clock-indices = <0>;
+			clock-output-names = "apb0_pio";
+		};
+
+		apb0_rst: reset@1f014b0 {
+			reg = <0x01f014b0 0x4>;
+			compatible = "allwinner,sun6i-a31-clock-reset";
+			#reset-cells = <1>;
+		};
+
+		r_pio: pinctrl@1f02c00 {
+			compatible = "allwinner,sun50i-a64-r-pinctrl";
+			reg = <0x01f02c00 0x400>;
+			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>;
+			clock-names = "apb", "hosc", "losc";
+			resets = <&apb0_rst 0>;
+			gpio-controller;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#gpio-cells = <3>;
+		};
 	};
 };
-- 
2.11.0

[PATCH 5/8] arm64: dts: allwinner: add R_PIO node

[Icenowy Zheng]

Allwinner A64 SoC has a R_PIO node like the one in H3.

Add the node as well as needed clocks and resets.

As there's no document for apb0_gates, I only added the R_PIO bit here.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 40 +++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 1c64ea2d23f9..4b0baa79554c 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -98,6 +98,15 @@
 		clock-output-names = "osc32k";
 	};
 
+	apb0: apb0_clk {
+		compatible = "fixed-factor-clock";
+		#clock-cells = <0>;
+		clock-div = <1>;
+		clock-mult = <1>;
+		clocks = <&osc24M>;
+		clock-output-names = "apb0";
+	};
+
 	psci {
 		compatible = "arm,psci-0.2";
 		method = "smc";
@@ -392,5 +401,36 @@
 			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 		};
+
+		apb0_gates: clk at 1f01428 {
+			compatible = "allwinner,sun50i-a64-apb0-gates-clk",
+				     "allwinner,sun4i-a10-gates-clk";
+			reg = <0x01f01428 0x4>;
+			#clock-cells = <1>;
+			clocks = <&apb0>;
+			clock-indices = <0>;
+			clock-output-names = "apb0_pio";
+		};
+
+		apb0_rst: reset at 1f014b0 {
+			reg = <0x01f014b0 0x4>;
+			compatible = "allwinner,sun6i-a31-clock-reset";
+			#reset-cells = <1>;
+		};
+
+		r_pio: pinctrl at 1f02c00 {
+			compatible = "allwinner,sun50i-a64-r-pinctrl";
+			reg = <0x01f02c00 0x400>;
+			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>;
+			clock-names = "apb", "hosc", "losc";
+			resets = <&apb0_rst 0>;
+			gpio-controller;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#gpio-cells = <3>;
+		};
 	};
 };
-- 
2.11.0

Re: [PATCH 5/8] arm64: dts: allwinner: add R_PIO node

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 1784 bytes --]

On Wed, Feb 08, 2017 at 06:00:06PM +0800, Icenowy Zheng wrote:
> Allwinner A64 SoC has a R_PIO node like the one in H3.
> 
> Add the node as well as needed clocks and resets.
> 
> As there's no document for apb0_gates, I only added the R_PIO bit here.
> 
> Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
> ---
>  arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 40 +++++++++++++++++++++++++++
>  1 file changed, 40 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> index 1c64ea2d23f9..4b0baa79554c 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> @@ -98,6 +98,15 @@
>  		clock-output-names = "osc32k";
>  	};
>  
> +	apb0: apb0_clk {
> +		compatible = "fixed-factor-clock";
> +		#clock-cells = <0>;
> +		clock-div = <1>;
> +		clock-mult = <1>;
> +		clocks = <&osc24M>;
> +		clock-output-names = "apb0";
> +	};
> +
>  	psci {
>  		compatible = "arm,psci-0.2";
>  		method = "smc";
> @@ -392,5 +401,36 @@
>  			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
>  				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
>  		};
> +
> +		apb0_gates: clk@1f01428 {
> +			compatible = "allwinner,sun50i-a64-apb0-gates-clk",
> +				     "allwinner,sun4i-a10-gates-clk";
> +			reg = <0x01f01428 0x4>;
> +			#clock-cells = <1>;
> +			clocks = <&apb0>;
> +			clock-indices = <0>;
> +			clock-output-names = "apb0_pio";
> +		};
> +
> +		apb0_rst: reset@1f014b0 {
> +			reg = <0x01f014b0 0x4>;
> +			compatible = "allwinner,sun6i-a31-clock-reset";
> +			#reset-cells = <1>;
> +		};

Please make a sunxi-ng driver for those clocks.

Thanks,
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

[PATCH 5/8] arm64: dts: allwinner: add R_PIO node

[Maxime Ripard]

On Wed, Feb 08, 2017 at 06:00:06PM +0800, Icenowy Zheng wrote:
> Allwinner A64 SoC has a R_PIO node like the one in H3.
> 
> Add the node as well as needed clocks and resets.
> 
> As there's no document for apb0_gates, I only added the R_PIO bit here.
> 
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> ---
>  arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 40 +++++++++++++++++++++++++++
>  1 file changed, 40 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> index 1c64ea2d23f9..4b0baa79554c 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> @@ -98,6 +98,15 @@
>  		clock-output-names = "osc32k";
>  	};
>  
> +	apb0: apb0_clk {
> +		compatible = "fixed-factor-clock";
> +		#clock-cells = <0>;
> +		clock-div = <1>;
> +		clock-mult = <1>;
> +		clocks = <&osc24M>;
> +		clock-output-names = "apb0";
> +	};
> +
>  	psci {
>  		compatible = "arm,psci-0.2";
>  		method = "smc";
> @@ -392,5 +401,36 @@
>  			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
>  				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
>  		};
> +
> +		apb0_gates: clk at 1f01428 {
> +			compatible = "allwinner,sun50i-a64-apb0-gates-clk",
> +				     "allwinner,sun4i-a10-gates-clk";
> +			reg = <0x01f01428 0x4>;
> +			#clock-cells = <1>;
> +			clocks = <&apb0>;
> +			clock-indices = <0>;
> +			clock-output-names = "apb0_pio";
> +		};
> +
> +		apb0_rst: reset at 1f014b0 {
> +			reg = <0x01f014b0 0x4>;
> +			compatible = "allwinner,sun6i-a31-clock-reset";
> +			#reset-cells = <1>;
> +		};

Please make a sunxi-ng driver for those clocks.

Thanks,
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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Re: [PATCH 5/8] arm64: dts: allwinner: add R_PIO node

[Maxime Ripard]

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On Wed, Feb 08, 2017 at 06:00:06PM +0800, Icenowy Zheng wrote:
> Allwinner A64 SoC has a R_PIO node like the one in H3.
> 
> Add the node as well as needed clocks and resets.
> 
> As there's no document for apb0_gates, I only added the R_PIO bit here.
> 
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> ---
>  arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 40 +++++++++++++++++++++++++++
>  1 file changed, 40 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> index 1c64ea2d23f9..4b0baa79554c 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> @@ -98,6 +98,15 @@
>  		clock-output-names = "osc32k";
>  	};
>  
> +	apb0: apb0_clk {
> +		compatible = "fixed-factor-clock";
> +		#clock-cells = <0>;
> +		clock-div = <1>;
> +		clock-mult = <1>;
> +		clocks = <&osc24M>;
> +		clock-output-names = "apb0";
> +	};
> +
>  	psci {
>  		compatible = "arm,psci-0.2";
>  		method = "smc";
> @@ -392,5 +401,36 @@
>  			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
>  				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
>  		};
> +
> +		apb0_gates: clk@1f01428 {
> +			compatible = "allwinner,sun50i-a64-apb0-gates-clk",
> +				     "allwinner,sun4i-a10-gates-clk";
> +			reg = <0x01f01428 0x4>;
> +			#clock-cells = <1>;
> +			clocks = <&apb0>;
> +			clock-indices = <0>;
> +			clock-output-names = "apb0_pio";
> +		};
> +
> +		apb0_rst: reset@1f014b0 {
> +			reg = <0x01f014b0 0x4>;
> +			compatible = "allwinner,sun6i-a31-clock-reset";
> +			#reset-cells = <1>;
> +		};

Please make a sunxi-ng driver for those clocks.

Thanks,
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

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Re: [PATCH 5/8] arm64: dts: allwinner: add R_PIO node

[Icenowy Zheng]

08.02.2017, 18:15, "Maxime Ripard" <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>:
> On Wed, Feb 08, 2017 at 06:00:06PM +0800, Icenowy Zheng wrote:
>>  Allwinner A64 SoC has a R_PIO node like the one in H3.
>>
>>  Add the node as well as needed clocks and resets.
>>
>>  As there's no document for apb0_gates, I only added the R_PIO bit here.
>>
>>  Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
>>  ---
>>   arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 40 +++++++++++++++++++++++++++
>>   1 file changed, 40 insertions(+)
>>
>>  diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
>>  index 1c64ea2d23f9..4b0baa79554c 100644
>>  --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
>>  +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
>>  @@ -98,6 +98,15 @@
>>                   clock-output-names = "osc32k";
>>           };
>>
>>  + apb0: apb0_clk {
>>  + compatible = "fixed-factor-clock";
>>  + #clock-cells = <0>;
>>  + clock-div = <1>;
>>  + clock-mult = <1>;
>>  + clocks = <&osc24M>;
>>  + clock-output-names = "apb0";
>>  + };
>>  +
>>           psci {
>>                   compatible = "arm,psci-0.2";
>>                   method = "smc";
>>  @@ -392,5 +401,36 @@
>>                           interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
>>                                        <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
>>                   };
>>  +
>>  + apb0_gates: clk@1f01428 {
>>  + compatible = "allwinner,sun50i-a64-apb0-gates-clk",
>>  + "allwinner,sun4i-a10-gates-clk";
>>  + reg = <0x01f01428 0x4>;
>>  + #clock-cells = <1>;
>>  + clocks = <&apb0>;
>>  + clock-indices = <0>;
>>  + clock-output-names = "apb0_pio";
>>  + };
>>  +
>>  + apb0_rst: reset@1f014b0 {
>>  + reg = <0x01f014b0 0x4>;
>>  + compatible = "allwinner,sun6i-a31-clock-reset";
>>  + #reset-cells = <1>;
>>  + };
>
> Please make a sunxi-ng driver for those clocks.

We have no enough materials to make such a CCU driver.

Clocks in CPUs are usually undocumented, and difficult to
be collected -- even the clk-sun50iw1.c in BSP do not have
all clocks in CPUs.

We should only make it sunxi-ng until it's fully discovered
(all functions in CPUs are functional).

>
> Thanks,
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux and Kernel engineering
> http://free-electrons.com

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[PATCH 5/8] arm64: dts: allwinner: add R_PIO node

[Icenowy Zheng]

08.02.2017, 18:15, "Maxime Ripard" <maxime.ripard@free-electrons.com>:
> On Wed, Feb 08, 2017 at 06:00:06PM +0800, Icenowy Zheng wrote:
>> ?Allwinner A64 SoC has a R_PIO node like the one in H3.
>>
>> ?Add the node as well as needed clocks and resets.
>>
>> ?As there's no document for apb0_gates, I only added the R_PIO bit here.
>>
>> ?Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
>> ?---
>> ??arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 40 +++++++++++++++++++++++++++
>> ??1 file changed, 40 insertions(+)
>>
>> ?diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
>> ?index 1c64ea2d23f9..4b0baa79554c 100644
>> ?--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
>> ?+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
>> ?@@ -98,6 +98,15 @@
>> ??????????????????clock-output-names = "osc32k";
>> ??????????};
>>
>> ?+ apb0: apb0_clk {
>> ?+ compatible = "fixed-factor-clock";
>> ?+ #clock-cells = <0>;
>> ?+ clock-div = <1>;
>> ?+ clock-mult = <1>;
>> ?+ clocks = <&osc24M>;
>> ?+ clock-output-names = "apb0";
>> ?+ };
>> ?+
>> ??????????psci {
>> ??????????????????compatible = "arm,psci-0.2";
>> ??????????????????method = "smc";
>> ?@@ -392,5 +401,36 @@
>> ??????????????????????????interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
>> ???????????????????????????????????????<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
>> ??????????????????};
>> ?+
>> ?+ apb0_gates: clk at 1f01428 {
>> ?+ compatible = "allwinner,sun50i-a64-apb0-gates-clk",
>> ?+ "allwinner,sun4i-a10-gates-clk";
>> ?+ reg = <0x01f01428 0x4>;
>> ?+ #clock-cells = <1>;
>> ?+ clocks = <&apb0>;
>> ?+ clock-indices = <0>;
>> ?+ clock-output-names = "apb0_pio";
>> ?+ };
>> ?+
>> ?+ apb0_rst: reset at 1f014b0 {
>> ?+ reg = <0x01f014b0 0x4>;
>> ?+ compatible = "allwinner,sun6i-a31-clock-reset";
>> ?+ #reset-cells = <1>;
>> ?+ };
>
> Please make a sunxi-ng driver for those clocks.

We have no enough materials to make such a CCU driver.

Clocks in CPUs are usually undocumented, and difficult to
be collected -- even the clk-sun50iw1.c in BSP do not have
all clocks in CPUs.

We should only make it sunxi-ng until it's fully discovered
(all functions in CPUs are functional).

>
> Thanks,
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux and Kernel engineering
> http://free-electrons.com

Re: [PATCH 5/8] arm64: dts: allwinner: add R_PIO node

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 3365 bytes --]

On Wed, Feb 08, 2017 at 07:08:46PM +0800, Icenowy Zheng wrote:
> 08.02.2017, 18:15, "Maxime Ripard" <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>:
> > On Wed, Feb 08, 2017 at 06:00:06PM +0800, Icenowy Zheng wrote:
> >>  Allwinner A64 SoC has a R_PIO node like the one in H3.
> >>
> >>  Add the node as well as needed clocks and resets.
> >>
> >>  As there's no document for apb0_gates, I only added the R_PIO bit here.
> >>
> >>  Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
> >>  ---
> >>   arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 40 +++++++++++++++++++++++++++
> >>   1 file changed, 40 insertions(+)
> >>
> >>  diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> >>  index 1c64ea2d23f9..4b0baa79554c 100644
> >>  --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> >>  +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> >>  @@ -98,6 +98,15 @@
> >>                   clock-output-names = "osc32k";
> >>           };
> >>
> >>  + apb0: apb0_clk {
> >>  + compatible = "fixed-factor-clock";
> >>  + #clock-cells = <0>;
> >>  + clock-div = <1>;
> >>  + clock-mult = <1>;
> >>  + clocks = <&osc24M>;
> >>  + clock-output-names = "apb0";
> >>  + };
> >>  +
> >>           psci {
> >>                   compatible = "arm,psci-0.2";
> >>                   method = "smc";
> >>  @@ -392,5 +401,36 @@
> >>                           interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
> >>                                        <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
> >>                   };
> >>  +
> >>  + apb0_gates: clk@1f01428 {
> >>  + compatible = "allwinner,sun50i-a64-apb0-gates-clk",
> >>  + "allwinner,sun4i-a10-gates-clk";
> >>  + reg = <0x01f01428 0x4>;
> >>  + #clock-cells = <1>;
> >>  + clocks = <&apb0>;
> >>  + clock-indices = <0>;
> >>  + clock-output-names = "apb0_pio";
> >>  + };
> >>  +
> >>  + apb0_rst: reset@1f014b0 {
> >>  + reg = <0x01f014b0 0x4>;
> >>  + compatible = "allwinner,sun6i-a31-clock-reset";
> >>  + #reset-cells = <1>;
> >>  + };
> >
> > Please make a sunxi-ng driver for those clocks.
> 
> We have no enough materials to make such a CCU driver.
> 
> Clocks in CPUs are usually undocumented, and difficult to
> be collected -- even the clk-sun50iw1.c in BSP do not have
> all clocks in CPUs.

That's unfortunate, but we can deal with that by simply extending the
clocks we have. Nothing too complicated or unconvenient to deal with.

> We should only make it sunxi-ng until it's fully discovered (all
> functions in CPUs are functional).

No, I expect that by 4.12 we have converted every users to sunxi-ng,
PRCM included.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

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[PATCH 5/8] arm64: dts: allwinner: add R_PIO node

[Maxime Ripard]

On Wed, Feb 08, 2017 at 07:08:46PM +0800, Icenowy Zheng wrote:
> 08.02.2017, 18:15, "Maxime Ripard" <maxime.ripard@free-electrons.com>:
> > On Wed, Feb 08, 2017 at 06:00:06PM +0800, Icenowy Zheng wrote:
> >> ?Allwinner A64 SoC has a R_PIO node like the one in H3.
> >>
> >> ?Add the node as well as needed clocks and resets.
> >>
> >> ?As there's no document for apb0_gates, I only added the R_PIO bit here.
> >>
> >> ?Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> >> ?---
> >> ??arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 40 +++++++++++++++++++++++++++
> >> ??1 file changed, 40 insertions(+)
> >>
> >> ?diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> >> ?index 1c64ea2d23f9..4b0baa79554c 100644
> >> ?--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> >> ?+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> >> ?@@ -98,6 +98,15 @@
> >> ??????????????????clock-output-names = "osc32k";
> >> ??????????};
> >>
> >> ?+ apb0: apb0_clk {
> >> ?+ compatible = "fixed-factor-clock";
> >> ?+ #clock-cells = <0>;
> >> ?+ clock-div = <1>;
> >> ?+ clock-mult = <1>;
> >> ?+ clocks = <&osc24M>;
> >> ?+ clock-output-names = "apb0";
> >> ?+ };
> >> ?+
> >> ??????????psci {
> >> ??????????????????compatible = "arm,psci-0.2";
> >> ??????????????????method = "smc";
> >> ?@@ -392,5 +401,36 @@
> >> ??????????????????????????interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
> >> ???????????????????????????????????????<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
> >> ??????????????????};
> >> ?+
> >> ?+ apb0_gates: clk at 1f01428 {
> >> ?+ compatible = "allwinner,sun50i-a64-apb0-gates-clk",
> >> ?+ "allwinner,sun4i-a10-gates-clk";
> >> ?+ reg = <0x01f01428 0x4>;
> >> ?+ #clock-cells = <1>;
> >> ?+ clocks = <&apb0>;
> >> ?+ clock-indices = <0>;
> >> ?+ clock-output-names = "apb0_pio";
> >> ?+ };
> >> ?+
> >> ?+ apb0_rst: reset at 1f014b0 {
> >> ?+ reg = <0x01f014b0 0x4>;
> >> ?+ compatible = "allwinner,sun6i-a31-clock-reset";
> >> ?+ #reset-cells = <1>;
> >> ?+ };
> >
> > Please make a sunxi-ng driver for those clocks.
> 
> We have no enough materials to make such a CCU driver.
> 
> Clocks in CPUs are usually undocumented, and difficult to
> be collected -- even the clk-sun50iw1.c in BSP do not have
> all clocks in CPUs.

That's unfortunate, but we can deal with that by simply extending the
clocks we have. Nothing too complicated or unconvenient to deal with.

> We should only make it sunxi-ng until it's fully discovered (all
> functions in CPUs are functional).

No, I expect that by 4.12 we have converted every users to sunxi-ng,
PRCM included.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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Re: [PATCH 5/8] arm64: dts: allwinner: add R_PIO node

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 2795 bytes --]

On Wed, Feb 08, 2017 at 07:08:46PM +0800, Icenowy Zheng wrote:
> 08.02.2017, 18:15, "Maxime Ripard" <maxime.ripard@free-electrons.com>:
> > On Wed, Feb 08, 2017 at 06:00:06PM +0800, Icenowy Zheng wrote:
> >>  Allwinner A64 SoC has a R_PIO node like the one in H3.
> >>
> >>  Add the node as well as needed clocks and resets.
> >>
> >>  As there's no document for apb0_gates, I only added the R_PIO bit here.
> >>
> >>  Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> >>  ---
> >>   arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 40 +++++++++++++++++++++++++++
> >>   1 file changed, 40 insertions(+)
> >>
> >>  diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> >>  index 1c64ea2d23f9..4b0baa79554c 100644
> >>  --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> >>  +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> >>  @@ -98,6 +98,15 @@
> >>                   clock-output-names = "osc32k";
> >>           };
> >>
> >>  + apb0: apb0_clk {
> >>  + compatible = "fixed-factor-clock";
> >>  + #clock-cells = <0>;
> >>  + clock-div = <1>;
> >>  + clock-mult = <1>;
> >>  + clocks = <&osc24M>;
> >>  + clock-output-names = "apb0";
> >>  + };
> >>  +
> >>           psci {
> >>                   compatible = "arm,psci-0.2";
> >>                   method = "smc";
> >>  @@ -392,5 +401,36 @@
> >>                           interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
> >>                                        <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
> >>                   };
> >>  +
> >>  + apb0_gates: clk@1f01428 {
> >>  + compatible = "allwinner,sun50i-a64-apb0-gates-clk",
> >>  + "allwinner,sun4i-a10-gates-clk";
> >>  + reg = <0x01f01428 0x4>;
> >>  + #clock-cells = <1>;
> >>  + clocks = <&apb0>;
> >>  + clock-indices = <0>;
> >>  + clock-output-names = "apb0_pio";
> >>  + };
> >>  +
> >>  + apb0_rst: reset@1f014b0 {
> >>  + reg = <0x01f014b0 0x4>;
> >>  + compatible = "allwinner,sun6i-a31-clock-reset";
> >>  + #reset-cells = <1>;
> >>  + };
> >
> > Please make a sunxi-ng driver for those clocks.
> 
> We have no enough materials to make such a CCU driver.
> 
> Clocks in CPUs are usually undocumented, and difficult to
> be collected -- even the clk-sun50iw1.c in BSP do not have
> all clocks in CPUs.

That's unfortunate, but we can deal with that by simply extending the
clocks we have. Nothing too complicated or unconvenient to deal with.

> We should only make it sunxi-ng until it's fully discovered (all
> functions in CPUs are functional).

No, I expect that by 4.12 we have converted every users to sunxi-ng,
PRCM included.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

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[PATCH 6/8] arm64: dts: allwinner: add device node for R_PWM

[Icenowy Zheng]

Allwinner A64 SoC has two PWM controller, both are similar to the
controller in H3 SoC.

Add one of the controllers which lies in the "CPUs" part of the SoC.

Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
---
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 4b0baa79554c..6204aee5c6f4 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -432,5 +432,13 @@
 			#size-cells = <0>;
 			#gpio-cells = <3>;
 		};
+
+		r_pwm: pwm@01f03800 {
+			compatible = "allwinner,sun8i-h3-pwm";
+			reg = <0x01f03800 0x8>;
+			clocks = <&osc24M>;
+			#pwm-cells = <3>;
+			status = "disabled";
+		};
 	};
 };
-- 
2.11.0

[PATCH 6/8] arm64: dts: allwinner: add device node for R_PWM

[Icenowy Zheng]

Allwinner A64 SoC has two PWM controller, both are similar to the
controller in H3 SoC.

Add one of the controllers which lies in the "CPUs" part of the SoC.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 4b0baa79554c..6204aee5c6f4 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -432,5 +432,13 @@
 			#size-cells = <0>;
 			#gpio-cells = <3>;
 		};
+
+		r_pwm: pwm at 01f03800 {
+			compatible = "allwinner,sun8i-h3-pwm";
+			reg = <0x01f03800 0x8>;
+			clocks = <&osc24M>;
+			#pwm-cells = <3>;
+			status = "disabled";
+		};
 	};
 };
-- 
2.11.0

Re: [PATCH 6/8] arm64: dts: allwinner: add device node for R_PWM

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 1029 bytes --]

On Wed, Feb 08, 2017 at 06:00:07PM +0800, Icenowy Zheng wrote:
> Allwinner A64 SoC has two PWM controller, both are similar to the
> controller in H3 SoC.
> 
> Add one of the controllers which lies in the "CPUs" part of the SoC.
> 
> Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
> ---
>  arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> index 4b0baa79554c..6204aee5c6f4 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> @@ -432,5 +432,13 @@
>  			#size-cells = <0>;
>  			#gpio-cells = <3>;
>  		};
> +
> +		r_pwm: pwm@01f03800 {
> +			compatible = "allwinner,sun8i-h3-pwm";

Please add an a64 compatible there too.

> +			reg = <0x01f03800 0x8>;

The size is 0x400

Thanks,
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

[PATCH 6/8] arm64: dts: allwinner: add device node for R_PWM

[Maxime Ripard]

On Wed, Feb 08, 2017 at 06:00:07PM +0800, Icenowy Zheng wrote:
> Allwinner A64 SoC has two PWM controller, both are similar to the
> controller in H3 SoC.
> 
> Add one of the controllers which lies in the "CPUs" part of the SoC.
> 
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> ---
>  arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> index 4b0baa79554c..6204aee5c6f4 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> @@ -432,5 +432,13 @@
>  			#size-cells = <0>;
>  			#gpio-cells = <3>;
>  		};
> +
> +		r_pwm: pwm at 01f03800 {
> +			compatible = "allwinner,sun8i-h3-pwm";

Please add an a64 compatible there too.

> +			reg = <0x01f03800 0x8>;

The size is 0x400

Thanks,
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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Re: [PATCH 6/8] arm64: dts: allwinner: add device node for R_PWM

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 1046 bytes --]

On Wed, Feb 08, 2017 at 06:00:07PM +0800, Icenowy Zheng wrote:
> Allwinner A64 SoC has two PWM controller, both are similar to the
> controller in H3 SoC.
> 
> Add one of the controllers which lies in the "CPUs" part of the SoC.
> 
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> ---
>  arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> index 4b0baa79554c..6204aee5c6f4 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> @@ -432,5 +432,13 @@
>  			#size-cells = <0>;
>  			#gpio-cells = <3>;
>  		};
> +
> +		r_pwm: pwm@01f03800 {
> +			compatible = "allwinner,sun8i-h3-pwm";

Please add an a64 compatible there too.

> +			reg = <0x01f03800 0x8>;

The size is 0x400

Thanks,
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

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[PATCH 7/8] arm64: dts: allwinner: add pinmux for A64's r_pwm

[Icenowy Zheng]

As the r_pwm controller in A64 have only one pinmux (PL10), and being
routed to the Pine64's "PI-2-bus", add the pinmux node in r_pio, then
make it the default pinctrl node for r_pwm node.

Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
---
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 6204aee5c6f4..6e34f5adcf06 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -431,12 +431,19 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			#gpio-cells = <3>;
+
+			r_pwm_pins: pwm@0 {
+				pins = "PL10";
+				function = "s_pwm";
+			};
 		};
 
 		r_pwm: pwm@01f03800 {
 			compatible = "allwinner,sun8i-h3-pwm";
 			reg = <0x01f03800 0x8>;
 			clocks = <&osc24M>;
+			pinctrl-0 = <&r_pwm_pins>;
+			pinctrl-names = "default";
 			#pwm-cells = <3>;
 			status = "disabled";
 		};
-- 
2.11.0

[PATCH 7/8] arm64: dts: allwinner: add pinmux for A64's r_pwm

[Icenowy Zheng]

As the r_pwm controller in A64 have only one pinmux (PL10), and being
routed to the Pine64's "PI-2-bus", add the pinmux node in r_pio, then
make it the default pinctrl node for r_pwm node.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 6204aee5c6f4..6e34f5adcf06 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -431,12 +431,19 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			#gpio-cells = <3>;
+
+			r_pwm_pins: pwm at 0 {
+				pins = "PL10";
+				function = "s_pwm";
+			};
 		};
 
 		r_pwm: pwm at 01f03800 {
 			compatible = "allwinner,sun8i-h3-pwm";
 			reg = <0x01f03800 0x8>;
 			clocks = <&osc24M>;
+			pinctrl-0 = <&r_pwm_pins>;
+			pinctrl-names = "default";
 			#pwm-cells = <3>;
 			status = "disabled";
 		};
-- 
2.11.0

[PATCH 8/8] arm64: dts: allwinner: add PWM node to A64 dtsi

[Icenowy Zheng]

Allwinner A64 has also a PWM controller on PD22 (not available on
Pine64, because it's muxed with EMAC, but it's used on Olimex TERES
laptop kit to adjust the screen backlight).

Add a device node for it.

Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
---
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 6e34f5adcf06..078322fb5d58 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -296,6 +296,14 @@
 			};
 		};
 
+		pwm: pwm@1c21400 {
+			compatible = "allwinner,sun8i-h3-pwm";
+			reg = <0x01c21400 0x8>;
+			clocks = <&osc24M>;
+			#pwm-cells = <3>;
+			status = "disabled";
+		};
+
 		uart0: serial@1c28000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x01c28000 0x400>;
-- 
2.11.0

[PATCH 8/8] arm64: dts: allwinner: add PWM node to A64 dtsi

[Icenowy Zheng]

Allwinner A64 has also a PWM controller on PD22 (not available on
Pine64, because it's muxed with EMAC, but it's used on Olimex TERES
laptop kit to adjust the screen backlight).

Add a device node for it.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 6e34f5adcf06..078322fb5d58 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -296,6 +296,14 @@
 			};
 		};
 
+		pwm: pwm at 1c21400 {
+			compatible = "allwinner,sun8i-h3-pwm";
+			reg = <0x01c21400 0x8>;
+			clocks = <&osc24M>;
+			#pwm-cells = <3>;
+			status = "disabled";
+		};
+
 		uart0: serial at 1c28000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x01c28000 0x400>;
-- 
2.11.0

Re: [PATCH 8/8] arm64: dts: allwinner: add PWM node to A64 dtsi

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 1041 bytes --]

On Wed, Feb 08, 2017 at 06:00:09PM +0800, Icenowy Zheng wrote:
> Allwinner A64 has also a PWM controller on PD22 (not available on
> Pine64, because it's muxed with EMAC, but it's used on Olimex TERES
> laptop kit to adjust the screen backlight).
> 
> Add a device node for it.
> 
> Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
> ---
>  arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> index 6e34f5adcf06..078322fb5d58 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> @@ -296,6 +296,14 @@
>  			};
>  		};
>  
> +		pwm: pwm@1c21400 {
> +			compatible = "allwinner,sun8i-h3-pwm";
> +			reg = <0x01c21400 0x8>;

Same thing here, the size is wrong, and you need a new compatible.

Thanks,
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

[PATCH 8/8] arm64: dts: allwinner: add PWM node to A64 dtsi

[Maxime Ripard]

On Wed, Feb 08, 2017 at 06:00:09PM +0800, Icenowy Zheng wrote:
> Allwinner A64 has also a PWM controller on PD22 (not available on
> Pine64, because it's muxed with EMAC, but it's used on Olimex TERES
> laptop kit to adjust the screen backlight).
> 
> Add a device node for it.
> 
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> ---
>  arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> index 6e34f5adcf06..078322fb5d58 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> @@ -296,6 +296,14 @@
>  			};
>  		};
>  
> +		pwm: pwm at 1c21400 {
> +			compatible = "allwinner,sun8i-h3-pwm";
> +			reg = <0x01c21400 0x8>;

Same thing here, the size is wrong, and you need a new compatible.

Thanks,
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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Re: [PATCH 8/8] arm64: dts: allwinner: add PWM node to A64 dtsi

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 1055 bytes --]

On Wed, Feb 08, 2017 at 06:00:09PM +0800, Icenowy Zheng wrote:
> Allwinner A64 has also a PWM controller on PD22 (not available on
> Pine64, because it's muxed with EMAC, but it's used on Olimex TERES
> laptop kit to adjust the screen backlight).
> 
> Add a device node for it.
> 
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> ---
>  arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> index 6e34f5adcf06..078322fb5d58 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> @@ -296,6 +296,14 @@
>  			};
>  		};
>  
> +		pwm: pwm@1c21400 {
> +			compatible = "allwinner,sun8i-h3-pwm";
> +			reg = <0x01c21400 0x8>;

Same thing here, the size is wrong, and you need a new compatible.

Thanks,
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

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Re: [PATCH 1/8] dt-bindings: fix for Allwinner H5 pinctrl's compatible

[Chen-Yu Tsai]

On Wed, Feb 8, 2017 at 6:00 PM, Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org> wrote:
> The compatible for Allwinner H5 pin controller is wrong written as
> allwinner,sun50i-h5-r-pinctrl, however, it's really a generic pinctrl
> rather than a "r" one.
>
> Fix this compatible string.
>
> Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>

Acked-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>

[linux-sunxi] [PATCH 1/8] dt-bindings: fix for Allwinner H5 pinctrl's compatible

[Chen-Yu Tsai]

On Wed, Feb 8, 2017 at 6:00 PM, Icenowy Zheng <icenowy@aosc.xyz> wrote:
> The compatible for Allwinner H5 pin controller is wrong written as
> allwinner,sun50i-h5-r-pinctrl, however, it's really a generic pinctrl
> rather than a "r" one.
>
> Fix this compatible string.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>

Acked-by: Chen-Yu Tsai <wens@csie.org>

Re: [linux-sunxi] [PATCH 1/8] dt-bindings: fix for Allwinner H5 pinctrl's compatible

[Chen-Yu Tsai]

On Wed, Feb 8, 2017 at 6:00 PM, Icenowy Zheng <icenowy@aosc.xyz> wrote:
> The compatible for Allwinner H5 pin controller is wrong written as
> allwinner,sun50i-h5-r-pinctrl, however, it's really a generic pinctrl
> rather than a "r" one.
>
> Fix this compatible string.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>

Acked-by: Chen-Yu Tsai <wens@csie.org>