From: Mark Rutland <mark.rutland@arm.com> To: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Simon Horman <horms@verge.net.au>, Magnus Damm <magnus.damm@gmail.com>, linux-renesas-soc@vger.kernel.org, Takeshi Kihara <takeshi.kihara.df@renesas.com>, linux-arm-kernel@lists.infradead.org, Dirk Behme <dirk.behme@gmail.com> Subject: Re: [PATCH v3] arm64: dts: r8a7795: Add Cortex-A53 CPU cores Date: Fri, 17 Feb 2017 18:07:35 +0000 [thread overview] Message-ID: <20170217180734.GA25876@leverpostej> (raw) In-Reply-To: <1487343849-32616-1-git-send-email-geert+renesas@glider.be> Hi, On Fri, Feb 17, 2017 at 04:04:09PM +0100, Geert Uytterhoeven wrote: > From: Takeshi Kihara <takeshi.kihara.df@renesas.com> > > This patch adds Cortex-A53 CPU cores to r8a7795 SoC for a total of 8 > cores (4 x Cortex-A57 + 4 x Cortex-A53). > interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; > + <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; > interrupt-affinity = <&a57_0>, > <&a57_1>, > <&a57_2>, > - <&a57_3>; > + <&a57_3>, > + <&a53_0>, > + <&a53_1>, > + <&a53_2>, > + <&a53_3>; > }; This isn't quite right; the A53 cores should have a separate PMU node. The PMU hardware is different across microarchitectures, and they must be handled separately. Thanks, Mark.
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From: mark.rutland@arm.com (Mark Rutland) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v3] arm64: dts: r8a7795: Add Cortex-A53 CPU cores Date: Fri, 17 Feb 2017 18:07:35 +0000 [thread overview] Message-ID: <20170217180734.GA25876@leverpostej> (raw) In-Reply-To: <1487343849-32616-1-git-send-email-geert+renesas@glider.be> Hi, On Fri, Feb 17, 2017 at 04:04:09PM +0100, Geert Uytterhoeven wrote: > From: Takeshi Kihara <takeshi.kihara.df@renesas.com> > > This patch adds Cortex-A53 CPU cores to r8a7795 SoC for a total of 8 > cores (4 x Cortex-A57 + 4 x Cortex-A53). > interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; > + <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; > interrupt-affinity = <&a57_0>, > <&a57_1>, > <&a57_2>, > - <&a57_3>; > + <&a57_3>, > + <&a53_0>, > + <&a53_1>, > + <&a53_2>, > + <&a53_3>; > }; This isn't quite right; the A53 cores should have a separate PMU node. The PMU hardware is different across microarchitectures, and they must be handled separately. Thanks, Mark.
next prev parent reply other threads:[~2017-02-17 18:07 UTC|newest] Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-02-17 15:04 [PATCH v3] arm64: dts: r8a7795: Add Cortex-A53 CPU cores Geert Uytterhoeven 2017-02-17 15:04 ` Geert Uytterhoeven 2017-02-17 18:07 ` Mark Rutland [this message] 2017-02-17 18:07 ` Mark Rutland 2017-02-23 14:07 ` Geert Uytterhoeven 2017-02-23 14:07 ` Geert Uytterhoeven
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