* [PATCH v3] arm64: dts: r8a7795: Add Cortex-A53 CPU cores
@ 2017-02-17 15:04 ` Geert Uytterhoeven
0 siblings, 0 replies; 6+ messages in thread
From: Geert Uytterhoeven @ 2017-02-17 15:04 UTC (permalink / raw)
To: Simon Horman, Magnus Damm
Cc: Dirk Behme, linux-renesas-soc, linux-arm-kernel, Takeshi Kihara,
Geert Uytterhoeven
From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
This patch adds Cortex-A53 CPU cores to r8a7795 SoC for a total of 8
cores (4 x Cortex-A57 + 4 x Cortex-A53).
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
[geert: Add power-domains and next-level-cache properties]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
This patch describes the hardware; actual enabling of the CPU depends on
the PSCI firmware.
With the current firmware version (v2.16.0), only the CA57 CPU cores are
enabled, hence this patch does not introduce undeterministic scheduling
behavior due to migration between big and LITTLE cores.
v3:
- Link recently added CPU nodes 100-103 to their L2 cache nodes,
v2:
- Rebased.
---
arch/arm64/boot/dts/renesas/r8a7795.dtsi | 58 ++++++++++++++++++++++++++++----
1 file changed, 51 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index 7f2434adb757498f..6148e514eb648288 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -73,6 +73,42 @@
enable-method = "psci";
};
+ a53_0: cpu@100 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x100>;
+ device_type = "cpu";
+ power-domains = <&sysc R8A7795_PD_CA53_CPU0>;
+ next-level-cache = <&L2_CA53>;
+ enable-method = "psci";
+ };
+
+ a53_1: cpu@101 {
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x101>;
+ device_type = "cpu";
+ power-domains = <&sysc R8A7795_PD_CA53_CPU1>;
+ next-level-cache = <&L2_CA53>;
+ enable-method = "psci";
+ };
+
+ a53_2: cpu@102 {
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x102>;
+ device_type = "cpu";
+ power-domains = <&sysc R8A7795_PD_CA53_CPU2>;
+ next-level-cache = <&L2_CA53>;
+ enable-method = "psci";
+ };
+
+ a53_3: cpu@103 {
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x103>;
+ device_type = "cpu";
+ power-domains = <&sysc R8A7795_PD_CA53_CPU3>;
+ next-level-cache = <&L2_CA53>;
+ enable-method = "psci";
+ };
+
L2_CA57: cache-controller@0 {
compatible = "cache";
reg = <0>;
@@ -166,7 +202,7 @@
<0x0 0xf1040000 0 0x20000>,
<0x0 0xf1060000 0 0x20000>;
interrupts = <GIC_PPI 9
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD 408>;
clock-names = "clk";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
@@ -307,23 +343,31 @@
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&a57_0>,
<&a57_1>,
<&a57_2>,
- <&a57_3>;
+ <&a57_3>,
+ <&a53_0>,
+ <&a53_1>,
+ <&a53_2>,
+ <&a53_3>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
};
cpg: clock-controller@e6150000 {
--
1.9.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v3] arm64: dts: r8a7795: Add Cortex-A53 CPU cores
@ 2017-02-17 15:04 ` Geert Uytterhoeven
0 siblings, 0 replies; 6+ messages in thread
From: Geert Uytterhoeven @ 2017-02-17 15:04 UTC (permalink / raw)
To: linux-arm-kernel
From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
This patch adds Cortex-A53 CPU cores to r8a7795 SoC for a total of 8
cores (4 x Cortex-A57 + 4 x Cortex-A53).
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
[geert: Add power-domains and next-level-cache properties]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
This patch describes the hardware; actual enabling of the CPU depends on
the PSCI firmware.
With the current firmware version (v2.16.0), only the CA57 CPU cores are
enabled, hence this patch does not introduce undeterministic scheduling
behavior due to migration between big and LITTLE cores.
v3:
- Link recently added CPU nodes 100-103 to their L2 cache nodes,
v2:
- Rebased.
---
arch/arm64/boot/dts/renesas/r8a7795.dtsi | 58 ++++++++++++++++++++++++++++----
1 file changed, 51 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index 7f2434adb757498f..6148e514eb648288 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -73,6 +73,42 @@
enable-method = "psci";
};
+ a53_0: cpu at 100 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x100>;
+ device_type = "cpu";
+ power-domains = <&sysc R8A7795_PD_CA53_CPU0>;
+ next-level-cache = <&L2_CA53>;
+ enable-method = "psci";
+ };
+
+ a53_1: cpu at 101 {
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x101>;
+ device_type = "cpu";
+ power-domains = <&sysc R8A7795_PD_CA53_CPU1>;
+ next-level-cache = <&L2_CA53>;
+ enable-method = "psci";
+ };
+
+ a53_2: cpu at 102 {
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x102>;
+ device_type = "cpu";
+ power-domains = <&sysc R8A7795_PD_CA53_CPU2>;
+ next-level-cache = <&L2_CA53>;
+ enable-method = "psci";
+ };
+
+ a53_3: cpu at 103 {
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x103>;
+ device_type = "cpu";
+ power-domains = <&sysc R8A7795_PD_CA53_CPU3>;
+ next-level-cache = <&L2_CA53>;
+ enable-method = "psci";
+ };
+
L2_CA57: cache-controller at 0 {
compatible = "cache";
reg = <0>;
@@ -166,7 +202,7 @@
<0x0 0xf1040000 0 0x20000>,
<0x0 0xf1060000 0 0x20000>;
interrupts = <GIC_PPI 9
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD 408>;
clock-names = "clk";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
@@ -307,23 +343,31 @@
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&a57_0>,
<&a57_1>,
<&a57_2>,
- <&a57_3>;
+ <&a57_3>,
+ <&a53_0>,
+ <&a53_1>,
+ <&a53_2>,
+ <&a53_3>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
};
cpg: clock-controller at e6150000 {
--
1.9.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v3] arm64: dts: r8a7795: Add Cortex-A53 CPU cores
2017-02-17 15:04 ` Geert Uytterhoeven
@ 2017-02-17 18:07 ` Mark Rutland
-1 siblings, 0 replies; 6+ messages in thread
From: Mark Rutland @ 2017-02-17 18:07 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Simon Horman, Magnus Damm, linux-renesas-soc, Takeshi Kihara,
linux-arm-kernel, Dirk Behme
Hi,
On Fri, Feb 17, 2017 at 04:04:09PM +0100, Geert Uytterhoeven wrote:
> From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
>
> This patch adds Cortex-A53 CPU cores to r8a7795 SoC for a total of 8
> cores (4 x Cortex-A57 + 4 x Cortex-A53).
> interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
> + <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-affinity = <&a57_0>,
> <&a57_1>,
> <&a57_2>,
> - <&a57_3>;
> + <&a57_3>,
> + <&a53_0>,
> + <&a53_1>,
> + <&a53_2>,
> + <&a53_3>;
> };
This isn't quite right; the A53 cores should have a separate PMU node.
The PMU hardware is different across microarchitectures, and they must
be handled separately.
Thanks,
Mark.
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v3] arm64: dts: r8a7795: Add Cortex-A53 CPU cores
@ 2017-02-17 18:07 ` Mark Rutland
0 siblings, 0 replies; 6+ messages in thread
From: Mark Rutland @ 2017-02-17 18:07 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
On Fri, Feb 17, 2017 at 04:04:09PM +0100, Geert Uytterhoeven wrote:
> From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
>
> This patch adds Cortex-A53 CPU cores to r8a7795 SoC for a total of 8
> cores (4 x Cortex-A57 + 4 x Cortex-A53).
> interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
> + <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-affinity = <&a57_0>,
> <&a57_1>,
> <&a57_2>,
> - <&a57_3>;
> + <&a57_3>,
> + <&a53_0>,
> + <&a53_1>,
> + <&a53_2>,
> + <&a53_3>;
> };
This isn't quite right; the A53 cores should have a separate PMU node.
The PMU hardware is different across microarchitectures, and they must
be handled separately.
Thanks,
Mark.
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v3] arm64: dts: r8a7795: Add Cortex-A53 CPU cores
2017-02-17 18:07 ` Mark Rutland
@ 2017-02-23 14:07 ` Geert Uytterhoeven
-1 siblings, 0 replies; 6+ messages in thread
From: Geert Uytterhoeven @ 2017-02-23 14:07 UTC (permalink / raw)
To: Mark Rutland
Cc: Geert Uytterhoeven, Simon Horman, Magnus Damm, Linux-Renesas,
Takeshi Kihara, linux-arm-kernel, Dirk Behme
Hi Mark,
On Fri, Feb 17, 2017 at 7:07 PM, Mark Rutland <mark.rutland@arm.com> wrote:
> On Fri, Feb 17, 2017 at 04:04:09PM +0100, Geert Uytterhoeven wrote:
>> From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
>>
>> This patch adds Cortex-A53 CPU cores to r8a7795 SoC for a total of 8
>> cores (4 x Cortex-A57 + 4 x Cortex-A53).
>
>> interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
>> <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
>> <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
>> - <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
>> + <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
>> interrupt-affinity = <&a57_0>,
>> <&a57_1>,
>> <&a57_2>,
>> - <&a57_3>;
>> + <&a57_3>,
>> + <&a53_0>,
>> + <&a53_1>,
>> + <&a53_2>,
>> + <&a53_3>;
>> };
>
> This isn't quite right; the A53 cores should have a separate PMU node.
>
> The PMU hardware is different across microarchitectures, and they must
> be handled separately.
Oops, the original patch predated the evolution of "arm,armv8-pmuv3" into
separate "arm,cortex-a57-pmu" and "arm,cortex-a53-pmu".
Will fix...
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v3] arm64: dts: r8a7795: Add Cortex-A53 CPU cores
@ 2017-02-23 14:07 ` Geert Uytterhoeven
0 siblings, 0 replies; 6+ messages in thread
From: Geert Uytterhoeven @ 2017-02-23 14:07 UTC (permalink / raw)
To: linux-arm-kernel
Hi Mark,
On Fri, Feb 17, 2017 at 7:07 PM, Mark Rutland <mark.rutland@arm.com> wrote:
> On Fri, Feb 17, 2017 at 04:04:09PM +0100, Geert Uytterhoeven wrote:
>> From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
>>
>> This patch adds Cortex-A53 CPU cores to r8a7795 SoC for a total of 8
>> cores (4 x Cortex-A57 + 4 x Cortex-A53).
>
>> interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
>> <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
>> <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
>> - <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
>> + <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
>> interrupt-affinity = <&a57_0>,
>> <&a57_1>,
>> <&a57_2>,
>> - <&a57_3>;
>> + <&a57_3>,
>> + <&a53_0>,
>> + <&a53_1>,
>> + <&a53_2>,
>> + <&a53_3>;
>> };
>
> This isn't quite right; the A53 cores should have a separate PMU node.
>
> The PMU hardware is different across microarchitectures, and they must
> be handled separately.
Oops, the original patch predated the evolution of "arm,armv8-pmuv3" into
separate "arm,cortex-a57-pmu" and "arm,cortex-a53-pmu".
Will fix...
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2017-02-23 14:07 UTC | newest]
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2017-02-17 15:04 [PATCH v3] arm64: dts: r8a7795: Add Cortex-A53 CPU cores Geert Uytterhoeven
2017-02-17 15:04 ` Geert Uytterhoeven
2017-02-17 18:07 ` Mark Rutland
2017-02-17 18:07 ` Mark Rutland
2017-02-23 14:07 ` Geert Uytterhoeven
2017-02-23 14:07 ` Geert Uytterhoeven
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