From: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org> To: Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>, Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>, Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>, Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>, Catalin Marinas <catalin.marinas-5wv7dgnIgG8@public.gmane.org>, Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org> Cc: linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org, Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org> Subject: [PATCH 5/5] pinctrl: sunxi: Add A64 R_PIO controller support Date: Wed, 1 Mar 2017 01:24:44 +0800 [thread overview] Message-ID: <20170228172444.59655-5-icenowy@aosc.xyz> (raw) In-Reply-To: <20170228172444.59655-1-icenowy-ymACFijhrKM@public.gmane.org> The A64 has a R_PIO pin controller, similar to the one found on the H3 SoC. Add support for the pins controlled by the R_PIO controller. Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org> --- drivers/pinctrl/sunxi/Kconfig | 5 + drivers/pinctrl/sunxi/Makefile | 1 + drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c | 143 +++++++++++++++++++++++++++ 3 files changed, 149 insertions(+) create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig index 92325736d953..0738b0df5a0b 100644 --- a/drivers/pinctrl/sunxi/Kconfig +++ b/drivers/pinctrl/sunxi/Kconfig @@ -69,6 +69,11 @@ config PINCTRL_SUN50I_A64 def_bool ARM64 && ARCH_SUNXI select PINCTRL_SUNXI +config PINCTRL_SUN50I_A64_R + def_bool ARM64 && ARCH_SUNXI + depends on RESET_CONTROLLER + select PINCTRL_SUNXI + config PINCTRL_SUN50I_H5 def_bool ARM64 && ARCH_SUNXI select PINCTRL_SUNXI diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile index 04ccb88ebd5f..df4ccd6cd44c 100644 --- a/drivers/pinctrl/sunxi/Makefile +++ b/drivers/pinctrl/sunxi/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_PINCTRL_SUN8I_A23) += pinctrl-sun8i-a23.o obj-$(CONFIG_PINCTRL_SUN8I_A23_R) += pinctrl-sun8i-a23-r.o obj-$(CONFIG_PINCTRL_SUN8I_A33) += pinctrl-sun8i-a33.o obj-$(CONFIG_PINCTRL_SUN50I_A64) += pinctrl-sun50i-a64.o +obj-$(CONFIG_PINCTRL_SUN50I_A64_R) += pinctrl-sun50i-a64-r.o obj-$(CONFIG_PINCTRL_SUN8I_A83T) += pinctrl-sun8i-a83t.o obj-$(CONFIG_PINCTRL_SUN8I_H3) += pinctrl-sun8i-h3.o obj-$(CONFIG_PINCTRL_SUN8I_H3_R) += pinctrl-sun8i-h3-r.o diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c new file mode 100644 index 000000000000..90996a63689b --- /dev/null +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c @@ -0,0 +1,143 @@ +/* + * Allwinner A64 SoCs special pins pinctrl driver. + * + * Based on pinctrl-sun8i-a23-r.c + * + * Copyright (C) 2016 Icenowy Zheng + * Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org> + * + * Copyright (C) 2014 Chen-Yu Tsai + * Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org> + * + * Copyright (C) 2014 Boris Brezillon + * Boris Brezillon <boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> + * + * Copyright (C) 2014 Maxime Ripard + * Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/platform_device.h> +#include <linux/reset.h> + +#include "pinctrl-sunxi.h" + +static const struct sunxi_desc_pin sun50i_a64_r_pins[] = { + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_rsb"), /* SCK */ + SUNXI_FUNCTION(0x3, "s_i2c"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PL_EINT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_rsb"), /* SDA */ + SUNXI_FUNCTION(0x3, "s_i2c"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PL_EINT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_uart"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PL_EINT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_uart"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PL_EINT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "s_jtag"), /* MS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PL_EINT4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "s_jtag"), /* CK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PL_EINT5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "s_jtag"), /* DO */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PL_EINT6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "s_jtag"), /* DI */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PL_EINT7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_i2c"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PL_EINT8 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_i2c"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PL_EINT9 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_pwm"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PL_EINT10 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_cir_rx"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PL_EINT11 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PL_EINT12 */ +}; + +static const struct sunxi_pinctrl_desc sun50i_a64_r_pinctrl_data = { + .pins = sun50i_a64_r_pins, + .npins = ARRAY_SIZE(sun50i_a64_r_pins), + .pin_base = PL_BASE, + .irq_banks = 1, +}; + +static int sun50i_a64_r_pinctrl_probe(struct platform_device *pdev) +{ + struct reset_control *rstc; + int ret; + + rstc = devm_reset_control_get(&pdev->dev, NULL); + if (IS_ERR(rstc)) { + dev_err(&pdev->dev, "Reset controller missing\n"); + return PTR_ERR(rstc); + } + + ret = reset_control_deassert(rstc); + if (ret) + return ret; + + ret = sunxi_pinctrl_init(pdev, + &sun50i_a64_r_pinctrl_data); + + if (ret) + reset_control_assert(rstc); + + return ret; +} + +static const struct of_device_id sun50i_a64_r_pinctrl_match[] = { + { .compatible = "allwinner,sun50i-a64-r-pinctrl", }, + {} +}; + +static struct platform_driver sun50i_a64_r_pinctrl_driver = { + .probe = sun50i_a64_r_pinctrl_probe, + .driver = { + .name = "sun50i-a64-r-pinctrl", + .of_match_table = sun50i_a64_r_pinctrl_match, + }, +}; +builtin_platform_driver(sun50i_a64_r_pinctrl_driver); -- 2.11.1
WARNING: multiple messages have this Message-ID (diff)
From: icenowy@aosc.xyz (Icenowy Zheng) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 5/5] pinctrl: sunxi: Add A64 R_PIO controller support Date: Wed, 1 Mar 2017 01:24:44 +0800 [thread overview] Message-ID: <20170228172444.59655-5-icenowy@aosc.xyz> (raw) In-Reply-To: <20170228172444.59655-1-icenowy@aosc.xyz> The A64 has a R_PIO pin controller, similar to the one found on the H3 SoC. Add support for the pins controlled by the R_PIO controller. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> --- drivers/pinctrl/sunxi/Kconfig | 5 + drivers/pinctrl/sunxi/Makefile | 1 + drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c | 143 +++++++++++++++++++++++++++ 3 files changed, 149 insertions(+) create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig index 92325736d953..0738b0df5a0b 100644 --- a/drivers/pinctrl/sunxi/Kconfig +++ b/drivers/pinctrl/sunxi/Kconfig @@ -69,6 +69,11 @@ config PINCTRL_SUN50I_A64 def_bool ARM64 && ARCH_SUNXI select PINCTRL_SUNXI +config PINCTRL_SUN50I_A64_R + def_bool ARM64 && ARCH_SUNXI + depends on RESET_CONTROLLER + select PINCTRL_SUNXI + config PINCTRL_SUN50I_H5 def_bool ARM64 && ARCH_SUNXI select PINCTRL_SUNXI diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile index 04ccb88ebd5f..df4ccd6cd44c 100644 --- a/drivers/pinctrl/sunxi/Makefile +++ b/drivers/pinctrl/sunxi/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_PINCTRL_SUN8I_A23) += pinctrl-sun8i-a23.o obj-$(CONFIG_PINCTRL_SUN8I_A23_R) += pinctrl-sun8i-a23-r.o obj-$(CONFIG_PINCTRL_SUN8I_A33) += pinctrl-sun8i-a33.o obj-$(CONFIG_PINCTRL_SUN50I_A64) += pinctrl-sun50i-a64.o +obj-$(CONFIG_PINCTRL_SUN50I_A64_R) += pinctrl-sun50i-a64-r.o obj-$(CONFIG_PINCTRL_SUN8I_A83T) += pinctrl-sun8i-a83t.o obj-$(CONFIG_PINCTRL_SUN8I_H3) += pinctrl-sun8i-h3.o obj-$(CONFIG_PINCTRL_SUN8I_H3_R) += pinctrl-sun8i-h3-r.o diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c new file mode 100644 index 000000000000..90996a63689b --- /dev/null +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c @@ -0,0 +1,143 @@ +/* + * Allwinner A64 SoCs special pins pinctrl driver. + * + * Based on pinctrl-sun8i-a23-r.c + * + * Copyright (C) 2016 Icenowy Zheng + * Icenowy Zheng <icenowy@aosc.xyz> + * + * Copyright (C) 2014 Chen-Yu Tsai + * Chen-Yu Tsai <wens@csie.org> + * + * Copyright (C) 2014 Boris Brezillon + * Boris Brezillon <boris.brezillon@free-electrons.com> + * + * Copyright (C) 2014 Maxime Ripard + * Maxime Ripard <maxime.ripard@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/platform_device.h> +#include <linux/reset.h> + +#include "pinctrl-sunxi.h" + +static const struct sunxi_desc_pin sun50i_a64_r_pins[] = { + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_rsb"), /* SCK */ + SUNXI_FUNCTION(0x3, "s_i2c"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PL_EINT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_rsb"), /* SDA */ + SUNXI_FUNCTION(0x3, "s_i2c"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PL_EINT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_uart"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PL_EINT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_uart"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PL_EINT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "s_jtag"), /* MS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PL_EINT4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "s_jtag"), /* CK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PL_EINT5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "s_jtag"), /* DO */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PL_EINT6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "s_jtag"), /* DI */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PL_EINT7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_i2c"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PL_EINT8 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_i2c"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PL_EINT9 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_pwm"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PL_EINT10 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_cir_rx"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PL_EINT11 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PL_EINT12 */ +}; + +static const struct sunxi_pinctrl_desc sun50i_a64_r_pinctrl_data = { + .pins = sun50i_a64_r_pins, + .npins = ARRAY_SIZE(sun50i_a64_r_pins), + .pin_base = PL_BASE, + .irq_banks = 1, +}; + +static int sun50i_a64_r_pinctrl_probe(struct platform_device *pdev) +{ + struct reset_control *rstc; + int ret; + + rstc = devm_reset_control_get(&pdev->dev, NULL); + if (IS_ERR(rstc)) { + dev_err(&pdev->dev, "Reset controller missing\n"); + return PTR_ERR(rstc); + } + + ret = reset_control_deassert(rstc); + if (ret) + return ret; + + ret = sunxi_pinctrl_init(pdev, + &sun50i_a64_r_pinctrl_data); + + if (ret) + reset_control_assert(rstc); + + return ret; +} + +static const struct of_device_id sun50i_a64_r_pinctrl_match[] = { + { .compatible = "allwinner,sun50i-a64-r-pinctrl", }, + {} +}; + +static struct platform_driver sun50i_a64_r_pinctrl_driver = { + .probe = sun50i_a64_r_pinctrl_probe, + .driver = { + .name = "sun50i-a64-r-pinctrl", + .of_match_table = sun50i_a64_r_pinctrl_match, + }, +}; +builtin_platform_driver(sun50i_a64_r_pinctrl_driver); -- 2.11.1
next prev parent reply other threads:[~2017-02-28 17:24 UTC|newest] Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-02-28 17:24 [PATCH 1/5] pinctrl: sunxi: refactor pinctrl choice selecting for ARM64 Icenowy Zheng 2017-02-28 17:24 ` Icenowy Zheng [not found] ` <20170228172444.59655-1-icenowy-ymACFijhrKM@public.gmane.org> 2017-02-28 17:24 ` [PATCH 2/5] arm64: only select PINCTRL_SUNXI for Allwinner platforms Icenowy Zheng 2017-02-28 17:24 ` Icenowy Zheng [not found] ` <20170228172444.59655-2-icenowy-ymACFijhrKM@public.gmane.org> 2017-02-28 18:19 ` Andre Przywara 2017-02-28 18:19 ` [linux-sunxi] " Andre Przywara 2017-02-28 18:19 ` Andre Przywara [not found] ` <c878ba53-a33a-e042-2d65-11f86a47b844-5wv7dgnIgG8@public.gmane.org> 2017-02-28 18:57 ` Icenowy Zheng 2017-02-28 18:57 ` [linux-sunxi] " Icenowy Zheng 2017-02-28 17:24 ` [PATCH 3/5] dt-bindings: fix for Allwinner H5 pinctrl's compatible Icenowy Zheng 2017-02-28 17:24 ` Icenowy Zheng 2017-02-28 17:24 ` [PATCH 4/5] dt: bindings: add binding for Allwinner A64 R_PIO pinctrl Icenowy Zheng 2017-02-28 17:24 ` Icenowy Zheng 2017-02-28 17:24 ` Icenowy Zheng [this message] 2017-02-28 17:24 ` [PATCH 5/5] pinctrl: sunxi: Add A64 R_PIO controller support Icenowy Zheng [not found] ` <20170228172444.59655-5-icenowy-ymACFijhrKM@public.gmane.org> 2017-02-28 18:29 ` Andre Przywara 2017-02-28 18:29 ` [linux-sunxi] " Andre Przywara 2017-02-28 18:29 ` Andre Przywara [not found] ` <b04ad85d-698b-56b4-6b82-1791bd7b14b7-5wv7dgnIgG8@public.gmane.org> 2017-02-28 18:58 ` Icenowy Zheng 2017-02-28 18:58 ` [linux-sunxi] " Icenowy Zheng 2017-03-01 2:34 ` Chen-Yu Tsai 2017-03-01 2:34 ` [linux-sunxi] " Chen-Yu Tsai 2017-03-01 2:34 ` Chen-Yu Tsai 2017-02-28 18:17 ` [PATCH 1/5] pinctrl: sunxi: refactor pinctrl choice selecting for ARM64 Andre Przywara 2017-02-28 18:17 ` [linux-sunxi] " Andre Przywara 2017-02-28 18:17 ` Andre Przywara [not found] ` <488811a1-b64f-c435-e919-7f83dc107697-5wv7dgnIgG8@public.gmane.org> 2017-02-28 18:55 ` Icenowy Zheng 2017-02-28 18:55 ` [linux-sunxi] " Icenowy Zheng [not found] ` <345321488308121-kPAM4p2RxX5uio3avFS2gg@public.gmane.org> 2017-03-01 2:38 ` Chen-Yu Tsai 2017-03-01 2:38 ` [linux-sunxi] " Chen-Yu Tsai 2017-03-01 2:38 ` Chen-Yu Tsai 2017-03-01 2:48 [PATCH 5/5] pinctrl: sunxi: Add A64 R_PIO controller support Icenowy Zheng
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