[PATCH 00/15] DC Patches Feb 28, 2017

[PATCH 00/15] DC Patches Feb 28, 2017

[Harry Wentland]

* Block legacy gamma on 10-bit, only supported on 8
* DMCU PSR refactor
* Bunch of other changes and fixes
* Bunch of warning fixes and enabling warnings as errors,
  aka DC-less-shouty.

Amy Zhang (1):
  drm/amd/display: DMCU PSR Refactor

Charlene Liu (2):
  drm/amd/display: HDMI deep color mode audio issue
  drm/amd/display: 420 clock divided by 2 twice

Dmytro Laktyushkin (6):
  drm/amd/display: rename bandwidth_calcs.c to dce_calcs.c
  drm/amd/display: add scaler coefficients for 64 phase 5-8 taps
  drm/amd/display: remove apply_clk_constraints, used validate_bandwidth
    universally
  drm/amd/display: bandwidth update fix
  drm/amd/display: move visual confirm recout adjustment to scaler
  drm/amd/display: fix dce100_validate_bandwidth return value

Harry Wentland (4):
  drm/amd/display: Fix warnings in amdgpu_dm
  drm/amd/display: Fix warnings in DC
  drm/amd/display: Some more warning fixes
  drm/amd/display: Enable warnings as errors

Jordan Lazare (1):
  drm/amd/display: Fix gamma colour corruption for 10 bit surfaces

Leon Elazar (1):
  drm/amd/display: Surface Validation Fixes + Audio Mask

 drivers/gpu/drm/amd/display/Makefile               |   2 +
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c    |   2 +-
 .../dc/calcs/{bandwidth_calcs.c => dce_calcs.c}    |   0
 drivers/gpu/drm/amd/display/dc/core/dc.c           | 228 +-------
 drivers/gpu/drm/amd/display/dc/core/dc_link.c      |  23 +-
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c   |   2 +-
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c  |   9 +-
 drivers/gpu/drm/amd/display/dc/core/dc_stream.c    |  11 +-
 drivers/gpu/drm/amd/display/dc/core/dc_surface.c   |   2 +-
 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c       |   1 -
 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c     |   9 +
 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h     |   1 +
 .../gpu/drm/amd/display/dc/dce/dce_clock_source.c  |   1 -
 drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c    |   6 +-
 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c      | 208 +++++++
 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h      | 107 +++-
 .../gpu/drm/amd/display/dc/dce/dce_link_encoder.c  | 280 ++--------
 .../gpu/drm/amd/display/dc/dce/dce_link_encoder.h  |  73 +--
 .../gpu/drm/amd/display/dc/dce/dce_scl_filters.c   | 608 +++++++++++++++++++++
 .../drm/amd/display/dc/dce/dce_stream_encoder.c    |  26 +-
 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c |   6 +
 .../amd/display/dc/dce100/dce100_hw_sequencer.c    |  15 +-
 .../drm/amd/display/dc/dce100/dce100_resource.c    |  10 +-
 .../amd/display/dc/dce110/dce110_hw_sequencer.c    | 312 ++++++-----
 .../drm/amd/display/dc/dce110/dce110_resource.c    |  29 +-
 .../display/dc/dce110/dce110_timing_generator_v.c  |   1 -
 .../drm/amd/display/dc/dce110/dce110_transform_v.c |   6 +
 .../drm/amd/display/dc/dce112/dce112_resource.c    |  22 +-
 .../drm/amd/display/dc/dce112/dce112_resource.h    |   2 +-
 drivers/gpu/drm/amd/display/dc/dce80/Makefile      |   3 +-
 .../drm/amd/display/dc/dce80/dce80_hw_sequencer.c  |  16 +-
 .../gpu/drm/amd/display/dc/dce80/dce80_ipp_gamma.c |  71 ---
 .../gpu/drm/amd/display/dc/dce80/dce80_resource.c  |   8 +-
 drivers/gpu/drm/amd/display/dc/inc/core_status.h   |   1 -
 drivers/gpu/drm/amd/display/dc/inc/core_types.h    |   6 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h       |   4 +
 .../gpu/drm/amd/display/dc/inc/hw/link_encoder.h   |   9 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/transform.h  |   4 +
 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h  |   9 +-
 39 files changed, 1299 insertions(+), 834 deletions(-)
 rename drivers/gpu/drm/amd/display/dc/calcs/{bandwidth_calcs.c => dce_calcs.c} (100%)
 delete mode 100644 drivers/gpu/drm/amd/display/dc/dce80/dce80_ipp_gamma.c

-- 
2.9.3

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[PATCH 01/15] drm/amd/display: rename bandwidth_calcs.c to dce_calcs.c

[Harry Wentland]

From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>

Change-Id: I78acf3d71d7d3cd838ad0d355d0f16c9f0d086f1
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Eagle Yeh <eagle.yeh@amd.com>
---
 drivers/gpu/drm/amd/display/dc/calcs/{bandwidth_calcs.c => dce_calcs.c} | 0
 1 file changed, 0 insertions(+), 0 deletions(-)
 rename drivers/gpu/drm/amd/display/dc/calcs/{bandwidth_calcs.c => dce_calcs.c} (100%)

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/bandwidth_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
similarity index 100%
rename from drivers/gpu/drm/amd/display/dc/calcs/bandwidth_calcs.c
rename to drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
-- 
2.9.3

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[PATCH 02/15] drm/amd/display: HDMI deep color mode audio issue

[Harry Wentland]

From: Charlene Liu <charlene.liu@amd.com>

Change-Id: Ie6abd89247bc2248063a57003d9841898e710502
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c  |  9 ++++++--
 drivers/gpu/drm/amd/display/dc/core/dc_stream.c    | 11 +++++----
 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c     |  9 ++++++++
 .../gpu/drm/amd/display/dc/dce/dce_clock_source.c  |  1 -
 .../drm/amd/display/dc/dce/dce_stream_encoder.c    | 26 +++++-----------------
 .../amd/display/dc/dce110/dce110_hw_sequencer.c    | 18 ---------------
 6 files changed, 28 insertions(+), 46 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 4d556b379524..407ce60f253e 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1101,9 +1101,14 @@ enum dc_status resource_map_pool_resources(
 	for (i = 0; i < context->stream_count; i++) {
 		struct core_stream *stream = context->streams[i];
 
-		if (!resource_is_stream_unchanged(dc->current_context, stream))
+		if (!resource_is_stream_unchanged(dc->current_context, stream)) {
+			if (stream != NULL && dc->current_context->streams[i] != NULL) {
+				stream->bit_depth_params =
+						dc->current_context->streams[i]->bit_depth_params;
+				stream->clamping = dc->current_context->streams[i]->clamping;
 			continue;
-
+		}
+	}
 		/* mark resources used for stream that is already active */
 		for (j = 0; j < MAX_PIPES; j++) {
 			struct pipe_ctx *pipe_ctx =
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index e1f579bcd789..4e1a933be021 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -305,7 +305,7 @@ void dc_stream_log(
 
 	dm_logger_write(dm_logger,
 			log_type,
-			"core_stream 0x%x: src: %d, %d, %d, %d; dst: %d, %d, %d, %d;\n",
+			"core_stream 0x%x: src: %d, %d, %d, %d; dst: %d, %d, %d, %d, colorSpace:%d\n",
 			core_stream,
 			core_stream->public.src.x,
 			core_stream->public.src.y,
@@ -314,13 +314,16 @@ void dc_stream_log(
 			core_stream->public.dst.x,
 			core_stream->public.dst.y,
 			core_stream->public.dst.width,
-			core_stream->public.dst.height);
+			core_stream->public.dst.height,
+			core_stream->public.output_color_space);
 	dm_logger_write(dm_logger,
 			log_type,
-			"\tpix_clk_khz: %d, h_total: %d, v_total: %d\n",
+			"\tpix_clk_khz: %d, h_total: %d, v_total: %d, pixelencoder:%d, displaycolorDepth:%d\n",
 			core_stream->public.timing.pix_clk_khz,
 			core_stream->public.timing.h_total,
-			core_stream->public.timing.v_total);
+			core_stream->public.timing.v_total,
+			core_stream->public.timing.pixel_encoding,
+			core_stream->public.timing.display_color_depth);
 	dm_logger_write(dm_logger,
 			log_type,
 			"\tsink name: %s, serial: %d\n",
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
index 596e039ee315..7f52e39ec92a 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
@@ -773,6 +773,15 @@ void dce_aud_wall_dto_setup(
 			crtc_info->calculated_pixel_clock,
 			&clock_info);
 
+		dm_logger_write(audio->ctx->logger, LOG_HW_SET_MODE,\
+				"\n************************%s:Input::requested_pixel_clock = %d"\
+				"calculated_pixel_clock =%d\n"\
+				"audio_dto_module = %d audio_dto_phase =%d \n\n", __func__,\
+				crtc_info->requested_pixel_clock,\
+				crtc_info->calculated_pixel_clock,\
+				clock_info.audio_dto_module,\
+				clock_info.audio_dto_phase);
+
 		/* On TN/SI, Program DTO source select and DTO select before
 		programming DTO modulo and DTO phase. These bits must be
 		programmed first, otherwise there will be no HDMI audio at boot
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
index 26742e038274..a2a2ecf8d077 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
@@ -874,7 +874,6 @@ static bool dce110_program_pix_clk(
 			bp_pc_params.flags.SET_XTALIN_REF_SRC =
 							!pll_settings->use_external_clk;
 			if (pix_clk_params->flags.SUPPORT_YCBCR420) {
-				bp_pc_params.target_pixel_clock = pll_settings->actual_pix_clk / 2;
 				bp_pc_params.flags.SUPPORT_YUV_420 = 1;
 			}
 		}
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
index e4092fd458a1..d6662fa2f4e1 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
@@ -873,22 +873,6 @@ static const struct audio_clock_info audio_clock_info_table[16] = {
 	{59400, 3072, 445500, 9408, 990000, 6144, 594000}
 };
 
-static const struct audio_clock_info audio_clock_info_table_30bpc[14] = {
-	{2517, 9152, 70312, 14014, 78125, 9152, 46875},
-	{2518, 9152, 70312, 14014, 78125, 9152, 46875},
-	{2520, 4096, 31500, 6272, 35000, 6144, 31500},
-	{2700, 4096, 33750, 6272, 37500, 6144, 33750},
-	{2702, 8192, 67567, 12544, 75075, 8192, 45045},
-	{2703, 8192, 67567, 12544, 75075, 8192, 45045},
-	{5400, 4096, 67500, 6272, 75000, 6144, 67500},
-	{5405, 8192, 135135, 6272, 75075, 8192, 90090},
-	{7417, 11648, 263672, 17836, 292969, 11648, 175181},
-	{7425, 8192, 185625,  6272, 103125, 12288, 185625},
-	{14835, 11648, 527344, 17836, 585938, 11648, 351563},
-	{14850, 4096, 185625, 6272, 206250, 6144, 185625},
-	{29670, 11648, 527344, 17836, 585938, 11648, 703125},
-	{29700, 6144, 556875, 4704, 309375, 5120, 309375}
-};
 static const struct audio_clock_info audio_clock_info_table_36bpc[14] = {
 	{2517,  9152,  84375,  7007,  48875,  9152,  56250},
 	{2518,  9152,  84375,  7007,  48875,  9152,  56250},
@@ -1005,11 +989,6 @@ bool get_audio_clock_info(
 		audio_array_size = ARRAY_SIZE(
 				audio_clock_info_table_36bpc);
 		break;
-	case COLOR_DEPTH_101010:
-		clock_info = audio_clock_info_table_30bpc;
-		audio_array_size = ARRAY_SIZE(
-				audio_clock_info_table_30bpc);
-		break;
 	default:
 		clock_info = audio_clock_info_table;
 		audio_array_size = ARRAY_SIZE(
@@ -1114,6 +1093,11 @@ static void dce110_se_setup_hdmi_audio(
 		crtc_info->requested_pixel_clock,
 		crtc_info->calculated_pixel_clock,
 		&audio_clock_info)) {
+		dm_logger_write(enc->ctx->logger, LOG_HW_SET_MODE,
+				"\n*********************%s:Input::requested_pixel_clock = %d"\
+				"calculated_pixel_clock = %d \n", __func__,\
+				crtc_info->requested_pixel_clock,\
+				crtc_info->calculated_pixel_clock);
 
 		/* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */
 		REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 6915cc46754b..2f68bf20dfe2 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -873,25 +873,7 @@ static void build_audio_output(
 					audio_output->crtc_info.requested_pixel_clock/2;
 			audio_output->crtc_info.calculated_pixel_clock =
 					pipe_ctx->pix_clk_params.requested_pix_clk/2;
-		}
 
-		if (pipe_ctx->pix_clk_params.pixel_encoding != PIXEL_ENCODING_YCBCR422) {
-			switch (pipe_ctx->pix_clk_params.color_depth) {
-			case COLOR_DEPTH_888:
-				break;
-			case COLOR_DEPTH_101010:
-				audio_output->crtc_info.calculated_pixel_clock = (audio_output->crtc_info.calculated_pixel_clock * 30) / 24;
-			break;
-			case COLOR_DEPTH_121212:
-				audio_output->crtc_info.calculated_pixel_clock = (audio_output->crtc_info.calculated_pixel_clock * 36) / 24;
-			break;
-			case COLOR_DEPTH_161616:
-				audio_output->crtc_info.calculated_pixel_clock = (audio_output->crtc_info.calculated_pixel_clock * 48) / 24;
-			break;
-			default:
-				ASSERT(0);
-			break;
-			}
 		}
 	}
 
-- 
2.9.3

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[PATCH 03/15] drm/amd/display: 420 clock divided by 2 twice

[Harry Wentland]

From: Charlene Liu <charlene.liu@amd.com>

Change-Id: I1bd1e091f1e9e3915997d3f216eadd429b605563
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
index 478c8d27f3bd..cd3942df70a7 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
@@ -780,6 +780,9 @@ static void get_pixel_clock_parameters(
 	if (stream->public.timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) {
 		pixel_clk_params->color_depth = COLOR_DEPTH_888;
 	}
+	if (stream->public.timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
+		pixel_clk_params->requested_pix_clk  = pixel_clk_params->requested_pix_clk / 2;
+	}
 }
 
 void dce110_resource_build_bit_depth_reduction_params(
-- 
2.9.3

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[PATCH 04/15] drm/amd/display: DMCU PSR Refactor

[Harry Wentland]

From: Amy Zhang <Amy.Zhang@amd.com>

- Move PSR programming from link encoder to dmcu

Change-Id: I90b7917e2f236deeb2aac32559c27b25f3da997a
Signed-off-by: Amy Zhang <Amy.Zhang@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c      |  21 +-
 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c      | 208 +++++++++++++++
 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h      | 107 +++++++-
 .../gpu/drm/amd/display/dc/dce/dce_link_encoder.c  | 280 +++------------------
 .../gpu/drm/amd/display/dc/dce/dce_link_encoder.h  |  73 +-----
 drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h       |   4 +
 .../gpu/drm/amd/display/dc/inc/hw/link_encoder.h   |   9 +-
 7 files changed, 376 insertions(+), 326 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 2b929393f68a..8eb6b342a49d 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -40,6 +40,7 @@
 #include "abm.h"
 #include "fixed31_32.h"
 #include "dpcd_defs.h"
+#include "dmcu.h"
 
 #include "dce/dce_11_0_d.h"
 #include "dce/dce_11_0_enum.h"
@@ -1433,28 +1434,33 @@ bool dc_link_set_backlight_level(const struct dc_link *dc_link, uint32_t level,
 bool dc_link_set_psr_enable(const struct dc_link *dc_link, bool enable)
 {
 	struct core_link *link = DC_LINK_TO_CORE(dc_link);
+	struct dc_context *ctx = link->ctx;
+	struct core_dc *core_dc = DC_TO_CORE(ctx->dc);
+	struct dmcu *dmcu = core_dc->res_pool->dmcu;
+
+	if (dmcu != NULL && dc_link->psr_caps.psr_version > 0)
+		dmcu->funcs->set_psr_enable(dmcu, enable);
 
-	if (dc_link != NULL && dc_link->psr_caps.psr_version > 0)
-		link->link_enc->funcs->set_dmcu_psr_enable(link->link_enc,
-								enable);
 	return true;
 }
 
 bool dc_link_setup_psr(const struct dc_link *dc_link,
 		const struct dc_stream *stream)
 {
-
 	struct core_link *link = DC_LINK_TO_CORE(dc_link);
 	struct dc_context *ctx = link->ctx;
 	struct core_dc *core_dc = DC_TO_CORE(ctx->dc);
+	struct dmcu *dmcu = core_dc->res_pool->dmcu;
 	struct core_stream *core_stream = DC_STREAM_TO_CORE(stream);
-	struct psr_dmcu_context psr_context = {0};
+	struct psr_context psr_context = {0};
 	int i;
 
 	psr_context.controllerId = CONTROLLER_ID_UNDEFINED;
 
 
-	if (dc_link != NULL && dc_link->psr_caps.psr_version > 0) {
+	if (dc_link != NULL &&
+		dmcu != NULL &&
+		dc_link->psr_caps.psr_version > 0) {
 		/* updateSinkPsrDpcdConfig*/
 		union dpcd_psr_configuration psr_configuration;
 
@@ -1552,8 +1558,7 @@ bool dc_link_setup_psr(const struct dc_link *dc_link,
 		 */
 		psr_context.frame_delay = 0;
 
-		link->link_enc->funcs->setup_dmcu_psr
-			(link->link_enc, &psr_context);
+		dmcu->funcs->setup_psr(dmcu, link, &psr_context);
 		return true;
 	} else
 		return false;
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
index eb0e95f57aa9..44eeeeb888fe 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
@@ -23,6 +23,8 @@
  *
  */
 
+#include "core_types.h"
+#include "link_encoder.h"
 #include "dce_dmcu.h"
 #include "dm_services.h"
 #include "reg_helper.h"
@@ -42,6 +44,12 @@
 #define CTX \
 	dmcu_dce->base.ctx
 
+/* PSR related commands */
+#define PSR_ENABLE 0x20
+#define PSR_EXIT 0x21
+#define PSR_SET 0x23
+#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK   0x00000001L
+
 bool dce_dmcu_load_iram(struct dmcu *dmcu,
 		unsigned int start_offset,
 		const char *src,
@@ -76,8 +84,208 @@ bool dce_dmcu_load_iram(struct dmcu *dmcu,
 	return true;
 }
 
+static void dce_get_dmcu_psr_state(struct dmcu *dmcu, uint32_t *psr_state)
+{
+	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
+
+	uint32_t count = 0;
+	uint32_t psrStateOffset = 0xf0;
+	uint32_t value = -1;
+
+	/* Enable write access to IRAM */
+	REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1);
+
+	while (REG(DCI_MEM_PWR_STATUS) && value != 0 && count++ < 10) {
+		dm_delay_in_microseconds(dmcu->ctx, 2);
+		REG_GET(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, &value);
+	}
+	while (REG(DMU_MEM_PWR_CNTL) && value != 0 && count++ < 10) {
+		dm_delay_in_microseconds(dmcu->ctx, 2);
+		REG_GET(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, &value);
+	}
+
+	/* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */
+	REG_WRITE(DMCU_IRAM_RD_CTRL, psrStateOffset);
+
+	/* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/
+	*psr_state = REG_READ(DMCU_IRAM_RD_DATA);
+
+	/* Disable write access to IRAM after finished using IRAM
+	 * in order to allow dynamic sleep state
+	 */
+	REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0);
+}
+
+static void dce_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable)
+{
+	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
+	unsigned int dmcu_max_retry_on_wait_reg_ready = 801;
+	unsigned int dmcu_wait_reg_ready_interval = 100;
+
+	unsigned int regValue;
+
+	unsigned int retryCount;
+	uint32_t psr_state = 0;
+
+	/* waitDMCUReadyForCmd */
+	do {
+		dm_delay_in_microseconds(dmcu->ctx,
+				dmcu_wait_reg_ready_interval);
+		regValue = REG_READ(MASTER_COMM_CNTL_REG);
+		dmcu_max_retry_on_wait_reg_ready--;
+	} while
+	/* expected value is 0, loop while not 0*/
+	((MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK & regValue) &&
+		dmcu_max_retry_on_wait_reg_ready > 0);
+
+	/* setDMCUParam_Cmd */
+	if (enable)
+		REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
+				PSR_ENABLE);
+	else
+		REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
+				PSR_EXIT);
+
+	/* notifyDMCUMsg */
+	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
+
+	for (retryCount = 0; retryCount <= 100; retryCount++) {
+		dce_get_dmcu_psr_state(dmcu, &psr_state);
+		if (enable) {
+			if (psr_state != 0)
+				break;
+		} else {
+			if (psr_state == 0)
+				break;
+		}
+		dm_delay_in_microseconds(dmcu->ctx, 10);
+	}
+}
+
+static void dce_dmcu_setup_psr(struct dmcu *dmcu,
+		struct core_link *link,
+		struct psr_context *psr_context)
+{
+	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
+
+	unsigned int dmcu_max_retry_on_wait_reg_ready = 801;
+	unsigned int dmcu_wait_reg_ready_interval = 100;
+	unsigned int regValue;
+
+	union dce_dmcu_psr_config_data_reg1 masterCmdData1;
+	union dce_dmcu_psr_config_data_reg2 masterCmdData2;
+	union dce_dmcu_psr_config_data_reg3 masterCmdData3;
+
+	link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc,
+			psr_context->psrExitLinkTrainingRequired);
+
+	/* Enable static screen interrupts for PSR supported display */
+	/* Disable the interrupt coming from other displays. */
+	REG_UPDATE_4(DMCU_INTERRUPT_TO_UC_EN_MASK,
+			STATIC_SCREEN1_INT_TO_UC_EN, 0,
+			STATIC_SCREEN2_INT_TO_UC_EN, 0,
+			STATIC_SCREEN3_INT_TO_UC_EN, 0,
+			STATIC_SCREEN4_INT_TO_UC_EN, 0);
+
+	switch (psr_context->controllerId) {
+	/* Driver uses case 1 for unconfigured */
+	case 1:
+		REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
+				STATIC_SCREEN1_INT_TO_UC_EN, 1);
+		break;
+	case 2:
+		REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
+				STATIC_SCREEN2_INT_TO_UC_EN, 1);
+		break;
+	case 3:
+		REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
+				STATIC_SCREEN3_INT_TO_UC_EN, 1);
+		break;
+	case 4:
+		REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
+				STATIC_SCREEN4_INT_TO_UC_EN, 1);
+		break;
+	case 5:
+		/* CZ/NL only has 4 CRTC!!
+		 * really valid.
+		 * There is no interrupt enable mask for these instances.
+		 */
+		break;
+	case 6:
+		/* CZ/NL only has 4 CRTC!!
+		 * These are here because they are defined in HW regspec,
+		 * but not really valid. There is no interrupt enable mask
+		 * for these instances.
+		 */
+		break;
+	default:
+		REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
+				STATIC_SCREEN1_INT_TO_UC_EN, 1);
+		break;
+	}
+
+	link->link_enc->funcs->psr_program_secondary_packet(link->link_enc,
+			psr_context->sdpTransmitLineNumDeadline);
+
+	if (psr_context->psr_level.bits.SKIP_SMU_NOTIFICATION)
+		REG_UPDATE(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, 1);
+
+	/* waitDMCUReadyForCmd */
+	do {
+		dm_delay_in_microseconds(dmcu->ctx,
+				dmcu_wait_reg_ready_interval);
+		regValue = REG_READ(MASTER_COMM_CNTL_REG);
+		dmcu_max_retry_on_wait_reg_ready--;
+	} while
+	/* expected value is 0, loop while not 0*/
+	((MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK & regValue) &&
+		dmcu_max_retry_on_wait_reg_ready > 0);
+
+	/* setDMCUParam_PSRHostConfigData */
+	masterCmdData1.u32All = 0;
+	masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames;
+	masterCmdData1.bits.hyst_lines = psr_context->hyst_lines;
+	masterCmdData1.bits.rfb_update_auto_en =
+			psr_context->rfb_update_auto_en;
+	masterCmdData1.bits.dp_port_num = psr_context->transmitterId;
+	masterCmdData1.bits.dcp_sel = psr_context->controllerId;
+	masterCmdData1.bits.phy_type  = psr_context->phyType;
+	masterCmdData1.bits.frame_cap_ind =
+			psr_context->psrFrameCaptureIndicationReq;
+	masterCmdData1.bits.aux_chan = psr_context->channel;
+	masterCmdData1.bits.aux_repeat = psr_context->aux_repeats;
+	dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1),
+					masterCmdData1.u32All);
+
+	masterCmdData2.u32All = 0;
+	masterCmdData2.bits.dig_fe = psr_context->engineId;
+	masterCmdData2.bits.dig_be = psr_context->transmitterId;
+	masterCmdData2.bits.skip_wait_for_pll_lock =
+			psr_context->skipPsrWaitForPllLock;
+	masterCmdData2.bits.frame_delay = psr_context->frame_delay;
+	masterCmdData2.bits.smu_phy_id = psr_context->smuPhyId;
+	masterCmdData2.bits.num_of_controllers =
+			psr_context->numberOfControllers;
+	dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2),
+			masterCmdData2.u32All);
+
+	masterCmdData3.u32All = 0;
+	masterCmdData3.bits.psr_level = psr_context->psr_level.u32all;
+	dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3),
+			masterCmdData3.u32All);
+
+	/* setDMCUParam_Cmd */
+	REG_UPDATE(MASTER_COMM_CMD_REG,
+			MASTER_COMM_CMD_REG_BYTE0, PSR_SET);
+
+	/* notifyDMCUMsg */
+	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
+}
+
 static const struct dmcu_funcs dce_funcs = {
 	.load_iram = dce_dmcu_load_iram,
+	.set_psr_enable = dce_dmcu_set_psr_enable,
+	.setup_psr = dce_dmcu_setup_psr,
 };
 
 static void dce_dmcu_construct(
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
index 33c1754f04f1..7dc25386c2bf 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
@@ -33,7 +33,16 @@
 	SR(DMCU_CTRL), \
 	SR(DMCU_RAM_ACCESS_CTRL), \
 	SR(DMCU_IRAM_WR_CTRL), \
-	SR(DMCU_IRAM_WR_DATA)
+	SR(DMCU_IRAM_WR_DATA), \
+	SR(MASTER_COMM_DATA_REG1), \
+	SR(MASTER_COMM_DATA_REG2), \
+	SR(MASTER_COMM_DATA_REG3), \
+	SR(MASTER_COMM_CMD_REG), \
+	SR(MASTER_COMM_CNTL_REG), \
+	SR(DMCU_IRAM_RD_CTRL), \
+	SR(DMCU_IRAM_RD_DATA), \
+	SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \
+	SR(SMU_INTERRUPT_CONTROL)
 
 #define DMCU_DCE110_COMMON_REG_LIST() \
 	DMCU_COMMON_REG_LIST_DCE_BASE(), \
@@ -48,18 +57,41 @@
 	DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
 			IRAM_HOST_ACCESS_EN, mask_sh), \
 	DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
-			IRAM_WR_ADDR_AUTO_INC, mask_sh)
+			IRAM_WR_ADDR_AUTO_INC, mask_sh), \
+	DMCU_SF(MASTER_COMM_CMD_REG, \
+			MASTER_COMM_CMD_REG_BYTE0, mask_sh), \
+	DMCU_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \
+	DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \
+			STATIC_SCREEN1_INT_TO_UC_EN, mask_sh), \
+	DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \
+			STATIC_SCREEN2_INT_TO_UC_EN, mask_sh), \
+	DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \
+			STATIC_SCREEN3_INT_TO_UC_EN, mask_sh), \
+	DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \
+			STATIC_SCREEN4_INT_TO_UC_EN, mask_sh), \
+	DMCU_SF(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, mask_sh)
 
 #define DMCU_MASK_SH_LIST_DCE110(mask_sh) \
 	DMCU_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
 	DMCU_SF(DCI_MEM_PWR_STATUS, \
-			DMCU_IRAM_MEM_PWR_STATE, mask_sh)
+		DMCU_IRAM_MEM_PWR_STATE, mask_sh)
 
 #define DMCU_REG_FIELD_LIST(type) \
 	type DMCU_IRAM_MEM_PWR_STATE; \
 	type IRAM_HOST_ACCESS_EN; \
 	type IRAM_WR_ADDR_AUTO_INC; \
-	type DMCU_ENABLE
+	type DMCU_ENABLE; \
+	type MASTER_COMM_CMD_REG_BYTE0; \
+	type MASTER_COMM_INTERRUPT; \
+	type DPHY_RX_FAST_TRAINING_CAPABLE; \
+	type DPHY_LOAD_BS_COUNT; \
+	type STATIC_SCREEN1_INT_TO_UC_EN; \
+	type STATIC_SCREEN2_INT_TO_UC_EN; \
+	type STATIC_SCREEN3_INT_TO_UC_EN; \
+	type STATIC_SCREEN4_INT_TO_UC_EN; \
+	type DP_SEC_GSP0_LINE_NUM; \
+	type DP_SEC_GSP0_PRIORITY; \
+	type DC_SMU_INT_ENABLE
 
 struct dce_dmcu_shift {
 	DMCU_REG_FIELD_LIST(uint8_t);
@@ -76,6 +108,16 @@ struct dce_dmcu_registers {
 	uint32_t DMU_MEM_PWR_CNTL;
 	uint32_t DMCU_IRAM_WR_CTRL;
 	uint32_t DMCU_IRAM_WR_DATA;
+
+	uint32_t MASTER_COMM_DATA_REG1;
+	uint32_t MASTER_COMM_DATA_REG2;
+	uint32_t MASTER_COMM_DATA_REG3;
+	uint32_t MASTER_COMM_CMD_REG;
+	uint32_t MASTER_COMM_CNTL_REG;
+	uint32_t DMCU_IRAM_RD_CTRL;
+	uint32_t DMCU_IRAM_RD_DATA;
+	uint32_t DMCU_INTERRUPT_TO_UC_EN_MASK;
+	uint32_t SMU_INTERRUPT_CONTROL;
 };
 
 struct dce_dmcu {
@@ -85,6 +127,63 @@ struct dce_dmcu {
 	const struct dce_dmcu_mask *dmcu_mask;
 };
 
+/*******************************************************************
+ *   MASTER_COMM_DATA_REG1   Bit position    Data
+ *                           7:0	            hyst_frames[7:0]
+ *                           14:8	        hyst_lines[6:0]
+ *                           15	            RFB_UPDATE_AUTO_EN
+ *                           18:16	        phy_num[2:0]
+ *                           21:19	        dcp_sel[2:0]
+ *                           22	            phy_type
+ *                           23	            frame_cap_ind
+ *                           26:24	        aux_chan[2:0]
+ *                           30:27	        aux_repeat[3:0]
+ *                           31:31	        reserved[31:31]
+ ******************************************************************/
+union dce_dmcu_psr_config_data_reg1 {
+	struct {
+		unsigned int timehyst_frames:8;    /*[7:0]*/
+		unsigned int hyst_lines:7;         /*[14:8]*/
+		unsigned int rfb_update_auto_en:1; /*[15:15]*/
+		unsigned int dp_port_num:3;        /*[18:16]*/
+		unsigned int dcp_sel:3;            /*[21:19]*/
+		unsigned int phy_type:1;           /*[22:22]*/
+		unsigned int frame_cap_ind:1;      /*[23:23]*/
+		unsigned int aux_chan:3;           /*[26:24]*/
+		unsigned int aux_repeat:4;         /*[30:27]*/
+		unsigned int reserved:1;           /*[31:31]*/
+	} bits;
+	unsigned int u32All;
+};
+
+/*******************************************************************
+ *   MASTER_COMM_DATA_REG2
+ *******************************************************************/
+union dce_dmcu_psr_config_data_reg2 {
+	struct {
+		unsigned int dig_fe:3;                  /*[2:0]*/
+		unsigned int dig_be:3;                  /*[5:3]*/
+		unsigned int skip_wait_for_pll_lock:1;  /*[6:6]*/
+		unsigned int reserved:9;                /*[15:7]*/
+		unsigned int frame_delay:8;             /*[23:16]*/
+		unsigned int smu_phy_id:4;              /*[27:24]*/
+		unsigned int num_of_controllers:4;      /*[31:28]*/
+	} bits;
+	unsigned int u32All;
+};
+
+/*******************************************************************
+ *   MASTER_COMM_DATA_REG3
+ *******************************************************************/
+union dce_dmcu_psr_config_data_reg3 {
+	struct {
+		unsigned int psr_level:16;      /*[15:0]*/
+		unsigned int link_rate:4;       /*[19:16]*/
+		unsigned int reserved:12;       /*[31:20]*/
+	} bits;
+	unsigned int u32All;
+};
+
 struct dmcu *dce_dmcu_create(
 	struct dc_context *ctx,
 	const struct dce_dmcu_registers *regs,
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
index 305a9d86a5d2..a1d35ad85605 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
@@ -95,14 +95,6 @@
 /* For current ASICs pixel clock - 600MHz */
 #define MAX_ENCODER_CLOCK 600000
 
-/* PSR related commands */
-#define PSR_ENABLE 0x20
-#define PSR_EXIT 0x21
-#define PSR_SET 0x23
-
-/*TODO: Used for psr wakeup for set backlight level*/
-static unsigned int psr_crtc_offset;
-
 enum {
 	DP_MST_UPDATE_MAX_RETRY = 50
 };
@@ -126,8 +118,9 @@ static const struct link_encoder_funcs dce110_lnk_enc_funcs = {
 	.dp_set_phy_pattern = dce110_link_encoder_dp_set_phy_pattern,
 	.update_mst_stream_allocation_table =
 		dce110_link_encoder_update_mst_stream_allocation_table,
-	.set_dmcu_psr_enable = dce110_link_encoder_set_dmcu_psr_enable,
-	.setup_dmcu_psr = dce110_link_encoder_setup_dmcu_psr,
+	.psr_program_dp_dphy_fast_training =
+			dce110_psr_program_dp_dphy_fast_training,
+	.psr_program_secondary_packet = dce110_psr_program_secondary_packet,
 	.backlight_control = dce110_link_encoder_edp_backlight_control,
 	.power_control = dce110_link_encoder_edp_power_control,
 	.connect_dig_be_to_fe = dce110_link_encoder_connect_dig_be_to_fe,
@@ -136,7 +129,6 @@ static const struct link_encoder_funcs dce110_lnk_enc_funcs = {
 	.destroy = dce110_link_encoder_destroy
 };
 
-
 static enum bp_result link_transmitter_control(
 	struct dce110_link_encoder *enc110,
 	struct bp_transmitter_control *cntl)
@@ -721,6 +713,40 @@ static bool is_panel_backlight_on(struct dce110_link_encoder *enc110)
 	return value;
 }
 
+void dce110_psr_program_dp_dphy_fast_training(struct link_encoder *enc,
+			bool exit_link_training_required)
+{
+	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
+
+	if (exit_link_training_required)
+		REG_UPDATE(DP_DPHY_FAST_TRAINING,
+				DPHY_RX_FAST_TRAINING_CAPABLE, 1);
+	else {
+		REG_UPDATE(DP_DPHY_FAST_TRAINING,
+				DPHY_RX_FAST_TRAINING_CAPABLE, 0);
+		/*In DCE 11, we are able to pre-program a Force SR register
+		 * to be able to trigger SR symbol after 5 idle patterns
+		 * transmitted. Upon PSR Exit, DMCU can trigger
+		 * DPHY_LOAD_BS_COUNT_START = 1. Upon writing 1 to
+		 * DPHY_LOAD_BS_COUNT_START and the internal counter
+		 * reaches DPHY_LOAD_BS_COUNT, the next BS symbol will be
+		 * replaced by SR symbol once.
+		 */
+
+		REG_UPDATE(DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, 0x5);
+	}
+}
+
+void dce110_psr_program_secondary_packet(struct link_encoder *enc,
+			unsigned int sdp_transmit_line_num_deadline)
+{
+	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
+
+	REG_UPDATE_2(DP_SEC_CNTL1,
+		DP_SEC_GSP0_LINE_NUM, sdp_transmit_line_num_deadline,
+		DP_SEC_GSP0_PRIORITY, 1);
+}
+
 /*todo: cloned in stream enc, fix*/
 /*
  * @brief
@@ -1560,238 +1586,6 @@ void dce110_link_encoder_update_mst_stream_allocation_table(
 	} while (retries < DP_MST_UPDATE_MAX_RETRY);
 }
 
-static void get_dmcu_psr_state(struct link_encoder *enc, uint32_t *psr_state)
-{
-	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
-	struct dc_context *ctx = enc110->base.ctx;
-
-	uint32_t count = 0;
-	uint32_t psrStateOffset = 0xf0;
-	uint32_t value = -1;
-
-	/* Enable write access to IRAM */
-	REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1);
-
-	while (REG(DCI_MEM_PWR_STATUS) && value != 0 && count++ < 10) {
-		dm_delay_in_microseconds(ctx, 2);
-		REG_GET(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, &value);
-	}
-	while (REG(DMU_MEM_PWR_CNTL) && value != 0 && count++ < 10) {
-		dm_delay_in_microseconds(ctx, 2);
-		REG_GET(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, &value);
-	}
-
-	/* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */
-	REG_WRITE(DMCU_IRAM_RD_CTRL, psrStateOffset);
-
-	/* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/
-	*psr_state = REG_READ(DMCU_IRAM_RD_DATA);
-
-	/* Disable write access to IRAM after finished using IRAM
-	 * in order to allow dynamic sleep state
-	 */
-	REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0);
-}
-
-void dce110_link_encoder_set_dmcu_psr_enable(struct link_encoder *enc,
-								bool enable)
-{
-	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
-	struct dc_context *ctx = enc110->base.ctx;
-
-	unsigned int dmcu_max_retry_on_wait_reg_ready = 801;
-	unsigned int dmcu_wait_reg_ready_interval = 100;
-
-	unsigned int regValue;
-
-	unsigned int retryCount;
-	uint32_t psr_state = 0;
-
-	/* waitDMCUReadyForCmd */
-	do {
-		dm_delay_in_microseconds(ctx, dmcu_wait_reg_ready_interval);
-		regValue = REG_READ(MASTER_COMM_CNTL_REG);
-		dmcu_max_retry_on_wait_reg_ready--;
-	} while
-	/* expected value is 0, loop while not 0*/
-	((MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK & regValue) &&
-		dmcu_max_retry_on_wait_reg_ready > 0);
-
-	/* setDMCUParam_Cmd */
-	if (enable)
-		REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_ENABLE);
-	else
-		REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_EXIT);
-
-	/* notifyDMCUMsg */
-	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
-
-	for (retryCount = 0; retryCount <= 100; retryCount++) {
-		get_dmcu_psr_state(enc, &psr_state);
-		if (enable) {
-			if (psr_state != 0)
-				break;
-		} else {
-			if (psr_state == 0)
-				break;
-		}
-		dm_delay_in_microseconds(ctx, 10);
-	}
-}
-
-void dce110_link_encoder_setup_dmcu_psr(struct link_encoder *enc,
-			struct psr_dmcu_context *psr_context)
-{
-	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
-	struct dc_context *ctx = enc110->base.ctx;
-
-	unsigned int dmcu_max_retry_on_wait_reg_ready = 801;
-	unsigned int dmcu_wait_reg_ready_interval = 100;
-	unsigned int regValue;
-
-	union dce110_dmcu_psr_config_data_reg1 masterCmdData1;
-	union dce110_dmcu_psr_config_data_reg2 masterCmdData2;
-	union dce110_dmcu_psr_config_data_reg3 masterCmdData3;
-
-	if (psr_context->psrExitLinkTrainingRequired)
-		REG_UPDATE(DP_DPHY_FAST_TRAINING, DPHY_RX_FAST_TRAINING_CAPABLE, 1);
-	else {
-		REG_UPDATE(DP_DPHY_FAST_TRAINING, DPHY_RX_FAST_TRAINING_CAPABLE, 0);
-		/*In DCE 11, we are able to pre-program a Force SR register
-		 * to be able to trigger SR symbol after 5 idle patterns
-		 * transmitted. Upon PSR Exit, DMCU can trigger
-		 * DPHY_LOAD_BS_COUNT_START = 1. Upon writing 1 to
-		 * DPHY_LOAD_BS_COUNT_START and the internal counter
-		 * reaches DPHY_LOAD_BS_COUNT, the next BS symbol will be
-		 * replaced by SR symbol once.
-		 */
-
-		REG_UPDATE(DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, 0x5);
-	}
-
-	/* Enable static screen interrupts for PSR supported display */
-	/* Disable the interrupt coming from other displays. */
-	REG_UPDATE_4(DMCU_INTERRUPT_TO_UC_EN_MASK,
-			STATIC_SCREEN1_INT_TO_UC_EN, 0,
-			STATIC_SCREEN2_INT_TO_UC_EN, 0,
-			STATIC_SCREEN3_INT_TO_UC_EN, 0,
-			STATIC_SCREEN4_INT_TO_UC_EN, 0);
-
-	switch (psr_context->controllerId) {
-	/* Driver uses case 1 for unconfigured */
-	case 1:
-		psr_crtc_offset = mmCRTC0_CRTC_STATIC_SCREEN_CONTROL -
-				mmCRTC0_CRTC_STATIC_SCREEN_CONTROL;
-
-		REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
-				STATIC_SCREEN1_INT_TO_UC_EN, 1);
-		break;
-	case 2:
-		psr_crtc_offset = mmCRTC1_CRTC_STATIC_SCREEN_CONTROL -
-				mmCRTC0_CRTC_STATIC_SCREEN_CONTROL;
-
-		REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
-				STATIC_SCREEN2_INT_TO_UC_EN, 1);
-		break;
-	case 3:
-		psr_crtc_offset = mmCRTC2_CRTC_STATIC_SCREEN_CONTROL -
-				mmCRTC0_CRTC_STATIC_SCREEN_CONTROL;
-
-		REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
-				STATIC_SCREEN3_INT_TO_UC_EN, 1);
-		break;
-	case 4:
-		psr_crtc_offset = mmCRTC3_CRTC_STATIC_SCREEN_CONTROL -
-				mmCRTC0_CRTC_STATIC_SCREEN_CONTROL;
-
-		REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
-				STATIC_SCREEN4_INT_TO_UC_EN, 1);
-		break;
-	case 5:
-		psr_crtc_offset = mmCRTC4_CRTC_STATIC_SCREEN_CONTROL -
-				mmCRTC0_CRTC_STATIC_SCREEN_CONTROL;
-		/* CZ/NL only has 4 CRTC!!
-		 * really valid.
-		 * There is no interrupt enable mask for these instances.
-		 */
-		break;
-	case 6:
-		psr_crtc_offset = mmCRTC5_CRTC_STATIC_SCREEN_CONTROL -
-				mmCRTC0_CRTC_STATIC_SCREEN_CONTROL;
-		/* CZ/NL only has 4 CRTC!!
-		 * These are here because they are defined in HW regspec,
-		 * but not really valid. There is no interrupt enable mask
-		 * for these instances.
-		 */
-		break;
-	default:
-		psr_crtc_offset = mmCRTC0_CRTC_STATIC_SCREEN_CONTROL -
-				mmCRTC0_CRTC_STATIC_SCREEN_CONTROL;
-
-		REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
-				STATIC_SCREEN1_INT_TO_UC_EN, 1);
-		break;
-	}
-
-	REG_UPDATE_2(DP_SEC_CNTL1,
-		DP_SEC_GSP0_LINE_NUM, psr_context->sdpTransmitLineNumDeadline,
-		DP_SEC_GSP0_PRIORITY, 1);
-
-	if (psr_context->psr_level.bits.SKIP_SMU_NOTIFICATION) {
-		REG_UPDATE(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, 1);
-	}
-
-	/* waitDMCUReadyForCmd */
-	do {
-		dm_delay_in_microseconds(ctx, dmcu_wait_reg_ready_interval);
-		regValue = REG_READ(MASTER_COMM_CNTL_REG);
-		dmcu_max_retry_on_wait_reg_ready--;
-	} while
-	/* expected value is 0, loop while not 0*/
-	((MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK & regValue) &&
-		dmcu_max_retry_on_wait_reg_ready > 0);
-
-	/* setDMCUParam_PSRHostConfigData */
-	masterCmdData1.u32All = 0;
-	masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames;
-	masterCmdData1.bits.hyst_lines = psr_context->hyst_lines;
-	masterCmdData1.bits.rfb_update_auto_en =
-			psr_context->rfb_update_auto_en;
-	masterCmdData1.bits.dp_port_num = psr_context->transmitterId;
-	masterCmdData1.bits.dcp_sel = psr_context->controllerId;
-	masterCmdData1.bits.phy_type  = psr_context->phyType;
-	masterCmdData1.bits.frame_cap_ind =
-			psr_context->psrFrameCaptureIndicationReq;
-	masterCmdData1.bits.aux_chan = psr_context->channel;
-	masterCmdData1.bits.aux_repeat = psr_context->aux_repeats;
-	dm_write_reg(ctx, REG(MASTER_COMM_DATA_REG1),
-					masterCmdData1.u32All);
-
-	masterCmdData2.u32All = 0;
-	masterCmdData2.bits.dig_fe = psr_context->engineId;
-	masterCmdData2.bits.dig_be = psr_context->transmitterId;
-	masterCmdData2.bits.skip_wait_for_pll_lock =
-			psr_context->skipPsrWaitForPllLock;
-	masterCmdData2.bits.frame_delay = psr_context->frame_delay;
-	masterCmdData2.bits.smu_phy_id = psr_context->smuPhyId;
-	masterCmdData2.bits.num_of_controllers =
-			psr_context->numberOfControllers;
-	dm_write_reg(ctx, REG(MASTER_COMM_DATA_REG2),
-			masterCmdData2.u32All);
-
-	masterCmdData3.u32All = 0;
-	masterCmdData3.bits.psr_level = psr_context->psr_level.u32all;
-	dm_write_reg(ctx, REG(MASTER_COMM_DATA_REG3),
-			masterCmdData3.u32All);
-
-	/* setDMCUParam_Cmd */
-	REG_UPDATE(MASTER_COMM_CMD_REG,
-			MASTER_COMM_CMD_REG_BYTE0, PSR_SET);
-
-	/* notifyDMCUMsg */
-	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
-}
-
 void dce110_link_encoder_connect_dig_be_to_fe(
 	struct link_encoder *enc,
 	enum engine_id engine,
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
index d382a6882d95..f337d607e36c 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
@@ -39,11 +39,6 @@
 	SRI(DC_HPD_CONTROL, HPD, id)
 
 #define LE_COMMON_REG_LIST_BASE(id) \
-	SR(MASTER_COMM_DATA_REG1), \
-	SR(MASTER_COMM_DATA_REG2), \
-	SR(MASTER_COMM_DATA_REG3), \
-	SR(MASTER_COMM_CMD_REG), \
-	SR(MASTER_COMM_CNTL_REG), \
 	SR(LVTMA_PWRSEQ_CNTL), \
 	SR(LVTMA_PWRSEQ_STATE), \
 	SR(DMCU_RAM_ACCESS_CTRL), \
@@ -149,62 +144,6 @@ struct dce110_link_encoder {
 	const struct dce110_link_enc_hpd_registers *hpd_regs;
 };
 
-/*******************************************************************
-*   MASTER_COMM_DATA_REG1   Bit position    Data
-*                           7:0	            hyst_frames[7:0]
-*                           14:8	        hyst_lines[6:0]
-*                           15	            RFB_UPDATE_AUTO_EN
-*                           18:16	        phy_num[2:0]
-*                           21:19	        dcp_sel[2:0]
-*                           22	            phy_type
-*                           23	            frame_cap_ind
-*                           26:24	        aux_chan[2:0]
-*                           30:27	        aux_repeat[3:0]
-*                           31:31	        reserved[31:31]
-*******************************************************************/
-union dce110_dmcu_psr_config_data_reg1 {
-	struct {
-		unsigned int timehyst_frames:8;    /*[7:0]*/
-		unsigned int hyst_lines:7;         /*[14:8]*/
-		unsigned int rfb_update_auto_en:1; /*[15:15]*/
-		unsigned int dp_port_num:3;        /*[18:16]*/
-		unsigned int dcp_sel:3;            /*[21:19]*/
-		unsigned int phy_type:1;           /*[22:22]*/
-		unsigned int frame_cap_ind:1;      /*[23:23]*/
-		unsigned int aux_chan:3;           /*[26:24]*/
-		unsigned int aux_repeat:4;         /*[30:27]*/
-		unsigned int reserved:1;           /*[31:31]*/
-	} bits;
-	unsigned int u32All;
-};
-
-/*******************************************************************
-*   MASTER_COMM_DATA_REG2
-*******************************************************************/
-union dce110_dmcu_psr_config_data_reg2 {
-	struct {
-		unsigned int dig_fe:3;                  /*[2:0]*/
-		unsigned int dig_be:3;                  /*[5:3]*/
-		unsigned int skip_wait_for_pll_lock:1;  /*[6:6]*/
-		unsigned int reserved:9;                /*[15:7]*/
-		unsigned int frame_delay:8;             /*[23:16]*/
-		unsigned int smu_phy_id:4;              /*[27:24]*/
-		unsigned int num_of_controllers:4;      /*[31:28]*/
-	} bits;
-	unsigned int u32All;
-};
-
-/*******************************************************************
-*   MASTER_COMM_DATA_REG3
-*******************************************************************/
-union dce110_dmcu_psr_config_data_reg3 {
-	struct {
-		unsigned int psr_level:16;      /*[15:0]*/
-		unsigned int link_rate:4;       /*[19:16]*/
-		unsigned int reserved:12;       /*[31:20]*/
-	} bits;
-	unsigned int u32All;
-};
 
 bool dce110_link_encoder_construct(
 	struct dce110_link_encoder *enc110,
@@ -290,12 +229,6 @@ void dce110_link_encoder_update_mst_stream_allocation_table(
 	struct link_encoder *enc,
 	const struct link_mst_stream_allocation_table *table);
 
-void dce110_link_encoder_set_dmcu_psr_enable(
-		struct link_encoder *enc, bool enable);
-
-void dce110_link_encoder_setup_dmcu_psr(struct link_encoder *enc,
-			struct psr_dmcu_context *psr_context);
-
 void dce110_link_encoder_edp_backlight_control(
 	struct link_encoder *enc,
 	bool enable);
@@ -317,4 +250,10 @@ void dce110_link_encoder_enable_hpd(struct link_encoder *enc);
 
 void dce110_link_encoder_disable_hpd(struct link_encoder *enc);
 
+void dce110_psr_program_dp_dphy_fast_training(struct link_encoder *enc,
+			bool exit_link_training_required);
+
+void dce110_psr_program_secondary_packet(struct link_encoder *enc,
+			unsigned int sdp_transmit_line_num_deadline);
+
 #endif /* __DC_LINK_ENCODER__DCE110_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h
index 62012f091836..656cfdc79891 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h
@@ -37,6 +37,10 @@ struct dmcu_funcs {
 			unsigned int start_offset,
 			const char *src,
 			unsigned int bytes);
+	void (*set_psr_enable)(struct dmcu *dmcu, bool enable);
+	void (*setup_psr)(struct dmcu *dmcu,
+			struct core_link *link,
+			struct psr_context *psr_context);
 };
 
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
index 7b37b963666e..7307f96c7679 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
@@ -116,7 +116,7 @@ union psr_sink_psr_status {
 	unsigned char raw;
 };
 
-struct psr_dmcu_context {
+struct psr_context {
 	/* ddc line */
 	enum channel_id channel;
 	/* Transmitter id */
@@ -220,9 +220,10 @@ struct link_encoder_funcs {
 	void (*update_mst_stream_allocation_table)(
 		struct link_encoder *enc,
 		const struct link_mst_stream_allocation_table *table);
-	void (*set_dmcu_psr_enable)(struct link_encoder *enc, bool enable);
-	void (*setup_dmcu_psr)(struct link_encoder *enc,
-			struct psr_dmcu_context *psr_context);
+	void (*psr_program_dp_dphy_fast_training)(struct link_encoder *enc,
+			bool exit_link_training_required);
+	void (*psr_program_secondary_packet)(struct link_encoder *enc,
+				unsigned int sdp_transmit_line_num_deadline);
 	void (*backlight_control) (struct link_encoder *enc,
 		bool enable);
 	void (*power_control) (struct link_encoder *enc,
-- 
2.9.3

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[PATCH 05/15] drm/amd/display: Fix gamma colour corruption for 10 bit surfaces

[Harry Wentland]

From: Jordan Lazare <Jordan.Lazare@amd.com>

Gamma LUT shouldn't be used for 10-bit and above. Should instead be
using prescale and bypassing input gamma.

Change-Id: I55c08c746bb1e1ab1739e47162ddf06db12fe873
Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
 .../amd/display/dc/dce110/dce110_hw_sequencer.c    | 15 ++++-
 drivers/gpu/drm/amd/display/dc/dce80/Makefile      |  3 +-
 .../gpu/drm/amd/display/dc/dce80/dce80_ipp_gamma.c | 71 ----------------------
 3 files changed, 15 insertions(+), 74 deletions(-)
 delete mode 100644 drivers/gpu/drm/amd/display/dc/dce80/dce80_ipp_gamma.c

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 2f68bf20dfe2..2d2daa694a30 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -233,6 +233,19 @@ static void build_prescale_params(struct ipp_prescale_params *prescale_params,
 	}
 }
 
+
+/* Only use LUT for 8 bit formats */
+static bool use_lut(const struct core_surface *surface)
+{
+	switch (surface->public.format) {
+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
+		return true;
+	default:
+		return false;
+	}
+}
+
 static bool dce110_set_input_transfer_func(
 	struct pipe_ctx *pipe_ctx,
 	const struct core_surface *surface)
@@ -251,7 +264,7 @@ static bool dce110_set_input_transfer_func(
 	build_prescale_params(&prescale_params, surface);
 	ipp->funcs->ipp_program_prescale(ipp, &prescale_params);
 
-	if (surface->public.gamma_correction)
+	if (surface->public.gamma_correction && use_lut(surface))
 	    ipp->funcs->ipp_program_input_lut(ipp, surface->public.gamma_correction);
 
 	if (tf == NULL) {
diff --git a/drivers/gpu/drm/amd/display/dc/dce80/Makefile b/drivers/gpu/drm/amd/display/dc/dce80/Makefile
index 0261d1bfccb5..8d2c3dbfced1 100644
--- a/drivers/gpu/drm/amd/display/dc/dce80/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dce80/Makefile
@@ -2,8 +2,7 @@
 # Makefile for the 'controller' sub-component of DAL.
 # It provides the control and status of HW CRTC block.
 
-DCE80 = dce80_ipp.o dce80_ipp_gamma.o \
-	dce80_timing_generator.o \
+DCE80 = dce80_ipp.o dce80_timing_generator.o \
 	dce80_compressor.o dce80_mem_input.o dce80_hw_sequencer.o \
 	dce80_resource.o
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_ipp_gamma.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_ipp_gamma.c
deleted file mode 100644
index 760168df5290..000000000000
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_ipp_gamma.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-
-#include "include/logger_interface.h"
-#include "include/fixed31_32.h"
-#include "basics/conversion.h"
-
-#include "dce/dce_8_0_d.h"
-#include "dce/dce_8_0_sh_mask.h"
-
-#include "dce80_ipp.h"
-#include "dce110/dce110_ipp.h"
-
-#define DCP_REG(reg)\
-	(reg + ipp80->offsets.dcp_offset)
-
-/*PROTOTYPE DECLARATIONS*/
-
-static void set_legacy_input_gamma_mode(
-	struct dce110_ipp *ipp80,
-	bool is_legacy);
-
-void dce80_ipp_set_legacy_input_gamma_mode(
-		struct input_pixel_processor *ipp,
-		bool is_legacy)
-{
-	struct dce110_ipp *ipp80 = TO_DCE80_IPP(ipp);
-
-	set_legacy_input_gamma_mode(ipp80, is_legacy);
-}
-
-static void set_legacy_input_gamma_mode(
-	struct dce110_ipp *ipp80,
-	bool is_legacy)
-{
-	const uint32_t addr = DCP_REG(mmINPUT_GAMMA_CONTROL);
-	uint32_t value = dm_read_reg(ipp80->base.ctx, addr);
-
-	set_reg_field_value(
-		value,
-		!is_legacy,
-		INPUT_GAMMA_CONTROL,
-		GRPH_INPUT_GAMMA_MODE);
-
-	dm_write_reg(ipp80->base.ctx, addr, value);
-}
-
-- 
2.9.3

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Re: [PATCH 05/15] drm/amd/display: Fix gamma colour corruption for 10 bit surfaces

[Michel Dänzer]

On 01/03/17 09:26 AM, Harry Wentland wrote:
> From: Jordan Lazare <Jordan.Lazare@amd.com>
> 
> Gamma LUT shouldn't be used for 10-bit and above. Should instead be
> using prescale and bypassing input gamma.
> 
> Change-Id: I55c08c746bb1e1ab1739e47162ddf06db12fe873
> Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
> Acked-by: Harry Wentland <Harry.Wentland@amd.com>
> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
> ---
>  .../amd/display/dc/dce110/dce110_hw_sequencer.c    | 15 ++++-
>  drivers/gpu/drm/amd/display/dc/dce80/Makefile      |  3 +-
>  .../gpu/drm/amd/display/dc/dce80/dce80_ipp_gamma.c | 71 ----------------------

The removal of dce80_ipp_gamma.c and corresponding Makefile change looks
unrelated and should be a separate change.


-- 
Earthling Michel Dänzer               |               http://www.amd.com
Libre software enthusiast             |             Mesa and X developer
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Re: [PATCH 05/15] drm/amd/display: Fix gamma colour corruption for 10 bit surfaces

[Harry Wentland]

On 2017-02-28 08:17 PM, Michel Dänzer wrote:
> On 01/03/17 09:26 AM, Harry Wentland wrote:
>> From: Jordan Lazare <Jordan.Lazare@amd.com>
>>
>> Gamma LUT shouldn't be used for 10-bit and above. Should instead be
>> using prescale and bypassing input gamma.
>>
>> Change-Id: I55c08c746bb1e1ab1739e47162ddf06db12fe873
>> Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
>> Acked-by: Harry Wentland <Harry.Wentland@amd.com>
>> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
>> ---
>>  .../amd/display/dc/dce110/dce110_hw_sequencer.c    | 15 ++++-
>>  drivers/gpu/drm/amd/display/dc/dce80/Makefile      |  3 +-
>>  .../gpu/drm/amd/display/dc/dce80/dce80_ipp_gamma.c | 71 ----------------------
>
> The removal of dce80_ipp_gamma.c and corresponding Makefile change looks
> unrelated and should be a separate change.
>
>

The change is removing dce80_ipp_gamma.c and has to remove it from 
Makefile as well, unless there's something I'm not seeing.

Harry
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Re: [PATCH 05/15] drm/amd/display: Fix gamma colour corruption for 10 bit surfaces

[Harry Wentland]

On 2017-03-01 10:01 AM, Harry Wentland wrote:
> On 2017-02-28 08:17 PM, Michel Dänzer wrote:
>> On 01/03/17 09:26 AM, Harry Wentland wrote:
>>> From: Jordan Lazare <Jordan.Lazare@amd.com>
>>>
>>> Gamma LUT shouldn't be used for 10-bit and above. Should instead be
>>> using prescale and bypassing input gamma.
>>>
>>> Change-Id: I55c08c746bb1e1ab1739e47162ddf06db12fe873
>>> Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
>>> Acked-by: Harry Wentland <Harry.Wentland@amd.com>
>>> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
>>> ---
>>>  .../amd/display/dc/dce110/dce110_hw_sequencer.c    | 15 ++++-
>>>  drivers/gpu/drm/amd/display/dc/dce80/Makefile      |  3 +-
>>>  .../gpu/drm/amd/display/dc/dce80/dce80_ipp_gamma.c | 71
>>> ----------------------
>>
>> The removal of dce80_ipp_gamma.c and corresponding Makefile change looks
>> unrelated and should be a separate change.
>>
>>
>
> The change is removing dce80_ipp_gamma.c and has to remove it from
> Makefile as well, unless there's something I'm not seeing.
>

Misread your comment. Yeah, that should probably be in a separate change.

Harry

> Harry
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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[PATCH 06/15] drm/amd/display: add scaler coefficients for 64 phase 5-8 taps

[Harry Wentland]

From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>

Change-Id: I5ec48ee9c23a9c7678ae5a2deca33a210fac3ad9
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
 .../gpu/drm/amd/display/dc/dce/dce_scl_filters.c   | 608 +++++++++++++++++++++
 drivers/gpu/drm/amd/display/dc/inc/hw/transform.h  |   4 +
 2 files changed, 612 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_scl_filters.c b/drivers/gpu/drm/amd/display/dc/dce/dce_scl_filters.c
index 3aab86781be2..2cfdb835f1a8 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_scl_filters.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_scl_filters.c
@@ -452,6 +452,566 @@ const uint16_t filter_4tap_64p_183[132] = {
 	252, 1832, 1784, 220,
 	236, 1808, 1808, 236 };
 
+const uint16_t filter_5tap_64p_upscale[165] = {
+	15936, 2496, 2496, 15936, 0,
+	15948, 2404, 2580, 15924, 0,
+	15960, 2312, 2664, 15912, 4,
+	15976, 2220, 2748, 15904, 8,
+	15992, 2128, 2832, 15896, 12,
+	16004, 2036, 2912, 15888, 16,
+	16020, 1944, 2992, 15880, 20,
+	16036, 1852, 3068, 15876, 20,
+	16056, 1760, 3140, 15876, 24,
+	16072, 1668, 3216, 15872, 28,
+	16088, 1580, 3284, 15872, 32,
+	16104, 1492, 3352, 15876, 32,
+	16120, 1404, 3420, 15876, 36,
+	16140, 1316, 3480, 15884, 40,
+	16156, 1228, 3540, 15892, 40,
+	16172, 1144, 3600, 15900, 40,
+	16188, 1060, 3652, 15908, 44,
+	16204, 980, 3704, 15924, 44,
+	16220, 900, 3756, 15936, 44,
+	16236, 824, 3800, 15956, 44,
+	16248, 744, 3844, 15972, 44,
+	16264, 672, 3884, 15996, 44,
+	16276, 600, 3920, 16020, 44,
+	16292, 528, 3952, 16044, 40,
+	16304, 460, 3980, 16072, 40,
+	16316, 396, 4008, 16104, 36,
+	16328, 332, 4032, 16136, 32,
+	16336, 272, 4048, 16172, 28,
+	16348, 212, 4064, 16208, 24,
+	16356, 156, 4080, 16248, 16,
+	16368, 100, 4088, 16292, 12,
+	16376, 48, 4092, 16336, 4,
+	0, 0, 4096, 0, 0 };
+
+const uint16_t filter_5tap_64p_117[165] = {
+	16056, 2372, 2372, 16056, 0,
+	16052, 2312, 2432, 16060, 0,
+	16052, 2252, 2488, 16064, 0,
+	16052, 2188, 2548, 16072, 0,
+	16052, 2124, 2600, 16076, 0,
+	16052, 2064, 2656, 16088, 0,
+	16052, 2000, 2708, 16096, 0,
+	16056, 1932, 2760, 16108, 0,
+	16060, 1868, 2808, 16120, 0,
+	16064, 1804, 2856, 16132, 0,
+	16068, 1740, 2904, 16148, 16380,
+	16076, 1676, 2948, 16164, 16380,
+	16080, 1612, 2992, 16180, 16376,
+	16088, 1544, 3032, 16200, 16372,
+	16096, 1480, 3072, 16220, 16372,
+	16104, 1420, 3108, 16244, 16368,
+	16112, 1356, 3144, 16268, 16364,
+	16120, 1292, 3180, 16292, 16360,
+	16128, 1232, 3212, 16320, 16356,
+	16136, 1168, 3240, 16344, 16352,
+	16144, 1108, 3268, 16376, 16344,
+	16156, 1048, 3292, 20, 16340,
+	16164, 988, 3316, 52, 16332,
+	16172, 932, 3336, 88, 16328,
+	16184, 872, 3356, 124, 16320,
+	16192, 816, 3372, 160, 16316,
+	16204, 760, 3388, 196, 16308,
+	16212, 708, 3400, 236, 16300,
+	16220, 656, 3412, 276, 16292,
+	16232, 604, 3420, 320, 16284,
+	16240, 552, 3424, 364, 16276,
+	16248, 504, 3428, 408, 16268,
+	16256, 456, 3428, 456, 16256 };
+
+const uint16_t filter_5tap_64p_150[165] = {
+	16368, 2064, 2064, 16368, 0,
+	16352, 2028, 2100, 16380, 16380,
+	16340, 1996, 2132, 12, 16376,
+	16328, 1960, 2168, 24, 16376,
+	16316, 1924, 2204, 44, 16372,
+	16308, 1888, 2236, 60, 16368,
+	16296, 1848, 2268, 76, 16364,
+	16288, 1812, 2300, 96, 16360,
+	16280, 1772, 2328, 116, 16356,
+	16272, 1736, 2360, 136, 16352,
+	16268, 1696, 2388, 160, 16348,
+	16260, 1656, 2416, 180, 16344,
+	16256, 1616, 2440, 204, 16340,
+	16248, 1576, 2464, 228, 16336,
+	16244, 1536, 2492, 252, 16332,
+	16240, 1496, 2512, 276, 16324,
+	16240, 1456, 2536, 304, 16320,
+	16236, 1416, 2556, 332, 16316,
+	16232, 1376, 2576, 360, 16312,
+	16232, 1336, 2592, 388, 16308,
+	16232, 1296, 2612, 416, 16300,
+	16232, 1256, 2628, 448, 16296,
+	16232, 1216, 2640, 480, 16292,
+	16232, 1172, 2652, 512, 16288,
+	16232, 1132, 2664, 544, 16284,
+	16232, 1092, 2676, 576, 16280,
+	16236, 1056, 2684, 608, 16272,
+	16236, 1016, 2692, 644, 16268,
+	16240, 976, 2700, 680, 16264,
+	16240, 936, 2704, 712, 16260,
+	16244, 900, 2708, 748, 16256,
+	16248, 860, 2708, 788, 16252,
+	16248, 824, 2708, 824, 16248 };
+
+const uint16_t filter_5tap_64p_183[165] = {
+	228, 1816, 1816, 228, 0,
+	216, 1792, 1836, 248, 16380,
+	200, 1772, 1860, 264, 16376,
+	184, 1748, 1884, 280, 16376,
+	168, 1728, 1904, 300, 16372,
+	156, 1704, 1928, 316, 16368,
+	144, 1680, 1948, 336, 16364,
+	128, 1656, 1968, 356, 16364,
+	116, 1632, 1988, 376, 16360,
+	104, 1604, 2008, 396, 16356,
+	96, 1580, 2024, 416, 16356,
+	84, 1556, 2044, 440, 16352,
+	72, 1528, 2060, 460, 16348,
+	64, 1504, 2076, 484, 16348,
+	52, 1476, 2092, 504, 16344,
+	44, 1448, 2104, 528, 16344,
+	36, 1424, 2120, 552, 16340,
+	28, 1396, 2132, 576, 16340,
+	20, 1368, 2144, 600, 16340,
+	12, 1340, 2156, 624, 16336,
+	4, 1312, 2168, 652, 16336,
+	0, 1284, 2180, 676, 16336,
+	16376, 1256, 2188, 700, 16332,
+	16372, 1228, 2196, 728, 16332,
+	16368, 1200, 2204, 752, 16332,
+	16364, 1172, 2212, 780, 16332,
+	16356, 1144, 2216, 808, 16332,
+	16352, 1116, 2220, 836, 16332,
+	16352, 1084, 2224, 860, 16332,
+	16348, 1056, 2228, 888, 16336,
+	16344, 1028, 2232, 916, 16336,
+	16340, 1000, 2232, 944, 16336,
+	16340, 972, 2232, 972, 16340 };
+
+const uint16_t filter_6tap_64p_upscale[198] = {
+	0, 0, 4092, 0, 0, 0,
+	12, 16332, 4092, 52, 16368, 0,
+	24, 16280, 4088, 108, 16356, 0,
+	36, 16236, 4080, 168, 16340, 0,
+	44, 16188, 4064, 228, 16324, 0,
+	56, 16148, 4052, 292, 16308, 0,
+	64, 16108, 4032, 356, 16292, 4,
+	72, 16072, 4008, 424, 16276, 4,
+	80, 16036, 3980, 492, 16256, 4,
+	88, 16004, 3952, 564, 16240, 8,
+	96, 15972, 3920, 636, 16220, 8,
+	100, 15944, 3884, 712, 16204, 12,
+	108, 15916, 3844, 788, 16184, 16,
+	112, 15896, 3800, 864, 16164, 20,
+	116, 15872, 3756, 944, 16144, 20,
+	120, 15852, 3708, 1024, 16124, 24,
+	120, 15836, 3656, 1108, 16104, 28,
+	124, 15824, 3600, 1192, 16084, 32,
+	124, 15808, 3544, 1276, 16064, 36,
+	124, 15800, 3484, 1360, 16044, 40,
+	128, 15792, 3420, 1448, 16024, 44,
+	128, 15784, 3352, 1536, 16004, 48,
+	124, 15780, 3288, 1624, 15988, 52,
+	124, 15776, 3216, 1712, 15968, 56,
+	124, 15776, 3144, 1800, 15948, 64,
+	120, 15776, 3068, 1888, 15932, 68,
+	120, 15780, 2992, 1976, 15912, 72,
+	116, 15784, 2916, 2064, 15896, 76,
+	112, 15792, 2836, 2152, 15880, 80,
+	108, 15796, 2752, 2244, 15868, 84,
+	104, 15804, 2672, 2328, 15852, 88,
+	104, 15816, 2588, 2416, 15840, 92,
+	100, 15828, 2504, 2504, 15828, 100 };
+
+const uint16_t filter_6tap_64p_117[198] = {
+	16168, 476, 3568, 476, 16168, 0,
+	16180, 428, 3564, 528, 16156, 0,
+	16192, 376, 3556, 584, 16144, 4,
+	16204, 328, 3548, 636, 16128, 4,
+	16216, 280, 3540, 692, 16116, 8,
+	16228, 232, 3524, 748, 16104, 12,
+	16240, 188, 3512, 808, 16092, 12,
+	16252, 148, 3492, 864, 16080, 16,
+	16264, 104, 3472, 924, 16068, 16,
+	16276, 64, 3452, 984, 16056, 20,
+	16284, 28, 3428, 1044, 16048, 24,
+	16296, 16376, 3400, 1108, 16036, 24,
+	16304, 16340, 3372, 1168, 16024, 28,
+	16316, 16304, 3340, 1232, 16016, 32,
+	16324, 16272, 3308, 1296, 16004, 32,
+	16332, 16244, 3272, 1360, 15996, 36,
+	16344, 16212, 3236, 1424, 15988, 36,
+	16352, 16188, 3200, 1488, 15980, 40,
+	16360, 16160, 3160, 1552, 15972, 40,
+	16368, 16136, 3116, 1616, 15964, 40,
+	16372, 16112, 3072, 1680, 15956, 44,
+	16380, 16092, 3028, 1744, 15952, 44,
+	0, 16072, 2980, 1808, 15948, 44,
+	8, 16052, 2932, 1872, 15944, 48,
+	12, 16036, 2880, 1936, 15940, 48,
+	16, 16020, 2828, 2000, 15936, 48,
+	20, 16008, 2776, 2064, 15936, 48,
+	24, 15996, 2724, 2128, 15936, 48,
+	28, 15984, 2668, 2192, 15936, 48,
+	32, 15972, 2612, 2252, 15940, 44,
+	36, 15964, 2552, 2316, 15940, 44,
+	40, 15956, 2496, 2376, 15944, 44,
+	40, 15952, 2436, 2436, 15952, 40 };
+
+const uint16_t filter_6tap_64p_150[198] = {
+	16148, 920, 2724, 920, 16148, 0,
+	16152, 880, 2724, 956, 16148, 0,
+	16152, 844, 2720, 996, 16144, 0,
+	16156, 804, 2716, 1032, 16144, 0,
+	16156, 768, 2712, 1072, 16144, 0,
+	16160, 732, 2708, 1112, 16144, 16380,
+	16164, 696, 2700, 1152, 16144, 16380,
+	16168, 660, 2692, 1192, 16148, 16380,
+	16172, 628, 2684, 1232, 16148, 16380,
+	16176, 592, 2672, 1272, 16152, 16376,
+	16180, 560, 2660, 1312, 16152, 16376,
+	16184, 524, 2648, 1348, 16156, 16376,
+	16192, 492, 2632, 1388, 16160, 16372,
+	16196, 460, 2616, 1428, 16164, 16372,
+	16200, 432, 2600, 1468, 16168, 16368,
+	16204, 400, 2584, 1508, 16176, 16364,
+	16212, 368, 2564, 1548, 16180, 16364,
+	16216, 340, 2544, 1588, 16188, 16360,
+	16220, 312, 2524, 1628, 16196, 16356,
+	16228, 284, 2504, 1668, 16204, 16356,
+	16232, 256, 2480, 1704, 16212, 16352,
+	16240, 232, 2456, 1744, 16224, 16348,
+	16244, 204, 2432, 1780, 16232, 16344,
+	16248, 180, 2408, 1820, 16244, 16340,
+	16256, 156, 2380, 1856, 16256, 16336,
+	16260, 132, 2352, 1896, 16268, 16332,
+	16268, 108, 2324, 1932, 16280, 16328,
+	16272, 88, 2296, 1968, 16292, 16324,
+	16276, 64, 2268, 2004, 16308, 16320,
+	16284, 44, 2236, 2036, 16324, 16312,
+	16288, 24, 2204, 2072, 16340, 16308,
+	16292, 8, 2172, 2108, 16356, 16304,
+	16300, 16372, 2140, 2140, 16372, 16300 };
+
+const uint16_t filter_6tap_64p_183[198] = {
+	16296, 1032, 2196, 1032, 16296, 0,
+	16292, 1004, 2200, 1060, 16304, 16380,
+	16288, 976, 2200, 1088, 16308, 16380,
+	16284, 952, 2196, 1116, 16312, 16376,
+	16284, 924, 2196, 1144, 16320, 16376,
+	16280, 900, 2192, 1172, 16324, 16372,
+	16276, 872, 2192, 1200, 16332, 16368,
+	16276, 848, 2188, 1228, 16340, 16368,
+	16272, 820, 2180, 1256, 16348, 16364,
+	16272, 796, 2176, 1280, 16356, 16360,
+	16268, 768, 2168, 1308, 16364, 16360,
+	16268, 744, 2164, 1336, 16372, 16356,
+	16268, 716, 2156, 1364, 16380, 16352,
+	16264, 692, 2148, 1392, 4, 16352,
+	16264, 668, 2136, 1420, 16, 16348,
+	16264, 644, 2128, 1448, 28, 16344,
+	16264, 620, 2116, 1472, 36, 16340,
+	16264, 596, 2108, 1500, 48, 16340,
+	16268, 572, 2096, 1524, 60, 16336,
+	16268, 548, 2080, 1552, 72, 16332,
+	16268, 524, 2068, 1576, 88, 16328,
+	16268, 504, 2056, 1604, 100, 16324,
+	16272, 480, 2040, 1628, 112, 16324,
+	16272, 456, 2024, 1652, 128, 16320,
+	16272, 436, 2008, 1680, 144, 16316,
+	16276, 416, 1992, 1704, 156, 16312,
+	16276, 392, 1976, 1724, 172, 16308,
+	16280, 372, 1956, 1748, 188, 16308,
+	16280, 352, 1940, 1772, 204, 16304,
+	16284, 332, 1920, 1796, 224, 16300,
+	16288, 312, 1900, 1816, 240, 16296,
+	16288, 296, 1880, 1840, 256, 16296,
+	16292, 276, 1860, 1860, 276, 16292 };
+
+const uint16_t filter_7tap_64p_upscale[231] = {
+	176, 15760, 2488, 2488, 15760, 176, 0,
+	172, 15772, 2404, 2572, 15752, 180, 16380,
+	168, 15784, 2324, 2656, 15740, 184, 16380,
+	164, 15800, 2240, 2736, 15732, 188, 16376,
+	160, 15812, 2152, 2816, 15728, 192, 16376,
+	152, 15828, 2068, 2896, 15724, 192, 16376,
+	148, 15848, 1984, 2972, 15720, 196, 16372,
+	140, 15864, 1896, 3048, 15720, 196, 16372,
+	136, 15884, 1812, 3124, 15720, 196, 16368,
+	128, 15900, 1724, 3196, 15720, 196, 16368,
+	120, 15920, 1640, 3268, 15724, 196, 16368,
+	116, 15940, 1552, 3336, 15732, 196, 16364,
+	108, 15964, 1468, 3400, 15740, 196, 16364,
+	104, 15984, 1384, 3464, 15748, 192, 16364,
+	96, 16004, 1300, 3524, 15760, 188, 16364,
+	88, 16028, 1216, 3584, 15776, 184, 16364,
+	84, 16048, 1132, 3640, 15792, 180, 16360,
+	76, 16072, 1048, 3692, 15812, 176, 16360,
+	68, 16092, 968, 3744, 15832, 168, 16360,
+	64, 16116, 888, 3788, 15856, 160, 16360,
+	56, 16140, 812, 3832, 15884, 152, 16360,
+	52, 16160, 732, 3876, 15912, 144, 16360,
+	44, 16184, 656, 3912, 15944, 136, 16364,
+	40, 16204, 584, 3944, 15976, 124, 16364,
+	32, 16228, 512, 3976, 16012, 116, 16364,
+	28, 16248, 440, 4004, 16048, 104, 16364,
+	24, 16268, 372, 4028, 16092, 88, 16368,
+	20, 16288, 304, 4048, 16132, 76, 16368,
+	12, 16308, 240, 4064, 16180, 60, 16372,
+	8, 16328, 176, 4076, 16228, 48, 16372,
+	4, 16348, 112, 4088, 16276, 32, 16376,
+	0, 16364, 56, 4092, 16328, 16, 16380,
+	0, 0, 0, 4096, 0, 0, 0 };
+
+const uint16_t filter_7tap_64p_117[231] = {
+	92, 15868, 2464, 2464, 15868, 92, 0,
+	96, 15864, 2404, 2528, 15876, 88, 0,
+	100, 15860, 2344, 2584, 15884, 84, 0,
+	104, 15856, 2280, 2644, 15892, 76, 0,
+	108, 15852, 2216, 2700, 15904, 72, 0,
+	108, 15852, 2152, 2756, 15916, 64, 0,
+	112, 15852, 2088, 2812, 15932, 60, 0,
+	112, 15852, 2024, 2864, 15948, 52, 0,
+	112, 15856, 1960, 2916, 15964, 44, 0,
+	116, 15860, 1892, 2964, 15984, 36, 0,
+	116, 15864, 1828, 3016, 16004, 24, 4,
+	116, 15868, 1760, 3060, 16024, 16, 4,
+	116, 15876, 1696, 3108, 16048, 8, 8,
+	116, 15884, 1628, 3152, 16072, 16380, 8,
+	112, 15892, 1564, 3192, 16100, 16372, 8,
+	112, 15900, 1496, 3232, 16124, 16360, 12,
+	112, 15908, 1428, 3268, 16156, 16348, 12,
+	108, 15920, 1364, 3304, 16188, 16336, 16,
+	108, 15928, 1300, 3340, 16220, 16324, 20,
+	104, 15940, 1232, 3372, 16252, 16312, 20,
+	104, 15952, 1168, 3400, 16288, 16300, 24,
+	100, 15964, 1104, 3428, 16328, 16284, 28,
+	96, 15980, 1040, 3452, 16364, 16272, 28,
+	96, 15992, 976, 3476, 20, 16256, 32,
+	92, 16004, 916, 3496, 64, 16244, 36,
+	88, 16020, 856, 3516, 108, 16228, 40,
+	84, 16032, 792, 3532, 152, 16216, 44,
+	80, 16048, 732, 3544, 200, 16200, 48,
+	80, 16064, 676, 3556, 248, 16184, 48,
+	76, 16080, 616, 3564, 296, 16168, 52,
+	72, 16092, 560, 3568, 344, 16156, 56,
+	68, 16108, 504, 3572, 396, 16140, 60,
+	64, 16124, 452, 3576, 452, 16124, 64 };
+
+const uint16_t filter_7tap_64p_150[231] = {
+	16224, 16380, 2208, 2208, 16380, 16224, 0,
+	16232, 16360, 2172, 2236, 16, 16216, 0,
+	16236, 16340, 2140, 2268, 40, 16212, 0,
+	16244, 16324, 2104, 2296, 60, 16204, 4,
+	16252, 16304, 2072, 2324, 84, 16196, 4,
+	16256, 16288, 2036, 2352, 108, 16192, 4,
+	16264, 16268, 2000, 2380, 132, 16184, 8,
+	16272, 16252, 1960, 2408, 160, 16176, 8,
+	16276, 16240, 1924, 2432, 184, 16172, 8,
+	16284, 16224, 1888, 2456, 212, 16164, 8,
+	16288, 16212, 1848, 2480, 240, 16160, 12,
+	16296, 16196, 1812, 2500, 268, 16152, 12,
+	16300, 16184, 1772, 2524, 296, 16144, 12,
+	16308, 16172, 1736, 2544, 324, 16140, 12,
+	16312, 16164, 1696, 2564, 356, 16136, 12,
+	16320, 16152, 1656, 2584, 388, 16128, 12,
+	16324, 16144, 1616, 2600, 416, 16124, 12,
+	16328, 16136, 1576, 2616, 448, 16116, 12,
+	16332, 16128, 1536, 2632, 480, 16112, 12,
+	16340, 16120, 1496, 2648, 516, 16108, 12,
+	16344, 16112, 1456, 2660, 548, 16104, 12,
+	16348, 16104, 1416, 2672, 580, 16100, 12,
+	16352, 16100, 1376, 2684, 616, 16096, 12,
+	16356, 16096, 1336, 2696, 652, 16092, 12,
+	16360, 16092, 1296, 2704, 688, 16088, 12,
+	16364, 16088, 1256, 2712, 720, 16084, 12,
+	16368, 16084, 1220, 2720, 760, 16084, 8,
+	16368, 16080, 1180, 2724, 796, 16080, 8,
+	16372, 16080, 1140, 2732, 832, 16080, 8,
+	16376, 16076, 1100, 2732, 868, 16076, 4,
+	16380, 16076, 1060, 2736, 908, 16076, 4,
+	16380, 16076, 1020, 2740, 944, 16076, 0,
+	0, 16076, 984, 2740, 984, 16076, 0 };
+
+const uint16_t filter_7tap_64p_183[231] = {
+	16216, 324, 1884, 1884, 324, 16216, 0,
+	16220, 304, 1864, 1904, 344, 16216, 0,
+	16224, 284, 1844, 1924, 364, 16216, 0,
+	16224, 264, 1824, 1944, 384, 16212, 16380,
+	16228, 248, 1804, 1960, 408, 16212, 16380,
+	16228, 228, 1784, 1976, 428, 16208, 16380,
+	16232, 212, 1760, 1996, 452, 16208, 16380,
+	16236, 192, 1740, 2012, 472, 16208, 16376,
+	16240, 176, 1716, 2028, 496, 16208, 16376,
+	16240, 160, 1696, 2040, 516, 16208, 16376,
+	16244, 144, 1672, 2056, 540, 16208, 16376,
+	16248, 128, 1648, 2068, 564, 16208, 16372,
+	16252, 112, 1624, 2084, 588, 16208, 16372,
+	16256, 96, 1600, 2096, 612, 16208, 16368,
+	16256, 84, 1576, 2108, 636, 16208, 16368,
+	16260, 68, 1552, 2120, 660, 16208, 16368,
+	16264, 56, 1524, 2132, 684, 16212, 16364,
+	16268, 40, 1500, 2140, 712, 16212, 16364,
+	16272, 28, 1476, 2152, 736, 16216, 16360,
+	16276, 16, 1448, 2160, 760, 16216, 16356,
+	16280, 4, 1424, 2168, 788, 16220, 16356,
+	16284, 16376, 1396, 2176, 812, 16224, 16352,
+	16288, 16368, 1372, 2184, 840, 16224, 16352,
+	16292, 16356, 1344, 2188, 864, 16228, 16348,
+	16292, 16344, 1320, 2196, 892, 16232, 16344,
+	16296, 16336, 1292, 2200, 916, 16236, 16344,
+	16300, 16324, 1264, 2204, 944, 16240, 16340,
+	16304, 16316, 1240, 2208, 972, 16248, 16336,
+	16308, 16308, 1212, 2212, 996, 16252, 16332,
+	16312, 16300, 1184, 2216, 1024, 16256, 16332,
+	16316, 16292, 1160, 2216, 1052, 16264, 16328,
+	16316, 16284, 1132, 2216, 1076, 16268, 16324,
+	16320, 16276, 1104, 2216, 1104, 16276, 16320 };
+
+const uint16_t filter_8tap_64p_upscale[264] = {
+	0, 0, 0, 4096, 0, 0, 0, 0,
+	16376, 20, 16328, 4092, 56, 16364, 4, 0,
+	16372, 36, 16272, 4088, 116, 16340, 12, 0,
+	16364, 56, 16220, 4080, 180, 16320, 20, 0,
+	16360, 76, 16172, 4064, 244, 16296, 24, 16380,
+	16356, 92, 16124, 4048, 312, 16276, 32, 16380,
+	16352, 108, 16080, 4032, 380, 16252, 40, 16380,
+	16344, 124, 16036, 4008, 452, 16228, 48, 16380,
+	16340, 136, 15996, 3980, 524, 16204, 56, 16380,
+	16340, 152, 15956, 3952, 600, 16180, 64, 16376,
+	16336, 164, 15920, 3920, 672, 16156, 76, 16376,
+	16332, 176, 15888, 3884, 752, 16132, 84, 16376,
+	16328, 188, 15860, 3844, 828, 16104, 92, 16372,
+	16328, 200, 15828, 3800, 908, 16080, 100, 16372,
+	16324, 208, 15804, 3756, 992, 16056, 108, 16372,
+	16324, 216, 15780, 3708, 1072, 16032, 120, 16368,
+	16320, 224, 15760, 3656, 1156, 16008, 128, 16368,
+	16320, 232, 15740, 3604, 1240, 15984, 136, 16364,
+	16320, 240, 15724, 3548, 1324, 15960, 144, 16364,
+	16320, 244, 15708, 3488, 1412, 15936, 152, 16360,
+	16320, 248, 15696, 3428, 1496, 15912, 160, 16360,
+	16320, 252, 15688, 3364, 1584, 15892, 172, 16356,
+	16320, 256, 15680, 3296, 1672, 15868, 180, 16352,
+	16320, 256, 15672, 3228, 1756, 15848, 188, 16352,
+	16320, 256, 15668, 3156, 1844, 15828, 192, 16348,
+	16320, 260, 15668, 3084, 1932, 15808, 200, 16348,
+	16320, 256, 15668, 3012, 2020, 15792, 208, 16344,
+	16324, 256, 15668, 2936, 2108, 15772, 216, 16344,
+	16324, 256, 15672, 2856, 2192, 15756, 220, 16340,
+	16324, 252, 15676, 2776, 2280, 15740, 228, 16336,
+	16328, 252, 15684, 2696, 2364, 15728, 232, 16336,
+	16328, 248, 15692, 2616, 2448, 15716, 240, 16332,
+	16332, 244, 15704, 2532, 2532, 15704, 244, 16332 };
+
+const uint16_t filter_8tap_64p_117[264] = {
+	116, 16100, 428, 3564, 428, 16100, 116, 0,
+	112, 16116, 376, 3564, 484, 16084, 120, 16380,
+	104, 16136, 324, 3560, 540, 16064, 124, 16380,
+	100, 16152, 272, 3556, 600, 16048, 128, 16380,
+	96, 16168, 220, 3548, 656, 16032, 136, 16376,
+	88, 16188, 172, 3540, 716, 16016, 140, 16376,
+	84, 16204, 124, 3528, 780, 16000, 144, 16376,
+	80, 16220, 76, 3512, 840, 15984, 148, 16372,
+	76, 16236, 32, 3496, 904, 15968, 152, 16372,
+	68, 16252, 16376, 3480, 968, 15952, 156, 16372,
+	64, 16268, 16332, 3456, 1032, 15936, 160, 16372,
+	60, 16284, 16292, 3432, 1096, 15920, 164, 16368,
+	56, 16300, 16252, 3408, 1164, 15908, 164, 16368,
+	48, 16316, 16216, 3380, 1228, 15892, 168, 16368,
+	44, 16332, 16180, 3348, 1296, 15880, 168, 16368,
+	40, 16348, 16148, 3316, 1364, 15868, 172, 16364,
+	36, 16360, 16116, 3284, 1428, 15856, 172, 16364,
+	32, 16376, 16084, 3248, 1496, 15848, 176, 16364,
+	28, 4, 16052, 3208, 1564, 15836, 176, 16364,
+	24, 16, 16028, 3168, 1632, 15828, 176, 16364,
+	20, 28, 16000, 3124, 1700, 15820, 176, 16364,
+	16, 40, 15976, 3080, 1768, 15812, 176, 16364,
+	12, 52, 15952, 3036, 1836, 15808, 176, 16364,
+	8, 64, 15932, 2988, 1904, 15800, 176, 16364,
+	4, 76, 15912, 2940, 1972, 15800, 172, 16364,
+	4, 84, 15892, 2888, 2040, 15796, 172, 16364,
+	0, 96, 15876, 2836, 2104, 15792, 168, 16364,
+	16380, 104, 15864, 2780, 2172, 15792, 164, 16364,
+	16380, 112, 15848, 2724, 2236, 15792, 160, 16364,
+	16376, 120, 15836, 2668, 2300, 15796, 156, 16368,
+	16376, 128, 15828, 2608, 2364, 15800, 152, 16368,
+	16372, 136, 15816, 2548, 2428, 15804, 148, 16368,
+	16372, 140, 15812, 2488, 2488, 15812, 140, 16372 };
+
+const uint16_t filter_8tap_64p_150[264] = {
+	16380, 16020, 1032, 2756, 1032, 16020, 16380, 0,
+	0, 16020, 992, 2756, 1068, 16024, 16376, 0,
+	4, 16020, 952, 2752, 1108, 16024, 16372, 0,
+	8, 16020, 916, 2748, 1148, 16028, 16368, 0,
+	12, 16020, 876, 2744, 1184, 16032, 16364, 4,
+	16, 16020, 840, 2740, 1224, 16036, 16356, 4,
+	20, 16024, 800, 2732, 1264, 16040, 16352, 4,
+	20, 16024, 764, 2724, 1304, 16044, 16348, 8,
+	24, 16028, 728, 2716, 1344, 16052, 16340, 8,
+	28, 16028, 692, 2704, 1380, 16056, 16336, 12,
+	28, 16032, 656, 2696, 1420, 16064, 16328, 12,
+	32, 16036, 620, 2684, 1460, 16072, 16324, 12,
+	36, 16040, 584, 2668, 1500, 16080, 16316, 16,
+	36, 16044, 548, 2656, 1536, 16088, 16308, 16,
+	36, 16048, 516, 2640, 1576, 16096, 16304, 20,
+	40, 16052, 480, 2624, 1612, 16108, 16296, 20,
+	40, 16060, 448, 2608, 1652, 16120, 16288, 20,
+	44, 16064, 416, 2588, 1692, 16132, 16280, 24,
+	44, 16068, 384, 2568, 1728, 16144, 16276, 24,
+	44, 16076, 352, 2548, 1764, 16156, 16268, 28,
+	44, 16080, 320, 2528, 1804, 16168, 16260, 28,
+	44, 16088, 292, 2508, 1840, 16184, 16252, 28,
+	44, 16096, 264, 2484, 1876, 16200, 16244, 32,
+	48, 16100, 232, 2460, 1912, 16216, 16236, 32,
+	48, 16108, 204, 2436, 1948, 16232, 16228, 32,
+	48, 16116, 176, 2412, 1980, 16248, 16220, 36,
+	48, 16124, 152, 2384, 2016, 16264, 16216, 36,
+	44, 16128, 124, 2356, 2052, 16284, 16208, 36,
+	44, 16136, 100, 2328, 2084, 16304, 16200, 40,
+	44, 16144, 72, 2300, 2116, 16324, 16192, 40,
+	44, 16152, 48, 2272, 2148, 16344, 16184, 40,
+	44, 16160, 24, 2244, 2180, 16364, 16176, 40,
+	44, 16168, 4, 2212, 2212, 4, 16168, 44 };
+
+const uint16_t filter_8tap_64p_183[264] = {
+	16264, 16264, 1164, 2244, 1164, 16264, 16264, 0,
+	16268, 16256, 1136, 2240, 1188, 16272, 16260, 0,
+	16272, 16248, 1108, 2240, 1216, 16280, 16256, 0,
+	16276, 16240, 1080, 2236, 1240, 16292, 16252, 0,
+	16280, 16232, 1056, 2236, 1268, 16300, 16248, 0,
+	16284, 16224, 1028, 2232, 1292, 16312, 16244, 0,
+	16288, 16216, 1000, 2228, 1320, 16324, 16240, 0,
+	16292, 16212, 976, 2224, 1344, 16336, 16236, 0,
+	16296, 16204, 948, 2220, 1372, 16348, 16232, 0,
+	16300, 16200, 920, 2212, 1396, 16360, 16228, 4,
+	16304, 16196, 896, 2204, 1424, 16372, 16224, 4,
+	16308, 16188, 868, 2200, 1448, 0, 16220, 4,
+	16312, 16184, 844, 2192, 1472, 12, 16216, 4,
+	16316, 16180, 816, 2184, 1500, 28, 16212, 4,
+	16320, 16176, 792, 2172, 1524, 40, 16208, 4,
+	16324, 16172, 764, 2164, 1548, 56, 16204, 0,
+	16328, 16172, 740, 2156, 1572, 72, 16200, 0,
+	16328, 16168, 712, 2144, 1596, 88, 16196, 0,
+	16332, 16164, 688, 2132, 1620, 100, 16192, 0,
+	16336, 16164, 664, 2120, 1644, 120, 16192, 0,
+	16340, 16160, 640, 2108, 1668, 136, 16188, 0,
+	16344, 16160, 616, 2096, 1688, 152, 16184, 0,
+	16344, 16160, 592, 2080, 1712, 168, 16180, 0,
+	16348, 16156, 568, 2068, 1736, 188, 16176, 16380,
+	16352, 16156, 544, 2052, 1756, 204, 16176, 16380,
+	16352, 16156, 520, 2036, 1780, 224, 16172, 16380,
+	16356, 16156, 496, 2024, 1800, 244, 16172, 16380,
+	16360, 16156, 472, 2008, 1820, 260, 16168, 16376,
+	16360, 16156, 452, 1988, 1840, 280, 16164, 16376,
+	16364, 16156, 428, 1972, 1860, 300, 16164, 16376,
+	16364, 16156, 408, 1956, 1880, 320, 16164, 16372,
+	16368, 16160, 384, 1936, 1900, 344, 16160, 16372,
+	16368, 16160, 364, 1920, 1920, 364, 16160, 16368 };
+
 const uint16_t *get_filter_3tap_16p(struct fixed31_32 ratio)
 {
 	if (ratio.value < dal_fixed31_32_one.value)
@@ -499,3 +1059,51 @@ const uint16_t *get_filter_4tap_64p(struct fixed31_32 ratio)
 	else
 		return filter_4tap_64p_183;
 }
+
+const uint16_t *get_filter_5tap_64p(struct fixed31_32 ratio)
+{
+	if (ratio.value < dal_fixed31_32_one.value)
+		return filter_5tap_64p_upscale;
+	else if (ratio.value < dal_fixed31_32_from_fraction(4, 3).value)
+		return filter_5tap_64p_117;
+	else if (ratio.value < dal_fixed31_32_from_fraction(5, 3).value)
+		return filter_5tap_64p_150;
+	else
+		return filter_5tap_64p_183;
+}
+
+const uint16_t *get_filter_6tap_64p(struct fixed31_32 ratio)
+{
+	if (ratio.value < dal_fixed31_32_one.value)
+		return filter_6tap_64p_upscale;
+	else if (ratio.value < dal_fixed31_32_from_fraction(4, 3).value)
+		return filter_6tap_64p_117;
+	else if (ratio.value < dal_fixed31_32_from_fraction(5, 3).value)
+		return filter_6tap_64p_150;
+	else
+		return filter_6tap_64p_183;
+}
+
+const uint16_t *get_filter_7tap_64p(struct fixed31_32 ratio)
+{
+	if (ratio.value < dal_fixed31_32_one.value)
+		return filter_7tap_64p_upscale;
+	else if (ratio.value < dal_fixed31_32_from_fraction(4, 3).value)
+		return filter_7tap_64p_117;
+	else if (ratio.value < dal_fixed31_32_from_fraction(5, 3).value)
+		return filter_7tap_64p_150;
+	else
+		return filter_7tap_64p_183;
+}
+
+const uint16_t *get_filter_8tap_64p(struct fixed31_32 ratio)
+{
+	if (ratio.value < dal_fixed31_32_one.value)
+		return filter_8tap_64p_upscale;
+	else if (ratio.value < dal_fixed31_32_from_fraction(4, 3).value)
+		return filter_8tap_64p_117;
+	else if (ratio.value < dal_fixed31_32_from_fraction(5, 3).value)
+		return filter_8tap_64p_150;
+	else
+		return filter_8tap_64p_183;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h
index a510d3fe48ec..9c5cb0ee4243 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h
@@ -186,5 +186,9 @@ const uint16_t *get_filter_3tap_16p(struct fixed31_32 ratio);
 const uint16_t *get_filter_3tap_64p(struct fixed31_32 ratio);
 const uint16_t *get_filter_4tap_16p(struct fixed31_32 ratio);
 const uint16_t *get_filter_4tap_64p(struct fixed31_32 ratio);
+const uint16_t *get_filter_5tap_64p(struct fixed31_32 ratio);
+const uint16_t *get_filter_6tap_64p(struct fixed31_32 ratio);
+const uint16_t *get_filter_7tap_64p(struct fixed31_32 ratio);
+const uint16_t *get_filter_8tap_64p(struct fixed31_32 ratio);
 
 #endif
-- 
2.9.3

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[PATCH 07/15] drm/amd/display: Surface Validation Fixes + Audio Mask

[Harry Wentland]

From: Leon Elazar <leon.elazar@amd.com>

1. dc: Adding missing mask for audio register DCCG_AUDIO_DTO_SOURCE
2. Changing the surface validation to check the limits of the clip rect instead of the source rect.

Change-Id: Ica0d1a8543f958e20bd94a27ebe1a1fd805e1dbf
Signed-off-by: Leon Elazar <leon.elazar@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h          | 1 +
 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c | 8 ++++----
 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c | 4 ++--
 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c   | 4 ++--
 4 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.h b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.h
index b98ee2d2a9c7..0dc5ff137c7a 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.h
@@ -48,6 +48,7 @@
 #define AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)\
 		SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\
 		SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\
+		SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO2_USE_512FBR_DTO, mask_sh),\
 		SF(DCCG_AUDIO_DTO0_MODULE, DCCG_AUDIO_DTO0_MODULE, mask_sh),\
 		SF(DCCG_AUDIO_DTO0_PHASE, DCCG_AUDIO_DTO0_PHASE, mask_sh),\
 		SF(DCCG_AUDIO_DTO1_MODULE, DCCG_AUDIO_DTO1_MODULE, mask_sh),\
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
index cd3942df70a7..80b2359a3cb4 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
@@ -1009,10 +1009,10 @@ static bool dce110_validate_surface_sets(
 		if (set[i].surface_count > 2)
 			return false;
 
-		if (set[i].surfaces[0]->src_rect.width
-				< set[i].stream->src.width
-				|| set[i].surfaces[0]->src_rect.height
-				< set[i].stream->src.height)
+		if (set[i].surfaces[0]->clip_rect.width
+				> set[i].stream->src.width
+				|| set[i].surfaces[0]->clip_rect.height
+				> set[i].stream->src.height)
 			return false;
 		if (set[i].surfaces[0]->format
 				>= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
index 526c106f6ebf..ce6c69fd1041 100644
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
@@ -975,9 +975,9 @@ static bool dce112_validate_surface_sets(
 			return false;
 
 		if (set[i].surfaces[0]->clip_rect.width
-				< set[i].stream->src.width
+				> set[i].stream->src.width
 				|| set[i].surfaces[0]->clip_rect.height
-				< set[i].stream->src.height)
+				> set[i].stream->src.height)
 			return false;
 		if (set[i].surfaces[0]->format
 				>= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
index 272c7fc31406..fbbdd0ee2d4c 100644
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
@@ -805,9 +805,9 @@ static bool dce80_validate_surface_sets(
 			return false;
 
 		if (set[i].surfaces[0]->clip_rect.width
-				!= set[i].stream->src.width
+				> set[i].stream->src.width
 				|| set[i].surfaces[0]->clip_rect.height
-				!= set[i].stream->src.height)
+				> set[i].stream->src.height)
 			return false;
 		if (set[i].surfaces[0]->format
 				>= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
-- 
2.9.3

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[PATCH 08/15] drm/amd/display: Fix warnings in amdgpu_dm

[Harry Wentland]

Change-Id: I4cb785727ffd367716728afb711b9905722d1d22
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index 3912dc80c17b..d0b855abd665 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -974,7 +974,7 @@ static void decide_crtc_timing_for_drm_display_mode(
 }
 
 static struct dc_stream *create_stream_for_sink(
-		const struct amdgpu_connector *aconnector,
+		struct amdgpu_connector *aconnector,
 		const struct drm_display_mode *drm_mode,
 		const struct dm_connector_state *dm_state)
 {
-- 
2.9.3

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[PATCH 09/15] drm/amd/display: Fix warnings in DC

[Harry Wentland]

Change-Id: I59b57232a901a0f574fa8436910152f04a6b2be9
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c                          | 2 --
 drivers/gpu/drm/amd/display/dc/core/dc_surface.c                  | 2 +-
 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c                      | 1 -
 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c | 1 -
 4 files changed, 1 insertion(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 6516c275e0c7..e0d9572768cb 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1068,7 +1068,6 @@ bool dc_pre_update_surfaces_to_stream(
 	int prev_disp_clk = core_dc->current_context->dispclk_khz;
 	struct dc_stream_status *stream_status = NULL;
 	struct validate_context *context;
-	struct validate_context *temp_context;
 	bool ret = true;
 
 	pre_surface_trace(dc, new_surfaces, new_surface_count);
@@ -1425,7 +1424,6 @@ void dc_update_surfaces_for_stream(struct dc *dc,
 		if (update_type == UPDATE_TYPE_FULL) {
 			for (j = 0; j < context->res_ctx.pool->pipe_count; j++) {
 				struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
-				struct core_stream *stream = pipe_ctx->stream;
 
 				if (pipe_ctx->surface != surface)
 					continue;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
index 21fedd447bd1..943895faee49 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
@@ -121,7 +121,7 @@ const struct dc_surface_status *dc_surface_get_status(
 		const struct dc_surface *dc_surface)
 {
 	struct dc_surface_status *surface_status;
-	struct core_surface *core_surface = DC_SURFACE_TO_CORE(dc_surface);;
+	struct core_surface *core_surface = DC_SURFACE_TO_CORE(dc_surface);
 	struct core_dc *core_dc;
 	int i;
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
index 7005ebb28d46..45a3079c0973 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
@@ -292,7 +292,6 @@ static void dce_abm_init(struct abm *abm)
 static bool dce_abm_set_level(struct abm *abm, uint32_t level)
 {
 	struct dce_abm *abm_dce = TO_DCE_ABM(abm);
-	struct dc_context *ctx = abm_dce->base.ctx;
 
 	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
 			100, 800);
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
index 682a3de7ba48..c95b69446ced 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
@@ -74,7 +74,6 @@ static bool dce110_timing_generator_v_disable_crtc(struct timing_generator *tg)
 
 static void dce110_timing_generator_v_blank_crtc(struct timing_generator *tg)
 {
-	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
 	uint32_t addr = mmCRTCV_BLANK_CONTROL;
 	uint32_t value = dm_read_reg(tg->ctx, addr);
 
-- 
2.9.3

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[PATCH 10/15] drm/amd/display: remove apply_clk_constraints, used validate_bandwidth universally

[Harry Wentland]

From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>

Change-Id: I4264c415862c6b4e64546a04c90b4be41496a0fa
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c           | 50 ++++++++++++++--------
 .../drm/amd/display/dc/dce100/dce100_resource.c    | 10 +++--
 .../drm/amd/display/dc/dce110/dce110_resource.c    | 18 ++++----
 .../drm/amd/display/dc/dce112/dce112_resource.c    | 18 ++++----
 .../drm/amd/display/dc/dce112/dce112_resource.h    |  2 +-
 .../gpu/drm/amd/display/dc/dce80/dce80_resource.c  |  4 +-
 drivers/gpu/drm/amd/display/dc/inc/core_status.h   |  1 -
 drivers/gpu/drm/amd/display/dc/inc/core_types.h    |  6 +--
 8 files changed, 59 insertions(+), 50 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index e0d9572768cb..da0f72071ef5 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1144,12 +1144,11 @@ bool dc_pre_update_surfaces_to_stream(
 			}
 		}
 
-	if (core_dc->res_pool->funcs->validate_bandwidth)
-		if (core_dc->res_pool->funcs->validate_bandwidth(core_dc, context) != DC_OK) {
-			BREAK_TO_DEBUGGER();
-			ret = false;
-			goto unexpected_fail;
-		}
+	if (!core_dc->res_pool->funcs->validate_bandwidth(core_dc, context)) {
+		BREAK_TO_DEBUGGER();
+		ret = false;
+		goto unexpected_fail;
+	}
 
 	if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)
 			&& prev_disp_clk < context->dispclk_khz) {
@@ -1184,28 +1183,36 @@ bool dc_pre_update_surfaces_to_stream(
 
 bool dc_post_update_surfaces_to_stream(struct dc *dc)
 {
-	struct core_dc *core_dc = DC_TO_CORE(dc);
 	int i;
+	struct core_dc *core_dc = DC_TO_CORE(dc);
+	struct validate_context *context = dm_alloc(sizeof(struct validate_context));
+
+	if (!context) {
+		dm_error("%s: failed to create validate ctx\n", __func__);
+		return false;
+	}
+	resource_validate_ctx_copy_construct(core_dc->current_context, context);
 
 	post_surface_trace(dc);
 
-	for (i = 0; i < core_dc->current_context->res_ctx.pool->pipe_count; i++)
-		if (core_dc->current_context->res_ctx.pipe_ctx[i].stream == NULL) {
-			core_dc->current_context->res_ctx.pipe_ctx[i].pipe_idx = i;
+	for (i = 0; i < context->res_ctx.pool->pipe_count; i++)
+		if (context->res_ctx.pipe_ctx[i].stream == NULL) {
+			context->res_ctx.pipe_ctx[i].pipe_idx = i;
 			core_dc->hwss.power_down_front_end(
-					core_dc, &core_dc->current_context->res_ctx.pipe_ctx[i]);
-		}
-	if (core_dc->res_pool->funcs->validate_bandwidth)
-		if (core_dc->res_pool->funcs->validate_bandwidth(
-				core_dc, core_dc->current_context) != DC_OK) {
-			BREAK_TO_DEBUGGER();
-			return false;
+					core_dc, &context->res_ctx.pipe_ctx[i]);
 		}
+	if (!core_dc->res_pool->funcs->validate_bandwidth(core_dc, context)) {
+		BREAK_TO_DEBUGGER();
+		return false;
+	}
 
 	core_dc->hwss.set_bandwidth(core_dc);
 
-	pplib_apply_display_requirements(
-			core_dc, core_dc->current_context, &core_dc->current_context->pp_display_cfg);
+	/*TODO: dce specific*/
+	pplib_apply_display_requirements(core_dc, context, &context->pp_display_cfg);
+
+	resource_validate_ctx_destruct(core_dc->current_context);
+	core_dc->current_context = context;
 
 	return true;
 }
@@ -1472,6 +1479,11 @@ void dc_update_surfaces_for_stream(struct dc *dc,
 				*(updates[i].hdr_static_metadata);
 	}
 
+	if (update_type == UPDATE_TYPE_FULL &&
+			!core_dc->res_pool->funcs->validate_bandwidth(core_dc, context)) {
+		BREAK_TO_DEBUGGER();
+		return;
+	}
 
 	if (!surface_count)  /* reset */
 		core_dc->hwss.apply_ctx_for_surface(core_dc, NULL, context);
diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
index 9ed7c06132fe..fc85efafb104 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
@@ -765,14 +765,14 @@ static enum dc_status validate_mapped_resource(
 	return DC_OK;
 }
 
-enum dc_status dce100_validate_bandwidth(
+bool dce100_validate_bandwidth(
 	const struct core_dc *dc,
 	struct validate_context *context)
 {
 	/* TODO implement when needed but for now hardcode max value*/
 	context->dispclk_khz = 681000;
 
-	return DC_OK;
+	return false;
 }
 
 static bool dce100_validate_surface_sets(
@@ -840,7 +840,8 @@ enum dc_status dce100_validate_with_context(
 		result = resource_build_scaling_params_for_context(dc, context);
 
 	if (result == DC_OK)
-		result = dce100_validate_bandwidth(dc, context);
+		if (!dce100_validate_bandwidth(dc, context))
+			result = DC_FAIL_BANDWIDTH_VALIDATE;
 
 	return result;
 }
@@ -873,7 +874,8 @@ enum dc_status dce100_validate_guaranteed(
 	}
 
 	if (result == DC_OK)
-		result = dce100_validate_bandwidth(dc, context);
+		if (!dce100_validate_bandwidth(dc, context))
+			result = DC_FAIL_BANDWIDTH_VALIDATE;
 
 	return result;
 }
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
index 80b2359a3cb4..b9d0b5eeca13 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
@@ -912,30 +912,28 @@ static enum dc_status validate_mapped_resource(
 	return DC_OK;
 }
 
-enum dc_status dce110_validate_bandwidth(
+bool dce110_validate_bandwidth(
 	const struct core_dc *dc,
 	struct validate_context *context)
 {
-	enum dc_status result = DC_ERROR_UNEXPECTED;
+	bool result = false;
 
 	dm_logger_write(
 		dc->ctx->logger, LOG_BANDWIDTH_CALCS,
 		"%s: start",
 		__func__);
 
-	if (!bw_calcs(
+	if (bw_calcs(
 			dc->ctx,
 			&dc->bw_dceip,
 			&dc->bw_vbios,
 			context->res_ctx.pipe_ctx,
 			context->res_ctx.pool->pipe_count,
 			&context->bw_results))
-		result =  DC_FAIL_BANDWIDTH_VALIDATE;
-	else
-		result =  DC_OK;
+		result =  true;
 	context->dispclk_khz = context->bw_results.dispclk_khz;
 
-	if (result == DC_FAIL_BANDWIDTH_VALIDATE)
+	if (!result)
 		dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_VALIDATION,
 			"%s: %dx%d@%d Bandwidth validation failed!\n",
 			__func__,
@@ -1073,7 +1071,8 @@ enum dc_status dce110_validate_with_context(
 		result = resource_build_scaling_params_for_context(dc, context);
 
 	if (result == DC_OK)
-		result = dce110_validate_bandwidth(dc, context);
+		if (!dce110_validate_bandwidth(dc, context))
+			result = DC_FAIL_BANDWIDTH_VALIDATE;
 
 	return result;
 }
@@ -1106,7 +1105,8 @@ enum dc_status dce110_validate_guaranteed(
 	}
 
 	if (result == DC_OK)
-		result = dce110_validate_bandwidth(dc, context);
+		if (!dce110_validate_bandwidth(dc, context))
+			result = DC_FAIL_BANDWIDTH_VALIDATE;
 
 	return result;
 }
diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
index ce6c69fd1041..32aa1b5bf1f9 100644
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
@@ -836,30 +836,28 @@ static enum dc_status validate_mapped_resource(
 	return DC_OK;
 }
 
-enum dc_status dce112_validate_bandwidth(
+bool dce112_validate_bandwidth(
 	const struct core_dc *dc,
 	struct validate_context *context)
 {
-	enum dc_status result = DC_ERROR_UNEXPECTED;
+	bool result = false;
 
 	dm_logger_write(
 		dc->ctx->logger, LOG_BANDWIDTH_CALCS,
 		"%s: start",
 		__func__);
 
-	if (!bw_calcs(
+	if (bw_calcs(
 			dc->ctx,
 			&dc->bw_dceip,
 			&dc->bw_vbios,
 			context->res_ctx.pipe_ctx,
 			context->res_ctx.pool->pipe_count,
 			&context->bw_results))
-		result =  DC_FAIL_BANDWIDTH_VALIDATE;
-	else
-		result =  DC_OK;
+		result = true;
 	context->dispclk_khz = context->bw_results.dispclk_khz;
 
-	if (result == DC_FAIL_BANDWIDTH_VALIDATE)
+	if (!result)
 		dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_VALIDATION,
 			"%s: Bandwidth validation failed!",
 			__func__);
@@ -1026,7 +1024,8 @@ enum dc_status dce112_validate_with_context(
 		result = resource_build_scaling_params_for_context(dc, context);
 
 	if (result == DC_OK)
-		result = dce112_validate_bandwidth(dc, context);
+		if (!dce112_validate_bandwidth(dc, context))
+			result = DC_FAIL_BANDWIDTH_VALIDATE;
 
 	return result;
 }
@@ -1059,7 +1058,8 @@ enum dc_status dce112_validate_guaranteed(
 	}
 
 	if (result == DC_OK)
-		result = dce112_validate_bandwidth(dc, context);
+		if (!dce112_validate_bandwidth(dc, context))
+			result = DC_FAIL_BANDWIDTH_VALIDATE;
 
 	return result;
 }
diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h
index faa8c45a3544..dc842aace766 100644
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h
@@ -46,7 +46,7 @@ enum dc_status dce112_validate_guaranteed(
 		const struct dc_stream *dc_stream,
 		struct validate_context *context);
 
-enum dc_status dce112_validate_bandwidth(
+bool dce112_validate_bandwidth(
 	const struct core_dc *dc,
 	struct validate_context *context);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
index fbbdd0ee2d4c..a3e8182885b2 100644
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
@@ -780,7 +780,7 @@ static enum dc_status validate_mapped_resource(
 	return DC_OK;
 }
 
-enum dc_status dce80_validate_bandwidth(
+bool dce80_validate_bandwidth(
 	const struct core_dc *dc,
 	struct validate_context *context)
 {
@@ -788,7 +788,7 @@ enum dc_status dce80_validate_bandwidth(
 	context->dispclk_khz = 681000;
 	context->bw_results.required_yclk = 250000 * MEMORY_TYPE_MULTIPLIER;
 
-	return DC_OK;
+	return true;
 }
 
 static bool dce80_validate_surface_sets(
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_status.h b/drivers/gpu/drm/amd/display/dc/inc/core_status.h
index 23d52aea55dd..128617dabc4a 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_status.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_status.h
@@ -41,7 +41,6 @@ enum dc_status {
 	DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED = 11,
 	DC_FAIL_BANDWIDTH_VALIDATE = 12, /* BW and Watermark validation */
 	DC_FAIL_SCALING = 13,
-	DC_FAIL_CLK_CONSTRAINT = 14,
 
 	DC_ERROR_UNEXPECTED = -1
 };
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index 124df6795b34..e8fe333c5918 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -207,11 +207,7 @@ struct resource_funcs {
 					const struct dc_stream *stream,
 					struct validate_context *context);
 
-	enum dc_status (*validate_bandwidth)(
-					const struct core_dc *dc,
-					struct validate_context *context);
-
-	struct validate_context *(*apply_clk_constraints)(
+	bool (*validate_bandwidth)(
 					const struct core_dc *dc,
 					struct validate_context *context);
 
-- 
2.9.3

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[PATCH 11/15] drm/amd/display: bandwidth update fix

[Harry Wentland]

From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>

Change-Id: Ia8b4a52b294cb2aaa8e4d3cd1a2df9b8d39aea61
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c           | 173 +------------
 .../amd/display/dc/dce100/dce100_hw_sequencer.c    |  15 +-
 .../amd/display/dc/dce110/dce110_hw_sequencer.c    | 279 ++++++++++++---------
 .../drm/amd/display/dc/dce80/dce80_hw_sequencer.c  |  16 +-
 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h  |   9 +-
 5 files changed, 179 insertions(+), 313 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index da0f72071ef5..0ec2c4f39735 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -795,159 +795,6 @@ static bool streams_changed(
 	return false;
 }
 
-static void fill_display_configs(
-	const struct validate_context *context,
-	struct dm_pp_display_configuration *pp_display_cfg)
-{
-	int j;
-	int num_cfgs = 0;
-
-	for (j = 0; j < context->stream_count; j++) {
-		int k;
-
-		const struct core_stream *stream = context->streams[j];
-		struct dm_pp_single_disp_config *cfg =
-			&pp_display_cfg->disp_configs[num_cfgs];
-		const struct pipe_ctx *pipe_ctx = NULL;
-
-		for (k = 0; k < MAX_PIPES; k++)
-			if (stream == context->res_ctx.pipe_ctx[k].stream) {
-				pipe_ctx = &context->res_ctx.pipe_ctx[k];
-				break;
-			}
-
-		ASSERT(pipe_ctx != NULL);
-
-		num_cfgs++;
-		cfg->signal = pipe_ctx->stream->signal;
-		cfg->pipe_idx = pipe_ctx->pipe_idx;
-		cfg->src_height = stream->public.src.height;
-		cfg->src_width = stream->public.src.width;
-		cfg->ddi_channel_mapping =
-			stream->sink->link->ddi_channel_mapping.raw;
-		cfg->transmitter =
-			stream->sink->link->link_enc->transmitter;
-		cfg->link_settings.lane_count =
-			stream->sink->link->public.cur_link_settings.lane_count;
-		cfg->link_settings.link_rate =
-			stream->sink->link->public.cur_link_settings.link_rate;
-		cfg->link_settings.link_spread =
-			stream->sink->link->public.cur_link_settings.link_spread;
-		cfg->sym_clock = stream->phy_pix_clk;
-		/* Round v_refresh*/
-		cfg->v_refresh = stream->public.timing.pix_clk_khz * 1000;
-		cfg->v_refresh /= stream->public.timing.h_total;
-		cfg->v_refresh = (cfg->v_refresh + stream->public.timing.v_total / 2)
-							/ stream->public.timing.v_total;
-	}
-
-	pp_display_cfg->display_count = num_cfgs;
-}
-
-static uint32_t get_min_vblank_time_us(const struct validate_context *context)
-{
-	uint8_t j;
-	uint32_t min_vertical_blank_time = -1;
-
-		for (j = 0; j < context->stream_count; j++) {
-			const struct dc_stream *stream = &context->streams[j]->public;
-			uint32_t vertical_blank_in_pixels = 0;
-			uint32_t vertical_blank_time = 0;
-
-			vertical_blank_in_pixels = stream->timing.h_total *
-				(stream->timing.v_total
-					- stream->timing.v_addressable);
-
-			vertical_blank_time = vertical_blank_in_pixels
-				* 1000 / stream->timing.pix_clk_khz;
-
-			if (min_vertical_blank_time > vertical_blank_time)
-				min_vertical_blank_time = vertical_blank_time;
-		}
-
-	return min_vertical_blank_time;
-}
-
-static int determine_sclk_from_bounding_box(
-		const struct core_dc *dc,
-		int required_sclk)
-{
-	int i;
-
-	/*
-	 * Some asics do not give us sclk levels, so we just report the actual
-	 * required sclk
-	 */
-	if (dc->sclk_lvls.num_levels == 0)
-		return required_sclk;
-
-	for (i = 0; i < dc->sclk_lvls.num_levels; i++) {
-		if (dc->sclk_lvls.clocks_in_khz[i] >= required_sclk)
-			return dc->sclk_lvls.clocks_in_khz[i];
-	}
-	/*
-	 * even maximum level could not satisfy requirement, this
-	 * is unexpected at this stage, should have been caught at
-	 * validation time
-	 */
-	ASSERT(0);
-	return dc->sclk_lvls.clocks_in_khz[dc->sclk_lvls.num_levels - 1];
-}
-
-void pplib_apply_display_requirements(
-	struct core_dc *dc,
-	const struct validate_context *context,
-	struct dm_pp_display_configuration *pp_display_cfg)
-{
-	pp_display_cfg->all_displays_in_sync =
-		context->bw_results.all_displays_in_sync;
-	pp_display_cfg->nb_pstate_switch_disable =
-			context->bw_results.nbp_state_change_enable == false;
-	pp_display_cfg->cpu_cc6_disable =
-			context->bw_results.cpuc_state_change_enable == false;
-	pp_display_cfg->cpu_pstate_disable =
-			context->bw_results.cpup_state_change_enable == false;
-	pp_display_cfg->cpu_pstate_separation_time =
-			context->bw_results.blackout_recovery_time_us;
-
-	pp_display_cfg->min_memory_clock_khz = context->bw_results.required_yclk
-		/ MEMORY_TYPE_MULTIPLIER;
-
-	pp_display_cfg->min_engine_clock_khz = determine_sclk_from_bounding_box(
-			dc,
-			context->bw_results.required_sclk);
-
-	pp_display_cfg->min_engine_clock_deep_sleep_khz
-			= context->bw_results.required_sclk_deep_sleep;
-
-	pp_display_cfg->avail_mclk_switch_time_us =
-						get_min_vblank_time_us(context);
-	/* TODO: dce11.2*/
-	pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0;
-
-	pp_display_cfg->disp_clk_khz = context->dispclk_khz;
-
-	fill_display_configs(context, pp_display_cfg);
-
-	/* TODO: is this still applicable?*/
-	if (pp_display_cfg->display_count == 1) {
-		const struct dc_crtc_timing *timing =
-			&context->streams[0]->public.timing;
-
-		pp_display_cfg->crtc_index =
-			pp_display_cfg->disp_configs[0].pipe_idx;
-		pp_display_cfg->line_time_in_us = timing->h_total * 1000
-							/ timing->pix_clk_khz;
-	}
-
-	if (memcmp(&dc->prev_display_config, pp_display_cfg, sizeof(
-			struct dm_pp_display_configuration)) !=  0)
-		dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
-
-	dc->prev_display_config = *pp_display_cfg;
-
-}
-
 bool dc_commit_streams(
 	struct dc *dc,
 	const struct dc_stream *streams[],
@@ -1036,9 +883,6 @@ bool dc_commit_streams(
 				context->streams[i]->public.timing.pix_clk_khz);
 	}
 
-	pplib_apply_display_requirements(core_dc,
-			context, &context->pp_display_cfg);
-
 	resource_validate_ctx_destruct(core_dc->current_context);
 
 	if (core_dc->temp_flip_context != core_dc->current_context) {
@@ -1065,7 +909,6 @@ bool dc_pre_update_surfaces_to_stream(
 {
 	int i, j;
 	struct core_dc *core_dc = DC_TO_CORE(dc);
-	int prev_disp_clk = core_dc->current_context->dispclk_khz;
 	struct dc_stream_status *stream_status = NULL;
 	struct validate_context *context;
 	bool ret = true;
@@ -1150,16 +993,7 @@ bool dc_pre_update_surfaces_to_stream(
 		goto unexpected_fail;
 	}
 
-	if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)
-			&& prev_disp_clk < context->dispclk_khz) {
-		pplib_apply_display_requirements(core_dc, context,
-						&context->pp_display_cfg);
-		context->res_ctx.pool->display_clock->funcs->set_clock(
-				context->res_ctx.pool->display_clock,
-				context->dispclk_khz * 115 / 100);
-		core_dc->current_context->bw_results.dispclk_khz = context->dispclk_khz;
-		core_dc->current_context->dispclk_khz = context->dispclk_khz;
-	}
+	core_dc->hwss.set_bandwidth(core_dc, context, false);
 
 	for (i = 0; i < new_surface_count; i++)
 		for (j = 0; j < context->res_ctx.pool->pipe_count; j++) {
@@ -1206,10 +1040,7 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc)
 		return false;
 	}
 
-	core_dc->hwss.set_bandwidth(core_dc);
-
-	/*TODO: dce specific*/
-	pplib_apply_display_requirements(core_dc, context, &context->pp_display_cfg);
+	core_dc->hwss.set_bandwidth(core_dc, context, true);
 
 	resource_validate_ctx_destruct(core_dc->current_context);
 	core_dc->current_context = context;
diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c
index e2fe024e1182..bd8e19f1038b 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c
@@ -104,22 +104,18 @@ static bool dce100_enable_display_power_gating(
 		return false;
 }
 
-static void set_display_mark_for_pipe_if_needed(struct core_dc *dc,
-		struct pipe_ctx *pipe_ctx,
-		struct validate_context *context)
-{
-	/* Do nothing until we have proper bandwitdth calcs */
-}
-
 static void set_displaymarks(
 		const struct core_dc *dc, struct validate_context *context)
 {
 	/* Do nothing until we have proper bandwitdth calcs */
 }
 
-static void set_bandwidth(struct core_dc *dc)
+static void set_bandwidth(
+		struct core_dc *dc,
+		struct validate_context *context,
+		bool decrease_allowed)
 {
-	/* Do nothing until we have proper bandwitdth calcs */
+	dc->hwss.set_displaymarks(dc, context);
 }
 
 
@@ -132,7 +128,6 @@ bool dce100_hw_sequencer_construct(struct core_dc *dc)
 	/* TODO: dce80 is empty implementation at the moment*/
 	dc->hwss.enable_display_power_gating = dce100_enable_display_power_gating;
 	dc->hwss.set_displaymarks = set_displaymarks;
-	dc->hwss.increase_watermarks_for_pipe = set_display_mark_for_pipe_if_needed;
 	dc->hwss.set_bandwidth = set_bandwidth;
 
 	return true;
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 2d2daa694a30..d9dcb37a4f65 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1209,93 +1209,6 @@ static uint32_t compute_pstate_blackout_duration(
 	return total_dest_line_time_ns;
 }
 
-/* get the index of the pipe_ctx if there were no gaps in the pipe_ctx array*/
-int get_bw_result_idx(
-		struct resource_context *res_ctx,
-		int pipe_idx)
-{
-	int i, collapsed_idx;
-
-	if (res_ctx->pipe_ctx[pipe_idx].top_pipe)
-		return 3;
-
-	collapsed_idx = 0;
-	for (i = 0; i < pipe_idx; i++) {
-		if (res_ctx->pipe_ctx[i].stream)
-			collapsed_idx++;
-	}
-
-	return collapsed_idx;
-}
-
-static bool is_watermark_set_a_greater(
-		const struct bw_watermarks *set_a,
-		const struct bw_watermarks *set_b)
-{
-	if (set_a->a_mark > set_b->a_mark
-			|| set_a->b_mark > set_b->b_mark
-			|| set_a->c_mark > set_b->c_mark
-			|| set_a->d_mark > set_b->d_mark)
-		return true;
-	return false;
-}
-
-static bool did_watermarks_increase(
-		struct pipe_ctx *pipe_ctx,
-		struct validate_context *context,
-		struct validate_context *old_context)
-{
-	int collapsed_pipe_idx = get_bw_result_idx(&context->res_ctx,
-			pipe_ctx->pipe_idx);
-	int old_collapsed_pipe_idx = get_bw_result_idx(&old_context->res_ctx,
-			pipe_ctx->pipe_idx);
-	struct pipe_ctx *old_pipe_ctx =  &old_context->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
-
-	if (!old_pipe_ctx->stream)
-		return true;
-
-	if (is_watermark_set_a_greater(
-			&context->bw_results.nbp_state_change_wm_ns[collapsed_pipe_idx],
-			&old_context->bw_results.nbp_state_change_wm_ns[old_collapsed_pipe_idx]))
-		return true;
-	if (is_watermark_set_a_greater(
-			&context->bw_results.stutter_exit_wm_ns[collapsed_pipe_idx],
-			&old_context->bw_results.stutter_exit_wm_ns[old_collapsed_pipe_idx]))
-		return true;
-	if (is_watermark_set_a_greater(
-			&context->bw_results.urgent_wm_ns[collapsed_pipe_idx],
-			&old_context->bw_results.urgent_wm_ns[old_collapsed_pipe_idx]))
-		return true;
-
-	return false;
-}
-
-static void program_wm_for_pipe(struct core_dc *dc,
-		struct pipe_ctx *pipe_ctx,
-		struct validate_context *context)
-{
-	int total_dest_line_time_ns = compute_pstate_blackout_duration(
-			dc->bw_vbios.blackout_duration,
-			pipe_ctx->stream);
-	int bw_result_idx = get_bw_result_idx(&context->res_ctx,
-				pipe_ctx->pipe_idx);
-
-	pipe_ctx->mi->funcs->mem_input_program_display_marks(
-		pipe_ctx->mi,
-		context->bw_results.nbp_state_change_wm_ns[bw_result_idx],
-		context->bw_results.stutter_exit_wm_ns[bw_result_idx],
-		context->bw_results.urgent_wm_ns[bw_result_idx],
-		total_dest_line_time_ns);
-
-	if (pipe_ctx->top_pipe)
-		pipe_ctx->mi->funcs->mem_input_program_chroma_display_marks(
-				pipe_ctx->mi,
-				context->bw_results.nbp_state_change_wm_ns[bw_result_idx + 1],
-				context->bw_results.stutter_exit_wm_ns[bw_result_idx + 1],
-				context->bw_results.urgent_wm_ns[bw_result_idx + 1],
-				total_dest_line_time_ns);
-}
-
 void dce110_set_displaymarks(
 	const struct core_dc *dc,
 	struct validate_context *context)
@@ -1589,7 +1502,7 @@ static void reset_hw_ctx_wrap(
 	}
 }
 
-/*TODO: const validate_context*/
+
 enum dc_status dce110_apply_ctx_to_hw(
 		struct core_dc *dc,
 		struct validate_context *context)
@@ -1768,7 +1681,7 @@ enum dc_status dce110_apply_ctx_to_hw(
 			return status;
 	}
 
-	dc->hwss.set_displaymarks(dc, context);
+	dc->hwss.set_bandwidth(dc, context, true);
 
 	/* to save power */
 	apply_min_clocks(dc, context, &clocks_state, false);
@@ -1777,6 +1690,7 @@ enum dc_status dce110_apply_ctx_to_hw(
 
 	switch_dp_clock_sources(dc, &context->res_ctx);
 
+
 	return DC_OK;
 }
 
@@ -2135,7 +2049,6 @@ static void init_hw(struct core_dc *dc)
 	}
 }
 
-/* TODO: move this to apply_ctx_tohw some how?*/
 static void dce110_power_on_pipe_if_needed(
 		struct core_dc *dc,
 		struct pipe_ctx *pipe_ctx,
@@ -2180,31 +2093,175 @@ static void dce110_power_on_pipe_if_needed(
 	}
 }
 
-static void dce110_increase_watermarks_for_pipe(
-		struct core_dc *dc,
-		struct pipe_ctx *pipe_ctx,
-		struct validate_context *context)
+static void fill_display_configs(
+	const struct validate_context *context,
+	struct dm_pp_display_configuration *pp_display_cfg)
+{
+	int j;
+	int num_cfgs = 0;
+
+	for (j = 0; j < context->stream_count; j++) {
+		int k;
+
+		const struct core_stream *stream = context->streams[j];
+		struct dm_pp_single_disp_config *cfg =
+			&pp_display_cfg->disp_configs[num_cfgs];
+		const struct pipe_ctx *pipe_ctx = NULL;
+
+		for (k = 0; k < MAX_PIPES; k++)
+			if (stream == context->res_ctx.pipe_ctx[k].stream) {
+				pipe_ctx = &context->res_ctx.pipe_ctx[k];
+				break;
+			}
+
+		ASSERT(pipe_ctx != NULL);
+
+		num_cfgs++;
+		cfg->signal = pipe_ctx->stream->signal;
+		cfg->pipe_idx = pipe_ctx->pipe_idx;
+		cfg->src_height = stream->public.src.height;
+		cfg->src_width = stream->public.src.width;
+		cfg->ddi_channel_mapping =
+			stream->sink->link->ddi_channel_mapping.raw;
+		cfg->transmitter =
+			stream->sink->link->link_enc->transmitter;
+		cfg->link_settings.lane_count =
+			stream->sink->link->public.cur_link_settings.lane_count;
+		cfg->link_settings.link_rate =
+			stream->sink->link->public.cur_link_settings.link_rate;
+		cfg->link_settings.link_spread =
+			stream->sink->link->public.cur_link_settings.link_spread;
+		cfg->sym_clock = stream->phy_pix_clk;
+		/* Round v_refresh*/
+		cfg->v_refresh = stream->public.timing.pix_clk_khz * 1000;
+		cfg->v_refresh /= stream->public.timing.h_total;
+		cfg->v_refresh = (cfg->v_refresh + stream->public.timing.v_total / 2)
+							/ stream->public.timing.v_total;
+	}
+
+	pp_display_cfg->display_count = num_cfgs;
+}
+
+static uint32_t get_min_vblank_time_us(const struct validate_context *context)
 {
-	if (did_watermarks_increase(pipe_ctx, context, dc->current_context))
-		program_wm_for_pipe(dc, pipe_ctx, context);
+	uint8_t j;
+	uint32_t min_vertical_blank_time = -1;
+
+		for (j = 0; j < context->stream_count; j++) {
+			const struct dc_stream *stream = &context->streams[j]->public;
+			uint32_t vertical_blank_in_pixels = 0;
+			uint32_t vertical_blank_time = 0;
+
+			vertical_blank_in_pixels = stream->timing.h_total *
+				(stream->timing.v_total
+					- stream->timing.v_addressable);
+
+			vertical_blank_time = vertical_blank_in_pixels
+				* 1000 / stream->timing.pix_clk_khz;
+
+			if (min_vertical_blank_time > vertical_blank_time)
+				min_vertical_blank_time = vertical_blank_time;
+		}
+
+	return min_vertical_blank_time;
 }
 
-static void dce110_set_bandwidth(struct core_dc *dc)
+static int determine_sclk_from_bounding_box(
+		const struct core_dc *dc,
+		int required_sclk)
 {
 	int i;
 
-	for (i = 0; i < dc->current_context->res_ctx.pool->pipe_count; i++) {
-		struct pipe_ctx *pipe_ctx = &dc->current_context->res_ctx.pipe_ctx[i];
+	/*
+	 * Some asics do not give us sclk levels, so we just report the actual
+	 * required sclk
+	 */
+	if (dc->sclk_lvls.num_levels == 0)
+		return required_sclk;
 
-		if (!pipe_ctx->stream)
-			continue;
+	for (i = 0; i < dc->sclk_lvls.num_levels; i++) {
+		if (dc->sclk_lvls.clocks_in_khz[i] >= required_sclk)
+			return dc->sclk_lvls.clocks_in_khz[i];
+	}
+	/*
+	 * even maximum level could not satisfy requirement, this
+	 * is unexpected at this stage, should have been caught at
+	 * validation time
+	 */
+	ASSERT(0);
+	return dc->sclk_lvls.clocks_in_khz[dc->sclk_lvls.num_levels - 1];
+}
+
+static void pplib_apply_display_requirements(
+	struct core_dc *dc,
+	struct validate_context *context)
+{
+	struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
+
+	pp_display_cfg->all_displays_in_sync =
+		context->bw_results.all_displays_in_sync;
+	pp_display_cfg->nb_pstate_switch_disable =
+			context->bw_results.nbp_state_change_enable == false;
+	pp_display_cfg->cpu_cc6_disable =
+			context->bw_results.cpuc_state_change_enable == false;
+	pp_display_cfg->cpu_pstate_disable =
+			context->bw_results.cpup_state_change_enable == false;
+	pp_display_cfg->cpu_pstate_separation_time =
+			context->bw_results.blackout_recovery_time_us;
+
+	pp_display_cfg->min_memory_clock_khz = context->bw_results.required_yclk
+		/ MEMORY_TYPE_MULTIPLIER;
+
+	pp_display_cfg->min_engine_clock_khz = determine_sclk_from_bounding_box(
+			dc,
+			context->bw_results.required_sclk);
+
+	pp_display_cfg->min_engine_clock_deep_sleep_khz
+			= context->bw_results.required_sclk_deep_sleep;
+
+	pp_display_cfg->avail_mclk_switch_time_us =
+						get_min_vblank_time_us(context);
+	/* TODO: dce11.2*/
+	pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0;
 
-		program_wm_for_pipe(dc, pipe_ctx, dc->current_context);
+	pp_display_cfg->disp_clk_khz = context->dispclk_khz;
+
+	fill_display_configs(context, pp_display_cfg);
+
+	/* TODO: is this still applicable?*/
+	if (pp_display_cfg->display_count == 1) {
+		const struct dc_crtc_timing *timing =
+			&context->streams[0]->public.timing;
+
+		pp_display_cfg->crtc_index =
+			pp_display_cfg->disp_configs[0].pipe_idx;
+		pp_display_cfg->line_time_in_us = timing->h_total * 1000
+							/ timing->pix_clk_khz;
+	}
+
+	if (memcmp(&dc->prev_display_config, pp_display_cfg, sizeof(
+			struct dm_pp_display_configuration)) !=  0)
+		dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
+
+	dc->prev_display_config = *pp_display_cfg;
+}
+
+static void dce110_set_bandwidth(
+		struct core_dc *dc,
+		struct validate_context *context,
+		bool decrease_allowed)
+{
+	dc->hwss.set_displaymarks(dc, context);
+
+	if (decrease_allowed || context->dispclk_khz > dc->current_context->dispclk_khz) {
+		context->res_ctx.pool->display_clock->funcs->set_clock(
+				context->res_ctx.pool->display_clock,
+				context->dispclk_khz * 115 / 100);
+		dc->current_context->bw_results.dispclk_khz = context->dispclk_khz;
+		dc->current_context->dispclk_khz = context->dispclk_khz;
 	}
 
-	dc->current_context->res_ctx.pool->display_clock->funcs->set_clock(
-			dc->current_context->res_ctx.pool->display_clock,
-			dc->current_context->dispclk_khz * 115 / 100);
+	pplib_apply_display_requirements(dc, context);
 }
 
 static void dce110_program_front_end_for_pipe(
@@ -2335,15 +2392,6 @@ static void dce110_program_front_end_for_pipe(
 			pipe_ctx->scl_data.recout.y);
 }
 
-static void dce110_prepare_pipe_for_context(
-		struct core_dc *dc,
-		struct pipe_ctx *pipe_ctx,
-		struct validate_context *context)
-{
-	dce110_power_on_pipe_if_needed(dc, pipe_ctx, context);
-	dc->hwss.increase_watermarks_for_pipe(dc, pipe_ctx, context);
-}
-
 static void dce110_apply_ctx_for_surface(
 		struct core_dc *dc,
 		struct core_surface *surface,
@@ -2388,7 +2436,7 @@ static void dce110_power_down_fe(struct core_dc *dc, struct pipe_ctx *pipe)
 static const struct hw_sequencer_funcs dce110_funcs = {
 	.init_hw = init_hw,
 	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
-	.prepare_pipe_for_context = dce110_prepare_pipe_for_context,
+	.prepare_pipe_for_context = dce110_power_on_pipe_if_needed,
 	.apply_ctx_for_surface = dce110_apply_ctx_for_surface,
 	.set_plane_config = set_plane_config,
 	.update_plane_addr = update_plane_addr,
@@ -2407,7 +2455,6 @@ static const struct hw_sequencer_funcs dce110_funcs = {
 	.power_down_front_end = dce110_power_down_fe,
 	.pipe_control_lock = dce_pipe_control_lock,
 	.set_displaymarks = dce110_set_displaymarks,
-	.increase_watermarks_for_pipe = dce110_increase_watermarks_for_pipe,
 	.set_bandwidth = dce110_set_bandwidth,
 	.set_drr = set_drr,
 	.set_static_screen_control = set_static_screen_control,
diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c
index c7a2b768bcd1..85a54d963f8d 100644
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c
@@ -106,23 +106,18 @@ static bool dce80_enable_display_power_gating(
 		return false;
 }
 
-
-static void set_display_mark_for_pipe_if_needed(struct core_dc *dc,
-		struct pipe_ctx *pipe_ctx,
-		struct validate_context *context)
-{
-	/* Do nothing until we have proper bandwitdth calcs */
-}
-
 static void set_displaymarks(
 		const struct core_dc *dc, struct validate_context *context)
 {
 	/* Do nothing until we have proper bandwitdth calcs */
 }
 
-static void set_bandwidth(struct core_dc *dc)
+static void set_bandwidth(
+		struct core_dc *dc,
+		struct validate_context *context,
+		bool decrease_allowed)
 {
-	/* Do nothing until we have proper bandwitdth calcs */
+	dc->hwss.set_displaymarks(dc, context);
 }
 
 
@@ -133,7 +128,6 @@ bool dce80_hw_sequencer_construct(struct core_dc *dc)
 	dc->hwss.enable_display_power_gating = dce80_enable_display_power_gating;
 	dc->hwss.pipe_control_lock = dce_pipe_control_lock;
 	dc->hwss.set_displaymarks = set_displaymarks;
-	dc->hwss.increase_watermarks_for_pipe = set_display_mark_for_pipe_if_needed;
 	dc->hwss.set_bandwidth = set_bandwidth;
 
 	return true;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 758a568589bb..7b780c610631 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -124,11 +124,10 @@ struct hw_sequencer_funcs {
 				const struct core_dc *dc,
 				struct validate_context *context);
 
-	void (*increase_watermarks_for_pipe)(struct core_dc *dc,
-			struct pipe_ctx *pipe_ctx,
-			struct validate_context *context);
-
-	void (*set_bandwidth)(struct core_dc *dc);
+	void (*set_bandwidth)(
+			struct core_dc *dc,
+			struct validate_context *context,
+			bool decrease_allowed);
 
 	void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes,
 			int vmin, int vmax);
-- 
2.9.3

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[PATCH 12/15] drm/amd/display: move visual confirm recout adjustment to scaler

[Harry Wentland]

From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>

Change-Id: Ia758a65b08a5bf4cc8d5f95170b682e615052f54
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c                   | 9 ---------
 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c         | 6 ++++++
 drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c | 6 ++++++
 3 files changed, 12 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 0ec2c4f39735..852932aec436 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -980,11 +980,6 @@ bool dc_pre_update_surfaces_to_stream(
 
 			resource_build_scaling_params(
 				new_surfaces[i], &context->res_ctx.pipe_ctx[j]);
-
-			if (dc->debug.surface_visual_confirm) {
-				context->res_ctx.pipe_ctx[j].scl_data.recout.height -= 2;
-				context->res_ctx.pipe_ctx[j].scl_data.recout.width -= 2;
-			}
 		}
 
 	if (!core_dc->res_pool->funcs->validate_bandwidth(core_dc, context)) {
@@ -1267,10 +1262,6 @@ void dc_update_surfaces_for_stream(struct dc *dc,
 					continue;
 
 				resource_build_scaling_params(updates[i].surface, pipe_ctx);
-				if (dc->debug.surface_visual_confirm) {
-					pipe_ctx->scl_data.recout.height -= 2;
-					pipe_ctx->scl_data.recout.width -= 2;
-				}
 			}
 		}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
index d8ffbff9a268..c861fd7b5767 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
@@ -27,6 +27,7 @@
 #include "reg_helper.h"
 #include "opp.h"
 #include "basics/conversion.h"
+#include "dc.h"
 
 #define REG(reg) \
 	(xfm_dce->regs->reg)
@@ -121,6 +122,11 @@ static void program_overscan(
 	int overscan_bottom = data->v_active
 			- data->recout.y - data->recout.height;
 
+	if (xfm_dce->base.ctx->dc->debug.surface_visual_confirm) {
+		overscan_bottom += 2;
+		overscan_right += 2;
+	}
+
 	if (overscan_right < 0) {
 		BREAK_TO_DEBUGGER();
 		overscan_right = 0;
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c
index feb5f3c29804..28963996693c 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c
@@ -25,6 +25,7 @@
 
 #include "dce110_transform_v.h"
 #include "dm_services.h"
+#include "dc.h"
 #include "dce/dce_11_0_d.h"
 #include "dce/dce_11_0_sh_mask.h"
 
@@ -232,6 +233,11 @@ static void program_overscan(
 	int overscan_right = data->h_active - data->recout.x - data->recout.width;
 	int overscan_bottom = data->v_active - data->recout.y - data->recout.height;
 
+	if (xfm_dce->base.ctx->dc->debug.surface_visual_confirm) {
+		overscan_bottom += 2;
+		overscan_right += 2;
+	}
+
 	if (overscan_right < 0) {
 		BREAK_TO_DEBUGGER();
 		overscan_right = 0;
-- 
2.9.3

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[PATCH 13/15] drm/amd/display: Some more warning fixes

[Harry Wentland]

This doesn't show with gcc6

Change-Id: I16ba47cd5ec2034baba510ebd68a5c5871ec5b57
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c    | 2 +-
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +-
 drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c  | 6 +++---
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 8eb6b342a49d..d275fc88f71e 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -928,7 +928,7 @@ static bool construct(
 {
 	uint8_t i;
 	struct gpio *hpd_gpio = NULL;
-	struct ddc_service_init_data ddc_service_init_data = { 0 };
+	struct ddc_service_init_data ddc_service_init_data = { { 0 } };
 	struct dc_context *dc_ctx = init_params->ctx;
 	struct encoder_init_data enc_init_data = { 0 };
 	struct integrated_info info = {{{ 0 }}};
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 96d69b4d2d17..c250d8f6d011 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -1762,7 +1762,7 @@ bool dc_link_handle_hpd_rx_irq(const struct dc_link *dc_link)
 {
 	struct core_link *link = DC_LINK_TO_LINK(dc_link);
 	union hpd_irq_data hpd_irq_dpcd_data = {{{{0}}}};
-	union device_service_irq device_service_clear = {0};
+	union device_service_irq device_service_clear = { { 0 } };
 	enum dc_status result = DDC_RESULT_UNKNOWN;
 	bool status = false;
 	/* For use cases related to down stream connection status change,
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
index dd922bdcc145..3e3eefea3e82 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
@@ -393,8 +393,8 @@ static void dce_clock_read_integrated_info(struct dce_disp_clk *clk_dce)
 {
 	struct dc_debug *debug = &clk_dce->base.ctx->dc->debug;
 	struct dc_bios *bp = clk_dce->base.ctx->dc_bios;
-	struct integrated_info info = { 0 };
-	struct firmware_info fw_info = { 0 };
+	struct integrated_info info = { { { 0 } } };
+	struct firmware_info fw_info = { { 0 } };
 	int i;
 
 	if (bp->integrated_info)
@@ -456,7 +456,7 @@ static void dce_clock_read_ss_info(struct dce_disp_clk *clk_dce)
 			bp, AS_SIGNAL_TYPE_GPU_PLL);
 
 	if (ss_info_num) {
-		struct spread_spectrum_info info = { 0 };
+		struct spread_spectrum_info info = { { 0 } };
 		enum bp_result result = bp->funcs->get_spread_spectrum_info(
 				bp, AS_SIGNAL_TYPE_GPU_PLL, 0, &info);
 
-- 
2.9.3

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[PATCH 14/15] drm/amd/display: Enable warnings as errors

[Harry Wentland]

Change-Id: I48d38e4d0224c9f0e52055b3c4ddef8e872b3dac
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Jordan Lazare <Jordan.Lazare@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
 drivers/gpu/drm/amd/display/Makefile | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/Makefile b/drivers/gpu/drm/amd/display/Makefile
index 8ba37dd9cf7f..c22475b55586 100644
--- a/drivers/gpu/drm/amd/display/Makefile
+++ b/drivers/gpu/drm/amd/display/Makefile
@@ -5,6 +5,8 @@
 
 AMDDALPATH = $(RELATIVE_AMD_DISPLAY_PATH)
 
+subdir-ccflags-y += -Werror
+
 subdir-ccflags-y += -I$(AMDDALPATH)/ -I$(AMDDALPATH)/include
 
 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/inc/
-- 
2.9.3

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Re: [PATCH 14/15] drm/amd/display: Enable warnings as errors

[Michel Dänzer]

On 01/03/17 09:26 AM, Harry Wentland wrote:
> Change-Id: I48d38e4d0224c9f0e52055b3c4ddef8e872b3dac
> Signed-off-by: Harry Wentland <harry.wentland@amd.com>
> Acked-by: Harry Wentland <Harry.Wentland@amd.com>
> Reviewed-by: Jordan Lazare <Jordan.Lazare@amd.com>
> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
> ---
>  drivers/gpu/drm/amd/display/Makefile | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/display/Makefile b/drivers/gpu/drm/amd/display/Makefile
> index 8ba37dd9cf7f..c22475b55586 100644
> --- a/drivers/gpu/drm/amd/display/Makefile
> +++ b/drivers/gpu/drm/amd/display/Makefile
> @@ -5,6 +5,8 @@
>  
>  AMDDALPATH = $(RELATIVE_AMD_DISPLAY_PATH)
>  
> +subdir-ccflags-y += -Werror

Please don't. This will result in compile failures for people with
different compiler versions, including your future selves.


-- 
Earthling Michel Dänzer               |               http://www.amd.com
Libre software enthusiast             |             Mesa and X developer
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Re: [PATCH 14/15] drm/amd/display: Enable warnings as errors

[Emil Velikov]

Hi Harry,

On 1 March 2017 at 00:26, Harry Wentland <harry.wentland@amd.com> wrote:
> Change-Id: I48d38e4d0224c9f0e52055b3c4ddef8e872b3dac
> Signed-off-by: Harry Wentland <harry.wentland@amd.com>
> Acked-by: Harry Wentland <Harry.Wentland@amd.com>
> Reviewed-by: Jordan Lazare <Jordan.Lazare@amd.com>
> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
> ---
>  drivers/gpu/drm/amd/display/Makefile | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/display/Makefile b/drivers/gpu/drm/amd/display/Makefile
> index 8ba37dd9cf7f..c22475b55586 100644
> --- a/drivers/gpu/drm/amd/display/Makefile
> +++ b/drivers/gpu/drm/amd/display/Makefile
> @@ -5,6 +5,8 @@
>
>  AMDDALPATH = $(RELATIVE_AMD_DISPLAY_PATH)
>
> +subdir-ccflags-y += -Werror
> +
Many kernel modules have tried this in the past and had to quickly
revert it. There's far too many compiler/toolchain combinations for
this to always be true.

By adding this you'll be adding serious annoyance to users and extra
burden on Alex.

-Emil
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Re: [PATCH 14/15] drm/amd/display: Enable warnings as errors

[Harry Wentland]

On 2017-02-28 08:20 PM, Emil Velikov wrote:
> Hi Harry,
>
> On 1 March 2017 at 00:26, Harry Wentland <harry.wentland@amd.com> wrote:
>> Change-Id: I48d38e4d0224c9f0e52055b3c4ddef8e872b3dac
>> Signed-off-by: Harry Wentland <harry.wentland@amd.com>
>> Acked-by: Harry Wentland <Harry.Wentland@amd.com>
>> Reviewed-by: Jordan Lazare <Jordan.Lazare@amd.com>
>> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
>> ---
>>  drivers/gpu/drm/amd/display/Makefile | 2 ++
>>  1 file changed, 2 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/display/Makefile b/drivers/gpu/drm/amd/display/Makefile
>> index 8ba37dd9cf7f..c22475b55586 100644
>> --- a/drivers/gpu/drm/amd/display/Makefile
>> +++ b/drivers/gpu/drm/amd/display/Makefile
>> @@ -5,6 +5,8 @@
>>
>>  AMDDALPATH = $(RELATIVE_AMD_DISPLAY_PATH)
>>
>> +subdir-ccflags-y += -Werror
>> +
> Many kernel modules have tried this in the past and had to quickly
> revert it. There's far too many compiler/toolchain combinations for
> this to always be true.
>
> By adding this you'll be adding serious annoyance to users and extra
> burden on Alex.
>
> -Emil
>

Point taken. I probably shouldn't have sent this one. This is something 
we're doing in our internal trees to make sure we catch warnings at 
pre-submission stage. Please ignore warnings too frequently and I'm 
getting tired of fixing all of them.

Would be nice if there was some consistency to gcc's warnings, but 
that's not something I see happening ever.

Harry
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[PATCH 15/15] drm/amd/display: fix dce100_validate_bandwidth return value

[Harry Wentland]

From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>

Change-Id: I5dee433d86018bd921f5c2c2a986ff9642f1139c
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
index fc85efafb104..c72858a1452f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
@@ -772,7 +772,7 @@ bool dce100_validate_bandwidth(
 	/* TODO implement when needed but for now hardcode max value*/
 	context->dispclk_khz = 681000;
 
-	return false;
+	return true;
 }
 
 static bool dce100_validate_surface_sets(
-- 
2.9.3

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