* [RESEND PATCH v7 0/7] Rockchip dw-mipi-dsi driver
@ 2017-02-20 8:02 ` Chris Zhong
0 siblings, 0 replies; 51+ messages in thread
From: Chris Zhong @ 2017-02-20 8:02 UTC (permalink / raw)
To: john, dianders, tfiga, heiko, yzq, mark.rutland, devicetree,
robh+dt, galak, pawel.moll, seanpaul
Cc: linux-rockchip, Chris Zhong, Mark Yao, linux-kernel, dri-devel,
David Airlie, linux-arm-kernel
Hi all
[Resend this v7 version series, since there are 5 mails have gone missing, last
week]
This version does not change the existing v6 patches, just to add the
"bandwidth fix" patch back, since we really need it.
This patch serial is for RK3399 MIPI DSI. The MIPI DSI controller of
RK3399 is almost the same as RK3288, except a little bit of difference
in phy clock controlling and port id selection register. These patches
add RK3399 support and the power domain support.
And these patches base on John Keeping's v3 patches[0], it fixes many bugs,
they have been tested on rk3288 evb board.
[0]:
[01/24] https://patchwork.kernel.org/patch/9544089
[02/24] https://patchwork.kernel.org/patch/9544061
[03/24] https://patchwork.kernel.org/patch/9544065
[04/24] https://patchwork.kernel.org/patch/9544077
[05/24] https://patchwork.kernel.org/patch/9544033
[06/24] https://patchwork.kernel.org/patch/9544037
[07/24] https://patchwork.kernel.org/patch/9544029
[08/24] https://patchwork.kernel.org/patch/9544031
[09/24] https://patchwork.kernel.org/patch/9544083
[10/24] https://patchwork.kernel.org/patch/9544063
[11/24] https://patchwork.kernel.org/patch/9544085
[12/24] https://patchwork.kernel.org/patch/9544093
[13/24] https://patchwork.kernel.org/patch/9544081
[14/24] https://patchwork.kernel.org/patch/9544057
[15/24] https://patchwork.kernel.org/patch/9544079
[16/24] https://patchwork.kernel.org/patch/9544035
[17/24] https://patchwork.kernel.org/patch/9544105
[18/24] https://patchwork.kernel.org/patch/9544059
[21/24] https://patchwork.kernel.org/patch/9544009
[22/24] https://patchwork.kernel.org/patch/9544049
[23/24] https://patchwork.kernel.org/patch/9544055
[24/24] https://patchwork.kernel.org/patch/9544109
Changes in v6:
- no need check phy_cfg_clk before enable/disable
Changes in v5:
- check the error of phy_cfg_clk in dw_mipi_dsi_bind
Changes in v4:
- remove the unrelated change
Changes in v3:
- base on John Keeping's patch series
Chris Zhong (7):
dt-bindings: add rk3399 support for dw-mipi-rockchip
drm/rockchip/dsi: dw-mipi: support RK3399 mipi dsi
drm/rockchip/dsi: dw-mipi: correct the coding style
drm/rockchip/dsi: remove mode_valid function
dt-bindings: add power domain node for dw-mipi-rockchip
drm/rockchip/dsi: fix insufficient bandwidth of some panel
drm/rockchip/dsi: add dw-mipi power domain support
.../display/rockchip/dw_mipi_dsi_rockchip.txt | 7 +-
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 160 ++++++++++++---------
2 files changed, 100 insertions(+), 67 deletions(-)
--
2.6.3
^ permalink raw reply [flat|nested] 51+ messages in thread
* [RESEND PATCH v7 0/7] Rockchip dw-mipi-dsi driver
@ 2017-02-20 8:02 ` Chris Zhong
0 siblings, 0 replies; 51+ messages in thread
From: Chris Zhong @ 2017-02-20 8:02 UTC (permalink / raw)
To: john-HooS5bfzL4hWk0Htik3J/w, dianders-F7+t8E8rja9g9hUCZPvPmw,
tfiga-F7+t8E8rja9g9hUCZPvPmw, heiko-4mtYJXux2i+zQB+pC5nmwQ,
yzq-TNX95d0MmH7DzftRWevZcw, mark.rutland-5wv7dgnIgG8,
devicetree-u79uwXL29TY76Z2rM5mHXA,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, galak-sgV2jX0FEOL9JmXXK+q4OQ,
pawel.moll-5wv7dgnIgG8, seanpaul-F7+t8E8rja9g9hUCZPvPmw
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Chris Zhong,
Mark Yao, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, David Airlie,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Hi all
[Resend this v7 version series, since there are 5 mails have gone missing, last
week]
This version does not change the existing v6 patches, just to add the
"bandwidth fix" patch back, since we really need it.
This patch serial is for RK3399 MIPI DSI. The MIPI DSI controller of
RK3399 is almost the same as RK3288, except a little bit of difference
in phy clock controlling and port id selection register. These patches
add RK3399 support and the power domain support.
And these patches base on John Keeping's v3 patches[0], it fixes many bugs,
they have been tested on rk3288 evb board.
[0]:
[01/24] https://patchwork.kernel.org/patch/9544089
[02/24] https://patchwork.kernel.org/patch/9544061
[03/24] https://patchwork.kernel.org/patch/9544065
[04/24] https://patchwork.kernel.org/patch/9544077
[05/24] https://patchwork.kernel.org/patch/9544033
[06/24] https://patchwork.kernel.org/patch/9544037
[07/24] https://patchwork.kernel.org/patch/9544029
[08/24] https://patchwork.kernel.org/patch/9544031
[09/24] https://patchwork.kernel.org/patch/9544083
[10/24] https://patchwork.kernel.org/patch/9544063
[11/24] https://patchwork.kernel.org/patch/9544085
[12/24] https://patchwork.kernel.org/patch/9544093
[13/24] https://patchwork.kernel.org/patch/9544081
[14/24] https://patchwork.kernel.org/patch/9544057
[15/24] https://patchwork.kernel.org/patch/9544079
[16/24] https://patchwork.kernel.org/patch/9544035
[17/24] https://patchwork.kernel.org/patch/9544105
[18/24] https://patchwork.kernel.org/patch/9544059
[21/24] https://patchwork.kernel.org/patch/9544009
[22/24] https://patchwork.kernel.org/patch/9544049
[23/24] https://patchwork.kernel.org/patch/9544055
[24/24] https://patchwork.kernel.org/patch/9544109
Changes in v6:
- no need check phy_cfg_clk before enable/disable
Changes in v5:
- check the error of phy_cfg_clk in dw_mipi_dsi_bind
Changes in v4:
- remove the unrelated change
Changes in v3:
- base on John Keeping's patch series
Chris Zhong (7):
dt-bindings: add rk3399 support for dw-mipi-rockchip
drm/rockchip/dsi: dw-mipi: support RK3399 mipi dsi
drm/rockchip/dsi: dw-mipi: correct the coding style
drm/rockchip/dsi: remove mode_valid function
dt-bindings: add power domain node for dw-mipi-rockchip
drm/rockchip/dsi: fix insufficient bandwidth of some panel
drm/rockchip/dsi: add dw-mipi power domain support
.../display/rockchip/dw_mipi_dsi_rockchip.txt | 7 +-
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 160 ++++++++++++---------
2 files changed, 100 insertions(+), 67 deletions(-)
--
2.6.3
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 51+ messages in thread
* [RESEND PATCH v7 0/7] Rockchip dw-mipi-dsi driver
@ 2017-02-20 8:02 ` Chris Zhong
0 siblings, 0 replies; 51+ messages in thread
From: Chris Zhong @ 2017-02-20 8:02 UTC (permalink / raw)
To: linux-arm-kernel
Hi all
[Resend this v7 version series, since there are 5 mails have gone missing, last
week]
This version does not change the existing v6 patches, just to add the
"bandwidth fix" patch back, since we really need it.
This patch serial is for RK3399 MIPI DSI. The MIPI DSI controller of
RK3399 is almost the same as RK3288, except a little bit of difference
in phy clock controlling and port id selection register. These patches
add RK3399 support and the power domain support.
And these patches base on John Keeping's v3 patches[0], it fixes many bugs,
they have been tested on rk3288 evb board.
[0]:
[01/24] https://patchwork.kernel.org/patch/9544089
[02/24] https://patchwork.kernel.org/patch/9544061
[03/24] https://patchwork.kernel.org/patch/9544065
[04/24] https://patchwork.kernel.org/patch/9544077
[05/24] https://patchwork.kernel.org/patch/9544033
[06/24] https://patchwork.kernel.org/patch/9544037
[07/24] https://patchwork.kernel.org/patch/9544029
[08/24] https://patchwork.kernel.org/patch/9544031
[09/24] https://patchwork.kernel.org/patch/9544083
[10/24] https://patchwork.kernel.org/patch/9544063
[11/24] https://patchwork.kernel.org/patch/9544085
[12/24] https://patchwork.kernel.org/patch/9544093
[13/24] https://patchwork.kernel.org/patch/9544081
[14/24] https://patchwork.kernel.org/patch/9544057
[15/24] https://patchwork.kernel.org/patch/9544079
[16/24] https://patchwork.kernel.org/patch/9544035
[17/24] https://patchwork.kernel.org/patch/9544105
[18/24] https://patchwork.kernel.org/patch/9544059
[21/24] https://patchwork.kernel.org/patch/9544009
[22/24] https://patchwork.kernel.org/patch/9544049
[23/24] https://patchwork.kernel.org/patch/9544055
[24/24] https://patchwork.kernel.org/patch/9544109
Changes in v6:
- no need check phy_cfg_clk before enable/disable
Changes in v5:
- check the error of phy_cfg_clk in dw_mipi_dsi_bind
Changes in v4:
- remove the unrelated change
Changes in v3:
- base on John Keeping's patch series
Chris Zhong (7):
dt-bindings: add rk3399 support for dw-mipi-rockchip
drm/rockchip/dsi: dw-mipi: support RK3399 mipi dsi
drm/rockchip/dsi: dw-mipi: correct the coding style
drm/rockchip/dsi: remove mode_valid function
dt-bindings: add power domain node for dw-mipi-rockchip
drm/rockchip/dsi: fix insufficient bandwidth of some panel
drm/rockchip/dsi: add dw-mipi power domain support
.../display/rockchip/dw_mipi_dsi_rockchip.txt | 7 +-
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 160 ++++++++++++---------
2 files changed, 100 insertions(+), 67 deletions(-)
--
2.6.3
^ permalink raw reply [flat|nested] 51+ messages in thread
* [RESEND PATCH v7 1/7] dt-bindings: add rk3399 support for dw-mipi-rockchip
2017-02-20 8:02 ` Chris Zhong
(?)
@ 2017-02-20 8:02 ` Chris Zhong
-1 siblings, 0 replies; 51+ messages in thread
From: Chris Zhong @ 2017-02-20 8:02 UTC (permalink / raw)
To: john, dianders, tfiga, heiko, yzq, mark.rutland, devicetree,
robh+dt, galak, pawel.moll, seanpaul
Cc: linux-rockchip, Chris Zhong, Mark Yao, David Airlie, dri-devel,
linux-arm-kernel, linux-kernel
The dw-mipi-dsi of rk3399 is almost the same as rk3288, the rk3399 has
additional phy config clock.
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
.../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
index 1753f0c..0f82568 100644
--- a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
+++ b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
@@ -5,10 +5,12 @@ Required properties:
- #address-cells: Should be <1>.
- #size-cells: Should be <0>.
- compatible: "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi".
+ "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi".
- reg: Represent the physical address range of the controller.
- interrupts: Represent the controller's interrupt to the CPU(s).
- clocks, clock-names: Phandles to the controller's pll reference
- clock(ref) and APB clock(pclk), as described in [1].
+ clock(ref) and APB clock(pclk). For RK3399, a phy config clock
+ (phy_cfg) is additional required. As described in [1].
- rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
- ports: contain a port node with endpoint definitions as defined in [2].
For vopb,set the reg = <0> and set the reg = <1> for vopl.
--
2.6.3
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [RESEND PATCH v7 1/7] dt-bindings: add rk3399 support for dw-mipi-rockchip
@ 2017-02-20 8:02 ` Chris Zhong
0 siblings, 0 replies; 51+ messages in thread
From: Chris Zhong @ 2017-02-20 8:02 UTC (permalink / raw)
To: john, dianders, tfiga, heiko, yzq, mark.rutland, devicetree,
robh+dt, galak, pawel.moll, seanpaul
Cc: linux-kernel, dri-devel, linux-rockchip, Chris Zhong, linux-arm-kernel
The dw-mipi-dsi of rk3399 is almost the same as rk3288, the rk3399 has
additional phy config clock.
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
.../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
index 1753f0c..0f82568 100644
--- a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
+++ b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
@@ -5,10 +5,12 @@ Required properties:
- #address-cells: Should be <1>.
- #size-cells: Should be <0>.
- compatible: "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi".
+ "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi".
- reg: Represent the physical address range of the controller.
- interrupts: Represent the controller's interrupt to the CPU(s).
- clocks, clock-names: Phandles to the controller's pll reference
- clock(ref) and APB clock(pclk), as described in [1].
+ clock(ref) and APB clock(pclk). For RK3399, a phy config clock
+ (phy_cfg) is additional required. As described in [1].
- rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
- ports: contain a port node with endpoint definitions as defined in [2].
For vopb,set the reg = <0> and set the reg = <1> for vopl.
--
2.6.3
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [RESEND PATCH v7 1/7] dt-bindings: add rk3399 support for dw-mipi-rockchip
@ 2017-02-20 8:02 ` Chris Zhong
0 siblings, 0 replies; 51+ messages in thread
From: Chris Zhong @ 2017-02-20 8:02 UTC (permalink / raw)
To: linux-arm-kernel
The dw-mipi-dsi of rk3399 is almost the same as rk3288, the rk3399 has
additional phy config clock.
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
.../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
index 1753f0c..0f82568 100644
--- a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
+++ b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
@@ -5,10 +5,12 @@ Required properties:
- #address-cells: Should be <1>.
- #size-cells: Should be <0>.
- compatible: "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi".
+ "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi".
- reg: Represent the physical address range of the controller.
- interrupts: Represent the controller's interrupt to the CPU(s).
- clocks, clock-names: Phandles to the controller's pll reference
- clock(ref) and APB clock(pclk), as described in [1].
+ clock(ref) and APB clock(pclk). For RK3399, a phy config clock
+ (phy_cfg) is additional required. As described in [1].
- rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
- ports: contain a port node with endpoint definitions as defined in [2].
For vopb,set the reg = <0> and set the reg = <1> for vopl.
--
2.6.3
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [RESEND PATCH v7 2/7] drm/rockchip/dsi: dw-mipi: support RK3399 mipi dsi
2017-02-20 8:02 ` Chris Zhong
(?)
@ 2017-02-20 8:02 ` Chris Zhong
-1 siblings, 0 replies; 51+ messages in thread
From: Chris Zhong @ 2017-02-20 8:02 UTC (permalink / raw)
To: john, dianders, tfiga, heiko, yzq, mark.rutland, devicetree,
robh+dt, galak, pawel.moll, seanpaul
Cc: linux-rockchip, Chris Zhong, Mark Yao, David Airlie, dri-devel,
linux-arm-kernel, linux-kernel
The vopb/vopl switch register of RK3399 mipi is different from RK3288,
the default setting for mipi dsi mode is different too, so add a
of_device_id structure to distinguish them, and make sure set the
correct mode before mipi phy init.
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
---
Changes in v6:
- no need check phy_cfg_clk before enable/disable
Changes in v5:
- check the error of phy_cfg_clk in dw_mipi_dsi_bind
Changes in v4:
- remove the unrelated change
Changes in v3:
- base on John Keeping's patch series
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 72 +++++++++++++++++++++++++++++-----
1 file changed, 62 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index cc58ada..4e74681 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -29,9 +29,17 @@
#define DRIVER_NAME "dw-mipi-dsi"
-#define GRF_SOC_CON6 0x025c
-#define DSI0_SEL_VOP_LIT (1 << 6)
-#define DSI1_SEL_VOP_LIT (1 << 9)
+#define RK3288_GRF_SOC_CON6 0x025c
+#define RK3288_DSI0_SEL_VOP_LIT BIT(6)
+#define RK3288_DSI1_SEL_VOP_LIT BIT(9)
+
+#define RK3399_GRF_SOC_CON19 0x6250
+#define RK3399_DSI0_SEL_VOP_LIT BIT(0)
+#define RK3399_DSI1_SEL_VOP_LIT BIT(4)
+
+/* disable turnrequest, turndisable, forcetxstopmode, forcerxmode */
+#define RK3399_GRF_SOC_CON22 0x6258
+#define RK3399_GRF_DSI_MODE 0xffff0000
#define DSI_VERSION 0x00
#define DSI_PWR_UP 0x04
@@ -265,6 +273,11 @@ enum {
};
struct dw_mipi_dsi_plat_data {
+ u32 dsi0_en_bit;
+ u32 dsi1_en_bit;
+ u32 grf_switch_reg;
+ u32 grf_dsi0_mode;
+ u32 grf_dsi0_mode_reg;
unsigned int max_data_lanes;
enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
struct drm_display_mode *mode);
@@ -281,6 +294,7 @@ struct dw_mipi_dsi {
struct clk *pllref_clk;
struct clk *pclk;
+ struct clk *phy_cfg_clk;
unsigned int lane_mbps; /* per lane */
u32 channel;
@@ -425,6 +439,12 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR);
dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
+ ret = clk_prepare_enable(dsi->phy_cfg_clk);
+ if (ret) {
+ dev_err(dsi->dev, "Failed to enable phy_cfg_clk\n");
+ return ret;
+ }
+
dw_mipi_dsi_phy_write(dsi, 0x10, BYPASS_VCO_RANGE |
VCO_RANGE_CON_SEL(vco) |
VCO_IN_CAP_CON_LOW |
@@ -481,17 +501,18 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
val, val & LOCK, 1000, PHY_STATUS_TIMEOUT_US);
if (ret < 0) {
dev_err(dsi->dev, "failed to wait for phy lock state\n");
- return ret;
+ goto phy_init_end;
}
ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
val, val & STOP_STATE_CLK_LANE, 1000,
PHY_STATUS_TIMEOUT_US);
- if (ret < 0) {
+ if (ret < 0)
dev_err(dsi->dev,
"failed to wait for phy clk lane stop state\n");
- return ret;
- }
+
+phy_init_end:
+ clk_disable_unprepare(dsi->phy_cfg_clk);
return ret;
}
@@ -960,6 +981,7 @@ static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
{
struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
+ const struct dw_mipi_dsi_plat_data *pdata = dsi->pdata;
int mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, encoder);
u32 val;
int ret;
@@ -985,6 +1007,10 @@ static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
dw_mipi_dsi_dphy_interface_config(dsi);
dw_mipi_dsi_clear_err(dsi);
+ if (pdata->grf_dsi0_mode_reg)
+ regmap_write(dsi->grf_regmap, pdata->grf_dsi0_mode_reg,
+ pdata->grf_dsi0_mode);
+
dw_mipi_dsi_phy_init(dsi);
dw_mipi_dsi_wait_for_two_frames(mode);
@@ -998,11 +1024,11 @@ static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
clk_disable_unprepare(dsi->pclk);
if (mux)
- val = DSI0_SEL_VOP_LIT | (DSI0_SEL_VOP_LIT << 16);
+ val = pdata->dsi0_en_bit | (pdata->dsi0_en_bit << 16);
else
- val = DSI0_SEL_VOP_LIT << 16;
+ val = pdata->dsi0_en_bit << 16;
- regmap_write(dsi->grf_regmap, GRF_SOC_CON6, val);
+ regmap_write(dsi->grf_regmap, pdata->grf_switch_reg, val);
dev_dbg(dsi->dev, "vop %s output to dsi0\n", (mux) ? "LIT" : "BIG");
}
@@ -1161,14 +1187,29 @@ static enum drm_mode_status rk3288_mipi_dsi_mode_valid(
}
static struct dw_mipi_dsi_plat_data rk3288_mipi_dsi_drv_data = {
+ .dsi0_en_bit = RK3288_DSI0_SEL_VOP_LIT,
+ .dsi1_en_bit = RK3288_DSI1_SEL_VOP_LIT,
+ .grf_switch_reg = RK3288_GRF_SOC_CON6,
.max_data_lanes = 4,
.mode_valid = rk3288_mipi_dsi_mode_valid,
};
+static struct dw_mipi_dsi_plat_data rk3399_mipi_dsi_drv_data = {
+ .dsi0_en_bit = RK3399_DSI0_SEL_VOP_LIT,
+ .dsi1_en_bit = RK3399_DSI1_SEL_VOP_LIT,
+ .grf_switch_reg = RK3399_GRF_SOC_CON19,
+ .grf_dsi0_mode = RK3399_GRF_DSI_MODE,
+ .grf_dsi0_mode_reg = RK3399_GRF_SOC_CON22,
+ .max_data_lanes = 4,
+};
+
static const struct of_device_id dw_mipi_dsi_dt_ids[] = {
{
.compatible = "rockchip,rk3288-mipi-dsi",
.data = &rk3288_mipi_dsi_drv_data,
+ }, {
+ .compatible = "rockchip,rk3399-mipi-dsi",
+ .data = &rk3399_mipi_dsi_drv_data,
},
{ /* sentinel */ }
};
@@ -1248,6 +1289,17 @@ static int dw_mipi_dsi_bind(struct device *dev, struct device *master,
clk_disable_unprepare(dsi->pclk);
}
+ dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg");
+ if (IS_ERR(dsi->phy_cfg_clk)) {
+ ret = PTR_ERR(dsi->phy_cfg_clk);
+ if (ret != -ENOENT) {
+ dev_err(dev, "Unable to get phy_cfg_clk: %d\n", ret);
+ return ret;
+ }
+ dsi->phy_cfg_clk = NULL;
+ dev_dbg(dev, "have not phy_cfg_clk\n");
+ }
+
ret = clk_prepare_enable(dsi->pllref_clk);
if (ret) {
dev_err(dev, "%s: Failed to enable pllref_clk\n", __func__);
--
2.6.3
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [RESEND PATCH v7 2/7] drm/rockchip/dsi: dw-mipi: support RK3399 mipi dsi
@ 2017-02-20 8:02 ` Chris Zhong
0 siblings, 0 replies; 51+ messages in thread
From: Chris Zhong @ 2017-02-20 8:02 UTC (permalink / raw)
To: john, dianders, tfiga, heiko, yzq, mark.rutland, devicetree,
robh+dt, galak, pawel.moll, seanpaul
Cc: linux-kernel, dri-devel, linux-rockchip, Chris Zhong, linux-arm-kernel
The vopb/vopl switch register of RK3399 mipi is different from RK3288,
the default setting for mipi dsi mode is different too, so add a
of_device_id structure to distinguish them, and make sure set the
correct mode before mipi phy init.
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
---
Changes in v6:
- no need check phy_cfg_clk before enable/disable
Changes in v5:
- check the error of phy_cfg_clk in dw_mipi_dsi_bind
Changes in v4:
- remove the unrelated change
Changes in v3:
- base on John Keeping's patch series
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 72 +++++++++++++++++++++++++++++-----
1 file changed, 62 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index cc58ada..4e74681 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -29,9 +29,17 @@
#define DRIVER_NAME "dw-mipi-dsi"
-#define GRF_SOC_CON6 0x025c
-#define DSI0_SEL_VOP_LIT (1 << 6)
-#define DSI1_SEL_VOP_LIT (1 << 9)
+#define RK3288_GRF_SOC_CON6 0x025c
+#define RK3288_DSI0_SEL_VOP_LIT BIT(6)
+#define RK3288_DSI1_SEL_VOP_LIT BIT(9)
+
+#define RK3399_GRF_SOC_CON19 0x6250
+#define RK3399_DSI0_SEL_VOP_LIT BIT(0)
+#define RK3399_DSI1_SEL_VOP_LIT BIT(4)
+
+/* disable turnrequest, turndisable, forcetxstopmode, forcerxmode */
+#define RK3399_GRF_SOC_CON22 0x6258
+#define RK3399_GRF_DSI_MODE 0xffff0000
#define DSI_VERSION 0x00
#define DSI_PWR_UP 0x04
@@ -265,6 +273,11 @@ enum {
};
struct dw_mipi_dsi_plat_data {
+ u32 dsi0_en_bit;
+ u32 dsi1_en_bit;
+ u32 grf_switch_reg;
+ u32 grf_dsi0_mode;
+ u32 grf_dsi0_mode_reg;
unsigned int max_data_lanes;
enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
struct drm_display_mode *mode);
@@ -281,6 +294,7 @@ struct dw_mipi_dsi {
struct clk *pllref_clk;
struct clk *pclk;
+ struct clk *phy_cfg_clk;
unsigned int lane_mbps; /* per lane */
u32 channel;
@@ -425,6 +439,12 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR);
dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
+ ret = clk_prepare_enable(dsi->phy_cfg_clk);
+ if (ret) {
+ dev_err(dsi->dev, "Failed to enable phy_cfg_clk\n");
+ return ret;
+ }
+
dw_mipi_dsi_phy_write(dsi, 0x10, BYPASS_VCO_RANGE |
VCO_RANGE_CON_SEL(vco) |
VCO_IN_CAP_CON_LOW |
@@ -481,17 +501,18 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
val, val & LOCK, 1000, PHY_STATUS_TIMEOUT_US);
if (ret < 0) {
dev_err(dsi->dev, "failed to wait for phy lock state\n");
- return ret;
+ goto phy_init_end;
}
ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
val, val & STOP_STATE_CLK_LANE, 1000,
PHY_STATUS_TIMEOUT_US);
- if (ret < 0) {
+ if (ret < 0)
dev_err(dsi->dev,
"failed to wait for phy clk lane stop state\n");
- return ret;
- }
+
+phy_init_end:
+ clk_disable_unprepare(dsi->phy_cfg_clk);
return ret;
}
@@ -960,6 +981,7 @@ static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
{
struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
+ const struct dw_mipi_dsi_plat_data *pdata = dsi->pdata;
int mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, encoder);
u32 val;
int ret;
@@ -985,6 +1007,10 @@ static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
dw_mipi_dsi_dphy_interface_config(dsi);
dw_mipi_dsi_clear_err(dsi);
+ if (pdata->grf_dsi0_mode_reg)
+ regmap_write(dsi->grf_regmap, pdata->grf_dsi0_mode_reg,
+ pdata->grf_dsi0_mode);
+
dw_mipi_dsi_phy_init(dsi);
dw_mipi_dsi_wait_for_two_frames(mode);
@@ -998,11 +1024,11 @@ static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
clk_disable_unprepare(dsi->pclk);
if (mux)
- val = DSI0_SEL_VOP_LIT | (DSI0_SEL_VOP_LIT << 16);
+ val = pdata->dsi0_en_bit | (pdata->dsi0_en_bit << 16);
else
- val = DSI0_SEL_VOP_LIT << 16;
+ val = pdata->dsi0_en_bit << 16;
- regmap_write(dsi->grf_regmap, GRF_SOC_CON6, val);
+ regmap_write(dsi->grf_regmap, pdata->grf_switch_reg, val);
dev_dbg(dsi->dev, "vop %s output to dsi0\n", (mux) ? "LIT" : "BIG");
}
@@ -1161,14 +1187,29 @@ static enum drm_mode_status rk3288_mipi_dsi_mode_valid(
}
static struct dw_mipi_dsi_plat_data rk3288_mipi_dsi_drv_data = {
+ .dsi0_en_bit = RK3288_DSI0_SEL_VOP_LIT,
+ .dsi1_en_bit = RK3288_DSI1_SEL_VOP_LIT,
+ .grf_switch_reg = RK3288_GRF_SOC_CON6,
.max_data_lanes = 4,
.mode_valid = rk3288_mipi_dsi_mode_valid,
};
+static struct dw_mipi_dsi_plat_data rk3399_mipi_dsi_drv_data = {
+ .dsi0_en_bit = RK3399_DSI0_SEL_VOP_LIT,
+ .dsi1_en_bit = RK3399_DSI1_SEL_VOP_LIT,
+ .grf_switch_reg = RK3399_GRF_SOC_CON19,
+ .grf_dsi0_mode = RK3399_GRF_DSI_MODE,
+ .grf_dsi0_mode_reg = RK3399_GRF_SOC_CON22,
+ .max_data_lanes = 4,
+};
+
static const struct of_device_id dw_mipi_dsi_dt_ids[] = {
{
.compatible = "rockchip,rk3288-mipi-dsi",
.data = &rk3288_mipi_dsi_drv_data,
+ }, {
+ .compatible = "rockchip,rk3399-mipi-dsi",
+ .data = &rk3399_mipi_dsi_drv_data,
},
{ /* sentinel */ }
};
@@ -1248,6 +1289,17 @@ static int dw_mipi_dsi_bind(struct device *dev, struct device *master,
clk_disable_unprepare(dsi->pclk);
}
+ dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg");
+ if (IS_ERR(dsi->phy_cfg_clk)) {
+ ret = PTR_ERR(dsi->phy_cfg_clk);
+ if (ret != -ENOENT) {
+ dev_err(dev, "Unable to get phy_cfg_clk: %d\n", ret);
+ return ret;
+ }
+ dsi->phy_cfg_clk = NULL;
+ dev_dbg(dev, "have not phy_cfg_clk\n");
+ }
+
ret = clk_prepare_enable(dsi->pllref_clk);
if (ret) {
dev_err(dev, "%s: Failed to enable pllref_clk\n", __func__);
--
2.6.3
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [RESEND PATCH v7 2/7] drm/rockchip/dsi: dw-mipi: support RK3399 mipi dsi
@ 2017-02-20 8:02 ` Chris Zhong
0 siblings, 0 replies; 51+ messages in thread
From: Chris Zhong @ 2017-02-20 8:02 UTC (permalink / raw)
To: linux-arm-kernel
The vopb/vopl switch register of RK3399 mipi is different from RK3288,
the default setting for mipi dsi mode is different too, so add a
of_device_id structure to distinguish them, and make sure set the
correct mode before mipi phy init.
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
---
Changes in v6:
- no need check phy_cfg_clk before enable/disable
Changes in v5:
- check the error of phy_cfg_clk in dw_mipi_dsi_bind
Changes in v4:
- remove the unrelated change
Changes in v3:
- base on John Keeping's patch series
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 72 +++++++++++++++++++++++++++++-----
1 file changed, 62 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index cc58ada..4e74681 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -29,9 +29,17 @@
#define DRIVER_NAME "dw-mipi-dsi"
-#define GRF_SOC_CON6 0x025c
-#define DSI0_SEL_VOP_LIT (1 << 6)
-#define DSI1_SEL_VOP_LIT (1 << 9)
+#define RK3288_GRF_SOC_CON6 0x025c
+#define RK3288_DSI0_SEL_VOP_LIT BIT(6)
+#define RK3288_DSI1_SEL_VOP_LIT BIT(9)
+
+#define RK3399_GRF_SOC_CON19 0x6250
+#define RK3399_DSI0_SEL_VOP_LIT BIT(0)
+#define RK3399_DSI1_SEL_VOP_LIT BIT(4)
+
+/* disable turnrequest, turndisable, forcetxstopmode, forcerxmode */
+#define RK3399_GRF_SOC_CON22 0x6258
+#define RK3399_GRF_DSI_MODE 0xffff0000
#define DSI_VERSION 0x00
#define DSI_PWR_UP 0x04
@@ -265,6 +273,11 @@ enum {
};
struct dw_mipi_dsi_plat_data {
+ u32 dsi0_en_bit;
+ u32 dsi1_en_bit;
+ u32 grf_switch_reg;
+ u32 grf_dsi0_mode;
+ u32 grf_dsi0_mode_reg;
unsigned int max_data_lanes;
enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
struct drm_display_mode *mode);
@@ -281,6 +294,7 @@ struct dw_mipi_dsi {
struct clk *pllref_clk;
struct clk *pclk;
+ struct clk *phy_cfg_clk;
unsigned int lane_mbps; /* per lane */
u32 channel;
@@ -425,6 +439,12 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR);
dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
+ ret = clk_prepare_enable(dsi->phy_cfg_clk);
+ if (ret) {
+ dev_err(dsi->dev, "Failed to enable phy_cfg_clk\n");
+ return ret;
+ }
+
dw_mipi_dsi_phy_write(dsi, 0x10, BYPASS_VCO_RANGE |
VCO_RANGE_CON_SEL(vco) |
VCO_IN_CAP_CON_LOW |
@@ -481,17 +501,18 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
val, val & LOCK, 1000, PHY_STATUS_TIMEOUT_US);
if (ret < 0) {
dev_err(dsi->dev, "failed to wait for phy lock state\n");
- return ret;
+ goto phy_init_end;
}
ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
val, val & STOP_STATE_CLK_LANE, 1000,
PHY_STATUS_TIMEOUT_US);
- if (ret < 0) {
+ if (ret < 0)
dev_err(dsi->dev,
"failed to wait for phy clk lane stop state\n");
- return ret;
- }
+
+phy_init_end:
+ clk_disable_unprepare(dsi->phy_cfg_clk);
return ret;
}
@@ -960,6 +981,7 @@ static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
{
struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
+ const struct dw_mipi_dsi_plat_data *pdata = dsi->pdata;
int mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, encoder);
u32 val;
int ret;
@@ -985,6 +1007,10 @@ static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
dw_mipi_dsi_dphy_interface_config(dsi);
dw_mipi_dsi_clear_err(dsi);
+ if (pdata->grf_dsi0_mode_reg)
+ regmap_write(dsi->grf_regmap, pdata->grf_dsi0_mode_reg,
+ pdata->grf_dsi0_mode);
+
dw_mipi_dsi_phy_init(dsi);
dw_mipi_dsi_wait_for_two_frames(mode);
@@ -998,11 +1024,11 @@ static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
clk_disable_unprepare(dsi->pclk);
if (mux)
- val = DSI0_SEL_VOP_LIT | (DSI0_SEL_VOP_LIT << 16);
+ val = pdata->dsi0_en_bit | (pdata->dsi0_en_bit << 16);
else
- val = DSI0_SEL_VOP_LIT << 16;
+ val = pdata->dsi0_en_bit << 16;
- regmap_write(dsi->grf_regmap, GRF_SOC_CON6, val);
+ regmap_write(dsi->grf_regmap, pdata->grf_switch_reg, val);
dev_dbg(dsi->dev, "vop %s output to dsi0\n", (mux) ? "LIT" : "BIG");
}
@@ -1161,14 +1187,29 @@ static enum drm_mode_status rk3288_mipi_dsi_mode_valid(
}
static struct dw_mipi_dsi_plat_data rk3288_mipi_dsi_drv_data = {
+ .dsi0_en_bit = RK3288_DSI0_SEL_VOP_LIT,
+ .dsi1_en_bit = RK3288_DSI1_SEL_VOP_LIT,
+ .grf_switch_reg = RK3288_GRF_SOC_CON6,
.max_data_lanes = 4,
.mode_valid = rk3288_mipi_dsi_mode_valid,
};
+static struct dw_mipi_dsi_plat_data rk3399_mipi_dsi_drv_data = {
+ .dsi0_en_bit = RK3399_DSI0_SEL_VOP_LIT,
+ .dsi1_en_bit = RK3399_DSI1_SEL_VOP_LIT,
+ .grf_switch_reg = RK3399_GRF_SOC_CON19,
+ .grf_dsi0_mode = RK3399_GRF_DSI_MODE,
+ .grf_dsi0_mode_reg = RK3399_GRF_SOC_CON22,
+ .max_data_lanes = 4,
+};
+
static const struct of_device_id dw_mipi_dsi_dt_ids[] = {
{
.compatible = "rockchip,rk3288-mipi-dsi",
.data = &rk3288_mipi_dsi_drv_data,
+ }, {
+ .compatible = "rockchip,rk3399-mipi-dsi",
+ .data = &rk3399_mipi_dsi_drv_data,
},
{ /* sentinel */ }
};
@@ -1248,6 +1289,17 @@ static int dw_mipi_dsi_bind(struct device *dev, struct device *master,
clk_disable_unprepare(dsi->pclk);
}
+ dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg");
+ if (IS_ERR(dsi->phy_cfg_clk)) {
+ ret = PTR_ERR(dsi->phy_cfg_clk);
+ if (ret != -ENOENT) {
+ dev_err(dev, "Unable to get phy_cfg_clk: %d\n", ret);
+ return ret;
+ }
+ dsi->phy_cfg_clk = NULL;
+ dev_dbg(dev, "have not phy_cfg_clk\n");
+ }
+
ret = clk_prepare_enable(dsi->pllref_clk);
if (ret) {
dev_err(dev, "%s: Failed to enable pllref_clk\n", __func__);
--
2.6.3
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [RESEND PATCH v7 3/7] drm/rockchip/dsi: dw-mipi: correct the coding style
2017-02-20 8:02 ` Chris Zhong
(?)
@ 2017-02-20 8:02 ` Chris Zhong
-1 siblings, 0 replies; 51+ messages in thread
From: Chris Zhong @ 2017-02-20 8:02 UTC (permalink / raw)
To: john, dianders, tfiga, heiko, yzq, mark.rutland, devicetree,
robh+dt, galak, pawel.moll, seanpaul
Cc: linux-rockchip, Chris Zhong, Mark Yao, David Airlie, dri-devel,
linux-arm-kernel, linux-kernel
correct the coding style, according the checkpatch scripts
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 29 ++++++++++++++---------------
1 file changed, 14 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index 4e74681..836cb83 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -157,7 +157,6 @@
#define LPRX_TO_CNT(p) ((p) & 0xffff)
#define DSI_BTA_TO_CNT 0x8c
-
#define DSI_LPCLK_CTRL 0x94
#define AUTO_CLKLANE_CTRL BIT(1)
#define PHY_TXREQUESTCLKHS BIT(0)
@@ -223,11 +222,11 @@
#define HSFREQRANGE_SEL(val) (((val) & 0x3f) << 1)
-#define INPUT_DIVIDER(val) ((val - 1) & 0x7f)
+#define INPUT_DIVIDER(val) (((val) - 1) & 0x7f)
#define LOW_PROGRAM_EN 0
#define HIGH_PROGRAM_EN BIT(7)
-#define LOOP_DIV_LOW_SEL(val) ((val - 1) & 0x1f)
-#define LOOP_DIV_HIGH_SEL(val) (((val - 1) >> 5) & 0x1f)
+#define LOOP_DIV_LOW_SEL(val) (((val) - 1) & 0x1f)
+#define LOOP_DIV_HIGH_SEL(val) ((((val) - 1) >> 5) & 0x1f)
#define PLL_LOOP_DIV_EN BIT(5)
#define PLL_INPUT_DIV_EN BIT(4)
@@ -369,6 +368,7 @@ static inline struct dw_mipi_dsi *encoder_to_dsi(struct drm_encoder *encoder)
{
return container_of(encoder, struct dw_mipi_dsi, encoder);
}
+
static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
{
writel(val, dsi->base + reg);
@@ -380,7 +380,7 @@ static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
}
static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi *dsi, u8 test_code,
- u8 test_data)
+ u8 test_data)
{
/*
* With the falling edge on TESTCLK, the TESTDIN[7:0] signal content
@@ -496,7 +496,6 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
-
ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
val, val & LOCK, 1000, PHY_STATUS_TIMEOUT_US);
if (ret < 0) {
@@ -571,7 +570,7 @@ static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
if (device->lanes > dsi->pdata->max_data_lanes) {
dev_err(dsi->dev, "the number of data lanes(%u) is too many\n",
- device->lanes);
+ device->lanes);
return -EINVAL;
}
@@ -1060,14 +1059,14 @@ dw_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder,
return 0;
}
-static struct drm_encoder_helper_funcs
+static const struct drm_encoder_helper_funcs
dw_mipi_dsi_encoder_helper_funcs = {
.enable = dw_mipi_dsi_encoder_enable,
.disable = dw_mipi_dsi_encoder_disable,
.atomic_check = dw_mipi_dsi_encoder_atomic_check,
};
-static struct drm_encoder_funcs dw_mipi_dsi_encoder_funcs = {
+static const struct drm_encoder_funcs dw_mipi_dsi_encoder_funcs = {
.destroy = drm_encoder_cleanup,
};
@@ -1103,7 +1102,7 @@ static void dw_mipi_dsi_drm_connector_destroy(struct drm_connector *connector)
drm_connector_cleanup(connector);
}
-static struct drm_connector_funcs dw_mipi_dsi_atomic_connector_funcs = {
+static const struct drm_connector_funcs dw_mipi_dsi_atomic_connector_funcs = {
.dpms = drm_atomic_helper_connector_dpms,
.fill_modes = drm_helper_probe_single_connector_modes,
.destroy = dw_mipi_dsi_drm_connector_destroy,
@@ -1113,7 +1112,7 @@ static struct drm_connector_funcs dw_mipi_dsi_atomic_connector_funcs = {
};
static int dw_mipi_dsi_register(struct drm_device *drm,
- struct dw_mipi_dsi *dsi)
+ struct dw_mipi_dsi *dsi)
{
struct drm_encoder *encoder = &dsi->encoder;
struct drm_connector *connector = &dsi->connector;
@@ -1134,14 +1133,14 @@ static int dw_mipi_dsi_register(struct drm_device *drm,
drm_encoder_helper_add(&dsi->encoder,
&dw_mipi_dsi_encoder_helper_funcs);
ret = drm_encoder_init(drm, &dsi->encoder, &dw_mipi_dsi_encoder_funcs,
- DRM_MODE_ENCODER_DSI, NULL);
+ DRM_MODE_ENCODER_DSI, NULL);
if (ret) {
dev_err(dev, "Failed to initialize encoder with drm\n");
return ret;
}
drm_connector_helper_add(connector,
- &dw_mipi_dsi_connector_helper_funcs);
+ &dw_mipi_dsi_connector_helper_funcs);
drm_connector_init(drm, &dsi->connector,
&dw_mipi_dsi_atomic_connector_funcs,
@@ -1216,7 +1215,7 @@ static const struct of_device_id dw_mipi_dsi_dt_ids[] = {
MODULE_DEVICE_TABLE(of, dw_mipi_dsi_dt_ids);
static int dw_mipi_dsi_bind(struct device *dev, struct device *master,
- void *data)
+ void *data)
{
const struct of_device_id *of_id =
of_match_device(dw_mipi_dsi_dt_ids, dev);
@@ -1331,7 +1330,7 @@ static int dw_mipi_dsi_bind(struct device *dev, struct device *master,
}
static void dw_mipi_dsi_unbind(struct device *dev, struct device *master,
- void *data)
+ void *data)
{
struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
--
2.6.3
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [RESEND PATCH v7 3/7] drm/rockchip/dsi: dw-mipi: correct the coding style
@ 2017-02-20 8:02 ` Chris Zhong
0 siblings, 0 replies; 51+ messages in thread
From: Chris Zhong @ 2017-02-20 8:02 UTC (permalink / raw)
To: john, dianders, tfiga, heiko, yzq, mark.rutland, devicetree,
robh+dt, galak, pawel.moll, seanpaul
Cc: linux-kernel, dri-devel, linux-rockchip, Chris Zhong, linux-arm-kernel
correct the coding style, according the checkpatch scripts
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 29 ++++++++++++++---------------
1 file changed, 14 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index 4e74681..836cb83 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -157,7 +157,6 @@
#define LPRX_TO_CNT(p) ((p) & 0xffff)
#define DSI_BTA_TO_CNT 0x8c
-
#define DSI_LPCLK_CTRL 0x94
#define AUTO_CLKLANE_CTRL BIT(1)
#define PHY_TXREQUESTCLKHS BIT(0)
@@ -223,11 +222,11 @@
#define HSFREQRANGE_SEL(val) (((val) & 0x3f) << 1)
-#define INPUT_DIVIDER(val) ((val - 1) & 0x7f)
+#define INPUT_DIVIDER(val) (((val) - 1) & 0x7f)
#define LOW_PROGRAM_EN 0
#define HIGH_PROGRAM_EN BIT(7)
-#define LOOP_DIV_LOW_SEL(val) ((val - 1) & 0x1f)
-#define LOOP_DIV_HIGH_SEL(val) (((val - 1) >> 5) & 0x1f)
+#define LOOP_DIV_LOW_SEL(val) (((val) - 1) & 0x1f)
+#define LOOP_DIV_HIGH_SEL(val) ((((val) - 1) >> 5) & 0x1f)
#define PLL_LOOP_DIV_EN BIT(5)
#define PLL_INPUT_DIV_EN BIT(4)
@@ -369,6 +368,7 @@ static inline struct dw_mipi_dsi *encoder_to_dsi(struct drm_encoder *encoder)
{
return container_of(encoder, struct dw_mipi_dsi, encoder);
}
+
static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
{
writel(val, dsi->base + reg);
@@ -380,7 +380,7 @@ static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
}
static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi *dsi, u8 test_code,
- u8 test_data)
+ u8 test_data)
{
/*
* With the falling edge on TESTCLK, the TESTDIN[7:0] signal content
@@ -496,7 +496,6 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
-
ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
val, val & LOCK, 1000, PHY_STATUS_TIMEOUT_US);
if (ret < 0) {
@@ -571,7 +570,7 @@ static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
if (device->lanes > dsi->pdata->max_data_lanes) {
dev_err(dsi->dev, "the number of data lanes(%u) is too many\n",
- device->lanes);
+ device->lanes);
return -EINVAL;
}
@@ -1060,14 +1059,14 @@ dw_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder,
return 0;
}
-static struct drm_encoder_helper_funcs
+static const struct drm_encoder_helper_funcs
dw_mipi_dsi_encoder_helper_funcs = {
.enable = dw_mipi_dsi_encoder_enable,
.disable = dw_mipi_dsi_encoder_disable,
.atomic_check = dw_mipi_dsi_encoder_atomic_check,
};
-static struct drm_encoder_funcs dw_mipi_dsi_encoder_funcs = {
+static const struct drm_encoder_funcs dw_mipi_dsi_encoder_funcs = {
.destroy = drm_encoder_cleanup,
};
@@ -1103,7 +1102,7 @@ static void dw_mipi_dsi_drm_connector_destroy(struct drm_connector *connector)
drm_connector_cleanup(connector);
}
-static struct drm_connector_funcs dw_mipi_dsi_atomic_connector_funcs = {
+static const struct drm_connector_funcs dw_mipi_dsi_atomic_connector_funcs = {
.dpms = drm_atomic_helper_connector_dpms,
.fill_modes = drm_helper_probe_single_connector_modes,
.destroy = dw_mipi_dsi_drm_connector_destroy,
@@ -1113,7 +1112,7 @@ static struct drm_connector_funcs dw_mipi_dsi_atomic_connector_funcs = {
};
static int dw_mipi_dsi_register(struct drm_device *drm,
- struct dw_mipi_dsi *dsi)
+ struct dw_mipi_dsi *dsi)
{
struct drm_encoder *encoder = &dsi->encoder;
struct drm_connector *connector = &dsi->connector;
@@ -1134,14 +1133,14 @@ static int dw_mipi_dsi_register(struct drm_device *drm,
drm_encoder_helper_add(&dsi->encoder,
&dw_mipi_dsi_encoder_helper_funcs);
ret = drm_encoder_init(drm, &dsi->encoder, &dw_mipi_dsi_encoder_funcs,
- DRM_MODE_ENCODER_DSI, NULL);
+ DRM_MODE_ENCODER_DSI, NULL);
if (ret) {
dev_err(dev, "Failed to initialize encoder with drm\n");
return ret;
}
drm_connector_helper_add(connector,
- &dw_mipi_dsi_connector_helper_funcs);
+ &dw_mipi_dsi_connector_helper_funcs);
drm_connector_init(drm, &dsi->connector,
&dw_mipi_dsi_atomic_connector_funcs,
@@ -1216,7 +1215,7 @@ static const struct of_device_id dw_mipi_dsi_dt_ids[] = {
MODULE_DEVICE_TABLE(of, dw_mipi_dsi_dt_ids);
static int dw_mipi_dsi_bind(struct device *dev, struct device *master,
- void *data)
+ void *data)
{
const struct of_device_id *of_id =
of_match_device(dw_mipi_dsi_dt_ids, dev);
@@ -1331,7 +1330,7 @@ static int dw_mipi_dsi_bind(struct device *dev, struct device *master,
}
static void dw_mipi_dsi_unbind(struct device *dev, struct device *master,
- void *data)
+ void *data)
{
struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
--
2.6.3
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [RESEND PATCH v7 3/7] drm/rockchip/dsi: dw-mipi: correct the coding style
@ 2017-02-20 8:02 ` Chris Zhong
0 siblings, 0 replies; 51+ messages in thread
From: Chris Zhong @ 2017-02-20 8:02 UTC (permalink / raw)
To: linux-arm-kernel
correct the coding style, according the checkpatch scripts
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 29 ++++++++++++++---------------
1 file changed, 14 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index 4e74681..836cb83 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -157,7 +157,6 @@
#define LPRX_TO_CNT(p) ((p) & 0xffff)
#define DSI_BTA_TO_CNT 0x8c
-
#define DSI_LPCLK_CTRL 0x94
#define AUTO_CLKLANE_CTRL BIT(1)
#define PHY_TXREQUESTCLKHS BIT(0)
@@ -223,11 +222,11 @@
#define HSFREQRANGE_SEL(val) (((val) & 0x3f) << 1)
-#define INPUT_DIVIDER(val) ((val - 1) & 0x7f)
+#define INPUT_DIVIDER(val) (((val) - 1) & 0x7f)
#define LOW_PROGRAM_EN 0
#define HIGH_PROGRAM_EN BIT(7)
-#define LOOP_DIV_LOW_SEL(val) ((val - 1) & 0x1f)
-#define LOOP_DIV_HIGH_SEL(val) (((val - 1) >> 5) & 0x1f)
+#define LOOP_DIV_LOW_SEL(val) (((val) - 1) & 0x1f)
+#define LOOP_DIV_HIGH_SEL(val) ((((val) - 1) >> 5) & 0x1f)
#define PLL_LOOP_DIV_EN BIT(5)
#define PLL_INPUT_DIV_EN BIT(4)
@@ -369,6 +368,7 @@ static inline struct dw_mipi_dsi *encoder_to_dsi(struct drm_encoder *encoder)
{
return container_of(encoder, struct dw_mipi_dsi, encoder);
}
+
static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
{
writel(val, dsi->base + reg);
@@ -380,7 +380,7 @@ static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
}
static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi *dsi, u8 test_code,
- u8 test_data)
+ u8 test_data)
{
/*
* With the falling edge on TESTCLK, the TESTDIN[7:0] signal content
@@ -496,7 +496,6 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
-
ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
val, val & LOCK, 1000, PHY_STATUS_TIMEOUT_US);
if (ret < 0) {
@@ -571,7 +570,7 @@ static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
if (device->lanes > dsi->pdata->max_data_lanes) {
dev_err(dsi->dev, "the number of data lanes(%u) is too many\n",
- device->lanes);
+ device->lanes);
return -EINVAL;
}
@@ -1060,14 +1059,14 @@ dw_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder,
return 0;
}
-static struct drm_encoder_helper_funcs
+static const struct drm_encoder_helper_funcs
dw_mipi_dsi_encoder_helper_funcs = {
.enable = dw_mipi_dsi_encoder_enable,
.disable = dw_mipi_dsi_encoder_disable,
.atomic_check = dw_mipi_dsi_encoder_atomic_check,
};
-static struct drm_encoder_funcs dw_mipi_dsi_encoder_funcs = {
+static const struct drm_encoder_funcs dw_mipi_dsi_encoder_funcs = {
.destroy = drm_encoder_cleanup,
};
@@ -1103,7 +1102,7 @@ static void dw_mipi_dsi_drm_connector_destroy(struct drm_connector *connector)
drm_connector_cleanup(connector);
}
-static struct drm_connector_funcs dw_mipi_dsi_atomic_connector_funcs = {
+static const struct drm_connector_funcs dw_mipi_dsi_atomic_connector_funcs = {
.dpms = drm_atomic_helper_connector_dpms,
.fill_modes = drm_helper_probe_single_connector_modes,
.destroy = dw_mipi_dsi_drm_connector_destroy,
@@ -1113,7 +1112,7 @@ static struct drm_connector_funcs dw_mipi_dsi_atomic_connector_funcs = {
};
static int dw_mipi_dsi_register(struct drm_device *drm,
- struct dw_mipi_dsi *dsi)
+ struct dw_mipi_dsi *dsi)
{
struct drm_encoder *encoder = &dsi->encoder;
struct drm_connector *connector = &dsi->connector;
@@ -1134,14 +1133,14 @@ static int dw_mipi_dsi_register(struct drm_device *drm,
drm_encoder_helper_add(&dsi->encoder,
&dw_mipi_dsi_encoder_helper_funcs);
ret = drm_encoder_init(drm, &dsi->encoder, &dw_mipi_dsi_encoder_funcs,
- DRM_MODE_ENCODER_DSI, NULL);
+ DRM_MODE_ENCODER_DSI, NULL);
if (ret) {
dev_err(dev, "Failed to initialize encoder with drm\n");
return ret;
}
drm_connector_helper_add(connector,
- &dw_mipi_dsi_connector_helper_funcs);
+ &dw_mipi_dsi_connector_helper_funcs);
drm_connector_init(drm, &dsi->connector,
&dw_mipi_dsi_atomic_connector_funcs,
@@ -1216,7 +1215,7 @@ static const struct of_device_id dw_mipi_dsi_dt_ids[] = {
MODULE_DEVICE_TABLE(of, dw_mipi_dsi_dt_ids);
static int dw_mipi_dsi_bind(struct device *dev, struct device *master,
- void *data)
+ void *data)
{
const struct of_device_id *of_id =
of_match_device(dw_mipi_dsi_dt_ids, dev);
@@ -1331,7 +1330,7 @@ static int dw_mipi_dsi_bind(struct device *dev, struct device *master,
}
static void dw_mipi_dsi_unbind(struct device *dev, struct device *master,
- void *data)
+ void *data)
{
struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
--
2.6.3
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [RESEND PATCH v7 4/7] drm/rockchip/dsi: remove mode_valid function
2017-02-20 8:02 ` Chris Zhong
(?)
@ 2017-02-20 8:02 ` Chris Zhong
-1 siblings, 0 replies; 51+ messages in thread
From: Chris Zhong @ 2017-02-20 8:02 UTC (permalink / raw)
To: john, dianders, tfiga, heiko, yzq, mark.rutland, devicetree,
robh+dt, galak, pawel.moll, seanpaul
Cc: linux-rockchip, Chris Zhong, Mark Yao, David Airlie, dri-devel,
linux-arm-kernel, linux-kernel
The MIPI DSI do not need check the validity of resolution, the max
resolution should depend VOP. Hence, remove rk3288_mipi_dsi_mode_valid
here.
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 39 ----------------------------------
1 file changed, 39 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index 836cb83..c2d7674 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -278,8 +278,6 @@ struct dw_mipi_dsi_plat_data {
u32 grf_dsi0_mode;
u32 grf_dsi0_mode_reg;
unsigned int max_data_lanes;
- enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
- struct drm_display_mode *mode);
};
struct dw_mipi_dsi {
@@ -1077,23 +1075,8 @@ static int dw_mipi_dsi_connector_get_modes(struct drm_connector *connector)
return drm_panel_get_modes(dsi->panel);
}
-static enum drm_mode_status dw_mipi_dsi_mode_valid(
- struct drm_connector *connector,
- struct drm_display_mode *mode)
-{
- struct dw_mipi_dsi *dsi = con_to_dsi(connector);
-
- enum drm_mode_status mode_status = MODE_OK;
-
- if (dsi->pdata->mode_valid)
- mode_status = dsi->pdata->mode_valid(connector, mode);
-
- return mode_status;
-}
-
static struct drm_connector_helper_funcs dw_mipi_dsi_connector_helper_funcs = {
.get_modes = dw_mipi_dsi_connector_get_modes,
- .mode_valid = dw_mipi_dsi_mode_valid,
};
static void dw_mipi_dsi_drm_connector_destroy(struct drm_connector *connector)
@@ -1164,33 +1147,11 @@ static int rockchip_mipi_parse_dt(struct dw_mipi_dsi *dsi)
return 0;
}
-static enum drm_mode_status rk3288_mipi_dsi_mode_valid(
- struct drm_connector *connector,
- struct drm_display_mode *mode)
-{
- /*
- * The VID_PKT_SIZE field in the DSI_VID_PKT_CFG
- * register is 11-bit.
- */
- if (mode->hdisplay > 0x7ff)
- return MODE_BAD_HVALUE;
-
- /*
- * The V_ACTIVE_LINES field in the DSI_VTIMING_CFG
- * register is 11-bit.
- */
- if (mode->vdisplay > 0x7ff)
- return MODE_BAD_VVALUE;
-
- return MODE_OK;
-}
-
static struct dw_mipi_dsi_plat_data rk3288_mipi_dsi_drv_data = {
.dsi0_en_bit = RK3288_DSI0_SEL_VOP_LIT,
.dsi1_en_bit = RK3288_DSI1_SEL_VOP_LIT,
.grf_switch_reg = RK3288_GRF_SOC_CON6,
.max_data_lanes = 4,
- .mode_valid = rk3288_mipi_dsi_mode_valid,
};
static struct dw_mipi_dsi_plat_data rk3399_mipi_dsi_drv_data = {
--
2.6.3
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [RESEND PATCH v7 4/7] drm/rockchip/dsi: remove mode_valid function
@ 2017-02-20 8:02 ` Chris Zhong
0 siblings, 0 replies; 51+ messages in thread
From: Chris Zhong @ 2017-02-20 8:02 UTC (permalink / raw)
To: john, dianders, tfiga, heiko, yzq, mark.rutland, devicetree,
robh+dt, galak, pawel.moll, seanpaul
Cc: linux-kernel, dri-devel, linux-rockchip, Chris Zhong, linux-arm-kernel
The MIPI DSI do not need check the validity of resolution, the max
resolution should depend VOP. Hence, remove rk3288_mipi_dsi_mode_valid
here.
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 39 ----------------------------------
1 file changed, 39 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index 836cb83..c2d7674 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -278,8 +278,6 @@ struct dw_mipi_dsi_plat_data {
u32 grf_dsi0_mode;
u32 grf_dsi0_mode_reg;
unsigned int max_data_lanes;
- enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
- struct drm_display_mode *mode);
};
struct dw_mipi_dsi {
@@ -1077,23 +1075,8 @@ static int dw_mipi_dsi_connector_get_modes(struct drm_connector *connector)
return drm_panel_get_modes(dsi->panel);
}
-static enum drm_mode_status dw_mipi_dsi_mode_valid(
- struct drm_connector *connector,
- struct drm_display_mode *mode)
-{
- struct dw_mipi_dsi *dsi = con_to_dsi(connector);
-
- enum drm_mode_status mode_status = MODE_OK;
-
- if (dsi->pdata->mode_valid)
- mode_status = dsi->pdata->mode_valid(connector, mode);
-
- return mode_status;
-}
-
static struct drm_connector_helper_funcs dw_mipi_dsi_connector_helper_funcs = {
.get_modes = dw_mipi_dsi_connector_get_modes,
- .mode_valid = dw_mipi_dsi_mode_valid,
};
static void dw_mipi_dsi_drm_connector_destroy(struct drm_connector *connector)
@@ -1164,33 +1147,11 @@ static int rockchip_mipi_parse_dt(struct dw_mipi_dsi *dsi)
return 0;
}
-static enum drm_mode_status rk3288_mipi_dsi_mode_valid(
- struct drm_connector *connector,
- struct drm_display_mode *mode)
-{
- /*
- * The VID_PKT_SIZE field in the DSI_VID_PKT_CFG
- * register is 11-bit.
- */
- if (mode->hdisplay > 0x7ff)
- return MODE_BAD_HVALUE;
-
- /*
- * The V_ACTIVE_LINES field in the DSI_VTIMING_CFG
- * register is 11-bit.
- */
- if (mode->vdisplay > 0x7ff)
- return MODE_BAD_VVALUE;
-
- return MODE_OK;
-}
-
static struct dw_mipi_dsi_plat_data rk3288_mipi_dsi_drv_data = {
.dsi0_en_bit = RK3288_DSI0_SEL_VOP_LIT,
.dsi1_en_bit = RK3288_DSI1_SEL_VOP_LIT,
.grf_switch_reg = RK3288_GRF_SOC_CON6,
.max_data_lanes = 4,
- .mode_valid = rk3288_mipi_dsi_mode_valid,
};
static struct dw_mipi_dsi_plat_data rk3399_mipi_dsi_drv_data = {
--
2.6.3
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [RESEND PATCH v7 4/7] drm/rockchip/dsi: remove mode_valid function
@ 2017-02-20 8:02 ` Chris Zhong
0 siblings, 0 replies; 51+ messages in thread
From: Chris Zhong @ 2017-02-20 8:02 UTC (permalink / raw)
To: linux-arm-kernel
The MIPI DSI do not need check the validity of resolution, the max
resolution should depend VOP. Hence, remove rk3288_mipi_dsi_mode_valid
here.
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 39 ----------------------------------
1 file changed, 39 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index 836cb83..c2d7674 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -278,8 +278,6 @@ struct dw_mipi_dsi_plat_data {
u32 grf_dsi0_mode;
u32 grf_dsi0_mode_reg;
unsigned int max_data_lanes;
- enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
- struct drm_display_mode *mode);
};
struct dw_mipi_dsi {
@@ -1077,23 +1075,8 @@ static int dw_mipi_dsi_connector_get_modes(struct drm_connector *connector)
return drm_panel_get_modes(dsi->panel);
}
-static enum drm_mode_status dw_mipi_dsi_mode_valid(
- struct drm_connector *connector,
- struct drm_display_mode *mode)
-{
- struct dw_mipi_dsi *dsi = con_to_dsi(connector);
-
- enum drm_mode_status mode_status = MODE_OK;
-
- if (dsi->pdata->mode_valid)
- mode_status = dsi->pdata->mode_valid(connector, mode);
-
- return mode_status;
-}
-
static struct drm_connector_helper_funcs dw_mipi_dsi_connector_helper_funcs = {
.get_modes = dw_mipi_dsi_connector_get_modes,
- .mode_valid = dw_mipi_dsi_mode_valid,
};
static void dw_mipi_dsi_drm_connector_destroy(struct drm_connector *connector)
@@ -1164,33 +1147,11 @@ static int rockchip_mipi_parse_dt(struct dw_mipi_dsi *dsi)
return 0;
}
-static enum drm_mode_status rk3288_mipi_dsi_mode_valid(
- struct drm_connector *connector,
- struct drm_display_mode *mode)
-{
- /*
- * The VID_PKT_SIZE field in the DSI_VID_PKT_CFG
- * register is 11-bit.
- */
- if (mode->hdisplay > 0x7ff)
- return MODE_BAD_HVALUE;
-
- /*
- * The V_ACTIVE_LINES field in the DSI_VTIMING_CFG
- * register is 11-bit.
- */
- if (mode->vdisplay > 0x7ff)
- return MODE_BAD_VVALUE;
-
- return MODE_OK;
-}
-
static struct dw_mipi_dsi_plat_data rk3288_mipi_dsi_drv_data = {
.dsi0_en_bit = RK3288_DSI0_SEL_VOP_LIT,
.dsi1_en_bit = RK3288_DSI1_SEL_VOP_LIT,
.grf_switch_reg = RK3288_GRF_SOC_CON6,
.max_data_lanes = 4,
- .mode_valid = rk3288_mipi_dsi_mode_valid,
};
static struct dw_mipi_dsi_plat_data rk3399_mipi_dsi_drv_data = {
--
2.6.3
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [RESEND PATCH v7 5/7] dt-bindings: add power domain node for dw-mipi-rockchip
2017-02-20 8:02 ` Chris Zhong
(?)
@ 2017-02-20 8:02 ` Chris Zhong
-1 siblings, 0 replies; 51+ messages in thread
From: Chris Zhong @ 2017-02-20 8:02 UTC (permalink / raw)
To: john, dianders, tfiga, heiko, yzq, mark.rutland, devicetree,
robh+dt, galak, pawel.moll, seanpaul
Cc: linux-rockchip, Chris Zhong, Mark Yao, David Airlie, dri-devel,
linux-arm-kernel, linux-kernel
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
.../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
index 0f82568..188f6f7 100644
--- a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
+++ b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
@@ -15,6 +15,9 @@ Required properties:
- ports: contain a port node with endpoint definitions as defined in [2].
For vopb,set the reg = <0> and set the reg = <1> for vopl.
+Optional properties:
+- power-domains: a phandle to mipi dsi power domain node.
+
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/media/video-interfaces.txt
--
2.6.3
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [RESEND PATCH v7 5/7] dt-bindings: add power domain node for dw-mipi-rockchip
@ 2017-02-20 8:02 ` Chris Zhong
0 siblings, 0 replies; 51+ messages in thread
From: Chris Zhong @ 2017-02-20 8:02 UTC (permalink / raw)
To: john, dianders, tfiga, heiko, yzq, mark.rutland, devicetree,
robh+dt, galak, pawel.moll, seanpaul
Cc: linux-kernel, dri-devel, linux-rockchip, Chris Zhong, linux-arm-kernel
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
.../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
index 0f82568..188f6f7 100644
--- a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
+++ b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
@@ -15,6 +15,9 @@ Required properties:
- ports: contain a port node with endpoint definitions as defined in [2].
For vopb,set the reg = <0> and set the reg = <1> for vopl.
+Optional properties:
+- power-domains: a phandle to mipi dsi power domain node.
+
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/media/video-interfaces.txt
--
2.6.3
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [RESEND PATCH v7 5/7] dt-bindings: add power domain node for dw-mipi-rockchip
@ 2017-02-20 8:02 ` Chris Zhong
0 siblings, 0 replies; 51+ messages in thread
From: Chris Zhong @ 2017-02-20 8:02 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
.../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
index 0f82568..188f6f7 100644
--- a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
+++ b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
@@ -15,6 +15,9 @@ Required properties:
- ports: contain a port node with endpoint definitions as defined in [2].
For vopb,set the reg = <0> and set the reg = <1> for vopl.
+Optional properties:
+- power-domains: a phandle to mipi dsi power domain node.
+
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/media/video-interfaces.txt
--
2.6.3
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [RESEND PATCH v7 6/7] drm/rockchip/dsi: fix insufficient bandwidth of some panel
2017-02-20 8:02 ` Chris Zhong
(?)
@ 2017-02-20 8:02 ` Chris Zhong
-1 siblings, 0 replies; 51+ messages in thread
From: Chris Zhong @ 2017-02-20 8:02 UTC (permalink / raw)
To: john, dianders, tfiga, heiko, yzq, mark.rutland, devicetree,
robh+dt, galak, pawel.moll, seanpaul
Cc: linux-rockchip, Chris Zhong, Mark Yao, David Airlie, dri-devel,
linux-arm-kernel, linux-kernel
Set the lanes bps to 1 / 0.9 times of pclk, the margin is not enough
for some panel, it will cause the screen display is not normal, so
increases the badnwidth to 1 / 0.8.
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index c2d7674..a653384 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -532,8 +532,8 @@ static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi,
mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC);
if (mpclk) {
- /* take 1 / 0.9, since mbps must big than bandwidth of RGB */
- tmp = mpclk * (bpp / dsi->lanes) * 10 / 9;
+ /* take 1 / 0.8, since mbps must big than bandwidth of RGB */
+ tmp = mpclk * (bpp / dsi->lanes) * 10 / 8;
if (tmp < max_mbps)
target_mbps = tmp;
else
--
2.6.3
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [RESEND PATCH v7 6/7] drm/rockchip/dsi: fix insufficient bandwidth of some panel
@ 2017-02-20 8:02 ` Chris Zhong
0 siblings, 0 replies; 51+ messages in thread
From: Chris Zhong @ 2017-02-20 8:02 UTC (permalink / raw)
To: john, dianders, tfiga, heiko, yzq, mark.rutland, devicetree,
robh+dt, galak, pawel.moll, seanpaul
Cc: linux-kernel, dri-devel, linux-rockchip, Chris Zhong, linux-arm-kernel
Set the lanes bps to 1 / 0.9 times of pclk, the margin is not enough
for some panel, it will cause the screen display is not normal, so
increases the badnwidth to 1 / 0.8.
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index c2d7674..a653384 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -532,8 +532,8 @@ static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi,
mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC);
if (mpclk) {
- /* take 1 / 0.9, since mbps must big than bandwidth of RGB */
- tmp = mpclk * (bpp / dsi->lanes) * 10 / 9;
+ /* take 1 / 0.8, since mbps must big than bandwidth of RGB */
+ tmp = mpclk * (bpp / dsi->lanes) * 10 / 8;
if (tmp < max_mbps)
target_mbps = tmp;
else
--
2.6.3
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [RESEND PATCH v7 6/7] drm/rockchip/dsi: fix insufficient bandwidth of some panel
@ 2017-02-20 8:02 ` Chris Zhong
0 siblings, 0 replies; 51+ messages in thread
From: Chris Zhong @ 2017-02-20 8:02 UTC (permalink / raw)
To: linux-arm-kernel
Set the lanes bps to 1 / 0.9 times of pclk, the margin is not enough
for some panel, it will cause the screen display is not normal, so
increases the badnwidth to 1 / 0.8.
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index c2d7674..a653384 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -532,8 +532,8 @@ static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi,
mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC);
if (mpclk) {
- /* take 1 / 0.9, since mbps must big than bandwidth of RGB */
- tmp = mpclk * (bpp / dsi->lanes) * 10 / 9;
+ /* take 1 / 0.8, since mbps must big than bandwidth of RGB */
+ tmp = mpclk * (bpp / dsi->lanes) * 10 / 8;
if (tmp < max_mbps)
target_mbps = tmp;
else
--
2.6.3
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [RESEND PATCH v7 7/7] drm/rockchip/dsi: add dw-mipi power domain support
2017-02-20 8:02 ` Chris Zhong
(?)
@ 2017-02-20 8:02 ` Chris Zhong
-1 siblings, 0 replies; 51+ messages in thread
From: Chris Zhong @ 2017-02-20 8:02 UTC (permalink / raw)
To: john, dianders, tfiga, heiko, yzq, mark.rutland, devicetree,
robh+dt, galak, pawel.moll, seanpaul
Cc: linux-rockchip, Chris Zhong, Mark Yao, David Airlie, dri-devel,
linux-arm-kernel, linux-kernel
Reference the power domain incase dw-mipi power down when
in use.
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index a653384..b32e4fc 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -12,6 +12,7 @@
#include <linux/math64.h>
#include <linux/module.h>
#include <linux/of_device.h>
+#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/mfd/syscon.h>
@@ -293,6 +294,7 @@ struct dw_mipi_dsi {
struct clk *pclk;
struct clk *phy_cfg_clk;
+ int dpms_mode;
unsigned int lane_mbps; /* per lane */
u32 channel;
u32 lanes;
@@ -960,6 +962,9 @@ static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
{
struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
+ if (dsi->dpms_mode != DRM_MODE_DPMS_ON)
+ return;
+
if (clk_prepare_enable(dsi->pclk)) {
dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
return;
@@ -971,7 +976,9 @@ static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
drm_panel_unprepare(dsi->panel);
dw_mipi_dsi_disable(dsi);
+ pm_runtime_put(dsi->dev);
clk_disable_unprepare(dsi->pclk);
+ dsi->dpms_mode = DRM_MODE_DPMS_OFF;
}
static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
@@ -987,11 +994,15 @@ static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
if (ret < 0)
return;
+ if (dsi->dpms_mode == DRM_MODE_DPMS_ON)
+ return;
+
if (clk_prepare_enable(dsi->pclk)) {
dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
return;
}
+ pm_runtime_get_sync(dsi->dev);
dw_mipi_dsi_init(dsi);
dw_mipi_dsi_dpi_config(dsi, mode);
dw_mipi_dsi_packet_handler_config(dsi);
@@ -1027,6 +1038,7 @@ static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
regmap_write(dsi->grf_regmap, pdata->grf_switch_reg, val);
dev_dbg(dsi->dev, "vop %s output to dsi0\n", (mux) ? "LIT" : "BIG");
+ dsi->dpms_mode = DRM_MODE_DPMS_ON;
}
static int
@@ -1194,6 +1206,7 @@ static int dw_mipi_dsi_bind(struct device *dev, struct device *master,
dsi->dev = dev;
dsi->pdata = pdata;
+ dsi->dpms_mode = DRM_MODE_DPMS_OFF;
ret = rockchip_mipi_parse_dt(dsi);
if (ret)
@@ -1274,6 +1287,8 @@ static int dw_mipi_dsi_bind(struct device *dev, struct device *master,
dev_set_drvdata(dev, dsi);
+ pm_runtime_enable(dev);
+
dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
dsi->dsi_host.dev = dev;
ret = mipi_dsi_host_register(&dsi->dsi_host);
@@ -1296,6 +1311,7 @@ static void dw_mipi_dsi_unbind(struct device *dev, struct device *master,
struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
mipi_dsi_host_unregister(&dsi->dsi_host);
+ pm_runtime_disable(dev);
clk_disable_unprepare(dsi->pllref_clk);
}
--
2.6.3
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [RESEND PATCH v7 7/7] drm/rockchip/dsi: add dw-mipi power domain support
@ 2017-02-20 8:02 ` Chris Zhong
0 siblings, 0 replies; 51+ messages in thread
From: Chris Zhong @ 2017-02-20 8:02 UTC (permalink / raw)
To: john, dianders, tfiga, heiko, yzq, mark.rutland, devicetree,
robh+dt, galak, pawel.moll, seanpaul
Cc: linux-kernel, dri-devel, linux-rockchip, Chris Zhong, linux-arm-kernel
Reference the power domain incase dw-mipi power down when
in use.
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index a653384..b32e4fc 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -12,6 +12,7 @@
#include <linux/math64.h>
#include <linux/module.h>
#include <linux/of_device.h>
+#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/mfd/syscon.h>
@@ -293,6 +294,7 @@ struct dw_mipi_dsi {
struct clk *pclk;
struct clk *phy_cfg_clk;
+ int dpms_mode;
unsigned int lane_mbps; /* per lane */
u32 channel;
u32 lanes;
@@ -960,6 +962,9 @@ static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
{
struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
+ if (dsi->dpms_mode != DRM_MODE_DPMS_ON)
+ return;
+
if (clk_prepare_enable(dsi->pclk)) {
dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
return;
@@ -971,7 +976,9 @@ static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
drm_panel_unprepare(dsi->panel);
dw_mipi_dsi_disable(dsi);
+ pm_runtime_put(dsi->dev);
clk_disable_unprepare(dsi->pclk);
+ dsi->dpms_mode = DRM_MODE_DPMS_OFF;
}
static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
@@ -987,11 +994,15 @@ static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
if (ret < 0)
return;
+ if (dsi->dpms_mode == DRM_MODE_DPMS_ON)
+ return;
+
if (clk_prepare_enable(dsi->pclk)) {
dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
return;
}
+ pm_runtime_get_sync(dsi->dev);
dw_mipi_dsi_init(dsi);
dw_mipi_dsi_dpi_config(dsi, mode);
dw_mipi_dsi_packet_handler_config(dsi);
@@ -1027,6 +1038,7 @@ static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
regmap_write(dsi->grf_regmap, pdata->grf_switch_reg, val);
dev_dbg(dsi->dev, "vop %s output to dsi0\n", (mux) ? "LIT" : "BIG");
+ dsi->dpms_mode = DRM_MODE_DPMS_ON;
}
static int
@@ -1194,6 +1206,7 @@ static int dw_mipi_dsi_bind(struct device *dev, struct device *master,
dsi->dev = dev;
dsi->pdata = pdata;
+ dsi->dpms_mode = DRM_MODE_DPMS_OFF;
ret = rockchip_mipi_parse_dt(dsi);
if (ret)
@@ -1274,6 +1287,8 @@ static int dw_mipi_dsi_bind(struct device *dev, struct device *master,
dev_set_drvdata(dev, dsi);
+ pm_runtime_enable(dev);
+
dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
dsi->dsi_host.dev = dev;
ret = mipi_dsi_host_register(&dsi->dsi_host);
@@ -1296,6 +1311,7 @@ static void dw_mipi_dsi_unbind(struct device *dev, struct device *master,
struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
mipi_dsi_host_unregister(&dsi->dsi_host);
+ pm_runtime_disable(dev);
clk_disable_unprepare(dsi->pllref_clk);
}
--
2.6.3
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [RESEND PATCH v7 7/7] drm/rockchip/dsi: add dw-mipi power domain support
@ 2017-02-20 8:02 ` Chris Zhong
0 siblings, 0 replies; 51+ messages in thread
From: Chris Zhong @ 2017-02-20 8:02 UTC (permalink / raw)
To: linux-arm-kernel
Reference the power domain incase dw-mipi power down when
in use.
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index a653384..b32e4fc 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -12,6 +12,7 @@
#include <linux/math64.h>
#include <linux/module.h>
#include <linux/of_device.h>
+#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/mfd/syscon.h>
@@ -293,6 +294,7 @@ struct dw_mipi_dsi {
struct clk *pclk;
struct clk *phy_cfg_clk;
+ int dpms_mode;
unsigned int lane_mbps; /* per lane */
u32 channel;
u32 lanes;
@@ -960,6 +962,9 @@ static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
{
struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
+ if (dsi->dpms_mode != DRM_MODE_DPMS_ON)
+ return;
+
if (clk_prepare_enable(dsi->pclk)) {
dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
return;
@@ -971,7 +976,9 @@ static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
drm_panel_unprepare(dsi->panel);
dw_mipi_dsi_disable(dsi);
+ pm_runtime_put(dsi->dev);
clk_disable_unprepare(dsi->pclk);
+ dsi->dpms_mode = DRM_MODE_DPMS_OFF;
}
static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
@@ -987,11 +994,15 @@ static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
if (ret < 0)
return;
+ if (dsi->dpms_mode == DRM_MODE_DPMS_ON)
+ return;
+
if (clk_prepare_enable(dsi->pclk)) {
dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
return;
}
+ pm_runtime_get_sync(dsi->dev);
dw_mipi_dsi_init(dsi);
dw_mipi_dsi_dpi_config(dsi, mode);
dw_mipi_dsi_packet_handler_config(dsi);
@@ -1027,6 +1038,7 @@ static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
regmap_write(dsi->grf_regmap, pdata->grf_switch_reg, val);
dev_dbg(dsi->dev, "vop %s output to dsi0\n", (mux) ? "LIT" : "BIG");
+ dsi->dpms_mode = DRM_MODE_DPMS_ON;
}
static int
@@ -1194,6 +1206,7 @@ static int dw_mipi_dsi_bind(struct device *dev, struct device *master,
dsi->dev = dev;
dsi->pdata = pdata;
+ dsi->dpms_mode = DRM_MODE_DPMS_OFF;
ret = rockchip_mipi_parse_dt(dsi);
if (ret)
@@ -1274,6 +1287,8 @@ static int dw_mipi_dsi_bind(struct device *dev, struct device *master,
dev_set_drvdata(dev, dsi);
+ pm_runtime_enable(dev);
+
dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
dsi->dsi_host.dev = dev;
ret = mipi_dsi_host_register(&dsi->dsi_host);
@@ -1296,6 +1311,7 @@ static void dw_mipi_dsi_unbind(struct device *dev, struct device *master,
struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
mipi_dsi_host_unregister(&dsi->dsi_host);
+ pm_runtime_disable(dev);
clk_disable_unprepare(dsi->pllref_clk);
}
--
2.6.3
^ permalink raw reply related [flat|nested] 51+ messages in thread
* Re: [RESEND PATCH v7 0/7] Rockchip dw-mipi-dsi driver
@ 2017-02-21 15:39 ` Sean Paul
0 siblings, 0 replies; 51+ messages in thread
From: Sean Paul @ 2017-02-21 15:39 UTC (permalink / raw)
To: Chris Zhong
Cc: john, dianders, tfiga, heiko, yzq, mark.rutland, devicetree,
robh+dt, galak, pawel.moll, seanpaul, linux-kernel, dri-devel,
linux-rockchip, linux-arm-kernel
On Mon, Feb 20, 2017 at 04:02:16PM +0800, Chris Zhong wrote:
> Hi all
>
> [Resend this v7 version series, since there are 5 mails have gone missing, last
> week]
>
> This version does not change the existing v6 patches, just to add the
> "bandwidth fix" patch back, since we really need it.
>
> This patch serial is for RK3399 MIPI DSI. The MIPI DSI controller of
> RK3399 is almost the same as RK3288, except a little bit of difference
> in phy clock controlling and port id selection register. These patches
> add RK3399 support and the power domain support.
>
> And these patches base on John Keeping's v3 patches[0], it fixes many bugs,
> they have been tested on rk3288 evb board.
Do we have an ETA on when John is planning on respinning his patchset based on
review feedback?
>
> [0]:
> [01/24] https://patchwork.kernel.org/patch/9544089
> [02/24] https://patchwork.kernel.org/patch/9544061
> [03/24] https://patchwork.kernel.org/patch/9544065
> [04/24] https://patchwork.kernel.org/patch/9544077
> [05/24] https://patchwork.kernel.org/patch/9544033
> [06/24] https://patchwork.kernel.org/patch/9544037
> [07/24] https://patchwork.kernel.org/patch/9544029
> [08/24] https://patchwork.kernel.org/patch/9544031
> [09/24] https://patchwork.kernel.org/patch/9544083
> [10/24] https://patchwork.kernel.org/patch/9544063
> [11/24] https://patchwork.kernel.org/patch/9544085
> [12/24] https://patchwork.kernel.org/patch/9544093
> [13/24] https://patchwork.kernel.org/patch/9544081
> [14/24] https://patchwork.kernel.org/patch/9544057
> [15/24] https://patchwork.kernel.org/patch/9544079
> [16/24] https://patchwork.kernel.org/patch/9544035
> [17/24] https://patchwork.kernel.org/patch/9544105
> [18/24] https://patchwork.kernel.org/patch/9544059
> [21/24] https://patchwork.kernel.org/patch/9544009
> [22/24] https://patchwork.kernel.org/patch/9544049
> [23/24] https://patchwork.kernel.org/patch/9544055
> [24/24] https://patchwork.kernel.org/patch/9544109
>
>
> Changes in v6:
> - no need check phy_cfg_clk before enable/disable
>
> Changes in v5:
> - check the error of phy_cfg_clk in dw_mipi_dsi_bind
>
> Changes in v4:
> - remove the unrelated change
>
> Changes in v3:
> - base on John Keeping's patch series
>
> Chris Zhong (7):
> dt-bindings: add rk3399 support for dw-mipi-rockchip
> drm/rockchip/dsi: dw-mipi: support RK3399 mipi dsi
> drm/rockchip/dsi: dw-mipi: correct the coding style
> drm/rockchip/dsi: remove mode_valid function
> dt-bindings: add power domain node for dw-mipi-rockchip
> drm/rockchip/dsi: fix insufficient bandwidth of some panel
> drm/rockchip/dsi: add dw-mipi power domain support
>
> .../display/rockchip/dw_mipi_dsi_rockchip.txt | 7 +-
> drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 160 ++++++++++++---------
> 2 files changed, 100 insertions(+), 67 deletions(-)
>
> --
> 2.6.3
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
--
Sean Paul, Software Engineer, Google / Chromium OS
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [RESEND PATCH v7 0/7] Rockchip dw-mipi-dsi driver
@ 2017-02-21 15:39 ` Sean Paul
0 siblings, 0 replies; 51+ messages in thread
From: Sean Paul @ 2017-02-21 15:39 UTC (permalink / raw)
To: Chris Zhong
Cc: john-HooS5bfzL4hWk0Htik3J/w, dianders-F7+t8E8rja9g9hUCZPvPmw,
tfiga-F7+t8E8rja9g9hUCZPvPmw, heiko-4mtYJXux2i+zQB+pC5nmwQ,
yzq-TNX95d0MmH7DzftRWevZcw, mark.rutland-5wv7dgnIgG8,
devicetree-u79uwXL29TY76Z2rM5mHXA,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, galak-sgV2jX0FEOL9JmXXK+q4OQ,
pawel.moll-5wv7dgnIgG8, seanpaul-F7+t8E8rja9g9hUCZPvPmw,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On Mon, Feb 20, 2017 at 04:02:16PM +0800, Chris Zhong wrote:
> Hi all
>
> [Resend this v7 version series, since there are 5 mails have gone missing, last
> week]
>
> This version does not change the existing v6 patches, just to add the
> "bandwidth fix" patch back, since we really need it.
>
> This patch serial is for RK3399 MIPI DSI. The MIPI DSI controller of
> RK3399 is almost the same as RK3288, except a little bit of difference
> in phy clock controlling and port id selection register. These patches
> add RK3399 support and the power domain support.
>
> And these patches base on John Keeping's v3 patches[0], it fixes many bugs,
> they have been tested on rk3288 evb board.
Do we have an ETA on when John is planning on respinning his patchset based on
review feedback?
>
> [0]:
> [01/24] https://patchwork.kernel.org/patch/9544089
> [02/24] https://patchwork.kernel.org/patch/9544061
> [03/24] https://patchwork.kernel.org/patch/9544065
> [04/24] https://patchwork.kernel.org/patch/9544077
> [05/24] https://patchwork.kernel.org/patch/9544033
> [06/24] https://patchwork.kernel.org/patch/9544037
> [07/24] https://patchwork.kernel.org/patch/9544029
> [08/24] https://patchwork.kernel.org/patch/9544031
> [09/24] https://patchwork.kernel.org/patch/9544083
> [10/24] https://patchwork.kernel.org/patch/9544063
> [11/24] https://patchwork.kernel.org/patch/9544085
> [12/24] https://patchwork.kernel.org/patch/9544093
> [13/24] https://patchwork.kernel.org/patch/9544081
> [14/24] https://patchwork.kernel.org/patch/9544057
> [15/24] https://patchwork.kernel.org/patch/9544079
> [16/24] https://patchwork.kernel.org/patch/9544035
> [17/24] https://patchwork.kernel.org/patch/9544105
> [18/24] https://patchwork.kernel.org/patch/9544059
> [21/24] https://patchwork.kernel.org/patch/9544009
> [22/24] https://patchwork.kernel.org/patch/9544049
> [23/24] https://patchwork.kernel.org/patch/9544055
> [24/24] https://patchwork.kernel.org/patch/9544109
>
>
> Changes in v6:
> - no need check phy_cfg_clk before enable/disable
>
> Changes in v5:
> - check the error of phy_cfg_clk in dw_mipi_dsi_bind
>
> Changes in v4:
> - remove the unrelated change
>
> Changes in v3:
> - base on John Keeping's patch series
>
> Chris Zhong (7):
> dt-bindings: add rk3399 support for dw-mipi-rockchip
> drm/rockchip/dsi: dw-mipi: support RK3399 mipi dsi
> drm/rockchip/dsi: dw-mipi: correct the coding style
> drm/rockchip/dsi: remove mode_valid function
> dt-bindings: add power domain node for dw-mipi-rockchip
> drm/rockchip/dsi: fix insufficient bandwidth of some panel
> drm/rockchip/dsi: add dw-mipi power domain support
>
> .../display/rockchip/dw_mipi_dsi_rockchip.txt | 7 +-
> drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 160 ++++++++++++---------
> 2 files changed, 100 insertions(+), 67 deletions(-)
>
> --
> 2.6.3
>
> _______________________________________________
> dri-devel mailing list
> dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
--
Sean Paul, Software Engineer, Google / Chromium OS
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 51+ messages in thread
* [RESEND PATCH v7 0/7] Rockchip dw-mipi-dsi driver
@ 2017-02-21 15:39 ` Sean Paul
0 siblings, 0 replies; 51+ messages in thread
From: Sean Paul @ 2017-02-21 15:39 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Feb 20, 2017 at 04:02:16PM +0800, Chris Zhong wrote:
> Hi all
>
> [Resend this v7 version series, since there are 5 mails have gone missing, last
> week]
>
> This version does not change the existing v6 patches, just to add the
> "bandwidth fix" patch back, since we really need it.
>
> This patch serial is for RK3399 MIPI DSI. The MIPI DSI controller of
> RK3399 is almost the same as RK3288, except a little bit of difference
> in phy clock controlling and port id selection register. These patches
> add RK3399 support and the power domain support.
>
> And these patches base on John Keeping's v3 patches[0], it fixes many bugs,
> they have been tested on rk3288 evb board.
Do we have an ETA on when John is planning on respinning his patchset based on
review feedback?
>
> [0]:
> [01/24] https://patchwork.kernel.org/patch/9544089
> [02/24] https://patchwork.kernel.org/patch/9544061
> [03/24] https://patchwork.kernel.org/patch/9544065
> [04/24] https://patchwork.kernel.org/patch/9544077
> [05/24] https://patchwork.kernel.org/patch/9544033
> [06/24] https://patchwork.kernel.org/patch/9544037
> [07/24] https://patchwork.kernel.org/patch/9544029
> [08/24] https://patchwork.kernel.org/patch/9544031
> [09/24] https://patchwork.kernel.org/patch/9544083
> [10/24] https://patchwork.kernel.org/patch/9544063
> [11/24] https://patchwork.kernel.org/patch/9544085
> [12/24] https://patchwork.kernel.org/patch/9544093
> [13/24] https://patchwork.kernel.org/patch/9544081
> [14/24] https://patchwork.kernel.org/patch/9544057
> [15/24] https://patchwork.kernel.org/patch/9544079
> [16/24] https://patchwork.kernel.org/patch/9544035
> [17/24] https://patchwork.kernel.org/patch/9544105
> [18/24] https://patchwork.kernel.org/patch/9544059
> [21/24] https://patchwork.kernel.org/patch/9544009
> [22/24] https://patchwork.kernel.org/patch/9544049
> [23/24] https://patchwork.kernel.org/patch/9544055
> [24/24] https://patchwork.kernel.org/patch/9544109
>
>
> Changes in v6:
> - no need check phy_cfg_clk before enable/disable
>
> Changes in v5:
> - check the error of phy_cfg_clk in dw_mipi_dsi_bind
>
> Changes in v4:
> - remove the unrelated change
>
> Changes in v3:
> - base on John Keeping's patch series
>
> Chris Zhong (7):
> dt-bindings: add rk3399 support for dw-mipi-rockchip
> drm/rockchip/dsi: dw-mipi: support RK3399 mipi dsi
> drm/rockchip/dsi: dw-mipi: correct the coding style
> drm/rockchip/dsi: remove mode_valid function
> dt-bindings: add power domain node for dw-mipi-rockchip
> drm/rockchip/dsi: fix insufficient bandwidth of some panel
> drm/rockchip/dsi: add dw-mipi power domain support
>
> .../display/rockchip/dw_mipi_dsi_rockchip.txt | 7 +-
> drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 160 ++++++++++++---------
> 2 files changed, 100 insertions(+), 67 deletions(-)
>
> --
> 2.6.3
>
> _______________________________________________
> dri-devel mailing list
> dri-devel at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
--
Sean Paul, Software Engineer, Google / Chromium OS
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [RESEND PATCH v7 6/7] drm/rockchip/dsi: fix insufficient bandwidth of some panel
2017-02-20 8:02 ` Chris Zhong
(?)
@ 2017-02-21 15:40 ` Sean Paul
-1 siblings, 0 replies; 51+ messages in thread
From: Sean Paul @ 2017-02-21 15:40 UTC (permalink / raw)
To: Chris Zhong
Cc: john, dianders, tfiga, heiko, yzq, mark.rutland, devicetree,
robh+dt, galak, pawel.moll, seanpaul, linux-kernel, dri-devel,
linux-rockchip, linux-arm-kernel
On Mon, Feb 20, 2017 at 04:02:22PM +0800, Chris Zhong wrote:
> Set the lanes bps to 1 / 0.9 times of pclk, the margin is not enough
> for some panel, it will cause the screen display is not normal, so
> increases the badnwidth to 1 / 0.8.
>
> Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
> ---
>
> Changes in v6: None
> Changes in v5: None
> Changes in v4: None
> Changes in v3: None
>
> drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> index c2d7674..a653384 100644
> --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> @@ -532,8 +532,8 @@ static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi,
>
> mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC);
> if (mpclk) {
> - /* take 1 / 0.9, since mbps must big than bandwidth of RGB */
> - tmp = mpclk * (bpp / dsi->lanes) * 10 / 9;
> + /* take 1 / 0.8, since mbps must big than bandwidth of RGB */
> + tmp = mpclk * (bpp / dsi->lanes) * 10 / 8;
> if (tmp < max_mbps)
> target_mbps = tmp;
> else
> --
> 2.6.3
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
--
Sean Paul, Software Engineer, Google / Chromium OS
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [RESEND PATCH v7 6/7] drm/rockchip/dsi: fix insufficient bandwidth of some panel
@ 2017-02-21 15:40 ` Sean Paul
0 siblings, 0 replies; 51+ messages in thread
From: Sean Paul @ 2017-02-21 15:40 UTC (permalink / raw)
To: Chris Zhong
Cc: mark.rutland, devicetree, pawel.moll, yzq, linux-kernel,
dianders, dri-devel, tfiga, linux-rockchip, robh+dt, galak,
linux-arm-kernel
On Mon, Feb 20, 2017 at 04:02:22PM +0800, Chris Zhong wrote:
> Set the lanes bps to 1 / 0.9 times of pclk, the margin is not enough
> for some panel, it will cause the screen display is not normal, so
> increases the badnwidth to 1 / 0.8.
>
> Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
> ---
>
> Changes in v6: None
> Changes in v5: None
> Changes in v4: None
> Changes in v3: None
>
> drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> index c2d7674..a653384 100644
> --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> @@ -532,8 +532,8 @@ static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi,
>
> mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC);
> if (mpclk) {
> - /* take 1 / 0.9, since mbps must big than bandwidth of RGB */
> - tmp = mpclk * (bpp / dsi->lanes) * 10 / 9;
> + /* take 1 / 0.8, since mbps must big than bandwidth of RGB */
> + tmp = mpclk * (bpp / dsi->lanes) * 10 / 8;
> if (tmp < max_mbps)
> target_mbps = tmp;
> else
> --
> 2.6.3
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
--
Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 51+ messages in thread
* [RESEND PATCH v7 6/7] drm/rockchip/dsi: fix insufficient bandwidth of some panel
@ 2017-02-21 15:40 ` Sean Paul
0 siblings, 0 replies; 51+ messages in thread
From: Sean Paul @ 2017-02-21 15:40 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Feb 20, 2017 at 04:02:22PM +0800, Chris Zhong wrote:
> Set the lanes bps to 1 / 0.9 times of pclk, the margin is not enough
> for some panel, it will cause the screen display is not normal, so
> increases the badnwidth to 1 / 0.8.
>
> Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
> ---
>
> Changes in v6: None
> Changes in v5: None
> Changes in v4: None
> Changes in v3: None
>
> drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> index c2d7674..a653384 100644
> --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> @@ -532,8 +532,8 @@ static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi,
>
> mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC);
> if (mpclk) {
> - /* take 1 / 0.9, since mbps must big than bandwidth of RGB */
> - tmp = mpclk * (bpp / dsi->lanes) * 10 / 9;
> + /* take 1 / 0.8, since mbps must big than bandwidth of RGB */
> + tmp = mpclk * (bpp / dsi->lanes) * 10 / 8;
> if (tmp < max_mbps)
> target_mbps = tmp;
> else
> --
> 2.6.3
>
> _______________________________________________
> dri-devel mailing list
> dri-devel at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
--
Sean Paul, Software Engineer, Google / Chromium OS
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [RESEND PATCH v7 0/7] Rockchip dw-mipi-dsi driver
2017-02-21 15:39 ` Sean Paul
(?)
@ 2017-02-22 1:44 ` Chris Zhong
-1 siblings, 0 replies; 51+ messages in thread
From: Chris Zhong @ 2017-02-22 1:44 UTC (permalink / raw)
To: Sean Paul
Cc: john, dianders, tfiga, heiko, yzq, mark.rutland, devicetree,
robh+dt, galak, pawel.moll, linux-kernel, dri-devel,
linux-rockchip, linux-arm-kernel
Hi Sean
On 02/21/2017 11:39 PM, Sean Paul wrote:
> On Mon, Feb 20, 2017 at 04:02:16PM +0800, Chris Zhong wrote:
>> Hi all
>>
>> [Resend this v7 version series, since there are 5 mails have gone missing, last
>> week]
>>
>> This version does not change the existing v6 patches, just to add the
>> "bandwidth fix" patch back, since we really need it.
>>
>> This patch serial is for RK3399 MIPI DSI. The MIPI DSI controller of
>> RK3399 is almost the same as RK3288, except a little bit of difference
>> in phy clock controlling and port id selection register. These patches
>> add RK3399 support and the power domain support.
>>
>> And these patches base on John Keeping's v3 patches[0], it fixes many bugs,
>> they have been tested on rk3288 evb board.
> Do we have an ETA on when John is planning on respinning his patchset based on
> review feedback?
>
I guess John will send the v4 patch soon, since there are not many point
need to change.
And as I know, Mark Yao is going to merge John's v4 series to his
branch, and this v7 series
will be merged after that.
>> [0]:
>> [01/24] https://patchwork.kernel.org/patch/9544089
>> [02/24] https://patchwork.kernel.org/patch/9544061
>> [03/24] https://patchwork.kernel.org/patch/9544065
>> [04/24] https://patchwork.kernel.org/patch/9544077
>> [05/24] https://patchwork.kernel.org/patch/9544033
>> [06/24] https://patchwork.kernel.org/patch/9544037
>> [07/24] https://patchwork.kernel.org/patch/9544029
>> [08/24] https://patchwork.kernel.org/patch/9544031
>> [09/24] https://patchwork.kernel.org/patch/9544083
>> [10/24] https://patchwork.kernel.org/patch/9544063
>> [11/24] https://patchwork.kernel.org/patch/9544085
>> [12/24] https://patchwork.kernel.org/patch/9544093
>> [13/24] https://patchwork.kernel.org/patch/9544081
>> [14/24] https://patchwork.kernel.org/patch/9544057
>> [15/24] https://patchwork.kernel.org/patch/9544079
>> [16/24] https://patchwork.kernel.org/patch/9544035
>> [17/24] https://patchwork.kernel.org/patch/9544105
>> [18/24] https://patchwork.kernel.org/patch/9544059
>> [21/24] https://patchwork.kernel.org/patch/9544009
>> [22/24] https://patchwork.kernel.org/patch/9544049
>> [23/24] https://patchwork.kernel.org/patch/9544055
>> [24/24] https://patchwork.kernel.org/patch/9544109
>>
>>
>> Changes in v6:
>> - no need check phy_cfg_clk before enable/disable
>>
>> Changes in v5:
>> - check the error of phy_cfg_clk in dw_mipi_dsi_bind
>>
>> Changes in v4:
>> - remove the unrelated change
>>
>> Changes in v3:
>> - base on John Keeping's patch series
>>
>> Chris Zhong (7):
>> dt-bindings: add rk3399 support for dw-mipi-rockchip
>> drm/rockchip/dsi: dw-mipi: support RK3399 mipi dsi
>> drm/rockchip/dsi: dw-mipi: correct the coding style
>> drm/rockchip/dsi: remove mode_valid function
>> dt-bindings: add power domain node for dw-mipi-rockchip
>> drm/rockchip/dsi: fix insufficient bandwidth of some panel
>> drm/rockchip/dsi: add dw-mipi power domain support
>>
>> .../display/rockchip/dw_mipi_dsi_rockchip.txt | 7 +-
>> drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 160 ++++++++++++---------
>> 2 files changed, 100 insertions(+), 67 deletions(-)
>>
>> --
>> 2.6.3
>>
>> _______________________________________________
>> dri-devel mailing list
>> dri-devel@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/dri-devel
--
Chris Zhong
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [RESEND PATCH v7 0/7] Rockchip dw-mipi-dsi driver
@ 2017-02-22 1:44 ` Chris Zhong
0 siblings, 0 replies; 51+ messages in thread
From: Chris Zhong @ 2017-02-22 1:44 UTC (permalink / raw)
To: Sean Paul
Cc: mark.rutland, devicetree, pawel.moll, yzq, linux-kernel,
dianders, dri-devel, tfiga, linux-rockchip, robh+dt, galak,
linux-arm-kernel
Hi Sean
On 02/21/2017 11:39 PM, Sean Paul wrote:
> On Mon, Feb 20, 2017 at 04:02:16PM +0800, Chris Zhong wrote:
>> Hi all
>>
>> [Resend this v7 version series, since there are 5 mails have gone missing, last
>> week]
>>
>> This version does not change the existing v6 patches, just to add the
>> "bandwidth fix" patch back, since we really need it.
>>
>> This patch serial is for RK3399 MIPI DSI. The MIPI DSI controller of
>> RK3399 is almost the same as RK3288, except a little bit of difference
>> in phy clock controlling and port id selection register. These patches
>> add RK3399 support and the power domain support.
>>
>> And these patches base on John Keeping's v3 patches[0], it fixes many bugs,
>> they have been tested on rk3288 evb board.
> Do we have an ETA on when John is planning on respinning his patchset based on
> review feedback?
>
I guess John will send the v4 patch soon, since there are not many point
need to change.
And as I know, Mark Yao is going to merge John's v4 series to his
branch, and this v7 series
will be merged after that.
>> [0]:
>> [01/24] https://patchwork.kernel.org/patch/9544089
>> [02/24] https://patchwork.kernel.org/patch/9544061
>> [03/24] https://patchwork.kernel.org/patch/9544065
>> [04/24] https://patchwork.kernel.org/patch/9544077
>> [05/24] https://patchwork.kernel.org/patch/9544033
>> [06/24] https://patchwork.kernel.org/patch/9544037
>> [07/24] https://patchwork.kernel.org/patch/9544029
>> [08/24] https://patchwork.kernel.org/patch/9544031
>> [09/24] https://patchwork.kernel.org/patch/9544083
>> [10/24] https://patchwork.kernel.org/patch/9544063
>> [11/24] https://patchwork.kernel.org/patch/9544085
>> [12/24] https://patchwork.kernel.org/patch/9544093
>> [13/24] https://patchwork.kernel.org/patch/9544081
>> [14/24] https://patchwork.kernel.org/patch/9544057
>> [15/24] https://patchwork.kernel.org/patch/9544079
>> [16/24] https://patchwork.kernel.org/patch/9544035
>> [17/24] https://patchwork.kernel.org/patch/9544105
>> [18/24] https://patchwork.kernel.org/patch/9544059
>> [21/24] https://patchwork.kernel.org/patch/9544009
>> [22/24] https://patchwork.kernel.org/patch/9544049
>> [23/24] https://patchwork.kernel.org/patch/9544055
>> [24/24] https://patchwork.kernel.org/patch/9544109
>>
>>
>> Changes in v6:
>> - no need check phy_cfg_clk before enable/disable
>>
>> Changes in v5:
>> - check the error of phy_cfg_clk in dw_mipi_dsi_bind
>>
>> Changes in v4:
>> - remove the unrelated change
>>
>> Changes in v3:
>> - base on John Keeping's patch series
>>
>> Chris Zhong (7):
>> dt-bindings: add rk3399 support for dw-mipi-rockchip
>> drm/rockchip/dsi: dw-mipi: support RK3399 mipi dsi
>> drm/rockchip/dsi: dw-mipi: correct the coding style
>> drm/rockchip/dsi: remove mode_valid function
>> dt-bindings: add power domain node for dw-mipi-rockchip
>> drm/rockchip/dsi: fix insufficient bandwidth of some panel
>> drm/rockchip/dsi: add dw-mipi power domain support
>>
>> .../display/rockchip/dw_mipi_dsi_rockchip.txt | 7 +-
>> drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 160 ++++++++++++---------
>> 2 files changed, 100 insertions(+), 67 deletions(-)
>>
>> --
>> 2.6.3
>>
>> _______________________________________________
>> dri-devel mailing list
>> dri-devel@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/dri-devel
--
Chris Zhong
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 51+ messages in thread
* [RESEND PATCH v7 0/7] Rockchip dw-mipi-dsi driver
@ 2017-02-22 1:44 ` Chris Zhong
0 siblings, 0 replies; 51+ messages in thread
From: Chris Zhong @ 2017-02-22 1:44 UTC (permalink / raw)
To: linux-arm-kernel
Hi Sean
On 02/21/2017 11:39 PM, Sean Paul wrote:
> On Mon, Feb 20, 2017 at 04:02:16PM +0800, Chris Zhong wrote:
>> Hi all
>>
>> [Resend this v7 version series, since there are 5 mails have gone missing, last
>> week]
>>
>> This version does not change the existing v6 patches, just to add the
>> "bandwidth fix" patch back, since we really need it.
>>
>> This patch serial is for RK3399 MIPI DSI. The MIPI DSI controller of
>> RK3399 is almost the same as RK3288, except a little bit of difference
>> in phy clock controlling and port id selection register. These patches
>> add RK3399 support and the power domain support.
>>
>> And these patches base on John Keeping's v3 patches[0], it fixes many bugs,
>> they have been tested on rk3288 evb board.
> Do we have an ETA on when John is planning on respinning his patchset based on
> review feedback?
>
I guess John will send the v4 patch soon, since there are not many point
need to change.
And as I know, Mark Yao is going to merge John's v4 series to his
branch, and this v7 series
will be merged after that.
>> [0]:
>> [01/24] https://patchwork.kernel.org/patch/9544089
>> [02/24] https://patchwork.kernel.org/patch/9544061
>> [03/24] https://patchwork.kernel.org/patch/9544065
>> [04/24] https://patchwork.kernel.org/patch/9544077
>> [05/24] https://patchwork.kernel.org/patch/9544033
>> [06/24] https://patchwork.kernel.org/patch/9544037
>> [07/24] https://patchwork.kernel.org/patch/9544029
>> [08/24] https://patchwork.kernel.org/patch/9544031
>> [09/24] https://patchwork.kernel.org/patch/9544083
>> [10/24] https://patchwork.kernel.org/patch/9544063
>> [11/24] https://patchwork.kernel.org/patch/9544085
>> [12/24] https://patchwork.kernel.org/patch/9544093
>> [13/24] https://patchwork.kernel.org/patch/9544081
>> [14/24] https://patchwork.kernel.org/patch/9544057
>> [15/24] https://patchwork.kernel.org/patch/9544079
>> [16/24] https://patchwork.kernel.org/patch/9544035
>> [17/24] https://patchwork.kernel.org/patch/9544105
>> [18/24] https://patchwork.kernel.org/patch/9544059
>> [21/24] https://patchwork.kernel.org/patch/9544009
>> [22/24] https://patchwork.kernel.org/patch/9544049
>> [23/24] https://patchwork.kernel.org/patch/9544055
>> [24/24] https://patchwork.kernel.org/patch/9544109
>>
>>
>> Changes in v6:
>> - no need check phy_cfg_clk before enable/disable
>>
>> Changes in v5:
>> - check the error of phy_cfg_clk in dw_mipi_dsi_bind
>>
>> Changes in v4:
>> - remove the unrelated change
>>
>> Changes in v3:
>> - base on John Keeping's patch series
>>
>> Chris Zhong (7):
>> dt-bindings: add rk3399 support for dw-mipi-rockchip
>> drm/rockchip/dsi: dw-mipi: support RK3399 mipi dsi
>> drm/rockchip/dsi: dw-mipi: correct the coding style
>> drm/rockchip/dsi: remove mode_valid function
>> dt-bindings: add power domain node for dw-mipi-rockchip
>> drm/rockchip/dsi: fix insufficient bandwidth of some panel
>> drm/rockchip/dsi: add dw-mipi power domain support
>>
>> .../display/rockchip/dw_mipi_dsi_rockchip.txt | 7 +-
>> drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 160 ++++++++++++---------
>> 2 files changed, 100 insertions(+), 67 deletions(-)
>>
>> --
>> 2.6.3
>>
>> _______________________________________________
>> dri-devel mailing list
>> dri-devel at lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/dri-devel
--
Chris Zhong
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [RESEND PATCH v7 0/7] Rockchip dw-mipi-dsi driver
2017-02-21 15:39 ` Sean Paul
(?)
@ 2017-02-22 13:43 ` John Keeping
-1 siblings, 0 replies; 51+ messages in thread
From: John Keeping @ 2017-02-22 13:43 UTC (permalink / raw)
To: Sean Paul
Cc: Chris Zhong, dianders, tfiga, heiko, yzq, mark.rutland,
devicetree, robh+dt, galak, pawel.moll, linux-kernel, dri-devel,
linux-rockchip, linux-arm-kernel
On Tue, 21 Feb 2017 10:39:18 -0500, Sean Paul wrote:
> On Mon, Feb 20, 2017 at 04:02:16PM +0800, Chris Zhong wrote:
> > Hi all
> >
> > [Resend this v7 version series, since there are 5 mails have gone missing, last
> > week]
> >
> > This version does not change the existing v6 patches, just to add the
> > "bandwidth fix" patch back, since we really need it.
> >
> > This patch serial is for RK3399 MIPI DSI. The MIPI DSI controller of
> > RK3399 is almost the same as RK3288, except a little bit of difference
> > in phy clock controlling and port id selection register. These patches
> > add RK3399 support and the power domain support.
> >
> > And these patches base on John Keeping's v3 patches[0], it fixes many bugs,
> > they have been tested on rk3288 evb board.
>
> Do we have an ETA on when John is planning on respinning his patchset based on
> review feedback?
I have all of the changes queued but I was hoping to find some time to
test the latest version before sending it out; unfortunately everything
else is more important at the moment. If you're happy with the caveat
that the latest changes are build tested only I can probably send it
out this afternoon.
John
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [RESEND PATCH v7 0/7] Rockchip dw-mipi-dsi driver
@ 2017-02-22 13:43 ` John Keeping
0 siblings, 0 replies; 51+ messages in thread
From: John Keeping @ 2017-02-22 13:43 UTC (permalink / raw)
To: Sean Paul
Cc: mark.rutland, devicetree, pawel.moll, yzq, linux-kernel,
dianders, dri-devel, tfiga, linux-rockchip, robh+dt, galak,
Chris Zhong, linux-arm-kernel
On Tue, 21 Feb 2017 10:39:18 -0500, Sean Paul wrote:
> On Mon, Feb 20, 2017 at 04:02:16PM +0800, Chris Zhong wrote:
> > Hi all
> >
> > [Resend this v7 version series, since there are 5 mails have gone missing, last
> > week]
> >
> > This version does not change the existing v6 patches, just to add the
> > "bandwidth fix" patch back, since we really need it.
> >
> > This patch serial is for RK3399 MIPI DSI. The MIPI DSI controller of
> > RK3399 is almost the same as RK3288, except a little bit of difference
> > in phy clock controlling and port id selection register. These patches
> > add RK3399 support and the power domain support.
> >
> > And these patches base on John Keeping's v3 patches[0], it fixes many bugs,
> > they have been tested on rk3288 evb board.
>
> Do we have an ETA on when John is planning on respinning his patchset based on
> review feedback?
I have all of the changes queued but I was hoping to find some time to
test the latest version before sending it out; unfortunately everything
else is more important at the moment. If you're happy with the caveat
that the latest changes are build tested only I can probably send it
out this afternoon.
John
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 51+ messages in thread
* [RESEND PATCH v7 0/7] Rockchip dw-mipi-dsi driver
@ 2017-02-22 13:43 ` John Keeping
0 siblings, 0 replies; 51+ messages in thread
From: John Keeping @ 2017-02-22 13:43 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, 21 Feb 2017 10:39:18 -0500, Sean Paul wrote:
> On Mon, Feb 20, 2017 at 04:02:16PM +0800, Chris Zhong wrote:
> > Hi all
> >
> > [Resend this v7 version series, since there are 5 mails have gone missing, last
> > week]
> >
> > This version does not change the existing v6 patches, just to add the
> > "bandwidth fix" patch back, since we really need it.
> >
> > This patch serial is for RK3399 MIPI DSI. The MIPI DSI controller of
> > RK3399 is almost the same as RK3288, except a little bit of difference
> > in phy clock controlling and port id selection register. These patches
> > add RK3399 support and the power domain support.
> >
> > And these patches base on John Keeping's v3 patches[0], it fixes many bugs,
> > they have been tested on rk3288 evb board.
>
> Do we have an ETA on when John is planning on respinning his patchset based on
> review feedback?
I have all of the changes queued but I was hoping to find some time to
test the latest version before sending it out; unfortunately everything
else is more important at the moment. If you're happy with the caveat
that the latest changes are build tested only I can probably send it
out this afternoon.
John
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [RESEND PATCH v7 0/7] Rockchip dw-mipi-dsi driver
@ 2017-02-22 15:57 ` Sean Paul
0 siblings, 0 replies; 51+ messages in thread
From: Sean Paul @ 2017-02-22 15:57 UTC (permalink / raw)
To: John Keeping
Cc: Chris Zhong, Doug Anderson, Tomasz Figa, Heiko Stuebner,
Mark Yao, Mark Rutland, devicetree, Rob Herring, Kumar Gala,
Pawel Moll, Linux Kernel Mailing List, dri-devel, linux-rockchip,
Linux ARM Kernel
On Wed, Feb 22, 2017 at 8:43 AM, John Keeping <john@metanate.com> wrote:
> On Tue, 21 Feb 2017 10:39:18 -0500, Sean Paul wrote:
>
>> On Mon, Feb 20, 2017 at 04:02:16PM +0800, Chris Zhong wrote:
>> > Hi all
>> >
>> > [Resend this v7 version series, since there are 5 mails have gone missing, last
>> > week]
>> >
>> > This version does not change the existing v6 patches, just to add the
>> > "bandwidth fix" patch back, since we really need it.
>> >
>> > This patch serial is for RK3399 MIPI DSI. The MIPI DSI controller of
>> > RK3399 is almost the same as RK3288, except a little bit of difference
>> > in phy clock controlling and port id selection register. These patches
>> > add RK3399 support and the power domain support.
>> >
>> > And these patches base on John Keeping's v3 patches[0], it fixes many bugs,
>> > they have been tested on rk3288 evb board.
>>
>> Do we have an ETA on when John is planning on respinning his patchset based on
>> review feedback?
>
> I have all of the changes queued but I was hoping to find some time to
> test the latest version before sending it out; unfortunately everything
> else is more important at the moment. If you're happy with the caveat
> that the latest changes are build tested only I can probably send it
> out this afternoon.
I suppose my answer depends on when the tested version will be
available, or perhaps Chris can test the new set for you? I don't have
any rockchip devices with mipi, so i'm not much help.
Sean
>
>
> John
--
Sean Paul, Software Engineer, Google / Chromium OS
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [RESEND PATCH v7 0/7] Rockchip dw-mipi-dsi driver
@ 2017-02-22 15:57 ` Sean Paul
0 siblings, 0 replies; 51+ messages in thread
From: Sean Paul @ 2017-02-22 15:57 UTC (permalink / raw)
To: John Keeping
Cc: Chris Zhong, Doug Anderson, Tomasz Figa, Heiko Stuebner,
Mark Yao, Mark Rutland, devicetree-u79uwXL29TY76Z2rM5mHXA,
Rob Herring, Kumar Gala, Pawel Moll, Linux Kernel Mailing List,
dri-devel, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Linux ARM Kernel
On Wed, Feb 22, 2017 at 8:43 AM, John Keeping <john-HooS5bfzL4hWk0Htik3J/w@public.gmane.org> wrote:
> On Tue, 21 Feb 2017 10:39:18 -0500, Sean Paul wrote:
>
>> On Mon, Feb 20, 2017 at 04:02:16PM +0800, Chris Zhong wrote:
>> > Hi all
>> >
>> > [Resend this v7 version series, since there are 5 mails have gone missing, last
>> > week]
>> >
>> > This version does not change the existing v6 patches, just to add the
>> > "bandwidth fix" patch back, since we really need it.
>> >
>> > This patch serial is for RK3399 MIPI DSI. The MIPI DSI controller of
>> > RK3399 is almost the same as RK3288, except a little bit of difference
>> > in phy clock controlling and port id selection register. These patches
>> > add RK3399 support and the power domain support.
>> >
>> > And these patches base on John Keeping's v3 patches[0], it fixes many bugs,
>> > they have been tested on rk3288 evb board.
>>
>> Do we have an ETA on when John is planning on respinning his patchset based on
>> review feedback?
>
> I have all of the changes queued but I was hoping to find some time to
> test the latest version before sending it out; unfortunately everything
> else is more important at the moment. If you're happy with the caveat
> that the latest changes are build tested only I can probably send it
> out this afternoon.
I suppose my answer depends on when the tested version will be
available, or perhaps Chris can test the new set for you? I don't have
any rockchip devices with mipi, so i'm not much help.
Sean
>
>
> John
--
Sean Paul, Software Engineer, Google / Chromium OS
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 51+ messages in thread
* [RESEND PATCH v7 0/7] Rockchip dw-mipi-dsi driver
@ 2017-02-22 15:57 ` Sean Paul
0 siblings, 0 replies; 51+ messages in thread
From: Sean Paul @ 2017-02-22 15:57 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Feb 22, 2017 at 8:43 AM, John Keeping <john@metanate.com> wrote:
> On Tue, 21 Feb 2017 10:39:18 -0500, Sean Paul wrote:
>
>> On Mon, Feb 20, 2017 at 04:02:16PM +0800, Chris Zhong wrote:
>> > Hi all
>> >
>> > [Resend this v7 version series, since there are 5 mails have gone missing, last
>> > week]
>> >
>> > This version does not change the existing v6 patches, just to add the
>> > "bandwidth fix" patch back, since we really need it.
>> >
>> > This patch serial is for RK3399 MIPI DSI. The MIPI DSI controller of
>> > RK3399 is almost the same as RK3288, except a little bit of difference
>> > in phy clock controlling and port id selection register. These patches
>> > add RK3399 support and the power domain support.
>> >
>> > And these patches base on John Keeping's v3 patches[0], it fixes many bugs,
>> > they have been tested on rk3288 evb board.
>>
>> Do we have an ETA on when John is planning on respinning his patchset based on
>> review feedback?
>
> I have all of the changes queued but I was hoping to find some time to
> test the latest version before sending it out; unfortunately everything
> else is more important at the moment. If you're happy with the caveat
> that the latest changes are build tested only I can probably send it
> out this afternoon.
I suppose my answer depends on when the tested version will be
available, or perhaps Chris can test the new set for you? I don't have
any rockchip devices with mipi, so i'm not much help.
Sean
>
>
> John
--
Sean Paul, Software Engineer, Google / Chromium OS
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [RESEND PATCH v7 0/7] Rockchip dw-mipi-dsi driver
@ 2017-02-22 18:55 ` John Keeping
0 siblings, 0 replies; 51+ messages in thread
From: John Keeping @ 2017-02-22 18:55 UTC (permalink / raw)
To: Sean Paul
Cc: Chris Zhong, Doug Anderson, Tomasz Figa, Heiko Stuebner,
Mark Yao, Mark Rutland, devicetree, Rob Herring, Kumar Gala,
Pawel Moll, Linux Kernel Mailing List, dri-devel, linux-rockchip,
Linux ARM Kernel
On Wed, 22 Feb 2017 10:57:05 -0500, Sean Paul wrote:
> On Wed, Feb 22, 2017 at 8:43 AM, John Keeping <john@metanate.com> wrote:
> > On Tue, 21 Feb 2017 10:39:18 -0500, Sean Paul wrote:
> >
> >> On Mon, Feb 20, 2017 at 04:02:16PM +0800, Chris Zhong wrote:
> >> > Hi all
> >> >
> >> > [Resend this v7 version series, since there are 5 mails have gone missing, last
> >> > week]
> >> >
> >> > This version does not change the existing v6 patches, just to add the
> >> > "bandwidth fix" patch back, since we really need it.
> >> >
> >> > This patch serial is for RK3399 MIPI DSI. The MIPI DSI controller of
> >> > RK3399 is almost the same as RK3288, except a little bit of difference
> >> > in phy clock controlling and port id selection register. These patches
> >> > add RK3399 support and the power domain support.
> >> >
> >> > And these patches base on John Keeping's v3 patches[0], it fixes many bugs,
> >> > they have been tested on rk3288 evb board.
> >>
> >> Do we have an ETA on when John is planning on respinning his patchset based on
> >> review feedback?
> >
> > I have all of the changes queued but I was hoping to find some time to
> > test the latest version before sending it out; unfortunately everything
> > else is more important at the moment. If you're happy with the caveat
> > that the latest changes are build tested only I can probably send it
> > out this afternoon.
>
> I suppose my answer depends on when the tested version will be
> available, or perhaps Chris can test the new set for you? I don't have
> any rockchip devices with mipi, so i'm not much help.
None of the changes scare me that much, so I don't expect testing to
throw up any problems but I don't like throwing out patches without at
least a basic test run.
I might have time to test on Friday, but I expect Chris has more time to
devote to this than I do, so maybe it's better if I send the patches out
tomorrow.
John
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [RESEND PATCH v7 0/7] Rockchip dw-mipi-dsi driver
@ 2017-02-22 18:55 ` John Keeping
0 siblings, 0 replies; 51+ messages in thread
From: John Keeping @ 2017-02-22 18:55 UTC (permalink / raw)
To: Sean Paul
Cc: Chris Zhong, Doug Anderson, Tomasz Figa, Heiko Stuebner,
Mark Yao, Mark Rutland, devicetree-u79uwXL29TY76Z2rM5mHXA,
Rob Herring, Kumar Gala, Pawel Moll, Linux Kernel Mailing List,
dri-devel, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Linux ARM Kernel
On Wed, 22 Feb 2017 10:57:05 -0500, Sean Paul wrote:
> On Wed, Feb 22, 2017 at 8:43 AM, John Keeping <john-HooS5bfzL4hWk0Htik3J/w@public.gmane.org> wrote:
> > On Tue, 21 Feb 2017 10:39:18 -0500, Sean Paul wrote:
> >
> >> On Mon, Feb 20, 2017 at 04:02:16PM +0800, Chris Zhong wrote:
> >> > Hi all
> >> >
> >> > [Resend this v7 version series, since there are 5 mails have gone missing, last
> >> > week]
> >> >
> >> > This version does not change the existing v6 patches, just to add the
> >> > "bandwidth fix" patch back, since we really need it.
> >> >
> >> > This patch serial is for RK3399 MIPI DSI. The MIPI DSI controller of
> >> > RK3399 is almost the same as RK3288, except a little bit of difference
> >> > in phy clock controlling and port id selection register. These patches
> >> > add RK3399 support and the power domain support.
> >> >
> >> > And these patches base on John Keeping's v3 patches[0], it fixes many bugs,
> >> > they have been tested on rk3288 evb board.
> >>
> >> Do we have an ETA on when John is planning on respinning his patchset based on
> >> review feedback?
> >
> > I have all of the changes queued but I was hoping to find some time to
> > test the latest version before sending it out; unfortunately everything
> > else is more important at the moment. If you're happy with the caveat
> > that the latest changes are build tested only I can probably send it
> > out this afternoon.
>
> I suppose my answer depends on when the tested version will be
> available, or perhaps Chris can test the new set for you? I don't have
> any rockchip devices with mipi, so i'm not much help.
None of the changes scare me that much, so I don't expect testing to
throw up any problems but I don't like throwing out patches without at
least a basic test run.
I might have time to test on Friday, but I expect Chris has more time to
devote to this than I do, so maybe it's better if I send the patches out
tomorrow.
John
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 51+ messages in thread
* [RESEND PATCH v7 0/7] Rockchip dw-mipi-dsi driver
@ 2017-02-22 18:55 ` John Keeping
0 siblings, 0 replies; 51+ messages in thread
From: John Keeping @ 2017-02-22 18:55 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, 22 Feb 2017 10:57:05 -0500, Sean Paul wrote:
> On Wed, Feb 22, 2017 at 8:43 AM, John Keeping <john@metanate.com> wrote:
> > On Tue, 21 Feb 2017 10:39:18 -0500, Sean Paul wrote:
> >
> >> On Mon, Feb 20, 2017 at 04:02:16PM +0800, Chris Zhong wrote:
> >> > Hi all
> >> >
> >> > [Resend this v7 version series, since there are 5 mails have gone missing, last
> >> > week]
> >> >
> >> > This version does not change the existing v6 patches, just to add the
> >> > "bandwidth fix" patch back, since we really need it.
> >> >
> >> > This patch serial is for RK3399 MIPI DSI. The MIPI DSI controller of
> >> > RK3399 is almost the same as RK3288, except a little bit of difference
> >> > in phy clock controlling and port id selection register. These patches
> >> > add RK3399 support and the power domain support.
> >> >
> >> > And these patches base on John Keeping's v3 patches[0], it fixes many bugs,
> >> > they have been tested on rk3288 evb board.
> >>
> >> Do we have an ETA on when John is planning on respinning his patchset based on
> >> review feedback?
> >
> > I have all of the changes queued but I was hoping to find some time to
> > test the latest version before sending it out; unfortunately everything
> > else is more important at the moment. If you're happy with the caveat
> > that the latest changes are build tested only I can probably send it
> > out this afternoon.
>
> I suppose my answer depends on when the tested version will be
> available, or perhaps Chris can test the new set for you? I don't have
> any rockchip devices with mipi, so i'm not much help.
None of the changes scare me that much, so I don't expect testing to
throw up any problems but I don't like throwing out patches without at
least a basic test run.
I might have time to test on Friday, but I expect Chris has more time to
devote to this than I do, so maybe it's better if I send the patches out
tomorrow.
John
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [RESEND PATCH v7 0/7] Rockchip dw-mipi-dsi driver
2017-02-22 18:55 ` John Keeping
(?)
@ 2017-02-22 22:10 ` Sean Paul
-1 siblings, 0 replies; 51+ messages in thread
From: Sean Paul @ 2017-02-22 22:10 UTC (permalink / raw)
To: John Keeping
Cc: Chris Zhong, Doug Anderson, Tomasz Figa, Heiko Stuebner,
Mark Yao, Mark Rutland, devicetree, Rob Herring, Kumar Gala,
Pawel Moll, Linux Kernel Mailing List, dri-devel,
open list:ARM/Rockchip SoC...,
Linux ARM Kernel
On Wed, Feb 22, 2017 at 1:55 PM, John Keeping <john@metanate.com> wrote:
> On Wed, 22 Feb 2017 10:57:05 -0500, Sean Paul wrote:
>
>> On Wed, Feb 22, 2017 at 8:43 AM, John Keeping <john@metanate.com> wrote:
>> > On Tue, 21 Feb 2017 10:39:18 -0500, Sean Paul wrote:
>> >
>> >> On Mon, Feb 20, 2017 at 04:02:16PM +0800, Chris Zhong wrote:
>> >> > Hi all
>> >> >
>> >> > [Resend this v7 version series, since there are 5 mails have gone missing, last
>> >> > week]
>> >> >
>> >> > This version does not change the existing v6 patches, just to add the
>> >> > "bandwidth fix" patch back, since we really need it.
>> >> >
>> >> > This patch serial is for RK3399 MIPI DSI. The MIPI DSI controller of
>> >> > RK3399 is almost the same as RK3288, except a little bit of difference
>> >> > in phy clock controlling and port id selection register. These patches
>> >> > add RK3399 support and the power domain support.
>> >> >
>> >> > And these patches base on John Keeping's v3 patches[0], it fixes many bugs,
>> >> > they have been tested on rk3288 evb board.
>> >>
>> >> Do we have an ETA on when John is planning on respinning his patchset based on
>> >> review feedback?
>> >
>> > I have all of the changes queued but I was hoping to find some time to
>> > test the latest version before sending it out; unfortunately everything
>> > else is more important at the moment. If you're happy with the caveat
>> > that the latest changes are build tested only I can probably send it
>> > out this afternoon.
>>
>> I suppose my answer depends on when the tested version will be
>> available, or perhaps Chris can test the new set for you? I don't have
>> any rockchip devices with mipi, so i'm not much help.
>
> None of the changes scare me that much, so I don't expect testing to
> throw up any problems but I don't like throwing out patches without at
> least a basic test run.
>
Agreed. I don't think we're in such desperate need that we should
forego testing. If Chris can provide Tested-by, you should send them
out, otherwise I'm happy to wait.
Thanks for the update,
Sean
> I might have time to test on Friday, but I expect Chris has more time to
> devote to this than I do, so maybe it's better if I send the patches out
> tomorrow.
>
>
> John
--
Sean Paul, Software Engineer, Google / Chromium OS
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [RESEND PATCH v7 0/7] Rockchip dw-mipi-dsi driver
@ 2017-02-22 22:10 ` Sean Paul
0 siblings, 0 replies; 51+ messages in thread
From: Sean Paul @ 2017-02-22 22:10 UTC (permalink / raw)
To: John Keeping
Cc: Mark Rutland, devicetree, Pawel Moll, Mark Yao,
Linux Kernel Mailing List, Doug Anderson, dri-devel, Tomasz Figa,
open list:ARM/Rockchip SoC...,
Rob Herring, Kumar Gala, Chris Zhong, Linux ARM Kernel
On Wed, Feb 22, 2017 at 1:55 PM, John Keeping <john@metanate.com> wrote:
> On Wed, 22 Feb 2017 10:57:05 -0500, Sean Paul wrote:
>
>> On Wed, Feb 22, 2017 at 8:43 AM, John Keeping <john@metanate.com> wrote:
>> > On Tue, 21 Feb 2017 10:39:18 -0500, Sean Paul wrote:
>> >
>> >> On Mon, Feb 20, 2017 at 04:02:16PM +0800, Chris Zhong wrote:
>> >> > Hi all
>> >> >
>> >> > [Resend this v7 version series, since there are 5 mails have gone missing, last
>> >> > week]
>> >> >
>> >> > This version does not change the existing v6 patches, just to add the
>> >> > "bandwidth fix" patch back, since we really need it.
>> >> >
>> >> > This patch serial is for RK3399 MIPI DSI. The MIPI DSI controller of
>> >> > RK3399 is almost the same as RK3288, except a little bit of difference
>> >> > in phy clock controlling and port id selection register. These patches
>> >> > add RK3399 support and the power domain support.
>> >> >
>> >> > And these patches base on John Keeping's v3 patches[0], it fixes many bugs,
>> >> > they have been tested on rk3288 evb board.
>> >>
>> >> Do we have an ETA on when John is planning on respinning his patchset based on
>> >> review feedback?
>> >
>> > I have all of the changes queued but I was hoping to find some time to
>> > test the latest version before sending it out; unfortunately everything
>> > else is more important at the moment. If you're happy with the caveat
>> > that the latest changes are build tested only I can probably send it
>> > out this afternoon.
>>
>> I suppose my answer depends on when the tested version will be
>> available, or perhaps Chris can test the new set for you? I don't have
>> any rockchip devices with mipi, so i'm not much help.
>
> None of the changes scare me that much, so I don't expect testing to
> throw up any problems but I don't like throwing out patches without at
> least a basic test run.
>
Agreed. I don't think we're in such desperate need that we should
forego testing. If Chris can provide Tested-by, you should send them
out, otherwise I'm happy to wait.
Thanks for the update,
Sean
> I might have time to test on Friday, but I expect Chris has more time to
> devote to this than I do, so maybe it's better if I send the patches out
> tomorrow.
>
>
> John
--
Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 51+ messages in thread
* [RESEND PATCH v7 0/7] Rockchip dw-mipi-dsi driver
@ 2017-02-22 22:10 ` Sean Paul
0 siblings, 0 replies; 51+ messages in thread
From: Sean Paul @ 2017-02-22 22:10 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Feb 22, 2017 at 1:55 PM, John Keeping <john@metanate.com> wrote:
> On Wed, 22 Feb 2017 10:57:05 -0500, Sean Paul wrote:
>
>> On Wed, Feb 22, 2017 at 8:43 AM, John Keeping <john@metanate.com> wrote:
>> > On Tue, 21 Feb 2017 10:39:18 -0500, Sean Paul wrote:
>> >
>> >> On Mon, Feb 20, 2017 at 04:02:16PM +0800, Chris Zhong wrote:
>> >> > Hi all
>> >> >
>> >> > [Resend this v7 version series, since there are 5 mails have gone missing, last
>> >> > week]
>> >> >
>> >> > This version does not change the existing v6 patches, just to add the
>> >> > "bandwidth fix" patch back, since we really need it.
>> >> >
>> >> > This patch serial is for RK3399 MIPI DSI. The MIPI DSI controller of
>> >> > RK3399 is almost the same as RK3288, except a little bit of difference
>> >> > in phy clock controlling and port id selection register. These patches
>> >> > add RK3399 support and the power domain support.
>> >> >
>> >> > And these patches base on John Keeping's v3 patches[0], it fixes many bugs,
>> >> > they have been tested on rk3288 evb board.
>> >>
>> >> Do we have an ETA on when John is planning on respinning his patchset based on
>> >> review feedback?
>> >
>> > I have all of the changes queued but I was hoping to find some time to
>> > test the latest version before sending it out; unfortunately everything
>> > else is more important at the moment. If you're happy with the caveat
>> > that the latest changes are build tested only I can probably send it
>> > out this afternoon.
>>
>> I suppose my answer depends on when the tested version will be
>> available, or perhaps Chris can test the new set for you? I don't have
>> any rockchip devices with mipi, so i'm not much help.
>
> None of the changes scare me that much, so I don't expect testing to
> throw up any problems but I don't like throwing out patches without at
> least a basic test run.
>
Agreed. I don't think we're in such desperate need that we should
forego testing. If Chris can provide Tested-by, you should send them
out, otherwise I'm happy to wait.
Thanks for the update,
Sean
> I might have time to test on Friday, but I expect Chris has more time to
> devote to this than I do, so maybe it's better if I send the patches out
> tomorrow.
>
>
> John
--
Sean Paul, Software Engineer, Google / Chromium OS
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [RESEND PATCH v7 0/7] Rockchip dw-mipi-dsi driver
2017-02-22 22:10 ` Sean Paul
(?)
@ 2017-02-23 0:25 ` Chris Zhong
-1 siblings, 0 replies; 51+ messages in thread
From: Chris Zhong @ 2017-02-23 0:25 UTC (permalink / raw)
To: Sean Paul, John Keeping
Cc: Doug Anderson, Tomasz Figa, Heiko Stuebner, Mark Yao,
Mark Rutland, devicetree, Rob Herring, Kumar Gala, Pawel Moll,
Linux Kernel Mailing List, dri-devel,
open list:ARM/Rockchip SoC...,
Linux ARM Kernel
On 02/23/2017 06:10 AM, Sean Paul wrote:
> On Wed, Feb 22, 2017 at 1:55 PM, John Keeping <john@metanate.com> wrote:
>> On Wed, 22 Feb 2017 10:57:05 -0500, Sean Paul wrote:
>>
>>> On Wed, Feb 22, 2017 at 8:43 AM, John Keeping <john@metanate.com> wrote:
>>>> On Tue, 21 Feb 2017 10:39:18 -0500, Sean Paul wrote:
>>>>
>>>>> On Mon, Feb 20, 2017 at 04:02:16PM +0800, Chris Zhong wrote:
>>>>>> Hi all
>>>>>>
>>>>>> [Resend this v7 version series, since there are 5 mails have gone missing, last
>>>>>> week]
>>>>>>
>>>>>> This version does not change the existing v6 patches, just to add the
>>>>>> "bandwidth fix" patch back, since we really need it.
>>>>>>
>>>>>> This patch serial is for RK3399 MIPI DSI. The MIPI DSI controller of
>>>>>> RK3399 is almost the same as RK3288, except a little bit of difference
>>>>>> in phy clock controlling and port id selection register. These patches
>>>>>> add RK3399 support and the power domain support.
>>>>>>
>>>>>> And these patches base on John Keeping's v3 patches[0], it fixes many bugs,
>>>>>> they have been tested on rk3288 evb board.
>>>>> Do we have an ETA on when John is planning on respinning his patchset based on
>>>>> review feedback?
>>>> I have all of the changes queued but I was hoping to find some time to
>>>> test the latest version before sending it out; unfortunately everything
>>>> else is more important at the moment. If you're happy with the caveat
>>>> that the latest changes are build tested only I can probably send it
>>>> out this afternoon.
>>> I suppose my answer depends on when the tested version will be
>>> available, or perhaps Chris can test the new set for you? I don't have
>>> any rockchip devices with mipi, so i'm not much help.
>> None of the changes scare me that much, so I don't expect testing to
>> throw up any problems but I don't like throwing out patches without at
>> least a basic test run.
>>
> Agreed. I don't think we're in such desperate need that we should
> forego testing. If Chris can provide Tested-by, you should send them
> out, otherwise I'm happy to wait.
>
> Thanks for the update,
>
> Sean
Sure, I am very glad to test them.
Actually, I have picked the v3 patches to cros kernel (changed a little
bit).
So far, my 2 mipi dsi panels works well. The cros patches:
https://chromium-review.googlesource.com/#/c/430596/
...
https://chromium-review.googlesource.com/#/c/442347/
>
>> I might have time to test on Friday, but I expect Chris has more time to
>> devote to this than I do, so maybe it's better if I send the patches out
>> tomorrow.
>>
>>
>> John
>
>
--
Chris Zhong
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [RESEND PATCH v7 0/7] Rockchip dw-mipi-dsi driver
@ 2017-02-23 0:25 ` Chris Zhong
0 siblings, 0 replies; 51+ messages in thread
From: Chris Zhong @ 2017-02-23 0:25 UTC (permalink / raw)
To: Sean Paul, John Keeping
Cc: Mark Rutland, devicetree, Pawel Moll, Mark Yao,
Linux Kernel Mailing List, Doug Anderson, dri-devel, Tomasz Figa,
open list:ARM/Rockchip SoC...,
Rob Herring, Kumar Gala, Linux ARM Kernel
On 02/23/2017 06:10 AM, Sean Paul wrote:
> On Wed, Feb 22, 2017 at 1:55 PM, John Keeping <john@metanate.com> wrote:
>> On Wed, 22 Feb 2017 10:57:05 -0500, Sean Paul wrote:
>>
>>> On Wed, Feb 22, 2017 at 8:43 AM, John Keeping <john@metanate.com> wrote:
>>>> On Tue, 21 Feb 2017 10:39:18 -0500, Sean Paul wrote:
>>>>
>>>>> On Mon, Feb 20, 2017 at 04:02:16PM +0800, Chris Zhong wrote:
>>>>>> Hi all
>>>>>>
>>>>>> [Resend this v7 version series, since there are 5 mails have gone missing, last
>>>>>> week]
>>>>>>
>>>>>> This version does not change the existing v6 patches, just to add the
>>>>>> "bandwidth fix" patch back, since we really need it.
>>>>>>
>>>>>> This patch serial is for RK3399 MIPI DSI. The MIPI DSI controller of
>>>>>> RK3399 is almost the same as RK3288, except a little bit of difference
>>>>>> in phy clock controlling and port id selection register. These patches
>>>>>> add RK3399 support and the power domain support.
>>>>>>
>>>>>> And these patches base on John Keeping's v3 patches[0], it fixes many bugs,
>>>>>> they have been tested on rk3288 evb board.
>>>>> Do we have an ETA on when John is planning on respinning his patchset based on
>>>>> review feedback?
>>>> I have all of the changes queued but I was hoping to find some time to
>>>> test the latest version before sending it out; unfortunately everything
>>>> else is more important at the moment. If you're happy with the caveat
>>>> that the latest changes are build tested only I can probably send it
>>>> out this afternoon.
>>> I suppose my answer depends on when the tested version will be
>>> available, or perhaps Chris can test the new set for you? I don't have
>>> any rockchip devices with mipi, so i'm not much help.
>> None of the changes scare me that much, so I don't expect testing to
>> throw up any problems but I don't like throwing out patches without at
>> least a basic test run.
>>
> Agreed. I don't think we're in such desperate need that we should
> forego testing. If Chris can provide Tested-by, you should send them
> out, otherwise I'm happy to wait.
>
> Thanks for the update,
>
> Sean
Sure, I am very glad to test them.
Actually, I have picked the v3 patches to cros kernel (changed a little
bit).
So far, my 2 mipi dsi panels works well. The cros patches:
https://chromium-review.googlesource.com/#/c/430596/
...
https://chromium-review.googlesource.com/#/c/442347/
>
>> I might have time to test on Friday, but I expect Chris has more time to
>> devote to this than I do, so maybe it's better if I send the patches out
>> tomorrow.
>>
>>
>> John
>
>
--
Chris Zhong
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 51+ messages in thread
* [RESEND PATCH v7 0/7] Rockchip dw-mipi-dsi driver
@ 2017-02-23 0:25 ` Chris Zhong
0 siblings, 0 replies; 51+ messages in thread
From: Chris Zhong @ 2017-02-23 0:25 UTC (permalink / raw)
To: linux-arm-kernel
On 02/23/2017 06:10 AM, Sean Paul wrote:
> On Wed, Feb 22, 2017 at 1:55 PM, John Keeping <john@metanate.com> wrote:
>> On Wed, 22 Feb 2017 10:57:05 -0500, Sean Paul wrote:
>>
>>> On Wed, Feb 22, 2017 at 8:43 AM, John Keeping <john@metanate.com> wrote:
>>>> On Tue, 21 Feb 2017 10:39:18 -0500, Sean Paul wrote:
>>>>
>>>>> On Mon, Feb 20, 2017 at 04:02:16PM +0800, Chris Zhong wrote:
>>>>>> Hi all
>>>>>>
>>>>>> [Resend this v7 version series, since there are 5 mails have gone missing, last
>>>>>> week]
>>>>>>
>>>>>> This version does not change the existing v6 patches, just to add the
>>>>>> "bandwidth fix" patch back, since we really need it.
>>>>>>
>>>>>> This patch serial is for RK3399 MIPI DSI. The MIPI DSI controller of
>>>>>> RK3399 is almost the same as RK3288, except a little bit of difference
>>>>>> in phy clock controlling and port id selection register. These patches
>>>>>> add RK3399 support and the power domain support.
>>>>>>
>>>>>> And these patches base on John Keeping's v3 patches[0], it fixes many bugs,
>>>>>> they have been tested on rk3288 evb board.
>>>>> Do we have an ETA on when John is planning on respinning his patchset based on
>>>>> review feedback?
>>>> I have all of the changes queued but I was hoping to find some time to
>>>> test the latest version before sending it out; unfortunately everything
>>>> else is more important at the moment. If you're happy with the caveat
>>>> that the latest changes are build tested only I can probably send it
>>>> out this afternoon.
>>> I suppose my answer depends on when the tested version will be
>>> available, or perhaps Chris can test the new set for you? I don't have
>>> any rockchip devices with mipi, so i'm not much help.
>> None of the changes scare me that much, so I don't expect testing to
>> throw up any problems but I don't like throwing out patches without at
>> least a basic test run.
>>
> Agreed. I don't think we're in such desperate need that we should
> forego testing. If Chris can provide Tested-by, you should send them
> out, otherwise I'm happy to wait.
>
> Thanks for the update,
>
> Sean
Sure, I am very glad to test them.
Actually, I have picked the v3 patches to cros kernel (changed a little
bit).
So far, my 2 mipi dsi panels works well. The cros patches:
https://chromium-review.googlesource.com/#/c/430596/
...
https://chromium-review.googlesource.com/#/c/442347/
>
>> I might have time to test on Friday, but I expect Chris has more time to
>> devote to this than I do, so maybe it's better if I send the patches out
>> tomorrow.
>>
>>
>> John
>
>
--
Chris Zhong
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [RESEND PATCH v7 0/7] Rockchip dw-mipi-dsi driver
2017-02-20 8:02 ` Chris Zhong
(?)
@ 2017-03-01 20:02 ` Sean Paul
-1 siblings, 0 replies; 51+ messages in thread
From: Sean Paul @ 2017-03-01 20:02 UTC (permalink / raw)
To: Chris Zhong
Cc: john, dianders, tfiga, heiko, yzq, mark.rutland, devicetree,
robh+dt, galak, pawel.moll, seanpaul, linux-kernel, dri-devel,
linux-rockchip, linux-arm-kernel
On Mon, Feb 20, 2017 at 04:02:16PM +0800, Chris Zhong wrote:
> Hi all
>
> [Resend this v7 version series, since there are 5 mails have gone missing, last
> week]
>
> This version does not change the existing v6 patches, just to add the
> "bandwidth fix" patch back, since we really need it.
>
> This patch serial is for RK3399 MIPI DSI. The MIPI DSI controller of
> RK3399 is almost the same as RK3288, except a little bit of difference
> in phy clock controlling and port id selection register. These patches
> add RK3399 support and the power domain support.
>
> And these patches base on John Keeping's v3 patches[0], it fixes many bugs,
> they have been tested on rk3288 evb board.
>
> [0]:
> [01/24] https://patchwork.kernel.org/patch/9544089
> [02/24] https://patchwork.kernel.org/patch/9544061
> [03/24] https://patchwork.kernel.org/patch/9544065
> [04/24] https://patchwork.kernel.org/patch/9544077
> [05/24] https://patchwork.kernel.org/patch/9544033
> [06/24] https://patchwork.kernel.org/patch/9544037
> [07/24] https://patchwork.kernel.org/patch/9544029
> [08/24] https://patchwork.kernel.org/patch/9544031
> [09/24] https://patchwork.kernel.org/patch/9544083
> [10/24] https://patchwork.kernel.org/patch/9544063
> [11/24] https://patchwork.kernel.org/patch/9544085
> [12/24] https://patchwork.kernel.org/patch/9544093
> [13/24] https://patchwork.kernel.org/patch/9544081
> [14/24] https://patchwork.kernel.org/patch/9544057
> [15/24] https://patchwork.kernel.org/patch/9544079
> [16/24] https://patchwork.kernel.org/patch/9544035
> [17/24] https://patchwork.kernel.org/patch/9544105
> [18/24] https://patchwork.kernel.org/patch/9544059
> [21/24] https://patchwork.kernel.org/patch/9544009
> [22/24] https://patchwork.kernel.org/patch/9544049
> [23/24] https://patchwork.kernel.org/patch/9544055
> [24/24] https://patchwork.kernel.org/patch/9544109
>
>
> Changes in v6:
> - no need check phy_cfg_clk before enable/disable
>
> Changes in v5:
> - check the error of phy_cfg_clk in dw_mipi_dsi_bind
>
> Changes in v4:
> - remove the unrelated change
>
> Changes in v3:
> - base on John Keeping's patch series
>
> Chris Zhong (7):
> dt-bindings: add rk3399 support for dw-mipi-rockchip
> drm/rockchip/dsi: dw-mipi: support RK3399 mipi dsi
> drm/rockchip/dsi: dw-mipi: correct the coding style
> drm/rockchip/dsi: remove mode_valid function
> dt-bindings: add power domain node for dw-mipi-rockchip
> drm/rockchip/dsi: fix insufficient bandwidth of some panel
> drm/rockchip/dsi: add dw-mipi power domain support
Applied to drm-misc
Thanks,
Sean
>
> .../display/rockchip/dw_mipi_dsi_rockchip.txt | 7 +-
> drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 160 ++++++++++++---------
> 2 files changed, 100 insertions(+), 67 deletions(-)
>
> --
> 2.6.3
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [RESEND PATCH v7 0/7] Rockchip dw-mipi-dsi driver
@ 2017-03-01 20:02 ` Sean Paul
0 siblings, 0 replies; 51+ messages in thread
From: Sean Paul @ 2017-03-01 20:02 UTC (permalink / raw)
To: Chris Zhong
Cc: mark.rutland, devicetree, pawel.moll, yzq, linux-kernel,
dianders, dri-devel, tfiga, linux-rockchip, robh+dt, galak,
linux-arm-kernel
On Mon, Feb 20, 2017 at 04:02:16PM +0800, Chris Zhong wrote:
> Hi all
>
> [Resend this v7 version series, since there are 5 mails have gone missing, last
> week]
>
> This version does not change the existing v6 patches, just to add the
> "bandwidth fix" patch back, since we really need it.
>
> This patch serial is for RK3399 MIPI DSI. The MIPI DSI controller of
> RK3399 is almost the same as RK3288, except a little bit of difference
> in phy clock controlling and port id selection register. These patches
> add RK3399 support and the power domain support.
>
> And these patches base on John Keeping's v3 patches[0], it fixes many bugs,
> they have been tested on rk3288 evb board.
>
> [0]:
> [01/24] https://patchwork.kernel.org/patch/9544089
> [02/24] https://patchwork.kernel.org/patch/9544061
> [03/24] https://patchwork.kernel.org/patch/9544065
> [04/24] https://patchwork.kernel.org/patch/9544077
> [05/24] https://patchwork.kernel.org/patch/9544033
> [06/24] https://patchwork.kernel.org/patch/9544037
> [07/24] https://patchwork.kernel.org/patch/9544029
> [08/24] https://patchwork.kernel.org/patch/9544031
> [09/24] https://patchwork.kernel.org/patch/9544083
> [10/24] https://patchwork.kernel.org/patch/9544063
> [11/24] https://patchwork.kernel.org/patch/9544085
> [12/24] https://patchwork.kernel.org/patch/9544093
> [13/24] https://patchwork.kernel.org/patch/9544081
> [14/24] https://patchwork.kernel.org/patch/9544057
> [15/24] https://patchwork.kernel.org/patch/9544079
> [16/24] https://patchwork.kernel.org/patch/9544035
> [17/24] https://patchwork.kernel.org/patch/9544105
> [18/24] https://patchwork.kernel.org/patch/9544059
> [21/24] https://patchwork.kernel.org/patch/9544009
> [22/24] https://patchwork.kernel.org/patch/9544049
> [23/24] https://patchwork.kernel.org/patch/9544055
> [24/24] https://patchwork.kernel.org/patch/9544109
>
>
> Changes in v6:
> - no need check phy_cfg_clk before enable/disable
>
> Changes in v5:
> - check the error of phy_cfg_clk in dw_mipi_dsi_bind
>
> Changes in v4:
> - remove the unrelated change
>
> Changes in v3:
> - base on John Keeping's patch series
>
> Chris Zhong (7):
> dt-bindings: add rk3399 support for dw-mipi-rockchip
> drm/rockchip/dsi: dw-mipi: support RK3399 mipi dsi
> drm/rockchip/dsi: dw-mipi: correct the coding style
> drm/rockchip/dsi: remove mode_valid function
> dt-bindings: add power domain node for dw-mipi-rockchip
> drm/rockchip/dsi: fix insufficient bandwidth of some panel
> drm/rockchip/dsi: add dw-mipi power domain support
Applied to drm-misc
Thanks,
Sean
>
> .../display/rockchip/dw_mipi_dsi_rockchip.txt | 7 +-
> drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 160 ++++++++++++---------
> 2 files changed, 100 insertions(+), 67 deletions(-)
>
> --
> 2.6.3
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 51+ messages in thread
* [RESEND PATCH v7 0/7] Rockchip dw-mipi-dsi driver
@ 2017-03-01 20:02 ` Sean Paul
0 siblings, 0 replies; 51+ messages in thread
From: Sean Paul @ 2017-03-01 20:02 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Feb 20, 2017 at 04:02:16PM +0800, Chris Zhong wrote:
> Hi all
>
> [Resend this v7 version series, since there are 5 mails have gone missing, last
> week]
>
> This version does not change the existing v6 patches, just to add the
> "bandwidth fix" patch back, since we really need it.
>
> This patch serial is for RK3399 MIPI DSI. The MIPI DSI controller of
> RK3399 is almost the same as RK3288, except a little bit of difference
> in phy clock controlling and port id selection register. These patches
> add RK3399 support and the power domain support.
>
> And these patches base on John Keeping's v3 patches[0], it fixes many bugs,
> they have been tested on rk3288 evb board.
>
> [0]:
> [01/24] https://patchwork.kernel.org/patch/9544089
> [02/24] https://patchwork.kernel.org/patch/9544061
> [03/24] https://patchwork.kernel.org/patch/9544065
> [04/24] https://patchwork.kernel.org/patch/9544077
> [05/24] https://patchwork.kernel.org/patch/9544033
> [06/24] https://patchwork.kernel.org/patch/9544037
> [07/24] https://patchwork.kernel.org/patch/9544029
> [08/24] https://patchwork.kernel.org/patch/9544031
> [09/24] https://patchwork.kernel.org/patch/9544083
> [10/24] https://patchwork.kernel.org/patch/9544063
> [11/24] https://patchwork.kernel.org/patch/9544085
> [12/24] https://patchwork.kernel.org/patch/9544093
> [13/24] https://patchwork.kernel.org/patch/9544081
> [14/24] https://patchwork.kernel.org/patch/9544057
> [15/24] https://patchwork.kernel.org/patch/9544079
> [16/24] https://patchwork.kernel.org/patch/9544035
> [17/24] https://patchwork.kernel.org/patch/9544105
> [18/24] https://patchwork.kernel.org/patch/9544059
> [21/24] https://patchwork.kernel.org/patch/9544009
> [22/24] https://patchwork.kernel.org/patch/9544049
> [23/24] https://patchwork.kernel.org/patch/9544055
> [24/24] https://patchwork.kernel.org/patch/9544109
>
>
> Changes in v6:
> - no need check phy_cfg_clk before enable/disable
>
> Changes in v5:
> - check the error of phy_cfg_clk in dw_mipi_dsi_bind
>
> Changes in v4:
> - remove the unrelated change
>
> Changes in v3:
> - base on John Keeping's patch series
>
> Chris Zhong (7):
> dt-bindings: add rk3399 support for dw-mipi-rockchip
> drm/rockchip/dsi: dw-mipi: support RK3399 mipi dsi
> drm/rockchip/dsi: dw-mipi: correct the coding style
> drm/rockchip/dsi: remove mode_valid function
> dt-bindings: add power domain node for dw-mipi-rockchip
> drm/rockchip/dsi: fix insufficient bandwidth of some panel
> drm/rockchip/dsi: add dw-mipi power domain support
Applied to drm-misc
Thanks,
Sean
>
> .../display/rockchip/dw_mipi_dsi_rockchip.txt | 7 +-
> drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 160 ++++++++++++---------
> 2 files changed, 100 insertions(+), 67 deletions(-)
>
> --
> 2.6.3
>
> _______________________________________________
> dri-devel mailing list
> dri-devel at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 51+ messages in thread
end of thread, other threads:[~2017-03-02 5:22 UTC | newest]
Thread overview: 51+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-02-20 8:02 [RESEND PATCH v7 0/7] Rockchip dw-mipi-dsi driver Chris Zhong
2017-02-20 8:02 ` Chris Zhong
2017-02-20 8:02 ` Chris Zhong
2017-02-20 8:02 ` [RESEND PATCH v7 1/7] dt-bindings: add rk3399 support for dw-mipi-rockchip Chris Zhong
2017-02-20 8:02 ` Chris Zhong
2017-02-20 8:02 ` Chris Zhong
2017-02-20 8:02 ` [RESEND PATCH v7 2/7] drm/rockchip/dsi: dw-mipi: support RK3399 mipi dsi Chris Zhong
2017-02-20 8:02 ` Chris Zhong
2017-02-20 8:02 ` Chris Zhong
2017-02-20 8:02 ` [RESEND PATCH v7 3/7] drm/rockchip/dsi: dw-mipi: correct the coding style Chris Zhong
2017-02-20 8:02 ` Chris Zhong
2017-02-20 8:02 ` Chris Zhong
2017-02-20 8:02 ` [RESEND PATCH v7 4/7] drm/rockchip/dsi: remove mode_valid function Chris Zhong
2017-02-20 8:02 ` Chris Zhong
2017-02-20 8:02 ` Chris Zhong
2017-02-20 8:02 ` [RESEND PATCH v7 5/7] dt-bindings: add power domain node for dw-mipi-rockchip Chris Zhong
2017-02-20 8:02 ` Chris Zhong
2017-02-20 8:02 ` Chris Zhong
2017-02-20 8:02 ` [RESEND PATCH v7 6/7] drm/rockchip/dsi: fix insufficient bandwidth of some panel Chris Zhong
2017-02-20 8:02 ` Chris Zhong
2017-02-20 8:02 ` Chris Zhong
2017-02-21 15:40 ` Sean Paul
2017-02-21 15:40 ` Sean Paul
2017-02-21 15:40 ` Sean Paul
2017-02-20 8:02 ` [RESEND PATCH v7 7/7] drm/rockchip/dsi: add dw-mipi power domain support Chris Zhong
2017-02-20 8:02 ` Chris Zhong
2017-02-20 8:02 ` Chris Zhong
2017-02-21 15:39 ` [RESEND PATCH v7 0/7] Rockchip dw-mipi-dsi driver Sean Paul
2017-02-21 15:39 ` Sean Paul
2017-02-21 15:39 ` Sean Paul
2017-02-22 1:44 ` Chris Zhong
2017-02-22 1:44 ` Chris Zhong
2017-02-22 1:44 ` Chris Zhong
2017-02-22 13:43 ` John Keeping
2017-02-22 13:43 ` John Keeping
2017-02-22 13:43 ` John Keeping
2017-02-22 15:57 ` Sean Paul
2017-02-22 15:57 ` Sean Paul
2017-02-22 15:57 ` Sean Paul
2017-02-22 18:55 ` John Keeping
2017-02-22 18:55 ` John Keeping
2017-02-22 18:55 ` John Keeping
2017-02-22 22:10 ` Sean Paul
2017-02-22 22:10 ` Sean Paul
2017-02-22 22:10 ` Sean Paul
2017-02-23 0:25 ` Chris Zhong
2017-02-23 0:25 ` Chris Zhong
2017-02-23 0:25 ` Chris Zhong
2017-03-01 20:02 ` Sean Paul
2017-03-01 20:02 ` Sean Paul
2017-03-01 20:02 ` Sean Paul
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