* Re: [PATCH] clk: tegra: mark TEGRA210_CLK_DBGAPB as always on
@ 2017-03-06 15:53 ` Geert Uytterhoeven
0 siblings, 0 replies; 32+ messages in thread
From: Geert Uytterhoeven @ 2017-03-06 15:53 UTC (permalink / raw)
To: Peter De Schrijver
Cc: Jon Hunter, Prashant Gaikwad, Michael Turquette, Stephen Boyd,
Stephen Warren, Thierry Reding, Alexandre Courbot, linux-clk,
linux-tegra, linux-kernel
Hi Peter,
On Mon, Mar 6, 2017 at 3:28 PM, Peter De Schrijver
<pdeschrijver@nvidia.com> wrote:
> On Mon, Mar 06, 2017 at 09:58:29AM +0000, Jon Hunter wrote:
>> On 06/03/17 08:38, Peter De Schrijver wrote:
>> > On Thu, Mar 02, 2017 at 05:56:49PM +0000, Jon Hunter wrote:
>> >> On 28/02/17 15:19, Peter De Schrijver wrote:
>> >>> This is needed to make the JTAG debugging interface work.
>> >>>
>> >>> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
>> >>> ---
>> >>> drivers/clk/tegra/clk-tegra210.c | 1 +
>> >>> 1 file changed, 1 insertion(+)
>> >>>
>> >>> diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
>> >>> index 9a2512a..708f5f1 100644
>> >>> --- a/drivers/clk/tegra/clk-tegra210.c
>> >>> +++ b/drivers/clk/tegra/clk-tegra210.c
>> >>> @@ -2680,6 +2680,7 @@ static void tegra210_cpu_clock_resume(void)
>> >>> { TEGRA210_CLK_EMC, TEGRA210_CLK_CLK_MAX, 0, 1 },
>> >>> { TEGRA210_CLK_MSELECT, TEGRA210_CLK_CLK_MAX, 0, 1 },
>> >>> { TEGRA210_CLK_CSITE, TEGRA210_CLK_CLK_MAX, 0, 1 },
>> >>> + { TEGRA210_CLK_DBGAPB, TEGRA210_CLK_CLK_MAX, 0, 1 },
>> >>> { TEGRA210_CLK_TSENSOR, TEGRA210_CLK_CLK_M, 400000, 0 },
>> >>> { TEGRA210_CLK_I2C1, TEGRA210_CLK_PLL_P, 0, 0 },
>> >>> { TEGRA210_CLK_I2C2, TEGRA210_CLK_PLL_P, 0, 0 },
>> >>
>> >> Should there be some dependency on say CONFIG_DEBUG_KERNEL? I am not
>> >> sure we always want this on for all cases.
>> >
>> > Why would you not want it to be always on?
>>
>> Purely for power reasons. I do not know how much power keeping this
>
> I don't expect it to be significant but I don't have any numbers.
>
>> clock running consumes, but I don't like the idea of clocks running all
>> the time when they are not needed.
>
> Problem is that in this case there is no easy way to determine if the clock
> needs to be on.
I had a similar issue with SH-Mobile AG5, where the power domain containing
the JTAG interface is powered down.
[DEBUG] ARM: dts: sh73a0: Add minimal device node for Coresight-ETM
https://patchwork.kernel.org/patch/8151511/
Want to debug? Apply patch. I know it's not ideal...
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH] clk: tegra: mark TEGRA210_CLK_DBGAPB as always on
2017-03-06 15:53 ` Geert Uytterhoeven
@ 2017-03-07 20:27 ` Jon Hunter
-1 siblings, 0 replies; 32+ messages in thread
From: Jon Hunter @ 2017-03-07 20:27 UTC (permalink / raw)
To: Geert Uytterhoeven, Peter De Schrijver
Cc: Prashant Gaikwad, Michael Turquette, Stephen Boyd,
Stephen Warren, Thierry Reding, Alexandre Courbot, linux-clk,
linux-tegra, linux-kernel
Hi Geert,
On 06/03/17 15:53, Geert Uytterhoeven wrote:
> Hi Peter,
>
> On Mon, Mar 6, 2017 at 3:28 PM, Peter De Schrijver
> <pdeschrijver@nvidia.com> wrote:
>> On Mon, Mar 06, 2017 at 09:58:29AM +0000, Jon Hunter wrote:
>>> On 06/03/17 08:38, Peter De Schrijver wrote:
>>>> On Thu, Mar 02, 2017 at 05:56:49PM +0000, Jon Hunter wrote:
>>>>> On 28/02/17 15:19, Peter De Schrijver wrote:
>>>>>> This is needed to make the JTAG debugging interface work.
>>>>>>
>>>>>> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
>>>>>> ---
>>>>>> drivers/clk/tegra/clk-tegra210.c | 1 +
>>>>>> 1 file changed, 1 insertion(+)
>>>>>>
>>>>>> diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
>>>>>> index 9a2512a..708f5f1 100644
>>>>>> --- a/drivers/clk/tegra/clk-tegra210.c
>>>>>> +++ b/drivers/clk/tegra/clk-tegra210.c
>>>>>> @@ -2680,6 +2680,7 @@ static void tegra210_cpu_clock_resume(void)
>>>>>> { TEGRA210_CLK_EMC, TEGRA210_CLK_CLK_MAX, 0, 1 },
>>>>>> { TEGRA210_CLK_MSELECT, TEGRA210_CLK_CLK_MAX, 0, 1 },
>>>>>> { TEGRA210_CLK_CSITE, TEGRA210_CLK_CLK_MAX, 0, 1 },
>>>>>> + { TEGRA210_CLK_DBGAPB, TEGRA210_CLK_CLK_MAX, 0, 1 },
>>>>>> { TEGRA210_CLK_TSENSOR, TEGRA210_CLK_CLK_M, 400000, 0 },
>>>>>> { TEGRA210_CLK_I2C1, TEGRA210_CLK_PLL_P, 0, 0 },
>>>>>> { TEGRA210_CLK_I2C2, TEGRA210_CLK_PLL_P, 0, 0 },
>>>>>
>>>>> Should there be some dependency on say CONFIG_DEBUG_KERNEL? I am not
>>>>> sure we always want this on for all cases.
>>>>
>>>> Why would you not want it to be always on?
>>>
>>> Purely for power reasons. I do not know how much power keeping this
>>
>> I don't expect it to be significant but I don't have any numbers.
>>
>>> clock running consumes, but I don't like the idea of clocks running all
>>> the time when they are not needed.
>>
>> Problem is that in this case there is no easy way to determine if the clock
>> needs to be on.
>
> I had a similar issue with SH-Mobile AG5, where the power domain containing
> the JTAG interface is powered down.
>
> [DEBUG] ARM: dts: sh73a0: Add minimal device node for Coresight-ETM
> https://patchwork.kernel.org/patch/8151511/
>
> Want to debug? Apply patch. I know it's not ideal...
Why don't you apply the patch and just keep the node disabled by default?
Cheers
Jon
--
nvpublic
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH] clk: tegra: mark TEGRA210_CLK_DBGAPB as always on
@ 2017-03-07 20:27 ` Jon Hunter
0 siblings, 0 replies; 32+ messages in thread
From: Jon Hunter @ 2017-03-07 20:27 UTC (permalink / raw)
To: Geert Uytterhoeven, Peter De Schrijver
Cc: Prashant Gaikwad, Michael Turquette, Stephen Boyd,
Stephen Warren, Thierry Reding, Alexandre Courbot, linux-clk,
linux-tegra, linux-kernel
Hi Geert,
On 06/03/17 15:53, Geert Uytterhoeven wrote:
> Hi Peter,
>
> On Mon, Mar 6, 2017 at 3:28 PM, Peter De Schrijver
> <pdeschrijver@nvidia.com> wrote:
>> On Mon, Mar 06, 2017 at 09:58:29AM +0000, Jon Hunter wrote:
>>> On 06/03/17 08:38, Peter De Schrijver wrote:
>>>> On Thu, Mar 02, 2017 at 05:56:49PM +0000, Jon Hunter wrote:
>>>>> On 28/02/17 15:19, Peter De Schrijver wrote:
>>>>>> This is needed to make the JTAG debugging interface work.
>>>>>>
>>>>>> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
>>>>>> ---
>>>>>> drivers/clk/tegra/clk-tegra210.c | 1 +
>>>>>> 1 file changed, 1 insertion(+)
>>>>>>
>>>>>> diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
>>>>>> index 9a2512a..708f5f1 100644
>>>>>> --- a/drivers/clk/tegra/clk-tegra210.c
>>>>>> +++ b/drivers/clk/tegra/clk-tegra210.c
>>>>>> @@ -2680,6 +2680,7 @@ static void tegra210_cpu_clock_resume(void)
>>>>>> { TEGRA210_CLK_EMC, TEGRA210_CLK_CLK_MAX, 0, 1 },
>>>>>> { TEGRA210_CLK_MSELECT, TEGRA210_CLK_CLK_MAX, 0, 1 },
>>>>>> { TEGRA210_CLK_CSITE, TEGRA210_CLK_CLK_MAX, 0, 1 },
>>>>>> + { TEGRA210_CLK_DBGAPB, TEGRA210_CLK_CLK_MAX, 0, 1 },
>>>>>> { TEGRA210_CLK_TSENSOR, TEGRA210_CLK_CLK_M, 400000, 0 },
>>>>>> { TEGRA210_CLK_I2C1, TEGRA210_CLK_PLL_P, 0, 0 },
>>>>>> { TEGRA210_CLK_I2C2, TEGRA210_CLK_PLL_P, 0, 0 },
>>>>>
>>>>> Should there be some dependency on say CONFIG_DEBUG_KERNEL? I am not
>>>>> sure we always want this on for all cases.
>>>>
>>>> Why would you not want it to be always on?
>>>
>>> Purely for power reasons. I do not know how much power keeping this
>>
>> I don't expect it to be significant but I don't have any numbers.
>>
>>> clock running consumes, but I don't like the idea of clocks running all
>>> the time when they are not needed.
>>
>> Problem is that in this case there is no easy way to determine if the clock
>> needs to be on.
>
> I had a similar issue with SH-Mobile AG5, where the power domain containing
> the JTAG interface is powered down.
>
> [DEBUG] ARM: dts: sh73a0: Add minimal device node for Coresight-ETM
> https://patchwork.kernel.org/patch/8151511/
>
> Want to debug? Apply patch. I know it's not ideal...
Why don't you apply the patch and just keep the node disabled by default?
Cheers
Jon
--
nvpublic
^ permalink raw reply [flat|nested] 32+ messages in thread
[parent not found: <598a2a7d-6e01-8884-e839-c758b731605a-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>]
* Re: [PATCH] clk: tegra: mark TEGRA210_CLK_DBGAPB as always on
2017-03-07 20:27 ` Jon Hunter
@ 2017-03-08 8:23 ` Geert Uytterhoeven
-1 siblings, 0 replies; 32+ messages in thread
From: Geert Uytterhoeven @ 2017-03-08 8:23 UTC (permalink / raw)
To: Jon Hunter
Cc: Peter De Schrijver, Prashant Gaikwad, Michael Turquette,
Stephen Boyd, Stephen Warren, Thierry Reding, Alexandre Courbot,
linux-clk, linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
Hi Jon,
On Tue, Mar 7, 2017 at 9:27 PM, Jon Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote:
> On 06/03/17 15:53, Geert Uytterhoeven wrote:
>> On Mon, Mar 6, 2017 at 3:28 PM, Peter De Schrijver
>> <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote:
>>> On Mon, Mar 06, 2017 at 09:58:29AM +0000, Jon Hunter wrote:
>>>> On 06/03/17 08:38, Peter De Schrijver wrote:
>>>>> On Thu, Mar 02, 2017 at 05:56:49PM +0000, Jon Hunter wrote:
>>>>>> On 28/02/17 15:19, Peter De Schrijver wrote:
>>>>>>> This is needed to make the JTAG debugging interface work.
>>>>>>>
>>>>>>> Signed-off-by: Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>>>>>>> ---
>>>>>>> drivers/clk/tegra/clk-tegra210.c | 1 +
>>>>>>> 1 file changed, 1 insertion(+)
>>>>>>>
>>>>>>> diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
>>>>>>> index 9a2512a..708f5f1 100644
>>>>>>> --- a/drivers/clk/tegra/clk-tegra210.c
>>>>>>> +++ b/drivers/clk/tegra/clk-tegra210.c
>>>>>>> @@ -2680,6 +2680,7 @@ static void tegra210_cpu_clock_resume(void)
>>>>>>> { TEGRA210_CLK_EMC, TEGRA210_CLK_CLK_MAX, 0, 1 },
>>>>>>> { TEGRA210_CLK_MSELECT, TEGRA210_CLK_CLK_MAX, 0, 1 },
>>>>>>> { TEGRA210_CLK_CSITE, TEGRA210_CLK_CLK_MAX, 0, 1 },
>>>>>>> + { TEGRA210_CLK_DBGAPB, TEGRA210_CLK_CLK_MAX, 0, 1 },
>>>>>>> { TEGRA210_CLK_TSENSOR, TEGRA210_CLK_CLK_M, 400000, 0 },
>>>>>>> { TEGRA210_CLK_I2C1, TEGRA210_CLK_PLL_P, 0, 0 },
>>>>>>> { TEGRA210_CLK_I2C2, TEGRA210_CLK_PLL_P, 0, 0 },
>>>>>>
>>>>>> Should there be some dependency on say CONFIG_DEBUG_KERNEL? I am not
>>>>>> sure we always want this on for all cases.
>>>>>
>>>>> Why would you not want it to be always on?
>>>>
>>>> Purely for power reasons. I do not know how much power keeping this
>>>
>>> I don't expect it to be significant but I don't have any numbers.
>>>
>>>> clock running consumes, but I don't like the idea of clocks running all
>>>> the time when they are not needed.
>>>
>>> Problem is that in this case there is no easy way to determine if the clock
>>> needs to be on.
>>
>> I had a similar issue with SH-Mobile AG5, where the power domain containing
>> the JTAG interface is powered down.
>>
>> [DEBUG] ARM: dts: sh73a0: Add minimal device node for Coresight-ETM
>> https://patchwork.kernel.org/patch/8151511/
>>
>> Want to debug? Apply patch. I know it's not ideal...
>
> Why don't you apply the patch and just keep the node disabled by default?
Thanks, good idea!
Then I first have to make get_special_pds() skip disabled nodes...
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH] clk: tegra: mark TEGRA210_CLK_DBGAPB as always on
@ 2017-03-08 8:23 ` Geert Uytterhoeven
0 siblings, 0 replies; 32+ messages in thread
From: Geert Uytterhoeven @ 2017-03-08 8:23 UTC (permalink / raw)
To: Jon Hunter
Cc: Peter De Schrijver, Prashant Gaikwad, Michael Turquette,
Stephen Boyd, Stephen Warren, Thierry Reding, Alexandre Courbot,
linux-clk, linux-tegra, linux-kernel
Hi Jon,
On Tue, Mar 7, 2017 at 9:27 PM, Jon Hunter <jonathanh@nvidia.com> wrote:
> On 06/03/17 15:53, Geert Uytterhoeven wrote:
>> On Mon, Mar 6, 2017 at 3:28 PM, Peter De Schrijver
>> <pdeschrijver@nvidia.com> wrote:
>>> On Mon, Mar 06, 2017 at 09:58:29AM +0000, Jon Hunter wrote:
>>>> On 06/03/17 08:38, Peter De Schrijver wrote:
>>>>> On Thu, Mar 02, 2017 at 05:56:49PM +0000, Jon Hunter wrote:
>>>>>> On 28/02/17 15:19, Peter De Schrijver wrote:
>>>>>>> This is needed to make the JTAG debugging interface work.
>>>>>>>
>>>>>>> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
>>>>>>> ---
>>>>>>> drivers/clk/tegra/clk-tegra210.c | 1 +
>>>>>>> 1 file changed, 1 insertion(+)
>>>>>>>
>>>>>>> diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
>>>>>>> index 9a2512a..708f5f1 100644
>>>>>>> --- a/drivers/clk/tegra/clk-tegra210.c
>>>>>>> +++ b/drivers/clk/tegra/clk-tegra210.c
>>>>>>> @@ -2680,6 +2680,7 @@ static void tegra210_cpu_clock_resume(void)
>>>>>>> { TEGRA210_CLK_EMC, TEGRA210_CLK_CLK_MAX, 0, 1 },
>>>>>>> { TEGRA210_CLK_MSELECT, TEGRA210_CLK_CLK_MAX, 0, 1 },
>>>>>>> { TEGRA210_CLK_CSITE, TEGRA210_CLK_CLK_MAX, 0, 1 },
>>>>>>> + { TEGRA210_CLK_DBGAPB, TEGRA210_CLK_CLK_MAX, 0, 1 },
>>>>>>> { TEGRA210_CLK_TSENSOR, TEGRA210_CLK_CLK_M, 400000, 0 },
>>>>>>> { TEGRA210_CLK_I2C1, TEGRA210_CLK_PLL_P, 0, 0 },
>>>>>>> { TEGRA210_CLK_I2C2, TEGRA210_CLK_PLL_P, 0, 0 },
>>>>>>
>>>>>> Should there be some dependency on say CONFIG_DEBUG_KERNEL? I am not
>>>>>> sure we always want this on for all cases.
>>>>>
>>>>> Why would you not want it to be always on?
>>>>
>>>> Purely for power reasons. I do not know how much power keeping this
>>>
>>> I don't expect it to be significant but I don't have any numbers.
>>>
>>>> clock running consumes, but I don't like the idea of clocks running all
>>>> the time when they are not needed.
>>>
>>> Problem is that in this case there is no easy way to determine if the clock
>>> needs to be on.
>>
>> I had a similar issue with SH-Mobile AG5, where the power domain containing
>> the JTAG interface is powered down.
>>
>> [DEBUG] ARM: dts: sh73a0: Add minimal device node for Coresight-ETM
>> https://patchwork.kernel.org/patch/8151511/
>>
>> Want to debug? Apply patch. I know it's not ideal...
>
> Why don't you apply the patch and just keep the node disabled by default?
Thanks, good idea!
Then I first have to make get_special_pds() skip disabled nodes...
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH] clk: tegra: mark TEGRA210_CLK_DBGAPB as always on
2017-03-06 15:53 ` Geert Uytterhoeven
@ 2017-03-08 10:13 ` Jon Hunter
-1 siblings, 0 replies; 32+ messages in thread
From: Jon Hunter @ 2017-03-08 10:13 UTC (permalink / raw)
To: Geert Uytterhoeven, Peter De Schrijver
Cc: Prashant Gaikwad, Michael Turquette, Stephen Boyd,
Stephen Warren, Thierry Reding, Alexandre Courbot, linux-clk,
linux-tegra, linux-kernel
Hi Peter,
On 06/03/17 15:53, Geert Uytterhoeven wrote:
> Hi Peter,
>
> On Mon, Mar 6, 2017 at 3:28 PM, Peter De Schrijver
> <pdeschrijver@nvidia.com> wrote:
>> On Mon, Mar 06, 2017 at 09:58:29AM +0000, Jon Hunter wrote:
>>> On 06/03/17 08:38, Peter De Schrijver wrote:
>>>> On Thu, Mar 02, 2017 at 05:56:49PM +0000, Jon Hunter wrote:
>>>>> On 28/02/17 15:19, Peter De Schrijver wrote:
>>>>>> This is needed to make the JTAG debugging interface work.
>>>>>>
>>>>>> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
>>>>>> ---
>>>>>> drivers/clk/tegra/clk-tegra210.c | 1 +
>>>>>> 1 file changed, 1 insertion(+)
>>>>>>
>>>>>> diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
>>>>>> index 9a2512a..708f5f1 100644
>>>>>> --- a/drivers/clk/tegra/clk-tegra210.c
>>>>>> +++ b/drivers/clk/tegra/clk-tegra210.c
>>>>>> @@ -2680,6 +2680,7 @@ static void tegra210_cpu_clock_resume(void)
>>>>>> { TEGRA210_CLK_EMC, TEGRA210_CLK_CLK_MAX, 0, 1 },
>>>>>> { TEGRA210_CLK_MSELECT, TEGRA210_CLK_CLK_MAX, 0, 1 },
>>>>>> { TEGRA210_CLK_CSITE, TEGRA210_CLK_CLK_MAX, 0, 1 },
>>>>>> + { TEGRA210_CLK_DBGAPB, TEGRA210_CLK_CLK_MAX, 0, 1 },
>>>>>> { TEGRA210_CLK_TSENSOR, TEGRA210_CLK_CLK_M, 400000, 0 },
>>>>>> { TEGRA210_CLK_I2C1, TEGRA210_CLK_PLL_P, 0, 0 },
>>>>>> { TEGRA210_CLK_I2C2, TEGRA210_CLK_PLL_P, 0, 0 },
>>>>>
>>>>> Should there be some dependency on say CONFIG_DEBUG_KERNEL? I am not
>>>>> sure we always want this on for all cases.
>>>>
>>>> Why would you not want it to be always on?
>>>
>>> Purely for power reasons. I do not know how much power keeping this
>>
>> I don't expect it to be significant but I don't have any numbers.
>>
>>> clock running consumes, but I don't like the idea of clocks running all
>>> the time when they are not needed.
>>
>> Problem is that in this case there is no easy way to determine if the clock
>> needs to be on.
>
> I had a similar issue with SH-Mobile AG5, where the power domain containing
> the JTAG interface is powered down.
This reminds me, does your patch assume that the DFD power domain is
enabled? I am guessing that it needs to be for JTAG to work.
Cheers
Jon
--
nvpublic
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH] clk: tegra: mark TEGRA210_CLK_DBGAPB as always on
@ 2017-03-08 10:13 ` Jon Hunter
0 siblings, 0 replies; 32+ messages in thread
From: Jon Hunter @ 2017-03-08 10:13 UTC (permalink / raw)
To: Geert Uytterhoeven, Peter De Schrijver
Cc: Prashant Gaikwad, Michael Turquette, Stephen Boyd,
Stephen Warren, Thierry Reding, Alexandre Courbot, linux-clk,
linux-tegra, linux-kernel
Hi Peter,
On 06/03/17 15:53, Geert Uytterhoeven wrote:
> Hi Peter,
>
> On Mon, Mar 6, 2017 at 3:28 PM, Peter De Schrijver
> <pdeschrijver@nvidia.com> wrote:
>> On Mon, Mar 06, 2017 at 09:58:29AM +0000, Jon Hunter wrote:
>>> On 06/03/17 08:38, Peter De Schrijver wrote:
>>>> On Thu, Mar 02, 2017 at 05:56:49PM +0000, Jon Hunter wrote:
>>>>> On 28/02/17 15:19, Peter De Schrijver wrote:
>>>>>> This is needed to make the JTAG debugging interface work.
>>>>>>
>>>>>> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
>>>>>> ---
>>>>>> drivers/clk/tegra/clk-tegra210.c | 1 +
>>>>>> 1 file changed, 1 insertion(+)
>>>>>>
>>>>>> diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
>>>>>> index 9a2512a..708f5f1 100644
>>>>>> --- a/drivers/clk/tegra/clk-tegra210.c
>>>>>> +++ b/drivers/clk/tegra/clk-tegra210.c
>>>>>> @@ -2680,6 +2680,7 @@ static void tegra210_cpu_clock_resume(void)
>>>>>> { TEGRA210_CLK_EMC, TEGRA210_CLK_CLK_MAX, 0, 1 },
>>>>>> { TEGRA210_CLK_MSELECT, TEGRA210_CLK_CLK_MAX, 0, 1 },
>>>>>> { TEGRA210_CLK_CSITE, TEGRA210_CLK_CLK_MAX, 0, 1 },
>>>>>> + { TEGRA210_CLK_DBGAPB, TEGRA210_CLK_CLK_MAX, 0, 1 },
>>>>>> { TEGRA210_CLK_TSENSOR, TEGRA210_CLK_CLK_M, 400000, 0 },
>>>>>> { TEGRA210_CLK_I2C1, TEGRA210_CLK_PLL_P, 0, 0 },
>>>>>> { TEGRA210_CLK_I2C2, TEGRA210_CLK_PLL_P, 0, 0 },
>>>>>
>>>>> Should there be some dependency on say CONFIG_DEBUG_KERNEL? I am not
>>>>> sure we always want this on for all cases.
>>>>
>>>> Why would you not want it to be always on?
>>>
>>> Purely for power reasons. I do not know how much power keeping this
>>
>> I don't expect it to be significant but I don't have any numbers.
>>
>>> clock running consumes, but I don't like the idea of clocks running all
>>> the time when they are not needed.
>>
>> Problem is that in this case there is no easy way to determine if the clock
>> needs to be on.
>
> I had a similar issue with SH-Mobile AG5, where the power domain containing
> the JTAG interface is powered down.
This reminds me, does your patch assume that the DFD power domain is
enabled? I am guessing that it needs to be for JTAG to work.
Cheers
Jon
--
nvpublic
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH] clk: tegra: mark TEGRA210_CLK_DBGAPB as always on
2017-03-08 10:13 ` Jon Hunter
(?)
@ 2017-03-08 11:38 ` Geert Uytterhoeven
2017-03-08 11:48 ` Jon Hunter
-1 siblings, 1 reply; 32+ messages in thread
From: Geert Uytterhoeven @ 2017-03-08 11:38 UTC (permalink / raw)
To: Jon Hunter
Cc: Peter De Schrijver, Prashant Gaikwad, Michael Turquette,
Stephen Boyd, Stephen Warren, Thierry Reding, Alexandre Courbot,
linux-clk, linux-tegra, linux-kernel
Hi Jon,
On Wed, Mar 8, 2017 at 11:13 AM, Jon Hunter <jonathanh@nvidia.com> wrote:
>> I had a similar issue with SH-Mobile AG5, where the power domain containing
>> the JTAG interface is powered down.
>
> This reminds me, does your patch assume that the DFD power domain is
> enabled? I am guessing that it needs to be for JTAG to work.
Yes. The pm-rmobile driver looks for "arm,coresight-etm3x" devices, and
marks the corresponding PM Domain as always-on, as long as the
Coresight code doesn't handle runtime PM.
For R-Mobile A1 and APE6 I already have added such device nodes, as any access
to a debug register hangs when the debug power domain is powered down.
For SH-Mobile AG5, I hadn't, as the debug power domain needs to be powered
for JTAG functionality only.
For the latter, perhaps we also need a command line parameter to change
a device status from "disabled" to "enabled"?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH] clk: tegra: mark TEGRA210_CLK_DBGAPB as always on
2017-03-08 11:38 ` Geert Uytterhoeven
@ 2017-03-08 11:48 ` Jon Hunter
0 siblings, 0 replies; 32+ messages in thread
From: Jon Hunter @ 2017-03-08 11:48 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Peter De Schrijver, Prashant Gaikwad, Michael Turquette,
Stephen Boyd, Stephen Warren, Thierry Reding, Alexandre Courbot,
linux-clk, linux-tegra, linux-kernel
On 08/03/17 11:38, Geert Uytterhoeven wrote:
> Hi Jon,
>
> On Wed, Mar 8, 2017 at 11:13 AM, Jon Hunter <jonathanh@nvidia.com> wrote:
>>> I had a similar issue with SH-Mobile AG5, where the power domain containing
>>> the JTAG interface is powered down.
>>
>> This reminds me, does your patch assume that the DFD power domain is
>> enabled? I am guessing that it needs to be for JTAG to work.
>
> Yes. The pm-rmobile driver looks for "arm,coresight-etm3x" devices, and
> marks the corresponding PM Domain as always-on, as long as the
> Coresight code doesn't handle runtime PM.
Sorry Geert, but I was asking Peter specifically about the power-domain
on Tegra as I have a feeling we may have the same scenario ;-)
Jon
--
nvpublic
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH] clk: tegra: mark TEGRA210_CLK_DBGAPB as always on
@ 2017-03-08 11:48 ` Jon Hunter
0 siblings, 0 replies; 32+ messages in thread
From: Jon Hunter @ 2017-03-08 11:48 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Peter De Schrijver, Prashant Gaikwad, Michael Turquette,
Stephen Boyd, Stephen Warren, Thierry Reding, Alexandre Courbot,
linux-clk, linux-tegra, linux-kernel
On 08/03/17 11:38, Geert Uytterhoeven wrote:
> Hi Jon,
>
> On Wed, Mar 8, 2017 at 11:13 AM, Jon Hunter <jonathanh@nvidia.com> wrote:
>>> I had a similar issue with SH-Mobile AG5, where the power domain containing
>>> the JTAG interface is powered down.
>>
>> This reminds me, does your patch assume that the DFD power domain is
>> enabled? I am guessing that it needs to be for JTAG to work.
>
> Yes. The pm-rmobile driver looks for "arm,coresight-etm3x" devices, and
> marks the corresponding PM Domain as always-on, as long as the
> Coresight code doesn't handle runtime PM.
Sorry Geert, but I was asking Peter specifically about the power-domain
on Tegra as I have a feeling we may have the same scenario ;-)
Jon
--
nvpublic
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH] clk: tegra: mark TEGRA210_CLK_DBGAPB as always on
2017-03-08 11:48 ` Jon Hunter
@ 2017-03-13 10:45 ` Peter De Schrijver
-1 siblings, 0 replies; 32+ messages in thread
From: Peter De Schrijver @ 2017-03-13 10:45 UTC (permalink / raw)
To: Jon Hunter
Cc: Geert Uytterhoeven, Prashant Gaikwad, Michael Turquette,
Stephen Boyd, Stephen Warren, Thierry Reding, Alexandre Courbot,
linux-clk, linux-tegra, linux-kernel
On Wed, Mar 08, 2017 at 11:48:21AM +0000, Jon Hunter wrote:
>
> On 08/03/17 11:38, Geert Uytterhoeven wrote:
> > Hi Jon,
> >
> > On Wed, Mar 8, 2017 at 11:13 AM, Jon Hunter <jonathanh@nvidia.com> wrote:
> >>> I had a similar issue with SH-Mobile AG5, where the power domain containing
> >>> the JTAG interface is powered down.
> >>
> >> This reminds me, does your patch assume that the DFD power domain is
> >> enabled? I am guessing that it needs to be for JTAG to work.
> >
> > Yes. The pm-rmobile driver looks for "arm,coresight-etm3x" devices, and
> > marks the corresponding PM Domain as always-on, as long as the
> > Coresight code doesn't handle runtime PM.
>
> Sorry Geert, but I was asking Peter specifically about the power-domain
> on Tegra as I have a feeling we may have the same scenario ;-)
We don't have a specific power domain for DFD on Tegra210. It's part of the
non-powergateable core domain.
Cheers,
Peter.
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH] clk: tegra: mark TEGRA210_CLK_DBGAPB as always on
@ 2017-03-13 10:45 ` Peter De Schrijver
0 siblings, 0 replies; 32+ messages in thread
From: Peter De Schrijver @ 2017-03-13 10:45 UTC (permalink / raw)
To: Jon Hunter
Cc: Geert Uytterhoeven, Prashant Gaikwad, Michael Turquette,
Stephen Boyd, Stephen Warren, Thierry Reding, Alexandre Courbot,
linux-clk, linux-tegra, linux-kernel
On Wed, Mar 08, 2017 at 11:48:21AM +0000, Jon Hunter wrote:
>
> On 08/03/17 11:38, Geert Uytterhoeven wrote:
> > Hi Jon,
> >
> > On Wed, Mar 8, 2017 at 11:13 AM, Jon Hunter <jonathanh@nvidia.com> wrote:
> >>> I had a similar issue with SH-Mobile AG5, where the power domain containing
> >>> the JTAG interface is powered down.
> >>
> >> This reminds me, does your patch assume that the DFD power domain is
> >> enabled? I am guessing that it needs to be for JTAG to work.
> >
> > Yes. The pm-rmobile driver looks for "arm,coresight-etm3x" devices, and
> > marks the corresponding PM Domain as always-on, as long as the
> > Coresight code doesn't handle runtime PM.
>
> Sorry Geert, but I was asking Peter specifically about the power-domain
> on Tegra as I have a feeling we may have the same scenario ;-)
We don't have a specific power domain for DFD on Tegra210. It's part of the
non-powergateable core domain.
Cheers,
Peter.
^ permalink raw reply [flat|nested] 32+ messages in thread
[parent not found: <20170313104532.GT26640-Rysk9IDjsxmJz7etNGeUX8VPkgjIgRvpAL8bYrjMMd8@public.gmane.org>]
* Re: [PATCH] clk: tegra: mark TEGRA210_CLK_DBGAPB as always on
2017-03-13 10:45 ` Peter De Schrijver
@ 2017-03-13 11:03 ` Jon Hunter
-1 siblings, 0 replies; 32+ messages in thread
From: Jon Hunter @ 2017-03-13 11:03 UTC (permalink / raw)
To: Peter De Schrijver
Cc: Geert Uytterhoeven, Prashant Gaikwad, Michael Turquette,
Stephen Boyd, Stephen Warren, Thierry Reding, Alexandre Courbot,
linux-clk, linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
On 13/03/17 10:45, Peter De Schrijver wrote:
> On Wed, Mar 08, 2017 at 11:48:21AM +0000, Jon Hunter wrote:
>>
>> On 08/03/17 11:38, Geert Uytterhoeven wrote:
>>> Hi Jon,
>>>
>>> On Wed, Mar 8, 2017 at 11:13 AM, Jon Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote:
>>>>> I had a similar issue with SH-Mobile AG5, where the power domain containing
>>>>> the JTAG interface is powered down.
>>>>
>>>> This reminds me, does your patch assume that the DFD power domain is
>>>> enabled? I am guessing that it needs to be for JTAG to work.
>>>
>>> Yes. The pm-rmobile driver looks for "arm,coresight-etm3x" devices, and
>>> marks the corresponding PM Domain as always-on, as long as the
>>> Coresight code doesn't handle runtime PM.
>>
>> Sorry Geert, but I was asking Peter specifically about the power-domain
>> on Tegra as I have a feeling we may have the same scenario ;-)
>
> We don't have a specific power domain for DFD on Tegra210. It's part of the
> non-powergateable core domain.
Either we are getting our wires crossed or the TRM is wrong :-(
static const char * const tegra210_powergates[] = {
[TEGRA_POWERGATE_CPU] = "crail",
[TEGRA_POWERGATE_3D] = "3d",
[TEGRA_POWERGATE_VENC] = "venc",
[TEGRA_POWERGATE_PCIE] = "pcie",
[TEGRA_POWERGATE_MPE] = "mpe",
[TEGRA_POWERGATE_SATA] = "sata",
[TEGRA_POWERGATE_CPU1] = "cpu1",
[TEGRA_POWERGATE_CPU2] = "cpu2",
[TEGRA_POWERGATE_CPU3] = "cpu3",
[TEGRA_POWERGATE_CPU0] = "cpu0",
[TEGRA_POWERGATE_C0NC] = "c0nc",
[TEGRA_POWERGATE_SOR] = "sor",
[TEGRA_POWERGATE_DIS] = "dis",
[TEGRA_POWERGATE_DISB] = "disb",
[TEGRA_POWERGATE_XUSBA] = "xusba",
[TEGRA_POWERGATE_XUSBB] = "xusbb",
[TEGRA_POWERGATE_XUSBC] = "xusbc",
[TEGRA_POWERGATE_VIC] = "vic",
[TEGRA_POWERGATE_IRAM] = "iram",
[TEGRA_POWERGATE_NVDEC] = "nvdec",
[TEGRA_POWERGATE_NVJPG] = "nvjpg",
[TEGRA_POWERGATE_AUD] = "aud",
[TEGRA_POWERGATE_DFD] = "dfd",
[TEGRA_POWERGATE_VE2] = "ve2",
};
Jon
--
nvpublic
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH] clk: tegra: mark TEGRA210_CLK_DBGAPB as always on
@ 2017-03-13 11:03 ` Jon Hunter
0 siblings, 0 replies; 32+ messages in thread
From: Jon Hunter @ 2017-03-13 11:03 UTC (permalink / raw)
To: Peter De Schrijver
Cc: Geert Uytterhoeven, Prashant Gaikwad, Michael Turquette,
Stephen Boyd, Stephen Warren, Thierry Reding, Alexandre Courbot,
linux-clk, linux-tegra, linux-kernel
On 13/03/17 10:45, Peter De Schrijver wrote:
> On Wed, Mar 08, 2017 at 11:48:21AM +0000, Jon Hunter wrote:
>>
>> On 08/03/17 11:38, Geert Uytterhoeven wrote:
>>> Hi Jon,
>>>
>>> On Wed, Mar 8, 2017 at 11:13 AM, Jon Hunter <jonathanh@nvidia.com> wrote:
>>>>> I had a similar issue with SH-Mobile AG5, where the power domain containing
>>>>> the JTAG interface is powered down.
>>>>
>>>> This reminds me, does your patch assume that the DFD power domain is
>>>> enabled? I am guessing that it needs to be for JTAG to work.
>>>
>>> Yes. The pm-rmobile driver looks for "arm,coresight-etm3x" devices, and
>>> marks the corresponding PM Domain as always-on, as long as the
>>> Coresight code doesn't handle runtime PM.
>>
>> Sorry Geert, but I was asking Peter specifically about the power-domain
>> on Tegra as I have a feeling we may have the same scenario ;-)
>
> We don't have a specific power domain for DFD on Tegra210. It's part of the
> non-powergateable core domain.
Either we are getting our wires crossed or the TRM is wrong :-(
static const char * const tegra210_powergates[] = {
[TEGRA_POWERGATE_CPU] = "crail",
[TEGRA_POWERGATE_3D] = "3d",
[TEGRA_POWERGATE_VENC] = "venc",
[TEGRA_POWERGATE_PCIE] = "pcie",
[TEGRA_POWERGATE_MPE] = "mpe",
[TEGRA_POWERGATE_SATA] = "sata",
[TEGRA_POWERGATE_CPU1] = "cpu1",
[TEGRA_POWERGATE_CPU2] = "cpu2",
[TEGRA_POWERGATE_CPU3] = "cpu3",
[TEGRA_POWERGATE_CPU0] = "cpu0",
[TEGRA_POWERGATE_C0NC] = "c0nc",
[TEGRA_POWERGATE_SOR] = "sor",
[TEGRA_POWERGATE_DIS] = "dis",
[TEGRA_POWERGATE_DISB] = "disb",
[TEGRA_POWERGATE_XUSBA] = "xusba",
[TEGRA_POWERGATE_XUSBB] = "xusbb",
[TEGRA_POWERGATE_XUSBC] = "xusbc",
[TEGRA_POWERGATE_VIC] = "vic",
[TEGRA_POWERGATE_IRAM] = "iram",
[TEGRA_POWERGATE_NVDEC] = "nvdec",
[TEGRA_POWERGATE_NVJPG] = "nvjpg",
[TEGRA_POWERGATE_AUD] = "aud",
[TEGRA_POWERGATE_DFD] = "dfd",
[TEGRA_POWERGATE_VE2] = "ve2",
};
Jon
--
nvpublic
^ permalink raw reply [flat|nested] 32+ messages in thread
[parent not found: <9e81c653-b6bb-a47c-8891-d7c7d42a7650-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>]
* Re: [PATCH] clk: tegra: mark TEGRA210_CLK_DBGAPB as always on
2017-03-13 11:03 ` Jon Hunter
@ 2017-03-13 14:18 ` Peter De Schrijver
-1 siblings, 0 replies; 32+ messages in thread
From: Peter De Schrijver @ 2017-03-13 14:18 UTC (permalink / raw)
To: Jon Hunter
Cc: Geert Uytterhoeven, Prashant Gaikwad, Michael Turquette,
Stephen Boyd, Stephen Warren, Thierry Reding, Alexandre Courbot,
linux-clk, linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
On Mon, Mar 13, 2017 at 11:03:27AM +0000, Jon Hunter wrote:
>
> On 13/03/17 10:45, Peter De Schrijver wrote:
> > On Wed, Mar 08, 2017 at 11:48:21AM +0000, Jon Hunter wrote:
> >>
> >> On 08/03/17 11:38, Geert Uytterhoeven wrote:
> >>> Hi Jon,
> >>>
> >>> On Wed, Mar 8, 2017 at 11:13 AM, Jon Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote:
> >>>>> I had a similar issue with SH-Mobile AG5, where the power domain containing
> >>>>> the JTAG interface is powered down.
> >>>>
> >>>> This reminds me, does your patch assume that the DFD power domain is
> >>>> enabled? I am guessing that it needs to be for JTAG to work.
> >>>
> >>> Yes. The pm-rmobile driver looks for "arm,coresight-etm3x" devices, and
> >>> marks the corresponding PM Domain as always-on, as long as the
> >>> Coresight code doesn't handle runtime PM.
> >>
> >> Sorry Geert, but I was asking Peter specifically about the power-domain
> >> on Tegra as I have a feeling we may have the same scenario ;-)
> >
> > We don't have a specific power domain for DFD on Tegra210. It's part of the
> > non-powergateable core domain.
>
> Either we are getting our wires crossed or the TRM is wrong :-(
>
> static const char * const tegra210_powergates[] = {
> [TEGRA_POWERGATE_CPU] = "crail",
> [TEGRA_POWERGATE_3D] = "3d",
> [TEGRA_POWERGATE_VENC] = "venc",
> [TEGRA_POWERGATE_PCIE] = "pcie",
> [TEGRA_POWERGATE_MPE] = "mpe",
> [TEGRA_POWERGATE_SATA] = "sata",
> [TEGRA_POWERGATE_CPU1] = "cpu1",
> [TEGRA_POWERGATE_CPU2] = "cpu2",
> [TEGRA_POWERGATE_CPU3] = "cpu3",
> [TEGRA_POWERGATE_CPU0] = "cpu0",
> [TEGRA_POWERGATE_C0NC] = "c0nc",
> [TEGRA_POWERGATE_SOR] = "sor",
> [TEGRA_POWERGATE_DIS] = "dis",
> [TEGRA_POWERGATE_DISB] = "disb",
> [TEGRA_POWERGATE_XUSBA] = "xusba",
> [TEGRA_POWERGATE_XUSBB] = "xusbb",
> [TEGRA_POWERGATE_XUSBC] = "xusbc",
> [TEGRA_POWERGATE_VIC] = "vic",
> [TEGRA_POWERGATE_IRAM] = "iram",
> [TEGRA_POWERGATE_NVDEC] = "nvdec",
> [TEGRA_POWERGATE_NVJPG] = "nvjpg",
> [TEGRA_POWERGATE_AUD] = "aud",
> [TEGRA_POWERGATE_DFD] = "dfd",
> [TEGRA_POWERGATE_VE2] = "ve2",
> };
>
This seems to exist indeed. However downstream has never used it, so I wonder
how well powergating this domain has been tested.
Peter.
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH] clk: tegra: mark TEGRA210_CLK_DBGAPB as always on
@ 2017-03-13 14:18 ` Peter De Schrijver
0 siblings, 0 replies; 32+ messages in thread
From: Peter De Schrijver @ 2017-03-13 14:18 UTC (permalink / raw)
To: Jon Hunter
Cc: Geert Uytterhoeven, Prashant Gaikwad, Michael Turquette,
Stephen Boyd, Stephen Warren, Thierry Reding, Alexandre Courbot,
linux-clk, linux-tegra, linux-kernel
On Mon, Mar 13, 2017 at 11:03:27AM +0000, Jon Hunter wrote:
>
> On 13/03/17 10:45, Peter De Schrijver wrote:
> > On Wed, Mar 08, 2017 at 11:48:21AM +0000, Jon Hunter wrote:
> >>
> >> On 08/03/17 11:38, Geert Uytterhoeven wrote:
> >>> Hi Jon,
> >>>
> >>> On Wed, Mar 8, 2017 at 11:13 AM, Jon Hunter <jonathanh@nvidia.com> wrote:
> >>>>> I had a similar issue with SH-Mobile AG5, where the power domain containing
> >>>>> the JTAG interface is powered down.
> >>>>
> >>>> This reminds me, does your patch assume that the DFD power domain is
> >>>> enabled? I am guessing that it needs to be for JTAG to work.
> >>>
> >>> Yes. The pm-rmobile driver looks for "arm,coresight-etm3x" devices, and
> >>> marks the corresponding PM Domain as always-on, as long as the
> >>> Coresight code doesn't handle runtime PM.
> >>
> >> Sorry Geert, but I was asking Peter specifically about the power-domain
> >> on Tegra as I have a feeling we may have the same scenario ;-)
> >
> > We don't have a specific power domain for DFD on Tegra210. It's part of the
> > non-powergateable core domain.
>
> Either we are getting our wires crossed or the TRM is wrong :-(
>
> static const char * const tegra210_powergates[] = {
> [TEGRA_POWERGATE_CPU] = "crail",
> [TEGRA_POWERGATE_3D] = "3d",
> [TEGRA_POWERGATE_VENC] = "venc",
> [TEGRA_POWERGATE_PCIE] = "pcie",
> [TEGRA_POWERGATE_MPE] = "mpe",
> [TEGRA_POWERGATE_SATA] = "sata",
> [TEGRA_POWERGATE_CPU1] = "cpu1",
> [TEGRA_POWERGATE_CPU2] = "cpu2",
> [TEGRA_POWERGATE_CPU3] = "cpu3",
> [TEGRA_POWERGATE_CPU0] = "cpu0",
> [TEGRA_POWERGATE_C0NC] = "c0nc",
> [TEGRA_POWERGATE_SOR] = "sor",
> [TEGRA_POWERGATE_DIS] = "dis",
> [TEGRA_POWERGATE_DISB] = "disb",
> [TEGRA_POWERGATE_XUSBA] = "xusba",
> [TEGRA_POWERGATE_XUSBB] = "xusbb",
> [TEGRA_POWERGATE_XUSBC] = "xusbc",
> [TEGRA_POWERGATE_VIC] = "vic",
> [TEGRA_POWERGATE_IRAM] = "iram",
> [TEGRA_POWERGATE_NVDEC] = "nvdec",
> [TEGRA_POWERGATE_NVJPG] = "nvjpg",
> [TEGRA_POWERGATE_AUD] = "aud",
> [TEGRA_POWERGATE_DFD] = "dfd",
> [TEGRA_POWERGATE_VE2] = "ve2",
> };
>
This seems to exist indeed. However downstream has never used it, so I wonder
how well powergating this domain has been tested.
Peter.
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH] clk: tegra: mark TEGRA210_CLK_DBGAPB as always on
2017-03-06 15:53 ` Geert Uytterhoeven
@ 2017-03-13 10:47 ` Peter De Schrijver
-1 siblings, 0 replies; 32+ messages in thread
From: Peter De Schrijver @ 2017-03-13 10:47 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Jon Hunter, Prashant Gaikwad, Michael Turquette, Stephen Boyd,
Stephen Warren, Thierry Reding, Alexandre Courbot, linux-clk,
linux-tegra, linux-kernel
On Mon, Mar 06, 2017 at 04:53:48PM +0100, Geert Uytterhoeven wrote:
> Hi Peter,
>
> On Mon, Mar 6, 2017 at 3:28 PM, Peter De Schrijver
> <pdeschrijver@nvidia.com> wrote:
> > On Mon, Mar 06, 2017 at 09:58:29AM +0000, Jon Hunter wrote:
> >> On 06/03/17 08:38, Peter De Schrijver wrote:
> >> > On Thu, Mar 02, 2017 at 05:56:49PM +0000, Jon Hunter wrote:
> >> >> On 28/02/17 15:19, Peter De Schrijver wrote:
> >> >>> This is needed to make the JTAG debugging interface work.
> >> >>>
> >> >>> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> >> >>> ---
> >> >>> drivers/clk/tegra/clk-tegra210.c | 1 +
> >> >>> 1 file changed, 1 insertion(+)
> >> >>>
> >> >>> diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
> >> >>> index 9a2512a..708f5f1 100644
> >> >>> --- a/drivers/clk/tegra/clk-tegra210.c
> >> >>> +++ b/drivers/clk/tegra/clk-tegra210.c
> >> >>> @@ -2680,6 +2680,7 @@ static void tegra210_cpu_clock_resume(void)
> >> >>> { TEGRA210_CLK_EMC, TEGRA210_CLK_CLK_MAX, 0, 1 },
> >> >>> { TEGRA210_CLK_MSELECT, TEGRA210_CLK_CLK_MAX, 0, 1 },
> >> >>> { TEGRA210_CLK_CSITE, TEGRA210_CLK_CLK_MAX, 0, 1 },
> >> >>> + { TEGRA210_CLK_DBGAPB, TEGRA210_CLK_CLK_MAX, 0, 1 },
> >> >>> { TEGRA210_CLK_TSENSOR, TEGRA210_CLK_CLK_M, 400000, 0 },
> >> >>> { TEGRA210_CLK_I2C1, TEGRA210_CLK_PLL_P, 0, 0 },
> >> >>> { TEGRA210_CLK_I2C2, TEGRA210_CLK_PLL_P, 0, 0 },
> >> >>
> >> >> Should there be some dependency on say CONFIG_DEBUG_KERNEL? I am not
> >> >> sure we always want this on for all cases.
> >> >
> >> > Why would you not want it to be always on?
> >>
> >> Purely for power reasons. I do not know how much power keeping this
> >
> > I don't expect it to be significant but I don't have any numbers.
> >
> >> clock running consumes, but I don't like the idea of clocks running all
> >> the time when they are not needed.
> >
> > Problem is that in this case there is no easy way to determine if the clock
> > needs to be on.
>
> I had a similar issue with SH-Mobile AG5, where the power domain containing
> the JTAG interface is powered down.
>
> [DEBUG] ARM: dts: sh73a0: Add minimal device node for Coresight-ETM
> https://patchwork.kernel.org/patch/8151511/
>
> Want to debug? Apply patch. I know it's not ideal...
>
Don't you always want to debug? :-)
Peter.
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH] clk: tegra: mark TEGRA210_CLK_DBGAPB as always on
@ 2017-03-13 10:47 ` Peter De Schrijver
0 siblings, 0 replies; 32+ messages in thread
From: Peter De Schrijver @ 2017-03-13 10:47 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Jon Hunter, Prashant Gaikwad, Michael Turquette, Stephen Boyd,
Stephen Warren, Thierry Reding, Alexandre Courbot, linux-clk,
linux-tegra, linux-kernel
On Mon, Mar 06, 2017 at 04:53:48PM +0100, Geert Uytterhoeven wrote:
> Hi Peter,
>
> On Mon, Mar 6, 2017 at 3:28 PM, Peter De Schrijver
> <pdeschrijver@nvidia.com> wrote:
> > On Mon, Mar 06, 2017 at 09:58:29AM +0000, Jon Hunter wrote:
> >> On 06/03/17 08:38, Peter De Schrijver wrote:
> >> > On Thu, Mar 02, 2017 at 05:56:49PM +0000, Jon Hunter wrote:
> >> >> On 28/02/17 15:19, Peter De Schrijver wrote:
> >> >>> This is needed to make the JTAG debugging interface work.
> >> >>>
> >> >>> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> >> >>> ---
> >> >>> drivers/clk/tegra/clk-tegra210.c | 1 +
> >> >>> 1 file changed, 1 insertion(+)
> >> >>>
> >> >>> diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
> >> >>> index 9a2512a..708f5f1 100644
> >> >>> --- a/drivers/clk/tegra/clk-tegra210.c
> >> >>> +++ b/drivers/clk/tegra/clk-tegra210.c
> >> >>> @@ -2680,6 +2680,7 @@ static void tegra210_cpu_clock_resume(void)
> >> >>> { TEGRA210_CLK_EMC, TEGRA210_CLK_CLK_MAX, 0, 1 },
> >> >>> { TEGRA210_CLK_MSELECT, TEGRA210_CLK_CLK_MAX, 0, 1 },
> >> >>> { TEGRA210_CLK_CSITE, TEGRA210_CLK_CLK_MAX, 0, 1 },
> >> >>> + { TEGRA210_CLK_DBGAPB, TEGRA210_CLK_CLK_MAX, 0, 1 },
> >> >>> { TEGRA210_CLK_TSENSOR, TEGRA210_CLK_CLK_M, 400000, 0 },
> >> >>> { TEGRA210_CLK_I2C1, TEGRA210_CLK_PLL_P, 0, 0 },
> >> >>> { TEGRA210_CLK_I2C2, TEGRA210_CLK_PLL_P, 0, 0 },
> >> >>
> >> >> Should there be some dependency on say CONFIG_DEBUG_KERNEL? I am not
> >> >> sure we always want this on for all cases.
> >> >
> >> > Why would you not want it to be always on?
> >>
> >> Purely for power reasons. I do not know how much power keeping this
> >
> > I don't expect it to be significant but I don't have any numbers.
> >
> >> clock running consumes, but I don't like the idea of clocks running all
> >> the time when they are not needed.
> >
> > Problem is that in this case there is no easy way to determine if the clock
> > needs to be on.
>
> I had a similar issue with SH-Mobile AG5, where the power domain containing
> the JTAG interface is powered down.
>
> [DEBUG] ARM: dts: sh73a0: Add minimal device node for Coresight-ETM
> https://patchwork.kernel.org/patch/8151511/
>
> Want to debug? Apply patch. I know it's not ideal...
>
Don't you always want to debug? :-)
Peter.
^ permalink raw reply [flat|nested] 32+ messages in thread