From: Andrew Lunn <andrew@lunn.ch>
To: Doug Berger <opendmb@gmail.com>
Cc: f.fainelli@gmail.com, robh+dt@kernel.org, mark.rutland@arm.com,
davem@davemloft.net, rafal@milecki.pl, xow@google.com,
joel@jms.id.au, jon.mason@broadcom.com, netdev@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
pgynther@google.com, jaedon.shin@gmail.com
Subject: Re: [PATCH net-next 02/12] net: phy: bcm7xxx: add support for 28nm EPHY
Date: Tue, 14 Mar 2017 02:06:51 +0100 [thread overview]
Message-ID: <20170314010651.GO15842@lunn.ch> (raw)
In-Reply-To: <20170314004142.4746-3-opendmb@gmail.com>
On Mon, Mar 13, 2017 at 05:41:32PM -0700, Doug Berger wrote:
> +static int bcm7xxx_28nm_ephy_01_afe_config_init(struct phy_device *phydev)
> +{
> + int ret;
> +
> + /* set shadow mode 2 */
> + ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,
> + MII_BCM7XXX_SHD_MODE_2, 0);
> + if (ret < 0)
> + return ret;
> +
> + /* Set current trim values INT_trim = -1, Ext_trim =0 */
> + ret = phy_write(phydev, MII_BCM7XXX_SHD_2_BIAS_TRIM, 0x3BE0);
> + if (ret < 0)
> + goto reset_shadow_mode;
> +
> + /* Cal reset */
> + ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
> + MII_BCM7XXX_SHD_3_TL4);
> + if (ret < 0)
> + goto reset_shadow_mode;
Hi Doug
It would be nice to have a few blank lines here and there...
> + ret = phy_set_clr_bits(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
> + MII_BCM7XXX_TL4_RST_MSK, 0);
> + if (ret < 0)
> + goto reset_shadow_mode;
> +
> + /* Cal reset disable */
> + ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
> + MII_BCM7XXX_SHD_3_TL4);
> + if (ret < 0)
> + goto reset_shadow_mode;
... just to break things up into readable chunks.
> + ret = phy_set_clr_bits(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
> + 0, MII_BCM7XXX_TL4_RST_MSK);
> + if (ret < 0)
> + goto reset_shadow_mode;
> +
> +reset_shadow_mode:
> + /* reset shadow mode 2 */
> + ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0,
> + MII_BCM7XXX_SHD_MODE_2);
> + if (ret < 0)
> + return ret;
> +
> + return 0;
How about:
return phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0,
MII_BCM7XXX_SHD_MODE_2);
> +/* The 28nm EPHY does not support Clause 45 (MMD) used by bcm-phy-lib */
> +static int bcm7xxx_28nm_ephy_apd_enable(struct phy_device *phydev)
> +{
> + int ret;
> +
> + /* set shadow mode 1 */
> + ret = phy_set_clr_bits(phydev, MII_BRCM_FET_BRCMTEST,
> + MII_BRCM_FET_BT_SRE, 0);
> + if (ret < 0)
> + return ret;
> +
> + /* Enable auto-power down */
> + ret = phy_set_clr_bits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2,
> + MII_BRCM_FET_SHDW_AS2_APDE, 0);
> + if (ret < 0)
> + return ret;
> +
> + /* reset shadow mode 1 */
> + ret = phy_set_clr_bits(phydev, MII_BRCM_FET_BRCMTEST, 0,
> + MII_BRCM_FET_BT_SRE);
> + if (ret < 0)
> + return ret;
> +
> + return 0;
How about just
return phy_set_clr_bits(phydev, MII_BRCM_FET_BRCMTEST, 0,
MII_BRCM_FET_BT_SRE);
> +}
> +
> +static int bcm7xxx_28nm_ephy_eee_enable(struct phy_device *phydev)
> +{
> + int ret;
> +
> + /* set shadow mode 2 */
> + ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,
> + MII_BCM7XXX_SHD_MODE_2, 0);
> + if (ret < 0)
> + return ret;
> +
> + /* Advertise supported modes */
> + ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
> + MII_BCM7XXX_SHD_3_AN_EEE_ADV);
> + if (ret < 0)
> + goto reset_shadow_mode;
blank...
> + ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
> + MDIO_EEE_100TX);
> + if (ret < 0)
> + goto reset_shadow_mode;
> +
> + /* Restore Defaults */
> + ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
> + MII_BCM7XXX_SHD_3_PCS_CTRL_2);
> + if (ret < 0)
> + goto reset_shadow_mode;
> + ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
> + MII_BCM7XXX_PCS_CTRL_2_DEF);
> + if (ret < 0)
> + goto reset_shadow_mode;
> +
> + ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
> + MII_BCM7XXX_SHD_3_EEE_THRESH);
> + if (ret < 0)
> + goto reset_shadow_mode;
> + ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
> + MII_BCM7XXX_EEE_THRESH_DEF);
> + if (ret < 0)
> + goto reset_shadow_mode;
> +
> + /* Enable EEE autonegotiation */
> + ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
> + MII_BCM7XXX_SHD_3_AN_STAT);
> + if (ret < 0)
> + goto reset_shadow_mode;
> + ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
> + (MII_BCM7XXX_AN_NULL_MSG_EN | MII_BCM7XXX_AN_EEE_EN));
> + if (ret < 0)
> + goto reset_shadow_mode;
> +
> +reset_shadow_mode:
> + /* reset shadow mode 2 */
> + ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0,
> + MII_BCM7XXX_SHD_MODE_2);
> + if (ret < 0)
> + return ret;
> +
> + /* Restart autoneg */
> + phy_write(phydev, MII_BMCR,
> + (BMCR_SPEED100 | BMCR_ANENABLE | BMCR_ANRESTART));
> +
> + return 0;
return phy_write(.....); ?
> +}
Andrew
WARNING: multiple messages have this Message-ID (diff)
From: Andrew Lunn <andrew-g2DYL2Zd6BY@public.gmane.org>
To: Doug Berger <opendmb-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: f.fainelli-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
mark.rutland-5wv7dgnIgG8@public.gmane.org,
davem-fT/PcQaiUtIeIZ0/mPfg9Q@public.gmane.org,
rafal-g1n6cQUeyibVItvQsEIGlw@public.gmane.org,
xow-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org,
joel-U3u1mxZcP9KHXe+LvDLADg@public.gmane.org,
jon.mason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org,
netdev-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
pgynther-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org,
jaedon.shin-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
Subject: Re: [PATCH net-next 02/12] net: phy: bcm7xxx: add support for 28nm EPHY
Date: Tue, 14 Mar 2017 02:06:51 +0100 [thread overview]
Message-ID: <20170314010651.GO15842@lunn.ch> (raw)
In-Reply-To: <20170314004142.4746-3-opendmb-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On Mon, Mar 13, 2017 at 05:41:32PM -0700, Doug Berger wrote:
> +static int bcm7xxx_28nm_ephy_01_afe_config_init(struct phy_device *phydev)
> +{
> + int ret;
> +
> + /* set shadow mode 2 */
> + ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,
> + MII_BCM7XXX_SHD_MODE_2, 0);
> + if (ret < 0)
> + return ret;
> +
> + /* Set current trim values INT_trim = -1, Ext_trim =0 */
> + ret = phy_write(phydev, MII_BCM7XXX_SHD_2_BIAS_TRIM, 0x3BE0);
> + if (ret < 0)
> + goto reset_shadow_mode;
> +
> + /* Cal reset */
> + ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
> + MII_BCM7XXX_SHD_3_TL4);
> + if (ret < 0)
> + goto reset_shadow_mode;
Hi Doug
It would be nice to have a few blank lines here and there...
> + ret = phy_set_clr_bits(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
> + MII_BCM7XXX_TL4_RST_MSK, 0);
> + if (ret < 0)
> + goto reset_shadow_mode;
> +
> + /* Cal reset disable */
> + ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
> + MII_BCM7XXX_SHD_3_TL4);
> + if (ret < 0)
> + goto reset_shadow_mode;
... just to break things up into readable chunks.
> + ret = phy_set_clr_bits(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
> + 0, MII_BCM7XXX_TL4_RST_MSK);
> + if (ret < 0)
> + goto reset_shadow_mode;
> +
> +reset_shadow_mode:
> + /* reset shadow mode 2 */
> + ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0,
> + MII_BCM7XXX_SHD_MODE_2);
> + if (ret < 0)
> + return ret;
> +
> + return 0;
How about:
return phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0,
MII_BCM7XXX_SHD_MODE_2);
> +/* The 28nm EPHY does not support Clause 45 (MMD) used by bcm-phy-lib */
> +static int bcm7xxx_28nm_ephy_apd_enable(struct phy_device *phydev)
> +{
> + int ret;
> +
> + /* set shadow mode 1 */
> + ret = phy_set_clr_bits(phydev, MII_BRCM_FET_BRCMTEST,
> + MII_BRCM_FET_BT_SRE, 0);
> + if (ret < 0)
> + return ret;
> +
> + /* Enable auto-power down */
> + ret = phy_set_clr_bits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2,
> + MII_BRCM_FET_SHDW_AS2_APDE, 0);
> + if (ret < 0)
> + return ret;
> +
> + /* reset shadow mode 1 */
> + ret = phy_set_clr_bits(phydev, MII_BRCM_FET_BRCMTEST, 0,
> + MII_BRCM_FET_BT_SRE);
> + if (ret < 0)
> + return ret;
> +
> + return 0;
How about just
return phy_set_clr_bits(phydev, MII_BRCM_FET_BRCMTEST, 0,
MII_BRCM_FET_BT_SRE);
> +}
> +
> +static int bcm7xxx_28nm_ephy_eee_enable(struct phy_device *phydev)
> +{
> + int ret;
> +
> + /* set shadow mode 2 */
> + ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,
> + MII_BCM7XXX_SHD_MODE_2, 0);
> + if (ret < 0)
> + return ret;
> +
> + /* Advertise supported modes */
> + ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
> + MII_BCM7XXX_SHD_3_AN_EEE_ADV);
> + if (ret < 0)
> + goto reset_shadow_mode;
blank...
> + ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
> + MDIO_EEE_100TX);
> + if (ret < 0)
> + goto reset_shadow_mode;
> +
> + /* Restore Defaults */
> + ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
> + MII_BCM7XXX_SHD_3_PCS_CTRL_2);
> + if (ret < 0)
> + goto reset_shadow_mode;
> + ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
> + MII_BCM7XXX_PCS_CTRL_2_DEF);
> + if (ret < 0)
> + goto reset_shadow_mode;
> +
> + ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
> + MII_BCM7XXX_SHD_3_EEE_THRESH);
> + if (ret < 0)
> + goto reset_shadow_mode;
> + ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
> + MII_BCM7XXX_EEE_THRESH_DEF);
> + if (ret < 0)
> + goto reset_shadow_mode;
> +
> + /* Enable EEE autonegotiation */
> + ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
> + MII_BCM7XXX_SHD_3_AN_STAT);
> + if (ret < 0)
> + goto reset_shadow_mode;
> + ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
> + (MII_BCM7XXX_AN_NULL_MSG_EN | MII_BCM7XXX_AN_EEE_EN));
> + if (ret < 0)
> + goto reset_shadow_mode;
> +
> +reset_shadow_mode:
> + /* reset shadow mode 2 */
> + ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0,
> + MII_BCM7XXX_SHD_MODE_2);
> + if (ret < 0)
> + return ret;
> +
> + /* Restart autoneg */
> + phy_write(phydev, MII_BMCR,
> + (BMCR_SPEED100 | BMCR_ANENABLE | BMCR_ANRESTART));
> +
> + return 0;
return phy_write(.....); ?
> +}
Andrew
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next prev parent reply other threads:[~2017-03-14 1:07 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-14 0:41 [PATCH net-next 00/12] net: bcmgenet: add support for GENETv5 Doug Berger
2017-03-14 0:41 ` Doug Berger
2017-03-14 0:41 ` [PATCH net-next 01/12] net: phy: bcm-phylib: replace obsolete EEE macro references Doug Berger
2017-03-14 0:49 ` Florian Fainelli
2017-03-14 0:49 ` Florian Fainelli
2017-03-14 0:41 ` [PATCH net-next 02/12] net: phy: bcm7xxx: add support for 28nm EPHY Doug Berger
2017-03-14 0:50 ` Florian Fainelli
2017-03-14 0:50 ` Florian Fainelli
2017-03-14 1:06 ` Andrew Lunn [this message]
2017-03-14 1:06 ` Andrew Lunn
2017-03-14 2:06 ` Doug Berger
2017-03-14 2:43 ` Andrew Lunn
2017-03-14 2:43 ` Andrew Lunn
2017-03-14 17:23 ` Doug Berger
2017-03-14 17:23 ` Doug Berger
2017-03-14 0:41 ` [PATCH net-next 03/12] net: bcmgenet: simplify circular pointer arithmetic Doug Berger
2017-03-14 0:54 ` Florian Fainelli
2017-03-14 0:54 ` Florian Fainelli
2017-03-14 0:41 ` [PATCH net-next 04/12] net: bcmgenet: remove meaningless lines Doug Berger
2017-03-14 0:55 ` Florian Fainelli
2017-03-14 0:55 ` Florian Fainelli
2017-03-14 0:41 ` [PATCH net-next 05/12] net: bcmgenet: manage dma interrupts in napi code Doug Berger
2017-03-14 0:55 ` Florian Fainelli
2017-03-14 0:41 ` [PATCH net-next 06/12] net: bcmgenet: remove handling of wol interrupts from isr0 Doug Berger
2017-03-14 0:41 ` Doug Berger
2017-03-14 0:56 ` Florian Fainelli
2017-03-14 0:56 ` Florian Fainelli
2017-03-14 0:41 ` [PATCH net-next 07/12] net: bcmgenet: clear status to reduce spurious interrupts Doug Berger
2017-03-14 0:56 ` Florian Fainelli
2017-03-14 0:56 ` Florian Fainelli
2017-03-14 0:41 ` [PATCH net-next 08/12] net: bcmgenet: correct return value of __bcmgenet_tx_reclaim Doug Berger
2017-03-14 0:57 ` Florian Fainelli
2017-03-14 0:41 ` [PATCH net-next 09/12] net: bcmgenet: return EOPNOTSUPP for unknown ioctl commands Doug Berger
2017-03-14 0:57 ` Florian Fainelli
2017-03-14 11:04 ` David Laight
2017-03-14 17:31 ` Doug Berger
2017-03-14 0:41 ` [PATCH net-next 10/12] dt-bindings: net: document bcmgenet WoL interrupt Doug Berger
2017-03-14 0:58 ` Florian Fainelli
2017-03-14 0:58 ` Florian Fainelli
2017-03-20 22:09 ` Rob Herring
2017-03-20 22:09 ` Rob Herring
2017-03-14 0:41 ` [PATCH net-next 11/12] dt-bindings: net: update bcmgenet binding for GENETv5 Doug Berger
2017-03-14 0:58 ` Florian Fainelli
2017-03-14 0:41 ` [PATCH net-next 12/12] net: bcmgenet: add support for the GENETv5 hardware Doug Berger
2017-03-14 0:59 ` Florian Fainelli
2017-03-14 0:59 ` Florian Fainelli
2017-03-14 4:53 ` [PATCH net-next 00/12] net: bcmgenet: add support for GENETv5 David Miller
2017-03-14 4:53 ` David Miller
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