From: Marc Zyngier <marc.zyngier@arm.com> To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Mark Rutland <mark.rutland@arm.com>, Catalin Marinas <catalin.marinas@arm.com>, Daniel Lezcano <daniel.lezcano@linaro.org>, Will Deacon <will.deacon@arm.com>, Scott Wood <oss@buserror.net>, Hanjun Guo <hanjun.guo@linaro.org>, Ding Tianhong <dingtianhong@huawei.com>, dann frazier <dann.frazier@canonical.com> Subject: [PATCH v2 00/18] clocksource/arch_timer: Errata workaround infrastructure rework Date: Mon, 20 Mar 2017 17:48:11 +0000 [thread overview] Message-ID: <20170320174829.28182-1-marc.zyngier@arm.com> (raw) It has recently become obvious that a number of arm64 systems have been blessed with a set of timers that are slightly less than perfect, and require a bit of hand-holding. We already have a bunch of errata-specific code to deal with this, but as we're adding more potential detection methods (DT, ACPI, capability), things are getting a bit out of hands. Instead of adding more ad-hoc fixes to an already difficult code base, let's give ourselves a bit of an infrastructure that can deal with this and hide most of the uggliness behind frendly accessors. The series is structured as such: - A bunch of arm64 specific patches that allow the rest of the workaround infrastructure to be built upon (such as being able to trap userspace access to the virtual counter). These are now separate in order to allow the creation of a shared branch between the arm64 and clocksource trees. - The following patches rework the existing workarounds, allowing errata to be matched using a given detection method - Another patch allows a workaround to affect a subset of the CPUs, and not the whole system - We then work around a Cortex-A73 erratum, whose counter can return a wrong value if read while crossing a 32bit boundary - Finally, we add some ACPI-specific workarounds for HiSilicon platforms that have the HISILICON_ERRATUM_161010101 defect. Note that so far, we only deal with arm64. Once the infrastructure is agreed upon, we can look at generalizing it (to some extent) to 32bit ARM (typical use case would be a 32bit guest running on an affected host). * From v1: - Addressed Hanjun and Mark review comments - Moved arm64 specific patches to the beginning of the series, leaving the clocksource patches at the end, resulting in an extra patch. - Added RBs, TBs, and Acks. Marc Zyngier (18): arm64: Allow checking of a CPU-local erratum arm64: Add CNTVCT_EL0 trap handler arm64: Define Cortex-A73 MIDR arm64: cpu_errata: Allow an erratum to be match for all revisions of a core arm64: cpu_errata: Add capability to advertise Cortex-A73 erratum 858921 arm64: arch_timer: Add infrastructure for multiple erratum detection methods arm64: arch_timer: Add erratum handler for globally defined capability arm64: arch_timer: Add erratum handler for CPU-specific capability arm64: arch_timer: Move arch_timer_reg_read/write around arm64: arch_timer: Get rid of erratum_workaround_set_sne arm64: arch_timer: Rework the set_next_event workarounds arm64: arch_timer: Make workaround methods optional arm64: arch_timer: Allows a CPU-specific erratum to only affect a subset of CPUs arm64: arch_timer: Move clocksource_counter and co around arm64: arch_timer: Enable CNTVCT_EL0 trap if workaround is enabled arm64: arch_timer: Workaround for Cortex-A73 erratum 858921 arm64: arch_timer: Allow erratum matching with ACPI OEM information arm64: arch_timer: Add HISILICON_ERRATUM_161010101 ACPI matching data Documentation/arm64/silicon-errata.txt | 1 + arch/arm64/include/asm/arch_timer.h | 44 ++- arch/arm64/include/asm/cpucaps.h | 3 +- arch/arm64/include/asm/cputype.h | 2 + arch/arm64/include/asm/esr.h | 2 + arch/arm64/kernel/cpu_errata.c | 15 + arch/arm64/kernel/cpufeature.c | 13 +- arch/arm64/kernel/traps.c | 14 + drivers/clocksource/Kconfig | 11 + drivers/clocksource/arm_arch_timer.c | 535 +++++++++++++++++++++++---------- 10 files changed, 471 insertions(+), 169 deletions(-) -- 2.11.0
WARNING: multiple messages have this Message-ID (diff)
From: marc.zyngier@arm.com (Marc Zyngier) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 00/18] clocksource/arch_timer: Errata workaround infrastructure rework Date: Mon, 20 Mar 2017 17:48:11 +0000 [thread overview] Message-ID: <20170320174829.28182-1-marc.zyngier@arm.com> (raw) It has recently become obvious that a number of arm64 systems have been blessed with a set of timers that are slightly less than perfect, and require a bit of hand-holding. We already have a bunch of errata-specific code to deal with this, but as we're adding more potential detection methods (DT, ACPI, capability), things are getting a bit out of hands. Instead of adding more ad-hoc fixes to an already difficult code base, let's give ourselves a bit of an infrastructure that can deal with this and hide most of the uggliness behind frendly accessors. The series is structured as such: - A bunch of arm64 specific patches that allow the rest of the workaround infrastructure to be built upon (such as being able to trap userspace access to the virtual counter). These are now separate in order to allow the creation of a shared branch between the arm64 and clocksource trees. - The following patches rework the existing workarounds, allowing errata to be matched using a given detection method - Another patch allows a workaround to affect a subset of the CPUs, and not the whole system - We then work around a Cortex-A73 erratum, whose counter can return a wrong value if read while crossing a 32bit boundary - Finally, we add some ACPI-specific workarounds for HiSilicon platforms that have the HISILICON_ERRATUM_161010101 defect. Note that so far, we only deal with arm64. Once the infrastructure is agreed upon, we can look at generalizing it (to some extent) to 32bit ARM (typical use case would be a 32bit guest running on an affected host). * From v1: - Addressed Hanjun and Mark review comments - Moved arm64 specific patches to the beginning of the series, leaving the clocksource patches at the end, resulting in an extra patch. - Added RBs, TBs, and Acks. Marc Zyngier (18): arm64: Allow checking of a CPU-local erratum arm64: Add CNTVCT_EL0 trap handler arm64: Define Cortex-A73 MIDR arm64: cpu_errata: Allow an erratum to be match for all revisions of a core arm64: cpu_errata: Add capability to advertise Cortex-A73 erratum 858921 arm64: arch_timer: Add infrastructure for multiple erratum detection methods arm64: arch_timer: Add erratum handler for globally defined capability arm64: arch_timer: Add erratum handler for CPU-specific capability arm64: arch_timer: Move arch_timer_reg_read/write around arm64: arch_timer: Get rid of erratum_workaround_set_sne arm64: arch_timer: Rework the set_next_event workarounds arm64: arch_timer: Make workaround methods optional arm64: arch_timer: Allows a CPU-specific erratum to only affect a subset of CPUs arm64: arch_timer: Move clocksource_counter and co around arm64: arch_timer: Enable CNTVCT_EL0 trap if workaround is enabled arm64: arch_timer: Workaround for Cortex-A73 erratum 858921 arm64: arch_timer: Allow erratum matching with ACPI OEM information arm64: arch_timer: Add HISILICON_ERRATUM_161010101 ACPI matching data Documentation/arm64/silicon-errata.txt | 1 + arch/arm64/include/asm/arch_timer.h | 44 ++- arch/arm64/include/asm/cpucaps.h | 3 +- arch/arm64/include/asm/cputype.h | 2 + arch/arm64/include/asm/esr.h | 2 + arch/arm64/kernel/cpu_errata.c | 15 + arch/arm64/kernel/cpufeature.c | 13 +- arch/arm64/kernel/traps.c | 14 + drivers/clocksource/Kconfig | 11 + drivers/clocksource/arm_arch_timer.c | 535 +++++++++++++++++++++++---------- 10 files changed, 471 insertions(+), 169 deletions(-) -- 2.11.0
next reply other threads:[~2017-03-20 17:48 UTC|newest] Thread overview: 88+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-03-20 17:48 Marc Zyngier [this message] 2017-03-20 17:48 ` [PATCH v2 00/18] clocksource/arch_timer: Errata workaround infrastructure rework Marc Zyngier 2017-03-20 17:48 ` [PATCH v2 01/18] arm64: Allow checking of a CPU-local erratum Marc Zyngier 2017-03-20 17:48 ` Marc Zyngier 2017-03-22 9:22 ` Daniel Lezcano 2017-03-22 9:22 ` Daniel Lezcano 2017-03-20 17:48 ` [PATCH v2 02/18] arm64: Add CNTVCT_EL0 trap handler Marc Zyngier 2017-03-20 17:48 ` Marc Zyngier 2017-03-20 17:48 ` [PATCH v2 03/18] arm64: Define Cortex-A73 MIDR Marc Zyngier 2017-03-20 17:48 ` Marc Zyngier 2017-03-20 17:48 ` [PATCH v2 04/18] arm64: cpu_errata: Allow an erratum to be match for all revisions of a core Marc Zyngier 2017-03-20 17:48 ` Marc Zyngier 2017-03-22 14:57 ` Daniel Lezcano 2017-03-22 14:57 ` Daniel Lezcano 2017-03-20 17:48 ` [PATCH v2 05/18] arm64: cpu_errata: Add capability to advertise Cortex-A73 erratum 858921 Marc Zyngier 2017-03-20 17:48 ` Marc Zyngier 2017-03-22 15:01 ` Daniel Lezcano 2017-03-22 15:01 ` Daniel Lezcano 2017-03-20 17:48 ` [PATCH v2 06/18] arm64: arch_timer: Add infrastructure for multiple erratum detection methods Marc Zyngier 2017-03-20 17:48 ` Marc Zyngier 2017-03-22 15:41 ` Daniel Lezcano 2017-03-22 15:41 ` Daniel Lezcano 2017-03-22 15:53 ` Marc Zyngier 2017-03-22 15:53 ` Marc Zyngier 2017-03-22 15:59 ` Marc Zyngier 2017-03-22 15:59 ` Marc Zyngier 2017-03-22 16:52 ` Daniel Lezcano 2017-03-22 16:52 ` Daniel Lezcano 2017-03-23 17:30 ` Daniel Lezcano 2017-03-23 17:30 ` Daniel Lezcano 2017-03-24 13:51 ` Marc Zyngier 2017-03-24 13:51 ` Marc Zyngier 2017-03-27 7:56 ` Daniel Lezcano 2017-03-27 7:56 ` Daniel Lezcano 2017-03-28 13:07 ` Marc Zyngier 2017-03-28 13:07 ` Marc Zyngier 2017-03-28 13:34 ` Daniel Lezcano 2017-03-28 13:34 ` Daniel Lezcano 2017-03-28 14:07 ` Marc Zyngier 2017-03-28 14:07 ` Marc Zyngier 2017-03-28 14:36 ` Daniel Lezcano 2017-03-28 14:36 ` Daniel Lezcano 2017-03-28 14:48 ` Marc Zyngier 2017-03-28 14:48 ` Marc Zyngier 2017-03-28 14:55 ` Daniel Lezcano 2017-03-28 14:55 ` Daniel Lezcano 2017-03-28 15:38 ` Marc Zyngier 2017-03-28 15:38 ` Marc Zyngier 2017-03-29 14:27 ` Daniel Lezcano 2017-03-29 14:27 ` Daniel Lezcano 2017-03-29 14:56 ` Marc Zyngier 2017-03-29 14:56 ` Marc Zyngier 2017-03-29 15:12 ` Daniel Lezcano 2017-03-29 15:12 ` Daniel Lezcano 2017-03-24 17:48 ` dann frazier 2017-03-24 17:48 ` dann frazier 2017-03-24 18:00 ` Marc Zyngier 2017-03-24 18:00 ` Marc Zyngier 2017-03-30 9:28 ` Daniel Lezcano 2017-03-30 9:28 ` Daniel Lezcano 2017-03-20 17:48 ` [PATCH v2 07/18] arm64: arch_timer: Add erratum handler for globally defined capability Marc Zyngier 2017-03-20 17:48 ` Marc Zyngier 2017-03-20 17:48 ` [PATCH v2 08/18] arm64: arch_timer: Add erratum handler for CPU-specific capability Marc Zyngier 2017-03-20 17:48 ` Marc Zyngier 2017-03-20 17:48 ` [PATCH v2 09/18] arm64: arch_timer: Move arch_timer_reg_read/write around Marc Zyngier 2017-03-20 17:48 ` Marc Zyngier 2017-03-22 15:47 ` Daniel Lezcano 2017-03-22 15:47 ` Daniel Lezcano 2017-03-20 17:48 ` [PATCH v2 10/18] arm64: arch_timer: Get rid of erratum_workaround_set_sne Marc Zyngier 2017-03-20 17:48 ` Marc Zyngier 2017-03-20 17:48 ` [PATCH v2 11/18] arm64: arch_timer: Rework the set_next_event workarounds Marc Zyngier 2017-03-20 17:48 ` Marc Zyngier 2017-03-20 17:48 ` [PATCH v2 12/18] arm64: arch_timer: Make workaround methods optional Marc Zyngier 2017-03-20 17:48 ` Marc Zyngier 2017-03-20 17:48 ` [PATCH v2 13/18] arm64: arch_timer: Allows a CPU-specific erratum to only affect a subset of CPUs Marc Zyngier 2017-03-20 17:48 ` Marc Zyngier 2017-03-20 17:48 ` [PATCH v2 14/18] arm64: arch_timer: Move clocksource_counter and co around Marc Zyngier 2017-03-20 17:48 ` Marc Zyngier 2017-03-20 17:48 ` [PATCH v2 15/18] arm64: arch_timer: Enable CNTVCT_EL0 trap if workaround is enabled Marc Zyngier 2017-03-20 17:48 ` Marc Zyngier 2017-03-20 17:48 ` [PATCH v2 16/18] arm64: arch_timer: Workaround for Cortex-A73 erratum 858921 Marc Zyngier 2017-03-20 17:48 ` Marc Zyngier 2017-03-20 17:48 ` [PATCH v2 17/18] arm64: arch_timer: Allow erratum matching with ACPI OEM information Marc Zyngier 2017-03-20 17:48 ` Marc Zyngier 2017-03-20 17:48 ` [PATCH v2 18/18] arm64: arch_timer: Add HISILICON_ERRATUM_161010101 ACPI matching data Marc Zyngier 2017-03-20 17:48 ` Marc Zyngier 2017-03-22 13:56 ` [PATCH v2 00/18] clocksource/arch_timer: Errata workaround infrastructure rework Ding Tianhong 2017-03-22 13:56 ` Ding Tianhong
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20170320174829.28182-1-marc.zyngier@arm.com \ --to=marc.zyngier@arm.com \ --cc=catalin.marinas@arm.com \ --cc=daniel.lezcano@linaro.org \ --cc=dann.frazier@canonical.com \ --cc=dingtianhong@huawei.com \ --cc=hanjun.guo@linaro.org \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-kernel@vger.kernel.org \ --cc=mark.rutland@arm.com \ --cc=oss@buserror.net \ --cc=will.deacon@arm.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.