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From: Ralf Baechle <ralf@linux-mips.org>
To: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org, "Paolo Bonzini" <pbonzini@redhat.com>,
	"Radim Krčmář" <rkrcmar@redhat.com>,
	kvm@vger.kernel.org, "# 3 . 10 . x-" <stable@vger.kernel.org>
Subject: Re: [PATCH 1/2] KVM: MIPS/Emulate: Fix TLBWR with wired for T&E
Date: Tue, 21 Mar 2017 20:50:02 +0100	[thread overview]
Message-ID: <20170321195002.GA9697@linux-mips.org> (raw)
In-Reply-To: <8083c96f7d942288a45a5f23d7bfd39bfceb273e.1489510483.git-series.james.hogan@imgtec.com>

On Tue, Mar 14, 2017 at 05:00:07PM +0000, James Hogan wrote:

> The implementation of the TLBWR instruction for Trap & Emulate does not
> take the CP0_Wired register into account, allowing the guest's wired
> entries to be easily overwritten during normal guest TLB refill
> operation.
> 
> Offset the random TLB index by CP0_Wired and keep it in the range of
> valid non-wired entries with a modulo operation instead of a mask. This
> allows wired TLB entries to be properly preserved.
> 
> Fixes: e685c689f3a8 ("KVM/MIPS32: Privileged instruction/target ...")
> Signed-off-by: James Hogan <james.hogan@imgtec.com>
> Cc: Paolo Bonzini <pbonzini@redhat.com>
> Cc: "Radim Krčmář" <rkrcmar@redhat.com>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> Cc: linux-mips@linux-mips.org
> Cc: kvm@vger.kernel.org
> Cc: <stable@vger.kernel.org> # 3.10.x-
> ---
>  arch/mips/kvm/emulate.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/mips/kvm/emulate.c b/arch/mips/kvm/emulate.c
> index 4833ebad89d9..dd47f2bda01b 100644
> --- a/arch/mips/kvm/emulate.c
> +++ b/arch/mips/kvm/emulate.c
> @@ -1094,10 +1094,12 @@ enum emulation_result kvm_mips_emul_tlbwr(struct kvm_vcpu *vcpu)
>  	struct mips_coproc *cop0 = vcpu->arch.cop0;
>  	struct kvm_mips_tlb *tlb = NULL;
>  	unsigned long pc = vcpu->arch.pc;
> +	unsigned int wired;
>  	int index;
>  
>  	get_random_bytes(&index, sizeof(index));
> -	index &= (KVM_MIPS_GUEST_TLB_SIZE - 1);
> +	wired = kvm_read_c0_guest_wired(cop0) & (KVM_MIPS_GUEST_TLB_SIZE - 1);
> +	index = wired + index % (KVM_MIPS_GUEST_TLB_SIZE - wired);

FWIW, the "random" register is just a counter on all MIPS CPUs which will
wrap around to the value of the wired register rsp. 8 on some R3000-class
CPUs once it reaches the number of TLB entries, so get_random_bytes isn't
strictly correct.  I however can't see any problem with this implementatio
other than get_random_bytes might be a a bit heavier than necessary.

Acked-by: Ralf Baechle <ralf@linux-mips.org>

  Ralf

  reply	other threads:[~2017-03-21 19:50 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-03-14 17:00 [PATCH 0/2] KVM: MIPS/Emulate: TLBWR & TLBR fixes for T&E James Hogan
2017-03-14 17:00 ` James Hogan
2017-03-14 17:00 ` [PATCH 1/2] KVM: MIPS/Emulate: Fix TLBWR with wired " James Hogan
2017-03-14 17:00   ` James Hogan
2017-03-21 19:50   ` Ralf Baechle [this message]
2017-03-14 17:00 ` [PATCH 2/2] KVM: MIPS/Emulate: Properly implement TLBR " James Hogan
2017-03-14 17:00   ` James Hogan
2017-03-21 19:55   ` Ralf Baechle

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