* [PATCH 0/2] KVM: MIPS/Emulate: TLBWR & TLBR fixes for T&E @ 2017-03-14 17:00 ` James Hogan 0 siblings, 0 replies; 8+ messages in thread From: James Hogan @ 2017-03-14 17:00 UTC (permalink / raw) To: linux-mips Cc: James Hogan, Paolo Bonzini, Radim Krčmář, Ralf Baechle, kvm, stable These two patches fix TLBWR and TLBR instruction emulation for Trap & Emulate guests, so that wired entries are properly preserved and so that the entries can be read back by the guest itself. Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: "Radim Krčmář" <rkrcmar@redhat.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Cc: stable@vger.kernel.org James Hogan (2): KVM: MIPS/Emulate: Fix TLBWR with wired for T&E KVM: MIPS/Emulate: Properly implement TLBR for T&E arch/mips/kvm/emulate.c | 103 ++++++++++++++++++++++------------------- 1 file changed, 56 insertions(+), 47 deletions(-) -- git-series 0.8.10 ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 0/2] KVM: MIPS/Emulate: TLBWR & TLBR fixes for T&E @ 2017-03-14 17:00 ` James Hogan 0 siblings, 0 replies; 8+ messages in thread From: James Hogan @ 2017-03-14 17:00 UTC (permalink / raw) To: linux-mips Cc: James Hogan, Paolo Bonzini, Radim Krčmář, Ralf Baechle, kvm, stable These two patches fix TLBWR and TLBR instruction emulation for Trap & Emulate guests, so that wired entries are properly preserved and so that the entries can be read back by the guest itself. Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: "Radim Krčmář" <rkrcmar@redhat.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Cc: stable@vger.kernel.org James Hogan (2): KVM: MIPS/Emulate: Fix TLBWR with wired for T&E KVM: MIPS/Emulate: Properly implement TLBR for T&E arch/mips/kvm/emulate.c | 103 ++++++++++++++++++++++------------------- 1 file changed, 56 insertions(+), 47 deletions(-) -- git-series 0.8.10 ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 1/2] KVM: MIPS/Emulate: Fix TLBWR with wired for T&E @ 2017-03-14 17:00 ` James Hogan 0 siblings, 0 replies; 8+ messages in thread From: James Hogan @ 2017-03-14 17:00 UTC (permalink / raw) To: linux-mips Cc: James Hogan, Paolo Bonzini, Radim Krčmář, Ralf Baechle, kvm, # 3 . 10 . x- The implementation of the TLBWR instruction for Trap & Emulate does not take the CP0_Wired register into account, allowing the guest's wired entries to be easily overwritten during normal guest TLB refill operation. Offset the random TLB index by CP0_Wired and keep it in the range of valid non-wired entries with a modulo operation instead of a mask. This allows wired TLB entries to be properly preserved. Fixes: e685c689f3a8 ("KVM/MIPS32: Privileged instruction/target ...") Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: "Radim Krčmář" <rkrcmar@redhat.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Cc: <stable@vger.kernel.org> # 3.10.x- --- arch/mips/kvm/emulate.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/mips/kvm/emulate.c b/arch/mips/kvm/emulate.c index 4833ebad89d9..dd47f2bda01b 100644 --- a/arch/mips/kvm/emulate.c +++ b/arch/mips/kvm/emulate.c @@ -1094,10 +1094,12 @@ enum emulation_result kvm_mips_emul_tlbwr(struct kvm_vcpu *vcpu) struct mips_coproc *cop0 = vcpu->arch.cop0; struct kvm_mips_tlb *tlb = NULL; unsigned long pc = vcpu->arch.pc; + unsigned int wired; int index; get_random_bytes(&index, sizeof(index)); - index &= (KVM_MIPS_GUEST_TLB_SIZE - 1); + wired = kvm_read_c0_guest_wired(cop0) & (KVM_MIPS_GUEST_TLB_SIZE - 1); + index = wired + index % (KVM_MIPS_GUEST_TLB_SIZE - wired); tlb = &vcpu->arch.guest_tlb[index]; -- git-series 0.8.10 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 1/2] KVM: MIPS/Emulate: Fix TLBWR with wired for T&E @ 2017-03-14 17:00 ` James Hogan 0 siblings, 0 replies; 8+ messages in thread From: James Hogan @ 2017-03-14 17:00 UTC (permalink / raw) To: linux-mips Cc: James Hogan, Paolo Bonzini, Radim Krčmář, Ralf Baechle, kvm, # 3 . 10 . x- The implementation of the TLBWR instruction for Trap & Emulate does not take the CP0_Wired register into account, allowing the guest's wired entries to be easily overwritten during normal guest TLB refill operation. Offset the random TLB index by CP0_Wired and keep it in the range of valid non-wired entries with a modulo operation instead of a mask. This allows wired TLB entries to be properly preserved. Fixes: e685c689f3a8 ("KVM/MIPS32: Privileged instruction/target ...") Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: "Radim Krčmář" <rkrcmar@redhat.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Cc: <stable@vger.kernel.org> # 3.10.x- --- arch/mips/kvm/emulate.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/mips/kvm/emulate.c b/arch/mips/kvm/emulate.c index 4833ebad89d9..dd47f2bda01b 100644 --- a/arch/mips/kvm/emulate.c +++ b/arch/mips/kvm/emulate.c @@ -1094,10 +1094,12 @@ enum emulation_result kvm_mips_emul_tlbwr(struct kvm_vcpu *vcpu) struct mips_coproc *cop0 = vcpu->arch.cop0; struct kvm_mips_tlb *tlb = NULL; unsigned long pc = vcpu->arch.pc; + unsigned int wired; int index; get_random_bytes(&index, sizeof(index)); - index &= (KVM_MIPS_GUEST_TLB_SIZE - 1); + wired = kvm_read_c0_guest_wired(cop0) & (KVM_MIPS_GUEST_TLB_SIZE - 1); + index = wired + index % (KVM_MIPS_GUEST_TLB_SIZE - wired); tlb = &vcpu->arch.guest_tlb[index]; -- git-series 0.8.10 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] KVM: MIPS/Emulate: Fix TLBWR with wired for T&E 2017-03-14 17:00 ` James Hogan (?) @ 2017-03-21 19:50 ` Ralf Baechle -1 siblings, 0 replies; 8+ messages in thread From: Ralf Baechle @ 2017-03-21 19:50 UTC (permalink / raw) To: James Hogan Cc: linux-mips, Paolo Bonzini, Radim Krčmář, kvm, # 3 . 10 . x- On Tue, Mar 14, 2017 at 05:00:07PM +0000, James Hogan wrote: > The implementation of the TLBWR instruction for Trap & Emulate does not > take the CP0_Wired register into account, allowing the guest's wired > entries to be easily overwritten during normal guest TLB refill > operation. > > Offset the random TLB index by CP0_Wired and keep it in the range of > valid non-wired entries with a modulo operation instead of a mask. This > allows wired TLB entries to be properly preserved. > > Fixes: e685c689f3a8 ("KVM/MIPS32: Privileged instruction/target ...") > Signed-off-by: James Hogan <james.hogan@imgtec.com> > Cc: Paolo Bonzini <pbonzini@redhat.com> > Cc: "Radim Krčmář" <rkrcmar@redhat.com> > Cc: Ralf Baechle <ralf@linux-mips.org> > Cc: linux-mips@linux-mips.org > Cc: kvm@vger.kernel.org > Cc: <stable@vger.kernel.org> # 3.10.x- > --- > arch/mips/kvm/emulate.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/arch/mips/kvm/emulate.c b/arch/mips/kvm/emulate.c > index 4833ebad89d9..dd47f2bda01b 100644 > --- a/arch/mips/kvm/emulate.c > +++ b/arch/mips/kvm/emulate.c > @@ -1094,10 +1094,12 @@ enum emulation_result kvm_mips_emul_tlbwr(struct kvm_vcpu *vcpu) > struct mips_coproc *cop0 = vcpu->arch.cop0; > struct kvm_mips_tlb *tlb = NULL; > unsigned long pc = vcpu->arch.pc; > + unsigned int wired; > int index; > > get_random_bytes(&index, sizeof(index)); > - index &= (KVM_MIPS_GUEST_TLB_SIZE - 1); > + wired = kvm_read_c0_guest_wired(cop0) & (KVM_MIPS_GUEST_TLB_SIZE - 1); > + index = wired + index % (KVM_MIPS_GUEST_TLB_SIZE - wired); FWIW, the "random" register is just a counter on all MIPS CPUs which will wrap around to the value of the wired register rsp. 8 on some R3000-class CPUs once it reaches the number of TLB entries, so get_random_bytes isn't strictly correct. I however can't see any problem with this implementatio other than get_random_bytes might be a a bit heavier than necessary. Acked-by: Ralf Baechle <ralf@linux-mips.org> Ralf ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 2/2] KVM: MIPS/Emulate: Properly implement TLBR for T&E @ 2017-03-14 17:00 ` James Hogan 0 siblings, 0 replies; 8+ messages in thread From: James Hogan @ 2017-03-14 17:00 UTC (permalink / raw) To: linux-mips Cc: James Hogan, Paolo Bonzini, Radim Krčmář, Ralf Baechle, kvm Properly implement emulation of the TLBR instruction for Trap & Emulate. This instruction reads the TLB entry pointed at by the CP0_Index register into the other TLB registers, which may have the side effect of changing the current ASID. Therefore abstract the CP0_EntryHi and ASID changing code into a common function in the process. A comment indicated that Linux doesn't use TLBR, which is true during normal use, however dumping of the TLB does use it (for example with the relatively recent 'x' magic sysrq key), as does a wired TLB entries test case in my KVM tests. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: "Radim Krčmář" <rkrcmar@redhat.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org --- arch/mips/kvm/emulate.c | 99 +++++++++++++++++++++-------------------- 1 file changed, 53 insertions(+), 46 deletions(-) diff --git a/arch/mips/kvm/emulate.c b/arch/mips/kvm/emulate.c index dd47f2bda01b..e82630b93270 100644 --- a/arch/mips/kvm/emulate.c +++ b/arch/mips/kvm/emulate.c @@ -990,17 +990,62 @@ enum emulation_result kvm_mips_emul_wait(struct kvm_vcpu *vcpu) return EMULATE_DONE; } -/* - * XXXKYMA: Linux doesn't seem to use TLBR, return EMULATE_FAIL for now so that - * we can catch this, if things ever change - */ +static void kvm_mips_change_entryhi(struct kvm_vcpu *vcpu, + unsigned long entryhi) +{ + struct mips_coproc *cop0 = vcpu->arch.cop0; + struct mm_struct *kern_mm = &vcpu->arch.guest_kernel_mm; + int cpu, i; + u32 nasid = entryhi & KVM_ENTRYHI_ASID; + + if (((kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID) != nasid)) { + trace_kvm_asid_change(vcpu, kvm_read_c0_guest_entryhi(cop0) & + KVM_ENTRYHI_ASID, nasid); + + /* + * Flush entries from the GVA page tables. + * Guest user page table will get flushed lazily on re-entry to + * guest user if the guest ASID actually changes. + */ + kvm_mips_flush_gva_pt(kern_mm->pgd, KMF_KERN); + + /* + * Regenerate/invalidate kernel MMU context. + * The user MMU context will be regenerated lazily on re-entry + * to guest user if the guest ASID actually changes. + */ + preempt_disable(); + cpu = smp_processor_id(); + get_new_mmu_context(kern_mm, cpu); + for_each_possible_cpu(i) + if (i != cpu) + cpu_context(i, kern_mm) = 0; + preempt_enable(); + } + kvm_write_c0_guest_entryhi(cop0, entryhi); +} + enum emulation_result kvm_mips_emul_tlbr(struct kvm_vcpu *vcpu) { struct mips_coproc *cop0 = vcpu->arch.cop0; + struct kvm_mips_tlb *tlb; unsigned long pc = vcpu->arch.pc; + int index; - kvm_err("[%#lx] COP0_TLBR [%d]\n", pc, kvm_read_c0_guest_index(cop0)); - return EMULATE_FAIL; + index = kvm_read_c0_guest_index(cop0); + if (index < 0 || index >= KVM_MIPS_GUEST_TLB_SIZE) { + /* UNDEFINED */ + kvm_debug("[%#lx] TLBR Index %#x out of range\n", pc, index); + index &= KVM_MIPS_GUEST_TLB_SIZE - 1; + } + + tlb = &vcpu->arch.guest_tlb[index]; + kvm_write_c0_guest_pagemask(cop0, tlb->tlb_mask); + kvm_write_c0_guest_entrylo0(cop0, tlb->tlb_lo[0]); + kvm_write_c0_guest_entrylo1(cop0, tlb->tlb_lo[1]); + kvm_mips_change_entryhi(vcpu, tlb->tlb_hi); + + return EMULATE_DONE; } /** @@ -1224,11 +1269,9 @@ enum emulation_result kvm_mips_emulate_CP0(union mips_instruction inst, struct kvm_vcpu *vcpu) { struct mips_coproc *cop0 = vcpu->arch.cop0; - struct mm_struct *kern_mm = &vcpu->arch.guest_kernel_mm; enum emulation_result er = EMULATE_DONE; u32 rt, rd, sel; unsigned long curr_pc; - int cpu, i; /* * Update PC and hold onto current PC in case there is @@ -1330,44 +1373,8 @@ enum emulation_result kvm_mips_emulate_CP0(union mips_instruction inst, kvm_change_c0_guest_ebase(cop0, 0x1ffff000, vcpu->arch.gprs[rt]); } else if (rd == MIPS_CP0_TLB_HI && sel == 0) { - u32 nasid = - vcpu->arch.gprs[rt] & KVM_ENTRYHI_ASID; - if (((kvm_read_c0_guest_entryhi(cop0) & - KVM_ENTRYHI_ASID) != nasid)) { - trace_kvm_asid_change(vcpu, - kvm_read_c0_guest_entryhi(cop0) - & KVM_ENTRYHI_ASID, - nasid); - - /* - * Flush entries from the GVA page - * tables. - * Guest user page table will get - * flushed lazily on re-entry to guest - * user if the guest ASID actually - * changes. - */ - kvm_mips_flush_gva_pt(kern_mm->pgd, - KMF_KERN); - - /* - * Regenerate/invalidate kernel MMU - * context. - * The user MMU context will be - * regenerated lazily on re-entry to - * guest user if the guest ASID actually - * changes. - */ - preempt_disable(); - cpu = smp_processor_id(); - get_new_mmu_context(kern_mm, cpu); - for_each_possible_cpu(i) - if (i != cpu) - cpu_context(i, kern_mm) = 0; - preempt_enable(); - } - kvm_write_c0_guest_entryhi(cop0, - vcpu->arch.gprs[rt]); + kvm_mips_change_entryhi(vcpu, + vcpu->arch.gprs[rt]); } /* Are we writing to COUNT */ else if ((rd == MIPS_CP0_COUNT) && (sel == 0)) { -- git-series 0.8.10 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 2/2] KVM: MIPS/Emulate: Properly implement TLBR for T&E @ 2017-03-14 17:00 ` James Hogan 0 siblings, 0 replies; 8+ messages in thread From: James Hogan @ 2017-03-14 17:00 UTC (permalink / raw) To: linux-mips Cc: James Hogan, Paolo Bonzini, Radim Krčmář, Ralf Baechle, kvm Properly implement emulation of the TLBR instruction for Trap & Emulate. This instruction reads the TLB entry pointed at by the CP0_Index register into the other TLB registers, which may have the side effect of changing the current ASID. Therefore abstract the CP0_EntryHi and ASID changing code into a common function in the process. A comment indicated that Linux doesn't use TLBR, which is true during normal use, however dumping of the TLB does use it (for example with the relatively recent 'x' magic sysrq key), as does a wired TLB entries test case in my KVM tests. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: "Radim Krčmář" <rkrcmar@redhat.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org --- arch/mips/kvm/emulate.c | 99 +++++++++++++++++++++-------------------- 1 file changed, 53 insertions(+), 46 deletions(-) diff --git a/arch/mips/kvm/emulate.c b/arch/mips/kvm/emulate.c index dd47f2bda01b..e82630b93270 100644 --- a/arch/mips/kvm/emulate.c +++ b/arch/mips/kvm/emulate.c @@ -990,17 +990,62 @@ enum emulation_result kvm_mips_emul_wait(struct kvm_vcpu *vcpu) return EMULATE_DONE; } -/* - * XXXKYMA: Linux doesn't seem to use TLBR, return EMULATE_FAIL for now so that - * we can catch this, if things ever change - */ +static void kvm_mips_change_entryhi(struct kvm_vcpu *vcpu, + unsigned long entryhi) +{ + struct mips_coproc *cop0 = vcpu->arch.cop0; + struct mm_struct *kern_mm = &vcpu->arch.guest_kernel_mm; + int cpu, i; + u32 nasid = entryhi & KVM_ENTRYHI_ASID; + + if (((kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID) != nasid)) { + trace_kvm_asid_change(vcpu, kvm_read_c0_guest_entryhi(cop0) & + KVM_ENTRYHI_ASID, nasid); + + /* + * Flush entries from the GVA page tables. + * Guest user page table will get flushed lazily on re-entry to + * guest user if the guest ASID actually changes. + */ + kvm_mips_flush_gva_pt(kern_mm->pgd, KMF_KERN); + + /* + * Regenerate/invalidate kernel MMU context. + * The user MMU context will be regenerated lazily on re-entry + * to guest user if the guest ASID actually changes. + */ + preempt_disable(); + cpu = smp_processor_id(); + get_new_mmu_context(kern_mm, cpu); + for_each_possible_cpu(i) + if (i != cpu) + cpu_context(i, kern_mm) = 0; + preempt_enable(); + } + kvm_write_c0_guest_entryhi(cop0, entryhi); +} + enum emulation_result kvm_mips_emul_tlbr(struct kvm_vcpu *vcpu) { struct mips_coproc *cop0 = vcpu->arch.cop0; + struct kvm_mips_tlb *tlb; unsigned long pc = vcpu->arch.pc; + int index; - kvm_err("[%#lx] COP0_TLBR [%d]\n", pc, kvm_read_c0_guest_index(cop0)); - return EMULATE_FAIL; + index = kvm_read_c0_guest_index(cop0); + if (index < 0 || index >= KVM_MIPS_GUEST_TLB_SIZE) { + /* UNDEFINED */ + kvm_debug("[%#lx] TLBR Index %#x out of range\n", pc, index); + index &= KVM_MIPS_GUEST_TLB_SIZE - 1; + } + + tlb = &vcpu->arch.guest_tlb[index]; + kvm_write_c0_guest_pagemask(cop0, tlb->tlb_mask); + kvm_write_c0_guest_entrylo0(cop0, tlb->tlb_lo[0]); + kvm_write_c0_guest_entrylo1(cop0, tlb->tlb_lo[1]); + kvm_mips_change_entryhi(vcpu, tlb->tlb_hi); + + return EMULATE_DONE; } /** @@ -1224,11 +1269,9 @@ enum emulation_result kvm_mips_emulate_CP0(union mips_instruction inst, struct kvm_vcpu *vcpu) { struct mips_coproc *cop0 = vcpu->arch.cop0; - struct mm_struct *kern_mm = &vcpu->arch.guest_kernel_mm; enum emulation_result er = EMULATE_DONE; u32 rt, rd, sel; unsigned long curr_pc; - int cpu, i; /* * Update PC and hold onto current PC in case there is @@ -1330,44 +1373,8 @@ enum emulation_result kvm_mips_emulate_CP0(union mips_instruction inst, kvm_change_c0_guest_ebase(cop0, 0x1ffff000, vcpu->arch.gprs[rt]); } else if (rd == MIPS_CP0_TLB_HI && sel == 0) { - u32 nasid = - vcpu->arch.gprs[rt] & KVM_ENTRYHI_ASID; - if (((kvm_read_c0_guest_entryhi(cop0) & - KVM_ENTRYHI_ASID) != nasid)) { - trace_kvm_asid_change(vcpu, - kvm_read_c0_guest_entryhi(cop0) - & KVM_ENTRYHI_ASID, - nasid); - - /* - * Flush entries from the GVA page - * tables. - * Guest user page table will get - * flushed lazily on re-entry to guest - * user if the guest ASID actually - * changes. - */ - kvm_mips_flush_gva_pt(kern_mm->pgd, - KMF_KERN); - - /* - * Regenerate/invalidate kernel MMU - * context. - * The user MMU context will be - * regenerated lazily on re-entry to - * guest user if the guest ASID actually - * changes. - */ - preempt_disable(); - cpu = smp_processor_id(); - get_new_mmu_context(kern_mm, cpu); - for_each_possible_cpu(i) - if (i != cpu) - cpu_context(i, kern_mm) = 0; - preempt_enable(); - } - kvm_write_c0_guest_entryhi(cop0, - vcpu->arch.gprs[rt]); + kvm_mips_change_entryhi(vcpu, + vcpu->arch.gprs[rt]); } /* Are we writing to COUNT */ else if ((rd == MIPS_CP0_COUNT) && (sel == 0)) { -- git-series 0.8.10 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2] KVM: MIPS/Emulate: Properly implement TLBR for T&E 2017-03-14 17:00 ` James Hogan (?) @ 2017-03-21 19:55 ` Ralf Baechle -1 siblings, 0 replies; 8+ messages in thread From: Ralf Baechle @ 2017-03-21 19:55 UTC (permalink / raw) To: James Hogan; +Cc: linux-mips, Paolo Bonzini, Radim Krčmář, kvm On Tue, Mar 14, 2017 at 05:00:08PM +0000, James Hogan wrote: > Properly implement emulation of the TLBR instruction for Trap & Emulate. > This instruction reads the TLB entry pointed at by the CP0_Index > register into the other TLB registers, which may have the side effect of > changing the current ASID. Therefore abstract the CP0_EntryHi and ASID > changing code into a common function in the process. > > A comment indicated that Linux doesn't use TLBR, which is true during > normal use, however dumping of the TLB does use it (for example with the > relatively recent 'x' magic sysrq key), as does a wired TLB entries test > case in my KVM tests. Acked-by: Ralf Baechle <ralf@linux-mips.org> Ralf ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2017-03-21 19:55 UTC | newest] Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2017-03-14 17:00 [PATCH 0/2] KVM: MIPS/Emulate: TLBWR & TLBR fixes for T&E James Hogan 2017-03-14 17:00 ` James Hogan 2017-03-14 17:00 ` [PATCH 1/2] KVM: MIPS/Emulate: Fix TLBWR with wired " James Hogan 2017-03-14 17:00 ` James Hogan 2017-03-21 19:50 ` Ralf Baechle 2017-03-14 17:00 ` [PATCH 2/2] KVM: MIPS/Emulate: Properly implement TLBR " James Hogan 2017-03-14 17:00 ` James Hogan 2017-03-21 19:55 ` Ralf Baechle
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.