[PATCH] drm/i915/guc: limit forcewake to blitter domain in guc_send

[PATCH] drm/i915/guc: limit forcewake to blitter domain in guc_send

[Daniele Ceraolo Spurio]

The forcewake_get call in the guc_send_mmio function was added to
avoid getting and releasing forcewake on each register access.
While this makes sense, all GuC registers are in the blitter range
so no need to wake all the wells.

Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
 drivers/gpu/drm/i915/intel_uc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 4a872cd..e016227 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -245,7 +245,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len)
 		return -EINVAL;
 
 	mutex_lock(&guc->send_mutex);
-	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_BLITTER);
 
 	dev_priv->guc.action_count += 1;
 	dev_priv->guc.action_cmd = action[0];
@@ -283,7 +283,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len)
 	}
 	dev_priv->guc.action_status = status;
 
-	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_BLITTER);
 	mutex_unlock(&guc->send_mutex);
 
 	return ret;
-- 
1.9.1

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✓ Fi.CI.BAT: success for drm/i915/guc: limit forcewake to blitter domain in guc_send

[Patchwork]

== Series Details ==

Series: drm/i915/guc: limit forcewake to blitter domain in guc_send
URL   : https://patchwork.freedesktop.org/series/21834/
State : success

== Summary ==

Series 21834v1 drm/i915/guc: limit forcewake to blitter domain in guc_send
https://patchwork.freedesktop.org/api/1.0/series/21834/revisions/1/mbox/

fi-bdw-5557u     total:278  pass:267  dwarn:0   dfail:0   fail:0   skip:11  time: 455s
fi-bdw-gvtdvm    total:278  pass:256  dwarn:8   dfail:0   fail:0   skip:14  time: 453s
fi-bsw-n3050     total:278  pass:239  dwarn:0   dfail:0   fail:0   skip:39  time: 541s
fi-bxt-j4205     total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19  time: 544s
fi-bxt-t5700     total:278  pass:258  dwarn:0   dfail:0   fail:0   skip:20  time: 565s
fi-byt-j1900     total:278  pass:251  dwarn:0   dfail:0   fail:0   skip:27  time: 507s
fi-byt-n2820     total:278  pass:247  dwarn:0   dfail:0   fail:0   skip:31  time: 500s
fi-hsw-4770      total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  time: 434s
fi-hsw-4770r     total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  time: 431s
fi-ilk-650       total:278  pass:228  dwarn:0   dfail:0   fail:0   skip:50  time: 448s
fi-ivb-3520m     total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  time: 519s
fi-ivb-3770      total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  time: 500s
fi-kbl-7500u     total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  time: 484s
fi-skl-6260u     total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  time: 489s
fi-skl-6700hq    total:278  pass:261  dwarn:0   dfail:0   fail:0   skip:17  time: 613s
fi-skl-6700k     total:278  pass:256  dwarn:4   dfail:0   fail:0   skip:18  time: 486s
fi-skl-6770hq    total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  time: 512s
fi-skl-gvtdvm    total:278  pass:265  dwarn:0   dfail:0   fail:0   skip:13  time: 462s
fi-snb-2520m     total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  time: 551s
fi-snb-2600      total:278  pass:249  dwarn:0   dfail:0   fail:0   skip:29  time: 414s

fd27e1e4c9b5dc11966b4953432bd6e0510da308 drm-tip: 2017y-03m-24d-08h-39m-20s UTC integration manifest
429dcea drm/i915/guc: limit forcewake to blitter domain in guc_send

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4294/
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Re: [PATCH] drm/i915/guc: limit forcewake to blitter domain in guc_send

[Kamble, Sagar A]

[-- Attachment #1.1: Type: text/plain, Size: 1416 bytes --]

Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>

On 3/24/2017 8:18 PM, Daniele Ceraolo Spurio wrote:
> The forcewake_get call in the guc_send_mmio function was added to
> avoid getting and releasing forcewake on each register access.
> While this makes sense, all GuC registers are in the blitter range
> so no need to wake all the wells.
>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_uc.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
> index 4a872cd..e016227 100644
> --- a/drivers/gpu/drm/i915/intel_uc.c
> +++ b/drivers/gpu/drm/i915/intel_uc.c
> @@ -245,7 +245,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len)
>   		return -EINVAL;
>   
>   	mutex_lock(&guc->send_mutex);
> -	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> +	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_BLITTER);
>   
>   	dev_priv->guc.action_count += 1;
>   	dev_priv->guc.action_cmd = action[0];
> @@ -283,7 +283,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len)
>   	}
>   	dev_priv->guc.action_status = status;
>   
> -	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> +	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_BLITTER);
>   	mutex_unlock(&guc->send_mutex);
>   
>   	return ret;


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Re: [PATCH] drm/i915/guc: limit forcewake to blitter domain in guc_send

[Chris Wilson]

On Fri, Mar 24, 2017 at 09:12:13PM +0530, Kamble, Sagar A wrote:
>    Reviewed-by: Sagar Arun Kamble [1]<sagar.a.kamble@intel.com>

and pushed.

Sagar, you might want to turn off sending html email for intel-gfx@.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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