* [Qemu-devel] [PATCH 01/21] ppc/pnv: Add cut down PSI bridge model and hookup external interrupt
2017-04-05 12:41 [Qemu-devel] [PATCH 00/21] pnv: PSI, OCC, IPMI and PCI models Cédric Le Goater
@ 2017-04-05 12:41 ` Cédric Le Goater
2017-04-05 12:41 ` [Qemu-devel] [PATCH 02/21] ppc/pnv: Add OCC model stub with interrupt support Cédric Le Goater
` (19 subsequent siblings)
20 siblings, 0 replies; 66+ messages in thread
From: Cédric Le Goater @ 2017-04-05 12:41 UTC (permalink / raw)
To: David Gibson
Cc: qemu-ppc, qemu-devel, Cédric Le Goater, Benjamin Herrenschmidt
The Processor Service Interface (PSI) Controller is one of the engines
of the "Bridge" unit which connects the different interfaces to the
Power Processor.
This adds just enough of the PSI bridge to handle various on-chip and
the one external interrupt. The rest of PSI has to do with the link to
the IBM FSP service processor which we don't plan to emulate (not used
on OpenPower machines).
The ics_get() and ics_resend() handlers of the XICSFabric interface of
the PowerNV machine are now defined to handle the Interrupt Control
Source of PSI. The InterruptStatsProvider interface is also modified
to dump the new ICS.
Originally from Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
The fact that the FSP and PSI interrupts are muxed makes the routine
pnv_psi_irq_set() a little difficult to follow. I didn't do any
better when I tried to be more explicit.
Changes since last version (I lost track) :
- took ownership
- introduced the ics_get() and ics_resend() handlers for the
XICSFabric interface
- introduced the handler for the InterruptStatsProvider interface
- add more comments on the register definitions
- removed the PSIHB_MMIO_ definitions which were not used
- fixed mask in pnv_psi_set_cr()
- fixed mask in pnv_psi_set_irsn()
- removed pnv_psi_irq_bits() and introduced per-irq number arrays to
retrieve the xivr, the control register and the status bit in
pnv_psi_irq_set().
- pnv_psi_set_xivr() :
. simplified the checks done on the server number, now that the
XICSFabric handles PIR CPU numbers
. handled pending bit when IRQ is masked
. removed FW workaround. Not needed anymore.
- added some more error handling in case of bad register usage and
off the limits IRQ numbers
- improved initial settings of the XIVR
- QOM'ified the ICS creation
- changed to become a SysBusDevice
- added properties to set the BAR
- added multi chip support
hw/ppc/Makefile.objs | 2 +-
hw/ppc/pnv.c | 65 +++++-
hw/ppc/pnv_psi.c | 571 +++++++++++++++++++++++++++++++++++++++++++++
include/hw/ppc/pnv.h | 13 ++
include/hw/ppc/pnv_psi.h | 67 ++++++
include/hw/ppc/pnv_xscom.h | 3 +
6 files changed, 714 insertions(+), 7 deletions(-)
create mode 100644 hw/ppc/pnv_psi.c
create mode 100644 include/hw/ppc/pnv_psi.h
diff --git a/hw/ppc/Makefile.objs b/hw/ppc/Makefile.objs
index 001293423c8d..dc19ee17fa57 100644
--- a/hw/ppc/Makefile.objs
+++ b/hw/ppc/Makefile.objs
@@ -6,7 +6,7 @@ obj-$(CONFIG_PSERIES) += spapr_hcall.o spapr_iommu.o spapr_rtas.o
obj-$(CONFIG_PSERIES) += spapr_pci.o spapr_rtc.o spapr_drc.o spapr_rng.o
obj-$(CONFIG_PSERIES) += spapr_cpu_core.o spapr_ovec.o
# IBM PowerNV
-obj-$(CONFIG_POWERNV) += pnv.o pnv_xscom.o pnv_core.o pnv_lpc.o
+obj-$(CONFIG_POWERNV) += pnv.o pnv_xscom.o pnv_core.o pnv_lpc.o pnv_psi.o
ifeq ($(CONFIG_PCI)$(CONFIG_PSERIES)$(CONFIG_LINUX), yyy)
obj-y += spapr_pci_vfio.o
endif
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 903bbac03fcc..5c90ac6ad950 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -353,15 +353,22 @@ static void ppc_powernv_reset(void)
* have a CPLD that will collect the SerIRQ and shoot them as a
* single level interrupt to the P8 chip. So let's setup a hook
* for doing just that.
- *
- * Note: The actual interrupt input isn't emulated yet, this will
- * come with the PSI bridge model.
*/
static void pnv_lpc_isa_irq_handler_cpld(void *opaque, int n, int level)
{
- /* We don't yet emulate the PSI bridge which provides the external
- * interrupt, so just drop interrupts on the floor
- */
+ PnvMachineState *pnv = POWERNV_MACHINE(qdev_get_machine());
+ uint32_t old_state = pnv->cpld_irqstate;
+ PnvChip *chip = opaque;
+
+ if (level) {
+ pnv->cpld_irqstate |= 1u << n;
+ } else {
+ pnv->cpld_irqstate &= ~(1u << n);
+ }
+ if (pnv->cpld_irqstate != old_state) {
+ pnv_psi_irq_set(&chip->psi, PSIHB_IRQ_EXTERNAL,
+ pnv->cpld_irqstate != 0);
+ }
}
static void pnv_lpc_isa_irq_handler(void *opaque, int n, int level)
@@ -682,6 +689,11 @@ static void pnv_chip_init(Object *obj)
object_initialize(&chip->lpc, sizeof(chip->lpc), TYPE_PNV_LPC);
object_property_add_child(obj, "lpc", OBJECT(&chip->lpc), NULL);
+
+ object_initialize(&chip->psi, sizeof(chip->psi), TYPE_PNV_PSI);
+ object_property_add_child(obj, "psi", OBJECT(&chip->psi), NULL);
+ object_property_add_const_link(OBJECT(&chip->psi), "xics",
+ OBJECT(qdev_get_machine()), &error_abort);
}
static void pnv_chip_icp_realize(PnvChip *chip, Error **errp)
@@ -794,6 +806,16 @@ static void pnv_chip_realize(DeviceState *dev, Error **errp)
error_propagate(errp, error);
return;
}
+
+ /* Processor Service Interface (PSI) Host Bridge */
+ object_property_set_int(OBJECT(&chip->psi), PNV_PSIHB_BASE(chip),
+ "bar", &error_fatal);
+ object_property_set_bool(OBJECT(&chip->psi), true, "realized", &error);
+ if (error) {
+ error_propagate(errp, error);
+ return;
+ }
+ pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, &chip->psi.xscom_regs);
}
static Property pnv_chip_properties[] = {
@@ -823,6 +845,29 @@ static const TypeInfo pnv_chip_info = {
.abstract = true,
};
+static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
+{
+ PnvMachineState *pnv = POWERNV_MACHINE(xi);
+ int i;
+
+ for (i = 0; i < pnv->num_chips; i++) {
+ if (ics_valid_irq(&pnv->chips[i]->psi.ics, irq)) {
+ return &pnv->chips[i]->psi.ics;
+ }
+ }
+ return NULL;
+}
+
+static void pnv_ics_resend(XICSFabric *xi)
+{
+ PnvMachineState *pnv = POWERNV_MACHINE(xi);
+ int i;
+
+ for (i = 0; i < pnv->num_chips; i++) {
+ ics_resend(&pnv->chips[i]->psi.ics);
+ }
+}
+
static PowerPCCPU *ppc_get_vcpu_by_pir(int pir)
{
CPUState *cs;
@@ -849,6 +894,8 @@ static ICPState *pnv_icp_get(XICSFabric *xi, int pir)
static void pnv_pic_print_info(InterruptStatsProvider *obj,
Monitor *mon)
{
+ PnvMachineState *pnv = POWERNV_MACHINE(obj);
+ int i;
CPUState *cs;
CPU_FOREACH(cs) {
@@ -856,6 +903,10 @@ static void pnv_pic_print_info(InterruptStatsProvider *obj,
icp_pic_print_info(ICP(cpu->intc), mon);
}
+
+ for (i = 0; i < pnv->num_chips; i++) {
+ ics_pic_print_info(&pnv->chips[i]->psi.ics, mon);
+ }
}
static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name,
@@ -921,6 +972,8 @@ static void powernv_machine_class_init(ObjectClass *oc, void *data)
mc->default_boot_order = NULL;
mc->default_ram_size = 1 * G_BYTE;
xic->icp_get = pnv_icp_get;
+ xic->ics_get = pnv_ics_get;
+ xic->ics_resend = pnv_ics_resend;
ispc->print_info = pnv_pic_print_info;
powernv_machine_class_props_init(oc);
diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c
new file mode 100644
index 000000000000..2bf5bfe3fdd6
--- /dev/null
+++ b/hw/ppc/pnv_psi.c
@@ -0,0 +1,571 @@
+/*
+ * QEMU PowerPC PowerNV Processor Service Interface (PSI) model
+ *
+ * Copyright (c) 2015-2017, IBM Corporation.
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/hw.h"
+#include "target/ppc/cpu.h"
+#include "qemu/log.h"
+#include "qapi/error.h"
+
+#include "exec/address-spaces.h"
+
+#include "hw/ppc/fdt.h"
+#include "hw/ppc/pnv.h"
+#include "hw/ppc/pnv_xscom.h"
+#include "hw/ppc/pnv_psi.h"
+
+#include <libfdt.h>
+
+#define PSIHB_XSCOM_FIR_RW 0x00
+#define PSIHB_XSCOM_FIR_AND 0x01
+#define PSIHB_XSCOM_FIR_OR 0x02
+#define PSIHB_XSCOM_FIRMASK_RW 0x03
+#define PSIHB_XSCOM_FIRMASK_AND 0x04
+#define PSIHB_XSCOM_FIRMASK_OR 0x05
+#define PSIHB_XSCOM_FIRACT0 0x06
+#define PSIHB_XSCOM_FIRACT1 0x07
+
+/* Host Bridge Base Address Register */
+#define PSIHB_XSCOM_BAR 0x0a
+#define PSIHB_BAR_EN 0x0000000000000001ull
+
+/* FSP Base Address Register */
+#define PSIHB_XSCOM_FSPBAR 0x0b
+
+/* PSI Host Bridge Control/Status Register */
+#define PSIHB_XSCOM_CR 0x0e
+#define PSIHB_CR_FSP_CMD_ENABLE 0x8000000000000000ull
+#define PSIHB_CR_FSP_MMIO_ENABLE 0x4000000000000000ull
+#define PSIHB_CR_FSP_IRQ_ENABLE 0x1000000000000000ull
+#define PSIHB_CR_FSP_ERR_RSP_ENABLE 0x0800000000000000ull
+#define PSIHB_CR_PSI_LINK_ENABLE 0x0400000000000000ull
+#define PSIHB_CR_FSP_RESET 0x0200000000000000ull
+#define PSIHB_CR_PSIHB_RESET 0x0100000000000000ull
+#define PSIHB_CR_PSI_IRQ 0x0000800000000000ull
+#define PSIHB_CR_FSP_IRQ 0x0000400000000000ull
+#define PSIHB_CR_FSP_LINK_ACTIVE 0x0000200000000000ull
+#define PSIHB_CR_IRQ_CMD_EXPECT 0x0000010000000000ull
+ /* and more ... */
+
+/* PSIHB Status / Error Mask Register */
+#define PSIHB_XSCOM_SEMR 0x0f
+
+/* XIVR, to signal interrupts to the CEC firmware. more XIVR below. */
+#define PSIHB_XSCOM_XIVR_FSP 0x10
+#define PSIHB_XIVR_SERVER_SH 40
+#define PSIHB_XIVR_SERVER_MSK (0xffffull << PSIHB_XIVR_SERVER_SH)
+#define PSIHB_XIVR_PRIO_SH 32
+#define PSIHB_XIVR_PRIO_MSK (0xffull << PSIHB_XIVR_PRIO_SH)
+#define PSIHB_XIVR_SRC_SH 29
+#define PSIHB_XIVR_SRC_MSK (0x7ull << PSIHB_XIVR_SRC_SH)
+#define PSIHB_XIVR_PENDING 0x01000000ull
+
+/* PSI Host Bridge Set Control/ Status Register */
+#define PSIHB_XSCOM_SCR 0x12
+
+/* PSI Host Bridge Clear Control/ Status Register */
+#define PSIHB_XSCOM_CCR 0x13
+
+/* DMA Upper Address Register */
+#define PSIHB_XSCOM_DMA_UPADD 0x14
+
+/* Interrupt Status */
+#define PSIHB_XSCOM_IRQ_STAT 0x15
+#define PSIHB_IRQ_STAT_OCC 0x0000001000000000ull
+#define PSIHB_IRQ_STAT_FSI 0x0000000800000000ull
+#define PSIHB_IRQ_STAT_LPCI2C 0x0000000400000000ull
+#define PSIHB_IRQ_STAT_LOCERR 0x0000000200000000ull
+#define PSIHB_IRQ_STAT_EXT 0x0000000100000000ull
+
+/* remaining XIVR */
+#define PSIHB_XSCOM_XIVR_OCC 0x16
+#define PSIHB_XSCOM_XIVR_FSI 0x17
+#define PSIHB_XSCOM_XIVR_LPCI2C 0x18
+#define PSIHB_XSCOM_XIVR_LOCERR 0x19
+#define PSIHB_XSCOM_XIVR_EXT 0x1a
+
+/* Interrupt Requester Source Compare Register */
+#define PSIHB_XSCOM_IRSN 0x1b
+#define PSIHB_IRSN_COMP_SH 45
+#define PSIHB_IRSN_COMP_MSK (0x7ffffull << PSIHB_IRSN_COMP_SH)
+#define PSIHB_IRSN_IRQ_MUX 0x0000000800000000ull
+#define PSIHB_IRSN_IRQ_RESET 0x0000000400000000ull
+#define PSIHB_IRSN_DOWNSTREAM_EN 0x0000000200000000ull
+#define PSIHB_IRSN_UPSTREAM_EN 0x0000000100000000ull
+#define PSIHB_IRSN_COMPMASK_SH 13
+#define PSIHB_IRSN_COMPMASK_MSK (0x7ffffull << PSIHB_IRSN_COMPMASK_SH)
+
+#define PSIHB_BAR_MASK 0x0003fffffff00000ull
+#define PSIHB_FSPBAR_MASK 0x0003ffff00000000ull
+
+static void pnv_psi_set_bar(PnvPsi *psi, uint64_t bar)
+{
+ MemoryRegion *sysmem = get_system_memory();
+ uint64_t old = psi->regs[PSIHB_XSCOM_BAR];
+
+ psi->regs[PSIHB_XSCOM_BAR] = bar & (PSIHB_BAR_MASK | PSIHB_BAR_EN);
+
+ /* Update MR, always remove it first */
+ if (old & PSIHB_BAR_EN) {
+ memory_region_del_subregion(sysmem, &psi->regs_mr);
+ }
+
+ /* Then add it back if needed */
+ if (bar & PSIHB_BAR_EN) {
+ uint64_t addr = bar & PSIHB_BAR_MASK;
+ memory_region_add_subregion(sysmem, addr, &psi->regs_mr);
+ }
+}
+
+static void pnv_psi_update_fsp_mr(PnvPsi *psi)
+{
+ /* TODO: Update FSP MR if/when we support FSP BAR */
+}
+
+static void pnv_psi_set_cr(PnvPsi *psi, uint64_t cr)
+{
+ uint64_t old = psi->regs[PSIHB_XSCOM_CR];
+
+ psi->regs[PSIHB_XSCOM_CR] = cr;
+
+ /* Check some bit changes */
+ if ((old ^ psi->regs[PSIHB_XSCOM_CR]) & PSIHB_CR_FSP_MMIO_ENABLE) {
+ pnv_psi_update_fsp_mr(psi);
+ }
+}
+
+static void pnv_psi_set_irsn(PnvPsi *psi, uint64_t val)
+{
+ ICSState *ics = &psi->ics;
+
+ /* In this model we ignore the up/down enable bits for now
+ * as SW doesn't use them (other than setting them at boot).
+ * We ignore IRQ_MUX, its meaning isn't clear and we don't use
+ * it and finally we ignore reset (XXX fix that ?)
+ */
+ psi->regs[PSIHB_XSCOM_IRSN] = val & (PSIHB_IRSN_COMP_MSK |
+ PSIHB_IRSN_IRQ_MUX |
+ PSIHB_IRSN_IRQ_RESET |
+ PSIHB_IRSN_DOWNSTREAM_EN |
+ PSIHB_IRSN_UPSTREAM_EN);
+
+ /* We ignore the compare mask as well, our ICS emulation is too
+ * simplistic to make any use if it, and we extract the offset
+ * from the compare value
+ */
+ ics->offset = (val & PSIHB_IRSN_COMP_MSK) >> PSIHB_IRSN_COMP_SH;
+}
+
+/*
+ * FSP and PSI interrupts are muxed under the same number.
+ */
+static const uint32_t xivr_regs[] = {
+ [PSIHB_IRQ_PSI] = PSIHB_XSCOM_XIVR_FSP,
+ [PSIHB_IRQ_FSP] = PSIHB_XSCOM_XIVR_FSP,
+ [PSIHB_IRQ_OCC] = PSIHB_XSCOM_XIVR_OCC,
+ [PSIHB_IRQ_FSI] = PSIHB_XSCOM_XIVR_FSI,
+ [PSIHB_IRQ_LPC_I2C] = PSIHB_XSCOM_XIVR_LPCI2C,
+ [PSIHB_IRQ_LOCAL_ERR] = PSIHB_XSCOM_XIVR_LOCERR,
+ [PSIHB_IRQ_EXTERNAL] = PSIHB_XSCOM_XIVR_EXT,
+};
+
+static const uint32_t stat_regs[] = {
+ [PSIHB_IRQ_PSI] = PSIHB_XSCOM_CR,
+ [PSIHB_IRQ_FSP] = PSIHB_XSCOM_CR,
+ [PSIHB_IRQ_OCC] = PSIHB_XSCOM_IRQ_STAT,
+ [PSIHB_IRQ_FSI] = PSIHB_XSCOM_IRQ_STAT,
+ [PSIHB_IRQ_LPC_I2C] = PSIHB_XSCOM_IRQ_STAT,
+ [PSIHB_IRQ_LOCAL_ERR] = PSIHB_XSCOM_IRQ_STAT,
+ [PSIHB_IRQ_EXTERNAL] = PSIHB_XSCOM_IRQ_STAT,
+};
+
+static const uint64_t stat_bits[] = {
+ [PSIHB_IRQ_PSI] = PSIHB_CR_PSI_IRQ,
+ [PSIHB_IRQ_FSP] = PSIHB_CR_FSP_IRQ,
+ [PSIHB_IRQ_OCC] = PSIHB_IRQ_STAT_OCC,
+ [PSIHB_IRQ_FSI] = PSIHB_IRQ_STAT_FSI,
+ [PSIHB_IRQ_LPC_I2C] = PSIHB_IRQ_STAT_LPCI2C,
+ [PSIHB_IRQ_LOCAL_ERR] = PSIHB_IRQ_STAT_LOCERR,
+ [PSIHB_IRQ_EXTERNAL] = PSIHB_IRQ_STAT_EXT,
+};
+
+void pnv_psi_irq_set(PnvPsi *psi, PnvPsiIrq irq, bool state)
+{
+ ICSState *ics = &psi->ics;
+ uint32_t xivr_reg;
+ uint32_t stat_reg;
+ uint32_t src;
+ bool masked;
+
+ if (irq > PSIHB_IRQ_EXTERNAL) {
+ qemu_log_mask(LOG_GUEST_ERROR, "PSI: Unsupported irq %d\n", irq);
+ return;
+ }
+
+ xivr_reg = xivr_regs[irq];
+ stat_reg = stat_regs[irq];
+
+ src = (psi->regs[xivr_reg] & PSIHB_XIVR_SRC_MSK) >> PSIHB_XIVR_SRC_SH;
+ if (state) {
+ psi->regs[stat_reg] |= stat_bits[irq];
+ /* TODO: optimization, check mask here. That means
+ * re-evaluating when unmasking
+ */
+ qemu_irq_raise(ics->qirqs[src]);
+ } else {
+ psi->regs[stat_reg] &= ~stat_bits[irq];
+
+ /* FSP and PSI are muxed so don't lower if either is still set */
+ if (stat_reg != PSIHB_XSCOM_CR ||
+ !(psi->regs[stat_reg] & (PSIHB_CR_PSI_IRQ | PSIHB_CR_FSP_IRQ))) {
+ qemu_irq_lower(ics->qirqs[src]);
+ } else {
+ state = true;
+ }
+ }
+
+ /* Note about the emulation of the pending bit: This isn't
+ * entirely correct. The pending bit should be cleared when the
+ * EOI has been received. However, we don't have callbacks on EOI
+ * (especially not under KVM) so no way to emulate that properly,
+ * so instead we just set that bit as the logical "output" of the
+ * XIVR (ie pending & !masked)
+ *
+ * CLG: We could define a new ICS object with a custom eoi()
+ * handler to clear the pending bit. But I am not sure this would
+ * be useful for the software anyhow.
+ */
+ masked = (psi->regs[xivr_reg] & PSIHB_XIVR_PRIO_MSK) == PSIHB_XIVR_PRIO_MSK;
+ if (state && !masked) {
+ psi->regs[xivr_reg] |= PSIHB_XIVR_PENDING;
+ } else {
+ psi->regs[xivr_reg] &= ~PSIHB_XIVR_PENDING;
+ }
+}
+
+static void pnv_psi_set_xivr(PnvPsi *psi, uint32_t reg, uint64_t val)
+{
+ ICSState *ics = &psi->ics;
+ uint16_t server;
+ uint8_t prio;
+ uint8_t src;
+
+ psi->regs[reg] = (psi->regs[reg] & PSIHB_XIVR_PENDING) |
+ (val & (PSIHB_XIVR_SERVER_MSK |
+ PSIHB_XIVR_PRIO_MSK |
+ PSIHB_XIVR_SRC_MSK));
+ val = psi->regs[reg];
+ server = (val & PSIHB_XIVR_SERVER_MSK) >> PSIHB_XIVR_SERVER_SH;
+ prio = (val & PSIHB_XIVR_PRIO_MSK) >> PSIHB_XIVR_PRIO_SH;
+ src = (val & PSIHB_XIVR_SRC_MSK) >> PSIHB_XIVR_SRC_SH;
+
+ if (src >= PSI_NUM_INTERRUPTS) {
+ qemu_log_mask(LOG_GUEST_ERROR, "PSI: Unsupported irq %d\n", src);
+ return;
+ }
+
+ /* Remove pending bit if the IRQ is masked */
+ if ((psi->regs[reg] & PSIHB_XIVR_PRIO_MSK) == PSIHB_XIVR_PRIO_MSK) {
+ psi->regs[reg] &= ~PSIHB_XIVR_PENDING;
+ }
+
+ /* The low order 2 bits are the link pointer (Type II interrupts).
+ * Shift back to get a valid IRQ server.
+ */
+ server >>= 2;
+
+ /* Now because of source remapping, weird things can happen
+ * if you change the source number dynamically, our simple ICS
+ * doesn't deal with remapping. So we just poke a different
+ * ICS entry based on what source number was written. This will
+ * do for now but a more accurate implementation would instead
+ * use a fixed server/prio and a remapper of the generated irq.
+ */
+ ics_simple_write_xive(ics, src, server, prio, prio);
+}
+
+static uint64_t pnv_psi_reg_read(PnvPsi *psi, uint32_t offset, bool mmio)
+{
+ uint64_t val = 0xffffffffffffffffull;
+
+ switch (offset) {
+ case PSIHB_XSCOM_FIR_RW:
+ case PSIHB_XSCOM_FIRACT0:
+ case PSIHB_XSCOM_FIRACT1:
+ case PSIHB_XSCOM_BAR:
+ case PSIHB_XSCOM_FSPBAR:
+ case PSIHB_XSCOM_CR:
+ case PSIHB_XSCOM_XIVR_FSP:
+ case PSIHB_XSCOM_XIVR_OCC:
+ case PSIHB_XSCOM_XIVR_FSI:
+ case PSIHB_XSCOM_XIVR_LPCI2C:
+ case PSIHB_XSCOM_XIVR_LOCERR:
+ case PSIHB_XSCOM_XIVR_EXT:
+ case PSIHB_XSCOM_IRQ_STAT:
+ case PSIHB_XSCOM_SEMR:
+ case PSIHB_XSCOM_DMA_UPADD:
+ case PSIHB_XSCOM_IRSN:
+ val = psi->regs[offset];
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "PSI: read at Ox%" PRIx32 "\n", offset);
+ }
+ return val;
+}
+
+static void pnv_psi_reg_write(PnvPsi *psi, uint32_t offset, uint64_t val,
+ bool mmio)
+{
+ switch (offset) {
+ case PSIHB_XSCOM_FIR_RW:
+ case PSIHB_XSCOM_FIRACT0:
+ case PSIHB_XSCOM_FIRACT1:
+ case PSIHB_XSCOM_SEMR:
+ case PSIHB_XSCOM_DMA_UPADD:
+ psi->regs[offset] = val;
+ break;
+ case PSIHB_XSCOM_FIR_OR:
+ psi->regs[PSIHB_XSCOM_FIR_RW] |= val;
+ break;
+ case PSIHB_XSCOM_FIR_AND:
+ psi->regs[PSIHB_XSCOM_FIR_RW] &= val;
+ break;
+ case PSIHB_XSCOM_BAR:
+ /* Only XSCOM can write this one */
+ if (!mmio) {
+ pnv_psi_set_bar(psi, val);
+ } else {
+ qemu_log_mask(LOG_GUEST_ERROR, "PSI: invalid write of BAR\n");
+ }
+ break;
+ case PSIHB_XSCOM_FSPBAR:
+ psi->regs[PSIHB_XSCOM_FSPBAR] = val & PSIHB_FSPBAR_MASK;
+ pnv_psi_update_fsp_mr(psi);
+ break;
+ case PSIHB_XSCOM_CR:
+ pnv_psi_set_cr(psi, val);
+ break;
+ case PSIHB_XSCOM_SCR:
+ pnv_psi_set_cr(psi, psi->regs[PSIHB_XSCOM_CR] | val);
+ break;
+ case PSIHB_XSCOM_CCR:
+ pnv_psi_set_cr(psi, psi->regs[PSIHB_XSCOM_CR] & ~val);
+ break;
+ case PSIHB_XSCOM_XIVR_FSP:
+ case PSIHB_XSCOM_XIVR_OCC:
+ case PSIHB_XSCOM_XIVR_FSI:
+ case PSIHB_XSCOM_XIVR_LPCI2C:
+ case PSIHB_XSCOM_XIVR_LOCERR:
+ case PSIHB_XSCOM_XIVR_EXT:
+ pnv_psi_set_xivr(psi, offset, val);
+ break;
+ case PSIHB_XSCOM_IRQ_STAT:
+ /* Read only */
+ qemu_log_mask(LOG_GUEST_ERROR, "PSI: invalid write of IRQ_STAT\n");
+ break;
+ case PSIHB_XSCOM_IRSN:
+ pnv_psi_set_irsn(psi, val);
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "PSI: write at Ox%" PRIx32 "\n", offset);
+ }
+}
+
+/*
+ * The values of the registers when accessed through the MMIO region
+ * follow the relation : xscom = (mmio + 0x50) >> 3
+ */
+static uint64_t pnv_psi_mmio_read(void *opaque, hwaddr addr, unsigned size)
+{
+ return pnv_psi_reg_read(opaque, (addr >> 3) + PSIHB_XSCOM_BAR, true);
+}
+
+static void pnv_psi_mmio_write(void *opaque, hwaddr addr,
+ uint64_t val, unsigned size)
+{
+ pnv_psi_reg_write(opaque, (addr >> 3) + PSIHB_XSCOM_BAR, val, true);
+}
+
+static const MemoryRegionOps psi_mmio_ops = {
+ .read = pnv_psi_mmio_read,
+ .write = pnv_psi_mmio_write,
+ .endianness = DEVICE_BIG_ENDIAN,
+ .valid = {
+ .min_access_size = 8,
+ .max_access_size = 8,
+ },
+ .impl = {
+ .min_access_size = 8,
+ .max_access_size = 8,
+ },
+};
+
+static uint64_t pnv_psi_xscom_read(void *opaque, hwaddr addr, unsigned size)
+{
+ return pnv_psi_reg_read(opaque, addr >> 3, false);
+}
+
+static void pnv_psi_xscom_write(void *opaque, hwaddr addr,
+ uint64_t val, unsigned size)
+{
+ pnv_psi_reg_write(opaque, addr >> 3, val, false);
+}
+
+static const MemoryRegionOps pnv_psi_xscom_ops = {
+ .read = pnv_psi_xscom_read,
+ .write = pnv_psi_xscom_write,
+ .endianness = DEVICE_BIG_ENDIAN,
+ .valid = {
+ .min_access_size = 8,
+ .max_access_size = 8,
+ },
+ .impl = {
+ .min_access_size = 8,
+ .max_access_size = 8,
+ }
+};
+
+static void pnv_psi_init(Object *obj)
+{
+ PnvPsi *psi = PNV_PSI(obj);
+
+ object_initialize(&psi->ics, sizeof(psi->ics), TYPE_ICS_SIMPLE);
+ object_property_add_child(obj, "ics-psi", OBJECT(&psi->ics), NULL);
+}
+
+static const uint8_t irq_to_xivr[] = {
+ PSIHB_XSCOM_XIVR_FSP,
+ PSIHB_XSCOM_XIVR_OCC,
+ PSIHB_XSCOM_XIVR_FSI,
+ PSIHB_XSCOM_XIVR_LPCI2C,
+ PSIHB_XSCOM_XIVR_LOCERR,
+ PSIHB_XSCOM_XIVR_EXT,
+};
+
+static void pnv_psi_realize(DeviceState *dev, Error **errp)
+{
+ PnvPsi *psi = PNV_PSI(dev);
+ ICSState *ics = &psi->ics;
+ Object *obj;
+ Error *err = NULL;
+ unsigned int i;
+
+ obj = object_property_get_link(OBJECT(dev), "xics", &err);
+ if (!obj) {
+ error_setg(errp, "%s: required link 'xics' not found: %s",
+ __func__, error_get_pretty(err));
+ return;
+ }
+
+ /* Create PSI interrupt control source */
+ object_property_add_const_link(OBJECT(ics), "xics", obj, &error_abort);
+ object_property_set_int(OBJECT(ics), PSI_NUM_INTERRUPTS, "nr-irqs", &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ object_property_set_bool(OBJECT(ics), true, "realized", &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+
+ for (i = 0; i < ics->nr_irqs; i++) {
+ ics_set_irq_type(ics, i, true);
+ }
+
+ /* XSCOM region for PSI registers */
+ pnv_xscom_region_init(&psi->xscom_regs, OBJECT(dev), &pnv_psi_xscom_ops,
+ psi, "xscom-psi", PNV_XSCOM_PSIHB_SIZE);
+
+ /* Initialize MMIO region */
+ memory_region_init_io(&psi->regs_mr, OBJECT(dev), &psi_mmio_ops, psi,
+ "psihb", PNV_PSIHB_SIZE);
+
+ /* Default BAR for MMIO region */
+ pnv_psi_set_bar(psi, psi->bar | PSIHB_BAR_EN);
+
+ /* Default sources in XIVR */
+ for (i = 0; i < PSI_NUM_INTERRUPTS; i++) {
+ uint8_t xivr = irq_to_xivr[i];
+ psi->regs[xivr] = PSIHB_XIVR_PRIO_MSK |
+ ((uint64_t) i << PSIHB_XIVR_SRC_SH);
+ }
+}
+
+static int pnv_psi_populate(PnvXScomInterface *dev, void *fdt, int xscom_offset)
+{
+ const char compat[] = "ibm,power8-psihb-x\0ibm,psihb-x";
+ char *name;
+ int offset;
+ uint32_t lpc_pcba = PNV_XSCOM_PSIHB_BASE;
+ uint32_t reg[] = {
+ cpu_to_be32(lpc_pcba),
+ cpu_to_be32(PNV_XSCOM_PSIHB_SIZE)
+ };
+
+ name = g_strdup_printf("psihb@%x", lpc_pcba);
+ offset = fdt_add_subnode(fdt, xscom_offset, name);
+ _FDT(offset);
+ g_free(name);
+
+ _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg))));
+
+ _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 2)));
+ _FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 1)));
+ _FDT((fdt_setprop(fdt, offset, "compatible", compat,
+ sizeof(compat))));
+ return 0;
+}
+
+static Property pnv_psi_properties[] = {
+ DEFINE_PROP_UINT64("bar", PnvPsi, bar, 0),
+ DEFINE_PROP_UINT64("fsp-bar", PnvPsi, fsp_bar, 0),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void pnv_psi_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass);
+
+ xdc->populate = pnv_psi_populate;
+
+ dc->realize = pnv_psi_realize;
+ dc->props = pnv_psi_properties;
+}
+
+static const TypeInfo pnv_psi_info = {
+ .name = TYPE_PNV_PSI,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(PnvPsi),
+ .instance_init = pnv_psi_init,
+ .class_init = pnv_psi_class_init,
+ .interfaces = (InterfaceInfo[]) {
+ { TYPE_PNV_XSCOM_INTERFACE },
+ { }
+ }
+};
+
+static void pnv_psi_register_types(void)
+{
+ type_register_static(&pnv_psi_info);
+}
+
+type_init(pnv_psi_register_types)
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 96231c1ff708..a3ed2ee647b9 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -22,6 +22,7 @@
#include "hw/boards.h"
#include "hw/sysbus.h"
#include "hw/ppc/pnv_lpc.h"
+#include "hw/ppc/pnv_psi.h"
#define TYPE_PNV_CHIP "powernv-chip"
#define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP)
@@ -57,6 +58,7 @@ typedef struct PnvChip {
MemoryRegion icp_mmio;
PnvLpcController lpc;
+ PnvPsi psi;
} PnvChip;
typedef struct PnvChipClass {
@@ -125,6 +127,7 @@ typedef struct PnvMachineState {
PnvChip **chips;
ISABus *isa_bus;
+ uint32_t cpld_irqstate;
} PnvMachineState;
#define PNV_FDT_ADDR 0x01000000
@@ -155,4 +158,14 @@ typedef struct PnvMachineState {
#define PNV_ICP_BASE(chip) \
(0x0003ffff80000000ull + (uint64_t) PNV_CHIP_INDEX(chip) * PNV_ICP_SIZE)
+
+#define PNV_PSIHB_SIZE 0x0000000000100000ull
+#define PNV_PSIHB_BASE(chip) \
+ (0x0003fffe80000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * PNV_PSIHB_SIZE)
+
+#define PNV_PSIHB_FSP_SIZE 0x0000000100000000ull
+#define PNV_PSIHB_FSP_BASE(chip) \
+ (0x0003ffe000000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * \
+ PNV_PSIHB_FSP_SIZE)
+
#endif /* _PPC_PNV_H */
diff --git a/include/hw/ppc/pnv_psi.h b/include/hw/ppc/pnv_psi.h
new file mode 100644
index 000000000000..11d83e43f8ad
--- /dev/null
+++ b/include/hw/ppc/pnv_psi.h
@@ -0,0 +1,67 @@
+/*
+ * QEMU PowerPC PowerNV Processor Service Interface (PSI) model
+ *
+ * Copyright (c) 2015-2017, IBM Corporation.
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef _PPC_PNV_PSI_H
+#define _PPC_PNV_PSI_H
+
+#include "hw/sysbus.h"
+#include "hw/ppc/xics.h"
+
+#define TYPE_PNV_PSI "pnv-psi"
+#define PNV_PSI(obj) \
+ OBJECT_CHECK(PnvPsi, (obj), TYPE_PNV_PSI)
+
+#define PSIHB_XSCOM_MAX 0x20
+
+typedef struct XICSState XICSState;
+
+typedef struct PnvPsi {
+ SysBusDevice parent;
+
+ MemoryRegion regs_mr;
+ uint64_t bar;
+
+ /* FSP region not supported */
+ /* MemoryRegion fsp_mr; */
+ uint64_t fsp_bar;
+
+ /* Interrupt generation */
+ ICSState ics;
+
+ /* Registers */
+ uint64_t regs[PSIHB_XSCOM_MAX];
+
+ MemoryRegion xscom_regs;
+} PnvPsi;
+
+/* The PSI and FSP interrupts are muxed on the same IRQ number */
+typedef enum PnvPsiIrq {
+ PSIHB_IRQ_PSI, /* internal use only */
+ PSIHB_IRQ_FSP, /* internal use only */
+ PSIHB_IRQ_OCC,
+ PSIHB_IRQ_FSI,
+ PSIHB_IRQ_LPC_I2C,
+ PSIHB_IRQ_LOCAL_ERR,
+ PSIHB_IRQ_EXTERNAL,
+} PnvPsiIrq;
+
+#define PSI_NUM_INTERRUPTS 6
+
+extern void pnv_psi_irq_set(PnvPsi *psi, PnvPsiIrq irq, bool state);
+
+#endif /* _PPC_PNV_PSI_H */
diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h
index 0faa1847bf13..15f7fdb147ee 100644
--- a/include/hw/ppc/pnv_xscom.h
+++ b/include/hw/ppc/pnv_xscom.h
@@ -60,6 +60,9 @@ typedef struct PnvXScomInterfaceClass {
#define PNV_XSCOM_LPC_BASE 0xb0020
#define PNV_XSCOM_LPC_SIZE 0x4
+#define PNV_XSCOM_PSIHB_BASE 0x2010900
+#define PNV_XSCOM_PSIHB_SIZE 0x20
+
extern void pnv_xscom_realize(PnvChip *chip, Error **errp);
extern int pnv_xscom_populate(PnvChip *chip, void *fdt, int offset);
--
2.7.4
^ permalink raw reply related [flat|nested] 66+ messages in thread* [Qemu-devel] [PATCH 02/21] ppc/pnv: Add OCC model stub with interrupt support
2017-04-05 12:41 [Qemu-devel] [PATCH 00/21] pnv: PSI, OCC, IPMI and PCI models Cédric Le Goater
2017-04-05 12:41 ` [Qemu-devel] [PATCH 01/21] ppc/pnv: Add cut down PSI bridge model and hookup external interrupt Cédric Le Goater
@ 2017-04-05 12:41 ` Cédric Le Goater
2017-04-05 12:41 ` [Qemu-devel] [PATCH 03/21] ppc/pnv: Add support for POWER8+ LPC Controller Cédric Le Goater
` (18 subsequent siblings)
20 siblings, 0 replies; 66+ messages in thread
From: Cédric Le Goater @ 2017-04-05 12:41 UTC (permalink / raw)
To: David Gibson
Cc: qemu-ppc, qemu-devel, Benjamin Herrenschmidt, Cédric Le Goater
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
The OCC is an on-chip microcontroller based on a ppc405 core used
for various power management tasks. It comes with a pile of additional
hardware sitting on the PIB (aka XSCOM bus). At this point we don't
emulate it (nor plan to do so). However there is one facility which
is provided by the surrounding hardware that we do need, which is the
interrupt generation facility. OPAL uses it to send itself interrupts
under some circumstances and there are other uses around the corner.
So this implement just enough to support this.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
[clg: - updated for qemu-2.9
- changed the XSCOM interface to fit new model
- QOMified the model ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/Makefile.objs | 2 +-
hw/ppc/pnv.c | 13 +++++
hw/ppc/pnv_occ.c | 136 +++++++++++++++++++++++++++++++++++++++++++++
include/hw/ppc/pnv.h | 2 +
include/hw/ppc/pnv_occ.h | 38 +++++++++++++
include/hw/ppc/pnv_xscom.h | 3 +
6 files changed, 193 insertions(+), 1 deletion(-)
create mode 100644 hw/ppc/pnv_occ.c
create mode 100644 include/hw/ppc/pnv_occ.h
diff --git a/hw/ppc/Makefile.objs b/hw/ppc/Makefile.objs
index dc19ee17fa57..ef67ea820158 100644
--- a/hw/ppc/Makefile.objs
+++ b/hw/ppc/Makefile.objs
@@ -6,7 +6,7 @@ obj-$(CONFIG_PSERIES) += spapr_hcall.o spapr_iommu.o spapr_rtas.o
obj-$(CONFIG_PSERIES) += spapr_pci.o spapr_rtc.o spapr_drc.o spapr_rng.o
obj-$(CONFIG_PSERIES) += spapr_cpu_core.o spapr_ovec.o
# IBM PowerNV
-obj-$(CONFIG_POWERNV) += pnv.o pnv_xscom.o pnv_core.o pnv_lpc.o pnv_psi.o
+obj-$(CONFIG_POWERNV) += pnv.o pnv_xscom.o pnv_core.o pnv_lpc.o pnv_psi.o pnv_occ.o
ifeq ($(CONFIG_PCI)$(CONFIG_PSERIES)$(CONFIG_LINUX), yyy)
obj-y += spapr_pci_vfio.o
endif
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 5c90ac6ad950..24e523f554c6 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -694,6 +694,11 @@ static void pnv_chip_init(Object *obj)
object_property_add_child(obj, "psi", OBJECT(&chip->psi), NULL);
object_property_add_const_link(OBJECT(&chip->psi), "xics",
OBJECT(qdev_get_machine()), &error_abort);
+
+ object_initialize(&chip->occ, sizeof(chip->occ), TYPE_PNV_OCC);
+ object_property_add_child(obj, "occ", OBJECT(&chip->occ), NULL);
+ object_property_add_const_link(OBJECT(&chip->occ), "psi",
+ OBJECT(&chip->psi), &error_abort);
}
static void pnv_chip_icp_realize(PnvChip *chip, Error **errp)
@@ -816,6 +821,14 @@ static void pnv_chip_realize(DeviceState *dev, Error **errp)
return;
}
pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, &chip->psi.xscom_regs);
+
+ /* Create the simplified OCC model */
+ object_property_set_bool(OBJECT(&chip->occ), true, "realized", &error);
+ if (error) {
+ error_propagate(errp, error);
+ return;
+ }
+ pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip->occ.xscom_regs);
}
static Property pnv_chip_properties[] = {
diff --git a/hw/ppc/pnv_occ.c b/hw/ppc/pnv_occ.c
new file mode 100644
index 000000000000..04880f26d612
--- /dev/null
+++ b/hw/ppc/pnv_occ.c
@@ -0,0 +1,136 @@
+/*
+ * QEMU PowerPC PowerNV Emulation of a few OCC related registers
+ *
+ * Copyright (c) 2015-2017, IBM Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/hw.h"
+#include "sysemu/sysemu.h"
+#include "target/ppc/cpu.h"
+#include "qapi/error.h"
+#include "qemu/log.h"
+
+#include "hw/ppc/pnv.h"
+#include "hw/ppc/pnv_xscom.h"
+#include "hw/ppc/pnv_occ.h"
+
+#define OCB_OCI_OCCMISC 0x4020
+#define OCB_OCI_OCCMISC_AND 0x4021
+#define OCB_OCI_OCCMISC_OR 0x4022
+
+static void pnv_occ_set_misc(PnvOCC *occ, uint64_t val)
+{
+ bool irq_state;
+
+ val &= 0xffff000000000000ull;
+
+ occ->occmisc = val;
+ irq_state = !!(val >> 63);
+ pnv_psi_irq_set(occ->psi, PSIHB_IRQ_OCC, irq_state);
+}
+
+static uint64_t pnv_occ_xscom_read(void *opaque, hwaddr addr, unsigned size)
+{
+ PnvOCC *occ = PNV_OCC(opaque);
+ uint32_t offset = addr >> 3;
+ uint64_t val = 0;
+
+ switch (offset) {
+ case OCB_OCI_OCCMISC:
+ val = occ->occmisc;
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%"
+ HWADDR_PRIx "\n", addr);
+ }
+ return val;
+}
+
+static void pnv_occ_xscom_write(void *opaque, hwaddr addr,
+ uint64_t val, unsigned size)
+{
+ PnvOCC *occ = PNV_OCC(opaque);
+ uint32_t offset = addr >> 3;
+
+ switch (offset) {
+ case OCB_OCI_OCCMISC_AND:
+ pnv_occ_set_misc(occ, occ->occmisc & val);
+ break;
+ case OCB_OCI_OCCMISC_OR:
+ pnv_occ_set_misc(occ, occ->occmisc | val);
+ break;
+ case OCB_OCI_OCCMISC:
+ pnv_occ_set_misc(occ, val);
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%"
+ HWADDR_PRIx "\n", addr);
+ }
+}
+
+static const MemoryRegionOps pnv_occ_xscom_ops = {
+ .read = pnv_occ_xscom_read,
+ .write = pnv_occ_xscom_write,
+ .valid.min_access_size = 8,
+ .valid.max_access_size = 8,
+ .impl.min_access_size = 8,
+ .impl.max_access_size = 8,
+ .endianness = DEVICE_BIG_ENDIAN,
+};
+
+
+static void pnv_occ_realize(DeviceState *dev, Error **errp)
+{
+ PnvOCC *occ = PNV_OCC(dev);
+ Object *obj;
+ Error *error = NULL;
+
+ occ->occmisc = 0;
+
+ /* get PSI object from chip */
+ obj = object_property_get_link(OBJECT(dev), "psi", &error);
+ if (!obj) {
+ error_setg(errp, "%s: required link 'psi' not found: %s",
+ __func__, error_get_pretty(error));
+ return;
+ }
+ occ->psi = PNV_PSI(obj);
+
+ /* XScom region for OCC registers */
+ pnv_xscom_region_init(&occ->xscom_regs, OBJECT(dev), &pnv_occ_xscom_ops,
+ occ, "xscom-occ", PNV_XSCOM_OCC_SIZE);
+}
+
+static void pnv_occ_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = pnv_occ_realize;
+}
+
+static const TypeInfo pnv_occ_type_info = {
+ .name = TYPE_PNV_OCC,
+ .parent = TYPE_DEVICE,
+ .instance_size = sizeof(PnvOCC),
+ .class_init = pnv_occ_class_init,
+};
+
+static void pnv_occ_register_types(void)
+{
+ type_register_static(&pnv_occ_type_info);
+}
+
+type_init(pnv_occ_register_types)
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index a3ed2ee647b9..b45a0d91c813 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -23,6 +23,7 @@
#include "hw/sysbus.h"
#include "hw/ppc/pnv_lpc.h"
#include "hw/ppc/pnv_psi.h"
+#include "hw/ppc/pnv_occ.h"
#define TYPE_PNV_CHIP "powernv-chip"
#define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP)
@@ -59,6 +60,7 @@ typedef struct PnvChip {
PnvLpcController lpc;
PnvPsi psi;
+ PnvOCC occ;
} PnvChip;
typedef struct PnvChipClass {
diff --git a/include/hw/ppc/pnv_occ.h b/include/hw/ppc/pnv_occ.h
new file mode 100644
index 000000000000..f8ec330abfd7
--- /dev/null
+++ b/include/hw/ppc/pnv_occ.h
@@ -0,0 +1,38 @@
+/*
+ * QEMU PowerPC PowerNV Emulation of a few OCC related registers
+ *
+ * Copyright (c) 2015-2017, IBM Corporation.
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef _PPC_PNV_OCC_H
+#define _PPC_PNV_OCC_H
+
+#define TYPE_PNV_OCC "pnv-occ"
+#define PNV_OCC(obj) OBJECT_CHECK(PnvOCC, (obj), TYPE_PNV_OCC)
+
+typedef struct PnvPsi PnvPsi;
+
+typedef struct PnvOCC {
+ DeviceState xd;
+
+ /* OCC Misc interrupt */
+ uint64_t occmisc;
+
+ PnvPsi *psi;
+
+ MemoryRegion xscom_regs;
+} PnvOCC;
+
+#endif /* _PPC_PNV_OCC_H */
diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h
index 15f7fdb147ee..3757b2cab94b 100644
--- a/include/hw/ppc/pnv_xscom.h
+++ b/include/hw/ppc/pnv_xscom.h
@@ -63,6 +63,9 @@ typedef struct PnvXScomInterfaceClass {
#define PNV_XSCOM_PSIHB_BASE 0x2010900
#define PNV_XSCOM_PSIHB_SIZE 0x20
+#define PNV_XSCOM_OCC_BASE 0x0066000
+#define PNV_XSCOM_OCC_SIZE 0x6000
+
extern void pnv_xscom_realize(PnvChip *chip, Error **errp);
extern int pnv_xscom_populate(PnvChip *chip, void *fdt, int offset);
--
2.7.4
^ permalink raw reply related [flat|nested] 66+ messages in thread* [Qemu-devel] [PATCH 03/21] ppc/pnv: Add support for POWER8+ LPC Controller
2017-04-05 12:41 [Qemu-devel] [PATCH 00/21] pnv: PSI, OCC, IPMI and PCI models Cédric Le Goater
2017-04-05 12:41 ` [Qemu-devel] [PATCH 01/21] ppc/pnv: Add cut down PSI bridge model and hookup external interrupt Cédric Le Goater
2017-04-05 12:41 ` [Qemu-devel] [PATCH 02/21] ppc/pnv: Add OCC model stub with interrupt support Cédric Le Goater
@ 2017-04-05 12:41 ` Cédric Le Goater
2017-04-06 2:02 ` David Gibson
2017-04-05 12:41 ` [Qemu-devel] [PATCH 04/21] ppc/pnv: enable only one LPC bus Cédric Le Goater
` (17 subsequent siblings)
20 siblings, 1 reply; 66+ messages in thread
From: Cédric Le Goater @ 2017-04-05 12:41 UTC (permalink / raw)
To: David Gibson
Cc: qemu-ppc, qemu-devel, Benjamin Herrenschmidt, Cédric Le Goater
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
It adds the Naples chip which supports proper LPC interrupts via the
LPC controller rather than via an external CPLD.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
[clg: - updated for qemu-2.9
- ported on latest PowerNV patchset ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/pnv.c | 13 ++++++++++++-
hw/ppc/pnv_lpc.c | 47 +++++++++++++++++++++++++++++++++++++++++++++--
include/hw/ppc/pnv_lpc.h | 9 +++++++++
3 files changed, 66 insertions(+), 3 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 24e523f554c6..78133e5d20e1 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -373,7 +373,14 @@ static void pnv_lpc_isa_irq_handler_cpld(void *opaque, int n, int level)
static void pnv_lpc_isa_irq_handler(void *opaque, int n, int level)
{
- /* XXX TODO */
+ PnvChip *chip = opaque;
+ PnvLpcController *lpc = &chip->lpc;
+
+ /* The Naples HW latches the 1 levels, clearing is done by SW */
+ if (level) {
+ lpc->lpc_hc_irqstat |= LPC_HC_IRQ_SERIRQ0 >> n;
+ pnv_lpc_eval_irqs(lpc);
+ }
}
static ISABus *pnv_isa_create(PnvChip *chip)
@@ -699,6 +706,10 @@ static void pnv_chip_init(Object *obj)
object_property_add_child(obj, "occ", OBJECT(&chip->occ), NULL);
object_property_add_const_link(OBJECT(&chip->occ), "psi",
OBJECT(&chip->psi), &error_abort);
+
+ /* The LPC controller needs PSI to generate interrupts */
+ object_property_add_const_link(OBJECT(&chip->lpc), "psi",
+ OBJECT(&chip->psi), &error_abort);
}
static void pnv_chip_icp_realize(PnvChip *chip, Error **errp)
diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c
index 78db52415b11..20cbb6a0dbbd 100644
--- a/hw/ppc/pnv_lpc.c
+++ b/hw/ppc/pnv_lpc.c
@@ -250,6 +250,34 @@ static const MemoryRegionOps pnv_lpc_xscom_ops = {
.endianness = DEVICE_BIG_ENDIAN,
};
+void pnv_lpc_eval_irqs(PnvLpcController *lpc)
+{
+ bool lpc_to_opb_irq = false;
+
+ /* Update LPC controller to OPB line */
+ if (lpc->lpc_hc_irqser_ctrl & LPC_HC_IRQSER_EN) {
+ uint32_t irqs;
+
+ irqs = lpc->lpc_hc_irqstat & lpc->lpc_hc_irqmask;
+ lpc_to_opb_irq = (irqs != 0);
+ }
+
+ /* We don't honor the polarity register, it's pointless and unused
+ * anyway
+ */
+ if (lpc_to_opb_irq) {
+ lpc->opb_irq_input |= OPB_MASTER_IRQ_LPC;
+ } else {
+ lpc->opb_irq_input &= ~OPB_MASTER_IRQ_LPC;
+ }
+
+ /* Update OPB internal latch */
+ lpc->opb_irq_stat |= lpc->opb_irq_input & lpc->opb_irq_mask;
+
+ /* Reflect the interrupt */
+ pnv_psi_irq_set(lpc->psi, PSIHB_IRQ_LPC_I2C, lpc->opb_irq_stat != 0);
+}
+
static uint64_t lpc_hc_read(void *opaque, hwaddr addr, unsigned size)
{
PnvLpcController *lpc = opaque;
@@ -300,12 +328,15 @@ static void lpc_hc_write(void *opaque, hwaddr addr, uint64_t val,
break;
case LPC_HC_IRQSER_CTRL:
lpc->lpc_hc_irqser_ctrl = val;
+ pnv_lpc_eval_irqs(lpc);
break;
case LPC_HC_IRQMASK:
lpc->lpc_hc_irqmask = val;
+ pnv_lpc_eval_irqs(lpc);
break;
case LPC_HC_IRQSTAT:
lpc->lpc_hc_irqstat &= ~val;
+ pnv_lpc_eval_irqs(lpc);
break;
case LPC_HC_ERROR_ADDRESS:
break;
@@ -363,14 +394,15 @@ static void opb_master_write(void *opaque, hwaddr addr,
switch (addr) {
case OPB_MASTER_LS_IRQ_STAT:
lpc->opb_irq_stat &= ~val;
+ pnv_lpc_eval_irqs(lpc);
break;
case OPB_MASTER_LS_IRQ_MASK:
- /* XXX Filter out reserved bits */
lpc->opb_irq_mask = val;
+ pnv_lpc_eval_irqs(lpc);
break;
case OPB_MASTER_LS_IRQ_POL:
- /* XXX Filter out reserved bits */
lpc->opb_irq_pol = val;
+ pnv_lpc_eval_irqs(lpc);
break;
case OPB_MASTER_LS_IRQ_INPUT:
/* Read only */
@@ -398,6 +430,8 @@ static const MemoryRegionOps opb_master_ops = {
static void pnv_lpc_realize(DeviceState *dev, Error **errp)
{
PnvLpcController *lpc = PNV_LPC(dev);
+ Object *obj;
+ Error *error = NULL;
/* Reg inits */
lpc->lpc_hc_fw_rd_acc_size = LPC_HC_FW_RD_4B;
@@ -441,6 +475,15 @@ static void pnv_lpc_realize(DeviceState *dev, Error **errp)
pnv_xscom_region_init(&lpc->xscom_regs, OBJECT(dev),
&pnv_lpc_xscom_ops, lpc, "xscom-lpc",
PNV_XSCOM_LPC_SIZE);
+
+ /* get PSI object from chip */
+ obj = object_property_get_link(OBJECT(dev), "psi", &error);
+ if (!obj) {
+ error_setg(errp, "%s: required link 'psi' not found: %s",
+ __func__, error_get_pretty(error));
+ return;
+ }
+ lpc->psi = PNV_PSI(obj);
}
static void pnv_lpc_class_init(ObjectClass *klass, void *data)
diff --git a/include/hw/ppc/pnv_lpc.h b/include/hw/ppc/pnv_lpc.h
index 38e5506975aa..53040026c37b 100644
--- a/include/hw/ppc/pnv_lpc.h
+++ b/include/hw/ppc/pnv_lpc.h
@@ -23,6 +23,8 @@
#define PNV_LPC(obj) \
OBJECT_CHECK(PnvLpcController, (obj), TYPE_PNV_LPC)
+typedef struct PnvPsi PnvPsi;
+
typedef struct PnvLpcController {
DeviceState parent;
@@ -62,6 +64,13 @@ typedef struct PnvLpcController {
/* XSCOM registers */
MemoryRegion xscom_regs;
+
+ /* PSI to generate interrupts */
+ PnvPsi *psi;
} PnvLpcController;
+#define LPC_HC_IRQ_SERIRQ0 0x80000000 /* all bits down to ... */
+
+void pnv_lpc_eval_irqs(PnvLpcController *lpc);
+
#endif /* _PPC_PNV_LPC_H */
--
2.7.4
^ permalink raw reply related [flat|nested] 66+ messages in thread* Re: [Qemu-devel] [PATCH 03/21] ppc/pnv: Add support for POWER8+ LPC Controller
2017-04-05 12:41 ` [Qemu-devel] [PATCH 03/21] ppc/pnv: Add support for POWER8+ LPC Controller Cédric Le Goater
@ 2017-04-06 2:02 ` David Gibson
2017-04-06 12:27 ` Cédric Le Goater
2017-04-06 12:44 ` Cédric Le Goater
0 siblings, 2 replies; 66+ messages in thread
From: David Gibson @ 2017-04-06 2:02 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: qemu-ppc, qemu-devel, Benjamin Herrenschmidt
[-- Attachment #1: Type: text/plain, Size: 6604 bytes --]
On Wed, Apr 05, 2017 at 02:41:28PM +0200, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>
> It adds the Naples chip which supports proper LPC interrupts via the
> LPC controller rather than via an external CPLD.
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> [clg: - updated for qemu-2.9
> - ported on latest PowerNV patchset ]
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
> ---
> hw/ppc/pnv.c | 13 ++++++++++++-
> hw/ppc/pnv_lpc.c | 47 +++++++++++++++++++++++++++++++++++++++++++++--
> include/hw/ppc/pnv_lpc.h | 9 +++++++++
> 3 files changed, 66 insertions(+), 3 deletions(-)
>
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index 24e523f554c6..78133e5d20e1 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -373,7 +373,14 @@ static void pnv_lpc_isa_irq_handler_cpld(void *opaque, int n, int level)
>
> static void pnv_lpc_isa_irq_handler(void *opaque, int n, int level)
> {
> - /* XXX TODO */
> + PnvChip *chip = opaque;
> + PnvLpcController *lpc = &chip->lpc;
> +
> + /* The Naples HW latches the 1 levels, clearing is done by SW */
> + if (level) {
> + lpc->lpc_hc_irqstat |= LPC_HC_IRQ_SERIRQ0 >> n;
> + pnv_lpc_eval_irqs(lpc);
> + }
> }
Now that you have a more complete LPC model, I think this function,
and the allocation of the LPC irqs should move into pnv_lpc.c.
Apart from that, looks fine.
>
> static ISABus *pnv_isa_create(PnvChip *chip)
> @@ -699,6 +706,10 @@ static void pnv_chip_init(Object *obj)
> object_property_add_child(obj, "occ", OBJECT(&chip->occ), NULL);
> object_property_add_const_link(OBJECT(&chip->occ), "psi",
> OBJECT(&chip->psi), &error_abort);
> +
> + /* The LPC controller needs PSI to generate interrupts */
> + object_property_add_const_link(OBJECT(&chip->lpc), "psi",
> + OBJECT(&chip->psi), &error_abort);
> }
>
> static void pnv_chip_icp_realize(PnvChip *chip, Error **errp)
> diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c
> index 78db52415b11..20cbb6a0dbbd 100644
> --- a/hw/ppc/pnv_lpc.c
> +++ b/hw/ppc/pnv_lpc.c
> @@ -250,6 +250,34 @@ static const MemoryRegionOps pnv_lpc_xscom_ops = {
> .endianness = DEVICE_BIG_ENDIAN,
> };
>
> +void pnv_lpc_eval_irqs(PnvLpcController *lpc)
> +{
> + bool lpc_to_opb_irq = false;
> +
> + /* Update LPC controller to OPB line */
> + if (lpc->lpc_hc_irqser_ctrl & LPC_HC_IRQSER_EN) {
> + uint32_t irqs;
> +
> + irqs = lpc->lpc_hc_irqstat & lpc->lpc_hc_irqmask;
> + lpc_to_opb_irq = (irqs != 0);
> + }
> +
> + /* We don't honor the polarity register, it's pointless and unused
> + * anyway
> + */
> + if (lpc_to_opb_irq) {
> + lpc->opb_irq_input |= OPB_MASTER_IRQ_LPC;
> + } else {
> + lpc->opb_irq_input &= ~OPB_MASTER_IRQ_LPC;
> + }
> +
> + /* Update OPB internal latch */
> + lpc->opb_irq_stat |= lpc->opb_irq_input & lpc->opb_irq_mask;
> +
> + /* Reflect the interrupt */
> + pnv_psi_irq_set(lpc->psi, PSIHB_IRQ_LPC_I2C, lpc->opb_irq_stat != 0);
> +}
> +
> static uint64_t lpc_hc_read(void *opaque, hwaddr addr, unsigned size)
> {
> PnvLpcController *lpc = opaque;
> @@ -300,12 +328,15 @@ static void lpc_hc_write(void *opaque, hwaddr addr, uint64_t val,
> break;
> case LPC_HC_IRQSER_CTRL:
> lpc->lpc_hc_irqser_ctrl = val;
> + pnv_lpc_eval_irqs(lpc);
> break;
> case LPC_HC_IRQMASK:
> lpc->lpc_hc_irqmask = val;
> + pnv_lpc_eval_irqs(lpc);
> break;
> case LPC_HC_IRQSTAT:
> lpc->lpc_hc_irqstat &= ~val;
> + pnv_lpc_eval_irqs(lpc);
> break;
> case LPC_HC_ERROR_ADDRESS:
> break;
> @@ -363,14 +394,15 @@ static void opb_master_write(void *opaque, hwaddr addr,
> switch (addr) {
> case OPB_MASTER_LS_IRQ_STAT:
> lpc->opb_irq_stat &= ~val;
> + pnv_lpc_eval_irqs(lpc);
> break;
> case OPB_MASTER_LS_IRQ_MASK:
> - /* XXX Filter out reserved bits */
> lpc->opb_irq_mask = val;
> + pnv_lpc_eval_irqs(lpc);
> break;
> case OPB_MASTER_LS_IRQ_POL:
> - /* XXX Filter out reserved bits */
> lpc->opb_irq_pol = val;
> + pnv_lpc_eval_irqs(lpc);
> break;
> case OPB_MASTER_LS_IRQ_INPUT:
> /* Read only */
> @@ -398,6 +430,8 @@ static const MemoryRegionOps opb_master_ops = {
> static void pnv_lpc_realize(DeviceState *dev, Error **errp)
> {
> PnvLpcController *lpc = PNV_LPC(dev);
> + Object *obj;
> + Error *error = NULL;
>
> /* Reg inits */
> lpc->lpc_hc_fw_rd_acc_size = LPC_HC_FW_RD_4B;
> @@ -441,6 +475,15 @@ static void pnv_lpc_realize(DeviceState *dev, Error **errp)
> pnv_xscom_region_init(&lpc->xscom_regs, OBJECT(dev),
> &pnv_lpc_xscom_ops, lpc, "xscom-lpc",
> PNV_XSCOM_LPC_SIZE);
> +
> + /* get PSI object from chip */
> + obj = object_property_get_link(OBJECT(dev), "psi", &error);
> + if (!obj) {
> + error_setg(errp, "%s: required link 'psi' not found: %s",
> + __func__, error_get_pretty(error));
> + return;
> + }
> + lpc->psi = PNV_PSI(obj);
> }
>
> static void pnv_lpc_class_init(ObjectClass *klass, void *data)
> diff --git a/include/hw/ppc/pnv_lpc.h b/include/hw/ppc/pnv_lpc.h
> index 38e5506975aa..53040026c37b 100644
> --- a/include/hw/ppc/pnv_lpc.h
> +++ b/include/hw/ppc/pnv_lpc.h
> @@ -23,6 +23,8 @@
> #define PNV_LPC(obj) \
> OBJECT_CHECK(PnvLpcController, (obj), TYPE_PNV_LPC)
>
> +typedef struct PnvPsi PnvPsi;
> +
> typedef struct PnvLpcController {
> DeviceState parent;
>
> @@ -62,6 +64,13 @@ typedef struct PnvLpcController {
>
> /* XSCOM registers */
> MemoryRegion xscom_regs;
> +
> + /* PSI to generate interrupts */
> + PnvPsi *psi;
> } PnvLpcController;
>
> +#define LPC_HC_IRQ_SERIRQ0 0x80000000 /* all bits down to ... */
> +
> +void pnv_lpc_eval_irqs(PnvLpcController *lpc);
> +
> #endif /* _PPC_PNV_LPC_H */
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 66+ messages in thread* Re: [Qemu-devel] [PATCH 03/21] ppc/pnv: Add support for POWER8+ LPC Controller
2017-04-06 2:02 ` David Gibson
@ 2017-04-06 12:27 ` Cédric Le Goater
2017-04-06 12:44 ` Cédric Le Goater
1 sibling, 0 replies; 66+ messages in thread
From: Cédric Le Goater @ 2017-04-06 12:27 UTC (permalink / raw)
To: David Gibson; +Cc: qemu-ppc, qemu-devel, Benjamin Herrenschmidt
On 04/06/2017 04:02 AM, David Gibson wrote:
> On Wed, Apr 05, 2017 at 02:41:28PM +0200, Cédric Le Goater wrote:
>> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>>
>> It adds the Naples chip which supports proper LPC interrupts via the
>> LPC controller rather than via an external CPLD.
>>
>> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>> [clg: - updated for qemu-2.9
>> - ported on latest PowerNV patchset ]
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>> Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
>> ---
>> hw/ppc/pnv.c | 13 ++++++++++++-
>> hw/ppc/pnv_lpc.c | 47 +++++++++++++++++++++++++++++++++++++++++++++--
>> include/hw/ppc/pnv_lpc.h | 9 +++++++++
>> 3 files changed, 66 insertions(+), 3 deletions(-)
>>
>> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
>> index 24e523f554c6..78133e5d20e1 100644
>> --- a/hw/ppc/pnv.c
>> +++ b/hw/ppc/pnv.c
>> @@ -373,7 +373,14 @@ static void pnv_lpc_isa_irq_handler_cpld(void *opaque, int n, int level)
>>
>> static void pnv_lpc_isa_irq_handler(void *opaque, int n, int level)
>> {
>> - /* XXX TODO */
>> + PnvChip *chip = opaque;
>> + PnvLpcController *lpc = &chip->lpc;
>> +
>> + /* The Naples HW latches the 1 levels, clearing is done by SW */
>> + if (level) {
>> + lpc->lpc_hc_irqstat |= LPC_HC_IRQ_SERIRQ0 >> n;
>> + pnv_lpc_eval_irqs(lpc);
>> + }
>> }
>
> Now that you have a more complete LPC model, I think this function,
> and the allocation of the LPC irqs should move into pnv_lpc.c.
I agree it would look better. I have introduced a pnv_lpc_isa_irq_create()
in next version.
Thanks,
C.
>
> Apart from that, looks fine.
>
>>
>> static ISABus *pnv_isa_create(PnvChip *chip)
>> @@ -699,6 +706,10 @@ static void pnv_chip_init(Object *obj)
>> object_property_add_child(obj, "occ", OBJECT(&chip->occ), NULL);
>> object_property_add_const_link(OBJECT(&chip->occ), "psi",
>> OBJECT(&chip->psi), &error_abort);
>> +
>> + /* The LPC controller needs PSI to generate interrupts */
>> + object_property_add_const_link(OBJECT(&chip->lpc), "psi",
>> + OBJECT(&chip->psi), &error_abort);
>> }
>>
>> static void pnv_chip_icp_realize(PnvChip *chip, Error **errp)
>> diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c
>> index 78db52415b11..20cbb6a0dbbd 100644
>> --- a/hw/ppc/pnv_lpc.c
>> +++ b/hw/ppc/pnv_lpc.c
>> @@ -250,6 +250,34 @@ static const MemoryRegionOps pnv_lpc_xscom_ops = {
>> .endianness = DEVICE_BIG_ENDIAN,
>> };
>>
>> +void pnv_lpc_eval_irqs(PnvLpcController *lpc)
>> +{
>> + bool lpc_to_opb_irq = false;
>> +
>> + /* Update LPC controller to OPB line */
>> + if (lpc->lpc_hc_irqser_ctrl & LPC_HC_IRQSER_EN) {
>> + uint32_t irqs;
>> +
>> + irqs = lpc->lpc_hc_irqstat & lpc->lpc_hc_irqmask;
>> + lpc_to_opb_irq = (irqs != 0);
>> + }
>> +
>> + /* We don't honor the polarity register, it's pointless and unused
>> + * anyway
>> + */
>> + if (lpc_to_opb_irq) {
>> + lpc->opb_irq_input |= OPB_MASTER_IRQ_LPC;
>> + } else {
>> + lpc->opb_irq_input &= ~OPB_MASTER_IRQ_LPC;
>> + }
>> +
>> + /* Update OPB internal latch */
>> + lpc->opb_irq_stat |= lpc->opb_irq_input & lpc->opb_irq_mask;
>> +
>> + /* Reflect the interrupt */
>> + pnv_psi_irq_set(lpc->psi, PSIHB_IRQ_LPC_I2C, lpc->opb_irq_stat != 0);
>> +}
>> +
>> static uint64_t lpc_hc_read(void *opaque, hwaddr addr, unsigned size)
>> {
>> PnvLpcController *lpc = opaque;
>> @@ -300,12 +328,15 @@ static void lpc_hc_write(void *opaque, hwaddr addr, uint64_t val,
>> break;
>> case LPC_HC_IRQSER_CTRL:
>> lpc->lpc_hc_irqser_ctrl = val;
>> + pnv_lpc_eval_irqs(lpc);
>> break;
>> case LPC_HC_IRQMASK:
>> lpc->lpc_hc_irqmask = val;
>> + pnv_lpc_eval_irqs(lpc);
>> break;
>> case LPC_HC_IRQSTAT:
>> lpc->lpc_hc_irqstat &= ~val;
>> + pnv_lpc_eval_irqs(lpc);
>> break;
>> case LPC_HC_ERROR_ADDRESS:
>> break;
>> @@ -363,14 +394,15 @@ static void opb_master_write(void *opaque, hwaddr addr,
>> switch (addr) {
>> case OPB_MASTER_LS_IRQ_STAT:
>> lpc->opb_irq_stat &= ~val;
>> + pnv_lpc_eval_irqs(lpc);
>> break;
>> case OPB_MASTER_LS_IRQ_MASK:
>> - /* XXX Filter out reserved bits */
>> lpc->opb_irq_mask = val;
>> + pnv_lpc_eval_irqs(lpc);
>> break;
>> case OPB_MASTER_LS_IRQ_POL:
>> - /* XXX Filter out reserved bits */
>> lpc->opb_irq_pol = val;
>> + pnv_lpc_eval_irqs(lpc);
>> break;
>> case OPB_MASTER_LS_IRQ_INPUT:
>> /* Read only */
>> @@ -398,6 +430,8 @@ static const MemoryRegionOps opb_master_ops = {
>> static void pnv_lpc_realize(DeviceState *dev, Error **errp)
>> {
>> PnvLpcController *lpc = PNV_LPC(dev);
>> + Object *obj;
>> + Error *error = NULL;
>>
>> /* Reg inits */
>> lpc->lpc_hc_fw_rd_acc_size = LPC_HC_FW_RD_4B;
>> @@ -441,6 +475,15 @@ static void pnv_lpc_realize(DeviceState *dev, Error **errp)
>> pnv_xscom_region_init(&lpc->xscom_regs, OBJECT(dev),
>> &pnv_lpc_xscom_ops, lpc, "xscom-lpc",
>> PNV_XSCOM_LPC_SIZE);
>> +
>> + /* get PSI object from chip */
>> + obj = object_property_get_link(OBJECT(dev), "psi", &error);
>> + if (!obj) {
>> + error_setg(errp, "%s: required link 'psi' not found: %s",
>> + __func__, error_get_pretty(error));
>> + return;
>> + }
>> + lpc->psi = PNV_PSI(obj);
>> }
>>
>> static void pnv_lpc_class_init(ObjectClass *klass, void *data)
>> diff --git a/include/hw/ppc/pnv_lpc.h b/include/hw/ppc/pnv_lpc.h
>> index 38e5506975aa..53040026c37b 100644
>> --- a/include/hw/ppc/pnv_lpc.h
>> +++ b/include/hw/ppc/pnv_lpc.h
>> @@ -23,6 +23,8 @@
>> #define PNV_LPC(obj) \
>> OBJECT_CHECK(PnvLpcController, (obj), TYPE_PNV_LPC)
>>
>> +typedef struct PnvPsi PnvPsi;
>> +
>> typedef struct PnvLpcController {
>> DeviceState parent;
>>
>> @@ -62,6 +64,13 @@ typedef struct PnvLpcController {
>>
>> /* XSCOM registers */
>> MemoryRegion xscom_regs;
>> +
>> + /* PSI to generate interrupts */
>> + PnvPsi *psi;
>> } PnvLpcController;
>>
>> +#define LPC_HC_IRQ_SERIRQ0 0x80000000 /* all bits down to ... */
>> +
>> +void pnv_lpc_eval_irqs(PnvLpcController *lpc);
>> +
>> #endif /* _PPC_PNV_LPC_H */
>
^ permalink raw reply [flat|nested] 66+ messages in thread* Re: [Qemu-devel] [PATCH 03/21] ppc/pnv: Add support for POWER8+ LPC Controller
2017-04-06 2:02 ` David Gibson
2017-04-06 12:27 ` Cédric Le Goater
@ 2017-04-06 12:44 ` Cédric Le Goater
2017-04-06 21:54 ` Benjamin Herrenschmidt
1 sibling, 1 reply; 66+ messages in thread
From: Cédric Le Goater @ 2017-04-06 12:44 UTC (permalink / raw)
To: David Gibson; +Cc: qemu-ppc, qemu-devel, Benjamin Herrenschmidt
On 04/06/2017 04:02 AM, David Gibson wrote:
> On Wed, Apr 05, 2017 at 02:41:28PM +0200, Cédric Le Goater wrote:
>> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>>
>> It adds the Naples chip which supports proper LPC interrupts via the
>> LPC controller rather than via an external CPLD.
>>
>> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>> [clg: - updated for qemu-2.9
>> - ported on latest PowerNV patchset ]
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>> Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
>> ---
>> hw/ppc/pnv.c | 13 ++++++++++++-
>> hw/ppc/pnv_lpc.c | 47 +++++++++++++++++++++++++++++++++++++++++++++--
>> include/hw/ppc/pnv_lpc.h | 9 +++++++++
>> 3 files changed, 66 insertions(+), 3 deletions(-)
>>
>> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
>> index 24e523f554c6..78133e5d20e1 100644
>> --- a/hw/ppc/pnv.c
>> +++ b/hw/ppc/pnv.c
>> @@ -373,7 +373,14 @@ static void pnv_lpc_isa_irq_handler_cpld(void *opaque, int n, int level)
>>
>> static void pnv_lpc_isa_irq_handler(void *opaque, int n, int level)
>> {
>> - /* XXX TODO */
>> + PnvChip *chip = opaque;
>> + PnvLpcController *lpc = &chip->lpc;
>> +
>> + /* The Naples HW latches the 1 levels, clearing is done by SW */
>> + if (level) {
>> + lpc->lpc_hc_irqstat |= LPC_HC_IRQ_SERIRQ0 >> n;
>> + pnv_lpc_eval_irqs(lpc);
>> + }
>> }
>
> Now that you have a more complete LPC model, I think this function,
> and the allocation of the LPC irqs should move into pnv_lpc.c.
>
>
> Apart from that, looks fine.
While I am at changing things, we have a 'cpld_irqstate' under the
machine to model the state of the CPLD chip. It is only used in :
static void pnv_lpc_isa_irq_handler_cpld(void *opaque, int n, int level)
{
PnvMachineState *pnv = POWERNV_MACHINE(qdev_get_machine());
uint32_t old_state = pnv->cpld_irqstate;
PnvLpcController *lpc = opaque;
if (level) {
pnv->cpld_irqstate |= 1u << n;
} else {
pnv->cpld_irqstate &= ~(1u << n);
}
if (pnv->cpld_irqstate != old_state) {
pnv_psi_irq_set(lpc->psi, PSIHB_IRQ_EXTERNAL, pnv->cpld_irqstate != 0);
}
}
May be we could move that under the LPC object even if it is not strictly
correct from a HW pov ?
Thanks,
C.
^ permalink raw reply [flat|nested] 66+ messages in thread* Re: [Qemu-devel] [PATCH 03/21] ppc/pnv: Add support for POWER8+ LPC Controller
2017-04-06 12:44 ` Cédric Le Goater
@ 2017-04-06 21:54 ` Benjamin Herrenschmidt
2017-04-07 6:12 ` Cédric Le Goater
0 siblings, 1 reply; 66+ messages in thread
From: Benjamin Herrenschmidt @ 2017-04-06 21:54 UTC (permalink / raw)
To: Cédric Le Goater, David Gibson; +Cc: qemu-ppc, qemu-devel
On Thu, 2017-04-06 at 14:44 +0200, Cédric Le Goater wrote:
> May be we could move that under the LPC object even if it is not
> strictly
> correct from a HW pov ?
I'm not fan of this. It's really not part of the LPC controller and
it's specific to a certain crop of P8 machines.
Cheers,
Ben.
^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [Qemu-devel] [PATCH 03/21] ppc/pnv: Add support for POWER8+ LPC Controller
2017-04-06 21:54 ` Benjamin Herrenschmidt
@ 2017-04-07 6:12 ` Cédric Le Goater
0 siblings, 0 replies; 66+ messages in thread
From: Cédric Le Goater @ 2017-04-07 6:12 UTC (permalink / raw)
To: Benjamin Herrenschmidt, David Gibson; +Cc: qemu-ppc, qemu-devel
On 04/06/2017 11:54 PM, Benjamin Herrenschmidt wrote:
> On Thu, 2017-04-06 at 14:44 +0200, Cédric Le Goater wrote:
>> May be we could move that under the LPC object even if it is not
>> strictly
>> correct from a HW pov ?
>
> I'm not fan of this. It's really not part of the LPC controller and
> it's specific to a certain crop of P8 machines.
OK Let's keep it there then. no big deal.
Thanks,
C.
^ permalink raw reply [flat|nested] 66+ messages in thread
* [Qemu-devel] [PATCH 04/21] ppc/pnv: enable only one LPC bus
2017-04-05 12:41 [Qemu-devel] [PATCH 00/21] pnv: PSI, OCC, IPMI and PCI models Cédric Le Goater
` (2 preceding siblings ...)
2017-04-05 12:41 ` [Qemu-devel] [PATCH 03/21] ppc/pnv: Add support for POWER8+ LPC Controller Cédric Le Goater
@ 2017-04-05 12:41 ` Cédric Le Goater
2017-04-06 4:23 ` David Gibson
2017-04-05 12:41 ` [Qemu-devel] [PATCH 05/21] ppc: add IPMI support Cédric Le Goater
` (16 subsequent siblings)
20 siblings, 1 reply; 66+ messages in thread
From: Cédric Le Goater @ 2017-04-05 12:41 UTC (permalink / raw)
To: David Gibson
Cc: qemu-ppc, qemu-devel, Cédric Le Goater, Benjamin Herrenschmidt
Multi chip systems only have one LPC bus, on chip 0. The PnvLPC object
will still be created under the PnvChip objects but only the one under
chip 0 will be advertise in the device tree.
Also remove the comment which is slightly wrong. Only chip 0 has a LPC
device node : xscom@3fc0000000000/isa@b0020
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
hw/ppc/pnv.c | 2 ++
hw/ppc/pnv_lpc.c | 20 ++++++++++++--------
include/hw/ppc/pnv_lpc.h | 2 ++
3 files changed, 16 insertions(+), 8 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 78133e5d20e1..493c7eed7980 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -811,6 +811,8 @@ static void pnv_chip_realize(DeviceState *dev, Error **errp)
g_free(typename);
/* Create LPC controller */
+ object_property_set_int(OBJECT(&chip->lpc), chip->chip_id, "chip-id",
+ &error_fatal);
object_property_set_bool(OBJECT(&chip->lpc), true, "realized",
&error_fatal);
pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip->lpc.xscom_regs);
diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c
index 20cbb6a0dbbd..1a212a2a399f 100644
--- a/hw/ppc/pnv_lpc.c
+++ b/hw/ppc/pnv_lpc.c
@@ -92,14 +92,6 @@ enum {
#define LPC_HC_REGS_OPB_SIZE 0x00001000
-/*
- * TODO: the "primary" cell should only be added on chip 0. This is
- * how skiboot chooses the default LPC controller on multichip
- * systems.
- *
- * It would be easly done if we can change the populate() interface to
- * replace the PnvXScomInterface parameter by a PnvChip one
- */
static int pnv_lpc_populate(PnvXScomInterface *dev, void *fdt, int xscom_offset)
{
const char compat[] = "ibm,power8-lpc\0ibm,lpc";
@@ -110,6 +102,12 @@ static int pnv_lpc_populate(PnvXScomInterface *dev, void *fdt, int xscom_offset)
cpu_to_be32(lpc_pcba),
cpu_to_be32(PNV_XSCOM_LPC_SIZE)
};
+ PnvLpcController *lpc = PNV_LPC(dev);
+
+ /* Only populate one LPC bus per system, the one on chip 0.*/
+ if (lpc->chip_id) {
+ return 0;
+ }
name = g_strdup_printf("isa@%x", lpc_pcba);
offset = fdt_add_subnode(fdt, xscom_offset, name);
@@ -486,6 +484,11 @@ static void pnv_lpc_realize(DeviceState *dev, Error **errp)
lpc->psi = PNV_PSI(obj);
}
+static Property pnv_lpc_properties[] = {
+ DEFINE_PROP_UINT32("chip-id", PnvLpcController, chip_id, 0),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
static void pnv_lpc_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -494,6 +497,7 @@ static void pnv_lpc_class_init(ObjectClass *klass, void *data)
xdc->populate = pnv_lpc_populate;
dc->realize = pnv_lpc_realize;
+ dc->props = pnv_lpc_properties;
}
static const TypeInfo pnv_lpc_info = {
diff --git a/include/hw/ppc/pnv_lpc.h b/include/hw/ppc/pnv_lpc.h
index 53040026c37b..dcfadda90090 100644
--- a/include/hw/ppc/pnv_lpc.h
+++ b/include/hw/ppc/pnv_lpc.h
@@ -67,6 +67,8 @@ typedef struct PnvLpcController {
/* PSI to generate interrupts */
PnvPsi *psi;
+
+ uint32_t chip_id;
} PnvLpcController;
#define LPC_HC_IRQ_SERIRQ0 0x80000000 /* all bits down to ... */
--
2.7.4
^ permalink raw reply related [flat|nested] 66+ messages in thread* Re: [Qemu-devel] [PATCH 04/21] ppc/pnv: enable only one LPC bus
2017-04-05 12:41 ` [Qemu-devel] [PATCH 04/21] ppc/pnv: enable only one LPC bus Cédric Le Goater
@ 2017-04-06 4:23 ` David Gibson
2017-04-06 9:06 ` Cédric Le Goater
0 siblings, 1 reply; 66+ messages in thread
From: David Gibson @ 2017-04-06 4:23 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: qemu-ppc, qemu-devel, Benjamin Herrenschmidt
[-- Attachment #1: Type: text/plain, Size: 4037 bytes --]
On Wed, Apr 05, 2017 at 02:41:29PM +0200, Cédric Le Goater wrote:
> Multi chip systems only have one LPC bus, on chip 0. The PnvLPC object
> will still be created under the PnvChip objects but only the one under
> chip 0 will be advertise in the device tree.
>
> Also remove the comment which is slightly wrong. Only chip 0 has a LPC
> device node : xscom@3fc0000000000/isa@b0020
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This seems a very round about way of accomplishing the goal. Wouldn't
it make more sense for the chip to only construct (or only realize)
the LPC if it's chip zero, rather than passing the chip id through to
the lpc object.
> ---
> hw/ppc/pnv.c | 2 ++
> hw/ppc/pnv_lpc.c | 20 ++++++++++++--------
> include/hw/ppc/pnv_lpc.h | 2 ++
> 3 files changed, 16 insertions(+), 8 deletions(-)
>
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index 78133e5d20e1..493c7eed7980 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -811,6 +811,8 @@ static void pnv_chip_realize(DeviceState *dev, Error **errp)
> g_free(typename);
>
> /* Create LPC controller */
> + object_property_set_int(OBJECT(&chip->lpc), chip->chip_id, "chip-id",
> + &error_fatal);
> object_property_set_bool(OBJECT(&chip->lpc), true, "realized",
> &error_fatal);
> pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip->lpc.xscom_regs);
> diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c
> index 20cbb6a0dbbd..1a212a2a399f 100644
> --- a/hw/ppc/pnv_lpc.c
> +++ b/hw/ppc/pnv_lpc.c
> @@ -92,14 +92,6 @@ enum {
> #define LPC_HC_REGS_OPB_SIZE 0x00001000
>
>
> -/*
> - * TODO: the "primary" cell should only be added on chip 0. This is
> - * how skiboot chooses the default LPC controller on multichip
> - * systems.
> - *
> - * It would be easly done if we can change the populate() interface to
> - * replace the PnvXScomInterface parameter by a PnvChip one
> - */
> static int pnv_lpc_populate(PnvXScomInterface *dev, void *fdt, int xscom_offset)
> {
> const char compat[] = "ibm,power8-lpc\0ibm,lpc";
> @@ -110,6 +102,12 @@ static int pnv_lpc_populate(PnvXScomInterface *dev, void *fdt, int xscom_offset)
> cpu_to_be32(lpc_pcba),
> cpu_to_be32(PNV_XSCOM_LPC_SIZE)
> };
> + PnvLpcController *lpc = PNV_LPC(dev);
> +
> + /* Only populate one LPC bus per system, the one on chip 0.*/
> + if (lpc->chip_id) {
> + return 0;
> + }
>
> name = g_strdup_printf("isa@%x", lpc_pcba);
> offset = fdt_add_subnode(fdt, xscom_offset, name);
> @@ -486,6 +484,11 @@ static void pnv_lpc_realize(DeviceState *dev, Error **errp)
> lpc->psi = PNV_PSI(obj);
> }
>
> +static Property pnv_lpc_properties[] = {
> + DEFINE_PROP_UINT32("chip-id", PnvLpcController, chip_id, 0),
> + DEFINE_PROP_END_OF_LIST(),
> +};
> +
> static void pnv_lpc_class_init(ObjectClass *klass, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(klass);
> @@ -494,6 +497,7 @@ static void pnv_lpc_class_init(ObjectClass *klass, void *data)
> xdc->populate = pnv_lpc_populate;
>
> dc->realize = pnv_lpc_realize;
> + dc->props = pnv_lpc_properties;
> }
>
> static const TypeInfo pnv_lpc_info = {
> diff --git a/include/hw/ppc/pnv_lpc.h b/include/hw/ppc/pnv_lpc.h
> index 53040026c37b..dcfadda90090 100644
> --- a/include/hw/ppc/pnv_lpc.h
> +++ b/include/hw/ppc/pnv_lpc.h
> @@ -67,6 +67,8 @@ typedef struct PnvLpcController {
>
> /* PSI to generate interrupts */
> PnvPsi *psi;
> +
> + uint32_t chip_id;
> } PnvLpcController;
>
> #define LPC_HC_IRQ_SERIRQ0 0x80000000 /* all bits down to ... */
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 66+ messages in thread* Re: [Qemu-devel] [PATCH 04/21] ppc/pnv: enable only one LPC bus
2017-04-06 4:23 ` David Gibson
@ 2017-04-06 9:06 ` Cédric Le Goater
2017-04-06 9:16 ` Benjamin Herrenschmidt
0 siblings, 1 reply; 66+ messages in thread
From: Cédric Le Goater @ 2017-04-06 9:06 UTC (permalink / raw)
To: David Gibson; +Cc: qemu-ppc, qemu-devel, Benjamin Herrenschmidt
On 04/06/2017 06:23 AM, David Gibson wrote:
> On Wed, Apr 05, 2017 at 02:41:29PM +0200, Cédric Le Goater wrote:
>> Multi chip systems only have one LPC bus, on chip 0. The PnvLPC object
>> will still be created under the PnvChip objects but only the one under
>> chip 0 will be advertise in the device tree.
>>
>> Also remove the comment which is slightly wrong. Only chip 0 has a LPC
>> device node : xscom@3fc0000000000/isa@b0020
>>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>
> This seems a very round about way of accomplishing the goal. Wouldn't
> it make more sense for the chip to only construct (or only realize)
> the LPC if it's chip zero, rather than passing the chip id through to
> the lpc object.
hmm, yes. I can do better on this.
The object will be initialized which raises some concern because we don't
have the chip id at the moment but the object is still valid in some way.
I think I need to remove it from the list of children of the chip or use
a pointer instead.
Thanks,
C.
>
>> ---
>> hw/ppc/pnv.c | 2 ++
>> hw/ppc/pnv_lpc.c | 20 ++++++++++++--------
>> include/hw/ppc/pnv_lpc.h | 2 ++
>> 3 files changed, 16 insertions(+), 8 deletions(-)
>>
>> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
>> index 78133e5d20e1..493c7eed7980 100644
>> --- a/hw/ppc/pnv.c
>> +++ b/hw/ppc/pnv.c
>> @@ -811,6 +811,8 @@ static void pnv_chip_realize(DeviceState *dev, Error **errp)
>> g_free(typename);
>>
>> /* Create LPC controller */
>> + object_property_set_int(OBJECT(&chip->lpc), chip->chip_id, "chip-id",
>> + &error_fatal);
>> object_property_set_bool(OBJECT(&chip->lpc), true, "realized",
>> &error_fatal);
>> pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip->lpc.xscom_regs);
>> diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c
>> index 20cbb6a0dbbd..1a212a2a399f 100644
>> --- a/hw/ppc/pnv_lpc.c
>> +++ b/hw/ppc/pnv_lpc.c
>> @@ -92,14 +92,6 @@ enum {
>> #define LPC_HC_REGS_OPB_SIZE 0x00001000
>>
>>
>> -/*
>> - * TODO: the "primary" cell should only be added on chip 0. This is
>> - * how skiboot chooses the default LPC controller on multichip
>> - * systems.
>> - *
>> - * It would be easly done if we can change the populate() interface to
>> - * replace the PnvXScomInterface parameter by a PnvChip one
>> - */
>> static int pnv_lpc_populate(PnvXScomInterface *dev, void *fdt, int xscom_offset)
>> {
>> const char compat[] = "ibm,power8-lpc\0ibm,lpc";
>> @@ -110,6 +102,12 @@ static int pnv_lpc_populate(PnvXScomInterface *dev, void *fdt, int xscom_offset)
>> cpu_to_be32(lpc_pcba),
>> cpu_to_be32(PNV_XSCOM_LPC_SIZE)
>> };
>> + PnvLpcController *lpc = PNV_LPC(dev);
>> +
>> + /* Only populate one LPC bus per system, the one on chip 0.*/
>> + if (lpc->chip_id) {
>> + return 0;
>> + }
>>
>> name = g_strdup_printf("isa@%x", lpc_pcba);
>> offset = fdt_add_subnode(fdt, xscom_offset, name);
>> @@ -486,6 +484,11 @@ static void pnv_lpc_realize(DeviceState *dev, Error **errp)
>> lpc->psi = PNV_PSI(obj);
>> }
>>
>> +static Property pnv_lpc_properties[] = {
>> + DEFINE_PROP_UINT32("chip-id", PnvLpcController, chip_id, 0),
>> + DEFINE_PROP_END_OF_LIST(),
>> +};
>> +
>> static void pnv_lpc_class_init(ObjectClass *klass, void *data)
>> {
>> DeviceClass *dc = DEVICE_CLASS(klass);
>> @@ -494,6 +497,7 @@ static void pnv_lpc_class_init(ObjectClass *klass, void *data)
>> xdc->populate = pnv_lpc_populate;
>>
>> dc->realize = pnv_lpc_realize;
>> + dc->props = pnv_lpc_properties;
>> }
>>
>> static const TypeInfo pnv_lpc_info = {
>> diff --git a/include/hw/ppc/pnv_lpc.h b/include/hw/ppc/pnv_lpc.h
>> index 53040026c37b..dcfadda90090 100644
>> --- a/include/hw/ppc/pnv_lpc.h
>> +++ b/include/hw/ppc/pnv_lpc.h
>> @@ -67,6 +67,8 @@ typedef struct PnvLpcController {
>>
>> /* PSI to generate interrupts */
>> PnvPsi *psi;
>> +
>> + uint32_t chip_id;
>> } PnvLpcController;
>>
>> #define LPC_HC_IRQ_SERIRQ0 0x80000000 /* all bits down to ... */
>
^ permalink raw reply [flat|nested] 66+ messages in thread* Re: [Qemu-devel] [PATCH 04/21] ppc/pnv: enable only one LPC bus
2017-04-06 9:06 ` Cédric Le Goater
@ 2017-04-06 9:16 ` Benjamin Herrenschmidt
2017-04-06 11:50 ` Cédric Le Goater
0 siblings, 1 reply; 66+ messages in thread
From: Benjamin Herrenschmidt @ 2017-04-06 9:16 UTC (permalink / raw)
To: Cédric Le Goater, David Gibson; +Cc: qemu-ppc, qemu-devel
On Thu, 2017-04-06 at 11:06 +0200, Cédric Le Goater wrote:
> The object will be initialized which raises some concern because we don't
> have the chip id at the moment but the object is still valid in some way.
> I think I need to remove it from the list of children of the chip or use
> a pointer instead.
Well... so it exists on all chips. All chips have an LPC controller...
Whether firmware enables it and whether it's connected to anything is a
system issue.
Cheers,
Ben.
^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [Qemu-devel] [PATCH 04/21] ppc/pnv: enable only one LPC bus
2017-04-06 9:16 ` Benjamin Herrenschmidt
@ 2017-04-06 11:50 ` Cédric Le Goater
2017-04-06 12:01 ` Benjamin Herrenschmidt
0 siblings, 1 reply; 66+ messages in thread
From: Cédric Le Goater @ 2017-04-06 11:50 UTC (permalink / raw)
To: Benjamin Herrenschmidt, David Gibson; +Cc: qemu-ppc, qemu-devel
On 04/06/2017 11:16 AM, Benjamin Herrenschmidt wrote:
> On Thu, 2017-04-06 at 11:06 +0200, Cédric Le Goater wrote:
>> The object will be initialized which raises some concern because we don't
>> have the chip id at the moment but the object is still valid in some way.
>> I think I need to remove it from the list of children of the chip or use
>> a pointer instead.
>
> Well... so it exists on all chips. All chips have an LPC controller...
>
> Whether firmware enables it and whether it's connected to anything is a
> system issue.
So, looking at hostboot, the lower level firmware, I think the initial
patch is more in sync with it :
https://github.com/open-power/hostboot/blob/master-p8/src/usr/devtree/bld_devtree.C#L1038
David, can we keep it as it is ? I will change the commit log which is
a bit fuzzy.
Cheers,
C.
^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [Qemu-devel] [PATCH 04/21] ppc/pnv: enable only one LPC bus
2017-04-06 11:50 ` Cédric Le Goater
@ 2017-04-06 12:01 ` Benjamin Herrenschmidt
2017-04-06 12:35 ` Cédric Le Goater
0 siblings, 1 reply; 66+ messages in thread
From: Benjamin Herrenschmidt @ 2017-04-06 12:01 UTC (permalink / raw)
To: Cédric Le Goater, David Gibson; +Cc: qemu-ppc, qemu-devel
On Thu, 2017-04-06 at 13:50 +0200, Cédric Le Goater wrote:
>
> So, looking at hostboot, the lower level firmware, I think the
> initial
> patch is more in sync with it :
>
> https://github.com/open-power/hostboot/blob/master-p8/src/usr/devt
> ree/bld_devtree.C#L1038
>
> David, can we keep it as it is ? I will change the commit log which
> is a bit fuzzy.
Note that OPAL should be happy to have multiple LPCs in the DT as long
as one of them has the "primary" property in the node to tell it that's
where the UART etc... are.
Cheers,
Ben.
^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [Qemu-devel] [PATCH 04/21] ppc/pnv: enable only one LPC bus
2017-04-06 12:01 ` Benjamin Herrenschmidt
@ 2017-04-06 12:35 ` Cédric Le Goater
2017-04-06 21:53 ` Benjamin Herrenschmidt
0 siblings, 1 reply; 66+ messages in thread
From: Cédric Le Goater @ 2017-04-06 12:35 UTC (permalink / raw)
To: Benjamin Herrenschmidt, David Gibson; +Cc: qemu-ppc, qemu-devel
On 04/06/2017 02:01 PM, Benjamin Herrenschmidt wrote:
> On Thu, 2017-04-06 at 13:50 +0200, Cédric Le Goater wrote:
>>
>> So, looking at hostboot, the lower level firmware, I think the
>> initial
>> patch is more in sync with it :
>>
>> https://github.com/open-power/hostboot/blob/master-p8/src/usr/devt
>> ree/bld_devtree.C#L1038
>>
>> David, can we keep it as it is ? I will change the commit log which
>> is a bit fuzzy.
>
> Note that OPAL should be happy to have multiple LPCs in the DT as long
> as one of them has the "primary" property in the node to tell it that's
> where the UART etc... are.
yes, that works also :
[ 0.024439731,5] LPC: LPC[000]: Initialized, access via XSCOM @0xb0020
[ 0.024499074,5] LPC: LPC[001]: Initialized, access via XSCOM @0xb0020
[ 0.024517962,5] LPC: LPC: Default bus on chip 0x0
but real HW (2 sockets OpenPOWER systems, garrison and firestone) does
not expose the LPC bus on the second chip, should we do so in qemu ?
Thanks,
C.
^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [Qemu-devel] [PATCH 04/21] ppc/pnv: enable only one LPC bus
2017-04-06 12:35 ` Cédric Le Goater
@ 2017-04-06 21:53 ` Benjamin Herrenschmidt
2017-04-07 6:14 ` Cédric Le Goater
0 siblings, 1 reply; 66+ messages in thread
From: Benjamin Herrenschmidt @ 2017-04-06 21:53 UTC (permalink / raw)
To: Cédric Le Goater, David Gibson; +Cc: qemu-ppc, qemu-devel
On Thu, 2017-04-06 at 14:35 +0200, Cédric Le Goater wrote:
> but real HW (2 sockets OpenPOWER systems, garrison and firestone)
> does
> not expose the LPC bus on the second chip, should we do so in qemu ?
It's not so much HW as it it HostBoot. Not a huge deal.
Cheers,
Ben.
^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [Qemu-devel] [PATCH 04/21] ppc/pnv: enable only one LPC bus
2017-04-06 21:53 ` Benjamin Herrenschmidt
@ 2017-04-07 6:14 ` Cédric Le Goater
2017-04-08 2:14 ` David Gibson
0 siblings, 1 reply; 66+ messages in thread
From: Cédric Le Goater @ 2017-04-07 6:14 UTC (permalink / raw)
To: Benjamin Herrenschmidt, David Gibson; +Cc: qemu-ppc, qemu-devel
On 04/06/2017 11:53 PM, Benjamin Herrenschmidt wrote:
> On Thu, 2017-04-06 at 14:35 +0200, Cédric Le Goater wrote:
>> but real HW (2 sockets OpenPOWER systems, garrison and firestone)
>> does
>> not expose the LPC bus on the second chip, should we do so in qemu ?
>
> It's not so much HW as it it HostBoot. Not a huge deal.
So let's have QEMU populate the second LPC bus without the "primary"
prop then. It's a different approach than hostboot, but it's good for
testing anyhow.
Thanks,
C.
^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [Qemu-devel] [PATCH 04/21] ppc/pnv: enable only one LPC bus
2017-04-07 6:14 ` Cédric Le Goater
@ 2017-04-08 2:14 ` David Gibson
0 siblings, 0 replies; 66+ messages in thread
From: David Gibson @ 2017-04-08 2:14 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: Benjamin Herrenschmidt, qemu-ppc, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 795 bytes --]
On Fri, Apr 07, 2017 at 08:14:36AM +0200, Cédric Le Goater wrote:
> On 04/06/2017 11:53 PM, Benjamin Herrenschmidt wrote:
> > On Thu, 2017-04-06 at 14:35 +0200, Cédric Le Goater wrote:
> >> but real HW (2 sockets OpenPOWER systems, garrison and firestone)
> >> does
> >> not expose the LPC bus on the second chip, should we do so in qemu ?
> >
> > It's not so much HW as it it HostBoot. Not a huge deal.
>
> So let's have QEMU populate the second LPC bus without the "primary"
> prop then. It's a different approach than hostboot, but it's good for
> testing anyhow.
Works for me.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 66+ messages in thread
* [Qemu-devel] [PATCH 05/21] ppc: add IPMI support
2017-04-05 12:41 [Qemu-devel] [PATCH 00/21] pnv: PSI, OCC, IPMI and PCI models Cédric Le Goater
` (3 preceding siblings ...)
2017-04-05 12:41 ` [Qemu-devel] [PATCH 04/21] ppc/pnv: enable only one LPC bus Cédric Le Goater
@ 2017-04-05 12:41 ` Cédric Le Goater
2017-04-05 12:41 ` [Qemu-devel] [PATCH 06/21] ipmi: use a file to load SDRs Cédric Le Goater
` (15 subsequent siblings)
20 siblings, 0 replies; 66+ messages in thread
From: Cédric Le Goater @ 2017-04-05 12:41 UTC (permalink / raw)
To: David Gibson; +Cc: qemu-ppc, qemu-devel, Cédric Le Goater
OpenPOWER systems use a BT device to communicate with the BMC.
Provide support for it.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
default-configs/ppc64-softmmu.mak | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/default-configs/ppc64-softmmu.mak b/default-configs/ppc64-softmmu.mak
index 05c83356e12a..7f5b56cbbe9e 100644
--- a/default-configs/ppc64-softmmu.mak
+++ b/default-configs/ppc64-softmmu.mak
@@ -6,6 +6,10 @@ include usb.mak
CONFIG_VIRTIO_VGA=y
CONFIG_ESCC=y
CONFIG_M48T59=y
+CONFIG_IPMI=y
+CONFIG_IPMI_LOCAL=y
+CONFIG_IPMI_EXTERN=y
+CONFIG_ISA_IPMI_BT=y
CONFIG_SERIAL=y
CONFIG_PARALLEL=y
CONFIG_I8254=y
--
2.7.4
^ permalink raw reply related [flat|nested] 66+ messages in thread* [Qemu-devel] [PATCH 06/21] ipmi: use a file to load SDRs
2017-04-05 12:41 [Qemu-devel] [PATCH 00/21] pnv: PSI, OCC, IPMI and PCI models Cédric Le Goater
` (4 preceding siblings ...)
2017-04-05 12:41 ` [Qemu-devel] [PATCH 05/21] ppc: add IPMI support Cédric Le Goater
@ 2017-04-05 12:41 ` Cédric Le Goater
2017-04-05 12:41 ` [Qemu-devel] [PATCH 07/21] ipmi: provide support for FRUs Cédric Le Goater
` (14 subsequent siblings)
20 siblings, 0 replies; 66+ messages in thread
From: Cédric Le Goater @ 2017-04-05 12:41 UTC (permalink / raw)
To: David Gibson
Cc: qemu-ppc, qemu-devel, Cédric Le Goater, Marcel Apfelbaum,
Michael S. Tsirkin, Corey Minyard
The IPMI BMC simulator populates the sdr/sensor tables with a minimal
set of entries (Watchdog). But some qemu platforms might want to use
extra entries for their custom needs.
This patch modifies slighty the initializing routine to take into
account a larger set read from a file. The name of the file to use is
defined through a new 'sdr' property of the simulator device.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Acked-by: Corey Minyard <cminyard@mvista.com>
Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
---
Changes since v1:
- log an error if file does not exist.
- change property name to 'sdrfile'
- add documentation of new properties
hw/ipmi/ipmi_bmc_sim.c | 23 +++++++++++++++++++++--
hw/ipmi/ipmi_bmc_sim.c | 23 +++++++++++++++++++++--
qemu-options.hx | 11 ++++++++++-
2 files changed, 31 insertions(+), 3 deletions(-)
diff --git a/hw/ipmi/ipmi_bmc_sim.c b/hw/ipmi/ipmi_bmc_sim.c
index c7883d6f5e6a..1142c0caae66 100644
--- a/hw/ipmi/ipmi_bmc_sim.c
+++ b/hw/ipmi/ipmi_bmc_sim.c
@@ -27,6 +27,7 @@
#include "qemu/timer.h"
#include "hw/ipmi/ipmi.h"
#include "qemu/error-report.h"
+#include "hw/loader.h"
#define IPMI_NETFN_CHASSIS 0x00
@@ -213,6 +214,7 @@ struct IPMIBmcSim {
IPMISel sel;
IPMISdr sdr;
IPMISensor sensors[MAX_SENSORS];
+ char *sdr_filename;
/* Odd netfns are for responses, so we only need the even ones. */
const IPMINetfn *netfns[MAX_NETFNS / 2];
@@ -1696,22 +1698,33 @@ static void ipmi_sdr_init(IPMIBmcSim *ibs)
sdrs_size = sizeof(init_sdrs);
sdrs = init_sdrs;
+ if (ibs->sdr_filename &&
+ !g_file_get_contents(ibs->sdr_filename, (gchar **) &sdrs, &sdrs_size,
+ NULL)) {
+ error_report("failed to load sdr file '%s'", ibs->sdr_filename);
+ sdrs_size = sizeof(init_sdrs);
+ sdrs = init_sdrs;
+ }
for (i = 0; i < sdrs_size; i += len) {
struct ipmi_sdr_header *sdrh;
if (i + IPMI_SDR_HEADER_SIZE > sdrs_size) {
error_report("Problem with recid 0x%4.4x", i);
- return;
+ break;
}
sdrh = (struct ipmi_sdr_header *) &sdrs[i];
len = ipmi_sdr_length(sdrh);
if (i + len > sdrs_size) {
error_report("Problem with recid 0x%4.4x", i);
- return;
+ break;
}
sdr_add_entry(ibs, sdrh, len, NULL);
}
+
+ if (sdrs != init_sdrs) {
+ g_free(sdrs);
+ }
}
static const VMStateDescription vmstate_ipmi_sim = {
@@ -1780,6 +1793,11 @@ static void ipmi_sim_realize(DeviceState *dev, Error **errp)
vmstate_register(NULL, 0, &vmstate_ipmi_sim, ibs);
}
+static Property ipmi_sim_properties[] = {
+ DEFINE_PROP_STRING("sdrfile", IPMIBmcSim, sdr_filename),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
static void ipmi_sim_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
@@ -1787,6 +1805,7 @@ static void ipmi_sim_class_init(ObjectClass *oc, void *data)
dc->hotpluggable = false;
dc->realize = ipmi_sim_realize;
+ dc->props = ipmi_sim_properties;
bk->handle_command = ipmi_sim_handle_command;
}
diff --git a/qemu-options.hx b/qemu-options.hx
index 99af8edf5f30..10b755ee4a5e 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -425,7 +425,7 @@ possible drivers and properties, use @code{-device help} and
@code{-device @var{driver},help}.
Some drivers are:
-@item -device ipmi-bmc-sim,id=@var{id}[,slave_addr=@var{val}]
+@item -device ipmi-bmc-sim,id=@var{id}[,slave_addr=@var{val}][,sdrfile=@var{file}]
Add an IPMI BMC. This is a simulation of a hardware management
interface processor that normally sits on a system. It provides
@@ -437,6 +437,15 @@ This address is the BMC's address on the I2C network of management
controllers. If you don't know what this means, it is safe to ignore
it.
+@table @option
+@item bmc=@var{id}
+The BMC to connect to, one of ipmi-bmc-sim or ipmi-bmc-extern above.
+@item slave_addr=@var{val}
+Define slave address to use for the BMC. The default is 0x20.
+@item sdrfile=@var{file}
+file containing raw Sensor Data Records (SDR) data. The default is none.
+@end table
+
@item -device ipmi-bmc-extern,id=@var{id},chardev=@var{id}[,slave_addr=@var{val}]
Add a connection to an external IPMI BMC simulator. Instead of
--
2.7.4
^ permalink raw reply related [flat|nested] 66+ messages in thread* [Qemu-devel] [PATCH 07/21] ipmi: provide support for FRUs
2017-04-05 12:41 [Qemu-devel] [PATCH 00/21] pnv: PSI, OCC, IPMI and PCI models Cédric Le Goater
` (5 preceding siblings ...)
2017-04-05 12:41 ` [Qemu-devel] [PATCH 06/21] ipmi: use a file to load SDRs Cédric Le Goater
@ 2017-04-05 12:41 ` Cédric Le Goater
2017-04-05 12:41 ` [Qemu-devel] [PATCH 08/21] ipmi: introduce an ipmi_bmc_sdr_find() API Cédric Le Goater
` (13 subsequent siblings)
20 siblings, 0 replies; 66+ messages in thread
From: Cédric Le Goater @ 2017-04-05 12:41 UTC (permalink / raw)
To: David Gibson
Cc: qemu-ppc, qemu-devel, Cédric Le Goater, Marcel Apfelbaum,
Michael S. Tsirkin, Corey Minyard
This patch provides a simple FRU support for the BMC simulator. FRUs
are loaded from a file which name is specified in the object
properties, each entry having a fixed size, also specified in the
properties. If the file is unknown or not accessible for some reason,
a unique entry of 1024 bytes is created as a default. Just enough to
start some simulation.
These commands complies with the IPMI spec : "34. FRU Inventory Device
Commands".
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Acked-by: Corey Minyard <cminyard@mvista.com>
---
Changes since v3:
- removed min/max definitions and used MIN() from "qemu/osdep.h"
Changes since v2:
- changed 'struct rsp_buffer' to 'RspBuffer'
Changes since v1:
- change property name to 'fruareasize' and 'frudatafile'
- add documentation of new properties
hw/ipmi/ipmi_bmc_sim.c | 128 +++++++++++++++++++++++++++++++++++++++++++++++++
qemu-options.hx | 8 +++-
2 files changed, 134 insertions(+), 2 deletions(-)
diff --git a/hw/ipmi/ipmi_bmc_sim.c b/hw/ipmi/ipmi_bmc_sim.c
index 1142c0caae66..eae7b2d8c92b 100644
--- a/hw/ipmi/ipmi_bmc_sim.c
+++ b/hw/ipmi/ipmi_bmc_sim.c
@@ -80,6 +80,9 @@
#define IPMI_CMD_ENTER_SDR_REP_UPD_MODE 0x2A
#define IPMI_CMD_EXIT_SDR_REP_UPD_MODE 0x2B
#define IPMI_CMD_RUN_INIT_AGENT 0x2C
+#define IPMI_CMD_GET_FRU_AREA_INFO 0x10
+#define IPMI_CMD_READ_FRU_DATA 0x11
+#define IPMI_CMD_WRITE_FRU_DATA 0x12
#define IPMI_CMD_GET_SEL_INFO 0x40
#define IPMI_CMD_GET_SEL_ALLOC_INFO 0x41
#define IPMI_CMD_RESERVE_SEL 0x42
@@ -122,6 +125,13 @@ typedef struct IPMISdr {
uint8_t overflow;
} IPMISdr;
+typedef struct IPMIFru {
+ char *filename;
+ unsigned int nentries;
+ uint16_t areasize;
+ uint8_t *data;
+} IPMIFru;
+
typedef struct IPMISensor {
uint8_t status;
uint8_t reading;
@@ -213,6 +223,7 @@ struct IPMIBmcSim {
IPMISel sel;
IPMISdr sdr;
+ IPMIFru fru;
IPMISensor sensors[MAX_SENSORS];
char *sdr_filename;
@@ -1317,6 +1328,91 @@ static void get_sel_info(IPMIBmcSim *ibs,
rsp_buffer_push(rsp, (ibs->sel.overflow << 7) | 0x02);
}
+static void get_fru_area_info(IPMIBmcSim *ibs,
+ uint8_t *cmd, unsigned int cmd_len,
+ RspBuffer *rsp)
+{
+ uint8_t fruid;
+ uint16_t fru_entry_size;
+
+ fruid = cmd[2];
+
+ if (fruid >= ibs->fru.nentries) {
+ rsp_buffer_set_error(rsp, IPMI_CC_INVALID_DATA_FIELD);
+ return;
+ }
+
+ fru_entry_size = ibs->fru.areasize;
+
+ rsp_buffer_push(rsp, fru_entry_size & 0xff);
+ rsp_buffer_push(rsp, fru_entry_size >> 8 & 0xff);
+ rsp_buffer_push(rsp, 0x0);
+}
+
+static void read_fru_data(IPMIBmcSim *ibs,
+ uint8_t *cmd, unsigned int cmd_len,
+ RspBuffer *rsp)
+{
+ uint8_t fruid;
+ uint16_t offset;
+ int i;
+ uint8_t *fru_entry;
+ unsigned int count;
+
+ fruid = cmd[2];
+ offset = (cmd[3] | cmd[4] << 8);
+
+ if (fruid >= ibs->fru.nentries) {
+ rsp_buffer_set_error(rsp, IPMI_CC_INVALID_DATA_FIELD);
+ return;
+ }
+
+ if (offset >= ibs->fru.areasize - 1) {
+ rsp_buffer_set_error(rsp, IPMI_CC_INVALID_DATA_FIELD);
+ return;
+ }
+
+ fru_entry = &ibs->fru.data[fruid * ibs->fru.areasize];
+
+ count = MIN(cmd[5], ibs->fru.areasize - offset);
+
+ rsp_buffer_push(rsp, count & 0xff);
+ for (i = 0; i < count; i++) {
+ rsp_buffer_push(rsp, fru_entry[offset + i]);
+ }
+}
+
+static void write_fru_data(IPMIBmcSim *ibs,
+ uint8_t *cmd, unsigned int cmd_len,
+ RspBuffer *rsp)
+{
+ uint8_t fruid;
+ uint16_t offset;
+ uint8_t *fru_entry;
+ unsigned int count;
+
+ fruid = cmd[2];
+ offset = (cmd[3] | cmd[4] << 8);
+
+ if (fruid >= ibs->fru.nentries) {
+ rsp_buffer_set_error(rsp, IPMI_CC_INVALID_DATA_FIELD);
+ return;
+ }
+
+ if (offset >= ibs->fru.areasize - 1) {
+ rsp_buffer_set_error(rsp, IPMI_CC_INVALID_DATA_FIELD);
+ return;
+ }
+
+ fru_entry = &ibs->fru.data[fruid * ibs->fru.areasize];
+
+ count = MIN(cmd_len - 5, ibs->fru.areasize - offset);
+
+ memcpy(fru_entry + offset, cmd + 5, count);
+
+ rsp_buffer_push(rsp, count & 0xff);
+}
+
static void reserve_sel(IPMIBmcSim *ibs,
uint8_t *cmd, unsigned int cmd_len,
RspBuffer *rsp)
@@ -1653,6 +1749,9 @@ static const IPMINetfn app_netfn = {
};
static const IPMICmdHandler storage_cmds[] = {
+ [IPMI_CMD_GET_FRU_AREA_INFO] = { get_fru_area_info, 3 },
+ [IPMI_CMD_READ_FRU_DATA] = { read_fru_data, 5 },
+ [IPMI_CMD_WRITE_FRU_DATA] = { write_fru_data, 5 },
[IPMI_CMD_GET_SDR_REP_INFO] = { get_sdr_rep_info },
[IPMI_CMD_RESERVE_SDR_REP] = { reserve_sdr_rep },
[IPMI_CMD_GET_SDR] = { get_sdr, 8 },
@@ -1755,6 +1854,31 @@ static const VMStateDescription vmstate_ipmi_sim = {
}
};
+static void ipmi_fru_init(IPMIFru *fru)
+{
+ int fsize;
+ int size = 0;
+
+ fsize = get_image_size(fru->filename);
+ if (fsize > 0) {
+ size = QEMU_ALIGN_UP(fsize, fru->areasize);
+ fru->data = g_malloc0(size);
+ if (load_image_size(fru->filename, fru->data, fsize) != fsize) {
+ error_report("Could not load file '%s'", fru->filename);
+ g_free(fru->data);
+ fru->data = NULL;
+ }
+ }
+
+ if (!fru->data) {
+ /* give one default FRU */
+ size = fru->areasize;
+ fru->data = g_malloc0(size);
+ }
+
+ fru->nentries = size / fru->areasize;
+}
+
static void ipmi_sim_realize(DeviceState *dev, Error **errp)
{
IPMIBmc *b = IPMI_BMC(dev);
@@ -1776,6 +1900,8 @@ static void ipmi_sim_realize(DeviceState *dev, Error **errp)
ipmi_sdr_init(ibs);
+ ipmi_fru_init(&ibs->fru);
+
ibs->acpi_power_state[0] = 0;
ibs->acpi_power_state[1] = 0;
@@ -1794,6 +1920,8 @@ static void ipmi_sim_realize(DeviceState *dev, Error **errp)
}
static Property ipmi_sim_properties[] = {
+ DEFINE_PROP_UINT16("fruareasize", IPMIBmcSim, fru.areasize, 1024),
+ DEFINE_PROP_STRING("frudatafile", IPMIBmcSim, fru.filename),
DEFINE_PROP_STRING("sdrfile", IPMIBmcSim, sdr_filename),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/qemu-options.hx b/qemu-options.hx
index 10b755ee4a5e..86b0904d6b79 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -425,7 +425,7 @@ possible drivers and properties, use @code{-device help} and
@code{-device @var{driver},help}.
Some drivers are:
-@item -device ipmi-bmc-sim,id=@var{id}[,slave_addr=@var{val}][,sdrfile=@var{file}]
+@item -device ipmi-bmc-sim,id=@var{id}[,slave_addr=@var{val}][,sdrfile=@var{file}][,furareasize=@var{val}][,furdatafile=@var{file}]
Add an IPMI BMC. This is a simulation of a hardware management
interface processor that normally sits on a system. It provides
@@ -443,7 +443,11 @@ The BMC to connect to, one of ipmi-bmc-sim or ipmi-bmc-extern above.
@item slave_addr=@var{val}
Define slave address to use for the BMC. The default is 0x20.
@item sdrfile=@var{file}
-file containing raw Sensor Data Records (SDR) data. The default is none.
+file containing raw Sensor Data Records (SDR) data. The default is none.
+@item fruareasize=@var{val}
+size of a Field Replaceable Unit (FRU) area. The default is 1024.
+@item frudatafile=@var{file}
+file containing raw Field Replaceable Unit (FRU) inventory data. The default is none.
@end table
@item -device ipmi-bmc-extern,id=@var{id},chardev=@var{id}[,slave_addr=@var{val}]
--
2.7.4
^ permalink raw reply related [flat|nested] 66+ messages in thread* [Qemu-devel] [PATCH 08/21] ipmi: introduce an ipmi_bmc_sdr_find() API
2017-04-05 12:41 [Qemu-devel] [PATCH 00/21] pnv: PSI, OCC, IPMI and PCI models Cédric Le Goater
` (6 preceding siblings ...)
2017-04-05 12:41 ` [Qemu-devel] [PATCH 07/21] ipmi: provide support for FRUs Cédric Le Goater
@ 2017-04-05 12:41 ` Cédric Le Goater
2017-04-06 5:36 ` David Gibson
2017-04-05 12:41 ` [Qemu-devel] [PATCH 09/21] ipmi: introduce an ipmi_bmc_gen_event() API Cédric Le Goater
` (12 subsequent siblings)
20 siblings, 1 reply; 66+ messages in thread
From: Cédric Le Goater @ 2017-04-05 12:41 UTC (permalink / raw)
To: David Gibson
Cc: qemu-ppc, qemu-devel, Cédric Le Goater, Marcel Apfelbaum,
Michael S. Tsirkin, Corey Minyard
This patch exposes a new IPMI routine to query a sdr entry from the
sdr table maintained by the IPMI BMC simulator. The API is very
similar to the internal sdr_find_entry() routine and should be used
the same way to query one or all sdrs.
A typical use would be to loop on the sdrs to build nodes of a device
tree.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Acked-by: Corey Minyard <cminyard@mvista.com>
---
hw/ipmi/ipmi_bmc_sim.c | 16 ++++++++++++++++
include/hw/ipmi/ipmi.h | 2 ++
2 files changed, 18 insertions(+)
diff --git a/hw/ipmi/ipmi_bmc_sim.c b/hw/ipmi/ipmi_bmc_sim.c
index eae7b2d8c92b..8185a84b76b9 100644
--- a/hw/ipmi/ipmi_bmc_sim.c
+++ b/hw/ipmi/ipmi_bmc_sim.c
@@ -416,6 +416,22 @@ static int sdr_find_entry(IPMISdr *sdr, uint16_t recid,
return 1;
}
+int ipmi_bmc_sdr_find(IPMIBmc *b, uint16_t recid,
+ const struct ipmi_sdr_compact **sdr, uint16_t *nextrec)
+
+{
+ IPMIBmcSim *ibs = IPMI_BMC_SIMULATOR(b);
+ unsigned int pos;
+
+ pos = 0;
+ if (sdr_find_entry(&ibs->sdr, recid, &pos, nextrec)) {
+ return -1;
+ }
+
+ *sdr = (const struct ipmi_sdr_compact *) &ibs->sdr.sdr[pos];
+ return 0;
+}
+
static void sel_inc_reservation(IPMISel *sel)
{
sel->reservation++;
diff --git a/include/hw/ipmi/ipmi.h b/include/hw/ipmi/ipmi.h
index 91b83b5bb0b6..0d36cfc6b7f3 100644
--- a/include/hw/ipmi/ipmi.h
+++ b/include/hw/ipmi/ipmi.h
@@ -259,4 +259,6 @@ struct ipmi_sdr_compact {
typedef uint8_t ipmi_sdr_compact_buffer[sizeof(struct ipmi_sdr_compact)];
+int ipmi_bmc_sdr_find(IPMIBmc *b, uint16_t recid,
+ const struct ipmi_sdr_compact **sdr, uint16_t *nextrec);
#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 66+ messages in thread* Re: [Qemu-devel] [PATCH 08/21] ipmi: introduce an ipmi_bmc_sdr_find() API
2017-04-05 12:41 ` [Qemu-devel] [PATCH 08/21] ipmi: introduce an ipmi_bmc_sdr_find() API Cédric Le Goater
@ 2017-04-06 5:36 ` David Gibson
2017-04-06 7:36 ` Cédric Le Goater
0 siblings, 1 reply; 66+ messages in thread
From: David Gibson @ 2017-04-06 5:36 UTC (permalink / raw)
To: Cédric Le Goater
Cc: qemu-ppc, qemu-devel, Marcel Apfelbaum, Michael S. Tsirkin,
Corey Minyard
[-- Attachment #1: Type: text/plain, Size: 2255 bytes --]
On Wed, Apr 05, 2017 at 02:41:33PM +0200, Cédric Le Goater wrote:
> This patch exposes a new IPMI routine to query a sdr entry from the
> sdr table maintained by the IPMI BMC simulator. The API is very
> similar to the internal sdr_find_entry() routine and should be used
> the same way to query one or all sdrs.
>
> A typical use would be to loop on the sdrs to build nodes of a device
> tree.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> Acked-by: Corey Minyard <cminyard@mvista.com>
I don't know much about IPMI, but since it has Corey's ack, I've
staged 5..8/21 in my for-2.10 tree. 9 I've left for now, since Corey
has comments.
> ---
> hw/ipmi/ipmi_bmc_sim.c | 16 ++++++++++++++++
> include/hw/ipmi/ipmi.h | 2 ++
> 2 files changed, 18 insertions(+)
>
> diff --git a/hw/ipmi/ipmi_bmc_sim.c b/hw/ipmi/ipmi_bmc_sim.c
> index eae7b2d8c92b..8185a84b76b9 100644
> --- a/hw/ipmi/ipmi_bmc_sim.c
> +++ b/hw/ipmi/ipmi_bmc_sim.c
> @@ -416,6 +416,22 @@ static int sdr_find_entry(IPMISdr *sdr, uint16_t recid,
> return 1;
> }
>
> +int ipmi_bmc_sdr_find(IPMIBmc *b, uint16_t recid,
> + const struct ipmi_sdr_compact **sdr, uint16_t *nextrec)
> +
> +{
> + IPMIBmcSim *ibs = IPMI_BMC_SIMULATOR(b);
> + unsigned int pos;
> +
> + pos = 0;
> + if (sdr_find_entry(&ibs->sdr, recid, &pos, nextrec)) {
> + return -1;
> + }
> +
> + *sdr = (const struct ipmi_sdr_compact *) &ibs->sdr.sdr[pos];
> + return 0;
> +}
> +
> static void sel_inc_reservation(IPMISel *sel)
> {
> sel->reservation++;
> diff --git a/include/hw/ipmi/ipmi.h b/include/hw/ipmi/ipmi.h
> index 91b83b5bb0b6..0d36cfc6b7f3 100644
> --- a/include/hw/ipmi/ipmi.h
> +++ b/include/hw/ipmi/ipmi.h
> @@ -259,4 +259,6 @@ struct ipmi_sdr_compact {
>
> typedef uint8_t ipmi_sdr_compact_buffer[sizeof(struct ipmi_sdr_compact)];
>
> +int ipmi_bmc_sdr_find(IPMIBmc *b, uint16_t recid,
> + const struct ipmi_sdr_compact **sdr, uint16_t *nextrec);
> #endif
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 66+ messages in thread* Re: [Qemu-devel] [PATCH 08/21] ipmi: introduce an ipmi_bmc_sdr_find() API
2017-04-06 5:36 ` David Gibson
@ 2017-04-06 7:36 ` Cédric Le Goater
2017-04-06 7:38 ` Cédric Le Goater
0 siblings, 1 reply; 66+ messages in thread
From: Cédric Le Goater @ 2017-04-06 7:36 UTC (permalink / raw)
To: David Gibson
Cc: qemu-ppc, qemu-devel, Marcel Apfelbaum, Michael S. Tsirkin,
Corey Minyard
On 04/06/2017 07:36 AM, David Gibson wrote:
> On Wed, Apr 05, 2017 at 02:41:33PM +0200, Cédric Le Goater wrote:
>> This patch exposes a new IPMI routine to query a sdr entry from the
>> sdr table maintained by the IPMI BMC simulator. The API is very
>> similar to the internal sdr_find_entry() routine and should be used
>> the same way to query one or all sdrs.
>>
>> A typical use would be to loop on the sdrs to build nodes of a device
>> tree.
>>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>> Acked-by: Corey Minyard <cminyard@mvista.com>
>
> I don't know much about IPMI, but since it has Corey's ack, I've
> staged 5..8/21 in my for-2.10 tree.
thanks for doing so. The patchset needs the interface introduced in
patch 9 and 10 to build the sensor nodes in the device tree and to
generate shutdown events which is important for the machine.
> 9 I've left for now, since Corey has comments.
It's patch 10 in fact which is about the SET_SENSOR_READING command.
I think this is the most complex command in the IPMI specs ... It's
not a strong requirement for the firmware but as I have started it
I am trying to reach a minimal and correct implementation ... It really
is giving me headaches tough. I am glad that Corey is giving some
support.
C.
>> ---
>> hw/ipmi/ipmi_bmc_sim.c | 16 ++++++++++++++++
>> include/hw/ipmi/ipmi.h | 2 ++
>> 2 files changed, 18 insertions(+)
>>
>> diff --git a/hw/ipmi/ipmi_bmc_sim.c b/hw/ipmi/ipmi_bmc_sim.c
>> index eae7b2d8c92b..8185a84b76b9 100644
>> --- a/hw/ipmi/ipmi_bmc_sim.c
>> +++ b/hw/ipmi/ipmi_bmc_sim.c
>> @@ -416,6 +416,22 @@ static int sdr_find_entry(IPMISdr *sdr, uint16_t recid,
>> return 1;
>> }
>>
>> +int ipmi_bmc_sdr_find(IPMIBmc *b, uint16_t recid,
>> + const struct ipmi_sdr_compact **sdr, uint16_t *nextrec)
>> +
>> +{
>> + IPMIBmcSim *ibs = IPMI_BMC_SIMULATOR(b);
>> + unsigned int pos;
>> +
>> + pos = 0;
>> + if (sdr_find_entry(&ibs->sdr, recid, &pos, nextrec)) {
>> + return -1;
>> + }
>> +
>> + *sdr = (const struct ipmi_sdr_compact *) &ibs->sdr.sdr[pos];
>> + return 0;
>> +}
>> +
>> static void sel_inc_reservation(IPMISel *sel)
>> {
>> sel->reservation++;
>> diff --git a/include/hw/ipmi/ipmi.h b/include/hw/ipmi/ipmi.h
>> index 91b83b5bb0b6..0d36cfc6b7f3 100644
>> --- a/include/hw/ipmi/ipmi.h
>> +++ b/include/hw/ipmi/ipmi.h
>> @@ -259,4 +259,6 @@ struct ipmi_sdr_compact {
>>
>> typedef uint8_t ipmi_sdr_compact_buffer[sizeof(struct ipmi_sdr_compact)];
>>
>> +int ipmi_bmc_sdr_find(IPMIBmc *b, uint16_t recid,
>> + const struct ipmi_sdr_compact **sdr, uint16_t *nextrec);
>> #endif
>
^ permalink raw reply [flat|nested] 66+ messages in thread* Re: [Qemu-devel] [PATCH 08/21] ipmi: introduce an ipmi_bmc_sdr_find() API
2017-04-06 7:36 ` Cédric Le Goater
@ 2017-04-06 7:38 ` Cédric Le Goater
0 siblings, 0 replies; 66+ messages in thread
From: Cédric Le Goater @ 2017-04-06 7:38 UTC (permalink / raw)
To: David Gibson
Cc: Marcel Apfelbaum, Corey Minyard, qemu-ppc, qemu-devel,
Michael S. Tsirkin
On 04/06/2017 09:36 AM, Cédric Le Goater wrote:
> On 04/06/2017 07:36 AM, David Gibson wrote:
>> On Wed, Apr 05, 2017 at 02:41:33PM +0200, Cédric Le Goater wrote:
>>> This patch exposes a new IPMI routine to query a sdr entry from the
>>> sdr table maintained by the IPMI BMC simulator. The API is very
>>> similar to the internal sdr_find_entry() routine and should be used
>>> the same way to query one or all sdrs.
>>>
>>> A typical use would be to loop on the sdrs to build nodes of a device
>>> tree.
>>>
>>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>>> Acked-by: Corey Minyard <cminyard@mvista.com>
>>
>> I don't know much about IPMI, but since it has Corey's ack, I've
>> staged 5..8/21 in my for-2.10 tree.
>
> thanks for doing so. The patchset needs the interface introduced in
> patch 9 and 10 to build the sensor nodes in the device tree and to
oups, I meant patch 8 and 9 :
[PATCH 08/21] ipmi: introduce an ipmi_bmc_sdr_find() API
[PATCH 09/21] ipmi: introduce an ipmi_bmc_gen_event() API
sorry for the noise.
C.
> generate shutdown events which is important for the machine.
>
>> 9 I've left for now, since Corey has comments.
>
> It's patch 10 in fact which is about the SET_SENSOR_READING command.
>
> I think this is the most complex command in the IPMI specs ... It's
> not a strong requirement for the firmware but as I have started it
> I am trying to reach a minimal and correct implementation ... It really
> is giving me headaches tough. I am glad that Corey is giving some
> support.
>
> C.
>
>>> ---
>>> hw/ipmi/ipmi_bmc_sim.c | 16 ++++++++++++++++
>>> include/hw/ipmi/ipmi.h | 2 ++
>>> 2 files changed, 18 insertions(+)
>>>
>>> diff --git a/hw/ipmi/ipmi_bmc_sim.c b/hw/ipmi/ipmi_bmc_sim.c
>>> index eae7b2d8c92b..8185a84b76b9 100644
>>> --- a/hw/ipmi/ipmi_bmc_sim.c
>>> +++ b/hw/ipmi/ipmi_bmc_sim.c
>>> @@ -416,6 +416,22 @@ static int sdr_find_entry(IPMISdr *sdr, uint16_t recid,
>>> return 1;
>>> }
>>>
>>> +int ipmi_bmc_sdr_find(IPMIBmc *b, uint16_t recid,
>>> + const struct ipmi_sdr_compact **sdr, uint16_t *nextrec)
>>> +
>>> +{
>>> + IPMIBmcSim *ibs = IPMI_BMC_SIMULATOR(b);
>>> + unsigned int pos;
>>> +
>>> + pos = 0;
>>> + if (sdr_find_entry(&ibs->sdr, recid, &pos, nextrec)) {
>>> + return -1;
>>> + }
>>> +
>>> + *sdr = (const struct ipmi_sdr_compact *) &ibs->sdr.sdr[pos];
>>> + return 0;
>>> +}
>>> +
>>> static void sel_inc_reservation(IPMISel *sel)
>>> {
>>> sel->reservation++;
>>> diff --git a/include/hw/ipmi/ipmi.h b/include/hw/ipmi/ipmi.h
>>> index 91b83b5bb0b6..0d36cfc6b7f3 100644
>>> --- a/include/hw/ipmi/ipmi.h
>>> +++ b/include/hw/ipmi/ipmi.h
>>> @@ -259,4 +259,6 @@ struct ipmi_sdr_compact {
>>>
>>> typedef uint8_t ipmi_sdr_compact_buffer[sizeof(struct ipmi_sdr_compact)];
>>>
>>> +int ipmi_bmc_sdr_find(IPMIBmc *b, uint16_t recid,
>>> + const struct ipmi_sdr_compact **sdr, uint16_t *nextrec);
>>> #endif
>>
>
>
^ permalink raw reply [flat|nested] 66+ messages in thread
* [Qemu-devel] [PATCH 09/21] ipmi: introduce an ipmi_bmc_gen_event() API
2017-04-05 12:41 [Qemu-devel] [PATCH 00/21] pnv: PSI, OCC, IPMI and PCI models Cédric Le Goater
` (7 preceding siblings ...)
2017-04-05 12:41 ` [Qemu-devel] [PATCH 08/21] ipmi: introduce an ipmi_bmc_sdr_find() API Cédric Le Goater
@ 2017-04-05 12:41 ` Cédric Le Goater
2017-04-05 12:41 ` [Qemu-devel] [PATCH 10/21] ipmi: add SET_SENSOR_READING command Cédric Le Goater
` (11 subsequent siblings)
20 siblings, 0 replies; 66+ messages in thread
From: Cédric Le Goater @ 2017-04-05 12:41 UTC (permalink / raw)
To: David Gibson
Cc: qemu-ppc, qemu-devel, Cédric Le Goater, Marcel Apfelbaum,
Michael S. Tsirkin, Corey Minyard
It will be used to fill the message buffer with custom events expected
by some systems. Typically, an Open PowerNV platform guest is notified
with an OEM SEL message before a shutdown or a reboot.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Acked-by: Corey Minyard <cminyard@mvista.com>
---
hw/ipmi/ipmi_bmc_sim.c | 24 ++++++++++++++++++++++++
include/hw/ipmi/ipmi.h | 2 ++
2 files changed, 26 insertions(+)
diff --git a/hw/ipmi/ipmi_bmc_sim.c b/hw/ipmi/ipmi_bmc_sim.c
index 8185a84b76b9..155561d06614 100644
--- a/hw/ipmi/ipmi_bmc_sim.c
+++ b/hw/ipmi/ipmi_bmc_sim.c
@@ -473,6 +473,30 @@ static int attn_irq_enabled(IPMIBmcSim *ibs)
IPMI_BMC_MSG_FLAG_EVT_BUF_FULL_SET(ibs));
}
+void ipmi_bmc_gen_event(IPMIBmc *b, uint8_t *evt, bool log)
+{
+ IPMIBmcSim *ibs = IPMI_BMC_SIMULATOR(b);
+ IPMIInterface *s = ibs->parent.intf;
+ IPMIInterfaceClass *k = IPMI_INTERFACE_GET_CLASS(s);
+
+ if (!IPMI_BMC_EVENT_MSG_BUF_ENABLED(ibs)) {
+ return;
+ }
+
+ if (log && IPMI_BMC_EVENT_LOG_ENABLED(ibs)) {
+ sel_add_event(ibs, evt);
+ }
+
+ if (ibs->msg_flags & IPMI_BMC_MSG_FLAG_EVT_BUF_FULL) {
+ goto out;
+ }
+
+ memcpy(ibs->evtbuf, evt, 16);
+ ibs->msg_flags |= IPMI_BMC_MSG_FLAG_EVT_BUF_FULL;
+ k->set_atn(s, 1, attn_irq_enabled(ibs));
+ out:
+ return;
+}
static void gen_event(IPMIBmcSim *ibs, unsigned int sens_num, uint8_t deassert,
uint8_t evd1, uint8_t evd2, uint8_t evd3)
{
diff --git a/include/hw/ipmi/ipmi.h b/include/hw/ipmi/ipmi.h
index 0d36cfc6b7f3..0affe5a4d864 100644
--- a/include/hw/ipmi/ipmi.h
+++ b/include/hw/ipmi/ipmi.h
@@ -261,4 +261,6 @@ typedef uint8_t ipmi_sdr_compact_buffer[sizeof(struct ipmi_sdr_compact)];
int ipmi_bmc_sdr_find(IPMIBmc *b, uint16_t recid,
const struct ipmi_sdr_compact **sdr, uint16_t *nextrec);
+void ipmi_bmc_gen_event(IPMIBmc *b, uint8_t *evt, bool log);
+
#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 66+ messages in thread* [Qemu-devel] [PATCH 10/21] ipmi: add SET_SENSOR_READING command
2017-04-05 12:41 [Qemu-devel] [PATCH 00/21] pnv: PSI, OCC, IPMI and PCI models Cédric Le Goater
` (8 preceding siblings ...)
2017-04-05 12:41 ` [Qemu-devel] [PATCH 09/21] ipmi: introduce an ipmi_bmc_gen_event() API Cédric Le Goater
@ 2017-04-05 12:41 ` Cédric Le Goater
2017-04-05 14:41 ` Corey Minyard
2017-04-05 12:41 ` [Qemu-devel] [PATCH 11/21] ppc/pnv: scan ISA bus to populate device tree Cédric Le Goater
` (10 subsequent siblings)
20 siblings, 1 reply; 66+ messages in thread
From: Cédric Le Goater @ 2017-04-05 12:41 UTC (permalink / raw)
To: David Gibson
Cc: qemu-ppc, qemu-devel, Cédric Le Goater, Marcel Apfelbaum,
Michael S. Tsirkin, Corey Minyard
SET_SENSOR_READING is a complex IPMI command (IPMI spec : "35.17 Set
Sensor Reading And Event Status Command"). Here is a very minimum
framework fitting the Open PowerNV platform needs. This command is
used on this platform to set the "System Firmware Progress" sensor and
the "Boot Count" sensor.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ipmi/ipmi_bmc_sim.c | 133 +++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 133 insertions(+)
diff --git a/hw/ipmi/ipmi_bmc_sim.c b/hw/ipmi/ipmi_bmc_sim.c
index 155561d06614..26036b20d4df 100644
--- a/hw/ipmi/ipmi_bmc_sim.c
+++ b/hw/ipmi/ipmi_bmc_sim.c
@@ -45,6 +45,7 @@
#define IPMI_CMD_GET_SENSOR_READING 0x2d
#define IPMI_CMD_SET_SENSOR_TYPE 0x2e
#define IPMI_CMD_GET_SENSOR_TYPE 0x2f
+#define IPMI_CMD_SET_SENSOR_READING 0x30
/* #define IPMI_NETFN_APP 0x06 In ipmi.h */
@@ -1739,6 +1740,137 @@ static void get_sensor_type(IPMIBmcSim *ibs,
rsp_buffer_push(rsp, sens->evt_reading_type_code);
}
+static void set_sensor_reading(IPMIBmcSim *ibs,
+ uint8_t *cmd, unsigned int cmd_len,
+ RspBuffer *rsp)
+{
+ IPMISensor *sens;
+ uint8_t evd1;
+ uint8_t evd2;
+ uint8_t evd3;
+
+ if ((cmd[2] > MAX_SENSORS) ||
+ !IPMI_SENSOR_GET_PRESENT(ibs->sensors + cmd[2])) {
+ rsp_buffer_set_error(rsp, IPMI_CC_REQ_ENTRY_NOT_PRESENT);
+ return;
+ }
+
+ sens = ibs->sensors + cmd[2];
+
+ /* Sensor Reading operation */
+ switch ((cmd[3]) & 0x3) {
+ case 0: /* Do not change */
+ break;
+ case 1: /* write given value to sensor reading byte */
+ sens->reading = cmd[4];
+ break;
+ case 2:
+ case 3:
+ rsp_buffer_set_error(rsp, IPMI_CC_INVALID_DATA_FIELD);
+ return;
+ }
+
+ /* Deassertion bits operation */
+ switch ((cmd[3] >> 2) & 0x3) {
+ case 0: /* Do not change */
+ break;
+ case 1: /* write given value */
+ if (cmd_len > 7) {
+ sens->deassert_states = cmd[7];
+ }
+ if (cmd_len > 8) {
+ sens->deassert_states = cmd[8] << 8;
+ }
+
+ case 2: /* mask on */
+ if (cmd_len > 7) {
+ sens->deassert_states |= cmd[7];
+ }
+ if (cmd_len > 8) {
+ sens->deassert_states |= cmd[8] << 8;
+ }
+ break;
+ case 3: /* mask off */
+ if (cmd_len > 7) {
+ sens->deassert_states &= cmd[7];
+ }
+ if (cmd_len > 8) {
+ sens->deassert_states &= (cmd[8] << 8);
+ }
+ break;
+ }
+
+ /* Assertion bits operation */
+ switch ((cmd[3] >> 4) & 0x3) {
+ case 0: /* Do not change */
+ break;
+ case 1: /* write given value */
+ if (cmd_len > 5) {
+ sens->assert_states = cmd[5];
+ }
+ if (cmd_len > 6) {
+ sens->assert_states = cmd[6] << 8;
+ }
+
+ case 2: /* mask on */
+ if (cmd_len > 5) {
+ sens->assert_states |= cmd[5];
+ }
+ if (cmd_len > 6) {
+ sens->assert_states |= cmd[6] << 8;
+ }
+ break;
+ case 3: /* mask off */
+ if (cmd_len > 5) {
+ sens->assert_states &= cmd[5];
+ }
+ if (cmd_len > 6) {
+ sens->assert_states &= (cmd[6] << 8);
+ }
+ break;
+ }
+
+ evd1 = evd2 = evd3 = 0x0;
+ if (cmd_len > 9) {
+ evd1 = cmd[9];
+ }
+ if (cmd_len > 10) {
+ evd2 = cmd[10];
+ }
+ if (cmd_len > 11) {
+ evd3 = cmd[11];
+ }
+
+ /* Event Data Bytes operation */
+ switch ((cmd[3] >> 6) & 0x3) {
+ case 0: /* Do not use the event data in message */
+ evd1 = evd2 = evd3 = 0x0;
+ break;
+ case 1: /* Write given values to event data bytes excluding bits
+ * [3:0] Event Data 1. */
+ evd1 &= 0xf0;
+ break;
+ case 2: /* Write given values to event data bytes including bits
+ * [3:0] Event Data 1. */
+ break;
+ case 3:
+ rsp_buffer_set_error(rsp, IPMI_CC_INVALID_DATA_FIELD);
+ return;
+ }
+
+ if (IPMI_SENSOR_IS_DISCRETE(sens)) {
+ unsigned int bit = evd1 & 0xf;
+ uint16_t mask = (1 << bit);
+
+ if (sens->assert_states & mask & sens->assert_enable) {
+ gen_event(ibs, cmd[2], 0, evd1, evd2, evd3);
+ }
+
+ if (sens->deassert_states & mask & sens->deassert_enable) {
+ gen_event(ibs, cmd[2], 1, evd1, evd2, evd3);
+ }
+ }
+}
static const IPMICmdHandler chassis_cmds[] = {
[IPMI_CMD_GET_CHASSIS_CAPABILITIES] = { chassis_capabilities },
@@ -1759,6 +1891,7 @@ static const IPMICmdHandler sensor_event_cmds[] = {
[IPMI_CMD_GET_SENSOR_READING] = { get_sensor_reading, 3 },
[IPMI_CMD_SET_SENSOR_TYPE] = { set_sensor_type, 5 },
[IPMI_CMD_GET_SENSOR_TYPE] = { get_sensor_type, 3 },
+ [IPMI_CMD_SET_SENSOR_READING] = { set_sensor_reading, 5 },
};
static const IPMINetfn sensor_event_netfn = {
.cmd_nums = ARRAY_SIZE(sensor_event_cmds),
--
2.7.4
^ permalink raw reply related [flat|nested] 66+ messages in thread* Re: [Qemu-devel] [PATCH 10/21] ipmi: add SET_SENSOR_READING command
2017-04-05 12:41 ` [Qemu-devel] [PATCH 10/21] ipmi: add SET_SENSOR_READING command Cédric Le Goater
@ 2017-04-05 14:41 ` Corey Minyard
2017-04-06 7:29 ` Cédric Le Goater
0 siblings, 1 reply; 66+ messages in thread
From: Corey Minyard @ 2017-04-05 14:41 UTC (permalink / raw)
To: Cédric Le Goater, David Gibson
Cc: qemu-ppc, qemu-devel, Marcel Apfelbaum, Michael S. Tsirkin
On 04/05/2017 07:41 AM, Cédric Le Goater wrote:
> SET_SENSOR_READING is a complex IPMI command (IPMI spec : "35.17 Set
> Sensor Reading And Event Status Command"). Here is a very minimum
> framework fitting the Open PowerNV platform needs. This command is
> used on this platform to set the "System Firmware Progress" sensor and
> the "Boot Count" sensor.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> hw/ipmi/ipmi_bmc_sim.c | 133 +++++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 133 insertions(+)
>
> diff --git a/hw/ipmi/ipmi_bmc_sim.c b/hw/ipmi/ipmi_bmc_sim.c
> index 155561d06614..26036b20d4df 100644
> --- a/hw/ipmi/ipmi_bmc_sim.c
> +++ b/hw/ipmi/ipmi_bmc_sim.c
> @@ -45,6 +45,7 @@
> #define IPMI_CMD_GET_SENSOR_READING 0x2d
> #define IPMI_CMD_SET_SENSOR_TYPE 0x2e
> #define IPMI_CMD_GET_SENSOR_TYPE 0x2f
> +#define IPMI_CMD_SET_SENSOR_READING 0x30
>
> /* #define IPMI_NETFN_APP 0x06 In ipmi.h */
>
> @@ -1739,6 +1740,137 @@ static void get_sensor_type(IPMIBmcSim *ibs,
> rsp_buffer_push(rsp, sens->evt_reading_type_code);
> }
>
> +static void set_sensor_reading(IPMIBmcSim *ibs,
> + uint8_t *cmd, unsigned int cmd_len,
> + RspBuffer *rsp)
> +{
> + IPMISensor *sens;
> + uint8_t evd1;
> + uint8_t evd2;
> + uint8_t evd3;
> +
> + if ((cmd[2] > MAX_SENSORS) ||
Should be ">=" here, I believe.
> + !IPMI_SENSOR_GET_PRESENT(ibs->sensors + cmd[2])) {
> + rsp_buffer_set_error(rsp, IPMI_CC_REQ_ENTRY_NOT_PRESENT);
> + return;
> + }
> +
> + sens = ibs->sensors + cmd[2];
> +
> + /* Sensor Reading operation */
> + switch ((cmd[3]) & 0x3) {
> + case 0: /* Do not change */
> + break;
> + case 1: /* write given value to sensor reading byte */
> + sens->reading = cmd[4];
> + break;
> + case 2:
> + case 3:
> + rsp_buffer_set_error(rsp, IPMI_CC_INVALID_DATA_FIELD);
> + return;
> + }
> +
> + /* Deassertion bits operation */
> + switch ((cmd[3] >> 2) & 0x3) {
> + case 0: /* Do not change */
> + break;
> + case 1: /* write given value */
> + if (cmd_len > 7) {
> + sens->deassert_states = cmd[7];
> + }
> + if (cmd_len > 8) {
> + sens->deassert_states = cmd[8] << 8;
> + }
> +
> + case 2: /* mask on */
> + if (cmd_len > 7) {
> + sens->deassert_states |= cmd[7];
> + }
> + if (cmd_len > 8) {
> + sens->deassert_states |= cmd[8] << 8;
> + }
> + break;
> + case 3: /* mask off */
> + if (cmd_len > 7) {
> + sens->deassert_states &= cmd[7];
> + }
> + if (cmd_len > 8) {
> + sens->deassert_states &= (cmd[8] << 8);
> + }
> + break;
> + }
> +
> + /* Assertion bits operation */
> + switch ((cmd[3] >> 4) & 0x3) {
> + case 0: /* Do not change */
> + break;
> + case 1: /* write given value */
> + if (cmd_len > 5) {
> + sens->assert_states = cmd[5];
> + }
> + if (cmd_len > 6) {
> + sens->assert_states = cmd[6] << 8;
> + }
> +
> + case 2: /* mask on */
> + if (cmd_len > 5) {
> + sens->assert_states |= cmd[5];
> + }
> + if (cmd_len > 6) {
> + sens->assert_states |= cmd[6] << 8;
> + }
> + break;
> + case 3: /* mask off */
> + if (cmd_len > 5) {
> + sens->assert_states &= cmd[5];
> + }
> + if (cmd_len > 6) {
> + sens->assert_states &= (cmd[6] << 8);
> + }
> + break;
> + }
> +
> + evd1 = evd2 = evd3 = 0x0;
> + if (cmd_len > 9) {
> + evd1 = cmd[9];
> + }
> + if (cmd_len > 10) {
> + evd2 = cmd[10];
> + }
> + if (cmd_len > 11) {
> + evd3 = cmd[11];
> + }
> +
> + /* Event Data Bytes operation */
> + switch ((cmd[3] >> 6) & 0x3) {
> + case 0: /* Do not use the event data in message */
> + evd1 = evd2 = evd3 = 0x0;
> + break;
> + case 1: /* Write given values to event data bytes excluding bits
> + * [3:0] Event Data 1. */
> + evd1 &= 0xf0;
> + break;
> + case 2: /* Write given values to event data bytes including bits
> + * [3:0] Event Data 1. */
> + break;
> + case 3:
> + rsp_buffer_set_error(rsp, IPMI_CC_INVALID_DATA_FIELD);
> + return;
> + }
I think the above section (from the initialization of evd<n>) should be
moved to
right before the sensor reading handling. Otherwise, on an error you
will set the sensor
reading and assertion bits but will return an error from the command and not
send an event. Actually, it may be better to create local copies of the
reading
and the assertion bits and commit everything together at the end, for
reasons
I will talk about later, and because it's more clear.
There is some vagueness in the spec about how to handle the event data
bytes if
they are not present in the command but the command says to use them. I'm
ok with this implementation, but I'm wondering if returning an error
wouldn't be
better in this particular case.
The spec is also silent about how to handle setting threshold bits if
they are not
present but the value exceeds the thresholds. I'm not sure what to do here.
My gut says that the event should be generated, but that add a lot of
complexity.
We should probably at least add a comment about this if we don't do it,
since
there is no handling of threshold sensors for event generation below.
> +
> + if (IPMI_SENSOR_IS_DISCRETE(sens)) {
> + unsigned int bit = evd1 & 0xf;
> + uint16_t mask = (1 << bit);
> +
> + if (sens->assert_states & mask & sens->assert_enable) {
> + gen_event(ibs, cmd[2], 0, evd1, evd2, evd3);
> + }
> +
> + if (sens->deassert_states & mask & sens->deassert_enable) {
> + gen_event(ibs, cmd[2], 1, evd1, evd2, evd3);
> + }
You should only generate the events if the values change. So you need
to save
the original values so you can compare. Also, if the command requests
that the
BMC generate it's own event, you would need to scan the new values compared
with the old values and send events for each bit that needs it. Again, more
complexity, but we should at least comment that we are not doing something
that may be needed later.
-corey
> + }
> +}
>
> static const IPMICmdHandler chassis_cmds[] = {
> [IPMI_CMD_GET_CHASSIS_CAPABILITIES] = { chassis_capabilities },
> @@ -1759,6 +1891,7 @@ static const IPMICmdHandler sensor_event_cmds[] = {
> [IPMI_CMD_GET_SENSOR_READING] = { get_sensor_reading, 3 },
> [IPMI_CMD_SET_SENSOR_TYPE] = { set_sensor_type, 5 },
> [IPMI_CMD_GET_SENSOR_TYPE] = { get_sensor_type, 3 },
> + [IPMI_CMD_SET_SENSOR_READING] = { set_sensor_reading, 5 },
> };
> static const IPMINetfn sensor_event_netfn = {
> .cmd_nums = ARRAY_SIZE(sensor_event_cmds),
^ permalink raw reply [flat|nested] 66+ messages in thread* Re: [Qemu-devel] [PATCH 10/21] ipmi: add SET_SENSOR_READING command
2017-04-05 14:41 ` Corey Minyard
@ 2017-04-06 7:29 ` Cédric Le Goater
0 siblings, 0 replies; 66+ messages in thread
From: Cédric Le Goater @ 2017-04-06 7:29 UTC (permalink / raw)
To: Corey Minyard, David Gibson
Cc: qemu-ppc, qemu-devel, Marcel Apfelbaum, Michael S. Tsirkin
On 04/05/2017 04:41 PM, Corey Minyard wrote:
> On 04/05/2017 07:41 AM, Cédric Le Goater wrote:
>> SET_SENSOR_READING is a complex IPMI command (IPMI spec : "35.17 Set
>> Sensor Reading And Event Status Command"). Here is a very minimum
>> framework fitting the Open PowerNV platform needs. This command is
>> used on this platform to set the "System Firmware Progress" sensor and
>> the "Boot Count" sensor.
>>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>> ---
>> hw/ipmi/ipmi_bmc_sim.c | 133 +++++++++++++++++++++++++++++++++++++++++++++++++
>> 1 file changed, 133 insertions(+)
>>
>> diff --git a/hw/ipmi/ipmi_bmc_sim.c b/hw/ipmi/ipmi_bmc_sim.c
>> index 155561d06614..26036b20d4df 100644
>> --- a/hw/ipmi/ipmi_bmc_sim.c
>> +++ b/hw/ipmi/ipmi_bmc_sim.c
>> @@ -45,6 +45,7 @@
>> #define IPMI_CMD_GET_SENSOR_READING 0x2d
>> #define IPMI_CMD_SET_SENSOR_TYPE 0x2e
>> #define IPMI_CMD_GET_SENSOR_TYPE 0x2f
>> +#define IPMI_CMD_SET_SENSOR_READING 0x30
>> /* #define IPMI_NETFN_APP 0x06 In ipmi.h */
>> @@ -1739,6 +1740,137 @@ static void get_sensor_type(IPMIBmcSim *ibs,
>> rsp_buffer_push(rsp, sens->evt_reading_type_code);
>> }
>> +static void set_sensor_reading(IPMIBmcSim *ibs,
>> + uint8_t *cmd, unsigned int cmd_len,
>> + RspBuffer *rsp)
>> +{
>> + IPMISensor *sens;
>> + uint8_t evd1;
>> + uint8_t evd2;
>> + uint8_t evd3;
>> +
>> + if ((cmd[2] > MAX_SENSORS) ||
>
> Should be ">=" here, I believe.
>
yes.
>> + !IPMI_SENSOR_GET_PRESENT(ibs->sensors + cmd[2])) {
>> + rsp_buffer_set_error(rsp, IPMI_CC_REQ_ENTRY_NOT_PRESENT);
>> + return;
>> + }
>> +
>> + sens = ibs->sensors + cmd[2];
>> +
>> + /* Sensor Reading operation */
>> + switch ((cmd[3]) & 0x3) {
>> + case 0: /* Do not change */
>> + break;
>> + case 1: /* write given value to sensor reading byte */
>> + sens->reading = cmd[4];
>> + break;
>> + case 2:
>> + case 3:
>> + rsp_buffer_set_error(rsp, IPMI_CC_INVALID_DATA_FIELD);
>> + return;
>> + }
>> +
>> + /* Deassertion bits operation */
>> + switch ((cmd[3] >> 2) & 0x3) {
>> + case 0: /* Do not change */
>> + break;
>> + case 1: /* write given value */
>> + if (cmd_len > 7) {
>> + sens->deassert_states = cmd[7];
>> + }
>> + if (cmd_len > 8) {
>> + sens->deassert_states = cmd[8] << 8;
>> + }
>> +
>> + case 2: /* mask on */
>> + if (cmd_len > 7) {
>> + sens->deassert_states |= cmd[7];
>> + }
>> + if (cmd_len > 8) {
>> + sens->deassert_states |= cmd[8] << 8;
>> + }
>> + break;
>> + case 3: /* mask off */
>> + if (cmd_len > 7) {
>> + sens->deassert_states &= cmd[7];
>> + }
>> + if (cmd_len > 8) {
>> + sens->deassert_states &= (cmd[8] << 8);
>> + }
>> + break;
>> + }
>> +
>> + /* Assertion bits operation */
>> + switch ((cmd[3] >> 4) & 0x3) {
>> + case 0: /* Do not change */
>> + break;
>> + case 1: /* write given value */
>> + if (cmd_len > 5) {
>> + sens->assert_states = cmd[5];
>> + }
>> + if (cmd_len > 6) {
>> + sens->assert_states = cmd[6] << 8;
>> + }
>> +
>> + case 2: /* mask on */
>> + if (cmd_len > 5) {
>> + sens->assert_states |= cmd[5];
>> + }
>> + if (cmd_len > 6) {
>> + sens->assert_states |= cmd[6] << 8;
>> + }
>> + break;
>> + case 3: /* mask off */
>> + if (cmd_len > 5) {
>> + sens->assert_states &= cmd[5];
>> + }
>> + if (cmd_len > 6) {
>> + sens->assert_states &= (cmd[6] << 8);
>> + }
>> + break;
>> + }
>> +
>> + evd1 = evd2 = evd3 = 0x0;
>> + if (cmd_len > 9) {
>> + evd1 = cmd[9];
>> + }
>> + if (cmd_len > 10) {
>> + evd2 = cmd[10];
>> + }
>> + if (cmd_len > 11) {
>> + evd3 = cmd[11];
>> + }
>> +
>> + /* Event Data Bytes operation */
>> + switch ((cmd[3] >> 6) & 0x3) {
>> + case 0: /* Do not use the event data in message */
>> + evd1 = evd2 = evd3 = 0x0;
>> + break;
>> + case 1: /* Write given values to event data bytes excluding bits
>> + * [3:0] Event Data 1. */
>> + evd1 &= 0xf0;
>> + break;
>> + case 2: /* Write given values to event data bytes including bits
>> + * [3:0] Event Data 1. */
>> + break;
>> + case 3:
>> + rsp_buffer_set_error(rsp, IPMI_CC_INVALID_DATA_FIELD);
>> + return;
>> + }
>
> I think the above section (from the initialization of evd<n>) should be moved to
> right before the sensor reading handling. Otherwise, on an error you will set the sensor
> reading and assertion bits but will return an error from the command and not
> send an event. Actually, it may be better to create local copies of the reading
> and the assertion bits and commit everything together at the end, for reasons
> I will talk about later, and because it's more clear.
Yes it seems better.
> There is some vagueness in the spec about how to handle the event data bytes if
> they are not present in the command but the command says to use them. I'm
> ok with this implementation, but I'm wondering if returning an error wouldn't be
> better in this particular case.
I can add that.
> The spec is also silent about how to handle setting threshold bits if they are not
> present but the value exceeds the thresholds. I'm not sure what to do here.
> My gut says that the event should be generated, but that add a lot of complexity.
> We should probably at least add a comment about this if we don't do it, since
> there is no handling of threshold sensors for event generation below.
I will leave that as a TODO for the moment. The command is becoming quite complex.
>> +
>> + if (IPMI_SENSOR_IS_DISCRETE(sens)) {
>> + unsigned int bit = evd1 & 0xf;
>> + uint16_t mask = (1 << bit);
>> +
>> + if (sens->assert_states & mask & sens->assert_enable) {
>> + gen_event(ibs, cmd[2], 0, evd1, evd2, evd3);
>> + }
>> +
>> + if (sens->deassert_states & mask & sens->deassert_enable) {
>> + gen_event(ibs, cmd[2], 1, evd1, evd2, evd3);
>> + }
>
> You should only generate the events if the values change.
hmm, if we do that test, we would not genereate an event if only evd2
changes. This is case with the command sent by the OpenPOWER firmware.
Should we really test for a change of the {de}assert_states fields ?
> So you need to save
> the original values so you can compare. Also, if the command requests that the
> BMC generate it's own event, you would need to scan the new values compared
> with the old values and send events for each bit that needs it.
I will see what I can do. I am not sure which event data I should be
using in that case ...
> Again, more
> complexity, but we should at least comment that we are not doing something
> that may be needed later.
OK. Thanks,
C.
> -corey
>
>> + }
>> +}
>> static const IPMICmdHandler chassis_cmds[] = {
>> [IPMI_CMD_GET_CHASSIS_CAPABILITIES] = { chassis_capabilities },
>> @@ -1759,6 +1891,7 @@ static const IPMICmdHandler sensor_event_cmds[] = {
>> [IPMI_CMD_GET_SENSOR_READING] = { get_sensor_reading, 3 },
>> [IPMI_CMD_SET_SENSOR_TYPE] = { set_sensor_type, 5 },
>> [IPMI_CMD_GET_SENSOR_TYPE] = { get_sensor_type, 3 },
>> + [IPMI_CMD_SET_SENSOR_READING] = { set_sensor_reading, 5 },
>> };
>> static const IPMINetfn sensor_event_netfn = {
>> .cmd_nums = ARRAY_SIZE(sensor_event_cmds),
>
>
^ permalink raw reply [flat|nested] 66+ messages in thread
* [Qemu-devel] [PATCH 11/21] ppc/pnv: scan ISA bus to populate device tree
2017-04-05 12:41 [Qemu-devel] [PATCH 00/21] pnv: PSI, OCC, IPMI and PCI models Cédric Le Goater
` (9 preceding siblings ...)
2017-04-05 12:41 ` [Qemu-devel] [PATCH 10/21] ipmi: add SET_SENSOR_READING command Cédric Le Goater
@ 2017-04-05 12:41 ` Cédric Le Goater
2017-04-10 5:17 ` David Gibson
2017-04-10 13:16 ` [Qemu-devel] [Qemu-ppc] " Greg Kurz
2017-04-05 12:41 ` [Qemu-devel] [PATCH 12/21] ppc/pnv: populate device tree for RTC devices Cédric Le Goater
` (9 subsequent siblings)
20 siblings, 2 replies; 66+ messages in thread
From: Cédric Le Goater @ 2017-04-05 12:41 UTC (permalink / raw)
To: David Gibson; +Cc: qemu-ppc, qemu-devel, Cédric Le Goater
This is an empty shell that we will use to include nodes in the device
tree for ISA devices. We expect RTC, UART and IPMI BT devices.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/pnv.c | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 493c7eed7980..a3c8f6594d10 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -281,6 +281,36 @@ static void powernv_populate_chip(PnvChip *chip, void *fdt)
g_free(typename);
}
+typedef struct ForeachPopulateArgs {
+ void *fdt;
+ int offset;
+} ForeachPopulateArgs;
+
+static int powernv_populate_isa_device(DeviceState *dev, void *opaque)
+{
+ return 0;
+}
+
+static void powernv_populate_isa(ISABus *bus, void *fdt)
+{
+ int lpc_offset;
+ ForeachPopulateArgs args;
+
+ lpc_offset = fdt_node_offset_by_compatible(fdt, -1, "ibm,lpc");
+ if (lpc_offset < 0) {
+ error_report("Could find the lpc node !?");
+ return;
+ }
+
+ args.fdt = fdt;
+ args.offset = lpc_offset;
+
+ /* ISA devices are not necessarily parented to the ISA bus so we
+ * can not use object_child_foreach() */
+ qbus_walk_children(BUS(bus), powernv_populate_isa_device,
+ NULL, NULL, NULL, &args);
+}
+
static void *powernv_create_fdt(MachineState *machine)
{
const char plat_compat[] = "qemu,powernv\0ibm,powernv";
@@ -328,6 +358,8 @@ static void *powernv_create_fdt(MachineState *machine)
for (i = 0; i < pnv->num_chips; i++) {
powernv_populate_chip(pnv->chips[i], fdt);
}
+
+ powernv_populate_isa(pnv->isa_bus, fdt);
return fdt;
}
--
2.7.4
^ permalink raw reply related [flat|nested] 66+ messages in thread* Re: [Qemu-devel] [PATCH 11/21] ppc/pnv: scan ISA bus to populate device tree
2017-04-05 12:41 ` [Qemu-devel] [PATCH 11/21] ppc/pnv: scan ISA bus to populate device tree Cédric Le Goater
@ 2017-04-10 5:17 ` David Gibson
2017-04-10 9:08 ` Cédric Le Goater
2017-04-10 13:16 ` [Qemu-devel] [Qemu-ppc] " Greg Kurz
1 sibling, 1 reply; 66+ messages in thread
From: David Gibson @ 2017-04-10 5:17 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: qemu-ppc, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 2224 bytes --]
On Wed, Apr 05, 2017 at 02:41:36PM +0200, Cédric Le Goater wrote:
> This is an empty shell that we will use to include nodes in the device
> tree for ISA devices. We expect RTC, UART and IPMI BT devices.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
This is so simple, I'd probably fold it into the next patch. But
apart from that.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
> ---
> hw/ppc/pnv.c | 32 ++++++++++++++++++++++++++++++++
> 1 file changed, 32 insertions(+)
>
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index 493c7eed7980..a3c8f6594d10 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -281,6 +281,36 @@ static void powernv_populate_chip(PnvChip *chip, void *fdt)
> g_free(typename);
> }
>
> +typedef struct ForeachPopulateArgs {
> + void *fdt;
> + int offset;
> +} ForeachPopulateArgs;
> +
> +static int powernv_populate_isa_device(DeviceState *dev, void *opaque)
> +{
> + return 0;
> +}
> +
> +static void powernv_populate_isa(ISABus *bus, void *fdt)
> +{
> + int lpc_offset;
> + ForeachPopulateArgs args;
> +
> + lpc_offset = fdt_node_offset_by_compatible(fdt, -1, "ibm,lpc");
> + if (lpc_offset < 0) {
> + error_report("Could find the lpc node !?");
> + return;
> + }
> +
> + args.fdt = fdt;
> + args.offset = lpc_offset;
> +
> + /* ISA devices are not necessarily parented to the ISA bus so we
> + * can not use object_child_foreach() */
> + qbus_walk_children(BUS(bus), powernv_populate_isa_device,
> + NULL, NULL, NULL, &args);
> +}
> +
> static void *powernv_create_fdt(MachineState *machine)
> {
> const char plat_compat[] = "qemu,powernv\0ibm,powernv";
> @@ -328,6 +358,8 @@ static void *powernv_create_fdt(MachineState *machine)
> for (i = 0; i < pnv->num_chips; i++) {
> powernv_populate_chip(pnv->chips[i], fdt);
> }
> +
> + powernv_populate_isa(pnv->isa_bus, fdt);
> return fdt;
> }
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 66+ messages in thread* Re: [Qemu-devel] [PATCH 11/21] ppc/pnv: scan ISA bus to populate device tree
2017-04-10 5:17 ` David Gibson
@ 2017-04-10 9:08 ` Cédric Le Goater
0 siblings, 0 replies; 66+ messages in thread
From: Cédric Le Goater @ 2017-04-10 9:08 UTC (permalink / raw)
To: David Gibson; +Cc: qemu-ppc, qemu-devel
On 04/10/2017 07:17 AM, David Gibson wrote:
> On Wed, Apr 05, 2017 at 02:41:36PM +0200, Cédric Le Goater wrote:
>> This is an empty shell that we will use to include nodes in the device
>> tree for ISA devices. We expect RTC, UART and IPMI BT devices.
>>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>
> This is so simple, I'd probably fold it into the next patch. But
> apart from that.
yes. I agree. The goal was to find an alternative to qbus_walk_children()
which is not a QOM API.
C.
> Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
>
>> ---
>> hw/ppc/pnv.c | 32 ++++++++++++++++++++++++++++++++
>> 1 file changed, 32 insertions(+)
>>
>> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
>> index 493c7eed7980..a3c8f6594d10 100644
>> --- a/hw/ppc/pnv.c
>> +++ b/hw/ppc/pnv.c
>> @@ -281,6 +281,36 @@ static void powernv_populate_chip(PnvChip *chip, void *fdt)
>> g_free(typename);
>> }
>>
>> +typedef struct ForeachPopulateArgs {
>> + void *fdt;
>> + int offset;
>> +} ForeachPopulateArgs;
>> +
>> +static int powernv_populate_isa_device(DeviceState *dev, void *opaque)
>> +{
>> + return 0;
>> +}
>> +
>> +static void powernv_populate_isa(ISABus *bus, void *fdt)
>> +{
>> + int lpc_offset;
>> + ForeachPopulateArgs args;
>> +
>> + lpc_offset = fdt_node_offset_by_compatible(fdt, -1, "ibm,lpc");
>> + if (lpc_offset < 0) {
>> + error_report("Could find the lpc node !?");
>> + return;
>> + }
>> +
>> + args.fdt = fdt;
>> + args.offset = lpc_offset;
>> +
>> + /* ISA devices are not necessarily parented to the ISA bus so we
>> + * can not use object_child_foreach() */
>> + qbus_walk_children(BUS(bus), powernv_populate_isa_device,
>> + NULL, NULL, NULL, &args);
>> +}
>> +
>> static void *powernv_create_fdt(MachineState *machine)
>> {
>> const char plat_compat[] = "qemu,powernv\0ibm,powernv";
>> @@ -328,6 +358,8 @@ static void *powernv_create_fdt(MachineState *machine)
>> for (i = 0; i < pnv->num_chips; i++) {
>> powernv_populate_chip(pnv->chips[i], fdt);
>> }
>> +
>> + powernv_populate_isa(pnv->isa_bus, fdt);
>> return fdt;
>> }
>>
>
^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [Qemu-devel] [Qemu-ppc] [PATCH 11/21] ppc/pnv: scan ISA bus to populate device tree
2017-04-05 12:41 ` [Qemu-devel] [PATCH 11/21] ppc/pnv: scan ISA bus to populate device tree Cédric Le Goater
2017-04-10 5:17 ` David Gibson
@ 2017-04-10 13:16 ` Greg Kurz
2017-04-10 13:21 ` Cédric Le Goater
1 sibling, 1 reply; 66+ messages in thread
From: Greg Kurz @ 2017-04-10 13:16 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: David Gibson, qemu-ppc, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 1930 bytes --]
On Wed, 5 Apr 2017 14:41:36 +0200
Cédric Le Goater <clg@kaod.org> wrote:
> This is an empty shell that we will use to include nodes in the device
> tree for ISA devices. We expect RTC, UART and IPMI BT devices.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> hw/ppc/pnv.c | 32 ++++++++++++++++++++++++++++++++
> 1 file changed, 32 insertions(+)
>
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index 493c7eed7980..a3c8f6594d10 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -281,6 +281,36 @@ static void powernv_populate_chip(PnvChip *chip, void *fdt)
> g_free(typename);
> }
>
> +typedef struct ForeachPopulateArgs {
> + void *fdt;
> + int offset;
> +} ForeachPopulateArgs;
> +
> +static int powernv_populate_isa_device(DeviceState *dev, void *opaque)
> +{
> + return 0;
> +}
> +
> +static void powernv_populate_isa(ISABus *bus, void *fdt)
> +{
> + int lpc_offset;
> + ForeachPopulateArgs args;
> +
> + lpc_offset = fdt_node_offset_by_compatible(fdt, -1, "ibm,lpc");
> + if (lpc_offset < 0) {
> + error_report("Could find the lpc node !?");
s/Could find/Could not find ?
> + return;
> + }
> +
> + args.fdt = fdt;
> + args.offset = lpc_offset;
> +
> + /* ISA devices are not necessarily parented to the ISA bus so we
> + * can not use object_child_foreach() */
> + qbus_walk_children(BUS(bus), powernv_populate_isa_device,
> + NULL, NULL, NULL, &args);
> +}
> +
> static void *powernv_create_fdt(MachineState *machine)
> {
> const char plat_compat[] = "qemu,powernv\0ibm,powernv";
> @@ -328,6 +358,8 @@ static void *powernv_create_fdt(MachineState *machine)
> for (i = 0; i < pnv->num_chips; i++) {
> powernv_populate_chip(pnv->chips[i], fdt);
> }
> +
> + powernv_populate_isa(pnv->isa_bus, fdt);
> return fdt;
> }
>
[-- Attachment #2: OpenPGP digital signature --]
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^ permalink raw reply [flat|nested] 66+ messages in thread* Re: [Qemu-devel] [Qemu-ppc] [PATCH 11/21] ppc/pnv: scan ISA bus to populate device tree
2017-04-10 13:16 ` [Qemu-devel] [Qemu-ppc] " Greg Kurz
@ 2017-04-10 13:21 ` Cédric Le Goater
0 siblings, 0 replies; 66+ messages in thread
From: Cédric Le Goater @ 2017-04-10 13:21 UTC (permalink / raw)
To: Greg Kurz; +Cc: David Gibson, qemu-ppc, qemu-devel
On 04/10/2017 03:16 PM, Greg Kurz wrote:
> On Wed, 5 Apr 2017 14:41:36 +0200
> Cédric Le Goater <clg@kaod.org> wrote:
>
>> This is an empty shell that we will use to include nodes in the device
>> tree for ISA devices. We expect RTC, UART and IPMI BT devices.
>>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>> ---
>> hw/ppc/pnv.c | 32 ++++++++++++++++++++++++++++++++
>> 1 file changed, 32 insertions(+)
>>
>> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
>> index 493c7eed7980..a3c8f6594d10 100644
>> --- a/hw/ppc/pnv.c
>> +++ b/hw/ppc/pnv.c
>> @@ -281,6 +281,36 @@ static void powernv_populate_chip(PnvChip *chip, void *fdt)
>> g_free(typename);
>> }
>>
>> +typedef struct ForeachPopulateArgs {
>> + void *fdt;
>> + int offset;
>> +} ForeachPopulateArgs;
>> +
>> +static int powernv_populate_isa_device(DeviceState *dev, void *opaque)
>> +{
>> + return 0;
>> +}
>> +
>> +static void powernv_populate_isa(ISABus *bus, void *fdt)
>> +{
>> + int lpc_offset;
>> + ForeachPopulateArgs args;
>> +
>> + lpc_offset = fdt_node_offset_by_compatible(fdt, -1, "ibm,lpc");
>> + if (lpc_offset < 0) {
>> + error_report("Could find the lpc node !?");
>
> s/Could find/Could not find ?
yes. I will fix that.
Thanks,
C.
>
>> + return;
>> + }
>> +
>> + args.fdt = fdt;
>> + args.offset = lpc_offset;
>> +
>> + /* ISA devices are not necessarily parented to the ISA bus so we
>> + * can not use object_child_foreach() */
>> + qbus_walk_children(BUS(bus), powernv_populate_isa_device,
>> + NULL, NULL, NULL, &args);
>> +}
>> +
>> static void *powernv_create_fdt(MachineState *machine)
>> {
>> const char plat_compat[] = "qemu,powernv\0ibm,powernv";
>> @@ -328,6 +358,8 @@ static void *powernv_create_fdt(MachineState *machine)
>> for (i = 0; i < pnv->num_chips; i++) {
>> powernv_populate_chip(pnv->chips[i], fdt);
>> }
>> +
>> + powernv_populate_isa(pnv->isa_bus, fdt);
>> return fdt;
>> }
>>
>
^ permalink raw reply [flat|nested] 66+ messages in thread
* [Qemu-devel] [PATCH 12/21] ppc/pnv: populate device tree for RTC devices
2017-04-05 12:41 [Qemu-devel] [PATCH 00/21] pnv: PSI, OCC, IPMI and PCI models Cédric Le Goater
` (10 preceding siblings ...)
2017-04-05 12:41 ` [Qemu-devel] [PATCH 11/21] ppc/pnv: scan ISA bus to populate device tree Cédric Le Goater
@ 2017-04-05 12:41 ` Cédric Le Goater
2017-04-10 5:18 ` David Gibson
2017-04-05 12:41 ` [Qemu-devel] [PATCH 13/21] ppc/pnv: populate device tree for serial devices Cédric Le Goater
` (8 subsequent siblings)
20 siblings, 1 reply; 66+ messages in thread
From: Cédric Le Goater @ 2017-04-05 12:41 UTC (permalink / raw)
To: David Gibson; +Cc: qemu-ppc, qemu-devel, Cédric Le Goater
The code could be common to any ISA device but we are missing the IO
length.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/pnv.c | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index a3c8f6594d10..2f9c41e350d4 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -281,6 +281,26 @@ static void powernv_populate_chip(PnvChip *chip, void *fdt)
g_free(typename);
}
+static void powernv_populate_rtc(ISADevice *d, void *fdt, int lpc_off)
+{
+ uint32_t io_base = d->ioport_id;
+ uint32_t io_regs[] = {
+ cpu_to_be32(1),
+ cpu_to_be32(io_base),
+ cpu_to_be32(2)
+ };
+ char *name;
+ int node;
+
+ name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
+ node = fdt_add_subnode(fdt, lpc_off, name);
+ _FDT(node);
+ g_free(name);
+
+ _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
+ _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00")));
+}
+
typedef struct ForeachPopulateArgs {
void *fdt;
int offset;
@@ -288,6 +308,16 @@ typedef struct ForeachPopulateArgs {
static int powernv_populate_isa_device(DeviceState *dev, void *opaque)
{
+ ForeachPopulateArgs *args = opaque;
+ ISADevice *d = ISA_DEVICE(dev);
+
+ if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) {
+ powernv_populate_rtc(d, args->fdt, args->offset);
+ } else {
+ error_report("unknown isa device %s@i%x", qdev_fw_name(dev),
+ d->ioport_id);
+ }
+
return 0;
}
--
2.7.4
^ permalink raw reply related [flat|nested] 66+ messages in thread* Re: [Qemu-devel] [PATCH 12/21] ppc/pnv: populate device tree for RTC devices
2017-04-05 12:41 ` [Qemu-devel] [PATCH 12/21] ppc/pnv: populate device tree for RTC devices Cédric Le Goater
@ 2017-04-10 5:18 ` David Gibson
0 siblings, 0 replies; 66+ messages in thread
From: David Gibson @ 2017-04-10 5:18 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: qemu-ppc, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 2063 bytes --]
On Wed, Apr 05, 2017 at 02:41:37PM +0200, Cédric Le Goater wrote:
> The code could be common to any ISA device but we are missing the IO
> length.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
> ---
> hw/ppc/pnv.c | 30 ++++++++++++++++++++++++++++++
> 1 file changed, 30 insertions(+)
>
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index a3c8f6594d10..2f9c41e350d4 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -281,6 +281,26 @@ static void powernv_populate_chip(PnvChip *chip, void *fdt)
> g_free(typename);
> }
>
> +static void powernv_populate_rtc(ISADevice *d, void *fdt, int lpc_off)
> +{
> + uint32_t io_base = d->ioport_id;
> + uint32_t io_regs[] = {
> + cpu_to_be32(1),
> + cpu_to_be32(io_base),
> + cpu_to_be32(2)
> + };
> + char *name;
> + int node;
> +
> + name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
> + node = fdt_add_subnode(fdt, lpc_off, name);
> + _FDT(node);
> + g_free(name);
> +
> + _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
> + _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00")));
> +}
> +
> typedef struct ForeachPopulateArgs {
> void *fdt;
> int offset;
> @@ -288,6 +308,16 @@ typedef struct ForeachPopulateArgs {
>
> static int powernv_populate_isa_device(DeviceState *dev, void *opaque)
> {
> + ForeachPopulateArgs *args = opaque;
> + ISADevice *d = ISA_DEVICE(dev);
> +
> + if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) {
> + powernv_populate_rtc(d, args->fdt, args->offset);
> + } else {
> + error_report("unknown isa device %s@i%x", qdev_fw_name(dev),
> + d->ioport_id);
> + }
> +
> return 0;
> }
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 66+ messages in thread
* [Qemu-devel] [PATCH 13/21] ppc/pnv: populate device tree for serial devices
2017-04-05 12:41 [Qemu-devel] [PATCH 00/21] pnv: PSI, OCC, IPMI and PCI models Cédric Le Goater
` (11 preceding siblings ...)
2017-04-05 12:41 ` [Qemu-devel] [PATCH 12/21] ppc/pnv: populate device tree for RTC devices Cédric Le Goater
@ 2017-04-05 12:41 ` Cédric Le Goater
2017-04-10 5:19 ` David Gibson
2017-04-05 12:41 ` [Qemu-devel] [PATCH 14/21] ppc/pnv: populate device tree for IPMI BT devices Cédric Le Goater
` (7 subsequent siblings)
20 siblings, 1 reply; 66+ messages in thread
From: Cédric Le Goater @ 2017-04-05 12:41 UTC (permalink / raw)
To: David Gibson; +Cc: qemu-ppc, qemu-devel, Cédric Le Goater
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/pnv.c | 33 +++++++++++++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 2f9c41e350d4..00e594a0cbe3 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -301,6 +301,37 @@ static void powernv_populate_rtc(ISADevice *d, void *fdt, int lpc_off)
_FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00")));
}
+static void powernv_populate_serial(ISADevice *d, void *fdt, int lpc_off)
+{
+ const char compatible[] = "ns16550\0pnpPNP,501";
+ uint32_t io_base = d->ioport_id;
+ uint32_t io_regs[] = {
+ cpu_to_be32(1),
+ cpu_to_be32(io_base),
+ cpu_to_be32(8)
+ };
+ char *name;
+ int node;
+
+ name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
+ node = fdt_add_subnode(fdt, lpc_off, name);
+ _FDT(node);
+ g_free(name);
+
+ _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
+ _FDT((fdt_setprop(fdt, node, "compatible", compatible,
+ sizeof(compatible))));
+
+ _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200)));
+ _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200)));
+ _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0])));
+ _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
+ fdt_get_phandle(fdt, lpc_off))));
+
+ /* This is needed by Linux */
+ _FDT((fdt_setprop_string(fdt, node, "device_type", "serial")));
+}
+
typedef struct ForeachPopulateArgs {
void *fdt;
int offset;
@@ -313,6 +344,8 @@ static int powernv_populate_isa_device(DeviceState *dev, void *opaque)
if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) {
powernv_populate_rtc(d, args->fdt, args->offset);
+ } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) {
+ powernv_populate_serial(d, args->fdt, args->offset);
} else {
error_report("unknown isa device %s@i%x", qdev_fw_name(dev),
d->ioport_id);
--
2.7.4
^ permalink raw reply related [flat|nested] 66+ messages in thread* Re: [Qemu-devel] [PATCH 13/21] ppc/pnv: populate device tree for serial devices
2017-04-05 12:41 ` [Qemu-devel] [PATCH 13/21] ppc/pnv: populate device tree for serial devices Cédric Le Goater
@ 2017-04-10 5:19 ` David Gibson
0 siblings, 0 replies; 66+ messages in thread
From: David Gibson @ 2017-04-10 5:19 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: qemu-ppc, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 2555 bytes --]
On Wed, Apr 05, 2017 at 02:41:38PM +0200, Cédric Le Goater wrote:
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
> ---
> hw/ppc/pnv.c | 33 +++++++++++++++++++++++++++++++++
> 1 file changed, 33 insertions(+)
>
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index 2f9c41e350d4..00e594a0cbe3 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -301,6 +301,37 @@ static void powernv_populate_rtc(ISADevice *d, void *fdt, int lpc_off)
> _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00")));
> }
>
> +static void powernv_populate_serial(ISADevice *d, void *fdt, int lpc_off)
> +{
> + const char compatible[] = "ns16550\0pnpPNP,501";
> + uint32_t io_base = d->ioport_id;
> + uint32_t io_regs[] = {
> + cpu_to_be32(1),
> + cpu_to_be32(io_base),
> + cpu_to_be32(8)
> + };
> + char *name;
> + int node;
> +
> + name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
> + node = fdt_add_subnode(fdt, lpc_off, name);
> + _FDT(node);
> + g_free(name);
> +
> + _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
> + _FDT((fdt_setprop(fdt, node, "compatible", compatible,
> + sizeof(compatible))));
> +
> + _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200)));
> + _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200)));
> + _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0])));
> + _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
> + fdt_get_phandle(fdt, lpc_off))));
> +
> + /* This is needed by Linux */
> + _FDT((fdt_setprop_string(fdt, node, "device_type", "serial")));
> +}
> +
> typedef struct ForeachPopulateArgs {
> void *fdt;
> int offset;
> @@ -313,6 +344,8 @@ static int powernv_populate_isa_device(DeviceState *dev, void *opaque)
>
> if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) {
> powernv_populate_rtc(d, args->fdt, args->offset);
> + } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) {
> + powernv_populate_serial(d, args->fdt, args->offset);
> } else {
> error_report("unknown isa device %s@i%x", qdev_fw_name(dev),
> d->ioport_id);
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 66+ messages in thread
* [Qemu-devel] [PATCH 14/21] ppc/pnv: populate device tree for IPMI BT devices
2017-04-05 12:41 [Qemu-devel] [PATCH 00/21] pnv: PSI, OCC, IPMI and PCI models Cédric Le Goater
` (12 preceding siblings ...)
2017-04-05 12:41 ` [Qemu-devel] [PATCH 13/21] ppc/pnv: populate device tree for serial devices Cédric Le Goater
@ 2017-04-05 12:41 ` Cédric Le Goater
2017-04-10 5:23 ` David Gibson
2017-04-05 12:41 ` [Qemu-devel] [PATCH 15/21] ppc/pnv: add initial IPMI sensors for the BMC simulator Cédric Le Goater
` (6 subsequent siblings)
20 siblings, 1 reply; 66+ messages in thread
From: Cédric Le Goater @ 2017-04-05 12:41 UTC (permalink / raw)
To: David Gibson; +Cc: qemu-ppc, qemu-devel, Cédric Le Goater
When an ipmi-bt device [1] is defined on the ISA bus, we need to
populate the device tree with the object properties. Such devices are
created with the command line options :
-device ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10
[1] https://lists.gnu.org/archive/html/qemu-devel/2015-11/msg03168.html
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/pnv.c | 35 +++++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 00e594a0cbe3..dfa1cf849b35 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -332,6 +332,39 @@ static void powernv_populate_serial(ISADevice *d, void *fdt, int lpc_off)
_FDT((fdt_setprop_string(fdt, node, "device_type", "serial")));
}
+static void powernv_populate_ipmi_bt(ISADevice *d, void *fdt, int lpc_off)
+{
+ const char compatible[] = "bt\0ipmi-bt";
+ uint32_t io_base = 0x0;
+ uint32_t io_regs[] = {
+ cpu_to_be32(1),
+ cpu_to_be32(io_base),
+ cpu_to_be32(3)
+ };
+ uint32_t irq;
+ char *name;
+ int node;
+
+ io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal);
+ io_regs[1] = cpu_to_be32(io_base);
+
+ irq = object_property_get_int(OBJECT(d), "irq", &error_fatal);
+
+ name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
+ node = fdt_add_subnode(fdt, lpc_off, name);
+ _FDT(node);
+ g_free(name);
+
+ fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs));
+ fdt_setprop(fdt, node, "compatible", compatible, sizeof(compatible));
+
+ /* Mark it as reserved to avoid Linux trying to claim it */
+ _FDT((fdt_setprop_string(fdt, node, "status", "reserved")));
+ _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq)));
+ _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
+ fdt_get_phandle(fdt, lpc_off))));
+}
+
typedef struct ForeachPopulateArgs {
void *fdt;
int offset;
@@ -346,6 +379,8 @@ static int powernv_populate_isa_device(DeviceState *dev, void *opaque)
powernv_populate_rtc(d, args->fdt, args->offset);
} else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) {
powernv_populate_serial(d, args->fdt, args->offset);
+ } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) {
+ powernv_populate_ipmi_bt(d, args->fdt, args->offset);
} else {
error_report("unknown isa device %s@i%x", qdev_fw_name(dev),
d->ioport_id);
--
2.7.4
^ permalink raw reply related [flat|nested] 66+ messages in thread* Re: [Qemu-devel] [PATCH 14/21] ppc/pnv: populate device tree for IPMI BT devices
2017-04-05 12:41 ` [Qemu-devel] [PATCH 14/21] ppc/pnv: populate device tree for IPMI BT devices Cédric Le Goater
@ 2017-04-10 5:23 ` David Gibson
0 siblings, 0 replies; 66+ messages in thread
From: David Gibson @ 2017-04-10 5:23 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: qemu-ppc, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 3130 bytes --]
On Wed, Apr 05, 2017 at 02:41:39PM +0200, Cédric Le Goater wrote:
> When an ipmi-bt device [1] is defined on the ISA bus, we need to
> populate the device tree with the object properties. Such devices are
> created with the command line options :
>
> -device ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10
>
> [1] https://lists.gnu.org/archive/html/qemu-devel/2015-11/msg03168.html
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> hw/ppc/pnv.c | 35 +++++++++++++++++++++++++++++++++++
> 1 file changed, 35 insertions(+)
>
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index 00e594a0cbe3..dfa1cf849b35 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -332,6 +332,39 @@ static void powernv_populate_serial(ISADevice *d, void *fdt, int lpc_off)
> _FDT((fdt_setprop_string(fdt, node, "device_type", "serial")));
> }
>
> +static void powernv_populate_ipmi_bt(ISADevice *d, void *fdt, int lpc_off)
> +{
> + const char compatible[] = "bt\0ipmi-bt";
> + uint32_t io_base = 0x0;
> + uint32_t io_regs[] = {
> + cpu_to_be32(1),
> + cpu_to_be32(io_base),
Best not to include this part of the initializer, since you have to
overwrite it later anyway. Either just use 0 with a /*placeholder */
comment, or use designated array initializers.
> + cpu_to_be32(3)
> + };
> + uint32_t irq;
> + char *name;
> + int node;
> +
> + io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal);
> + io_regs[1] = cpu_to_be32(io_base);
> +
> + irq = object_property_get_int(OBJECT(d), "irq", &error_fatal);
> +
> + name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
> + node = fdt_add_subnode(fdt, lpc_off, name);
> + _FDT(node);
> + g_free(name);
> +
> + fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs));
> + fdt_setprop(fdt, node, "compatible", compatible, sizeof(compatible));
> +
> + /* Mark it as reserved to avoid Linux trying to claim it */
> + _FDT((fdt_setprop_string(fdt, node, "status", "reserved")));
> + _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq)));
> + _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
> + fdt_get_phandle(fdt, lpc_off))));
> +}
> +
> typedef struct ForeachPopulateArgs {
> void *fdt;
> int offset;
> @@ -346,6 +379,8 @@ static int powernv_populate_isa_device(DeviceState *dev, void *opaque)
> powernv_populate_rtc(d, args->fdt, args->offset);
> } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) {
> powernv_populate_serial(d, args->fdt, args->offset);
> + } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) {
> + powernv_populate_ipmi_bt(d, args->fdt, args->offset);
> } else {
> error_report("unknown isa device %s@i%x", qdev_fw_name(dev),
> d->ioport_id);
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 66+ messages in thread
* [Qemu-devel] [PATCH 15/21] ppc/pnv: add initial IPMI sensors for the BMC simulator
2017-04-05 12:41 [Qemu-devel] [PATCH 00/21] pnv: PSI, OCC, IPMI and PCI models Cédric Le Goater
` (13 preceding siblings ...)
2017-04-05 12:41 ` [Qemu-devel] [PATCH 14/21] ppc/pnv: populate device tree for IPMI BT devices Cédric Le Goater
@ 2017-04-05 12:41 ` Cédric Le Goater
2017-04-10 5:31 ` David Gibson
2017-04-05 12:41 ` [Qemu-devel] [PATCH 16/21] ppc/pnv: generate an OEM SEL event on shutdown Cédric Le Goater
` (5 subsequent siblings)
20 siblings, 1 reply; 66+ messages in thread
From: Cédric Le Goater @ 2017-04-05 12:41 UTC (permalink / raw)
To: David Gibson; +Cc: qemu-ppc, qemu-devel, Cédric Le Goater
Skiboot, the firmware for the PowerNV platform, expects the BMC to
provide some specific IPMI sensors. These sensors are exposed in the
device tree and their values are updated by the firmware at boot time.
Sensors of interest are :
"FW Boot Progress"
"Boot Count"
As such a device is defined on the command line, we can only detect
its presence at reset time.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/Makefile.objs | 2 +-
hw/ppc/pnv.c | 17 +++++++++++
hw/ppc/pnv_bmc.c | 81 ++++++++++++++++++++++++++++++++++++++++++++++++++++
include/hw/ppc/pnv.h | 7 +++++
4 files changed, 106 insertions(+), 1 deletion(-)
create mode 100644 hw/ppc/pnv_bmc.c
diff --git a/hw/ppc/Makefile.objs b/hw/ppc/Makefile.objs
index ef67ea820158..7efc68674819 100644
--- a/hw/ppc/Makefile.objs
+++ b/hw/ppc/Makefile.objs
@@ -6,7 +6,7 @@ obj-$(CONFIG_PSERIES) += spapr_hcall.o spapr_iommu.o spapr_rtas.o
obj-$(CONFIG_PSERIES) += spapr_pci.o spapr_rtc.o spapr_drc.o spapr_rng.o
obj-$(CONFIG_PSERIES) += spapr_cpu_core.o spapr_ovec.o
# IBM PowerNV
-obj-$(CONFIG_POWERNV) += pnv.o pnv_xscom.o pnv_core.o pnv_lpc.o pnv_psi.o pnv_occ.o
+obj-$(CONFIG_POWERNV) += pnv.o pnv_xscom.o pnv_core.o pnv_lpc.o pnv_psi.o pnv_occ.o pnv_bmc.o
ifeq ($(CONFIG_PCI)$(CONFIG_PSERIES)$(CONFIG_LINUX), yyy)
obj-y += spapr_pci_vfio.o
endif
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index dfa1cf849b35..c7caecad0aa6 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -35,6 +35,7 @@
#include "qapi/visitor.h"
#include "monitor/monitor.h"
#include "hw/intc/intc.h"
+#include "hw/ipmi/ipmi.h"
#include "hw/ppc/xics.h"
#include "hw/ppc/pnv_xscom.h"
@@ -458,16 +459,32 @@ static void *powernv_create_fdt(MachineState *machine)
}
powernv_populate_isa(pnv->isa_bus, fdt);
+
+ if (pnv->bmc) {
+ pnv_bmc_populate_sensors(pnv->bmc, fdt);
+ }
+
return fdt;
}
static void ppc_powernv_reset(void)
{
MachineState *machine = MACHINE(qdev_get_machine());
+ PnvMachineState *pnv = POWERNV_MACHINE(machine);
void *fdt;
qemu_devices_reset();
+ /* OpenPOWER systems have a BMC, which can be defined on the
+ * command line with:
+ *
+ * -device ipmi-bmc-sim,id=bmc0
+ *
+ * This is the internal simulator but it could also be an external
+ * BMC.
+ */
+ pnv->bmc = object_resolve_path_type("", TYPE_IPMI_BMC, NULL);
+
fdt = powernv_create_fdt(machine);
/* Pack resulting tree */
diff --git a/hw/ppc/pnv_bmc.c b/hw/ppc/pnv_bmc.c
new file mode 100644
index 000000000000..2998530dc4c0
--- /dev/null
+++ b/hw/ppc/pnv_bmc.c
@@ -0,0 +1,81 @@
+/*
+ * QEMU PowerNV, BMC related functions
+ *
+ * Copyright (c) 2016-2017, IBM Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/hw.h"
+#include "sysemu/sysemu.h"
+#include "target/ppc/cpu.h"
+#include "qapi/error.h"
+#include "qemu/log.h"
+#include "hw/ipmi/ipmi.h"
+#include "hw/ppc/fdt.h"
+
+#include "hw/ppc/pnv.h"
+
+#include <libfdt.h>
+
+/* TODO: include definition in ipmi.h */
+#define IPMI_SDR_FULL_TYPE 1
+
+void pnv_bmc_populate_sensors(Object *bmc, void *fdt)
+{
+ int offset;
+ int i;
+ const struct ipmi_sdr_compact *sdr;
+ uint16_t nextrec;
+
+ offset = fdt_add_subnode(fdt, 0, "/bmc");
+ _FDT(offset);
+
+ _FDT((fdt_setprop_string(fdt, offset, "name", "bmc")));
+ _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0x1)));
+ _FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 0x0)));
+
+ offset = fdt_add_subnode(fdt, offset, "sensors");
+ _FDT(offset);
+
+ _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0x1)));
+ _FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 0x0)));
+
+ for (i = 0; !ipmi_bmc_sdr_find(IPMI_BMC(bmc), i, &sdr, &nextrec); i++) {
+ int off;
+ char *name;
+
+ if (sdr->header.rec_type != IPMI_SDR_COMPACT_TYPE ||
+ sdr->header.rec_type != IPMI_SDR_FULL_TYPE) {
+ continue;
+ }
+
+ name = g_strdup_printf("sensor@%x", sdr->sensor_owner_number);
+ off = fdt_add_subnode(fdt, offset, name);
+ _FDT(off);
+ g_free(name);
+
+ _FDT((fdt_setprop_cell(fdt, off, "reg", sdr->sensor_owner_number)));
+ _FDT((fdt_setprop_string(fdt, off, "name", "sensor")));
+ _FDT((fdt_setprop_string(fdt, off, "compatible", "ibm,ipmi-sensor")));
+ _FDT((fdt_setprop_cell(fdt, off, "ipmi-sensor-reading-type",
+ sdr->reading_type)));
+ _FDT((fdt_setprop_cell(fdt, off, "ipmi-entity-id",
+ sdr->entity_id)));
+ _FDT((fdt_setprop_cell(fdt, off, "ipmi-entity-instance",
+ sdr->entity_instance)));
+ _FDT((fdt_setprop_cell(fdt, off, "ipmi-sensor-type",
+ sdr->sensor_type)));
+ }
+}
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index b45a0d91c813..050763f6cf54 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -130,12 +130,19 @@ typedef struct PnvMachineState {
ISABus *isa_bus;
uint32_t cpld_irqstate;
+
+ Object *bmc;
} PnvMachineState;
#define PNV_FDT_ADDR 0x01000000
#define PNV_TIMEBASE_FREQ 512000000ULL
/*
+ * BMC helpers
+ */
+void pnv_bmc_populate_sensors(Object *objbmc, void *fdt);
+
+/*
* POWER8 MMIO base addresses
*/
#define PNV_XSCOM_SIZE 0x800000000ull
--
2.7.4
^ permalink raw reply related [flat|nested] 66+ messages in thread* Re: [Qemu-devel] [PATCH 15/21] ppc/pnv: add initial IPMI sensors for the BMC simulator
2017-04-05 12:41 ` [Qemu-devel] [PATCH 15/21] ppc/pnv: add initial IPMI sensors for the BMC simulator Cédric Le Goater
@ 2017-04-10 5:31 ` David Gibson
2017-04-10 9:25 ` Cédric Le Goater
0 siblings, 1 reply; 66+ messages in thread
From: David Gibson @ 2017-04-10 5:31 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: qemu-ppc, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 7092 bytes --]
On Wed, Apr 05, 2017 at 02:41:40PM +0200, Cédric Le Goater wrote:
> Skiboot, the firmware for the PowerNV platform, expects the BMC to
> provide some specific IPMI sensors. These sensors are exposed in the
> device tree and their values are updated by the firmware at boot time.
>
> Sensors of interest are :
>
> "FW Boot Progress"
> "Boot Count"
>
> As such a device is defined on the command line, we can only detect
> its presence at reset time.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> hw/ppc/Makefile.objs | 2 +-
> hw/ppc/pnv.c | 17 +++++++++++
> hw/ppc/pnv_bmc.c | 81 ++++++++++++++++++++++++++++++++++++++++++++++++++++
> include/hw/ppc/pnv.h | 7 +++++
> 4 files changed, 106 insertions(+), 1 deletion(-)
> create mode 100644 hw/ppc/pnv_bmc.c
>
> diff --git a/hw/ppc/Makefile.objs b/hw/ppc/Makefile.objs
> index ef67ea820158..7efc68674819 100644
> --- a/hw/ppc/Makefile.objs
> +++ b/hw/ppc/Makefile.objs
> @@ -6,7 +6,7 @@ obj-$(CONFIG_PSERIES) += spapr_hcall.o spapr_iommu.o spapr_rtas.o
> obj-$(CONFIG_PSERIES) += spapr_pci.o spapr_rtc.o spapr_drc.o spapr_rng.o
> obj-$(CONFIG_PSERIES) += spapr_cpu_core.o spapr_ovec.o
> # IBM PowerNV
> -obj-$(CONFIG_POWERNV) += pnv.o pnv_xscom.o pnv_core.o pnv_lpc.o pnv_psi.o pnv_occ.o
> +obj-$(CONFIG_POWERNV) += pnv.o pnv_xscom.o pnv_core.o pnv_lpc.o pnv_psi.o pnv_occ.o pnv_bmc.o
> ifeq ($(CONFIG_PCI)$(CONFIG_PSERIES)$(CONFIG_LINUX), yyy)
> obj-y += spapr_pci_vfio.o
> endif
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index dfa1cf849b35..c7caecad0aa6 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -35,6 +35,7 @@
> #include "qapi/visitor.h"
> #include "monitor/monitor.h"
> #include "hw/intc/intc.h"
> +#include "hw/ipmi/ipmi.h"
>
> #include "hw/ppc/xics.h"
> #include "hw/ppc/pnv_xscom.h"
> @@ -458,16 +459,32 @@ static void *powernv_create_fdt(MachineState *machine)
> }
>
> powernv_populate_isa(pnv->isa_bus, fdt);
> +
> + if (pnv->bmc) {
> + pnv_bmc_populate_sensors(pnv->bmc, fdt);
> + }
> +
> return fdt;
> }
>
> static void ppc_powernv_reset(void)
> {
> MachineState *machine = MACHINE(qdev_get_machine());
> + PnvMachineState *pnv = POWERNV_MACHINE(machine);
> void *fdt;
>
> qemu_devices_reset();
>
> + /* OpenPOWER systems have a BMC, which can be defined on the
> + * command line with:
> + *
> + * -device ipmi-bmc-sim,id=bmc0
> + *
> + * This is the internal simulator but it could also be an external
> + * BMC.
> + */
> + pnv->bmc = object_resolve_path_type("", TYPE_IPMI_BMC, NULL);
I'd suggest typing the pointer and doing the cast/test here, rather
than in the functions that need to manipulate it.
> fdt = powernv_create_fdt(machine);
>
> /* Pack resulting tree */
> diff --git a/hw/ppc/pnv_bmc.c b/hw/ppc/pnv_bmc.c
> new file mode 100644
> index 000000000000..2998530dc4c0
> --- /dev/null
> +++ b/hw/ppc/pnv_bmc.c
> @@ -0,0 +1,81 @@
> +/*
> + * QEMU PowerNV, BMC related functions
> + *
> + * Copyright (c) 2016-2017, IBM Corporation.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License, version 2, as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "hw/hw.h"
> +#include "sysemu/sysemu.h"
> +#include "target/ppc/cpu.h"
> +#include "qapi/error.h"
> +#include "qemu/log.h"
> +#include "hw/ipmi/ipmi.h"
> +#include "hw/ppc/fdt.h"
> +
> +#include "hw/ppc/pnv.h"
> +
> +#include <libfdt.h>
> +
> +/* TODO: include definition in ipmi.h */
> +#define IPMI_SDR_FULL_TYPE 1
> +
> +void pnv_bmc_populate_sensors(Object *bmc, void *fdt)
> +{
> + int offset;
> + int i;
> + const struct ipmi_sdr_compact *sdr;
> + uint16_t nextrec;
> +
> + offset = fdt_add_subnode(fdt, 0, "/bmc");
> + _FDT(offset);
> +
> + _FDT((fdt_setprop_string(fdt, offset, "name", "bmc")));
> + _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0x1)));
> + _FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 0x0)));
> +
> + offset = fdt_add_subnode(fdt, offset, "sensors");
> + _FDT(offset);
> +
> + _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0x1)));
> + _FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 0x0)));
> +
> + for (i = 0; !ipmi_bmc_sdr_find(IPMI_BMC(bmc), i, &sdr, &nextrec); i++) {
> + int off;
> + char *name;
> +
> + if (sdr->header.rec_type != IPMI_SDR_COMPACT_TYPE ||
> + sdr->header.rec_type != IPMI_SDR_FULL_TYPE) {
Um.. the condition above is always true. It's only false if rec_type
is equal to both FULL_TYPE and COMPACT_TYPE at the same time...
> + continue;
> + }
> +
> + name = g_strdup_printf("sensor@%x", sdr->sensor_owner_number);
> + off = fdt_add_subnode(fdt, offset, name);
> + _FDT(off);
> + g_free(name);
> +
> + _FDT((fdt_setprop_cell(fdt, off, "reg", sdr->sensor_owner_number)));
> + _FDT((fdt_setprop_string(fdt, off, "name", "sensor")));
> + _FDT((fdt_setprop_string(fdt, off, "compatible", "ibm,ipmi-sensor")));
> + _FDT((fdt_setprop_cell(fdt, off, "ipmi-sensor-reading-type",
> + sdr->reading_type)));
> + _FDT((fdt_setprop_cell(fdt, off, "ipmi-entity-id",
> + sdr->entity_id)));
> + _FDT((fdt_setprop_cell(fdt, off, "ipmi-entity-instance",
> + sdr->entity_instance)));
> + _FDT((fdt_setprop_cell(fdt, off, "ipmi-sensor-type",
> + sdr->sensor_type)));
> + }
> +}
> diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
> index b45a0d91c813..050763f6cf54 100644
> --- a/include/hw/ppc/pnv.h
> +++ b/include/hw/ppc/pnv.h
> @@ -130,12 +130,19 @@ typedef struct PnvMachineState {
>
> ISABus *isa_bus;
> uint32_t cpld_irqstate;
> +
> + Object *bmc;
> } PnvMachineState;
>
> #define PNV_FDT_ADDR 0x01000000
> #define PNV_TIMEBASE_FREQ 512000000ULL
>
> /*
> + * BMC helpers
> + */
> +void pnv_bmc_populate_sensors(Object *objbmc, void *fdt);
> +
> +/*
> * POWER8 MMIO base addresses
> */
> #define PNV_XSCOM_SIZE 0x800000000ull
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 66+ messages in thread* Re: [Qemu-devel] [PATCH 15/21] ppc/pnv: add initial IPMI sensors for the BMC simulator
2017-04-10 5:31 ` David Gibson
@ 2017-04-10 9:25 ` Cédric Le Goater
0 siblings, 0 replies; 66+ messages in thread
From: Cédric Le Goater @ 2017-04-10 9:25 UTC (permalink / raw)
To: David Gibson; +Cc: qemu-ppc, qemu-devel
On 04/10/2017 07:31 AM, David Gibson wrote:
> On Wed, Apr 05, 2017 at 02:41:40PM +0200, Cédric Le Goater wrote:
>> Skiboot, the firmware for the PowerNV platform, expects the BMC to
>> provide some specific IPMI sensors. These sensors are exposed in the
>> device tree and their values are updated by the firmware at boot time.
>>
>> Sensors of interest are :
>>
>> "FW Boot Progress"
>> "Boot Count"
>>
>> As such a device is defined on the command line, we can only detect
>> its presence at reset time.
>>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>> ---
>> hw/ppc/Makefile.objs | 2 +-
>> hw/ppc/pnv.c | 17 +++++++++++
>> hw/ppc/pnv_bmc.c | 81 ++++++++++++++++++++++++++++++++++++++++++++++++++++
>> include/hw/ppc/pnv.h | 7 +++++
>> 4 files changed, 106 insertions(+), 1 deletion(-)
>> create mode 100644 hw/ppc/pnv_bmc.c
>>
>> diff --git a/hw/ppc/Makefile.objs b/hw/ppc/Makefile.objs
>> index ef67ea820158..7efc68674819 100644
>> --- a/hw/ppc/Makefile.objs
>> +++ b/hw/ppc/Makefile.objs
>> @@ -6,7 +6,7 @@ obj-$(CONFIG_PSERIES) += spapr_hcall.o spapr_iommu.o spapr_rtas.o
>> obj-$(CONFIG_PSERIES) += spapr_pci.o spapr_rtc.o spapr_drc.o spapr_rng.o
>> obj-$(CONFIG_PSERIES) += spapr_cpu_core.o spapr_ovec.o
>> # IBM PowerNV
>> -obj-$(CONFIG_POWERNV) += pnv.o pnv_xscom.o pnv_core.o pnv_lpc.o pnv_psi.o pnv_occ.o
>> +obj-$(CONFIG_POWERNV) += pnv.o pnv_xscom.o pnv_core.o pnv_lpc.o pnv_psi.o pnv_occ.o pnv_bmc.o
>> ifeq ($(CONFIG_PCI)$(CONFIG_PSERIES)$(CONFIG_LINUX), yyy)
>> obj-y += spapr_pci_vfio.o
>> endif
>> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
>> index dfa1cf849b35..c7caecad0aa6 100644
>> --- a/hw/ppc/pnv.c
>> +++ b/hw/ppc/pnv.c
>> @@ -35,6 +35,7 @@
>> #include "qapi/visitor.h"
>> #include "monitor/monitor.h"
>> #include "hw/intc/intc.h"
>> +#include "hw/ipmi/ipmi.h"
>>
>> #include "hw/ppc/xics.h"
>> #include "hw/ppc/pnv_xscom.h"
>> @@ -458,16 +459,32 @@ static void *powernv_create_fdt(MachineState *machine)
>> }
>>
>> powernv_populate_isa(pnv->isa_bus, fdt);
>> +
>> + if (pnv->bmc) {
>> + pnv_bmc_populate_sensors(pnv->bmc, fdt);
>> + }
>> +
>> return fdt;
>> }
>>
>> static void ppc_powernv_reset(void)
>> {
>> MachineState *machine = MACHINE(qdev_get_machine());
>> + PnvMachineState *pnv = POWERNV_MACHINE(machine);
>> void *fdt;
>>
>> qemu_devices_reset();
>>
>> + /* OpenPOWER systems have a BMC, which can be defined on the
>> + * command line with:
>> + *
>> + * -device ipmi-bmc-sim,id=bmc0
>> + *
>> + * This is the internal simulator but it could also be an external
>> + * BMC.
>> + */
>> + pnv->bmc = object_resolve_path_type("", TYPE_IPMI_BMC, NULL);
>
> I'd suggest typing the pointer and doing the cast/test here, rather
> than in the functions that need to manipulate it.
OK.
>
>> fdt = powernv_create_fdt(machine);
>>
>> /* Pack resulting tree */
>> diff --git a/hw/ppc/pnv_bmc.c b/hw/ppc/pnv_bmc.c
>> new file mode 100644
>> index 000000000000..2998530dc4c0
>> --- /dev/null
>> +++ b/hw/ppc/pnv_bmc.c
>> @@ -0,0 +1,81 @@
>> +/*
>> + * QEMU PowerNV, BMC related functions
>> + *
>> + * Copyright (c) 2016-2017, IBM Corporation.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License, version 2, as
>> + * published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program; if not, see <http://www.gnu.org/licenses/>.
>> + */
>> +
>> +#include "qemu/osdep.h"
>> +#include "hw/hw.h"
>> +#include "sysemu/sysemu.h"
>> +#include "target/ppc/cpu.h"
>> +#include "qapi/error.h"
>> +#include "qemu/log.h"
>> +#include "hw/ipmi/ipmi.h"
>> +#include "hw/ppc/fdt.h"
>> +
>> +#include "hw/ppc/pnv.h"
>> +
>> +#include <libfdt.h>
>> +
>> +/* TODO: include definition in ipmi.h */
>> +#define IPMI_SDR_FULL_TYPE 1
>> +
>> +void pnv_bmc_populate_sensors(Object *bmc, void *fdt)
>> +{
>> + int offset;
>> + int i;
>> + const struct ipmi_sdr_compact *sdr;
>> + uint16_t nextrec;
>> +
>> + offset = fdt_add_subnode(fdt, 0, "/bmc");
>> + _FDT(offset);
>> +
>> + _FDT((fdt_setprop_string(fdt, offset, "name", "bmc")));
>> + _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0x1)));
>> + _FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 0x0)));
>> +
>> + offset = fdt_add_subnode(fdt, offset, "sensors");
>> + _FDT(offset);
>> +
>> + _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0x1)));
>> + _FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 0x0)));
>> +
>> + for (i = 0; !ipmi_bmc_sdr_find(IPMI_BMC(bmc), i, &sdr, &nextrec); i++) {
>> + int off;
>> + char *name;
>> +
>> + if (sdr->header.rec_type != IPMI_SDR_COMPACT_TYPE ||
>> + sdr->header.rec_type != IPMI_SDR_FULL_TYPE) {
>
> Um.. the condition above is always true. It's only false if rec_type
> is equal to both FULL_TYPE and COMPACT_TYPE at the same time...
yes. that is a last minute bug ... It should be using "&&".
Thanks,
C.
>
>> + continue;
>> + }
>> +
>> + name = g_strdup_printf("sensor@%x", sdr->sensor_owner_number);
>> + off = fdt_add_subnode(fdt, offset, name);
>> + _FDT(off);
>> + g_free(name);
>> +
>> + _FDT((fdt_setprop_cell(fdt, off, "reg", sdr->sensor_owner_number)));
>> + _FDT((fdt_setprop_string(fdt, off, "name", "sensor")));
>> + _FDT((fdt_setprop_string(fdt, off, "compatible", "ibm,ipmi-sensor")));
>> + _FDT((fdt_setprop_cell(fdt, off, "ipmi-sensor-reading-type",
>> + sdr->reading_type)));
>> + _FDT((fdt_setprop_cell(fdt, off, "ipmi-entity-id",
>> + sdr->entity_id)));
>> + _FDT((fdt_setprop_cell(fdt, off, "ipmi-entity-instance",
>> + sdr->entity_instance)));
>> + _FDT((fdt_setprop_cell(fdt, off, "ipmi-sensor-type",
>> + sdr->sensor_type)));
>> + }
>> +}
>> diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
>> index b45a0d91c813..050763f6cf54 100644
>> --- a/include/hw/ppc/pnv.h
>> +++ b/include/hw/ppc/pnv.h
>> @@ -130,12 +130,19 @@ typedef struct PnvMachineState {
>>
>> ISABus *isa_bus;
>> uint32_t cpld_irqstate;
>> +
>> + Object *bmc;
>> } PnvMachineState;
>>
>> #define PNV_FDT_ADDR 0x01000000
>> #define PNV_TIMEBASE_FREQ 512000000ULL
>>
>> /*
>> + * BMC helpers
>> + */
>> +void pnv_bmc_populate_sensors(Object *objbmc, void *fdt);
>> +
>> +/*
>> * POWER8 MMIO base addresses
>> */
>> #define PNV_XSCOM_SIZE 0x800000000ull
>
^ permalink raw reply [flat|nested] 66+ messages in thread
* [Qemu-devel] [PATCH 16/21] ppc/pnv: generate an OEM SEL event on shutdown
2017-04-05 12:41 [Qemu-devel] [PATCH 00/21] pnv: PSI, OCC, IPMI and PCI models Cédric Le Goater
` (14 preceding siblings ...)
2017-04-05 12:41 ` [Qemu-devel] [PATCH 15/21] ppc/pnv: add initial IPMI sensors for the BMC simulator Cédric Le Goater
@ 2017-04-05 12:41 ` Cédric Le Goater
2017-04-10 5:32 ` David Gibson
2017-04-05 12:41 ` [Qemu-devel] [PATCH 17/21] qdev: Add a hook for a bus to device if it can add devices Cédric Le Goater
` (4 subsequent siblings)
20 siblings, 1 reply; 66+ messages in thread
From: Cédric Le Goater @ 2017-04-05 12:41 UTC (permalink / raw)
To: David Gibson; +Cc: qemu-ppc, qemu-devel, Cédric Le Goater
OpenPOWER systems expect to be notified with such an event before a
shutdown or a reboot. An OEM SEL message is sent with specific
identifiers and a user data containing the request : OFF or REBOOT.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/pnv.c | 14 ++++++++++++++
hw/ppc/pnv_bmc.c | 42 ++++++++++++++++++++++++++++++++++++++++++
include/hw/ppc/pnv.h | 3 +++
3 files changed, 59 insertions(+)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index c7caecad0aa6..df0a88c3e252 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -467,6 +467,15 @@ static void *powernv_create_fdt(MachineState *machine)
return fdt;
}
+static void pnv_powerdown_notify(Notifier *n, void *opaque)
+{
+ PnvMachineState *pnv = POWERNV_MACHINE(qdev_get_machine());
+
+ if (pnv->bmc) {
+ pnv_bmc_powerdown(pnv->bmc);
+ }
+}
+
static void ppc_powernv_reset(void)
{
MachineState *machine = MACHINE(qdev_get_machine());
@@ -662,6 +671,11 @@ static void ppc_powernv_init(MachineState *machine)
/* Create an RTC ISA device too */
rtc_init(pnv->isa_bus, 2000, NULL);
+
+ /* OpenPOWER systems use a IPMI SEL Event message to notify the
+ * host to powerdown */
+ pnv->powerdown_notifier.notify = pnv_powerdown_notify;
+ qemu_register_powerdown_notifier(&pnv->powerdown_notifier);
}
/*
diff --git a/hw/ppc/pnv_bmc.c b/hw/ppc/pnv_bmc.c
index 2998530dc4c0..d9ed774acbac 100644
--- a/hw/ppc/pnv_bmc.c
+++ b/hw/ppc/pnv_bmc.c
@@ -32,6 +32,48 @@
/* TODO: include definition in ipmi.h */
#define IPMI_SDR_FULL_TYPE 1
+/*
+ * OEM SEL Event data packet sent by BMC in response of a Read Event
+ * Message Buffer command
+ */
+typedef struct OemSel {
+ /* SEL header */
+ uint8_t id[2];
+ uint8_t type;
+ uint8_t timestamp[4];
+ uint8_t manuf_id[3];
+
+ /* OEM SEL data (6 bytes) follows */
+ uint8_t netfun;
+ uint8_t cmd;
+ uint8_t data[4];
+} OemSel;
+
+#define SOFT_OFF 0x00
+#define SOFT_REBOOT 0x01
+
+static void pnv_gen_oem_sel(Object *obj, uint8_t reboot)
+{
+ /* IPMI SEL Event are 16 bytes long */
+ OemSel sel = {
+ .id = { 0x55 , 0x55 },
+ .type = 0xC0, /* OEM */
+ .manuf_id = { 0x0, 0x0, 0x0 },
+ .timestamp = { 0x0, 0x0, 0x0, 0x0 },
+ .netfun = 0x3A, /* IBM */
+ .cmd = 0x04, /* AMI OEM SEL Power Notification */
+ .data = { reboot, 0xFF, 0xFF, 0xFF },
+ };
+
+ ipmi_bmc_gen_event(IPMI_BMC(obj), (uint8_t *) &sel,
+ 0 /* do not log the event */);
+}
+
+void pnv_bmc_powerdown(Object *obj)
+{
+ pnv_gen_oem_sel(obj, SOFT_OFF);
+}
+
void pnv_bmc_populate_sensors(Object *bmc, void *fdt)
{
int offset;
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 050763f6cf54..b70a13bd4175 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -132,6 +132,8 @@ typedef struct PnvMachineState {
uint32_t cpld_irqstate;
Object *bmc;
+
+ Notifier powerdown_notifier;
} PnvMachineState;
#define PNV_FDT_ADDR 0x01000000
@@ -141,6 +143,7 @@ typedef struct PnvMachineState {
* BMC helpers
*/
void pnv_bmc_populate_sensors(Object *objbmc, void *fdt);
+void pnv_bmc_powerdown(Object *objbmc);
/*
* POWER8 MMIO base addresses
--
2.7.4
^ permalink raw reply related [flat|nested] 66+ messages in thread* Re: [Qemu-devel] [PATCH 16/21] ppc/pnv: generate an OEM SEL event on shutdown
2017-04-05 12:41 ` [Qemu-devel] [PATCH 16/21] ppc/pnv: generate an OEM SEL event on shutdown Cédric Le Goater
@ 2017-04-10 5:32 ` David Gibson
0 siblings, 0 replies; 66+ messages in thread
From: David Gibson @ 2017-04-10 5:32 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: qemu-ppc, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 3971 bytes --]
On Wed, Apr 05, 2017 at 02:41:41PM +0200, Cédric Le Goater wrote:
> OpenPOWER systems expect to be notified with such an event before a
> shutdown or a reboot. An OEM SEL message is sent with specific
> identifiers and a user data containing the request : OFF or REBOOT.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
> ---
> hw/ppc/pnv.c | 14 ++++++++++++++
> hw/ppc/pnv_bmc.c | 42 ++++++++++++++++++++++++++++++++++++++++++
> include/hw/ppc/pnv.h | 3 +++
> 3 files changed, 59 insertions(+)
>
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index c7caecad0aa6..df0a88c3e252 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -467,6 +467,15 @@ static void *powernv_create_fdt(MachineState *machine)
> return fdt;
> }
>
> +static void pnv_powerdown_notify(Notifier *n, void *opaque)
> +{
> + PnvMachineState *pnv = POWERNV_MACHINE(qdev_get_machine());
> +
> + if (pnv->bmc) {
> + pnv_bmc_powerdown(pnv->bmc);
> + }
> +}
> +
> static void ppc_powernv_reset(void)
> {
> MachineState *machine = MACHINE(qdev_get_machine());
> @@ -662,6 +671,11 @@ static void ppc_powernv_init(MachineState *machine)
>
> /* Create an RTC ISA device too */
> rtc_init(pnv->isa_bus, 2000, NULL);
> +
> + /* OpenPOWER systems use a IPMI SEL Event message to notify the
> + * host to powerdown */
> + pnv->powerdown_notifier.notify = pnv_powerdown_notify;
> + qemu_register_powerdown_notifier(&pnv->powerdown_notifier);
> }
>
> /*
> diff --git a/hw/ppc/pnv_bmc.c b/hw/ppc/pnv_bmc.c
> index 2998530dc4c0..d9ed774acbac 100644
> --- a/hw/ppc/pnv_bmc.c
> +++ b/hw/ppc/pnv_bmc.c
> @@ -32,6 +32,48 @@
> /* TODO: include definition in ipmi.h */
> #define IPMI_SDR_FULL_TYPE 1
>
> +/*
> + * OEM SEL Event data packet sent by BMC in response of a Read Event
> + * Message Buffer command
> + */
> +typedef struct OemSel {
> + /* SEL header */
> + uint8_t id[2];
> + uint8_t type;
> + uint8_t timestamp[4];
> + uint8_t manuf_id[3];
> +
> + /* OEM SEL data (6 bytes) follows */
> + uint8_t netfun;
> + uint8_t cmd;
> + uint8_t data[4];
> +} OemSel;
> +
> +#define SOFT_OFF 0x00
> +#define SOFT_REBOOT 0x01
> +
> +static void pnv_gen_oem_sel(Object *obj, uint8_t reboot)
> +{
> + /* IPMI SEL Event are 16 bytes long */
> + OemSel sel = {
> + .id = { 0x55 , 0x55 },
> + .type = 0xC0, /* OEM */
> + .manuf_id = { 0x0, 0x0, 0x0 },
> + .timestamp = { 0x0, 0x0, 0x0, 0x0 },
> + .netfun = 0x3A, /* IBM */
> + .cmd = 0x04, /* AMI OEM SEL Power Notification */
> + .data = { reboot, 0xFF, 0xFF, 0xFF },
> + };
> +
> + ipmi_bmc_gen_event(IPMI_BMC(obj), (uint8_t *) &sel,
> + 0 /* do not log the event */);
> +}
> +
> +void pnv_bmc_powerdown(Object *obj)
> +{
> + pnv_gen_oem_sel(obj, SOFT_OFF);
> +}
> +
> void pnv_bmc_populate_sensors(Object *bmc, void *fdt)
> {
> int offset;
> diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
> index 050763f6cf54..b70a13bd4175 100644
> --- a/include/hw/ppc/pnv.h
> +++ b/include/hw/ppc/pnv.h
> @@ -132,6 +132,8 @@ typedef struct PnvMachineState {
> uint32_t cpld_irqstate;
>
> Object *bmc;
> +
> + Notifier powerdown_notifier;
> } PnvMachineState;
>
> #define PNV_FDT_ADDR 0x01000000
> @@ -141,6 +143,7 @@ typedef struct PnvMachineState {
> * BMC helpers
> */
> void pnv_bmc_populate_sensors(Object *objbmc, void *fdt);
> +void pnv_bmc_powerdown(Object *objbmc);
>
> /*
> * POWER8 MMIO base addresses
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 66+ messages in thread
* [Qemu-devel] [PATCH 17/21] qdev: Add a hook for a bus to device if it can add devices
2017-04-05 12:41 [Qemu-devel] [PATCH 00/21] pnv: PSI, OCC, IPMI and PCI models Cédric Le Goater
` (15 preceding siblings ...)
2017-04-05 12:41 ` [Qemu-devel] [PATCH 16/21] ppc/pnv: generate an OEM SEL event on shutdown Cédric Le Goater
@ 2017-04-05 12:41 ` Cédric Le Goater
2017-04-10 5:36 ` David Gibson
2017-04-05 12:41 ` [Qemu-devel] [PATCH 18/21] pci: Use the new pci_can_add_device() to enforce devfn_min/max Cédric Le Goater
` (3 subsequent siblings)
20 siblings, 1 reply; 66+ messages in thread
From: Cédric Le Goater @ 2017-04-05 12:41 UTC (permalink / raw)
To: David Gibson
Cc: qemu-ppc, qemu-devel, Benjamin Herrenschmidt, Marcel Apfelbaum,
Michael S. Tsirkin, Cédric Le Goater
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This allows a bus class to tell whether a given bus has room for
any new device. max_dev isn't sufficient as the rules can depend
on some arguments or can differ between instances of a bus. This
will be used by PCI in subsequent patches
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
[clg: updated for qemu-2.9 ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/qdev-core.h | 1 +
qdev-monitor.c | 14 +++++++++-----
2 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h
index b44b47676576..867662ba5352 100644
--- a/include/hw/qdev-core.h
+++ b/include/hw/qdev-core.h
@@ -201,6 +201,7 @@ struct BusClass {
*/
char *(*get_fw_dev_path)(DeviceState *dev);
void (*reset)(BusState *bus);
+ bool (*can_add_device)(BusState *bus, QemuOpts *opts);
BusRealize realize;
BusUnrealize unrealize;
diff --git a/qdev-monitor.c b/qdev-monitor.c
index 5f2fcdfc4551..c6eca929c473 100644
--- a/qdev-monitor.c
+++ b/qdev-monitor.c
@@ -415,7 +415,7 @@ static inline bool qbus_is_full(BusState *bus)
* Return the bus if found, else %NULL.
*/
static BusState *qbus_find_recursive(BusState *bus, const char *name,
- const char *bus_typename)
+ const char *bus_typename, QemuOpts *opts)
{
BusChild *kid;
BusState *pick, *child, *ret;
@@ -429,7 +429,10 @@ static BusState *qbus_find_recursive(BusState *bus, const char *name,
}
if (match && !qbus_is_full(bus)) {
- return bus; /* root matches and isn't full */
+ BusClass *bc = BUS_GET_CLASS(bus);
+ if (!bc->can_add_device || bc->can_add_device(bus, opts)) {
+ return bus; /* root matches and isn't full */
+ }
}
pick = match ? bus : NULL;
@@ -437,7 +440,7 @@ static BusState *qbus_find_recursive(BusState *bus, const char *name,
QTAILQ_FOREACH(kid, &bus->children, sibling) {
DeviceState *dev = kid->child;
QLIST_FOREACH(child, &dev->child_bus, sibling) {
- ret = qbus_find_recursive(child, name, bus_typename);
+ ret = qbus_find_recursive(child, name, bus_typename, opts);
if (ret && !qbus_is_full(ret)) {
return ret; /* a descendant matches and isn't full */
}
@@ -467,7 +470,7 @@ static BusState *qbus_find(const char *path, Error **errp)
assert(!path[0]);
elem[0] = len = 0;
}
- bus = qbus_find_recursive(sysbus_get_default(), elem, NULL);
+ bus = qbus_find_recursive(sysbus_get_default(), elem, NULL, NULL);
if (!bus) {
error_setg(errp, "Bus '%s' not found", elem);
return NULL;
@@ -591,7 +594,8 @@ DeviceState *qdev_device_add(QemuOpts *opts, Error **errp)
return NULL;
}
} else if (dc->bus_type != NULL) {
- bus = qbus_find_recursive(sysbus_get_default(), NULL, dc->bus_type);
+ bus = qbus_find_recursive(sysbus_get_default(), NULL, dc->bus_type,
+ opts);
if (!bus || qbus_is_full(bus)) {
error_setg(errp, "No '%s' bus found for device '%s'",
dc->bus_type, driver);
--
2.7.4
^ permalink raw reply related [flat|nested] 66+ messages in thread* Re: [Qemu-devel] [PATCH 17/21] qdev: Add a hook for a bus to device if it can add devices
2017-04-05 12:41 ` [Qemu-devel] [PATCH 17/21] qdev: Add a hook for a bus to device if it can add devices Cédric Le Goater
@ 2017-04-10 5:36 ` David Gibson
0 siblings, 0 replies; 66+ messages in thread
From: David Gibson @ 2017-04-10 5:36 UTC (permalink / raw)
To: Cédric Le Goater
Cc: qemu-ppc, qemu-devel, Benjamin Herrenschmidt, Marcel Apfelbaum,
Michael S. Tsirkin
[-- Attachment #1: Type: text/plain, Size: 4106 bytes --]
On Wed, Apr 05, 2017 at 02:41:42PM +0200, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>
> This allows a bus class to tell whether a given bus has room for
> any new device. max_dev isn't sufficient as the rules can depend
> on some arguments or can differ between instances of a bus. This
> will be used by PCI in subsequent patches
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> [clg: updated for qemu-2.9 ]
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> include/hw/qdev-core.h | 1 +
> qdev-monitor.c | 14 +++++++++-----
> 2 files changed, 10 insertions(+), 5 deletions(-)
>
> diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h
> index b44b47676576..867662ba5352 100644
> --- a/include/hw/qdev-core.h
> +++ b/include/hw/qdev-core.h
> @@ -201,6 +201,7 @@ struct BusClass {
> */
> char *(*get_fw_dev_path)(DeviceState *dev);
> void (*reset)(BusState *bus);
> + bool (*can_add_device)(BusState *bus, QemuOpts *opts);
> BusRealize realize;
> BusUnrealize unrealize;
>
> diff --git a/qdev-monitor.c b/qdev-monitor.c
> index 5f2fcdfc4551..c6eca929c473 100644
> --- a/qdev-monitor.c
> +++ b/qdev-monitor.c
> @@ -415,7 +415,7 @@ static inline bool qbus_is_full(BusState *bus)
> * Return the bus if found, else %NULL.
> */
> static BusState *qbus_find_recursive(BusState *bus, const char *name,
> - const char *bus_typename)
> + const char *bus_typename, QemuOpts *opts)
> {
> BusChild *kid;
> BusState *pick, *child, *ret;
> @@ -429,7 +429,10 @@ static BusState *qbus_find_recursive(BusState *bus, const char *name,
> }
>
> if (match && !qbus_is_full(bus)) {
> - return bus; /* root matches and isn't full */
> + BusClass *bc = BUS_GET_CLASS(bus);
> + if (!bc->can_add_device || bc->can_add_device(bus, opts)) {
> + return bus; /* root matches and isn't full */
Seems like qbus_is_full() should be changed to use the can_add_device
hook, rather than changing the caller here. Essentially the current
max_devs implementation would become the fallback if the bus doesn't
define a bus specific test.
> + }
> }
>
> pick = match ? bus : NULL;
> @@ -437,7 +440,7 @@ static BusState *qbus_find_recursive(BusState *bus, const char *name,
> QTAILQ_FOREACH(kid, &bus->children, sibling) {
> DeviceState *dev = kid->child;
> QLIST_FOREACH(child, &dev->child_bus, sibling) {
> - ret = qbus_find_recursive(child, name, bus_typename);
> + ret = qbus_find_recursive(child, name, bus_typename, opts);
> if (ret && !qbus_is_full(ret)) {
> return ret; /* a descendant matches and isn't full */
> }
> @@ -467,7 +470,7 @@ static BusState *qbus_find(const char *path, Error **errp)
> assert(!path[0]);
> elem[0] = len = 0;
> }
> - bus = qbus_find_recursive(sysbus_get_default(), elem, NULL);
> + bus = qbus_find_recursive(sysbus_get_default(), elem, NULL, NULL);
> if (!bus) {
> error_setg(errp, "Bus '%s' not found", elem);
> return NULL;
> @@ -591,7 +594,8 @@ DeviceState *qdev_device_add(QemuOpts *opts, Error **errp)
> return NULL;
> }
> } else if (dc->bus_type != NULL) {
> - bus = qbus_find_recursive(sysbus_get_default(), NULL, dc->bus_type);
> + bus = qbus_find_recursive(sysbus_get_default(), NULL, dc->bus_type,
> + opts);
> if (!bus || qbus_is_full(bus)) {
> error_setg(errp, "No '%s' bus found for device '%s'",
> dc->bus_type, driver);
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 66+ messages in thread
* [Qemu-devel] [PATCH 18/21] pci: Use the new pci_can_add_device() to enforce devfn_min/max
2017-04-05 12:41 [Qemu-devel] [PATCH 00/21] pnv: PSI, OCC, IPMI and PCI models Cédric Le Goater
` (16 preceding siblings ...)
2017-04-05 12:41 ` [Qemu-devel] [PATCH 17/21] qdev: Add a hook for a bus to device if it can add devices Cédric Le Goater
@ 2017-04-05 12:41 ` Cédric Le Goater
2017-04-10 5:41 ` David Gibson
2017-04-10 19:48 ` Michael S. Tsirkin
2017-04-05 12:41 ` [Qemu-devel] [PATCH 19/21] pci: Don't call pci_irq_handler() for a negative intx Cédric Le Goater
` (2 subsequent siblings)
20 siblings, 2 replies; 66+ messages in thread
From: Cédric Le Goater @ 2017-04-05 12:41 UTC (permalink / raw)
To: David Gibson
Cc: qemu-ppc, qemu-devel, Benjamin Herrenschmidt, Marcel Apfelbaum,
Michael S. Tsirkin, Cédric Le Goater
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This adds a devfn_max field to PCIBus and adds a pci_can_add_device()
function which, if no "addr" (aka devfn) is specified, will tell whether
there is any slot free between devfn_min and devfn_max.
When devfn_max is 0 (default), it will be ignored (no constraints).
This will be used by some PCI root complex implementations that support
only one direct child to avoid having qemu put dumb devices at different
slot numbers.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
[clg: updated for qemu-2.9 ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/pci/pci.c | 22 ++++++++++++++++++++++
include/hw/pci/pci_bus.h | 1 +
2 files changed, 23 insertions(+)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index 259483b1c01a..817ad14ed987 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -143,6 +143,27 @@ static uint16_t pcibus_numa_node(PCIBus *bus)
return NUMA_NODE_UNASSIGNED;
}
+static bool pci_can_add_device(BusState *bus, QemuOpts *opts)
+{
+ unsigned int devfn, max;
+ PCIBus *pbus = PCI_BUS(bus);
+
+ /* If address is specified, say yes and let it fail if that doesn't work */
+ if (qemu_opt_get(opts, "addr") != NULL) {
+ return true;
+ }
+ max = ARRAY_SIZE(pbus->devices);
+ if (pbus->devfn_max && pbus->devfn_max < max) {
+ max = pbus->devfn_max;
+ }
+ for (devfn = pbus->devfn_min ; devfn < max; devfn += PCI_FUNC_MAX) {
+ if (!pbus->devices[devfn]) {
+ break;
+ }
+ }
+ return devfn < max;
+}
+
static void pci_bus_class_init(ObjectClass *klass, void *data)
{
BusClass *k = BUS_CLASS(klass);
@@ -154,6 +175,7 @@ static void pci_bus_class_init(ObjectClass *klass, void *data)
k->realize = pci_bus_realize;
k->unrealize = pci_bus_unrealize;
k->reset = pcibus_reset;
+ k->can_add_device = pci_can_add_device;
pbc->is_root = pcibus_is_root;
pbc->bus_num = pcibus_num;
diff --git a/include/hw/pci/pci_bus.h b/include/hw/pci/pci_bus.h
index 5484a9b5c573..05c9dd22a8fa 100644
--- a/include/hw/pci/pci_bus.h
+++ b/include/hw/pci/pci_bus.h
@@ -23,6 +23,7 @@ struct PCIBus {
PCIIOMMUFunc iommu_fn;
void *iommu_opaque;
uint8_t devfn_min;
+ uint8_t devfn_max;
pci_set_irq_fn set_irq;
pci_map_irq_fn map_irq;
pci_route_irq_fn route_intx_to_irq;
--
2.7.4
^ permalink raw reply related [flat|nested] 66+ messages in thread* Re: [Qemu-devel] [PATCH 18/21] pci: Use the new pci_can_add_device() to enforce devfn_min/max
2017-04-05 12:41 ` [Qemu-devel] [PATCH 18/21] pci: Use the new pci_can_add_device() to enforce devfn_min/max Cédric Le Goater
@ 2017-04-10 5:41 ` David Gibson
2017-04-10 19:48 ` Michael S. Tsirkin
1 sibling, 0 replies; 66+ messages in thread
From: David Gibson @ 2017-04-10 5:41 UTC (permalink / raw)
To: Cédric Le Goater
Cc: qemu-ppc, qemu-devel, Benjamin Herrenschmidt, Marcel Apfelbaum,
Michael S. Tsirkin
[-- Attachment #1: Type: text/plain, Size: 3099 bytes --]
On Wed, Apr 05, 2017 at 02:41:43PM +0200, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>
> This adds a devfn_max field to PCIBus and adds a pci_can_add_device()
> function which, if no "addr" (aka devfn) is specified, will tell whether
> there is any slot free between devfn_min and devfn_max.
>
> When devfn_max is 0 (default), it will be ignored (no constraints).
>
> This will be used by some PCI root complex implementations that support
> only one direct child to avoid having qemu put dumb devices at different
> slot numbers.
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> [clg: updated for qemu-2.9 ]
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> hw/pci/pci.c | 22 ++++++++++++++++++++++
> include/hw/pci/pci_bus.h | 1 +
> 2 files changed, 23 insertions(+)
>
> diff --git a/hw/pci/pci.c b/hw/pci/pci.c
> index 259483b1c01a..817ad14ed987 100644
> --- a/hw/pci/pci.c
> +++ b/hw/pci/pci.c
> @@ -143,6 +143,27 @@ static uint16_t pcibus_numa_node(PCIBus *bus)
> return NUMA_NODE_UNASSIGNED;
> }
>
> +static bool pci_can_add_device(BusState *bus, QemuOpts *opts)
> +{
> + unsigned int devfn, max;
> + PCIBus *pbus = PCI_BUS(bus);
> +
> + /* If address is specified, say yes and let it fail if that doesn't work */
> + if (qemu_opt_get(opts, "addr") != NULL) {
Ah, so these are options for the device to add, not for the bus. I'm
not entirely sure that device options are standardized enough to do
this safely.
Could you use an initialized, but not realized, device pointer instead?
> + return true;
> + }
> + max = ARRAY_SIZE(pbus->devices);
> + if (pbus->devfn_max && pbus->devfn_max < max) {
> + max = pbus->devfn_max;
> + }
> + for (devfn = pbus->devfn_min ; devfn < max; devfn += PCI_FUNC_MAX) {
> + if (!pbus->devices[devfn]) {
> + break;
> + }
> + }
> + return devfn < max;
> +}
> +
> static void pci_bus_class_init(ObjectClass *klass, void *data)
> {
> BusClass *k = BUS_CLASS(klass);
> @@ -154,6 +175,7 @@ static void pci_bus_class_init(ObjectClass *klass, void *data)
> k->realize = pci_bus_realize;
> k->unrealize = pci_bus_unrealize;
> k->reset = pcibus_reset;
> + k->can_add_device = pci_can_add_device;
>
> pbc->is_root = pcibus_is_root;
> pbc->bus_num = pcibus_num;
> diff --git a/include/hw/pci/pci_bus.h b/include/hw/pci/pci_bus.h
> index 5484a9b5c573..05c9dd22a8fa 100644
> --- a/include/hw/pci/pci_bus.h
> +++ b/include/hw/pci/pci_bus.h
> @@ -23,6 +23,7 @@ struct PCIBus {
> PCIIOMMUFunc iommu_fn;
> void *iommu_opaque;
> uint8_t devfn_min;
> + uint8_t devfn_max;
> pci_set_irq_fn set_irq;
> pci_map_irq_fn map_irq;
> pci_route_irq_fn route_intx_to_irq;
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 66+ messages in thread* Re: [Qemu-devel] [PATCH 18/21] pci: Use the new pci_can_add_device() to enforce devfn_min/max
2017-04-05 12:41 ` [Qemu-devel] [PATCH 18/21] pci: Use the new pci_can_add_device() to enforce devfn_min/max Cédric Le Goater
2017-04-10 5:41 ` David Gibson
@ 2017-04-10 19:48 ` Michael S. Tsirkin
1 sibling, 0 replies; 66+ messages in thread
From: Michael S. Tsirkin @ 2017-04-10 19:48 UTC (permalink / raw)
To: Cédric Le Goater
Cc: David Gibson, qemu-devel, qemu-ppc, Marcel Apfelbaum
On Wed, Apr 05, 2017 at 02:41:43PM +0200, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>
> This adds a devfn_max field to PCIBus and adds a pci_can_add_device()
> function which, if no "addr" (aka devfn) is specified, will tell whether
> there is any slot free between devfn_min and devfn_max.
>
> When devfn_max is 0 (default), it will be ignored (no constraints).
>
> This will be used by some PCI root complex implementations that support
> only one direct child to avoid having qemu put dumb devices at different
> slot numbers.
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> [clg: updated for qemu-2.9 ]
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> hw/pci/pci.c | 22 ++++++++++++++++++++++
> include/hw/pci/pci_bus.h | 1 +
> 2 files changed, 23 insertions(+)
>
> diff --git a/hw/pci/pci.c b/hw/pci/pci.c
> index 259483b1c01a..817ad14ed987 100644
> --- a/hw/pci/pci.c
> +++ b/hw/pci/pci.c
> @@ -143,6 +143,27 @@ static uint16_t pcibus_numa_node(PCIBus *bus)
> return NUMA_NODE_UNASSIGNED;
> }
>
> +static bool pci_can_add_device(BusState *bus, QemuOpts *opts)
> +{
> + unsigned int devfn, max;
> + PCIBus *pbus = PCI_BUS(bus);
> +
> + /* If address is specified, say yes and let it fail if that doesn't work */
> + if (qemu_opt_get(opts, "addr") != NULL) {
> + return true;
> + }
> + max = ARRAY_SIZE(pbus->devices);
> + if (pbus->devfn_max && pbus->devfn_max < max) {
> + max = pbus->devfn_max;
> + }
> + for (devfn = pbus->devfn_min ; devfn < max; devfn += PCI_FUNC_MAX) {
> + if (!pbus->devices[devfn]) {
> + break;
> + }
> + }
> + return devfn < max;
> +}
> +
This doesn't do the right thing for AER I think.
> static void pci_bus_class_init(ObjectClass *klass, void *data)
> {
> BusClass *k = BUS_CLASS(klass);
> @@ -154,6 +175,7 @@ static void pci_bus_class_init(ObjectClass *klass, void *data)
> k->realize = pci_bus_realize;
> k->unrealize = pci_bus_unrealize;
> k->reset = pcibus_reset;
> + k->can_add_device = pci_can_add_device;
>
> pbc->is_root = pcibus_is_root;
> pbc->bus_num = pcibus_num;
> diff --git a/include/hw/pci/pci_bus.h b/include/hw/pci/pci_bus.h
> index 5484a9b5c573..05c9dd22a8fa 100644
> --- a/include/hw/pci/pci_bus.h
> +++ b/include/hw/pci/pci_bus.h
> @@ -23,6 +23,7 @@ struct PCIBus {
> PCIIOMMUFunc iommu_fn;
> void *iommu_opaque;
> uint8_t devfn_min;
> + uint8_t devfn_max;
> pci_set_irq_fn set_irq;
> pci_map_irq_fn map_irq;
> pci_route_irq_fn route_intx_to_irq;
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 66+ messages in thread
* [Qemu-devel] [PATCH 19/21] pci: Don't call pci_irq_handler() for a negative intx
2017-04-05 12:41 [Qemu-devel] [PATCH 00/21] pnv: PSI, OCC, IPMI and PCI models Cédric Le Goater
` (17 preceding siblings ...)
2017-04-05 12:41 ` [Qemu-devel] [PATCH 18/21] pci: Use the new pci_can_add_device() to enforce devfn_min/max Cédric Le Goater
@ 2017-04-05 12:41 ` Cédric Le Goater
2017-04-10 5:59 ` David Gibson
2017-04-05 12:41 ` [Qemu-devel] [PATCH 20/21] ppc/pnv: Add model for Power8 PHB3 PCIe Host bridge Cédric Le Goater
2017-04-05 12:41 ` [Qemu-devel] [PATCH 21/21] ppc/pnv: Create a default PCI layout Cédric Le Goater
20 siblings, 1 reply; 66+ messages in thread
From: Cédric Le Goater @ 2017-04-05 12:41 UTC (permalink / raw)
To: David Gibson
Cc: qemu-ppc, qemu-devel, Benjamin Herrenschmidt, Marcel Apfelbaum,
Michael S. Tsirkin, Cédric Le Goater
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Under some circumstances, pci_intx() can return -1 (when the interrupt
pin in the config space is 0 which normally means no interrupt).
I have seen cases of pci_set_irq() being called on such devices, in
turn causing pci_irq_handler() to be called with "-1" as an argument
which doesn't seem like a terribly good idea.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
[clg: updated for qemu-2.9 ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/pci/pci.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index 817ad14ed987..bfd65461348c 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -1419,7 +1419,9 @@ qemu_irq pci_allocate_irq(PCIDevice *pci_dev)
void pci_set_irq(PCIDevice *pci_dev, int level)
{
int intx = pci_intx(pci_dev);
- pci_irq_handler(pci_dev, intx, level);
+ if (intx >= 0) {
+ pci_irq_handler(pci_dev, intx, level);
+ }
}
/* Special hooks used by device assignment */
--
2.7.4
^ permalink raw reply related [flat|nested] 66+ messages in thread* Re: [Qemu-devel] [PATCH 19/21] pci: Don't call pci_irq_handler() for a negative intx
2017-04-05 12:41 ` [Qemu-devel] [PATCH 19/21] pci: Don't call pci_irq_handler() for a negative intx Cédric Le Goater
@ 2017-04-10 5:59 ` David Gibson
2017-04-11 15:41 ` Cédric Le Goater
0 siblings, 1 reply; 66+ messages in thread
From: David Gibson @ 2017-04-10 5:59 UTC (permalink / raw)
To: Cédric Le Goater
Cc: qemu-ppc, qemu-devel, Benjamin Herrenschmidt, Marcel Apfelbaum,
Michael S. Tsirkin
[-- Attachment #1: Type: text/plain, Size: 1560 bytes --]
On Wed, Apr 05, 2017 at 02:41:44PM +0200, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>
> Under some circumstances, pci_intx() can return -1 (when the interrupt
> pin in the config space is 0 which normally means no interrupt).
>
> I have seen cases of pci_set_irq() being called on such devices, in
> turn causing pci_irq_handler() to be called with "-1" as an argument
> which doesn't seem like a terribly good idea.
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> [clg: updated for qemu-2.9 ]
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
This looks like a real bug fix which should go to Michael independent
of the rest of the series.
> ---
> hw/pci/pci.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/hw/pci/pci.c b/hw/pci/pci.c
> index 817ad14ed987..bfd65461348c 100644
> --- a/hw/pci/pci.c
> +++ b/hw/pci/pci.c
> @@ -1419,7 +1419,9 @@ qemu_irq pci_allocate_irq(PCIDevice *pci_dev)
> void pci_set_irq(PCIDevice *pci_dev, int level)
> {
> int intx = pci_intx(pci_dev);
> - pci_irq_handler(pci_dev, intx, level);
> + if (intx >= 0) {
> + pci_irq_handler(pci_dev, intx, level);
> + }
> }
>
> /* Special hooks used by device assignment */
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 66+ messages in thread* Re: [Qemu-devel] [PATCH 19/21] pci: Don't call pci_irq_handler() for a negative intx
2017-04-10 5:59 ` David Gibson
@ 2017-04-11 15:41 ` Cédric Le Goater
0 siblings, 0 replies; 66+ messages in thread
From: Cédric Le Goater @ 2017-04-11 15:41 UTC (permalink / raw)
To: David Gibson
Cc: qemu-ppc, qemu-devel, Benjamin Herrenschmidt, Marcel Apfelbaum,
Michael S. Tsirkin
On 04/10/2017 07:59 AM, David Gibson wrote:
> On Wed, Apr 05, 2017 at 02:41:44PM +0200, Cédric Le Goater wrote:
>> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>>
>> Under some circumstances, pci_intx() can return -1 (when the interrupt
>> pin in the config space is 0 which normally means no interrupt).
>>
>> I have seen cases of pci_set_irq() being called on such devices, in
>> turn causing pci_irq_handler() to be called with "-1" as an argument
>> which doesn't seem like a terribly good idea.
>>
>> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>> [clg: updated for qemu-2.9 ]
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>
> Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
>
> This looks like a real bug fix which should go to Michael independent
> of the rest of the series.
Michael,
Do you want a resend or can you pick it up from this series ?
Thanks,
C.
>
>> ---
>> hw/pci/pci.c | 4 +++-
>> 1 file changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/hw/pci/pci.c b/hw/pci/pci.c
>> index 817ad14ed987..bfd65461348c 100644
>> --- a/hw/pci/pci.c
>> +++ b/hw/pci/pci.c
>> @@ -1419,7 +1419,9 @@ qemu_irq pci_allocate_irq(PCIDevice *pci_dev)
>> void pci_set_irq(PCIDevice *pci_dev, int level)
>> {
>> int intx = pci_intx(pci_dev);
>> - pci_irq_handler(pci_dev, intx, level);
>> + if (intx >= 0) {
>> + pci_irq_handler(pci_dev, intx, level);
>> + }
>> }
>>
>> /* Special hooks used by device assignment */
>
^ permalink raw reply [flat|nested] 66+ messages in thread
* [Qemu-devel] [PATCH 20/21] ppc/pnv: Add model for Power8 PHB3 PCIe Host bridge
2017-04-05 12:41 [Qemu-devel] [PATCH 00/21] pnv: PSI, OCC, IPMI and PCI models Cédric Le Goater
` (18 preceding siblings ...)
2017-04-05 12:41 ` [Qemu-devel] [PATCH 19/21] pci: Don't call pci_irq_handler() for a negative intx Cédric Le Goater
@ 2017-04-05 12:41 ` Cédric Le Goater
2017-04-10 8:14 ` David Gibson
2017-04-05 12:41 ` [Qemu-devel] [PATCH 21/21] ppc/pnv: Create a default PCI layout Cédric Le Goater
20 siblings, 1 reply; 66+ messages in thread
From: Cédric Le Goater @ 2017-04-05 12:41 UTC (permalink / raw)
To: David Gibson
Cc: qemu-ppc, qemu-devel, Benjamin Herrenschmidt, Marcel Apfelbaum,
Michael S. Tsirkin, Cédric Le Goater
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This is a model of the PCIe host bridge found on Power8 chips,
including IOMMU support, PCIe root complex etc...
This implementation doesn't emulate the EEH error handling (and
may never do).
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
[clg: updated for qemu-2.9
QOM'ified the models
introduced pnv_chip_phb_realize() to create the PHB3 objects
updated the XICSFabric handlers to loop on the PHB3 ICS
fixed the XIVE update
fixed IRQ number overlap in pnv_phb3_remap_irqs() ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/intc/xics.c | 2 +-
hw/pci-host/Makefile.objs | 1 +
hw/pci-host/pnv_phb3.c | 1052 +++++++++++++++++++++++++++++++++++
hw/pci-host/pnv_phb3_msi.c | 304 ++++++++++
hw/pci-host/pnv_phb3_pbcq.c | 361 ++++++++++++
hw/pci-host/pnv_phb3_rc.c | 134 +++++
hw/ppc/pnv.c | 76 ++-
hw/ppc/pnv_xscom.c | 5 +-
include/hw/pci-host/pnv_phb3.h | 156 ++++++
include/hw/pci-host/pnv_phb3_regs.h | 506 +++++++++++++++++
include/hw/ppc/pnv.h | 6 +
include/hw/ppc/pnv_xscom.h | 9 +
include/hw/ppc/xics.h | 1 +
13 files changed, 2608 insertions(+), 5 deletions(-)
create mode 100644 hw/pci-host/pnv_phb3.c
create mode 100644 hw/pci-host/pnv_phb3_msi.c
create mode 100644 hw/pci-host/pnv_phb3_pbcq.c
create mode 100644 hw/pci-host/pnv_phb3_rc.c
create mode 100644 include/hw/pci-host/pnv_phb3.h
create mode 100644 include/hw/pci-host/pnv_phb3_regs.h
diff --git a/hw/intc/xics.c b/hw/intc/xics.c
index 292fffecd376..efb65aabdf30 100644
--- a/hw/intc/xics.c
+++ b/hw/intc/xics.c
@@ -263,7 +263,7 @@ void icp_eoi(ICPState *icp, uint32_t xirr)
}
}
-static void icp_irq(ICSState *ics, int server, int nr, uint8_t priority)
+void icp_irq(ICSState *ics, int server, int nr, uint8_t priority)
{
ICPState *icp = xics_icp_get(ics->xics, server);
diff --git a/hw/pci-host/Makefile.objs b/hw/pci-host/Makefile.objs
index 9c7909cf44c6..3167b4430eb9 100644
--- a/hw/pci-host/Makefile.objs
+++ b/hw/pci-host/Makefile.objs
@@ -17,3 +17,4 @@ common-obj-$(CONFIG_PCI_PIIX) += piix.o
common-obj-$(CONFIG_PCI_Q35) += q35.o
common-obj-$(CONFIG_PCI_GENERIC) += gpex.o
common-obj-$(CONFIG_PCI_XILINX) += xilinx-pcie.o
+obj-$(CONFIG_POWERNV) += pnv_phb3.o pnv_phb3_pbcq.o pnv_phb3_rc.o pnv_phb3_msi.o
diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c
new file mode 100644
index 000000000000..4068ae6d8c62
--- /dev/null
+++ b/hw/pci-host/pnv_phb3.c
@@ -0,0 +1,1052 @@
+/*
+ * QEMU PowerPC PowerNV PHB3 model
+ *
+ * Copyright (c) 2014-2017, IBM Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qapi/error.h"
+#include "qemu-common.h"
+#include "hw/pci-host/pnv_phb3.h"
+#include "hw/pci/pci_bridge.h"
+#include "hw/pci/pci_bus.h"
+
+#undef DISPLAY_UNIMPLENTED_REG
+
+static PCIDevice *pnb_phb3_find_cfg_dev(PnvPhb3State *phb)
+{
+ PCIHostState *pci = PCI_HOST_BRIDGE(phb);
+ uint64_t addr = phb->regs[PHB_CONFIG_ADDRESS >> 3];
+ uint8_t bus, devfn;
+
+ if (!(addr >> 63)) {
+ return NULL;
+ }
+ bus = (addr >> 52) & 0xff;
+ devfn = (addr >> 44) & 0xff;
+
+ return pci_find_device(pci->bus, bus, devfn);
+}
+
+static void pnv_phb3_config_write(PnvPhb3State *phb, unsigned off,
+ unsigned size, uint64_t val)
+{
+ uint32_t cfg_addr, limit;
+ PCIDevice *pdev;
+
+ pdev = pnb_phb3_find_cfg_dev(phb);
+ if (!pdev) {
+ return;
+ }
+ cfg_addr = (phb->regs[PHB_CONFIG_ADDRESS >> 3] >> 32) & 0xfff;
+ cfg_addr |= off;
+ limit = pci_config_size(pdev);
+ if (limit <= cfg_addr) {
+ /* conventional pci device can be behind pcie-to-pci bridge.
+ 256 <= addr < 4K has no effects. */
+ return;
+ }
+ switch (size) {
+ case 1:
+ break;
+ case 2:
+ val = bswap16(val);
+ break;
+ case 4:
+ val = bswap32(val);
+ break;
+ default:
+ return;
+ }
+ pci_host_config_write_common(pdev, cfg_addr, limit, val, size);
+}
+
+static uint64_t pnv_phb3_config_read(PnvPhb3State *phb, unsigned off,
+ unsigned size)
+{
+ uint32_t cfg_addr, limit;
+ PCIDevice *pdev;
+ uint64_t val;
+
+ pdev = pnb_phb3_find_cfg_dev(phb);
+ if (!pdev) {
+ return ~0ull;
+ }
+ cfg_addr = (phb->regs[PHB_CONFIG_ADDRESS >> 3] >> 32) & 0xffc;
+ cfg_addr |= off;
+ limit = pci_config_size(pdev);
+ if (limit <= cfg_addr) {
+ /* conventional pci device can be behind pcie-to-pci bridge.
+ 256 <= addr < 4K has no effects. */
+ return ~0ull;
+ }
+ val = pci_host_config_read_common(pdev, cfg_addr, limit, size);
+ switch (size) {
+ case 1:
+ return val;
+ case 2:
+ return bswap16(val);
+ case 4:
+ return bswap32(val);
+ default:
+ return ~0ull;
+ }
+}
+
+static void pnv_phb3_check_m32(PnvPhb3State *phb)
+{
+ uint64_t base, start, size;
+ MemoryRegion *parent;
+
+ if (phb->m32_mapped) {
+ /* Should we destroy it in RCU friendly way... ? */
+ memory_region_del_subregion(phb->mr_m32.container, &phb->mr_m32);
+ phb->m32_mapped = false;
+ }
+
+ /* Disabled ? move on with life ... */
+ if (!(phb->regs[PHB_PHB3_CONFIG >> 3] & PHB_PHB3C_M32_EN)) {
+ return;
+ }
+
+ /* Grab geometry from registers */
+ base = phb->regs[PHB_M32_BASE_ADDR >> 3];
+ start = phb->regs[PHB_M32_START_ADDR >> 3];
+ size = ~(phb->regs[PHB_M32_BASE_MASK >> 3] | 0xfffc000000000000ull) + 1;
+
+ /* Check if it matches an enabled MMIO region in the PBCQ */
+ if (phb->pbcq->mmio0_mapped && base >= phb->pbcq->mmio0_base &&
+ (base + size) <= (phb->pbcq->mmio0_base + phb->pbcq->mmio0_size)) {
+ parent = &phb->pbcq->mmbar0;
+ base -= phb->pbcq->mmio0_base;
+ } else if (phb->pbcq->mmio1_mapped && base >= phb->pbcq->mmio1_base &&
+ (base + size) <= (phb->pbcq->mmio1_base + phb->pbcq->mmio1_size)) {
+ parent = &phb->pbcq->mmbar1;
+ base -= phb->pbcq->mmio1_base;
+ } else {
+ return;
+ }
+
+ /* Create alias */
+ memory_region_init_alias(&phb->mr_m32, OBJECT(phb), "phb3-m32",
+ &phb->pci_mmio, start, size);
+ memory_region_add_subregion(parent, base, &phb->mr_m32);
+ phb->m32_mapped = true;
+}
+
+static void pnv_phb3_check_m64(PnvPhb3State *phb, uint32_t index)
+{
+ uint64_t base, start, size, m64;
+ MemoryRegion *parent;
+
+ if (phb->m64_mapped[index]) {
+ /* Should we destroy it in RCU friendly way... ? */
+ memory_region_del_subregion(phb->mr_m64[index].container,
+ &phb->mr_m64[index]);
+ phb->m64_mapped[index] = false;
+ }
+
+ /* Get table entry */
+ m64 = phb->ioda_M64BT[index];
+
+ /* Disabled ? move on with life ... */
+ if (!(m64 & IODA2_M64BT_ENABLE)) {
+ return;
+ }
+
+ /* Grab geometry from registers */
+ base = GETFIELD(IODA2_M64BT_BASE, m64) << 20;
+ if (m64 & IODA2_M64BT_SINGLE_PE) {
+ base &= ~0x1ffffffull;
+ }
+ size = GETFIELD(IODA2_M64BT_MASK, m64) << 20;
+ size |= 0xfffc000000000000ull;
+ size = ~size + 1;
+ start = base | (phb->regs[PHB_M64_UPPER_BITS >> 3]);
+
+ /* Check if it matches an enabled MMIO region in the PBCQ */
+ if (phb->pbcq->mmio0_mapped && base >= phb->pbcq->mmio0_base &&
+ (base + size) <= (phb->pbcq->mmio0_base + phb->pbcq->mmio0_size)) {
+ parent = &phb->pbcq->mmbar0;
+ base -= phb->pbcq->mmio0_base;
+ } else if (phb->pbcq->mmio1_mapped && base >= phb->pbcq->mmio1_base &&
+ (base + size) <= (phb->pbcq->mmio1_base + phb->pbcq->mmio1_size)) {
+ parent = &phb->pbcq->mmbar1;
+ base -= phb->pbcq->mmio1_base;
+ } else {
+ return;
+ }
+
+ /* Create alias */
+ memory_region_init_alias(&phb->mr_m64[index], OBJECT(phb), "phb3-m64",
+ &phb->pci_mmio, start, size);
+ memory_region_add_subregion(parent, base, &phb->mr_m64[index]);
+ phb->m64_mapped[index] = true;
+}
+
+static void pnv_phb3_check_all_m64s(PnvPhb3State *phb)
+{
+ uint64_t i;
+
+ for (i = 0; i < PNV_PHB3_NUM_M64; i++) {
+ pnv_phb3_check_m64(phb, i);
+ }
+}
+
+static void pnv_phb3_lxivt_write(PnvPhb3State *phb, unsigned idx, uint64_t val)
+{
+ ICSState *ics = phb->lsi_ics;
+ uint8_t server, prio;
+
+ phb->ioda_LXIVT[idx] = val & (IODA2_LXIVT_SERVER_MASK |
+ IODA2_LXIVT_PRIORITY_MASK |
+ IODA2_LXIVT_NODE_ID_MASK);
+ server = GETFIELD(IODA2_LXIVT_SERVER, val);
+ prio = GETFIELD(IODA2_LXIVT_PRIORITY, val);
+
+ /*
+ * The low order 2 bits are the link pointer (Type II interrupts).
+ * Shift back to get a valid IRQ server.
+ */
+ server >>= 2;
+
+ ics_simple_write_xive(ics, idx, server, prio, prio);
+}
+
+static uint64_t *pnv_phb3_ioda_access(PnvPhb3State *phb,
+ unsigned *out_table, unsigned *out_idx)
+{
+ uint64_t adreg = phb->regs[PHB_IODA_ADDR >> 3];
+ unsigned int index = GETFIELD(PHB_IODA_AD_TADR, adreg);
+ unsigned int table = GETFIELD(PHB_IODA_AD_TSEL, adreg);
+ unsigned int mask;
+ uint64_t *tptr = NULL;
+
+ switch (table) {
+ case IODA2_TBL_LIST:
+ tptr = phb->ioda_LIST;
+ mask = 7;
+ break;
+ case IODA2_TBL_LXIVT:
+ tptr = phb->ioda_LXIVT;
+ mask = 7;
+ break;
+ case IODA2_TBL_IVC_CAM:
+ case IODA2_TBL_RBA:
+ mask = 31;
+ break;
+ case IODA2_TBL_RCAM:
+ mask = 63;
+ break;
+ case IODA2_TBL_MRT:
+ mask = 7;
+ break;
+ case IODA2_TBL_PESTA:
+ case IODA2_TBL_PESTB:
+ mask = 255;
+ break;
+ case IODA2_TBL_TVT:
+ tptr = phb->ioda_TVT;
+ mask = 511;
+ break;
+ case IODA2_TBL_TCAM:
+ case IODA2_TBL_TDR:
+ mask = 63;
+ break;
+ case IODA2_TBL_M64BT:
+ tptr = phb->ioda_M64BT;
+ mask = 15;
+ break;
+ case IODA2_TBL_M32DT:
+ tptr = phb->ioda_MDT;
+ mask = 255;
+ break;
+ case IODA2_TBL_PEEV:
+ tptr = phb->ioda_PEEV;
+ mask = 3;
+ break;
+ default:
+ return NULL;
+ }
+ index &= mask;
+ if (out_idx) {
+ *out_idx = index;
+ }
+ if (out_table) {
+ *out_table = table;
+ }
+ if (adreg & PHB_IODA_AD_AUTOINC) {
+ index = (index + 1) & mask;
+ adreg = SETFIELD(PHB_IODA_AD_TADR, adreg, index);
+ }
+ if (tptr) {
+ tptr += index;
+ }
+ phb->regs[PHB_IODA_ADDR >> 3] = adreg;
+ return tptr;
+}
+
+static uint64_t pnv_phb3_ioda_read(PnvPhb3State *phb)
+{
+ unsigned table;
+ uint64_t *tptr;
+
+ tptr = pnv_phb3_ioda_access(phb, &table, NULL);
+ if (!tptr) {
+ /* Return 0 on unsupported tables, not ff's */
+ return 0;
+ }
+ return *tptr;
+}
+
+static void pnv_phb3_ioda_write(PnvPhb3State *phb, uint64_t val)
+{
+ unsigned table, idx;
+ uint64_t *tptr;
+
+ tptr = pnv_phb3_ioda_access(phb, &table, &idx);
+ if (!tptr) {
+ return;
+ }
+
+ /* Handle side effects */
+ switch (table) {
+ case IODA2_TBL_LXIVT:
+ pnv_phb3_lxivt_write(phb, idx, val);
+ break;
+ case IODA2_TBL_M64BT:
+ *tptr = val;
+ pnv_phb3_check_m64(phb, idx);
+ break;
+ default:
+ *tptr = val;
+ }
+}
+
+/* This is called whenever the PHB LSI, MSI source ID register or
+ * the PBCQ irq filters are written.
+ */
+void pnv_phb3_remap_irqs(PnvPhb3State *phb)
+{
+ ICSState *ics = phb->lsi_ics;
+ uint32_t local, global, count, mask, comp;
+ uint64_t baren;
+
+ /* First check if we are enabled. Unlike real HW we don't separate TX and RX
+ * so we enable if both are set
+ */
+ baren = phb->pbcq->nest_regs[PBCQ_NEST_BAR_EN];
+ if (!(baren & PBCQ_NEST_BAR_EN_IRSN_RX) ||
+ !(baren & PBCQ_NEST_BAR_EN_IRSN_TX)) {
+ ics->offset = 0;
+ return;
+ }
+
+ /* Grab local LSI source ID */
+ local = GETFIELD(PHB_LSI_SRC_ID, phb->regs[PHB_LSI_SOURCE_ID >> 3]) << 3;
+
+ /* Grab global one and compare */
+ global = GETFIELD(PBCQ_NEST_LSI_SRC,
+ phb->pbcq->nest_regs[PBCQ_NEST_LSI_SRC_ID]) << 3;
+ if (global != local) {
+ /* This happens during initialization, let's come back when we
+ * are properly configured
+ */
+ ics->offset = 0;
+ return;
+ }
+
+ /* Get the base on the powerbus */
+ comp = GETFIELD(PBCQ_NEST_IRSN_COMP,
+ phb->pbcq->nest_regs[PBCQ_NEST_IRSN_COMPARE]);
+ mask = GETFIELD(PBCQ_NEST_IRSN_COMP,
+ phb->pbcq->nest_regs[PBCQ_NEST_IRSN_MASK]);
+ count = ((~mask) + 1) & 0x7ffff;
+ phb->total_irq = count;
+
+ /* Sanity checks */
+ if ((global + PNV_PHB3_NUM_LSI) > count) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "LSIs out of reach: LSI base=%d total irq=%d",
+ global, count);
+ }
+
+ if (count > 2048) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "More interrupts than supported: %d", count);
+ }
+
+ if ((comp & mask) != comp) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "IRQ compare bits not in mask: comp=0x%x mask=0x%x",
+ comp, mask);
+ comp &= mask;
+ }
+ /* Setup LSI offset */
+ ics->offset = comp + global;
+
+ /* Setup MSI offset */
+ pnv_phb3_msi_update_config(phb->msis, comp, count - PNV_PHB3_NUM_LSI);
+}
+
+static void pnv_phb3_lsi_src_id_write(PnvPhb3State *phb, uint64_t val)
+{
+ /* Sanitize content */
+ val &= PHB_LSI_SRC_ID_MASK;
+ phb->regs[PHB_LSI_SOURCE_ID >> 3] = val;
+ pnv_phb3_remap_irqs(phb);
+}
+
+static void pnv_phb3_rtc_invalidate(PnvPhb3State *phb, uint64_t val)
+{
+ PnvPhb3DMASpace *ds;
+
+ /* Always invalidate all for now ... */
+ QLIST_FOREACH(ds, &phb->dma_spaces, list) {
+ ds->pe_num = PHB_INVALID_PE;
+ }
+}
+
+
+static void pnv_phb3_update_msi_regions(PnvPhb3DMASpace *ds)
+{
+ uint64_t cfg = ds->phb->regs[PHB_PHB3_CONFIG >> 3];
+
+ if (cfg & PHB_PHB3C_32BIT_MSI_EN) {
+ if (!ds->msi32_mapped) {
+ memory_region_add_subregion(&ds->dma_mr, 0xffff0000, &ds->msi32_mr);
+ ds->msi32_mapped = true;
+ }
+ } else {
+ if (ds->msi32_mapped) {
+ memory_region_del_subregion(&ds->dma_mr, &ds->msi32_mr);
+ ds->msi32_mapped = false;
+ }
+ }
+
+ if (cfg & PHB_PHB3C_64BIT_MSI_EN) {
+ if (!ds->msi64_mapped) {
+ memory_region_add_subregion(&ds->dma_mr,
+ (1ull << 60), &ds->msi64_mr);
+ ds->msi64_mapped = true;
+ }
+ } else {
+ if (ds->msi64_mapped) {
+ memory_region_del_subregion(&ds->dma_mr, &ds->msi64_mr);
+ ds->msi64_mapped = false;
+ }
+ }
+}
+
+static void pnv_phb3_update_all_msi_regions(PnvPhb3State *phb)
+{
+ PnvPhb3DMASpace *ds;
+
+ QLIST_FOREACH(ds, &phb->dma_spaces, list) {
+ pnv_phb3_update_msi_regions(ds);
+ }
+}
+
+void pnv_phb3_reg_write(void *opaque, hwaddr off, uint64_t val, unsigned size)
+{
+ PnvPhb3State *phb = opaque;
+ bool changed;
+
+ /* Special case configuration data */
+ if ((off & 0xfffc) == PHB_CONFIG_DATA) {
+ pnv_phb3_config_write(phb, off & 0x3, size, val);
+ return;
+ }
+
+ /* Other registers are 64-bit only */
+ if (size != 8 || off & 0x7) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "Invalid register access, offset: 0x%"PRIx64" size: %d",
+ off, size);
+ return;
+ }
+
+ /* Handle masking */
+ switch (off) {
+ case PHB_M64_UPPER_BITS:
+ val &= 0xfffc000000000000ull;
+ break;
+ }
+
+ /* Record whether it changed */
+ changed = phb->regs[off >> 3] != val;
+
+ /* Store in register cache first */
+ phb->regs[off >> 3] = val;
+
+ /* Handle side effects */
+ switch (off) {
+ case PHB_PHB3_CONFIG:
+ if (changed) {
+ pnv_phb3_update_all_msi_regions(phb);
+ }
+ /* fall through */
+ case PHB_M32_BASE_ADDR:
+ case PHB_M32_BASE_MASK:
+ case PHB_M32_START_ADDR:
+ if (changed) {
+ pnv_phb3_check_m32(phb);
+ }
+ break;
+ case PHB_M64_UPPER_BITS:
+ if (changed) {
+ pnv_phb3_check_all_m64s(phb);
+ }
+ break;
+ case PHB_LSI_SOURCE_ID:
+ if (changed) {
+ pnv_phb3_lsi_src_id_write(phb, val);
+ }
+ break;
+
+ /* IODA table accesses */
+ case PHB_IODA_DATA0:
+ pnv_phb3_ioda_write(phb, val);
+ break;
+
+ /* RTC invalidation */
+ case PHB_RTC_INVALIDATE:
+ pnv_phb3_rtc_invalidate(phb, val);
+ break;
+
+ /* FFI request */
+ case PHB_FFI_REQUEST:
+ pnv_phb3_msi_ffi(phb->msis, val);
+ break;
+
+ /* Silent simple writes */
+ case PHB_CONFIG_ADDRESS:
+ case PHB_IODA_ADDR:
+ case PHB_TCE_KILL:
+ case PHB_TCE_SPEC_CTL:
+ case PHB_PEST_BAR:
+ case PHB_PELTV_BAR:
+ case PHB_RTT_BAR:
+ case PHB_RBA_BAR:
+ case PHB_IVT_BAR:
+ case PHB_FFI_LOCK:
+ break;
+
+#ifdef DISPLAY_UNIMPLENTED_REG
+ /* Noise on anything else */
+ default:
+ qemu_log_mask(LOG_UNIMP, "reg_write 0x%"PRIx64"=%"PRIx64, off, val);
+#endif
+ }
+}
+
+uint64_t pnv_phb3_reg_read(void *opaque, hwaddr off, unsigned size)
+{
+ PnvPhb3State *phb = opaque;
+ uint64_t val;
+
+ if ((off & 0xfffc) == PHB_CONFIG_DATA) {
+ return pnv_phb3_config_read(phb, off & 0x3, size);
+ }
+
+ /* Other registers are 64-bit only */
+ if (size != 8 || off & 0x7) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "Invalid register access, offset: 0x%"PRIx64" size: %d",
+ off, size);
+ return ~0ull;
+ }
+
+ /* Default read from cache */
+ val = phb->regs[off >> 3];
+
+ switch (off) {
+ /* Simulate venice DD2.0 */
+ case PHB_VERSION:
+ return 0x000000a300000005ull;
+
+ /* IODA table accesses */
+ case PHB_IODA_DATA0:
+ return pnv_phb3_ioda_read(phb);
+
+ /* Link training always appears trained */
+ case PHB_PCIE_DLP_TRAIN_CTL:
+ return PHB_PCIE_DLP_INBAND_PRESENCE | PHB_PCIE_DLP_TC_DL_LINKACT;
+
+ /* FFI Lock */
+ case PHB_FFI_LOCK:
+ /* Set lock and return previous value */
+ phb->regs[off >> 3] |= PHB_FFI_LOCK_STATE;
+ return val;
+
+ /* Silent simple reads */
+ case PHB_PHB3_CONFIG:
+ case PHB_M32_BASE_ADDR:
+ case PHB_M32_BASE_MASK:
+ case PHB_M32_START_ADDR:
+ case PHB_CONFIG_ADDRESS:
+ case PHB_IODA_ADDR:
+ case PHB_RTC_INVALIDATE:
+ case PHB_TCE_KILL:
+ case PHB_TCE_SPEC_CTL:
+ case PHB_PEST_BAR:
+ case PHB_PELTV_BAR:
+ case PHB_RTT_BAR:
+ case PHB_RBA_BAR:
+ case PHB_IVT_BAR:
+ case PHB_M64_UPPER_BITS:
+ break;
+
+#ifdef DISPLAY_UNIMPLENTED_REG
+ /* Noise on anything else */
+ default:
+ qemu_log_mask(LOG_UNIMP, "reg_read 0x%"PRIx64"=%"PRIx64, off, val);
+#endif
+ }
+ return val;
+}
+
+static const MemoryRegionOps pnv_phb3_reg_ops = {
+ .read = pnv_phb3_reg_read,
+ .write = pnv_phb3_reg_write,
+ .valid.min_access_size = 1,
+ .valid.max_access_size = 8,
+ .impl.min_access_size = 1,
+ .impl.max_access_size = 8,
+ .endianness = DEVICE_BIG_ENDIAN,
+};
+
+static int pnv_phb3_map_irq(PCIDevice *pci_dev, int irq_num)
+{
+ /* Check that out properly ... */
+ return irq_num & 3;
+}
+
+static void pnv_phb3_set_irq(void *opaque, int irq_num, int level)
+{
+ PnvPhb3State *phb = opaque;
+
+ /* LSI only ... */
+ if (irq_num > 3) {
+ qemu_log_mask(LOG_GUEST_ERROR, "Unknown IRQ to set %d", irq_num);
+ }
+ qemu_set_irq(phb->lsi_ics->qirqs[irq_num], level);
+}
+
+static bool pnv_phb3_resolve_pe(PnvPhb3DMASpace *ds)
+{
+ uint64_t rtt, addr;
+ uint16_t rte;
+ int bus_num;
+
+ /* Already resolved ? */
+ if (ds->pe_num != PHB_INVALID_PE) {
+ return true;
+ }
+
+ /* We need to lookup the RTT */
+ rtt = ds->phb->regs[PHB_RTT_BAR >> 3];
+ if (!(rtt & PHB_RBA_BAR_ENABLE)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "DMA with RTT BAR disabled !");
+ /* Set error bits ? fence ? ... */
+ return false;
+ }
+
+ /* Read RTE */
+ bus_num = pci_bus_num(ds->bus);
+ addr = rtt & PHB_RTT_BASE_ADDRESS_MASK;
+ addr += 2 * ((bus_num << 8) | ds->devfn);
+ if (dma_memory_read(&address_space_memory, addr, &rte, sizeof(rte))) {
+ qemu_log_mask(LOG_GUEST_ERROR, "Failed to read RTT entry at 0x%"PRIx64,
+ addr);
+ /* Set error bits ? fence ? ... */
+ return false;
+ }
+ rte = be16_to_cpu(rte);
+
+ /* Fail upon reading of invalid PE# */
+ if (rte >= PNV_PHB3_NUM_PE) {
+ qemu_log_mask(LOG_GUEST_ERROR, "RTE for RID 0x%x invalid (%04x)",
+ ds->devfn, rte);
+ /* Set error bits ? fence ? ... */
+ return false;
+ }
+ ds->pe_num = rte;
+ return true;
+}
+
+static void pnv_phb3_translate_tve(PnvPhb3DMASpace *ds, hwaddr addr,
+ bool is_write, uint64_t tve,
+ IOMMUTLBEntry *tlb)
+{
+ uint64_t tta = GETFIELD(IODA2_TVT_TABLE_ADDR, tve);
+ int32_t lev = GETFIELD(IODA2_TVT_NUM_LEVELS, tve);
+ uint32_t tts = GETFIELD(IODA2_TVT_TCE_TABLE_SIZE, tve);
+ uint32_t tps = GETFIELD(IODA2_TVT_IO_PSIZE, tve);
+
+ /* Invalid levels */
+ if (lev > 4) {
+ qemu_log_mask(LOG_GUEST_ERROR, "Invalid #levels in TVE %d", lev);
+ return;
+ }
+
+ /* IO Page Size of 0 means untranslated, else use TCEs */
+ if (tps == 0) {
+ /* We only support non-translate in top window
+ * XXX FIX THAT, Venice/Murano support it on bottom window
+ * above 4G and Naples suports it on everything
+ */
+ if (!(tve & PPC_BIT(51))) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "xlate for invalid non-translate TVE");
+ return;
+ }
+ /* XXX Handle boundaries */
+
+ /* XXX Use 4k pages like q35 ... for now */
+ tlb->iova = addr & 0xfffffffffffff000ull;
+ tlb->translated_addr = addr & 0x0003fffffffff000ull;
+ tlb->addr_mask = 0xfffull;
+ tlb->perm = IOMMU_RW;
+ } else {
+ uint32_t tce_shift, tbl_shift, sh;
+ uint64_t base, taddr, tce, tce_mask;
+
+ /* TVE disabled ? */
+ if (tts == 0) {
+ qemu_log_mask(LOG_GUEST_ERROR, "xlate for invalid translated TVE");
+ return;
+ }
+
+ /* Address bits per bottom level TCE entry */
+ tce_shift = tps + 11;
+
+ /* Address bits per table level */
+ tbl_shift = tts + 8;
+
+ /* Top level table base address */
+ base = tta << 12;
+
+ /* Total shift to first level */
+ sh = tbl_shift * lev + tce_shift;
+
+ /* XXX Multi-level untested */
+ while ((lev--) >= 0) {
+ /* Grab the TCE address */
+ taddr = base | (((addr >> sh) & ((1ul << tbl_shift) - 1)) << 3);
+ if (dma_memory_read(&address_space_memory, taddr, &tce,
+ sizeof(tce))) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "Failed to read TCE at 0x%"PRIx64, taddr);
+ return;
+ }
+ tce = be64_to_cpu(tce);
+
+ /* Check permission for indirect TCE */
+ if ((lev >= 0) && !(tce & 3)) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "Invalid indirect TCE at 0x%"PRIx64, taddr);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ " xlate %"PRIx64":%c TVE=%"PRIx64,
+ addr, is_write ? 'W' : 'R', tve);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ " tta=%"PRIx64" lev=%d tts=%d tps=%d",
+ tta, lev, tts, tps);
+ return;
+ }
+ sh -= tbl_shift;
+ base = tce & ~0xfffull;
+ }
+
+ /* We exit the loop with TCE being the final TCE */
+ tce_mask = ~((1ull << tce_shift) - 1);
+ tlb->iova = addr & tce_mask;
+ tlb->translated_addr = tce & tce_mask;
+ tlb->addr_mask = ~tce_mask;
+ tlb->perm = tce & 3;
+ if ((is_write & !(tce & 2)) || ((!is_write) && !(tce & 1))) {
+ qemu_log_mask(LOG_GUEST_ERROR, "TCE access fault at 0x%"PRIx64,
+ taddr);
+ qemu_log_mask(LOG_GUEST_ERROR, " xlate %"PRIx64":%c TVE=%"PRIx64,
+ addr, is_write ? 'W' : 'R', tve);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ " tta=%"PRIx64" lev=%d tts=%d tps=%d",
+ tta, lev, tts, tps);
+ }
+ }
+}
+
+static IOMMUTLBEntry pnv_phb3_translate_iommu(MemoryRegion *iommu, hwaddr addr,
+ bool is_write)
+{
+ PnvPhb3DMASpace *ds = container_of(iommu, PnvPhb3DMASpace, dma_mr);
+ int tve_sel;
+ uint64_t tve, cfg;
+ IOMMUTLBEntry ret = {
+ .target_as = &address_space_memory,
+ .iova = addr,
+ .translated_addr = 0,
+ .addr_mask = ~(hwaddr)0,
+ .perm = IOMMU_NONE,
+ };
+
+ /* Resolve PE# */
+ if (!pnv_phb3_resolve_pe(ds)) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "Failed to resolve PE# for bus @%p (%d) devfn 0x%x",
+ ds->bus, pci_bus_num(ds->bus), ds->devfn);
+ return ret;
+ }
+
+ /* Check top bits */
+ switch (addr >> 60) {
+ case 00:
+ /* DMA or 32-bit MSI ? */
+ cfg = ds->phb->regs[PHB_PHB3_CONFIG >> 3];
+ if ((cfg & PHB_PHB3C_32BIT_MSI_EN) &&
+ ((addr & 0xffffffffffff0000ull) == 0xffff0000ull)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "xlate on 32-bit MSI region");
+ return ret;
+ }
+ /* Choose TVE XXX Use PHB3 Control Register */
+ tve_sel = (addr >> 59) & 1;
+ tve = ds->phb->ioda_TVT[ds->pe_num * 2 + tve_sel];
+ pnv_phb3_translate_tve(ds, addr, is_write, tve, &ret);
+ break;
+ case 01:
+ qemu_log_mask(LOG_GUEST_ERROR, "xlate on 64-bit MSI region");
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "xlate on unsupported address 0x%"PRIx64,
+ addr);
+ }
+ return ret;
+}
+
+static const MemoryRegionIOMMUOps pnv_phb3_iommu_ops = {
+ .translate = pnv_phb3_translate_iommu,
+};
+
+/*
+ * MSI/MSIX memory region implementation.
+ * The handler handles both MSI and MSIX.
+ */
+static void pnv_phb3_msi_write(void *opaque, hwaddr addr,
+ uint64_t data, unsigned size)
+{
+ PnvPhb3DMASpace *ds = opaque;
+
+ /* Resolve PE# */
+ if (!pnv_phb3_resolve_pe(ds)) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "Failed to resolve PE# for bus @%p (%d) devfn 0x%x",
+ ds->bus, pci_bus_num(ds->bus), ds->devfn);
+ return;
+ }
+
+ pnv_phb3_msi_send(ds->phb->msis, addr, data, ds->pe_num);
+}
+
+static const MemoryRegionOps pnv_phb3_msi_ops = {
+ /* There is no .read as the read result is undefined by PCI spec */
+ .read = NULL,
+ .write = pnv_phb3_msi_write,
+ .endianness = DEVICE_LITTLE_ENDIAN
+};
+
+static AddressSpace *pnv_phb3_dma_iommu(PCIBus *bus, void *opaque, int devfn)
+{
+ PnvPhb3State *phb = opaque;
+ PnvPhb3DMASpace *ds;
+
+ QLIST_FOREACH(ds, &phb->dma_spaces, list) {
+ if (ds->bus == bus && ds->devfn == devfn) {
+ break;
+ }
+ }
+ if (ds == NULL) {
+ ds = g_malloc0(sizeof(PnvPhb3DMASpace));
+ ds->bus = bus;
+ ds->devfn = devfn;
+ ds->pe_num = PHB_INVALID_PE;
+ ds->phb = phb;
+ memory_region_init_iommu(&ds->dma_mr, OBJECT(phb),
+ &pnv_phb3_iommu_ops, "phb3_iommu", UINT64_MAX);
+ address_space_init(&ds->dma_as, &ds->dma_mr, "phb3_iommu");
+ memory_region_init_io(&ds->msi32_mr, OBJECT(phb), &pnv_phb3_msi_ops,
+ ds, "msi32", 0x10000);
+ memory_region_init_io(&ds->msi64_mr, OBJECT(phb), &pnv_phb3_msi_ops,
+ ds, "msi64", 0x100000);
+ pnv_phb3_update_msi_regions(ds);
+
+ QLIST_INSERT_HEAD(&phb->dma_spaces, ds, list);
+ }
+ return &ds->dma_as;
+}
+
+static void pnv_phb3_root_bus_class_init(ObjectClass *klass, void *data)
+{
+ BusClass *k = BUS_CLASS(klass);
+
+ k->max_dev = 1;
+}
+
+#define TYPE_PNV_PHB3_ROOT_BUS "pnv-phb3-root-bus"
+
+static const TypeInfo pnv_phb3_root_bus_info = {
+ .name = TYPE_PNV_PHB3_ROOT_BUS,
+ .parent = TYPE_PCIE_BUS,
+ .class_init = pnv_phb3_root_bus_class_init,
+};
+
+static void pnv_phb3_initfn(Object *obj)
+{
+ PnvPhb3State *phb = PNV_PHB3(obj);
+ /* Create LSI source */
+ phb->lsi_ics = ICS_SIMPLE(object_new(TYPE_ICS_SIMPLE));
+ object_property_add_child(OBJECT(phb), "ics-phb-lsi", OBJECT(phb->lsi_ics),
+ NULL);
+
+ /* Default init ... will be fixed by HW inits */
+ phb->lsi_ics->offset = 0;
+ phb->lsi_ics->nr_irqs = PNV_PHB3_NUM_LSI;
+
+ /* Create MSI source */
+ phb->msis = PHB3_MSI(object_new(TYPE_PHB3_MSI));
+ object_property_add_const_link(OBJECT(phb->msis), "phb", obj, &error_abort);
+ object_property_add_child(OBJECT(phb), "ics-phb-msi", OBJECT(phb->msis),
+ NULL);
+
+ /* Create PBCQ */
+ phb->pbcq = PNV_PBCQ(object_new(TYPE_PNV_PBCQ));
+ object_property_add_const_link(OBJECT(phb->pbcq), "phb", obj, &error_abort);
+ object_property_add_child(OBJECT(phb), "pbcq", OBJECT(phb->pbcq), NULL);
+
+ QLIST_INIT(&phb->dma_spaces);
+}
+
+static void pnv_phb3_realize(DeviceState *dev, Error **errp)
+{
+ PnvPhb3State *phb = PNV_PHB3(dev);
+ PCIHostState *pci = PCI_HOST_BRIDGE(dev);
+ Object *obj;
+ Error *error = NULL;
+ int i;
+
+ memory_region_init(&phb->pci_mmio, OBJECT(phb), "pci-mmio",
+ PCI_MMIO_TOTAL_SIZE);
+
+ /* PHB3 doesn't support IO space. However, qemu gets very upset if
+ * we don't have an IO region to anchor IO BARs onto so we just
+ * initialize one which we never hook up to anything
+ */
+ memory_region_init(&phb->pci_io, OBJECT(phb), "pci-io", 0x10000);
+
+ memory_region_init_io(&phb->mr_regs, OBJECT(phb), &pnv_phb3_reg_ops, phb,
+ "phb3-regs", 0x1000);
+
+ /* get XICSFabric from chip */
+ obj = object_property_get_link(OBJECT(dev), "xics", &error);
+ if (!obj) {
+ error_setg(errp, "%s: required link 'xics' not found: %s",
+ __func__, error_get_pretty(error));
+ return;
+ }
+
+ object_property_add_const_link(OBJECT(phb->lsi_ics), "xics", obj, &error);
+ object_property_set_bool(OBJECT(phb->lsi_ics), true, "realized", &error);
+ if (error) {
+ error_propagate(errp, error);
+ return;
+ }
+
+ for (i = 0; i < PNV_PHB3_NUM_LSI; i++) {
+ ics_set_irq_type(phb->lsi_ics, i, true);
+ }
+
+ object_property_add_const_link(OBJECT(phb->msis), "xics", obj, &error);
+ object_property_set_bool(OBJECT(phb->msis), true, "realized", &error);
+ if (error) {
+ error_propagate(errp, error);
+ return;
+ }
+
+ object_property_set_int(OBJECT(phb->pbcq), phb->phb_id, "phb-id", &error);
+ object_property_set_int(OBJECT(phb->pbcq), phb->chip_id, "chip-id", &error);
+ object_property_set_bool(OBJECT(phb->pbcq), true, "realized", &error);
+ if (error) {
+ error_propagate(errp, error);
+ return;
+ }
+
+ pci->bus = pci_register_bus(dev, "phb3-root-bus",
+ pnv_phb3_set_irq, pnv_phb3_map_irq, phb,
+ &phb->pci_mmio, &phb->pci_io,
+ 0, 4, TYPE_PNV_PHB3_ROOT_BUS);
+ pci->bus->devfn_max = 1;
+ pci_setup_iommu(pci->bus, pnv_phb3_dma_iommu, phb);
+}
+
+void pnv_phb3_update_regions(PnvPhb3State *phb)
+{
+ /* Unmap first always */
+ if (phb->regs_mapped) {
+ memory_region_del_subregion(&phb->pbcq->phbbar, &phb->mr_regs);
+ phb->regs_mapped = false;
+ }
+
+ /* Map registers if enabled */
+ if (phb->pbcq->phb_mapped) {
+ /* XXX We should use the PHB BAR 2 register but we don't ... */
+ memory_region_add_subregion(&phb->pbcq->phbbar, 0, &phb->mr_regs);
+ phb->regs_mapped = true;
+ }
+
+ /* Check/update m32 */
+ if (phb->m32_mapped) {
+ pnv_phb3_check_m32(phb);
+ }
+}
+
+static Property pnv_phb3_properties[] = {
+ DEFINE_PROP_UINT32("phb-id", PnvPhb3State, phb_id, 0),
+ DEFINE_PROP_UINT32("chip-id", PnvPhb3State, chip_id, 0),
+ DEFINE_PROP_END_OF_LIST(),
+
+};
+
+static void pnv_phb3_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = pnv_phb3_realize;
+ dc->props = pnv_phb3_properties;
+}
+
+static const TypeInfo pnv_phb3_type_info = {
+ .name = TYPE_PNV_PHB3,
+ .parent = TYPE_PCI_HOST_BRIDGE,
+ .instance_size = sizeof(PnvPhb3State),
+ .class_init = pnv_phb3_class_init,
+ .instance_init = pnv_phb3_initfn,
+};
+
+static void pnv_phb3_register_types(void)
+{
+ type_register_static(&pnv_phb3_type_info);
+ type_register_static(&pnv_phb3_root_bus_info);
+}
+
+type_init(pnv_phb3_register_types)
diff --git a/hw/pci-host/pnv_phb3_msi.c b/hw/pci-host/pnv_phb3_msi.c
new file mode 100644
index 000000000000..d4041de37b16
--- /dev/null
+++ b/hw/pci-host/pnv_phb3_msi.c
@@ -0,0 +1,304 @@
+/*
+ * QEMU PowerPC PowerNV PHB3 model
+ *
+ * Copyright (c) 2014-2017, IBM Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qapi/error.h"
+#include "qemu-common.h"
+#include "hw/pci-host/pnv_phb3.h"
+#include "hw/pci/msi.h"
+
+static uint64_t phb3_msi_ive_addr(PnvPhb3State *phb, int srcno)
+{
+ uint64_t ivtbar = phb->regs[PHB_IVT_BAR >> 3];
+ uint64_t phbctl = phb->regs[PHB_CONTROL >> 3];
+
+ if (!(ivtbar & PHB_IVT_BAR_ENABLE)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "Failed access to disable IVT BAR !");
+ return 0;
+ }
+
+ if (srcno >= (ivtbar & PHB_IVT_LENGTH_MASK)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "MSI out of bounds (%d vs 0x%"PRIx64")",
+ srcno, ivtbar & PHB_IVT_LENGTH_MASK);
+ return 0;
+ }
+
+ ivtbar &= PHB_IVT_BASE_ADDRESS_MASK;
+
+ if (phbctl & PHB_CTRL_IVE_128_BYTES) {
+ return ivtbar + 128 * srcno;
+ } else {
+ return ivtbar + 16 * srcno;
+ }
+}
+
+static bool phb3_msi_read_ive(PnvPhb3State *phb, int srcno, uint64_t *out_ive)
+{
+ uint64_t ive_addr, ive;
+
+ ive_addr = phb3_msi_ive_addr(phb, srcno);
+ if (!ive_addr) {
+ return false;
+ }
+
+ if (dma_memory_read(&address_space_memory, ive_addr, &ive, sizeof(ive))) {
+ qemu_log_mask(LOG_GUEST_ERROR, "Failed to read IVE at 0x%" PRIx64,
+ ive_addr);
+ return false;
+ }
+ *out_ive = be64_to_cpu(ive);
+
+ return true;
+}
+
+static void phb3_msi_set_p(Phb3MsiState *msis, int srcno, uint8_t gen)
+{
+ uint64_t ive_addr;
+ uint8_t p = 0x01 | (gen << 1);
+
+ ive_addr = phb3_msi_ive_addr(msis->phb, srcno);
+ if (!ive_addr) {
+ return;
+ }
+
+ if (dma_memory_write(&address_space_memory, ive_addr + 4, &p, 1)) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "Failed to write IVE (set P) at 0x%" PRIx64, ive_addr);
+ }
+}
+
+static void phb3_msi_set_q(Phb3MsiState *msis, int srcno)
+{
+ uint64_t ive_addr;
+ uint8_t q = 0x01;
+
+ ive_addr = phb3_msi_ive_addr(msis->phb, srcno);
+ if (!ive_addr) {
+ return;
+ }
+
+ if (dma_memory_write(&address_space_memory, ive_addr + 5, &q, 1)) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "Failed to write IVE (set Q) at 0x%" PRIx64, ive_addr);
+ }
+}
+
+static void phb3_msi_try_send(Phb3MsiState *msis, int srcno, bool ignore_p)
+{
+ ICSState *ics = &msis->ics;
+ uint64_t ive;
+ uint64_t server, prio, pq, gen;
+
+ if (!phb3_msi_read_ive(msis->phb, srcno, &ive)) {
+ return;
+ }
+
+ server = GETFIELD(IODA2_IVT_SERVER, ive);
+ prio = GETFIELD(IODA2_IVT_PRIORITY, ive);
+ pq = GETFIELD(IODA2_IVT_Q, ive);
+ if (!ignore_p) {
+ pq |= GETFIELD(IODA2_IVT_P, ive) << 1;
+ }
+ gen = GETFIELD(IODA2_IVT_GEN, ive);
+
+ /*
+ * The low order 2 bits are the link pointer (Type II interrupts).
+ * Shift back to get a valid IRQ server.
+ */
+ server >>= 2;
+
+ switch (pq) {
+ case 0: /* 00 */
+ if (prio == 0xff) {
+ /* Masked, set Q */
+ phb3_msi_set_q(msis, srcno);
+ } else {
+ /* Enabled, set P and send */
+ phb3_msi_set_p(msis, srcno, gen);
+ icp_irq(ics, server, srcno + ics->offset, prio);
+ }
+ break;
+ case 2: /* 10 */
+ /* Already pending, set Q */
+ phb3_msi_set_q(msis, srcno);
+ break;
+ case 1: /* 01 */
+ case 3: /* 11 */
+ default:
+ /* Just drop stuff if Q already set */
+ break;
+ }
+}
+
+static void phb3_msi_set_irq(void *opaque, int srcno, int val)
+{
+ Phb3MsiState *msis = opaque;
+
+ if (val) {
+ phb3_msi_try_send(msis, srcno, false);
+ }
+}
+
+
+void pnv_phb3_msi_send(Phb3MsiState *msis, uint64_t addr, uint16_t data,
+ int32_t dev_pe)
+{
+ uint64_t ive;
+ uint16_t pe;
+ uint32_t src = ((addr >> 4) & 0xffff) | (data & 0x1f);
+
+ if (src >= msis->ics.nr_irqs) {
+ qemu_log_mask(LOG_GUEST_ERROR, "MSI %d out of bounds", src);
+ return;
+ }
+ if (dev_pe >= 0) {
+ if (!phb3_msi_read_ive(msis->phb, src, &ive)) {
+ return;
+ }
+ pe = GETFIELD(IODA2_IVT_PE, ive);
+ if (pe != dev_pe) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "MSI %d send by PE#%d but assigned to PE#%d",
+ src, dev_pe, pe);
+ return;
+ }
+ }
+ qemu_irq_pulse(msis->ics.qirqs[src]);
+}
+
+void pnv_phb3_msi_ffi(Phb3MsiState *msis, uint64_t val)
+{
+ /* Emit interrupt */
+ pnv_phb3_msi_send(msis, val, 0, -1);
+
+ /* Clear FFI lock */
+ msis->phb->regs[PHB_FFI_LOCK >> 3] = 0;
+}
+
+static void phb3_msi_reject(ICSState *ics, uint32_t nr)
+{
+ Phb3MsiState *msis = PHB3_MSI(ics);
+ unsigned int srcno = nr - ics->offset;
+ unsigned int idx = srcno >> 6;
+ unsigned int bit = 1ull << (srcno & 0x3f);
+
+ assert(srcno < PHB3_MAX_MSI);
+
+ msis->rba[idx] |= bit;
+ msis->rba_sum |= (1u << idx);
+}
+
+static void phb3_msi_resend(ICSState *ics)
+{
+ Phb3MsiState *msis = PHB3_MSI(ics);
+ unsigned int i, j;
+
+ if (msis->rba_sum == 0) {
+ return;
+ }
+
+ for (i = 0; i < 32; i++) {
+ if ((msis->rba_sum & (1u << i)) == 0) {
+ continue;
+ }
+ msis->rba_sum &= ~(1u << i);
+ for (j = 0; j < 64; j++) {
+ if ((msis->rba[i] & (1ull << j)) == 0) {
+ continue;
+ }
+ msis->rba[i] &= ~(1u << j);
+ phb3_msi_try_send(msis, i * 64 + j, true);
+ }
+ }
+}
+
+static void phb3_msi_reset(void *dev)
+{
+ Phb3MsiState *msis = PHB3_MSI(dev);
+
+ memset(msis->rba, 0, sizeof(msis->rba));
+ msis->rba_sum = 0;
+}
+
+void pnv_phb3_msi_update_config(Phb3MsiState *msis, uint32_t base,
+ uint32_t count)
+{
+ if (count > PHB3_MAX_MSI) {
+ count = PHB3_MAX_MSI;
+ }
+ msis->ics.nr_irqs = count;
+ msis->ics.offset = base;
+}
+
+static void phb3_msi_initfn(Object *obj)
+{
+ Phb3MsiState *msis = PHB3_MSI(obj);
+
+ /* Will be overriden later */
+ msis->ics.offset = 0;
+
+ /* Hard wire 2048, we ignore the fact that 8 of them can be
+ * taken over by LSIs at this point
+ */
+ msis->ics.nr_irqs = PHB3_MAX_MSI;
+}
+
+static void phb3_msi_realize(DeviceState *dev, Error **errp)
+{
+ Phb3MsiState *msis = PHB3_MSI(dev);
+ Object *obj;
+ Error *err = NULL;
+
+ obj = object_property_get_link(OBJECT(dev), "phb", &err);
+ if (!obj) {
+ error_setg(errp, "%s: required link 'phb' not found: %s",
+ __func__, error_get_pretty(err));
+ return;
+ }
+ msis->phb = PNV_PHB3(obj);
+
+ msis->ics.irqs = NULL;
+ msis->ics.qirqs = qemu_allocate_irqs(phb3_msi_set_irq, msis, PHB3_MAX_MSI);
+
+ qemu_register_reset(phb3_msi_reset, dev);
+}
+
+static void phb3_msi_class_init(ObjectClass *klass, void *data)
+{
+ ICSStateClass *isc = ICS_BASE_CLASS(klass);
+
+ isc->realize = phb3_msi_realize;
+ isc->reject = phb3_msi_reject;
+ isc->resend = phb3_msi_resend;
+}
+
+static const TypeInfo phb3_msi_info = {
+ .name = TYPE_PHB3_MSI,
+ .parent = TYPE_ICS_BASE,
+ .instance_size = sizeof(Phb3MsiState),
+ .class_init = phb3_msi_class_init,
+ .class_size = sizeof(ICSStateClass),
+ .instance_init = phb3_msi_initfn,
+};
+
+static void pnv_phb3_msi_register_types(void)
+{
+ type_register_static(&phb3_msi_info);
+}
+
+type_init(pnv_phb3_msi_register_types)
diff --git a/hw/pci-host/pnv_phb3_pbcq.c b/hw/pci-host/pnv_phb3_pbcq.c
new file mode 100644
index 000000000000..2f32632c2aff
--- /dev/null
+++ b/hw/pci-host/pnv_phb3_pbcq.c
@@ -0,0 +1,361 @@
+/*
+ * QEMU PowerPC PowerNV PHB3 model
+ *
+ * Copyright (c) 2014-2017, IBM Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qemu-common.h"
+#include "qemu/log.h"
+#include "hw/ppc/fdt.h"
+#include "hw/pci-host/pnv_phb3.h"
+#include "hw/ppc/pnv.h"
+#include "hw/ppc/pnv_xscom.h"
+#include "hw/pci/pci_bridge.h"
+#include "hw/pci/pci_bus.h"
+
+#include <libfdt.h>
+
+static uint64_t pnv_pbcq_nest_xscom_read(void *opaque, hwaddr addr,
+ unsigned size)
+{
+ PnvPBCQState *pbcq = PNV_PBCQ(opaque);
+ uint32_t offset = addr >> 3;
+
+ return pbcq->nest_regs[offset];
+}
+
+static uint64_t pnv_pbcq_pci_xscom_read(void *opaque, hwaddr addr,
+ unsigned size)
+{
+ PnvPBCQState *pbcq = PNV_PBCQ(opaque);
+ uint32_t offset = addr >> 3;
+
+ return pbcq->pci_regs[offset];
+}
+
+static uint64_t pnv_pbcq_spci_xscom_read(void *opaque, hwaddr addr,
+ unsigned size)
+{
+ PnvPBCQState *pbcq = PNV_PBCQ(opaque);
+ uint32_t offset = addr >> 3;
+
+ if (offset == PBCQ_SPCI_ASB_DATA) {
+ return pnv_phb3_reg_read(pbcq->phb,
+ pbcq->spci_regs[PBCQ_SPCI_ASB_ADDR], 8);
+ }
+ return pbcq->spci_regs[offset];
+}
+
+static void pnv_pbcq_update_map(PnvPBCQState *pbcq)
+{
+ uint64_t bar_en = pbcq->nest_regs[PBCQ_NEST_BAR_EN];
+ uint64_t bar, mask, size;
+
+ /*
+ * NOTE: This will really not work well if those are remapped
+ * after the PHB has created its sub regions. We could do better
+ * if we had a way to resize regions but we don't really care
+ * that much in practice as the stuff below really only happens
+ * once early during boot
+ */
+
+ /* Handle unmaps */
+ if (pbcq->mmio0_mapped && !(bar_en & PBCQ_NEST_BAR_EN_MMIO0)) {
+ memory_region_del_subregion(get_system_memory(), &pbcq->mmbar0);
+ pbcq->mmio0_mapped = false;
+ }
+ if (pbcq->mmio1_mapped && !(bar_en & PBCQ_NEST_BAR_EN_MMIO1)) {
+ memory_region_del_subregion(get_system_memory(), &pbcq->mmbar1);
+ pbcq->mmio1_mapped = false;
+ }
+ if (pbcq->phb_mapped && !(bar_en & PBCQ_NEST_BAR_EN_PHB)) {
+ memory_region_del_subregion(get_system_memory(), &pbcq->phbbar);
+ pbcq->phb_mapped = false;
+ }
+
+ /* Update PHB */
+ pnv_phb3_update_regions(pbcq->phb);
+
+ /* Handle maps */
+ if (!pbcq->mmio0_mapped && (bar_en & PBCQ_NEST_BAR_EN_MMIO0)) {
+ bar = pbcq->nest_regs[PBCQ_NEST_MMIO_BAR0] >> 14;
+ mask = pbcq->nest_regs[PBCQ_NEST_MMIO_MASK0];
+ size = ((~mask) >> 14) + 1;
+ memory_region_init(&pbcq->mmbar0, OBJECT(pbcq), "pbcq-mmio0", size);
+ memory_region_add_subregion(get_system_memory(), bar, &pbcq->mmbar0);
+ pbcq->mmio0_mapped = true;
+ pbcq->mmio0_base = bar;
+ pbcq->mmio0_size = size;
+ }
+ if (!pbcq->mmio1_mapped && (bar_en & PBCQ_NEST_BAR_EN_MMIO1)) {
+ bar = pbcq->nest_regs[PBCQ_NEST_MMIO_BAR1] >> 14;
+ mask = pbcq->nest_regs[PBCQ_NEST_MMIO_MASK1];
+ size = ((~mask) >> 14) + 1;
+ memory_region_init(&pbcq->mmbar1, OBJECT(pbcq), "pbcq-mmio1", size);
+ memory_region_add_subregion(get_system_memory(), bar, &pbcq->mmbar1);
+ pbcq->mmio1_mapped = true;
+ pbcq->mmio1_base = bar;
+ pbcq->mmio1_size = size;
+ }
+ if (!pbcq->phb_mapped && (bar_en & PBCQ_NEST_BAR_EN_PHB)) {
+ bar = pbcq->nest_regs[PBCQ_NEST_PHB_BAR] >> 14;
+ size = 0x1000;
+ memory_region_init(&pbcq->phbbar, OBJECT(pbcq), "pbcq-phb", size);
+ memory_region_add_subregion(get_system_memory(), bar, &pbcq->phbbar);
+ pbcq->phb_mapped = true;
+ }
+
+ /* Update PHB */
+ pnv_phb3_update_regions(pbcq->phb);
+}
+
+static void pnv_pbcq_nest_xscom_write(void *opaque, hwaddr addr,
+ uint64_t val, unsigned size)
+{
+ PnvPBCQState *pbcq = PNV_PBCQ(opaque);
+ uint32_t reg = addr >> 3;
+
+ switch (reg) {
+ case PBCQ_NEST_MMIO_BAR0:
+ case PBCQ_NEST_MMIO_BAR1:
+ case PBCQ_NEST_MMIO_MASK0:
+ case PBCQ_NEST_MMIO_MASK1:
+ if (pbcq->nest_regs[PBCQ_NEST_BAR_EN] &
+ (PBCQ_NEST_BAR_EN_MMIO0 |
+ PBCQ_NEST_BAR_EN_MMIO1)) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "PHB3: Changing enabled BAR unsupported\n");
+ }
+ pbcq->nest_regs[reg] = val & 0xffffffffc0000000ull;
+ break;
+ case PBCQ_NEST_PHB_BAR:
+ if (pbcq->nest_regs[PBCQ_NEST_BAR_EN] & PBCQ_NEST_BAR_EN_PHB) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "PHB3: Changing enabled BAR unsupported\n");
+ }
+ pbcq->nest_regs[reg] = val & 0xfffffffffc000000ull;
+ break;
+ case PBCQ_NEST_BAR_EN:
+ pbcq->nest_regs[reg] = val & 0xf800000000000000ull;
+ pnv_pbcq_update_map(pbcq);
+ pnv_phb3_remap_irqs(pbcq->phb);
+ break;
+ case PBCQ_NEST_IRSN_COMPARE:
+ case PBCQ_NEST_IRSN_MASK:
+ pbcq->nest_regs[reg] = val & PBCQ_NEST_IRSN_COMP_MASK;
+ pnv_phb3_remap_irqs(pbcq->phb);
+ break;
+ case PBCQ_NEST_LSI_SRC_ID:
+ pbcq->nest_regs[reg] = val & PBCQ_NEST_LSI_SRC_MASK;
+ pnv_phb3_remap_irqs(pbcq->phb);
+ break;
+ }
+
+ /* XXX Don't error out on other regs for now ... */
+}
+
+static void pnv_pbcq_pci_xscom_write(void *opaque, hwaddr addr,
+ uint64_t val, unsigned size)
+{
+ PnvPBCQState *pbcq = PNV_PBCQ(opaque);
+ uint32_t reg = addr >> 3;
+
+ switch (reg) {
+ case PBCQ_PCI_BAR2:
+ pbcq->pci_regs[reg] = val & 0xfffffffffc000000ull;
+ pnv_pbcq_update_map(pbcq);
+ break;
+ }
+
+ /* XXX Don't error out on other regs for now ... */
+}
+
+static void pnv_pbcq_spci_xscom_write(void *opaque, hwaddr addr,
+ uint64_t val, unsigned size)
+{
+ PnvPBCQState *pbcq = PNV_PBCQ(opaque);
+ uint32_t reg = addr >> 3;
+
+ switch (reg) {
+ case PBCQ_SPCI_ASB_ADDR:
+ pbcq->spci_regs[reg] = val & 0xfff;
+ break;
+ case PBCQ_SPCI_ASB_STATUS:
+ pbcq->spci_regs[reg] &= ~val;
+ break;
+ case PBCQ_SPCI_ASB_DATA:
+ pnv_phb3_reg_write(pbcq->phb, pbcq->spci_regs[PBCQ_SPCI_ASB_ADDR],
+ val, 8);
+ break;
+ case PBCQ_SPCI_AIB_CAPP_EN:
+ case PBCQ_SPCI_CAPP_SEC_TMR:
+ break;
+ }
+
+ /* XXX Don't error out on other regs for now ... */
+}
+
+static const MemoryRegionOps pnv_pbcq_nest_xscom_ops = {
+ .read = pnv_pbcq_nest_xscom_read,
+ .write = pnv_pbcq_nest_xscom_write,
+ .valid.min_access_size = 8,
+ .valid.max_access_size = 8,
+ .impl.min_access_size = 8,
+ .impl.max_access_size = 8,
+ .endianness = DEVICE_BIG_ENDIAN,
+};
+
+static const MemoryRegionOps pnv_pbcq_pci_xscom_ops = {
+ .read = pnv_pbcq_pci_xscom_read,
+ .write = pnv_pbcq_pci_xscom_write,
+ .valid.min_access_size = 8,
+ .valid.max_access_size = 8,
+ .impl.min_access_size = 8,
+ .impl.max_access_size = 8,
+ .endianness = DEVICE_BIG_ENDIAN,
+};
+
+static const MemoryRegionOps pnv_pbcq_spci_xscom_ops = {
+ .read = pnv_pbcq_spci_xscom_read,
+ .write = pnv_pbcq_spci_xscom_write,
+ .valid.min_access_size = 8,
+ .valid.max_access_size = 8,
+ .impl.min_access_size = 8,
+ .impl.max_access_size = 8,
+ .endianness = DEVICE_BIG_ENDIAN,
+};
+
+static void pnv_pbcq_default_bars(PnvPBCQState *pbcq)
+{
+ uint64_t mm0, mm1, reg;
+
+ mm0 = 0x3d00000000000ull +
+ 0x4000000000ull * pbcq->chip_id +
+ 0x1000000000ull * pbcq->phb_id;
+ mm1 = 0x3ff8000000000ull +
+ 0x0200000000ull * pbcq->chip_id +
+ 0x0080000000ull * pbcq->phb_id;
+ reg = 0x3fffe40000000ull +
+ 0x0000400000ull * pbcq->chip_id +
+ 0x0000100000ull * pbcq->phb_id;
+
+ pbcq->nest_regs[PBCQ_NEST_MMIO_BAR0] = mm0 << 14;
+ pbcq->nest_regs[PBCQ_NEST_MMIO_BAR1] = mm1 << 14;
+ pbcq->nest_regs[PBCQ_NEST_PHB_BAR] = reg << 14;
+ pbcq->nest_regs[PBCQ_NEST_MMIO_MASK0] = 0x3fff000000000ull << 14;
+ pbcq->nest_regs[PBCQ_NEST_MMIO_MASK1] = 0x3ffff80000000ull << 14;
+ pbcq->pci_regs[PBCQ_PCI_BAR2] = reg << 14;
+}
+
+static void pnv_pbcq_realize(DeviceState *dev, Error **errp)
+{
+ PnvPBCQState *pbcq = PNV_PBCQ(dev);
+ Object *obj;
+ Error *err = NULL;
+
+ assert(pbcq->phb_id < 4);
+
+ obj = object_property_get_link(OBJECT(dev), "phb", &err);
+ if (!obj) {
+ error_setg(errp, "%s: required link 'phb' not found: %s",
+ __func__, error_get_pretty(err));
+ return;
+ }
+ pbcq->phb = PNV_PHB3(obj);
+
+ /* XXX Fix OPAL to do that: establish default BAR values */
+ pnv_pbcq_default_bars(pbcq);
+
+ /* XScom region for PBCQ registers */
+ memory_region_init_io(&pbcq->xscom_nest_regs, OBJECT(dev),
+ &pnv_pbcq_nest_xscom_ops,
+ pbcq, "xscom-pbcq-nest",
+ PNV_XSCOM_PBCQ_NEST_SIZE << 3);
+ memory_region_init_io(&pbcq->xscom_pci_regs, OBJECT(dev),
+ &pnv_pbcq_pci_xscom_ops,
+ pbcq, "xscom-pbcq-pci",
+ PNV_XSCOM_PBCQ_PCI_SIZE << 3);
+ memory_region_init_io(&pbcq->xscom_spci_regs, OBJECT(dev),
+ &pnv_pbcq_spci_xscom_ops,
+ pbcq, "xscom-pbcq-spci",
+ PNV_XSCOM_PBCQ_SPCI_SIZE << 3);
+}
+
+static int pnv_pbcq_populate(PnvXScomInterface *dev, void *fdt,
+ int xscom_offset)
+{
+ const char compat[] = "ibm,power8-pbcq";
+ PnvPBCQState *pbcq = PNV_PBCQ(dev);
+ char *name;
+ int offset;
+ uint32_t lpc_pcba = PNV_XSCOM_PBCQ_NEST_BASE;
+ uint32_t reg[] = {
+ cpu_to_be32(lpc_pcba),
+ cpu_to_be32(PNV_XSCOM_PBCQ_NEST_SIZE),
+ cpu_to_be32(PNV_XSCOM_PBCQ_PCI_BASE),
+ cpu_to_be32(PNV_XSCOM_PBCQ_PCI_SIZE),
+ cpu_to_be32(PNV_XSCOM_PBCQ_SPCI_BASE),
+ cpu_to_be32(PNV_XSCOM_PBCQ_SPCI_SIZE)
+ };
+
+ name = g_strdup_printf("pbcq@%x", lpc_pcba);
+ offset = fdt_add_subnode(fdt, xscom_offset, name);
+ _FDT(offset);
+ g_free(name);
+
+ _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg))));
+
+ _FDT((fdt_setprop_cell(fdt, offset, "ibm,phb-index", pbcq->phb_id)));
+ _FDT((fdt_setprop(fdt, offset, "compatible", compat,
+ sizeof(compat))));
+ return 0;
+}
+
+static Property pnv_pbcq_properties[] = {
+ DEFINE_PROP_UINT32("phb-id", PnvPBCQState, phb_id, 0),
+ DEFINE_PROP_UINT32("chip-id", PnvPBCQState, chip_id, 0),
+ DEFINE_PROP_END_OF_LIST(),
+
+};
+
+static void pnv_pbcq_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass);
+
+ xdc->populate = pnv_pbcq_populate;
+
+ dc->realize = pnv_pbcq_realize;
+ dc->props = pnv_pbcq_properties;
+}
+
+static const TypeInfo pnv_pbcq_type_info = {
+ .name = TYPE_PNV_PBCQ,
+ .parent = TYPE_DEVICE,
+ .instance_size = sizeof(PnvPBCQState),
+ .class_init = pnv_pbcq_class_init,
+ .interfaces = (InterfaceInfo[]) {
+ { TYPE_PNV_XSCOM_INTERFACE },
+ { }
+ }
+};
+
+static void pnv_pbcq_register_types(void)
+{
+ type_register_static(&pnv_pbcq_type_info);
+}
+
+type_init(pnv_pbcq_register_types)
diff --git a/hw/pci-host/pnv_phb3_rc.c b/hw/pci-host/pnv_phb3_rc.c
new file mode 100644
index 000000000000..b68e694518ca
--- /dev/null
+++ b/hw/pci-host/pnv_phb3_rc.c
@@ -0,0 +1,134 @@
+/*
+ * QEMU PowerPC PowerNV PHB3 model
+ *
+ * Copyright (c) 2014-2017, IBM Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qemu-common.h"
+#include "hw/pci-host/pnv_phb3.h"
+#include "hw/pci/pcie_port.h"
+
+static void pnv_phb3_rc_write_config(PCIDevice *d,
+ uint32_t address, uint32_t val, int len)
+{
+ uint32_t root_cmd =
+ pci_get_long(d->config + d->exp.aer_cap + PCI_ERR_ROOT_COMMAND);
+
+ pci_bridge_write_config(d, address, val, len);
+ pcie_cap_slot_write_config(d, address, val, len);
+ pcie_aer_write_config(d, address, val, len);
+ pcie_aer_root_write_config(d, address, val, len, root_cmd);
+}
+
+static void pnv_phb3_rc_reset(DeviceState *qdev)
+{
+ PCIDevice *d = PCI_DEVICE(qdev);
+
+ pcie_cap_root_reset(d);
+ pcie_cap_deverr_reset(d);
+ pcie_cap_slot_reset(d);
+ pcie_cap_arifwd_reset(d);
+ pcie_aer_root_reset(d);
+ pci_bridge_reset(qdev);
+ pci_bridge_disable_base_limit(d);
+}
+
+static void pnv_phb3_rc_realize(PCIDevice *d, Error **errp)
+{
+ PCIEPort *p = PCIE_PORT(d);
+ PCIESlot *s = PCIE_SLOT(d);
+ int rc;
+ Error *err = NULL;
+
+ DEVICE(d)->id = "pcie";
+ pci_bridge_initfn(d, TYPE_PCIE_BUS);
+
+ /* TODO Make that a property ? Allow for only one device (8 functions) */
+ pci_bridge_get_sec_bus(PCI_BRIDGE(d))->devfn_max = 8;
+
+ pcie_port_init_reg(d);
+
+ rc = pcie_cap_init(d, 0x48, PCI_EXP_TYPE_ROOT_PORT, p->port);
+ if (rc < 0) {
+ error_setg(errp, "phb3-rc: pcie_cap_init() error %d !", rc);
+ goto err_bridge;
+ }
+ pcie_cap_arifwd_init(d);
+ pcie_cap_deverr_init(d);
+ pcie_cap_slot_init(d, s->slot);
+ pcie_chassis_create(s->chassis);
+ rc = pcie_chassis_add_slot(s);
+ if (rc < 0) {
+ error_setg(errp, "phb3-rc: pcie_chassis_add_slot() error %d !", rc);
+ goto err_pcie_cap;
+ }
+ pcie_cap_root_init(d);
+ rc = pcie_aer_init(d, PCI_ERR_VER, 0x100, PCI_ERR_SIZEOF, &err);
+ if (rc < 0) {
+ error_propagate(errp, err);
+ goto err_slot;
+ }
+ pcie_aer_root_init(d);
+ return;
+
+err_slot:
+ pcie_chassis_del_slot(s);
+err_pcie_cap:
+ pcie_cap_exit(d);
+err_bridge:
+ pci_bridge_exitfn(d);
+}
+
+static void pnv_phb3_rc_exit(PCIDevice *d)
+{
+ PCIESlot *s = PCIE_SLOT(d);
+
+ pcie_aer_exit(d);
+ pcie_chassis_del_slot(s);
+ pcie_cap_exit(d);
+ pci_bridge_exitfn(d);
+}
+
+static void pnv_phb3_rc_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+
+ k->is_express = 1;
+ k->is_bridge = 1;
+ k->realize = pnv_phb3_rc_realize;
+ k->exit = pnv_phb3_rc_exit;
+ k->config_write = pnv_phb3_rc_write_config;
+ k->vendor_id = PCI_VENDOR_ID_IBM;
+ k->device_id = 0x03dc;
+ k->revision = 0;
+ set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
+ dc->desc = "IBM PHB3 PCIE Root Port";
+ dc->reset = pnv_phb3_rc_reset;
+}
+
+static const TypeInfo pnv_phb3_rc_info = {
+ .name = TYPE_PNV_PHB3_RC,
+ .parent = TYPE_PCIE_SLOT,
+ .class_init = pnv_phb3_rc_class_init,
+};
+
+static void pnv_phb3_rc_register_types(void)
+{
+ type_register_static(&pnv_phb3_rc_info);
+}
+
+type_init(pnv_phb3_rc_register_types)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index df0a88c3e252..db6e078edcea 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -43,6 +43,11 @@
#include "hw/isa/isa.h"
#include "hw/char/serial.h"
#include "hw/timer/mc146818rtc.h"
+#include "hw/pci/pci.h"
+#include "hw/pci/pci_bus.h"
+#include "hw/pci/pci_bridge.h"
+#include "hw/pci/msi.h"
+#include "hw/pci-host/pnv_phb3.h"
#include <libfdt.h>
@@ -659,6 +664,7 @@ static void ppc_powernv_init(MachineState *machine)
object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id",
&error_fatal);
object_property_set_int(chip, smp_cores, "nr-cores", &error_fatal);
+ object_property_set_int(chip, 1, "num-phbs", &error_fatal);
object_property_set_bool(chip, true, "realized", &error_fatal);
}
g_free(chip_typename);
@@ -905,6 +911,41 @@ static void pnv_chip_icp_realize(PnvChip *chip, Error **errp)
g_free(typename);
}
+static PnvPhb3State *pnv_chip_phb_realize(PnvChip *chip, int i, Error **errp)
+{
+ Error *error = NULL;
+ PnvPhb3State *phb = NULL;
+ Object *obj;
+ char name[32];
+
+ snprintf(name, sizeof(name), "phb[%d]", i);
+ obj = object_new(TYPE_PNV_PHB3);
+ qdev_set_parent_bus(DEVICE(obj), sysbus_get_default());
+ object_property_set_int(obj, i, "phb-id", &error_fatal);
+ object_property_set_int(obj, chip->chip_id, "chip-id", &error_fatal);
+ object_property_add_child(OBJECT(chip), name, obj, &error_fatal);
+ object_property_add_const_link(obj, "xics", qdev_get_machine(),
+ &error_fatal);
+ object_property_set_bool(obj, true, "realized", &error);
+ if (error) {
+ error_propagate(errp, error);
+ return NULL;
+ }
+
+ phb = PNV_PHB3(obj);
+
+ memory_region_add_subregion(&chip->xscom,
+ (PNV_XSCOM_PBCQ_NEST_BASE + 0x400 * i) << 3,
+ &phb->pbcq->xscom_nest_regs);
+ memory_region_add_subregion(&chip->xscom,
+ (PNV_XSCOM_PBCQ_PCI_BASE + 0x400 * i) << 3,
+ &phb->pbcq->xscom_pci_regs);
+ memory_region_add_subregion(&chip->xscom,
+ (PNV_XSCOM_PBCQ_SPCI_BASE + 0x040 * i) << 3,
+ &phb->pbcq->xscom_spci_regs);
+ return phb;
+}
+
static void pnv_chip_realize(DeviceState *dev, Error **errp)
{
PnvChip *chip = PNV_CHIP(dev);
@@ -1003,6 +1044,18 @@ static void pnv_chip_realize(DeviceState *dev, Error **errp)
return;
}
pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip->occ.xscom_regs);
+
+ /* MSIs are supported on this platform */
+ msi_nonbroken = true;
+
+ /* Create Power system Host Bridges 3 (PHB3) */
+ for (i = 0; i < chip->num_phbs; i++) {
+ chip->phbs[i] = pnv_chip_phb_realize(chip, i, &error);
+ if (error) {
+ error_propagate(errp, error);
+ return;
+ }
+ }
}
static Property pnv_chip_properties[] = {
@@ -1011,6 +1064,7 @@ static Property pnv_chip_properties[] = {
DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0),
DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1),
DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0),
+ DEFINE_PROP_UINT32("num-phbs", PnvChip, num_phbs, 1),
DEFINE_PROP_END_OF_LIST(),
};
@@ -1035,12 +1089,20 @@ static const TypeInfo pnv_chip_info = {
static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
{
PnvMachineState *pnv = POWERNV_MACHINE(xi);
- int i;
+ int i, j;
for (i = 0; i < pnv->num_chips; i++) {
if (ics_valid_irq(&pnv->chips[i]->psi.ics, irq)) {
return &pnv->chips[i]->psi.ics;
}
+ for (j = 0; j < pnv->chips[i]->num_phbs; j++) {
+ if (ics_valid_irq(pnv->chips[i]->phbs[j]->lsi_ics, irq)) {
+ return pnv->chips[i]->phbs[j]->lsi_ics;
+ }
+ if (ics_valid_irq(ICS_BASE(pnv->chips[i]->phbs[j]->msis), irq)) {
+ return ICS_BASE(pnv->chips[i]->phbs[j]->msis);
+ }
+ }
}
return NULL;
}
@@ -1048,10 +1110,14 @@ static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
static void pnv_ics_resend(XICSFabric *xi)
{
PnvMachineState *pnv = POWERNV_MACHINE(xi);
- int i;
+ int i, j;
for (i = 0; i < pnv->num_chips; i++) {
ics_resend(&pnv->chips[i]->psi.ics);
+ for (j = 0; j < pnv->chips[i]->num_phbs; j++) {
+ ics_resend(pnv->chips[i]->phbs[j]->lsi_ics);
+ ics_resend(ICS_BASE(pnv->chips[i]->phbs[j]->msis));
+ }
}
}
@@ -1082,7 +1148,7 @@ static void pnv_pic_print_info(InterruptStatsProvider *obj,
Monitor *mon)
{
PnvMachineState *pnv = POWERNV_MACHINE(obj);
- int i;
+ int i, j;
CPUState *cs;
CPU_FOREACH(cs) {
@@ -1093,6 +1159,10 @@ static void pnv_pic_print_info(InterruptStatsProvider *obj,
for (i = 0; i < pnv->num_chips; i++) {
ics_pic_print_info(&pnv->chips[i]->psi.ics, mon);
+ for (j = 0; j < pnv->chips[i]->num_phbs; j++) {
+ ics_pic_print_info(pnv->chips[i]->phbs[j]->lsi_ics, mon);
+ ics_pic_print_info(ICS_BASE(pnv->chips[i]->phbs[j]->msis), mon);
+ }
}
}
diff --git a/hw/ppc/pnv_xscom.c b/hw/ppc/pnv_xscom.c
index 38bc85f117f6..a75e6c95b885 100644
--- a/hw/ppc/pnv_xscom.c
+++ b/hw/ppc/pnv_xscom.c
@@ -255,7 +255,10 @@ int pnv_xscom_populate(PnvChip *chip, void *fdt, int root_offset)
args.fdt = fdt;
args.xscom_offset = xscom_offset;
- object_child_foreach(OBJECT(chip), xscom_populate_child, &args);
+ /* Some PnvXScomInterface objects lie a bit deeper (PnvPBCQState)
+ * than the first layer, so we need to loop on the whole object
+ * hierarchy to catch them */
+ object_child_foreach_recursive(OBJECT(chip), xscom_populate_child, &args);
return 0;
}
diff --git a/include/hw/pci-host/pnv_phb3.h b/include/hw/pci-host/pnv_phb3.h
new file mode 100644
index 000000000000..ef7cdf6b2089
--- /dev/null
+++ b/include/hw/pci-host/pnv_phb3.h
@@ -0,0 +1,156 @@
+/*
+ * QEMU PowerPC PowerNV PHB3 model
+ *
+ * Copyright (c) 2014-2017, IBM Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef PCI_HOST_PNV_PHB3_H
+#define PCI_HOST_PNV_PHB3_H
+
+#include "hw/pci/pci_host.h"
+#include "hw/ppc/xics.h"
+#include "hw/pci-host/pnv_phb3_regs.h"
+
+#define PNV_PHB3_NUM_M64 16
+#define PNV_PHB3_NUM_REGS (0x1000 >> 3)
+#define PNV_PHB3_NUM_LSI 8
+#define PNV_PHB3_NUM_PE 256
+
+#define PCI_MMIO_TOTAL_SIZE (0x1ull << 60)
+
+#define IODA2_PCI_BUS_MAX 256
+
+typedef struct PnvPBCQState PnvPBCQState;
+typedef struct PnvPhb3State PnvPhb3State;
+typedef struct PnvPhb3DMASpace PnvPhb3DMASpace;
+
+/* Similarily with pnv_phb3_msi */
+typedef struct Phb3MsiState Phb3MsiState;
+
+/* We have one such address space wrapper per possible device
+ * under the PHB since they need to be assigned statically at
+ * qemu device creation time. The relationship to a PE is done
+ * later dynamically. This means we can potentially create a lot
+ * of these guys. Q35 stores them as some kind of radix tree but
+ * we never really need to do fast lookups so instead we simply
+ * keep a QLIST of them for now, we can add the radix if needed
+ * later on.
+ *
+ * We do cache the PE number to speed things up a bit though.
+ */
+struct PnvPhb3DMASpace {
+ PCIBus *bus;
+ uint8_t devfn;
+ int pe_num; /* Cached PE number */
+#define PHB_INVALID_PE (-1)
+ PnvPhb3State *phb;
+ AddressSpace dma_as;
+ MemoryRegion dma_mr;
+ MemoryRegion msi32_mr;
+ MemoryRegion msi64_mr;
+ bool msi32_mapped;
+ bool msi64_mapped;
+ QLIST_ENTRY(PnvPhb3DMASpace) list;
+};
+
+struct PnvPhb3State {
+ PCIHostState parent_obj;
+
+ uint32_t chip_id;
+ uint32_t phb_id;
+ MemoryRegion mr_m32;
+ MemoryRegion mr_m64[PNV_PHB3_NUM_M64];
+ MemoryRegion mr_regs;
+ bool regs_mapped;
+ bool m32_mapped;
+ bool m64_mapped[PNV_PHB3_NUM_M64];
+ MemoryRegion pci_mmio;
+ MemoryRegion pci_io;
+ uint64_t regs[PNV_PHB3_NUM_REGS];
+ PnvPBCQState *pbcq;
+ uint64_t ioda_LIST[8];
+ uint64_t ioda_LXIVT[8];
+ uint64_t ioda_TVT[512];
+ uint64_t ioda_M64BT[16];
+ uint64_t ioda_MDT[256];
+ uint64_t ioda_PEEV[4];
+ uint32_t total_irq;
+ ICSState *lsi_ics;
+ Phb3MsiState *msis;
+ QLIST_HEAD(, PnvPhb3DMASpace) dma_spaces;
+};
+
+struct PnvPBCQState {
+ DeviceState parent;
+
+ uint32_t chip_id;
+ uint32_t phb_id;
+ uint32_t nest_xbase;
+ uint32_t spci_xbase;
+ uint32_t pci_xbase;
+ uint64_t nest_regs[PBCQ_NEST_REGS_COUNT];
+ uint64_t spci_regs[PBCQ_SPCI_REGS_COUNT];
+ uint64_t pci_regs[PBCQ_PCI_REGS_COUNT];
+ MemoryRegion mmbar0;
+ MemoryRegion mmbar1;
+ MemoryRegion phbbar;
+ bool mmio0_mapped;
+ bool mmio1_mapped;
+ bool phb_mapped;
+ uint64_t mmio0_base;
+ uint64_t mmio0_size;
+ uint64_t mmio1_base;
+ uint64_t mmio1_size;
+ PnvPhb3State *phb;
+
+ MemoryRegion xscom_nest_regs;
+ MemoryRegion xscom_pci_regs;
+ MemoryRegion xscom_spci_regs;
+};
+
+#define TYPE_PNV_PBCQ "pnv-pbcq"
+#define PNV_PBCQ(obj) \
+ OBJECT_CHECK(PnvPBCQState, (obj), TYPE_PNV_PBCQ)
+
+
+#define TYPE_PNV_PHB3 "pnv-phb3"
+#define PNV_PHB3(obj) \
+ OBJECT_CHECK(PnvPhb3State, (obj), TYPE_PNV_PHB3)
+
+#define TYPE_PNV_PHB3_RC "pnv-phb3-rc"
+
+#define PHB3_MAX_MSI 2048
+
+typedef struct Phb3MsiState {
+ ICSState ics;
+ PnvPhb3State *phb;
+ uint64_t rba[PHB3_MAX_MSI / 64];
+ uint32_t rba_sum;
+} Phb3MsiState;
+
+#define TYPE_PHB3_MSI "phb3-msi"
+#define PHB3_MSI(obj) OBJECT_CHECK(Phb3MsiState, (obj), TYPE_PHB3_MSI)
+
+uint64_t pnv_phb3_reg_read(void *opaque, hwaddr off, unsigned size);
+void pnv_phb3_reg_write(void *opaque, hwaddr off, uint64_t val, unsigned size);
+void pnv_phb3_update_regions(PnvPhb3State *phb);
+void pnv_phb3_remap_irqs(PnvPhb3State *phb);
+void pnv_phb3_msi_update_config(Phb3MsiState *msis, uint32_t base,
+ uint32_t count);
+void pnv_phb3_msi_send(Phb3MsiState *msis, uint64_t addr, uint16_t data,
+ int32_t dev_pe);
+void pnv_phb3_msi_ffi(Phb3MsiState *msis, uint64_t val);
+
+#endif /* PCI_HOST_PNV_PHB3_H */
diff --git a/include/hw/pci-host/pnv_phb3_regs.h b/include/hw/pci-host/pnv_phb3_regs.h
new file mode 100644
index 000000000000..4c3187434355
--- /dev/null
+++ b/include/hw/pci-host/pnv_phb3_regs.h
@@ -0,0 +1,506 @@
+/* Copyright (c) 2013-2017, IBM Corporation.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ * implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef PCI_HOST_PNV_PHB3_REGS_H
+#define PCI_HOST_PNV_PHB3_REGS_H
+
+#define PPC_BIT(bit) (0x8000000000000000UL >> (bit))
+#define PPC_BIT32(bit) (0x80000000UL >> (bit))
+#define PPC_BIT8(bit) (0x80UL >> (bit))
+#define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
+#define PPC_BITMASK32(bs, be) ((PPC_BIT32(bs) - PPC_BIT32(be)) | \
+ PPC_BIT32(bs))
+#define PPC_BITLSHIFT(be) (63 - (be))
+#define PPC_BITLSHIFT32(be) (31 - (be))
+
+/* Extract field fname from val */
+#define GETFIELD(fname, val) \
+ (((val) & fname##_MASK) >> fname##_LSH)
+
+/* Set field fname of oval to fval
+ * NOTE: oval isn't modified, the combined result is returned
+ */
+#define SETFIELD(fname, oval, fval) \
+ (((oval) & ~fname##_MASK) | \
+ ((((typeof(oval))(fval)) << fname##_LSH) & fname##_MASK))
+
+/*
+ * PBCQ XSCOM registers
+ */
+
+#define PBCQ_NEST_IRSN_COMPARE 0x1a
+#define PBCQ_NEST_IRSN_COMP_MASK PPC_BITMASK(0, 18)
+#define PBCQ_NEST_IRSN_COMP_LSH PPC_BITLSHIFT(18)
+#define PBCQ_NEST_IRSN_MASK 0x1b
+#define PBCQ_NEST_LSI_SRC_ID 0x1f
+#define PBCQ_NEST_LSI_SRC_MASK PPC_BITMASK(0, 7)
+#define PBCQ_NEST_LSI_SRC_LSH PPC_BITLSHIFT(7)
+#define PBCQ_NEST_REGS_COUNT 0x46
+#define PBCQ_NEST_MMIO_BAR0 0x40
+#define PBCQ_NEST_MMIO_BAR1 0x41
+#define PBCQ_NEST_PHB_BAR 0x42
+#define PBCQ_NEST_MMIO_MASK0 0x43
+#define PBCQ_NEST_MMIO_MASK1 0x44
+#define PBCQ_NEST_BAR_EN 0x45
+#define PBCQ_NEST_BAR_EN_MMIO0 PPC_BIT(0)
+#define PBCQ_NEST_BAR_EN_MMIO1 PPC_BIT(1)
+#define PBCQ_NEST_BAR_EN_PHB PPC_BIT(2)
+#define PBCQ_NEST_BAR_EN_IRSN_RX PPC_BIT(3)
+#define PBCQ_NEST_BAR_EN_IRSN_TX PPC_BIT(4)
+
+#define PBCQ_PCI_REGS_COUNT 0x15
+#define PBCQ_PCI_BAR2 0x0b
+
+#define PBCQ_SPCI_REGS_COUNT 0x5
+#define PBCQ_SPCI_ASB_ADDR 0x0
+#define PBCQ_SPCI_ASB_STATUS 0x1
+#define PBCQ_SPCI_ASB_DATA 0x2
+#define PBCQ_SPCI_AIB_CAPP_EN 0x3
+#define PBCQ_SPCI_CAPP_SEC_TMR 0x4
+
+/*
+ * PHB MMIO registers
+ */
+
+/* PHB Fundamental register set A */
+#define PHB_LSI_SOURCE_ID 0x100
+#define PHB_LSI_SRC_ID_MASK PPC_BITMASK(5, 12)
+#define PHB_LSI_SRC_ID_LSH PPC_BITLSHIFT(12)
+#define PHB_DMA_CHAN_STATUS 0x110
+#define PHB_DMA_CHAN_ANY_ERR PPC_BIT(27)
+#define PHB_DMA_CHAN_ANY_ERR1 PPC_BIT(28)
+#define PHB_DMA_CHAN_ANY_FREEZE PPC_BIT(29)
+#define PHB_CPU_LOADSTORE_STATUS 0x120
+#define PHB_CPU_LS_ANY_ERR PPC_BIT(27)
+#define PHB_CPU_LS_ANY_ERR1 PPC_BIT(28)
+#define PHB_CPU_LS_ANY_FREEZE PPC_BIT(29)
+#define PHB_DMA_MSI_NODE_ID 0x128
+#define PHB_DMAMSI_NID_FIXED PPC_BIT(0)
+#define PHB_DMAMSI_NID_MASK PPC_BITMASK(24, 31)
+#define PHB_DMAMSI_NID_LSH PPC_BITLSHIFT(31)
+#define PHB_CONFIG_DATA 0x130
+#define PHB_LOCK0 0x138
+#define PHB_CONFIG_ADDRESS 0x140
+#define PHB_CA_ENABLE PPC_BIT(0)
+#define PHB_CA_BUS_MASK PPC_BITMASK(4, 11)
+#define PHB_CA_BUS_LSH PPC_BITLSHIFT(11)
+#define PHB_CA_DEV_MASK PPC_BITMASK(12, 16)
+#define PHB_CA_DEV_LSH PPC_BITLSHIFT(16)
+#define PHB_CA_FUNC_MASK PPC_BITMASK(17, 19)
+#define PHB_CA_FUNC_LSH PPC_BITLSHIFT(19)
+#define PHB_CA_REG_MASK PPC_BITMASK(20, 31)
+#define PHB_CA_REG_LSH PPC_BITLSHIFT(31)
+#define PHB_CA_PE_MASK PPC_BITMASK(40, 47)
+#define PHB_CA_PE_LSH PPC_BITLSHIFT(47)
+#define PHB_LOCK1 0x148
+#define PHB_IVT_BAR 0x150
+#define PHB_IVT_BAR_ENABLE PPC_BIT(0)
+#define PHB_IVT_BASE_ADDRESS_MASK PPC_BITMASK(14, 48)
+#define PHB_IVT_BASE_ADDRESS_LSH PPC_BITLSHIFT(48)
+#define PHB_IVT_LENGTH_MASK PPC_BITMASK(52, 63)
+#define PHB_IVT_LENGTH_ADDRESS_LSH PPC_BITLSHIFT(63)
+#define PHB_RBA_BAR 0x158
+#define PHB_RBA_BAR_ENABLE PPC_BIT(0)
+#define PHB_RBA_BASE_ADDRESS_MASK PPC_BITMASK(14, 55)
+#define PHB_RBA_BASE_ADDRESS_LSH PPC_BITLSHIFT(55)
+#define PHB_PHB3_CONFIG 0x160
+#define PHB_PHB3C_64B_TCE_EN PPC_BIT(2)
+#define PHB_PHB3C_32BIT_MSI_EN PPC_BIT(8)
+#define PHB_PHB3C_64BIT_MSI_EN PPC_BIT(14)
+#define PHB_PHB3C_M32_EN PPC_BIT(16)
+#define PHB_RTT_BAR 0x168
+#define PHB_RTT_BAR_ENABLE PPC_BIT(0)
+#define PHB_RTT_BASE_ADDRESS_MASK PPC_BITMASK(14, 46)
+#define PHB_RTT_BASE_ADDRESS_LSH PPC_BITLSHIFT(46)
+#define PHB_PELTV_BAR 0x188
+#define PHB_PELTV_BAR_ENABLE PPC_BIT(0)
+#define PHB_PELTV_BASE_ADDRESS_MASK PPC_BITMASK(14, 50)
+#define PHB_PELTV_BASE_ADDRESS_LSH PPC_BITLSHIFT(50)
+#define PHB_M32_BASE_ADDR 0x190
+#define PHB_M32_BASE_MASK 0x198
+#define PHB_M32_START_ADDR 0x1a0
+#define PHB_PEST_BAR 0x1a8
+#define PHB_PEST_BAR_ENABLE PPC_BIT(0)
+#define PHB_PEST_BASE_ADDRESS_MASK PPC_BITMASK(14, 51)
+#define PHB_PEST_BASE_ADDRESS_LSH PPC_BITLSHIFT(51)
+#define PHB_M64_UPPER_BITS 0x1f0
+#define PHB_INTREP_TIMER 0x1f8
+#define PHB_DMARD_SYNC 0x200
+#define PHB_RTC_INVALIDATE 0x208
+#define PHB_RTC_INVALIDATE_ALL PPC_BIT(0)
+#define PHB_RTC_INVALIDATE_RID_MASK PPC_BITMASK(16, 31)
+#define PHB_RTC_INVALIDATE_RID_LSH PPC_BITLSHIFT(31)
+#define PHB_TCE_KILL 0x210
+#define PHB_TCE_KILL_ALL PPC_BIT(0)
+#define PHB_TCE_SPEC_CTL 0x218
+#define PHB_IODA_ADDR 0x220
+#define PHB_IODA_AD_AUTOINC PPC_BIT(0)
+#define PHB_IODA_AD_TSEL_MASK PPC_BITMASK(11, 15)
+#define PHB_IODA_AD_TSEL_LSH PPC_BITLSHIFT(15)
+#define PHB_IODA_AD_TADR_MASK PPC_BITMASK(55, 63)
+#define PHB_IODA_AD_TADR_LSH PPC_BITLSHIFT(63)
+#define PHB_IODA_DATA0 0x228
+#define PHB_FFI_REQUEST 0x238
+#define PHB_FFI_LOCK_CLEAR PPC_BIT(3)
+#define PHB_FFI_REQUEST_ISN_MASK PPC_BITMASK(49, 59)
+#define PHB_FFI_REQUEST_ISN_LSH PPC_BITLSHIFT(59)
+#define PHB_FFI_LOCK 0x240
+#define PHB_FFI_LOCK_STATE PPC_BIT(0)
+#define PHB_XIVE_UPDATE 0x248 /* Broken in DD1 */
+#define PHB_PHB3_GEN_CAP 0x250
+#define PHB_PHB3_TCE_CAP 0x258
+#define PHB_PHB3_IRQ_CAP 0x260
+#define PHB_PHB3_EEH_CAP 0x268
+#define PHB_IVC_INVALIDATE 0x2a0
+#define PHB_IVC_INVALIDATE_ALL PPC_BIT(0)
+#define PHB_IVC_INVALIDATE_SID_MASK PPC_BITMASK(16, 31)
+#define PHB_IVC_INVALIDATE_SID_LSH PPC_BITLSHIFT(31)
+#define PHB_IVC_UPDATE 0x2a8
+#define PHB_IVC_UPDATE_ENABLE_P PPC_BIT(0)
+#define PHB_IVC_UPDATE_ENABLE_Q PPC_BIT(1)
+#define PHB_IVC_UPDATE_ENABLE_SERVER PPC_BIT(2)
+#define PHB_IVC_UPDATE_ENABLE_PRI PPC_BIT(3)
+#define PHB_IVC_UPDATE_ENABLE_GEN PPC_BIT(4)
+#define PHB_IVC_UPDATE_ENABLE_CON PPC_BIT(5)
+#define PHB_IVC_UPDATE_GEN_MATCH_MASK PPC_BITMASK(6, 7)
+#define PHB_IVC_UPDATE_GEN_MATCH_LSH PPC_BITLSHIFT(7)
+#define PHB_IVC_UPDATE_SERVER_MASK PPC_BITMASK(8, 23)
+#define PHB_IVC_UPDATE_SERVER_LSH PPC_BITLSHIFT(23)
+#define PHB_IVC_UPDATE_PRI_MASK PPC_BITMASK(24, 31)
+#define PHB_IVC_UPDATE_PRI_LSH PPC_BITLSHIFT(31)
+#define PHB_IVC_UPDATE_GEN_MASK PPC_BITMASK(32, 33)
+#define PHB_IVC_UPDATE_GEN_LSH PPC_BITLSHIFT(33)
+#define PHB_IVC_UPDATE_P_MASK PPC_BITMASK(34, 34)
+#define PHB_IVC_UPDATE_P_LSH PPC_BITLSHIFT(34)
+#define PHB_IVC_UPDATE_Q_MASK PPC_BITMASK(35, 35)
+#define PHB_IVC_UPDATE_Q_LSH PPC_BITLSHIFT(35)
+#define PHB_IVC_UPDATE_SID_MASK PPC_BITMASK(48, 63)
+#define PHB_IVC_UPDATE_SID_LSH PPC_BITLSHIFT(63)
+#define PHB_PAPR_ERR_INJ_CTL 0x2b0
+#define PHB_PAPR_ERR_INJ_CTL_INB PPC_BIT(0)
+#define PHB_PAPR_ERR_INJ_CTL_OUTB PPC_BIT(1)
+#define PHB_PAPR_ERR_INJ_CTL_STICKY PPC_BIT(2)
+#define PHB_PAPR_ERR_INJ_CTL_CFG PPC_BIT(3)
+#define PHB_PAPR_ERR_INJ_CTL_RD PPC_BIT(4)
+#define PHB_PAPR_ERR_INJ_CTL_WR PPC_BIT(5)
+#define PHB_PAPR_ERR_INJ_CTL_FREEZE PPC_BIT(6)
+#define PHB_PAPR_ERR_INJ_ADDR 0x2b8
+#define PHB_PAPR_ERR_INJ_ADDR_MMIO_MASK PPC_BITMASK(16, 63)
+#define PHB_PAPR_ERR_INJ_ADDR_MMIO_LSH PPC_BITLSHIFT(63)
+#define PHB_PAPR_ERR_INJ_MASK 0x2c0
+#define PHB_PAPR_ERR_INJ_MASK_CFG_MASK PPC_BITMASK(4, 11)
+#define PHB_PAPR_ERR_INJ_MASK_CFG_LSH PPC_BITLSHIFT(11)
+#define PHB_PAPR_ERR_INJ_MASK_MMIO_MASK PPC_BITMASK(16, 63)
+#define PHB_PAPR_ERR_INJ_MASK_MMIO_LSH PPC_BITLSHIFT(63)
+#define PHB_ETU_ERR_SUMMARY 0x2c8
+
+/* UTL registers */
+#define UTL_SYS_BUS_CONTROL 0x400
+#define UTL_STATUS 0x408
+#define UTL_SYS_BUS_AGENT_STATUS 0x410
+#define UTL_SYS_BUS_AGENT_ERR_SEVERITY 0x418
+#define UTL_SYS_BUS_AGENT_IRQ_EN 0x420
+#define UTL_SYS_BUS_BURST_SZ_CONF 0x440
+#define UTL_REVISION_ID 0x448
+#define UTL_BCLK_DOMAIN_DBG1 0x460
+#define UTL_BCLK_DOMAIN_DBG2 0x468
+#define UTL_BCLK_DOMAIN_DBG3 0x470
+#define UTL_BCLK_DOMAIN_DBG4 0x478
+#define UTL_BCLK_DOMAIN_DBG5 0x480
+#define UTL_BCLK_DOMAIN_DBG6 0x488
+#define UTL_OUT_POST_HDR_BUF_ALLOC 0x4c0
+#define UTL_OUT_POST_DAT_BUF_ALLOC 0x4d0
+#define UTL_IN_POST_HDR_BUF_ALLOC 0x4e0
+#define UTL_IN_POST_DAT_BUF_ALLOC 0x4f0
+#define UTL_OUT_NP_BUF_ALLOC 0x500
+#define UTL_IN_NP_BUF_ALLOC 0x510
+#define UTL_PCIE_TAGS_ALLOC 0x520
+#define UTL_GBIF_READ_TAGS_ALLOC 0x530
+#define UTL_PCIE_PORT_CONTROL 0x540
+#define UTL_PCIE_PORT_STATUS 0x548
+#define UTL_PCIE_PORT_ERROR_SEV 0x550
+#define UTL_PCIE_PORT_IRQ_EN 0x558
+#define UTL_RC_STATUS 0x560
+#define UTL_RC_ERR_SEVERITY 0x568
+#define UTL_RC_IRQ_EN 0x570
+#define UTL_EP_STATUS 0x578
+#define UTL_EP_ERR_SEVERITY 0x580
+#define UTL_EP_ERR_IRQ_EN 0x588
+#define UTL_PCI_PM_CTRL1 0x590
+#define UTL_PCI_PM_CTRL2 0x598
+#define UTL_GP_CTL1 0x5a0
+#define UTL_GP_CTL2 0x5a8
+#define UTL_PCLK_DOMAIN_DBG1 0x5b0
+#define UTL_PCLK_DOMAIN_DBG2 0x5b8
+#define UTL_PCLK_DOMAIN_DBG3 0x5c0
+#define UTL_PCLK_DOMAIN_DBG4 0x5c8
+
+/* PCI-E Stack registers */
+#define PHB_PCIE_SYSTEM_CONFIG 0x600
+#define PHB_PCIE_BUS_NUMBER 0x608
+#define PHB_PCIE_SYSTEM_TEST 0x618
+#define PHB_PCIE_LINK_MANAGEMENT 0x630
+#define PHB_PCIE_LM_LINK_ACTIVE PPC_BIT(8)
+#define PHB_PCIE_DLP_TRAIN_CTL 0x640
+#define PHB_PCIE_DLP_TCTX_DISABLE PPC_BIT(1)
+#define PHB_PCIE_DLP_TCRX_DISABLED PPC_BIT(16)
+#define PHB_PCIE_DLP_INBAND_PRESENCE PPC_BIT(19)
+#define PHB_PCIE_DLP_TC_DL_LINKUP PPC_BIT(21)
+#define PHB_PCIE_DLP_TC_DL_PGRESET PPC_BIT(22)
+#define PHB_PCIE_DLP_TC_DL_LINKACT PPC_BIT(23)
+#define PHB_PCIE_SLOP_LOOPBACK_STATUS 0x648
+#define PHB_PCIE_SYS_LINK_INIT 0x668
+#define PHB_PCIE_UTL_CONFIG 0x670
+#define PHB_PCIE_DLP_CONTROL 0x678
+#define PHB_PCIE_UTL_ERRLOG1 0x680
+#define PHB_PCIE_UTL_ERRLOG2 0x688
+#define PHB_PCIE_UTL_ERRLOG3 0x690
+#define PHB_PCIE_UTL_ERRLOG4 0x698
+#define PHB_PCIE_DLP_ERRLOG1 0x6a0
+#define PHB_PCIE_DLP_ERRLOG2 0x6a8
+#define PHB_PCIE_DLP_ERR_STATUS 0x6b0
+#define PHB_PCIE_DLP_ERR_COUNTERS 0x6b8
+#define PHB_PCIE_UTL_ERR_INJECT 0x6c0
+#define PHB_PCIE_TLDLP_ERR_INJECT 0x6c8
+#define PHB_PCIE_LANE_EQ_CNTL0 0x6d0
+#define PHB_PCIE_LANE_EQ_CNTL1 0x6d8
+#define PHB_PCIE_LANE_EQ_CNTL2 0x6e0
+#define PHB_PCIE_LANE_EQ_CNTL3 0x6e8
+#define PHB_PCIE_STRAPPING 0x700
+
+/* Fundamental register set B */
+#define PHB_VERSION 0x800
+#define PHB_RESET 0x808
+#define PHB_CONTROL 0x810
+#define PHB_CTRL_IVE_128_BYTES PPC_BIT(24)
+#define PHB_AIB_RX_CRED_INIT_TIMER 0x818
+#define PHB_AIB_RX_CMD_CRED 0x820
+#define PHB_AIB_RX_DATA_CRED 0x828
+#define PHB_AIB_TX_CMD_CRED 0x830
+#define PHB_AIB_TX_DATA_CRED 0x838
+#define PHB_AIB_TX_CHAN_MAPPING 0x840
+#define PHB_AIB_TAG_ENABLE 0x858
+#define PHB_AIB_FENCE_CTRL 0x860
+#define PHB_TCE_TAG_ENABLE 0x868
+#define PHB_TCE_WATERMARK 0x870
+#define PHB_TIMEOUT_CTRL1 0x878
+#define PHB_TIMEOUT_CTRL2 0x880
+#define PHB_QUIESCE_DMA_G 0x888
+#define PHB_AIB_TAG_STATUS 0x900
+#define PHB_TCE_TAG_STATUS 0x908
+
+/* FIR & Error registers */
+#define PHB_LEM_FIR_ACCUM 0xc00
+#define PHB_LEM_FIR_AND_MASK 0xc08
+#define PHB_LEM_FIR_OR_MASK 0xc10
+#define PHB_LEM_ERROR_MASK 0xc18
+#define PHB_LEM_ERROR_AND_MASK 0xc20
+#define PHB_LEM_ERROR_OR_MASK 0xc28
+#define PHB_LEM_ACTION0 0xc30
+#define PHB_LEM_ACTION1 0xc38
+#define PHB_LEM_WOF 0xc40
+#define PHB_ERR_STATUS 0xc80
+#define PHB_ERR1_STATUS 0xc88
+#define PHB_ERR_INJECT 0xc90
+#define PHB_ERR_LEM_ENABLE 0xc98
+#define PHB_ERR_IRQ_ENABLE 0xca0
+#define PHB_ERR_FREEZE_ENABLE 0xca8
+#define PHB_ERR_AIB_FENCE_ENABLE 0xcb0
+#define PHB_ERR_LOG_0 0xcc0
+#define PHB_ERR_LOG_1 0xcc8
+#define PHB_ERR_STATUS_MASK 0xcd0
+#define PHB_ERR1_STATUS_MASK 0xcd8
+
+#define PHB_OUT_ERR_STATUS 0xd00
+#define PHB_OUT_ERR1_STATUS 0xd08
+#define PHB_OUT_ERR_INJECT 0xd10
+#define PHB_OUT_ERR_LEM_ENABLE 0xd18
+#define PHB_OUT_ERR_IRQ_ENABLE 0xd20
+#define PHB_OUT_ERR_FREEZE_ENABLE 0xd28
+#define PHB_OUT_ERR_AIB_FENCE_ENABLE 0xd30
+#define PHB_OUT_ERR_LOG_0 0xd40
+#define PHB_OUT_ERR_LOG_1 0xd48
+#define PHB_OUT_ERR_STATUS_MASK 0xd50
+#define PHB_OUT_ERR1_STATUS_MASK 0xd58
+
+#define PHB_INA_ERR_STATUS 0xd80
+#define PHB_INA_ERR1_STATUS 0xd88
+#define PHB_INA_ERR_INJECT 0xd90
+#define PHB_INA_ERR_LEM_ENABLE 0xd98
+#define PHB_INA_ERR_IRQ_ENABLE 0xda0
+#define PHB_INA_ERR_FREEZE_ENABLE 0xda8
+#define PHB_INA_ERR_AIB_FENCE_ENABLE 0xdb0
+#define PHB_INA_ERR_LOG_0 0xdc0
+#define PHB_INA_ERR_LOG_1 0xdc8
+#define PHB_INA_ERR_STATUS_MASK 0xdd0
+#define PHB_INA_ERR1_STATUS_MASK 0xdd8
+
+#define PHB_INB_ERR_STATUS 0xe00
+#define PHB_INB_ERR1_STATUS 0xe08
+#define PHB_INB_ERR_INJECT 0xe10
+#define PHB_INB_ERR_LEM_ENABLE 0xe18
+#define PHB_INB_ERR_IRQ_ENABLE 0xe20
+#define PHB_INB_ERR_FREEZE_ENABLE 0xe28
+#define PHB_INB_ERR_AIB_FENCE_ENABLE 0xe30
+#define PHB_INB_ERR_LOG_0 0xe40
+#define PHB_INB_ERR_LOG_1 0xe48
+#define PHB_INB_ERR_STATUS_MASK 0xe50
+#define PHB_INB_ERR1_STATUS_MASK 0xe58
+
+/* Performance monitor & Debug registers */
+#define PHB_TRACE_CONTROL 0xf80
+#define PHB_PERFMON_CONFIG 0xf88
+#define PHB_PERFMON_CTR0 0xf90
+#define PHB_PERFMON_CTR1 0xf98
+#define PHB_PERFMON_CTR2 0xfa0
+#define PHB_PERFMON_CTR3 0xfa8
+#define PHB_HOTPLUG_OVERRIDE 0xfb0
+#define PHB_HPOVR_FORCE_RESAMPLE PPC_BIT(9)
+#define PHB_HPOVR_PRESENCE_A PPC_BIT(10)
+#define PHB_HPOVR_PRESENCE_B PPC_BIT(11)
+#define PHB_HPOVR_LINK_ACTIVE PPC_BIT(12)
+#define PHB_HPOVR_LINK_BIFURCATED PPC_BIT(13)
+#define PHB_HPOVR_LINK_LANE_SWAPPED PPC_BIT(14)
+
+/*
+ * IODA2 on-chip tables
+ */
+
+#define IODA2_TBL_LIST 1
+#define IODA2_TBL_LXIVT 2
+#define IODA2_TBL_IVC_CAM 3
+#define IODA2_TBL_RBA 4
+#define IODA2_TBL_RCAM 5
+#define IODA2_TBL_MRT 6
+#define IODA2_TBL_PESTA 7
+#define IODA2_TBL_PESTB 8
+#define IODA2_TBL_TVT 9
+#define IODA2_TBL_TCAM 10
+#define IODA2_TBL_TDR 11
+#define IODA2_TBL_M64BT 16
+#define IODA2_TBL_M32DT 17
+#define IODA2_TBL_PEEV 20
+
+/* LXIVT */
+#define IODA2_LXIVT_SERVER_MASK PPC_BITMASK(8, 23)
+#define IODA2_LXIVT_SERVER_LSH PPC_BITLSHIFT(23)
+#define IODA2_LXIVT_PRIORITY_MASK PPC_BITMASK(24, 31)
+#define IODA2_LXIVT_PRIORITY_LSH PPC_BITLSHIFT(31)
+#define IODA2_LXIVT_NODE_ID_MASK PPC_BITMASK(56, 63)
+#define IODA2_LXIVT_NODE_ID_LSH PPC_BITLSHIFT(63)
+
+/* IVT */
+#define IODA2_IVT_SERVER_MASK PPC_BITMASK(0, 23)
+#define IODA2_IVT_SERVER_LSH PPC_BITLSHIFT(23)
+#define IODA2_IVT_PRIORITY_MASK PPC_BITMASK(24, 31)
+#define IODA2_IVT_PRIORITY_LSH PPC_BITLSHIFT(31)
+#define IODA2_IVT_GEN_MASK PPC_BITMASK(37, 38)
+#define IODA2_IVT_GEN_LSH PPC_BITLSHIFT(38)
+#define IODA2_IVT_P_MASK PPC_BITMASK(39, 39)
+#define IODA2_IVT_P_LSH PPC_BITLSHIFT(39)
+#define IODA2_IVT_Q_MASK PPC_BITMASK(47, 47)
+#define IODA2_IVT_Q_LSH PPC_BITLSHIFT(47)
+#define IODA2_IVT_PE_MASK PPC_BITMASK(48, 63)
+#define IODA2_IVT_PE_LSH PPC_BITLSHIFT(63)
+
+/* TVT */
+#define IODA2_TVT_TABLE_ADDR_MASK PPC_BITMASK(0, 47)
+#define IODA2_TVT_TABLE_ADDR_LSH PPC_BITLSHIFT(47)
+#define IODA2_TVT_NUM_LEVELS_MASK PPC_BITMASK(48, 50)
+#define IODA2_TVT_NUM_LEVELS_LSH PPC_BITLSHIFT(50)
+#define IODA2_TVE_1_LEVEL 0
+#define IODA2_TVE_2_LEVELS 1
+#define IODA2_TVE_3_LEVELS 2
+#define IODA2_TVE_4_LEVELS 3
+#define IODA2_TVE_5_LEVELS 4
+#define IODA2_TVT_TCE_TABLE_SIZE_MASK PPC_BITMASK(51, 55)
+#define IODA2_TVT_TCE_TABLE_SIZE_LSH PPC_BITLSHIFT(55)
+#define IODA2_TVT_IO_PSIZE_MASK PPC_BITMASK(59, 63)
+#define IODA2_TVT_IO_PSIZE_LSH PPC_BITLSHIFT(63)
+
+/* PESTA */
+#define IODA2_PESTA_MMIO_FROZEN PPC_BIT(0)
+
+/* PESTB */
+#define IODA2_PESTB_DMA_STOPPED PPC_BIT(0)
+
+/* M32DT */
+#define IODA2_M32DT_PE_MASK PPC_BITMASK(8, 15)
+#define IODA2_M32DT_PE_LSH PPC_BITLSHIFT(15)
+
+/* M64BT */
+#define IODA2_M64BT_ENABLE PPC_BIT(0)
+#define IODA2_M64BT_SINGLE_PE PPC_BIT(1)
+#define IODA2_M64BT_BASE_MASK PPC_BITMASK(2, 31)
+#define IODA2_M64BT_BASE_LSH PPC_BITLSHIFT(31)
+#define IODA2_M64BT_MASK_MASK PPC_BITMASK(34, 63)
+#define IODA2_M64BT_MASK_LSH PPC_BITLSHIFT(63)
+#define IODA2_M64BT_SINGLE_BASE_MASK PPC_BITMASK(2, 26)
+#define IODA2_M64BT_SINGLE_BASE_LSH PPC_BITLSHIFT(26)
+#define IODA2_M64BT_PE_HI_MASK PPC_BITMASK(27, 31)
+#define IODA2_M64BT_PE_HI_LSH PPC_BITLSHIFT(31)
+#define IODA2_M64BT_SINGLE_MASK_MASK PPC_BITMASK(34, 58)
+#define IODA2_M64BT_SINGLE_MASK_LSH PPC_BITLSHIFT(58)
+#define IODA2_M64BT_PE_LOW_MASK PPC_BITMASK(59, 63)
+#define IODA2_M64BT_PE_LOW_LSH PPC_BITLSHIFT(63)
+
+/*
+ * IODA2 in-memory tables
+ */
+
+/* PEST
+ *
+ * 2x8 bytes entries, PEST0 and PEST1
+ */
+
+#define IODA2_PEST0_MMIO_CAUSE PPC_BIT(2)
+#define IODA2_PEST0_CFG_READ PPC_BIT(3)
+#define IODA2_PEST0_CFG_WRITE PPC_BIT(4)
+#define IODA2_PEST0_TTYPE_MASK PPC_BITMASK(5, 7)
+#define IODA2_PEST0_TTYPE_LSH PPC_BITLSHIFT(7)
+#define PEST_TTYPE_DMA_WRITE 0
+#define PEST_TTYPE_MSI 1
+#define PEST_TTYPE_DMA_READ 2
+#define PEST_TTYPE_DMA_READ_RESP 3
+#define PEST_TTYPE_MMIO_LOAD 4
+#define PEST_TTYPE_MMIO_STORE 5
+#define PEST_TTYPE_OTHER 7
+#define IODA2_PEST0_CA_RETURN PPC_BIT(8)
+#define IODA2_PEST0_UTL_RTOS_TIMEOUT PPC_BIT(8) /* Same bit as CA return */
+#define IODA2_PEST0_UR_RETURN PPC_BIT(9)
+#define IODA2_PEST0_UTL_NONFATAL PPC_BIT(10)
+#define IODA2_PEST0_UTL_FATAL PPC_BIT(11)
+#define IODA2_PEST0_PARITY_UE PPC_BIT(13)
+#define IODA2_PEST0_UTL_CORRECTABLE PPC_BIT(14)
+#define IODA2_PEST0_UTL_INTERRUPT PPC_BIT(15)
+#define IODA2_PEST0_MMIO_XLATE PPC_BIT(16)
+#define IODA2_PEST0_IODA2_ERROR PPC_BIT(16) /* Same bit as MMIO xlate */
+#define IODA2_PEST0_TCE_PAGE_FAULT PPC_BIT(18)
+#define IODA2_PEST0_TCE_ACCESS_FAULT PPC_BIT(19)
+#define IODA2_PEST0_DMA_RESP_TIMEOUT PPC_BIT(20)
+#define IODA2_PEST0_AIB_SIZE_INVALID PPC_BIT(21)
+#define IODA2_PEST0_LEM_BIT_MASK PPC_BITMASK(26, 31)
+#define IODA2_PEST0_LEM_BIT_LSH PPC_BITLSHIFT(31)
+#define IODA2_PEST0_RID_MASK PPC_BITMASK(32, 47)
+#define IODA2_PEST0_RID_LSH PPC_BITLSHIFT(47)
+#define IODA2_PEST0_MSI_DATA_MASK PPC_BITMASK(48, 63)
+#define IODA2_PEST0_MSI_DATA_LSH PPC_BITLSHIFT(63)
+
+#define IODA2_PEST1_FAIL_ADDR_MASK PPC_BITMASK(3, 63)
+#define IODA2_PEST1_FAIL_ADDR_LSH PPC_BITLSHIFT(63)
+
+
+#endif /* PCI_HOST_PNV_PHB3_REGS_H */
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index b70a13bd4175..b6feff140cb0 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -25,6 +25,8 @@
#include "hw/ppc/pnv_psi.h"
#include "hw/ppc/pnv_occ.h"
+typedef struct PnvPhb3State PnvPhb3State;
+
#define TYPE_PNV_CHIP "powernv-chip"
#define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP)
#define PNV_CHIP_CLASS(klass) \
@@ -61,6 +63,10 @@ typedef struct PnvChip {
PnvLpcController lpc;
PnvPsi psi;
PnvOCC occ;
+
+ uint32_t num_phbs;
+#define PNV_MAX_CHIP_PHB 4
+ PnvPhb3State *phbs[PNV_MAX_CHIP_PHB];
} PnvChip;
typedef struct PnvChipClass {
diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h
index 3757b2cab94b..731c2fff26e2 100644
--- a/include/hw/ppc/pnv_xscom.h
+++ b/include/hw/ppc/pnv_xscom.h
@@ -66,6 +66,15 @@ typedef struct PnvXScomInterfaceClass {
#define PNV_XSCOM_OCC_BASE 0x0066000
#define PNV_XSCOM_OCC_SIZE 0x6000
+#define PNV_XSCOM_PBCQ_NEST_BASE 0x2012000
+#define PNV_XSCOM_PBCQ_NEST_SIZE 0x46
+
+#define PNV_XSCOM_PBCQ_PCI_BASE 0x9012000
+#define PNV_XSCOM_PBCQ_PCI_SIZE 0x15
+
+#define PNV_XSCOM_PBCQ_SPCI_BASE 0x9013c00
+#define PNV_XSCOM_PBCQ_SPCI_SIZE 0x5
+
extern void pnv_xscom_realize(PnvChip *chip, Error **errp);
extern int pnv_xscom_populate(PnvChip *chip, void *fdt, int offset);
diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h
index e6699c917e24..eeee5abd86f5 100644
--- a/include/hw/ppc/xics.h
+++ b/include/hw/ppc/xics.h
@@ -190,6 +190,7 @@ void icp_set_mfrr(ICPState *icp, uint8_t mfrr);
uint32_t icp_accept(ICPState *ss);
uint32_t icp_ipoll(ICPState *ss, uint32_t *mfrr);
void icp_eoi(ICPState *icp, uint32_t xirr);
+void icp_irq(ICSState *ics, int server, int nr, uint8_t priority);
void ics_simple_write_xive(ICSState *ics, int nr, int server,
uint8_t priority, uint8_t saved_priority);
--
2.7.4
^ permalink raw reply related [flat|nested] 66+ messages in thread* Re: [Qemu-devel] [PATCH 20/21] ppc/pnv: Add model for Power8 PHB3 PCIe Host bridge
2017-04-05 12:41 ` [Qemu-devel] [PATCH 20/21] ppc/pnv: Add model for Power8 PHB3 PCIe Host bridge Cédric Le Goater
@ 2017-04-10 8:14 ` David Gibson
2017-04-11 3:05 ` Benjamin Herrenschmidt
2017-04-11 16:35 ` Cédric Le Goater
0 siblings, 2 replies; 66+ messages in thread
From: David Gibson @ 2017-04-10 8:14 UTC (permalink / raw)
To: Cédric Le Goater
Cc: qemu-ppc, qemu-devel, Benjamin Herrenschmidt, Marcel Apfelbaum,
Michael S. Tsirkin
[-- Attachment #1: Type: text/plain, Size: 105173 bytes --]
On Wed, Apr 05, 2017 at 02:41:45PM +0200, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>
> This is a model of the PCIe host bridge found on Power8 chips,
> including IOMMU support, PCIe root complex etc...
>
> This implementation doesn't emulate the EEH error handling (and
> may never do).
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> [clg: updated for qemu-2.9
> QOM'ified the models
> introduced pnv_chip_phb_realize() to create the PHB3 objects
> updated the XICSFabric handlers to loop on the PHB3 ICS
> fixed the XIVE update
> fixed IRQ number overlap in pnv_phb3_remap_irqs() ]
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> hw/intc/xics.c | 2 +-
> hw/pci-host/Makefile.objs | 1 +
> hw/pci-host/pnv_phb3.c | 1052 +++++++++++++++++++++++++++++++++++
> hw/pci-host/pnv_phb3_msi.c | 304 ++++++++++
> hw/pci-host/pnv_phb3_pbcq.c | 361 ++++++++++++
> hw/pci-host/pnv_phb3_rc.c | 134 +++++
> hw/ppc/pnv.c | 76 ++-
> hw/ppc/pnv_xscom.c | 5 +-
> include/hw/pci-host/pnv_phb3.h | 156 ++++++
> include/hw/pci-host/pnv_phb3_regs.h | 506 +++++++++++++++++
> include/hw/ppc/pnv.h | 6 +
> include/hw/ppc/pnv_xscom.h | 9 +
> include/hw/ppc/xics.h | 1 +
> 13 files changed, 2608 insertions(+), 5 deletions(-)
> create mode 100644 hw/pci-host/pnv_phb3.c
> create mode 100644 hw/pci-host/pnv_phb3_msi.c
> create mode 100644 hw/pci-host/pnv_phb3_pbcq.c
> create mode 100644 hw/pci-host/pnv_phb3_rc.c
> create mode 100644 include/hw/pci-host/pnv_phb3.h
> create mode 100644 include/hw/pci-host/pnv_phb3_regs.h
>
> diff --git a/hw/intc/xics.c b/hw/intc/xics.c
> index 292fffecd376..efb65aabdf30 100644
> --- a/hw/intc/xics.c
> +++ b/hw/intc/xics.c
> @@ -263,7 +263,7 @@ void icp_eoi(ICPState *icp, uint32_t xirr)
> }
> }
>
> -static void icp_irq(ICSState *ics, int server, int nr, uint8_t priority)
> +void icp_irq(ICSState *ics, int server, int nr, uint8_t priority)
> {
> ICPState *icp = xics_icp_get(ics->xics, server);
>
> diff --git a/hw/pci-host/Makefile.objs b/hw/pci-host/Makefile.objs
> index 9c7909cf44c6..3167b4430eb9 100644
> --- a/hw/pci-host/Makefile.objs
> +++ b/hw/pci-host/Makefile.objs
> @@ -17,3 +17,4 @@ common-obj-$(CONFIG_PCI_PIIX) += piix.o
> common-obj-$(CONFIG_PCI_Q35) += q35.o
> common-obj-$(CONFIG_PCI_GENERIC) += gpex.o
> common-obj-$(CONFIG_PCI_XILINX) += xilinx-pcie.o
> +obj-$(CONFIG_POWERNV) += pnv_phb3.o pnv_phb3_pbcq.o pnv_phb3_rc.o pnv_phb3_msi.o
> diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c
> new file mode 100644
> index 000000000000..4068ae6d8c62
> --- /dev/null
> +++ b/hw/pci-host/pnv_phb3.c
> @@ -0,0 +1,1052 @@
> +/*
> + * QEMU PowerPC PowerNV PHB3 model
> + *
> + * Copyright (c) 2014-2017, IBM Corporation.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License, version 2, as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
> +#include "qemu/osdep.h"
> +#include "qemu/log.h"
> +#include "qapi/error.h"
> +#include "qemu-common.h"
> +#include "hw/pci-host/pnv_phb3.h"
> +#include "hw/pci/pci_bridge.h"
> +#include "hw/pci/pci_bus.h"
> +
> +#undef DISPLAY_UNIMPLENTED_REG
> +
> +static PCIDevice *pnb_phb3_find_cfg_dev(PnvPhb3State *phb)
Is this supposed to be "pnv" instead of "pnb"? Note also that just
"phb3_" is probably a sufficiently distinct prefix if you wanted to
shorten all the function names.
> +{
> + PCIHostState *pci = PCI_HOST_BRIDGE(phb);
> + uint64_t addr = phb->regs[PHB_CONFIG_ADDRESS >> 3];
> + uint8_t bus, devfn;
> +
> + if (!(addr >> 63)) {
> + return NULL;
> + }
> + bus = (addr >> 52) & 0xff;
> + devfn = (addr >> 44) & 0xff;
> +
> + return pci_find_device(pci->bus, bus, devfn);
> +}
> +
> +static void pnv_phb3_config_write(PnvPhb3State *phb, unsigned off,
> + unsigned size, uint64_t val)
> +{
> + uint32_t cfg_addr, limit;
> + PCIDevice *pdev;
> +
> + pdev = pnb_phb3_find_cfg_dev(phb);
> + if (!pdev) {
> + return;
> + }
> + cfg_addr = (phb->regs[PHB_CONFIG_ADDRESS >> 3] >> 32) & 0xfff;
> + cfg_addr |= off;
> + limit = pci_config_size(pdev);
> + if (limit <= cfg_addr) {
> + /* conventional pci device can be behind pcie-to-pci bridge.
> + 256 <= addr < 4K has no effects. */
> + return;
> + }
> + switch (size) {
> + case 1:
> + break;
> + case 2:
> + val = bswap16(val);
An unconditional bswap() seems unlikely to be correct. What's the
purpose of thise?
> + break;
> + case 4:
> + val = bswap32(val);
> + break;
No 64-bit config registers?
> + default:
> + return;
You can probably have an assert() here, since the memory region
registration should prevent bad access sizes.
> + }
> + pci_host_config_write_common(pdev, cfg_addr, limit, val, size);
> +}
> +
> +static uint64_t pnv_phb3_config_read(PnvPhb3State *phb, unsigned off,
> + unsigned size)
> +{
> + uint32_t cfg_addr, limit;
> + PCIDevice *pdev;
> + uint64_t val;
> +
> + pdev = pnb_phb3_find_cfg_dev(phb);
> + if (!pdev) {
> + return ~0ull;
> + }
> + cfg_addr = (phb->regs[PHB_CONFIG_ADDRESS >> 3] >> 32) & 0xffc;
> + cfg_addr |= off;
> + limit = pci_config_size(pdev);
> + if (limit <= cfg_addr) {
> + /* conventional pci device can be behind pcie-to-pci bridge.
> + 256 <= addr < 4K has no effects. */
> + return ~0ull;
> + }
> + val = pci_host_config_read_common(pdev, cfg_addr, limit, size);
> + switch (size) {
> + case 1:
> + return val;
> + case 2:
> + return bswap16(val);
> + case 4:
> + return bswap32(val);
> + default:
> + return ~0ull;
As with read, I expect you can have an assert() here.
> + }
> +}
> +
> +static void pnv_phb3_check_m32(PnvPhb3State *phb)
> +{
> + uint64_t base, start, size;
> + MemoryRegion *parent;
> +
> + if (phb->m32_mapped) {
> + /* Should we destroy it in RCU friendly way... ? */
Should be fine for now - everything is under the BQL anyway.
> + memory_region_del_subregion(phb->mr_m32.container, &phb->mr_m32);
> + phb->m32_mapped = false;
> + }
> +
> + /* Disabled ? move on with life ... */
> + if (!(phb->regs[PHB_PHB3_CONFIG >> 3] & PHB_PHB3C_M32_EN)) {
> + return;
> + }
> +
> + /* Grab geometry from registers */
> + base = phb->regs[PHB_M32_BASE_ADDR >> 3];
> + start = phb->regs[PHB_M32_START_ADDR >> 3];
> + size = ~(phb->regs[PHB_M32_BASE_MASK >> 3] | 0xfffc000000000000ull) + 1;
> +
> + /* Check if it matches an enabled MMIO region in the PBCQ */
> + if (phb->pbcq->mmio0_mapped && base >= phb->pbcq->mmio0_base &&
> + (base + size) <= (phb->pbcq->mmio0_base + phb->pbcq->mmio0_size)) {
> + parent = &phb->pbcq->mmbar0;
> + base -= phb->pbcq->mmio0_base;
> + } else if (phb->pbcq->mmio1_mapped && base >= phb->pbcq->mmio1_base &&
> + (base + size) <= (phb->pbcq->mmio1_base + phb->pbcq->mmio1_size)) {
> + parent = &phb->pbcq->mmbar1;
> + base -= phb->pbcq->mmio1_base;
> + } else {
> + return;
> + }
> +
> + /* Create alias */
> + memory_region_init_alias(&phb->mr_m32, OBJECT(phb), "phb3-m32",
> + &phb->pci_mmio, start, size);
> + memory_region_add_subregion(parent, base, &phb->mr_m32);
> + phb->m32_mapped = true;
> +}
> +
> +static void pnv_phb3_check_m64(PnvPhb3State *phb, uint32_t index)
> +{
> + uint64_t base, start, size, m64;
> + MemoryRegion *parent;
> +
> + if (phb->m64_mapped[index]) {
> + /* Should we destroy it in RCU friendly way... ? */
> + memory_region_del_subregion(phb->mr_m64[index].container,
> + &phb->mr_m64[index]);
> + phb->m64_mapped[index] = false;
> + }
> +
> + /* Get table entry */
> + m64 = phb->ioda_M64BT[index];
> +
> + /* Disabled ? move on with life ... */
> + if (!(m64 & IODA2_M64BT_ENABLE)) {
> + return;
> + }
> +
> + /* Grab geometry from registers */
> + base = GETFIELD(IODA2_M64BT_BASE, m64) << 20;
> + if (m64 & IODA2_M64BT_SINGLE_PE) {
> + base &= ~0x1ffffffull;
> + }
> + size = GETFIELD(IODA2_M64BT_MASK, m64) << 20;
> + size |= 0xfffc000000000000ull;
> + size = ~size + 1;
> + start = base | (phb->regs[PHB_M64_UPPER_BITS >> 3]);
> +
> + /* Check if it matches an enabled MMIO region in the PBCQ */
> + if (phb->pbcq->mmio0_mapped && base >= phb->pbcq->mmio0_base &&
> + (base + size) <= (phb->pbcq->mmio0_base + phb->pbcq->mmio0_size)) {
> + parent = &phb->pbcq->mmbar0;
> + base -= phb->pbcq->mmio0_base;
> + } else if (phb->pbcq->mmio1_mapped && base >= phb->pbcq->mmio1_base &&
> + (base + size) <= (phb->pbcq->mmio1_base + phb->pbcq->mmio1_size)) {
> + parent = &phb->pbcq->mmbar1;
> + base -= phb->pbcq->mmio1_base;
> + } else {
> + return;
> + }
> +
> + /* Create alias */
> + memory_region_init_alias(&phb->mr_m64[index], OBJECT(phb), "phb3-m64",
> + &phb->pci_mmio, start, size);
> + memory_region_add_subregion(parent, base, &phb->mr_m64[index]);
> + phb->m64_mapped[index] = true;
> +}
> +
> +static void pnv_phb3_check_all_m64s(PnvPhb3State *phb)
> +{
> + uint64_t i;
> +
> + for (i = 0; i < PNV_PHB3_NUM_M64; i++) {
> + pnv_phb3_check_m64(phb, i);
> + }
> +}
> +
> +static void pnv_phb3_lxivt_write(PnvPhb3State *phb, unsigned idx, uint64_t val)
> +{
> + ICSState *ics = phb->lsi_ics;
> + uint8_t server, prio;
> +
> + phb->ioda_LXIVT[idx] = val & (IODA2_LXIVT_SERVER_MASK |
> + IODA2_LXIVT_PRIORITY_MASK |
> + IODA2_LXIVT_NODE_ID_MASK);
> + server = GETFIELD(IODA2_LXIVT_SERVER, val);
> + prio = GETFIELD(IODA2_LXIVT_PRIORITY, val);
> +
> + /*
> + * The low order 2 bits are the link pointer (Type II interrupts).
> + * Shift back to get a valid IRQ server.
> + */
> + server >>= 2;
> +
> + ics_simple_write_xive(ics, idx, server, prio, prio);
> +}
> +
> +static uint64_t *pnv_phb3_ioda_access(PnvPhb3State *phb,
> + unsigned *out_table, unsigned *out_idx)
> +{
> + uint64_t adreg = phb->regs[PHB_IODA_ADDR >> 3];
> + unsigned int index = GETFIELD(PHB_IODA_AD_TADR, adreg);
> + unsigned int table = GETFIELD(PHB_IODA_AD_TSEL, adreg);
> + unsigned int mask;
> + uint64_t *tptr = NULL;
> +
> + switch (table) {
> + case IODA2_TBL_LIST:
> + tptr = phb->ioda_LIST;
> + mask = 7;
> + break;
> + case IODA2_TBL_LXIVT:
> + tptr = phb->ioda_LXIVT;
> + mask = 7;
> + break;
> + case IODA2_TBL_IVC_CAM:
> + case IODA2_TBL_RBA:
> + mask = 31;
> + break;
> + case IODA2_TBL_RCAM:
> + mask = 63;
> + break;
> + case IODA2_TBL_MRT:
> + mask = 7;
> + break;
> + case IODA2_TBL_PESTA:
> + case IODA2_TBL_PESTB:
> + mask = 255;
> + break;
> + case IODA2_TBL_TVT:
> + tptr = phb->ioda_TVT;
> + mask = 511;
> + break;
> + case IODA2_TBL_TCAM:
> + case IODA2_TBL_TDR:
> + mask = 63;
> + break;
> + case IODA2_TBL_M64BT:
> + tptr = phb->ioda_M64BT;
> + mask = 15;
> + break;
> + case IODA2_TBL_M32DT:
> + tptr = phb->ioda_MDT;
> + mask = 255;
> + break;
> + case IODA2_TBL_PEEV:
> + tptr = phb->ioda_PEEV;
> + mask = 3;
> + break;
> + default:
> + return NULL;
> + }
> + index &= mask;
> + if (out_idx) {
> + *out_idx = index;
> + }
> + if (out_table) {
> + *out_table = table;
> + }
> + if (adreg & PHB_IODA_AD_AUTOINC) {
> + index = (index + 1) & mask;
> + adreg = SETFIELD(PHB_IODA_AD_TADR, adreg, index);
> + }
> + if (tptr) {
> + tptr += index;
> + }
> + phb->regs[PHB_IODA_ADDR >> 3] = adreg;
> + return tptr;
> +}
> +
> +static uint64_t pnv_phb3_ioda_read(PnvPhb3State *phb)
> +{
> + unsigned table;
> + uint64_t *tptr;
> +
> + tptr = pnv_phb3_ioda_access(phb, &table, NULL);
> + if (!tptr) {
> + /* Return 0 on unsupported tables, not ff's */
> + return 0;
> + }
> + return *tptr;
> +}
> +
> +static void pnv_phb3_ioda_write(PnvPhb3State *phb, uint64_t val)
> +{
> + unsigned table, idx;
> + uint64_t *tptr;
> +
> + tptr = pnv_phb3_ioda_access(phb, &table, &idx);
> + if (!tptr) {
> + return;
> + }
> +
> + /* Handle side effects */
> + switch (table) {
> + case IODA2_TBL_LXIVT:
> + pnv_phb3_lxivt_write(phb, idx, val);
> + break;
> + case IODA2_TBL_M64BT:
> + *tptr = val;
> + pnv_phb3_check_m64(phb, idx);
> + break;
> + default:
> + *tptr = val;
> + }
> +}
> +
> +/* This is called whenever the PHB LSI, MSI source ID register or
> + * the PBCQ irq filters are written.
> + */
> +void pnv_phb3_remap_irqs(PnvPhb3State *phb)
> +{
> + ICSState *ics = phb->lsi_ics;
> + uint32_t local, global, count, mask, comp;
> + uint64_t baren;
> +
> + /* First check if we are enabled. Unlike real HW we don't separate TX and RX
> + * so we enable if both are set
> + */
> + baren = phb->pbcq->nest_regs[PBCQ_NEST_BAR_EN];
> + if (!(baren & PBCQ_NEST_BAR_EN_IRSN_RX) ||
> + !(baren & PBCQ_NEST_BAR_EN_IRSN_TX)) {
> + ics->offset = 0;
> + return;
> + }
> +
> + /* Grab local LSI source ID */
> + local = GETFIELD(PHB_LSI_SRC_ID, phb->regs[PHB_LSI_SOURCE_ID >> 3]) << 3;
> +
> + /* Grab global one and compare */
> + global = GETFIELD(PBCQ_NEST_LSI_SRC,
> + phb->pbcq->nest_regs[PBCQ_NEST_LSI_SRC_ID]) << 3;
> + if (global != local) {
> + /* This happens during initialization, let's come back when we
> + * are properly configured
> + */
> + ics->offset = 0;
> + return;
> + }
> +
> + /* Get the base on the powerbus */
> + comp = GETFIELD(PBCQ_NEST_IRSN_COMP,
> + phb->pbcq->nest_regs[PBCQ_NEST_IRSN_COMPARE]);
> + mask = GETFIELD(PBCQ_NEST_IRSN_COMP,
> + phb->pbcq->nest_regs[PBCQ_NEST_IRSN_MASK]);
> + count = ((~mask) + 1) & 0x7ffff;
> + phb->total_irq = count;
> +
> + /* Sanity checks */
> + if ((global + PNV_PHB3_NUM_LSI) > count) {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "LSIs out of reach: LSI base=%d total irq=%d",
> + global, count);
> + }
> +
> + if (count > 2048) {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "More interrupts than supported: %d", count);
> + }
> +
> + if ((comp & mask) != comp) {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "IRQ compare bits not in mask: comp=0x%x mask=0x%x",
> + comp, mask);
> + comp &= mask;
> + }
> + /* Setup LSI offset */
> + ics->offset = comp + global;
> +
> + /* Setup MSI offset */
> + pnv_phb3_msi_update_config(phb->msis, comp, count - PNV_PHB3_NUM_LSI);
> +}
> +
> +static void pnv_phb3_lsi_src_id_write(PnvPhb3State *phb, uint64_t val)
> +{
> + /* Sanitize content */
> + val &= PHB_LSI_SRC_ID_MASK;
> + phb->regs[PHB_LSI_SOURCE_ID >> 3] = val;
> + pnv_phb3_remap_irqs(phb);
> +}
> +
> +static void pnv_phb3_rtc_invalidate(PnvPhb3State *phb, uint64_t val)
> +{
> + PnvPhb3DMASpace *ds;
> +
> + /* Always invalidate all for now ... */
> + QLIST_FOREACH(ds, &phb->dma_spaces, list) {
> + ds->pe_num = PHB_INVALID_PE;
> + }
> +}
> +
> +
> +static void pnv_phb3_update_msi_regions(PnvPhb3DMASpace *ds)
> +{
> + uint64_t cfg = ds->phb->regs[PHB_PHB3_CONFIG >> 3];
> +
> + if (cfg & PHB_PHB3C_32BIT_MSI_EN) {
> + if (!ds->msi32_mapped) {
> + memory_region_add_subregion(&ds->dma_mr, 0xffff0000, &ds->msi32_mr);
> + ds->msi32_mapped = true;
> + }
> + } else {
> + if (ds->msi32_mapped) {
> + memory_region_del_subregion(&ds->dma_mr, &ds->msi32_mr);
> + ds->msi32_mapped = false;
Could you just use the MR build in enabled flag
(memory_region_set_enabled() etc.) instead of using your own flags?
> + }
> + }
> +
> + if (cfg & PHB_PHB3C_64BIT_MSI_EN) {
> + if (!ds->msi64_mapped) {
> + memory_region_add_subregion(&ds->dma_mr,
> + (1ull << 60), &ds->msi64_mr);
> + ds->msi64_mapped = true;
> + }
> + } else {
> + if (ds->msi64_mapped) {
> + memory_region_del_subregion(&ds->dma_mr, &ds->msi64_mr);
> + ds->msi64_mapped = false;
> + }
> + }
> +}
> +
> +static void pnv_phb3_update_all_msi_regions(PnvPhb3State *phb)
> +{
> + PnvPhb3DMASpace *ds;
> +
> + QLIST_FOREACH(ds, &phb->dma_spaces, list) {
> + pnv_phb3_update_msi_regions(ds);
> + }
> +}
> +
> +void pnv_phb3_reg_write(void *opaque, hwaddr off, uint64_t val, unsigned size)
> +{
> + PnvPhb3State *phb = opaque;
> + bool changed;
> +
> + /* Special case configuration data */
> + if ((off & 0xfffc) == PHB_CONFIG_DATA) {
> + pnv_phb3_config_write(phb, off & 0x3, size, val);
> + return;
> + }
> +
> + /* Other registers are 64-bit only */
> + if (size != 8 || off & 0x7) {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "Invalid register access, offset: 0x%"PRIx64" size: %d",
> + off, size);
> + return;
> + }
> +
> + /* Handle masking */
> + switch (off) {
> + case PHB_M64_UPPER_BITS:
> + val &= 0xfffc000000000000ull;
> + break;
> + }
> +
> + /* Record whether it changed */
> + changed = phb->regs[off >> 3] != val;
> +
> + /* Store in register cache first */
> + phb->regs[off >> 3] = val;
> +
> + /* Handle side effects */
> + switch (off) {
> + case PHB_PHB3_CONFIG:
> + if (changed) {
> + pnv_phb3_update_all_msi_regions(phb);
> + }
> + /* fall through */
> + case PHB_M32_BASE_ADDR:
> + case PHB_M32_BASE_MASK:
> + case PHB_M32_START_ADDR:
> + if (changed) {
> + pnv_phb3_check_m32(phb);
> + }
> + break;
> + case PHB_M64_UPPER_BITS:
> + if (changed) {
> + pnv_phb3_check_all_m64s(phb);
> + }
> + break;
> + case PHB_LSI_SOURCE_ID:
> + if (changed) {
> + pnv_phb3_lsi_src_id_write(phb, val);
> + }
> + break;
> +
> + /* IODA table accesses */
> + case PHB_IODA_DATA0:
> + pnv_phb3_ioda_write(phb, val);
> + break;
> +
> + /* RTC invalidation */
> + case PHB_RTC_INVALIDATE:
> + pnv_phb3_rtc_invalidate(phb, val);
> + break;
> +
> + /* FFI request */
> + case PHB_FFI_REQUEST:
> + pnv_phb3_msi_ffi(phb->msis, val);
> + break;
> +
> + /* Silent simple writes */
> + case PHB_CONFIG_ADDRESS:
> + case PHB_IODA_ADDR:
> + case PHB_TCE_KILL:
> + case PHB_TCE_SPEC_CTL:
> + case PHB_PEST_BAR:
> + case PHB_PELTV_BAR:
> + case PHB_RTT_BAR:
> + case PHB_RBA_BAR:
> + case PHB_IVT_BAR:
> + case PHB_FFI_LOCK:
> + break;
> +
> +#ifdef DISPLAY_UNIMPLENTED_REG
I don't think you need the ifdef - qemu_log_mask() already has a test
to see whether to write the message.
> + /* Noise on anything else */
> + default:
> + qemu_log_mask(LOG_UNIMP, "reg_write 0x%"PRIx64"=%"PRIx64, off, val);
> +#endif
> + }
> +}
> +
> +uint64_t pnv_phb3_reg_read(void *opaque, hwaddr off, unsigned size)
> +{
> + PnvPhb3State *phb = opaque;
> + uint64_t val;
> +
> + if ((off & 0xfffc) == PHB_CONFIG_DATA) {
> + return pnv_phb3_config_read(phb, off & 0x3, size);
> + }
> +
> + /* Other registers are 64-bit only */
> + if (size != 8 || off & 0x7) {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "Invalid register access, offset: 0x%"PRIx64" size: %d",
> + off, size);
> + return ~0ull;
> + }
> +
> + /* Default read from cache */
> + val = phb->regs[off >> 3];
> +
> + switch (off) {
> + /* Simulate venice DD2.0 */
> + case PHB_VERSION:
> + return 0x000000a300000005ull;
> +
> + /* IODA table accesses */
> + case PHB_IODA_DATA0:
> + return pnv_phb3_ioda_read(phb);
> +
> + /* Link training always appears trained */
> + case PHB_PCIE_DLP_TRAIN_CTL:
> + return PHB_PCIE_DLP_INBAND_PRESENCE | PHB_PCIE_DLP_TC_DL_LINKACT;
> +
> + /* FFI Lock */
> + case PHB_FFI_LOCK:
> + /* Set lock and return previous value */
> + phb->regs[off >> 3] |= PHB_FFI_LOCK_STATE;
> + return val;
> +
> + /* Silent simple reads */
> + case PHB_PHB3_CONFIG:
> + case PHB_M32_BASE_ADDR:
> + case PHB_M32_BASE_MASK:
> + case PHB_M32_START_ADDR:
> + case PHB_CONFIG_ADDRESS:
> + case PHB_IODA_ADDR:
> + case PHB_RTC_INVALIDATE:
> + case PHB_TCE_KILL:
> + case PHB_TCE_SPEC_CTL:
> + case PHB_PEST_BAR:
> + case PHB_PELTV_BAR:
> + case PHB_RTT_BAR:
> + case PHB_RBA_BAR:
> + case PHB_IVT_BAR:
> + case PHB_M64_UPPER_BITS:
> + break;
> +
> +#ifdef DISPLAY_UNIMPLENTED_REG
> + /* Noise on anything else */
> + default:
> + qemu_log_mask(LOG_UNIMP, "reg_read 0x%"PRIx64"=%"PRIx64, off, val);
> +#endif
> + }
> + return val;
> +}
> +
> +static const MemoryRegionOps pnv_phb3_reg_ops = {
> + .read = pnv_phb3_reg_read,
> + .write = pnv_phb3_reg_write,
> + .valid.min_access_size = 1,
> + .valid.max_access_size = 8,
> + .impl.min_access_size = 1,
> + .impl.max_access_size = 8,
> + .endianness = DEVICE_BIG_ENDIAN,
> +};
> +
> +static int pnv_phb3_map_irq(PCIDevice *pci_dev, int irq_num)
> +{
> + /* Check that out properly ... */
> + return irq_num & 3;
> +}
> +
> +static void pnv_phb3_set_irq(void *opaque, int irq_num, int level)
> +{
> + PnvPhb3State *phb = opaque;
> +
> + /* LSI only ... */
> + if (irq_num > 3) {
> + qemu_log_mask(LOG_GUEST_ERROR, "Unknown IRQ to set %d", irq_num);
> + }
> + qemu_set_irq(phb->lsi_ics->qirqs[irq_num], level);
> +}
> +
> +static bool pnv_phb3_resolve_pe(PnvPhb3DMASpace *ds)
> +{
> + uint64_t rtt, addr;
> + uint16_t rte;
> + int bus_num;
> +
> + /* Already resolved ? */
> + if (ds->pe_num != PHB_INVALID_PE) {
> + return true;
> + }
> +
> + /* We need to lookup the RTT */
> + rtt = ds->phb->regs[PHB_RTT_BAR >> 3];
> + if (!(rtt & PHB_RBA_BAR_ENABLE)) {
> + qemu_log_mask(LOG_GUEST_ERROR, "DMA with RTT BAR disabled !");
> + /* Set error bits ? fence ? ... */
> + return false;
> + }
> +
> + /* Read RTE */
> + bus_num = pci_bus_num(ds->bus);
> + addr = rtt & PHB_RTT_BASE_ADDRESS_MASK;
> + addr += 2 * ((bus_num << 8) | ds->devfn);
> + if (dma_memory_read(&address_space_memory, addr, &rte, sizeof(rte))) {
> + qemu_log_mask(LOG_GUEST_ERROR, "Failed to read RTT entry at 0x%"PRIx64,
> + addr);
> + /* Set error bits ? fence ? ... */
> + return false;
> + }
> + rte = be16_to_cpu(rte);
> +
> + /* Fail upon reading of invalid PE# */
> + if (rte >= PNV_PHB3_NUM_PE) {
> + qemu_log_mask(LOG_GUEST_ERROR, "RTE for RID 0x%x invalid (%04x)",
> + ds->devfn, rte);
> + /* Set error bits ? fence ? ... */
> + return false;
> + }
> + ds->pe_num = rte;
> + return true;
> +}
> +
> +static void pnv_phb3_translate_tve(PnvPhb3DMASpace *ds, hwaddr addr,
> + bool is_write, uint64_t tve,
> + IOMMUTLBEntry *tlb)
> +{
> + uint64_t tta = GETFIELD(IODA2_TVT_TABLE_ADDR, tve);
> + int32_t lev = GETFIELD(IODA2_TVT_NUM_LEVELS, tve);
> + uint32_t tts = GETFIELD(IODA2_TVT_TCE_TABLE_SIZE, tve);
> + uint32_t tps = GETFIELD(IODA2_TVT_IO_PSIZE, tve);
> +
> + /* Invalid levels */
> + if (lev > 4) {
> + qemu_log_mask(LOG_GUEST_ERROR, "Invalid #levels in TVE %d", lev);
> + return;
> + }
> +
> + /* IO Page Size of 0 means untranslated, else use TCEs */
> + if (tps == 0) {
> + /* We only support non-translate in top window
> + * XXX FIX THAT, Venice/Murano support it on bottom window
> + * above 4G and Naples suports it on everything
> + */
> + if (!(tve & PPC_BIT(51))) {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "xlate for invalid non-translate TVE");
> + return;
> + }
> + /* XXX Handle boundaries */
> +
> + /* XXX Use 4k pages like q35 ... for now */
> + tlb->iova = addr & 0xfffffffffffff000ull;
> + tlb->translated_addr = addr & 0x0003fffffffff000ull;
> + tlb->addr_mask = 0xfffull;
> + tlb->perm = IOMMU_RW;
> + } else {
> + uint32_t tce_shift, tbl_shift, sh;
> + uint64_t base, taddr, tce, tce_mask;
> +
> + /* TVE disabled ? */
> + if (tts == 0) {
> + qemu_log_mask(LOG_GUEST_ERROR, "xlate for invalid translated TVE");
> + return;
> + }
> +
> + /* Address bits per bottom level TCE entry */
> + tce_shift = tps + 11;
> +
> + /* Address bits per table level */
> + tbl_shift = tts + 8;
> +
> + /* Top level table base address */
> + base = tta << 12;
> +
> + /* Total shift to first level */
> + sh = tbl_shift * lev + tce_shift;
> +
> + /* XXX Multi-level untested */
> + while ((lev--) >= 0) {
> + /* Grab the TCE address */
> + taddr = base | (((addr >> sh) & ((1ul << tbl_shift) - 1)) << 3);
> + if (dma_memory_read(&address_space_memory, taddr, &tce,
> + sizeof(tce))) {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "Failed to read TCE at 0x%"PRIx64, taddr);
> + return;
> + }
> + tce = be64_to_cpu(tce);
> +
> + /* Check permission for indirect TCE */
> + if ((lev >= 0) && !(tce & 3)) {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "Invalid indirect TCE at 0x%"PRIx64, taddr);
> + qemu_log_mask(LOG_GUEST_ERROR,
> + " xlate %"PRIx64":%c TVE=%"PRIx64,
> + addr, is_write ? 'W' : 'R', tve);
> + qemu_log_mask(LOG_GUEST_ERROR,
> + " tta=%"PRIx64" lev=%d tts=%d tps=%d",
> + tta, lev, tts, tps);
> + return;
> + }
> + sh -= tbl_shift;
> + base = tce & ~0xfffull;
> + }
> +
> + /* We exit the loop with TCE being the final TCE */
> + tce_mask = ~((1ull << tce_shift) - 1);
> + tlb->iova = addr & tce_mask;
> + tlb->translated_addr = tce & tce_mask;
> + tlb->addr_mask = ~tce_mask;
> + tlb->perm = tce & 3;
> + if ((is_write & !(tce & 2)) || ((!is_write) && !(tce & 1))) {
> + qemu_log_mask(LOG_GUEST_ERROR, "TCE access fault at 0x%"PRIx64,
> + taddr);
> + qemu_log_mask(LOG_GUEST_ERROR, " xlate %"PRIx64":%c TVE=%"PRIx64,
> + addr, is_write ? 'W' : 'R', tve);
> + qemu_log_mask(LOG_GUEST_ERROR,
> + " tta=%"PRIx64" lev=%d tts=%d tps=%d",
> + tta, lev, tts, tps);
> + }
> + }
> +}
> +
> +static IOMMUTLBEntry pnv_phb3_translate_iommu(MemoryRegion *iommu, hwaddr addr,
> + bool is_write)
> +{
> + PnvPhb3DMASpace *ds = container_of(iommu, PnvPhb3DMASpace, dma_mr);
> + int tve_sel;
> + uint64_t tve, cfg;
> + IOMMUTLBEntry ret = {
> + .target_as = &address_space_memory,
> + .iova = addr,
> + .translated_addr = 0,
> + .addr_mask = ~(hwaddr)0,
> + .perm = IOMMU_NONE,
> + };
> +
> + /* Resolve PE# */
> + if (!pnv_phb3_resolve_pe(ds)) {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "Failed to resolve PE# for bus @%p (%d) devfn 0x%x",
> + ds->bus, pci_bus_num(ds->bus), ds->devfn);
> + return ret;
> + }
> +
> + /* Check top bits */
> + switch (addr >> 60) {
> + case 00:
> + /* DMA or 32-bit MSI ? */
> + cfg = ds->phb->regs[PHB_PHB3_CONFIG >> 3];
> + if ((cfg & PHB_PHB3C_32BIT_MSI_EN) &&
> + ((addr & 0xffffffffffff0000ull) == 0xffff0000ull)) {
> + qemu_log_mask(LOG_GUEST_ERROR, "xlate on 32-bit MSI region");
> + return ret;
> + }
> + /* Choose TVE XXX Use PHB3 Control Register */
> + tve_sel = (addr >> 59) & 1;
> + tve = ds->phb->ioda_TVT[ds->pe_num * 2 + tve_sel];
> + pnv_phb3_translate_tve(ds, addr, is_write, tve, &ret);
> + break;
> + case 01:
> + qemu_log_mask(LOG_GUEST_ERROR, "xlate on 64-bit MSI region");
> + break;
> + default:
> + qemu_log_mask(LOG_GUEST_ERROR, "xlate on unsupported address 0x%"PRIx64,
> + addr);
> + }
> + return ret;
> +}
> +
> +static const MemoryRegionIOMMUOps pnv_phb3_iommu_ops = {
> + .translate = pnv_phb3_translate_iommu,
> +};
> +
> +/*
> + * MSI/MSIX memory region implementation.
> + * The handler handles both MSI and MSIX.
> + */
> +static void pnv_phb3_msi_write(void *opaque, hwaddr addr,
> + uint64_t data, unsigned size)
> +{
> + PnvPhb3DMASpace *ds = opaque;
> +
> + /* Resolve PE# */
> + if (!pnv_phb3_resolve_pe(ds)) {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "Failed to resolve PE# for bus @%p (%d) devfn 0x%x",
> + ds->bus, pci_bus_num(ds->bus), ds->devfn);
> + return;
> + }
> +
> + pnv_phb3_msi_send(ds->phb->msis, addr, data, ds->pe_num);
> +}
> +
> +static const MemoryRegionOps pnv_phb3_msi_ops = {
> + /* There is no .read as the read result is undefined by PCI spec */
> + .read = NULL,
> + .write = pnv_phb3_msi_write,
> + .endianness = DEVICE_LITTLE_ENDIAN
> +};
> +
> +static AddressSpace *pnv_phb3_dma_iommu(PCIBus *bus, void *opaque, int devfn)
> +{
> + PnvPhb3State *phb = opaque;
> + PnvPhb3DMASpace *ds;
> +
> + QLIST_FOREACH(ds, &phb->dma_spaces, list) {
> + if (ds->bus == bus && ds->devfn == devfn) {
> + break;
> + }
> + }
> + if (ds == NULL) {
> + ds = g_malloc0(sizeof(PnvPhb3DMASpace));
> + ds->bus = bus;
> + ds->devfn = devfn;
> + ds->pe_num = PHB_INVALID_PE;
> + ds->phb = phb;
> + memory_region_init_iommu(&ds->dma_mr, OBJECT(phb),
> + &pnv_phb3_iommu_ops, "phb3_iommu", UINT64_MAX);
Since you can have multiple of these per PHB, shouldn't they have a
more specific name?
> + address_space_init(&ds->dma_as, &ds->dma_mr, "phb3_iommu");
> + memory_region_init_io(&ds->msi32_mr, OBJECT(phb), &pnv_phb3_msi_ops,
> + ds, "msi32", 0x10000);
> + memory_region_init_io(&ds->msi64_mr, OBJECT(phb), &pnv_phb3_msi_ops,
> + ds, "msi64", 0x100000);
> + pnv_phb3_update_msi_regions(ds);
> +
> + QLIST_INSERT_HEAD(&phb->dma_spaces, ds, list);
> + }
> + return &ds->dma_as;
> +}
> +
> +static void pnv_phb3_root_bus_class_init(ObjectClass *klass, void *data)
> +{
> + BusClass *k = BUS_CLASS(klass);
> +
> + k->max_dev = 1;
> +}
> +
> +#define TYPE_PNV_PHB3_ROOT_BUS "pnv-phb3-root-bus"
> +
> +static const TypeInfo pnv_phb3_root_bus_info = {
> + .name = TYPE_PNV_PHB3_ROOT_BUS,
> + .parent = TYPE_PCIE_BUS,
> + .class_init = pnv_phb3_root_bus_class_init,
> +};
> +
> +static void pnv_phb3_initfn(Object *obj)
> +{
> + PnvPhb3State *phb = PNV_PHB3(obj);
> + /* Create LSI source */
> + phb->lsi_ics = ICS_SIMPLE(object_new(TYPE_ICS_SIMPLE));
> + object_property_add_child(OBJECT(phb), "ics-phb-lsi", OBJECT(phb->lsi_ics),
> + NULL);
> +
> + /* Default init ... will be fixed by HW inits */
> + phb->lsi_ics->offset = 0;
> + phb->lsi_ics->nr_irqs = PNV_PHB3_NUM_LSI;
> +
> + /* Create MSI source */
> + phb->msis = PHB3_MSI(object_new(TYPE_PHB3_MSI));
> + object_property_add_const_link(OBJECT(phb->msis), "phb", obj, &error_abort);
> + object_property_add_child(OBJECT(phb), "ics-phb-msi", OBJECT(phb->msis),
> + NULL);
> +
> + /* Create PBCQ */
> + phb->pbcq = PNV_PBCQ(object_new(TYPE_PNV_PBCQ));
> + object_property_add_const_link(OBJECT(phb->pbcq), "phb", obj, &error_abort);
> + object_property_add_child(OBJECT(phb), "pbcq", OBJECT(phb->pbcq), NULL);
> +
> + QLIST_INIT(&phb->dma_spaces);
> +}
> +
> +static void pnv_phb3_realize(DeviceState *dev, Error **errp)
> +{
> + PnvPhb3State *phb = PNV_PHB3(dev);
> + PCIHostState *pci = PCI_HOST_BRIDGE(dev);
> + Object *obj;
> + Error *error = NULL;
> + int i;
> +
> + memory_region_init(&phb->pci_mmio, OBJECT(phb), "pci-mmio",
> + PCI_MMIO_TOTAL_SIZE);
> +
> + /* PHB3 doesn't support IO space. However, qemu gets very upset if
> + * we don't have an IO region to anchor IO BARs onto so we just
> + * initialize one which we never hook up to anything
> + */
> + memory_region_init(&phb->pci_io, OBJECT(phb), "pci-io", 0x10000);
> +
> + memory_region_init_io(&phb->mr_regs, OBJECT(phb), &pnv_phb3_reg_ops, phb,
> + "phb3-regs", 0x1000);
> +
> + /* get XICSFabric from chip */
> + obj = object_property_get_link(OBJECT(dev), "xics", &error);
> + if (!obj) {
> + error_setg(errp, "%s: required link 'xics' not found: %s",
> + __func__, error_get_pretty(error));
> + return;
> + }
> +
> + object_property_add_const_link(OBJECT(phb->lsi_ics), "xics", obj, &error);
> + object_property_set_bool(OBJECT(phb->lsi_ics), true, "realized", &error);
> + if (error) {
> + error_propagate(errp, error);
> + return;
> + }
> +
> + for (i = 0; i < PNV_PHB3_NUM_LSI; i++) {
> + ics_set_irq_type(phb->lsi_ics, i, true);
> + }
> +
> + object_property_add_const_link(OBJECT(phb->msis), "xics", obj, &error);
> + object_property_set_bool(OBJECT(phb->msis), true, "realized", &error);
> + if (error) {
> + error_propagate(errp, error);
> + return;
> + }
> +
> + object_property_set_int(OBJECT(phb->pbcq), phb->phb_id, "phb-id", &error);
> + object_property_set_int(OBJECT(phb->pbcq), phb->chip_id, "chip-id", &error);
> + object_property_set_bool(OBJECT(phb->pbcq), true, "realized", &error);
> + if (error) {
> + error_propagate(errp, error);
> + return;
> + }
> +
> + pci->bus = pci_register_bus(dev, "phb3-root-bus",
> + pnv_phb3_set_irq, pnv_phb3_map_irq, phb,
> + &phb->pci_mmio, &phb->pci_io,
> + 0, 4, TYPE_PNV_PHB3_ROOT_BUS);
> + pci->bus->devfn_max = 1;
> + pci_setup_iommu(pci->bus, pnv_phb3_dma_iommu, phb);
> +}
> +
> +void pnv_phb3_update_regions(PnvPhb3State *phb)
> +{
> + /* Unmap first always */
> + if (phb->regs_mapped) {
> + memory_region_del_subregion(&phb->pbcq->phbbar, &phb->mr_regs);
> + phb->regs_mapped = false;
> + }
> +
> + /* Map registers if enabled */
> + if (phb->pbcq->phb_mapped) {
> + /* XXX We should use the PHB BAR 2 register but we don't ... */
> + memory_region_add_subregion(&phb->pbcq->phbbar, 0, &phb->mr_regs);
> + phb->regs_mapped = true;
> + }
> +
> + /* Check/update m32 */
> + if (phb->m32_mapped) {
> + pnv_phb3_check_m32(phb);
> + }
> +}
> +
> +static Property pnv_phb3_properties[] = {
> + DEFINE_PROP_UINT32("phb-id", PnvPhb3State, phb_id, 0),
> + DEFINE_PROP_UINT32("chip-id", PnvPhb3State, chip_id, 0),
> + DEFINE_PROP_END_OF_LIST(),
> +
> +};
> +
> +static void pnv_phb3_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> +
> + dc->realize = pnv_phb3_realize;
> + dc->props = pnv_phb3_properties;
> +}
> +
> +static const TypeInfo pnv_phb3_type_info = {
> + .name = TYPE_PNV_PHB3,
> + .parent = TYPE_PCI_HOST_BRIDGE,
> + .instance_size = sizeof(PnvPhb3State),
> + .class_init = pnv_phb3_class_init,
> + .instance_init = pnv_phb3_initfn,
> +};
> +
> +static void pnv_phb3_register_types(void)
> +{
> + type_register_static(&pnv_phb3_type_info);
> + type_register_static(&pnv_phb3_root_bus_info);
> +}
> +
> +type_init(pnv_phb3_register_types)
> diff --git a/hw/pci-host/pnv_phb3_msi.c b/hw/pci-host/pnv_phb3_msi.c
> new file mode 100644
> index 000000000000..d4041de37b16
> --- /dev/null
> +++ b/hw/pci-host/pnv_phb3_msi.c
> @@ -0,0 +1,304 @@
> +/*
> + * QEMU PowerPC PowerNV PHB3 model
> + *
> + * Copyright (c) 2014-2017, IBM Corporation.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License, version 2, as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
> +#include "qemu/osdep.h"
> +#include "qemu/log.h"
> +#include "qapi/error.h"
> +#include "qemu-common.h"
> +#include "hw/pci-host/pnv_phb3.h"
> +#include "hw/pci/msi.h"
> +
> +static uint64_t phb3_msi_ive_addr(PnvPhb3State *phb, int srcno)
> +{
> + uint64_t ivtbar = phb->regs[PHB_IVT_BAR >> 3];
> + uint64_t phbctl = phb->regs[PHB_CONTROL >> 3];
> +
> + if (!(ivtbar & PHB_IVT_BAR_ENABLE)) {
> + qemu_log_mask(LOG_GUEST_ERROR, "Failed access to disable IVT BAR !");
> + return 0;
> + }
> +
> + if (srcno >= (ivtbar & PHB_IVT_LENGTH_MASK)) {
> + qemu_log_mask(LOG_GUEST_ERROR, "MSI out of bounds (%d vs 0x%"PRIx64")",
> + srcno, ivtbar & PHB_IVT_LENGTH_MASK);
> + return 0;
> + }
> +
> + ivtbar &= PHB_IVT_BASE_ADDRESS_MASK;
> +
> + if (phbctl & PHB_CTRL_IVE_128_BYTES) {
> + return ivtbar + 128 * srcno;
> + } else {
> + return ivtbar + 16 * srcno;
> + }
> +}
> +
> +static bool phb3_msi_read_ive(PnvPhb3State *phb, int srcno, uint64_t *out_ive)
> +{
> + uint64_t ive_addr, ive;
> +
> + ive_addr = phb3_msi_ive_addr(phb, srcno);
> + if (!ive_addr) {
> + return false;
> + }
> +
> + if (dma_memory_read(&address_space_memory, ive_addr, &ive, sizeof(ive))) {
> + qemu_log_mask(LOG_GUEST_ERROR, "Failed to read IVE at 0x%" PRIx64,
> + ive_addr);
> + return false;
> + }
> + *out_ive = be64_to_cpu(ive);
> +
> + return true;
> +}
> +
> +static void phb3_msi_set_p(Phb3MsiState *msis, int srcno, uint8_t gen)
> +{
> + uint64_t ive_addr;
> + uint8_t p = 0x01 | (gen << 1);
> +
> + ive_addr = phb3_msi_ive_addr(msis->phb, srcno);
> + if (!ive_addr) {
> + return;
> + }
> +
> + if (dma_memory_write(&address_space_memory, ive_addr + 4, &p, 1)) {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "Failed to write IVE (set P) at 0x%" PRIx64, ive_addr);
> + }
> +}
> +
> +static void phb3_msi_set_q(Phb3MsiState *msis, int srcno)
> +{
> + uint64_t ive_addr;
> + uint8_t q = 0x01;
> +
> + ive_addr = phb3_msi_ive_addr(msis->phb, srcno);
> + if (!ive_addr) {
> + return;
> + }
> +
> + if (dma_memory_write(&address_space_memory, ive_addr + 5, &q, 1)) {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "Failed to write IVE (set Q) at 0x%" PRIx64, ive_addr);
> + }
> +}
> +
> +static void phb3_msi_try_send(Phb3MsiState *msis, int srcno, bool ignore_p)
> +{
> + ICSState *ics = &msis->ics;
> + uint64_t ive;
> + uint64_t server, prio, pq, gen;
> +
> + if (!phb3_msi_read_ive(msis->phb, srcno, &ive)) {
> + return;
> + }
> +
> + server = GETFIELD(IODA2_IVT_SERVER, ive);
> + prio = GETFIELD(IODA2_IVT_PRIORITY, ive);
> + pq = GETFIELD(IODA2_IVT_Q, ive);
> + if (!ignore_p) {
> + pq |= GETFIELD(IODA2_IVT_P, ive) << 1;
> + }
> + gen = GETFIELD(IODA2_IVT_GEN, ive);
> +
> + /*
> + * The low order 2 bits are the link pointer (Type II interrupts).
> + * Shift back to get a valid IRQ server.
> + */
> + server >>= 2;
> +
> + switch (pq) {
> + case 0: /* 00 */
> + if (prio == 0xff) {
> + /* Masked, set Q */
> + phb3_msi_set_q(msis, srcno);
> + } else {
> + /* Enabled, set P and send */
> + phb3_msi_set_p(msis, srcno, gen);
> + icp_irq(ics, server, srcno + ics->offset, prio);
> + }
> + break;
> + case 2: /* 10 */
> + /* Already pending, set Q */
> + phb3_msi_set_q(msis, srcno);
> + break;
> + case 1: /* 01 */
> + case 3: /* 11 */
> + default:
> + /* Just drop stuff if Q already set */
> + break;
> + }
> +}
> +
> +static void phb3_msi_set_irq(void *opaque, int srcno, int val)
> +{
> + Phb3MsiState *msis = opaque;
> +
> + if (val) {
> + phb3_msi_try_send(msis, srcno, false);
> + }
> +}
> +
> +
> +void pnv_phb3_msi_send(Phb3MsiState *msis, uint64_t addr, uint16_t data,
> + int32_t dev_pe)
> +{
> + uint64_t ive;
> + uint16_t pe;
> + uint32_t src = ((addr >> 4) & 0xffff) | (data & 0x1f);
> +
> + if (src >= msis->ics.nr_irqs) {
> + qemu_log_mask(LOG_GUEST_ERROR, "MSI %d out of bounds", src);
> + return;
> + }
> + if (dev_pe >= 0) {
> + if (!phb3_msi_read_ive(msis->phb, src, &ive)) {
> + return;
> + }
> + pe = GETFIELD(IODA2_IVT_PE, ive);
> + if (pe != dev_pe) {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "MSI %d send by PE#%d but assigned to PE#%d",
> + src, dev_pe, pe);
> + return;
> + }
> + }
> + qemu_irq_pulse(msis->ics.qirqs[src]);
> +}
> +
> +void pnv_phb3_msi_ffi(Phb3MsiState *msis, uint64_t val)
> +{
> + /* Emit interrupt */
> + pnv_phb3_msi_send(msis, val, 0, -1);
> +
> + /* Clear FFI lock */
> + msis->phb->regs[PHB_FFI_LOCK >> 3] = 0;
> +}
> +
> +static void phb3_msi_reject(ICSState *ics, uint32_t nr)
> +{
> + Phb3MsiState *msis = PHB3_MSI(ics);
> + unsigned int srcno = nr - ics->offset;
> + unsigned int idx = srcno >> 6;
> + unsigned int bit = 1ull << (srcno & 0x3f);
> +
> + assert(srcno < PHB3_MAX_MSI);
> +
> + msis->rba[idx] |= bit;
> + msis->rba_sum |= (1u << idx);
> +}
> +
> +static void phb3_msi_resend(ICSState *ics)
> +{
> + Phb3MsiState *msis = PHB3_MSI(ics);
> + unsigned int i, j;
> +
> + if (msis->rba_sum == 0) {
> + return;
> + }
> +
> + for (i = 0; i < 32; i++) {
> + if ((msis->rba_sum & (1u << i)) == 0) {
> + continue;
> + }
> + msis->rba_sum &= ~(1u << i);
> + for (j = 0; j < 64; j++) {
> + if ((msis->rba[i] & (1ull << j)) == 0) {
> + continue;
> + }
> + msis->rba[i] &= ~(1u << j);
> + phb3_msi_try_send(msis, i * 64 + j, true);
> + }
> + }
> +}
> +
> +static void phb3_msi_reset(void *dev)
> +{
> + Phb3MsiState *msis = PHB3_MSI(dev);
> +
> + memset(msis->rba, 0, sizeof(msis->rba));
> + msis->rba_sum = 0;
> +}
> +
> +void pnv_phb3_msi_update_config(Phb3MsiState *msis, uint32_t base,
> + uint32_t count)
> +{
> + if (count > PHB3_MAX_MSI) {
> + count = PHB3_MAX_MSI;
> + }
> + msis->ics.nr_irqs = count;
> + msis->ics.offset = base;
> +}
> +
> +static void phb3_msi_initfn(Object *obj)
> +{
> + Phb3MsiState *msis = PHB3_MSI(obj);
> +
> + /* Will be overriden later */
> + msis->ics.offset = 0;
> +
> + /* Hard wire 2048, we ignore the fact that 8 of them can be
> + * taken over by LSIs at this point
> + */
> + msis->ics.nr_irqs = PHB3_MAX_MSI;
> +}
> +
> +static void phb3_msi_realize(DeviceState *dev, Error **errp)
> +{
> + Phb3MsiState *msis = PHB3_MSI(dev);
> + Object *obj;
> + Error *err = NULL;
> +
> + obj = object_property_get_link(OBJECT(dev), "phb", &err);
> + if (!obj) {
> + error_setg(errp, "%s: required link 'phb' not found: %s",
> + __func__, error_get_pretty(err));
> + return;
> + }
> + msis->phb = PNV_PHB3(obj);
> +
> + msis->ics.irqs = NULL;
> + msis->ics.qirqs = qemu_allocate_irqs(phb3_msi_set_irq, msis, PHB3_MAX_MSI);
> +
> + qemu_register_reset(phb3_msi_reset, dev);
> +}
> +
> +static void phb3_msi_class_init(ObjectClass *klass, void *data)
> +{
> + ICSStateClass *isc = ICS_BASE_CLASS(klass);
> +
> + isc->realize = phb3_msi_realize;
> + isc->reject = phb3_msi_reject;
> + isc->resend = phb3_msi_resend;
> +}
> +
> +static const TypeInfo phb3_msi_info = {
> + .name = TYPE_PHB3_MSI,
> + .parent = TYPE_ICS_BASE,
> + .instance_size = sizeof(Phb3MsiState),
> + .class_init = phb3_msi_class_init,
> + .class_size = sizeof(ICSStateClass),
> + .instance_init = phb3_msi_initfn,
> +};
> +
> +static void pnv_phb3_msi_register_types(void)
> +{
> + type_register_static(&phb3_msi_info);
> +}
> +
> +type_init(pnv_phb3_msi_register_types)
> diff --git a/hw/pci-host/pnv_phb3_pbcq.c b/hw/pci-host/pnv_phb3_pbcq.c
> new file mode 100644
> index 000000000000..2f32632c2aff
> --- /dev/null
> +++ b/hw/pci-host/pnv_phb3_pbcq.c
> @@ -0,0 +1,361 @@
> +/*
> + * QEMU PowerPC PowerNV PHB3 model
> + *
> + * Copyright (c) 2014-2017, IBM Corporation.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License, version 2, as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
> +#include "qemu/osdep.h"
> +#include "qapi/error.h"
> +#include "qemu-common.h"
> +#include "qemu/log.h"
> +#include "hw/ppc/fdt.h"
> +#include "hw/pci-host/pnv_phb3.h"
> +#include "hw/ppc/pnv.h"
> +#include "hw/ppc/pnv_xscom.h"
> +#include "hw/pci/pci_bridge.h"
> +#include "hw/pci/pci_bus.h"
> +
> +#include <libfdt.h>
> +
> +static uint64_t pnv_pbcq_nest_xscom_read(void *opaque, hwaddr addr,
> + unsigned size)
> +{
> + PnvPBCQState *pbcq = PNV_PBCQ(opaque);
> + uint32_t offset = addr >> 3;
> +
> + return pbcq->nest_regs[offset];
> +}
> +
> +static uint64_t pnv_pbcq_pci_xscom_read(void *opaque, hwaddr addr,
> + unsigned size)
> +{
> + PnvPBCQState *pbcq = PNV_PBCQ(opaque);
> + uint32_t offset = addr >> 3;
> +
> + return pbcq->pci_regs[offset];
> +}
> +
> +static uint64_t pnv_pbcq_spci_xscom_read(void *opaque, hwaddr addr,
> + unsigned size)
> +{
> + PnvPBCQState *pbcq = PNV_PBCQ(opaque);
> + uint32_t offset = addr >> 3;
> +
> + if (offset == PBCQ_SPCI_ASB_DATA) {
> + return pnv_phb3_reg_read(pbcq->phb,
> + pbcq->spci_regs[PBCQ_SPCI_ASB_ADDR], 8);
> + }
> + return pbcq->spci_regs[offset];
> +}
> +
> +static void pnv_pbcq_update_map(PnvPBCQState *pbcq)
> +{
> + uint64_t bar_en = pbcq->nest_regs[PBCQ_NEST_BAR_EN];
> + uint64_t bar, mask, size;
> +
> + /*
> + * NOTE: This will really not work well if those are remapped
> + * after the PHB has created its sub regions. We could do better
> + * if we had a way to resize regions but we don't really care
> + * that much in practice as the stuff below really only happens
> + * once early during boot
> + */
> +
> + /* Handle unmaps */
> + if (pbcq->mmio0_mapped && !(bar_en & PBCQ_NEST_BAR_EN_MMIO0)) {
> + memory_region_del_subregion(get_system_memory(), &pbcq->mmbar0);
> + pbcq->mmio0_mapped = false;
> + }
> + if (pbcq->mmio1_mapped && !(bar_en & PBCQ_NEST_BAR_EN_MMIO1)) {
> + memory_region_del_subregion(get_system_memory(), &pbcq->mmbar1);
> + pbcq->mmio1_mapped = false;
> + }
> + if (pbcq->phb_mapped && !(bar_en & PBCQ_NEST_BAR_EN_PHB)) {
> + memory_region_del_subregion(get_system_memory(), &pbcq->phbbar);
> + pbcq->phb_mapped = false;
> + }
> +
> + /* Update PHB */
> + pnv_phb3_update_regions(pbcq->phb);
> +
> + /* Handle maps */
> + if (!pbcq->mmio0_mapped && (bar_en & PBCQ_NEST_BAR_EN_MMIO0)) {
> + bar = pbcq->nest_regs[PBCQ_NEST_MMIO_BAR0] >> 14;
> + mask = pbcq->nest_regs[PBCQ_NEST_MMIO_MASK0];
> + size = ((~mask) >> 14) + 1;
> + memory_region_init(&pbcq->mmbar0, OBJECT(pbcq), "pbcq-mmio0", size);
> + memory_region_add_subregion(get_system_memory(), bar, &pbcq->mmbar0);
> + pbcq->mmio0_mapped = true;
> + pbcq->mmio0_base = bar;
> + pbcq->mmio0_size = size;
> + }
> + if (!pbcq->mmio1_mapped && (bar_en & PBCQ_NEST_BAR_EN_MMIO1)) {
> + bar = pbcq->nest_regs[PBCQ_NEST_MMIO_BAR1] >> 14;
> + mask = pbcq->nest_regs[PBCQ_NEST_MMIO_MASK1];
> + size = ((~mask) >> 14) + 1;
> + memory_region_init(&pbcq->mmbar1, OBJECT(pbcq), "pbcq-mmio1", size);
> + memory_region_add_subregion(get_system_memory(), bar, &pbcq->mmbar1);
> + pbcq->mmio1_mapped = true;
> + pbcq->mmio1_base = bar;
> + pbcq->mmio1_size = size;
> + }
> + if (!pbcq->phb_mapped && (bar_en & PBCQ_NEST_BAR_EN_PHB)) {
> + bar = pbcq->nest_regs[PBCQ_NEST_PHB_BAR] >> 14;
> + size = 0x1000;
> + memory_region_init(&pbcq->phbbar, OBJECT(pbcq), "pbcq-phb", size);
> + memory_region_add_subregion(get_system_memory(), bar, &pbcq->phbbar);
> + pbcq->phb_mapped = true;
> + }
> +
> + /* Update PHB */
> + pnv_phb3_update_regions(pbcq->phb);
> +}
> +
> +static void pnv_pbcq_nest_xscom_write(void *opaque, hwaddr addr,
> + uint64_t val, unsigned size)
> +{
> + PnvPBCQState *pbcq = PNV_PBCQ(opaque);
> + uint32_t reg = addr >> 3;
> +
> + switch (reg) {
> + case PBCQ_NEST_MMIO_BAR0:
> + case PBCQ_NEST_MMIO_BAR1:
> + case PBCQ_NEST_MMIO_MASK0:
> + case PBCQ_NEST_MMIO_MASK1:
> + if (pbcq->nest_regs[PBCQ_NEST_BAR_EN] &
> + (PBCQ_NEST_BAR_EN_MMIO0 |
> + PBCQ_NEST_BAR_EN_MMIO1)) {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "PHB3: Changing enabled BAR unsupported\n");
> + }
> + pbcq->nest_regs[reg] = val & 0xffffffffc0000000ull;
> + break;
> + case PBCQ_NEST_PHB_BAR:
> + if (pbcq->nest_regs[PBCQ_NEST_BAR_EN] & PBCQ_NEST_BAR_EN_PHB) {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "PHB3: Changing enabled BAR unsupported\n");
> + }
> + pbcq->nest_regs[reg] = val & 0xfffffffffc000000ull;
> + break;
> + case PBCQ_NEST_BAR_EN:
> + pbcq->nest_regs[reg] = val & 0xf800000000000000ull;
> + pnv_pbcq_update_map(pbcq);
> + pnv_phb3_remap_irqs(pbcq->phb);
> + break;
> + case PBCQ_NEST_IRSN_COMPARE:
> + case PBCQ_NEST_IRSN_MASK:
> + pbcq->nest_regs[reg] = val & PBCQ_NEST_IRSN_COMP_MASK;
> + pnv_phb3_remap_irqs(pbcq->phb);
> + break;
> + case PBCQ_NEST_LSI_SRC_ID:
> + pbcq->nest_regs[reg] = val & PBCQ_NEST_LSI_SRC_MASK;
> + pnv_phb3_remap_irqs(pbcq->phb);
> + break;
> + }
> +
> + /* XXX Don't error out on other regs for now ... */
> +}
> +
> +static void pnv_pbcq_pci_xscom_write(void *opaque, hwaddr addr,
> + uint64_t val, unsigned size)
> +{
> + PnvPBCQState *pbcq = PNV_PBCQ(opaque);
> + uint32_t reg = addr >> 3;
> +
> + switch (reg) {
> + case PBCQ_PCI_BAR2:
> + pbcq->pci_regs[reg] = val & 0xfffffffffc000000ull;
> + pnv_pbcq_update_map(pbcq);
> + break;
> + }
> +
> + /* XXX Don't error out on other regs for now ... */
> +}
> +
> +static void pnv_pbcq_spci_xscom_write(void *opaque, hwaddr addr,
> + uint64_t val, unsigned size)
> +{
> + PnvPBCQState *pbcq = PNV_PBCQ(opaque);
> + uint32_t reg = addr >> 3;
> +
> + switch (reg) {
> + case PBCQ_SPCI_ASB_ADDR:
> + pbcq->spci_regs[reg] = val & 0xfff;
> + break;
> + case PBCQ_SPCI_ASB_STATUS:
> + pbcq->spci_regs[reg] &= ~val;
> + break;
> + case PBCQ_SPCI_ASB_DATA:
> + pnv_phb3_reg_write(pbcq->phb, pbcq->spci_regs[PBCQ_SPCI_ASB_ADDR],
> + val, 8);
> + break;
> + case PBCQ_SPCI_AIB_CAPP_EN:
> + case PBCQ_SPCI_CAPP_SEC_TMR:
> + break;
> + }
> +
> + /* XXX Don't error out on other regs for now ... */
> +}
> +
> +static const MemoryRegionOps pnv_pbcq_nest_xscom_ops = {
> + .read = pnv_pbcq_nest_xscom_read,
> + .write = pnv_pbcq_nest_xscom_write,
> + .valid.min_access_size = 8,
> + .valid.max_access_size = 8,
> + .impl.min_access_size = 8,
> + .impl.max_access_size = 8,
> + .endianness = DEVICE_BIG_ENDIAN,
> +};
> +
> +static const MemoryRegionOps pnv_pbcq_pci_xscom_ops = {
> + .read = pnv_pbcq_pci_xscom_read,
> + .write = pnv_pbcq_pci_xscom_write,
> + .valid.min_access_size = 8,
> + .valid.max_access_size = 8,
> + .impl.min_access_size = 8,
> + .impl.max_access_size = 8,
> + .endianness = DEVICE_BIG_ENDIAN,
> +};
> +
> +static const MemoryRegionOps pnv_pbcq_spci_xscom_ops = {
> + .read = pnv_pbcq_spci_xscom_read,
> + .write = pnv_pbcq_spci_xscom_write,
> + .valid.min_access_size = 8,
> + .valid.max_access_size = 8,
> + .impl.min_access_size = 8,
> + .impl.max_access_size = 8,
> + .endianness = DEVICE_BIG_ENDIAN,
> +};
> +
> +static void pnv_pbcq_default_bars(PnvPBCQState *pbcq)
> +{
> + uint64_t mm0, mm1, reg;
> +
> + mm0 = 0x3d00000000000ull +
> + 0x4000000000ull * pbcq->chip_id +
> + 0x1000000000ull * pbcq->phb_id;
> + mm1 = 0x3ff8000000000ull +
> + 0x0200000000ull * pbcq->chip_id +
> + 0x0080000000ull * pbcq->phb_id;
> + reg = 0x3fffe40000000ull +
> + 0x0000400000ull * pbcq->chip_id +
> + 0x0000100000ull * pbcq->phb_id;
> +
> + pbcq->nest_regs[PBCQ_NEST_MMIO_BAR0] = mm0 << 14;
> + pbcq->nest_regs[PBCQ_NEST_MMIO_BAR1] = mm1 << 14;
> + pbcq->nest_regs[PBCQ_NEST_PHB_BAR] = reg << 14;
> + pbcq->nest_regs[PBCQ_NEST_MMIO_MASK0] = 0x3fff000000000ull << 14;
> + pbcq->nest_regs[PBCQ_NEST_MMIO_MASK1] = 0x3ffff80000000ull << 14;
> + pbcq->pci_regs[PBCQ_PCI_BAR2] = reg << 14;
> +}
> +
> +static void pnv_pbcq_realize(DeviceState *dev, Error **errp)
> +{
> + PnvPBCQState *pbcq = PNV_PBCQ(dev);
> + Object *obj;
> + Error *err = NULL;
> +
> + assert(pbcq->phb_id < 4);
> +
> + obj = object_property_get_link(OBJECT(dev), "phb", &err);
> + if (!obj) {
> + error_setg(errp, "%s: required link 'phb' not found: %s",
> + __func__, error_get_pretty(err));
> + return;
> + }
> + pbcq->phb = PNV_PHB3(obj);
> +
> + /* XXX Fix OPAL to do that: establish default BAR values */
> + pnv_pbcq_default_bars(pbcq);
> +
> + /* XScom region for PBCQ registers */
> + memory_region_init_io(&pbcq->xscom_nest_regs, OBJECT(dev),
> + &pnv_pbcq_nest_xscom_ops,
> + pbcq, "xscom-pbcq-nest",
> + PNV_XSCOM_PBCQ_NEST_SIZE << 3);
> + memory_region_init_io(&pbcq->xscom_pci_regs, OBJECT(dev),
> + &pnv_pbcq_pci_xscom_ops,
> + pbcq, "xscom-pbcq-pci",
> + PNV_XSCOM_PBCQ_PCI_SIZE << 3);
> + memory_region_init_io(&pbcq->xscom_spci_regs, OBJECT(dev),
> + &pnv_pbcq_spci_xscom_ops,
> + pbcq, "xscom-pbcq-spci",
> + PNV_XSCOM_PBCQ_SPCI_SIZE << 3);
> +}
> +
> +static int pnv_pbcq_populate(PnvXScomInterface *dev, void *fdt,
> + int xscom_offset)
> +{
> + const char compat[] = "ibm,power8-pbcq";
> + PnvPBCQState *pbcq = PNV_PBCQ(dev);
> + char *name;
> + int offset;
> + uint32_t lpc_pcba = PNV_XSCOM_PBCQ_NEST_BASE;
> + uint32_t reg[] = {
> + cpu_to_be32(lpc_pcba),
> + cpu_to_be32(PNV_XSCOM_PBCQ_NEST_SIZE),
> + cpu_to_be32(PNV_XSCOM_PBCQ_PCI_BASE),
> + cpu_to_be32(PNV_XSCOM_PBCQ_PCI_SIZE),
> + cpu_to_be32(PNV_XSCOM_PBCQ_SPCI_BASE),
> + cpu_to_be32(PNV_XSCOM_PBCQ_SPCI_SIZE)
> + };
> +
> + name = g_strdup_printf("pbcq@%x", lpc_pcba);
> + offset = fdt_add_subnode(fdt, xscom_offset, name);
> + _FDT(offset);
> + g_free(name);
> +
> + _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg))));
> +
> + _FDT((fdt_setprop_cell(fdt, offset, "ibm,phb-index", pbcq->phb_id)));
> + _FDT((fdt_setprop(fdt, offset, "compatible", compat,
> + sizeof(compat))));
> + return 0;
> +}
> +
> +static Property pnv_pbcq_properties[] = {
> + DEFINE_PROP_UINT32("phb-id", PnvPBCQState, phb_id, 0),
> + DEFINE_PROP_UINT32("chip-id", PnvPBCQState, chip_id, 0),
> + DEFINE_PROP_END_OF_LIST(),
> +
> +};
> +
> +static void pnv_pbcq_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> + PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass);
> +
> + xdc->populate = pnv_pbcq_populate;
> +
> + dc->realize = pnv_pbcq_realize;
> + dc->props = pnv_pbcq_properties;
> +}
> +
> +static const TypeInfo pnv_pbcq_type_info = {
> + .name = TYPE_PNV_PBCQ,
> + .parent = TYPE_DEVICE,
> + .instance_size = sizeof(PnvPBCQState),
> + .class_init = pnv_pbcq_class_init,
> + .interfaces = (InterfaceInfo[]) {
> + { TYPE_PNV_XSCOM_INTERFACE },
> + { }
> + }
> +};
> +
> +static void pnv_pbcq_register_types(void)
> +{
> + type_register_static(&pnv_pbcq_type_info);
> +}
> +
> +type_init(pnv_pbcq_register_types)
> diff --git a/hw/pci-host/pnv_phb3_rc.c b/hw/pci-host/pnv_phb3_rc.c
> new file mode 100644
> index 000000000000..b68e694518ca
> --- /dev/null
> +++ b/hw/pci-host/pnv_phb3_rc.c
> @@ -0,0 +1,134 @@
> +/*
> + * QEMU PowerPC PowerNV PHB3 model
> + *
> + * Copyright (c) 2014-2017, IBM Corporation.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License, version 2, as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
> +#include "qemu/osdep.h"
> +#include "qapi/error.h"
> +#include "qemu-common.h"
> +#include "hw/pci-host/pnv_phb3.h"
> +#include "hw/pci/pcie_port.h"
> +
> +static void pnv_phb3_rc_write_config(PCIDevice *d,
> + uint32_t address, uint32_t val, int len)
> +{
> + uint32_t root_cmd =
> + pci_get_long(d->config + d->exp.aer_cap + PCI_ERR_ROOT_COMMAND);
> +
> + pci_bridge_write_config(d, address, val, len);
> + pcie_cap_slot_write_config(d, address, val, len);
> + pcie_aer_write_config(d, address, val, len);
> + pcie_aer_root_write_config(d, address, val, len, root_cmd);
> +}
> +
> +static void pnv_phb3_rc_reset(DeviceState *qdev)
> +{
> + PCIDevice *d = PCI_DEVICE(qdev);
> +
> + pcie_cap_root_reset(d);
> + pcie_cap_deverr_reset(d);
> + pcie_cap_slot_reset(d);
> + pcie_cap_arifwd_reset(d);
> + pcie_aer_root_reset(d);
> + pci_bridge_reset(qdev);
> + pci_bridge_disable_base_limit(d);
> +}
> +
> +static void pnv_phb3_rc_realize(PCIDevice *d, Error **errp)
> +{
> + PCIEPort *p = PCIE_PORT(d);
> + PCIESlot *s = PCIE_SLOT(d);
> + int rc;
> + Error *err = NULL;
> +
> + DEVICE(d)->id = "pcie";
> + pci_bridge_initfn(d, TYPE_PCIE_BUS);
> +
> + /* TODO Make that a property ? Allow for only one device (8 functions) */
> + pci_bridge_get_sec_bus(PCI_BRIDGE(d))->devfn_max = 8;
> +
> + pcie_port_init_reg(d);
> +
> + rc = pcie_cap_init(d, 0x48, PCI_EXP_TYPE_ROOT_PORT, p->port);
> + if (rc < 0) {
> + error_setg(errp, "phb3-rc: pcie_cap_init() error %d !", rc);
> + goto err_bridge;
> + }
> + pcie_cap_arifwd_init(d);
> + pcie_cap_deverr_init(d);
> + pcie_cap_slot_init(d, s->slot);
> + pcie_chassis_create(s->chassis);
> + rc = pcie_chassis_add_slot(s);
> + if (rc < 0) {
> + error_setg(errp, "phb3-rc: pcie_chassis_add_slot() error %d !", rc);
> + goto err_pcie_cap;
> + }
> + pcie_cap_root_init(d);
> + rc = pcie_aer_init(d, PCI_ERR_VER, 0x100, PCI_ERR_SIZEOF, &err);
> + if (rc < 0) {
> + error_propagate(errp, err);
> + goto err_slot;
> + }
> + pcie_aer_root_init(d);
> + return;
> +
> +err_slot:
> + pcie_chassis_del_slot(s);
> +err_pcie_cap:
> + pcie_cap_exit(d);
> +err_bridge:
> + pci_bridge_exitfn(d);
> +}
> +
> +static void pnv_phb3_rc_exit(PCIDevice *d)
> +{
> + PCIESlot *s = PCIE_SLOT(d);
> +
> + pcie_aer_exit(d);
> + pcie_chassis_del_slot(s);
> + pcie_cap_exit(d);
> + pci_bridge_exitfn(d);
> +}
> +
> +static void pnv_phb3_rc_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> + PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
> +
> + k->is_express = 1;
> + k->is_bridge = 1;
> + k->realize = pnv_phb3_rc_realize;
> + k->exit = pnv_phb3_rc_exit;
> + k->config_write = pnv_phb3_rc_write_config;
> + k->vendor_id = PCI_VENDOR_ID_IBM;
> + k->device_id = 0x03dc;
> + k->revision = 0;
> + set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
> + dc->desc = "IBM PHB3 PCIE Root Port";
> + dc->reset = pnv_phb3_rc_reset;
> +}
> +
> +static const TypeInfo pnv_phb3_rc_info = {
> + .name = TYPE_PNV_PHB3_RC,
> + .parent = TYPE_PCIE_SLOT,
> + .class_init = pnv_phb3_rc_class_init,
> +};
> +
> +static void pnv_phb3_rc_register_types(void)
> +{
> + type_register_static(&pnv_phb3_rc_info);
> +}
> +
> +type_init(pnv_phb3_rc_register_types)
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index df0a88c3e252..db6e078edcea 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -43,6 +43,11 @@
> #include "hw/isa/isa.h"
> #include "hw/char/serial.h"
> #include "hw/timer/mc146818rtc.h"
> +#include "hw/pci/pci.h"
> +#include "hw/pci/pci_bus.h"
> +#include "hw/pci/pci_bridge.h"
> +#include "hw/pci/msi.h"
> +#include "hw/pci-host/pnv_phb3.h"
>
> #include <libfdt.h>
>
> @@ -659,6 +664,7 @@ static void ppc_powernv_init(MachineState *machine)
> object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id",
> &error_fatal);
> object_property_set_int(chip, smp_cores, "nr-cores", &error_fatal);
> + object_property_set_int(chip, 1, "num-phbs", &error_fatal);
> object_property_set_bool(chip, true, "realized", &error_fatal);
> }
> g_free(chip_typename);
> @@ -905,6 +911,41 @@ static void pnv_chip_icp_realize(PnvChip *chip, Error **errp)
> g_free(typename);
> }
>
> +static PnvPhb3State *pnv_chip_phb_realize(PnvChip *chip, int i, Error **errp)
> +{
> + Error *error = NULL;
> + PnvPhb3State *phb = NULL;
> + Object *obj;
> + char name[32];
> +
> + snprintf(name, sizeof(name), "phb[%d]", i);
> + obj = object_new(TYPE_PNV_PHB3);
> + qdev_set_parent_bus(DEVICE(obj), sysbus_get_default());
> + object_property_set_int(obj, i, "phb-id", &error_fatal);
> + object_property_set_int(obj, chip->chip_id, "chip-id", &error_fatal);
> + object_property_add_child(OBJECT(chip), name, obj, &error_fatal);
> + object_property_add_const_link(obj, "xics", qdev_get_machine(),
> + &error_fatal);
> + object_property_set_bool(obj, true, "realized", &error);
> + if (error) {
> + error_propagate(errp, error);
> + return NULL;
> + }
> +
> + phb = PNV_PHB3(obj);
> +
> + memory_region_add_subregion(&chip->xscom,
> + (PNV_XSCOM_PBCQ_NEST_BASE + 0x400 * i) << 3,
> + &phb->pbcq->xscom_nest_regs);
> + memory_region_add_subregion(&chip->xscom,
> + (PNV_XSCOM_PBCQ_PCI_BASE + 0x400 * i) << 3,
> + &phb->pbcq->xscom_pci_regs);
> + memory_region_add_subregion(&chip->xscom,
> + (PNV_XSCOM_PBCQ_SPCI_BASE + 0x040 * i) << 3,
> + &phb->pbcq->xscom_spci_regs);
> + return phb;
> +}
> +
> static void pnv_chip_realize(DeviceState *dev, Error **errp)
> {
> PnvChip *chip = PNV_CHIP(dev);
> @@ -1003,6 +1044,18 @@ static void pnv_chip_realize(DeviceState *dev, Error **errp)
> return;
> }
> pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip->occ.xscom_regs);
> +
> + /* MSIs are supported on this platform */
> + msi_nonbroken = true;
> +
> + /* Create Power system Host Bridges 3 (PHB3) */
> + for (i = 0; i < chip->num_phbs; i++) {
> + chip->phbs[i] = pnv_chip_phb_realize(chip, i, &error);
> + if (error) {
> + error_propagate(errp, error);
> + return;
> + }
> + }
> }
>
> static Property pnv_chip_properties[] = {
> @@ -1011,6 +1064,7 @@ static Property pnv_chip_properties[] = {
> DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0),
> DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1),
> DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0),
> + DEFINE_PROP_UINT32("num-phbs", PnvChip, num_phbs, 1),
> DEFINE_PROP_END_OF_LIST(),
> };
>
> @@ -1035,12 +1089,20 @@ static const TypeInfo pnv_chip_info = {
> static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
> {
> PnvMachineState *pnv = POWERNV_MACHINE(xi);
> - int i;
> + int i, j;
>
> for (i = 0; i < pnv->num_chips; i++) {
> if (ics_valid_irq(&pnv->chips[i]->psi.ics, irq)) {
> return &pnv->chips[i]->psi.ics;
> }
> + for (j = 0; j < pnv->chips[i]->num_phbs; j++) {
> + if (ics_valid_irq(pnv->chips[i]->phbs[j]->lsi_ics, irq)) {
> + return pnv->chips[i]->phbs[j]->lsi_ics;
> + }
> + if (ics_valid_irq(ICS_BASE(pnv->chips[i]->phbs[j]->msis), irq)) {
> + return ICS_BASE(pnv->chips[i]->phbs[j]->msis);
> + }
> + }
> }
> return NULL;
> }
> @@ -1048,10 +1110,14 @@ static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
> static void pnv_ics_resend(XICSFabric *xi)
> {
> PnvMachineState *pnv = POWERNV_MACHINE(xi);
> - int i;
> + int i, j;
>
> for (i = 0; i < pnv->num_chips; i++) {
> ics_resend(&pnv->chips[i]->psi.ics);
> + for (j = 0; j < pnv->chips[i]->num_phbs; j++) {
> + ics_resend(pnv->chips[i]->phbs[j]->lsi_ics);
> + ics_resend(ICS_BASE(pnv->chips[i]->phbs[j]->msis));
> + }
> }
> }
>
> @@ -1082,7 +1148,7 @@ static void pnv_pic_print_info(InterruptStatsProvider *obj,
> Monitor *mon)
> {
> PnvMachineState *pnv = POWERNV_MACHINE(obj);
> - int i;
> + int i, j;
> CPUState *cs;
>
> CPU_FOREACH(cs) {
> @@ -1093,6 +1159,10 @@ static void pnv_pic_print_info(InterruptStatsProvider *obj,
>
> for (i = 0; i < pnv->num_chips; i++) {
> ics_pic_print_info(&pnv->chips[i]->psi.ics, mon);
> + for (j = 0; j < pnv->chips[i]->num_phbs; j++) {
> + ics_pic_print_info(pnv->chips[i]->phbs[j]->lsi_ics, mon);
> + ics_pic_print_info(ICS_BASE(pnv->chips[i]->phbs[j]->msis), mon);
> + }
> }
> }
>
> diff --git a/hw/ppc/pnv_xscom.c b/hw/ppc/pnv_xscom.c
> index 38bc85f117f6..a75e6c95b885 100644
> --- a/hw/ppc/pnv_xscom.c
> +++ b/hw/ppc/pnv_xscom.c
> @@ -255,7 +255,10 @@ int pnv_xscom_populate(PnvChip *chip, void *fdt, int root_offset)
> args.fdt = fdt;
> args.xscom_offset = xscom_offset;
>
> - object_child_foreach(OBJECT(chip), xscom_populate_child, &args);
> + /* Some PnvXScomInterface objects lie a bit deeper (PnvPBCQState)
> + * than the first layer, so we need to loop on the whole object
> + * hierarchy to catch them */
> + object_child_foreach_recursive(OBJECT(chip), xscom_populate_child, &args);
> return 0;
> }
>
> diff --git a/include/hw/pci-host/pnv_phb3.h b/include/hw/pci-host/pnv_phb3.h
> new file mode 100644
> index 000000000000..ef7cdf6b2089
> --- /dev/null
> +++ b/include/hw/pci-host/pnv_phb3.h
> @@ -0,0 +1,156 @@
> +/*
> + * QEMU PowerPC PowerNV PHB3 model
> + *
> + * Copyright (c) 2014-2017, IBM Corporation.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License, version 2, as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef PCI_HOST_PNV_PHB3_H
> +#define PCI_HOST_PNV_PHB3_H
> +
> +#include "hw/pci/pci_host.h"
> +#include "hw/ppc/xics.h"
> +#include "hw/pci-host/pnv_phb3_regs.h"
> +
> +#define PNV_PHB3_NUM_M64 16
> +#define PNV_PHB3_NUM_REGS (0x1000 >> 3)
> +#define PNV_PHB3_NUM_LSI 8
> +#define PNV_PHB3_NUM_PE 256
> +
> +#define PCI_MMIO_TOTAL_SIZE (0x1ull << 60)
> +
> +#define IODA2_PCI_BUS_MAX 256
> +
> +typedef struct PnvPBCQState PnvPBCQState;
> +typedef struct PnvPhb3State PnvPhb3State;
> +typedef struct PnvPhb3DMASpace PnvPhb3DMASpace;
> +
> +/* Similarily with pnv_phb3_msi */
> +typedef struct Phb3MsiState Phb3MsiState;
> +
> +/* We have one such address space wrapper per possible device
> + * under the PHB since they need to be assigned statically at
> + * qemu device creation time. The relationship to a PE is done
> + * later dynamically. This means we can potentially create a lot
> + * of these guys. Q35 stores them as some kind of radix tree but
> + * we never really need to do fast lookups so instead we simply
> + * keep a QLIST of them for now, we can add the radix if needed
> + * later on.
> + *
> + * We do cache the PE number to speed things up a bit though.
> + */
> +struct PnvPhb3DMASpace {
> + PCIBus *bus;
> + uint8_t devfn;
> + int pe_num; /* Cached PE number */
> +#define PHB_INVALID_PE (-1)
> + PnvPhb3State *phb;
> + AddressSpace dma_as;
> + MemoryRegion dma_mr;
> + MemoryRegion msi32_mr;
> + MemoryRegion msi64_mr;
> + bool msi32_mapped;
> + bool msi64_mapped;
> + QLIST_ENTRY(PnvPhb3DMASpace) list;
> +};
> +
> +struct PnvPhb3State {
> + PCIHostState parent_obj;
> +
> + uint32_t chip_id;
> + uint32_t phb_id;
> + MemoryRegion mr_m32;
> + MemoryRegion mr_m64[PNV_PHB3_NUM_M64];
> + MemoryRegion mr_regs;
> + bool regs_mapped;
> + bool m32_mapped;
> + bool m64_mapped[PNV_PHB3_NUM_M64];
> + MemoryRegion pci_mmio;
> + MemoryRegion pci_io;
> + uint64_t regs[PNV_PHB3_NUM_REGS];
> + PnvPBCQState *pbcq;
> + uint64_t ioda_LIST[8];
> + uint64_t ioda_LXIVT[8];
> + uint64_t ioda_TVT[512];
> + uint64_t ioda_M64BT[16];
> + uint64_t ioda_MDT[256];
> + uint64_t ioda_PEEV[4];
> + uint32_t total_irq;
> + ICSState *lsi_ics;
> + Phb3MsiState *msis;
> + QLIST_HEAD(, PnvPhb3DMASpace) dma_spaces;
> +};
> +
> +struct PnvPBCQState {
> + DeviceState parent;
> +
> + uint32_t chip_id;
> + uint32_t phb_id;
> + uint32_t nest_xbase;
> + uint32_t spci_xbase;
> + uint32_t pci_xbase;
> + uint64_t nest_regs[PBCQ_NEST_REGS_COUNT];
> + uint64_t spci_regs[PBCQ_SPCI_REGS_COUNT];
> + uint64_t pci_regs[PBCQ_PCI_REGS_COUNT];
> + MemoryRegion mmbar0;
> + MemoryRegion mmbar1;
> + MemoryRegion phbbar;
> + bool mmio0_mapped;
> + bool mmio1_mapped;
> + bool phb_mapped;
> + uint64_t mmio0_base;
> + uint64_t mmio0_size;
> + uint64_t mmio1_base;
> + uint64_t mmio1_size;
> + PnvPhb3State *phb;
> +
> + MemoryRegion xscom_nest_regs;
> + MemoryRegion xscom_pci_regs;
> + MemoryRegion xscom_spci_regs;
> +};
> +
> +#define TYPE_PNV_PBCQ "pnv-pbcq"
> +#define PNV_PBCQ(obj) \
> + OBJECT_CHECK(PnvPBCQState, (obj), TYPE_PNV_PBCQ)
> +
> +
> +#define TYPE_PNV_PHB3 "pnv-phb3"
> +#define PNV_PHB3(obj) \
> + OBJECT_CHECK(PnvPhb3State, (obj), TYPE_PNV_PHB3)
> +
> +#define TYPE_PNV_PHB3_RC "pnv-phb3-rc"
> +
> +#define PHB3_MAX_MSI 2048
> +
> +typedef struct Phb3MsiState {
> + ICSState ics;
> + PnvPhb3State *phb;
> + uint64_t rba[PHB3_MAX_MSI / 64];
> + uint32_t rba_sum;
> +} Phb3MsiState;
> +
> +#define TYPE_PHB3_MSI "phb3-msi"
> +#define PHB3_MSI(obj) OBJECT_CHECK(Phb3MsiState, (obj), TYPE_PHB3_MSI)
> +
> +uint64_t pnv_phb3_reg_read(void *opaque, hwaddr off, unsigned size);
> +void pnv_phb3_reg_write(void *opaque, hwaddr off, uint64_t val, unsigned size);
> +void pnv_phb3_update_regions(PnvPhb3State *phb);
> +void pnv_phb3_remap_irqs(PnvPhb3State *phb);
> +void pnv_phb3_msi_update_config(Phb3MsiState *msis, uint32_t base,
> + uint32_t count);
> +void pnv_phb3_msi_send(Phb3MsiState *msis, uint64_t addr, uint16_t data,
> + int32_t dev_pe);
> +void pnv_phb3_msi_ffi(Phb3MsiState *msis, uint64_t val);
> +
> +#endif /* PCI_HOST_PNV_PHB3_H */
> diff --git a/include/hw/pci-host/pnv_phb3_regs.h b/include/hw/pci-host/pnv_phb3_regs.h
> new file mode 100644
> index 000000000000..4c3187434355
> --- /dev/null
> +++ b/include/hw/pci-host/pnv_phb3_regs.h
> @@ -0,0 +1,506 @@
> +/* Copyright (c) 2013-2017, IBM Corporation.
> + *
> + * Licensed under the Apache License, Version 2.0 (the "License");
> + * you may not use this file except in compliance with the License.
> + * You may obtain a copy of the License at
> + *
> + * http://www.apache.org/licenses/LICENSE-2.0
> + *
> + * Unless required by applicable law or agreed to in writing, software
> + * distributed under the License is distributed on an "AS IS" BASIS,
> + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
> + * implied.
> + * See the License for the specific language governing permissions and
> + * limitations under the License.
> + */
> +
> +#ifndef PCI_HOST_PNV_PHB3_REGS_H
> +#define PCI_HOST_PNV_PHB3_REGS_H
> +
> +#define PPC_BIT(bit) (0x8000000000000000UL >> (bit))
> +#define PPC_BIT32(bit) (0x80000000UL >> (bit))
> +#define PPC_BIT8(bit) (0x80UL >> (bit))
> +#define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
> +#define PPC_BITMASK32(bs, be) ((PPC_BIT32(bs) - PPC_BIT32(be)) | \
> + PPC_BIT32(bs))
> +#define PPC_BITLSHIFT(be) (63 - (be))
> +#define PPC_BITLSHIFT32(be) (31 - (be))
> +
> +/* Extract field fname from val */
> +#define GETFIELD(fname, val) \
> + (((val) & fname##_MASK) >> fname##_LSH)
> +
> +/* Set field fname of oval to fval
> + * NOTE: oval isn't modified, the combined result is returned
> + */
> +#define SETFIELD(fname, oval, fval) \
> + (((oval) & ~fname##_MASK) | \
> + ((((typeof(oval))(fval)) << fname##_LSH) & fname##_MASK))
> +
> +/*
> + * PBCQ XSCOM registers
> + */
> +
> +#define PBCQ_NEST_IRSN_COMPARE 0x1a
> +#define PBCQ_NEST_IRSN_COMP_MASK PPC_BITMASK(0, 18)
> +#define PBCQ_NEST_IRSN_COMP_LSH PPC_BITLSHIFT(18)
> +#define PBCQ_NEST_IRSN_MASK 0x1b
> +#define PBCQ_NEST_LSI_SRC_ID 0x1f
> +#define PBCQ_NEST_LSI_SRC_MASK PPC_BITMASK(0, 7)
> +#define PBCQ_NEST_LSI_SRC_LSH PPC_BITLSHIFT(7)
> +#define PBCQ_NEST_REGS_COUNT 0x46
> +#define PBCQ_NEST_MMIO_BAR0 0x40
> +#define PBCQ_NEST_MMIO_BAR1 0x41
> +#define PBCQ_NEST_PHB_BAR 0x42
> +#define PBCQ_NEST_MMIO_MASK0 0x43
> +#define PBCQ_NEST_MMIO_MASK1 0x44
> +#define PBCQ_NEST_BAR_EN 0x45
> +#define PBCQ_NEST_BAR_EN_MMIO0 PPC_BIT(0)
> +#define PBCQ_NEST_BAR_EN_MMIO1 PPC_BIT(1)
> +#define PBCQ_NEST_BAR_EN_PHB PPC_BIT(2)
> +#define PBCQ_NEST_BAR_EN_IRSN_RX PPC_BIT(3)
> +#define PBCQ_NEST_BAR_EN_IRSN_TX PPC_BIT(4)
> +
> +#define PBCQ_PCI_REGS_COUNT 0x15
> +#define PBCQ_PCI_BAR2 0x0b
> +
> +#define PBCQ_SPCI_REGS_COUNT 0x5
> +#define PBCQ_SPCI_ASB_ADDR 0x0
> +#define PBCQ_SPCI_ASB_STATUS 0x1
> +#define PBCQ_SPCI_ASB_DATA 0x2
> +#define PBCQ_SPCI_AIB_CAPP_EN 0x3
> +#define PBCQ_SPCI_CAPP_SEC_TMR 0x4
> +
> +/*
> + * PHB MMIO registers
> + */
> +
> +/* PHB Fundamental register set A */
> +#define PHB_LSI_SOURCE_ID 0x100
> +#define PHB_LSI_SRC_ID_MASK PPC_BITMASK(5, 12)
> +#define PHB_LSI_SRC_ID_LSH PPC_BITLSHIFT(12)
> +#define PHB_DMA_CHAN_STATUS 0x110
> +#define PHB_DMA_CHAN_ANY_ERR PPC_BIT(27)
> +#define PHB_DMA_CHAN_ANY_ERR1 PPC_BIT(28)
> +#define PHB_DMA_CHAN_ANY_FREEZE PPC_BIT(29)
> +#define PHB_CPU_LOADSTORE_STATUS 0x120
> +#define PHB_CPU_LS_ANY_ERR PPC_BIT(27)
> +#define PHB_CPU_LS_ANY_ERR1 PPC_BIT(28)
> +#define PHB_CPU_LS_ANY_FREEZE PPC_BIT(29)
> +#define PHB_DMA_MSI_NODE_ID 0x128
> +#define PHB_DMAMSI_NID_FIXED PPC_BIT(0)
> +#define PHB_DMAMSI_NID_MASK PPC_BITMASK(24, 31)
> +#define PHB_DMAMSI_NID_LSH PPC_BITLSHIFT(31)
> +#define PHB_CONFIG_DATA 0x130
> +#define PHB_LOCK0 0x138
> +#define PHB_CONFIG_ADDRESS 0x140
> +#define PHB_CA_ENABLE PPC_BIT(0)
> +#define PHB_CA_BUS_MASK PPC_BITMASK(4, 11)
> +#define PHB_CA_BUS_LSH PPC_BITLSHIFT(11)
> +#define PHB_CA_DEV_MASK PPC_BITMASK(12, 16)
> +#define PHB_CA_DEV_LSH PPC_BITLSHIFT(16)
> +#define PHB_CA_FUNC_MASK PPC_BITMASK(17, 19)
> +#define PHB_CA_FUNC_LSH PPC_BITLSHIFT(19)
> +#define PHB_CA_REG_MASK PPC_BITMASK(20, 31)
> +#define PHB_CA_REG_LSH PPC_BITLSHIFT(31)
> +#define PHB_CA_PE_MASK PPC_BITMASK(40, 47)
> +#define PHB_CA_PE_LSH PPC_BITLSHIFT(47)
> +#define PHB_LOCK1 0x148
> +#define PHB_IVT_BAR 0x150
> +#define PHB_IVT_BAR_ENABLE PPC_BIT(0)
> +#define PHB_IVT_BASE_ADDRESS_MASK PPC_BITMASK(14, 48)
> +#define PHB_IVT_BASE_ADDRESS_LSH PPC_BITLSHIFT(48)
> +#define PHB_IVT_LENGTH_MASK PPC_BITMASK(52, 63)
> +#define PHB_IVT_LENGTH_ADDRESS_LSH PPC_BITLSHIFT(63)
> +#define PHB_RBA_BAR 0x158
> +#define PHB_RBA_BAR_ENABLE PPC_BIT(0)
> +#define PHB_RBA_BASE_ADDRESS_MASK PPC_BITMASK(14, 55)
> +#define PHB_RBA_BASE_ADDRESS_LSH PPC_BITLSHIFT(55)
> +#define PHB_PHB3_CONFIG 0x160
> +#define PHB_PHB3C_64B_TCE_EN PPC_BIT(2)
> +#define PHB_PHB3C_32BIT_MSI_EN PPC_BIT(8)
> +#define PHB_PHB3C_64BIT_MSI_EN PPC_BIT(14)
> +#define PHB_PHB3C_M32_EN PPC_BIT(16)
> +#define PHB_RTT_BAR 0x168
> +#define PHB_RTT_BAR_ENABLE PPC_BIT(0)
> +#define PHB_RTT_BASE_ADDRESS_MASK PPC_BITMASK(14, 46)
> +#define PHB_RTT_BASE_ADDRESS_LSH PPC_BITLSHIFT(46)
> +#define PHB_PELTV_BAR 0x188
> +#define PHB_PELTV_BAR_ENABLE PPC_BIT(0)
> +#define PHB_PELTV_BASE_ADDRESS_MASK PPC_BITMASK(14, 50)
> +#define PHB_PELTV_BASE_ADDRESS_LSH PPC_BITLSHIFT(50)
> +#define PHB_M32_BASE_ADDR 0x190
> +#define PHB_M32_BASE_MASK 0x198
> +#define PHB_M32_START_ADDR 0x1a0
> +#define PHB_PEST_BAR 0x1a8
> +#define PHB_PEST_BAR_ENABLE PPC_BIT(0)
> +#define PHB_PEST_BASE_ADDRESS_MASK PPC_BITMASK(14, 51)
> +#define PHB_PEST_BASE_ADDRESS_LSH PPC_BITLSHIFT(51)
> +#define PHB_M64_UPPER_BITS 0x1f0
> +#define PHB_INTREP_TIMER 0x1f8
> +#define PHB_DMARD_SYNC 0x200
> +#define PHB_RTC_INVALIDATE 0x208
> +#define PHB_RTC_INVALIDATE_ALL PPC_BIT(0)
> +#define PHB_RTC_INVALIDATE_RID_MASK PPC_BITMASK(16, 31)
> +#define PHB_RTC_INVALIDATE_RID_LSH PPC_BITLSHIFT(31)
> +#define PHB_TCE_KILL 0x210
> +#define PHB_TCE_KILL_ALL PPC_BIT(0)
> +#define PHB_TCE_SPEC_CTL 0x218
> +#define PHB_IODA_ADDR 0x220
> +#define PHB_IODA_AD_AUTOINC PPC_BIT(0)
> +#define PHB_IODA_AD_TSEL_MASK PPC_BITMASK(11, 15)
> +#define PHB_IODA_AD_TSEL_LSH PPC_BITLSHIFT(15)
> +#define PHB_IODA_AD_TADR_MASK PPC_BITMASK(55, 63)
> +#define PHB_IODA_AD_TADR_LSH PPC_BITLSHIFT(63)
> +#define PHB_IODA_DATA0 0x228
> +#define PHB_FFI_REQUEST 0x238
> +#define PHB_FFI_LOCK_CLEAR PPC_BIT(3)
> +#define PHB_FFI_REQUEST_ISN_MASK PPC_BITMASK(49, 59)
> +#define PHB_FFI_REQUEST_ISN_LSH PPC_BITLSHIFT(59)
> +#define PHB_FFI_LOCK 0x240
> +#define PHB_FFI_LOCK_STATE PPC_BIT(0)
> +#define PHB_XIVE_UPDATE 0x248 /* Broken in DD1 */
> +#define PHB_PHB3_GEN_CAP 0x250
> +#define PHB_PHB3_TCE_CAP 0x258
> +#define PHB_PHB3_IRQ_CAP 0x260
> +#define PHB_PHB3_EEH_CAP 0x268
> +#define PHB_IVC_INVALIDATE 0x2a0
> +#define PHB_IVC_INVALIDATE_ALL PPC_BIT(0)
> +#define PHB_IVC_INVALIDATE_SID_MASK PPC_BITMASK(16, 31)
> +#define PHB_IVC_INVALIDATE_SID_LSH PPC_BITLSHIFT(31)
> +#define PHB_IVC_UPDATE 0x2a8
> +#define PHB_IVC_UPDATE_ENABLE_P PPC_BIT(0)
> +#define PHB_IVC_UPDATE_ENABLE_Q PPC_BIT(1)
> +#define PHB_IVC_UPDATE_ENABLE_SERVER PPC_BIT(2)
> +#define PHB_IVC_UPDATE_ENABLE_PRI PPC_BIT(3)
> +#define PHB_IVC_UPDATE_ENABLE_GEN PPC_BIT(4)
> +#define PHB_IVC_UPDATE_ENABLE_CON PPC_BIT(5)
> +#define PHB_IVC_UPDATE_GEN_MATCH_MASK PPC_BITMASK(6, 7)
> +#define PHB_IVC_UPDATE_GEN_MATCH_LSH PPC_BITLSHIFT(7)
> +#define PHB_IVC_UPDATE_SERVER_MASK PPC_BITMASK(8, 23)
> +#define PHB_IVC_UPDATE_SERVER_LSH PPC_BITLSHIFT(23)
> +#define PHB_IVC_UPDATE_PRI_MASK PPC_BITMASK(24, 31)
> +#define PHB_IVC_UPDATE_PRI_LSH PPC_BITLSHIFT(31)
> +#define PHB_IVC_UPDATE_GEN_MASK PPC_BITMASK(32, 33)
> +#define PHB_IVC_UPDATE_GEN_LSH PPC_BITLSHIFT(33)
> +#define PHB_IVC_UPDATE_P_MASK PPC_BITMASK(34, 34)
> +#define PHB_IVC_UPDATE_P_LSH PPC_BITLSHIFT(34)
> +#define PHB_IVC_UPDATE_Q_MASK PPC_BITMASK(35, 35)
> +#define PHB_IVC_UPDATE_Q_LSH PPC_BITLSHIFT(35)
> +#define PHB_IVC_UPDATE_SID_MASK PPC_BITMASK(48, 63)
> +#define PHB_IVC_UPDATE_SID_LSH PPC_BITLSHIFT(63)
> +#define PHB_PAPR_ERR_INJ_CTL 0x2b0
> +#define PHB_PAPR_ERR_INJ_CTL_INB PPC_BIT(0)
> +#define PHB_PAPR_ERR_INJ_CTL_OUTB PPC_BIT(1)
> +#define PHB_PAPR_ERR_INJ_CTL_STICKY PPC_BIT(2)
> +#define PHB_PAPR_ERR_INJ_CTL_CFG PPC_BIT(3)
> +#define PHB_PAPR_ERR_INJ_CTL_RD PPC_BIT(4)
> +#define PHB_PAPR_ERR_INJ_CTL_WR PPC_BIT(5)
> +#define PHB_PAPR_ERR_INJ_CTL_FREEZE PPC_BIT(6)
> +#define PHB_PAPR_ERR_INJ_ADDR 0x2b8
> +#define PHB_PAPR_ERR_INJ_ADDR_MMIO_MASK PPC_BITMASK(16, 63)
> +#define PHB_PAPR_ERR_INJ_ADDR_MMIO_LSH PPC_BITLSHIFT(63)
> +#define PHB_PAPR_ERR_INJ_MASK 0x2c0
> +#define PHB_PAPR_ERR_INJ_MASK_CFG_MASK PPC_BITMASK(4, 11)
> +#define PHB_PAPR_ERR_INJ_MASK_CFG_LSH PPC_BITLSHIFT(11)
> +#define PHB_PAPR_ERR_INJ_MASK_MMIO_MASK PPC_BITMASK(16, 63)
> +#define PHB_PAPR_ERR_INJ_MASK_MMIO_LSH PPC_BITLSHIFT(63)
> +#define PHB_ETU_ERR_SUMMARY 0x2c8
> +
> +/* UTL registers */
> +#define UTL_SYS_BUS_CONTROL 0x400
> +#define UTL_STATUS 0x408
> +#define UTL_SYS_BUS_AGENT_STATUS 0x410
> +#define UTL_SYS_BUS_AGENT_ERR_SEVERITY 0x418
> +#define UTL_SYS_BUS_AGENT_IRQ_EN 0x420
> +#define UTL_SYS_BUS_BURST_SZ_CONF 0x440
> +#define UTL_REVISION_ID 0x448
> +#define UTL_BCLK_DOMAIN_DBG1 0x460
> +#define UTL_BCLK_DOMAIN_DBG2 0x468
> +#define UTL_BCLK_DOMAIN_DBG3 0x470
> +#define UTL_BCLK_DOMAIN_DBG4 0x478
> +#define UTL_BCLK_DOMAIN_DBG5 0x480
> +#define UTL_BCLK_DOMAIN_DBG6 0x488
> +#define UTL_OUT_POST_HDR_BUF_ALLOC 0x4c0
> +#define UTL_OUT_POST_DAT_BUF_ALLOC 0x4d0
> +#define UTL_IN_POST_HDR_BUF_ALLOC 0x4e0
> +#define UTL_IN_POST_DAT_BUF_ALLOC 0x4f0
> +#define UTL_OUT_NP_BUF_ALLOC 0x500
> +#define UTL_IN_NP_BUF_ALLOC 0x510
> +#define UTL_PCIE_TAGS_ALLOC 0x520
> +#define UTL_GBIF_READ_TAGS_ALLOC 0x530
> +#define UTL_PCIE_PORT_CONTROL 0x540
> +#define UTL_PCIE_PORT_STATUS 0x548
> +#define UTL_PCIE_PORT_ERROR_SEV 0x550
> +#define UTL_PCIE_PORT_IRQ_EN 0x558
> +#define UTL_RC_STATUS 0x560
> +#define UTL_RC_ERR_SEVERITY 0x568
> +#define UTL_RC_IRQ_EN 0x570
> +#define UTL_EP_STATUS 0x578
> +#define UTL_EP_ERR_SEVERITY 0x580
> +#define UTL_EP_ERR_IRQ_EN 0x588
> +#define UTL_PCI_PM_CTRL1 0x590
> +#define UTL_PCI_PM_CTRL2 0x598
> +#define UTL_GP_CTL1 0x5a0
> +#define UTL_GP_CTL2 0x5a8
> +#define UTL_PCLK_DOMAIN_DBG1 0x5b0
> +#define UTL_PCLK_DOMAIN_DBG2 0x5b8
> +#define UTL_PCLK_DOMAIN_DBG3 0x5c0
> +#define UTL_PCLK_DOMAIN_DBG4 0x5c8
> +
> +/* PCI-E Stack registers */
> +#define PHB_PCIE_SYSTEM_CONFIG 0x600
> +#define PHB_PCIE_BUS_NUMBER 0x608
> +#define PHB_PCIE_SYSTEM_TEST 0x618
> +#define PHB_PCIE_LINK_MANAGEMENT 0x630
> +#define PHB_PCIE_LM_LINK_ACTIVE PPC_BIT(8)
> +#define PHB_PCIE_DLP_TRAIN_CTL 0x640
> +#define PHB_PCIE_DLP_TCTX_DISABLE PPC_BIT(1)
> +#define PHB_PCIE_DLP_TCRX_DISABLED PPC_BIT(16)
> +#define PHB_PCIE_DLP_INBAND_PRESENCE PPC_BIT(19)
> +#define PHB_PCIE_DLP_TC_DL_LINKUP PPC_BIT(21)
> +#define PHB_PCIE_DLP_TC_DL_PGRESET PPC_BIT(22)
> +#define PHB_PCIE_DLP_TC_DL_LINKACT PPC_BIT(23)
> +#define PHB_PCIE_SLOP_LOOPBACK_STATUS 0x648
> +#define PHB_PCIE_SYS_LINK_INIT 0x668
> +#define PHB_PCIE_UTL_CONFIG 0x670
> +#define PHB_PCIE_DLP_CONTROL 0x678
> +#define PHB_PCIE_UTL_ERRLOG1 0x680
> +#define PHB_PCIE_UTL_ERRLOG2 0x688
> +#define PHB_PCIE_UTL_ERRLOG3 0x690
> +#define PHB_PCIE_UTL_ERRLOG4 0x698
> +#define PHB_PCIE_DLP_ERRLOG1 0x6a0
> +#define PHB_PCIE_DLP_ERRLOG2 0x6a8
> +#define PHB_PCIE_DLP_ERR_STATUS 0x6b0
> +#define PHB_PCIE_DLP_ERR_COUNTERS 0x6b8
> +#define PHB_PCIE_UTL_ERR_INJECT 0x6c0
> +#define PHB_PCIE_TLDLP_ERR_INJECT 0x6c8
> +#define PHB_PCIE_LANE_EQ_CNTL0 0x6d0
> +#define PHB_PCIE_LANE_EQ_CNTL1 0x6d8
> +#define PHB_PCIE_LANE_EQ_CNTL2 0x6e0
> +#define PHB_PCIE_LANE_EQ_CNTL3 0x6e8
> +#define PHB_PCIE_STRAPPING 0x700
> +
> +/* Fundamental register set B */
> +#define PHB_VERSION 0x800
> +#define PHB_RESET 0x808
> +#define PHB_CONTROL 0x810
> +#define PHB_CTRL_IVE_128_BYTES PPC_BIT(24)
> +#define PHB_AIB_RX_CRED_INIT_TIMER 0x818
> +#define PHB_AIB_RX_CMD_CRED 0x820
> +#define PHB_AIB_RX_DATA_CRED 0x828
> +#define PHB_AIB_TX_CMD_CRED 0x830
> +#define PHB_AIB_TX_DATA_CRED 0x838
> +#define PHB_AIB_TX_CHAN_MAPPING 0x840
> +#define PHB_AIB_TAG_ENABLE 0x858
> +#define PHB_AIB_FENCE_CTRL 0x860
> +#define PHB_TCE_TAG_ENABLE 0x868
> +#define PHB_TCE_WATERMARK 0x870
> +#define PHB_TIMEOUT_CTRL1 0x878
> +#define PHB_TIMEOUT_CTRL2 0x880
> +#define PHB_QUIESCE_DMA_G 0x888
> +#define PHB_AIB_TAG_STATUS 0x900
> +#define PHB_TCE_TAG_STATUS 0x908
> +
> +/* FIR & Error registers */
> +#define PHB_LEM_FIR_ACCUM 0xc00
> +#define PHB_LEM_FIR_AND_MASK 0xc08
> +#define PHB_LEM_FIR_OR_MASK 0xc10
> +#define PHB_LEM_ERROR_MASK 0xc18
> +#define PHB_LEM_ERROR_AND_MASK 0xc20
> +#define PHB_LEM_ERROR_OR_MASK 0xc28
> +#define PHB_LEM_ACTION0 0xc30
> +#define PHB_LEM_ACTION1 0xc38
> +#define PHB_LEM_WOF 0xc40
> +#define PHB_ERR_STATUS 0xc80
> +#define PHB_ERR1_STATUS 0xc88
> +#define PHB_ERR_INJECT 0xc90
> +#define PHB_ERR_LEM_ENABLE 0xc98
> +#define PHB_ERR_IRQ_ENABLE 0xca0
> +#define PHB_ERR_FREEZE_ENABLE 0xca8
> +#define PHB_ERR_AIB_FENCE_ENABLE 0xcb0
> +#define PHB_ERR_LOG_0 0xcc0
> +#define PHB_ERR_LOG_1 0xcc8
> +#define PHB_ERR_STATUS_MASK 0xcd0
> +#define PHB_ERR1_STATUS_MASK 0xcd8
> +
> +#define PHB_OUT_ERR_STATUS 0xd00
> +#define PHB_OUT_ERR1_STATUS 0xd08
> +#define PHB_OUT_ERR_INJECT 0xd10
> +#define PHB_OUT_ERR_LEM_ENABLE 0xd18
> +#define PHB_OUT_ERR_IRQ_ENABLE 0xd20
> +#define PHB_OUT_ERR_FREEZE_ENABLE 0xd28
> +#define PHB_OUT_ERR_AIB_FENCE_ENABLE 0xd30
> +#define PHB_OUT_ERR_LOG_0 0xd40
> +#define PHB_OUT_ERR_LOG_1 0xd48
> +#define PHB_OUT_ERR_STATUS_MASK 0xd50
> +#define PHB_OUT_ERR1_STATUS_MASK 0xd58
> +
> +#define PHB_INA_ERR_STATUS 0xd80
> +#define PHB_INA_ERR1_STATUS 0xd88
> +#define PHB_INA_ERR_INJECT 0xd90
> +#define PHB_INA_ERR_LEM_ENABLE 0xd98
> +#define PHB_INA_ERR_IRQ_ENABLE 0xda0
> +#define PHB_INA_ERR_FREEZE_ENABLE 0xda8
> +#define PHB_INA_ERR_AIB_FENCE_ENABLE 0xdb0
> +#define PHB_INA_ERR_LOG_0 0xdc0
> +#define PHB_INA_ERR_LOG_1 0xdc8
> +#define PHB_INA_ERR_STATUS_MASK 0xdd0
> +#define PHB_INA_ERR1_STATUS_MASK 0xdd8
> +
> +#define PHB_INB_ERR_STATUS 0xe00
> +#define PHB_INB_ERR1_STATUS 0xe08
> +#define PHB_INB_ERR_INJECT 0xe10
> +#define PHB_INB_ERR_LEM_ENABLE 0xe18
> +#define PHB_INB_ERR_IRQ_ENABLE 0xe20
> +#define PHB_INB_ERR_FREEZE_ENABLE 0xe28
> +#define PHB_INB_ERR_AIB_FENCE_ENABLE 0xe30
> +#define PHB_INB_ERR_LOG_0 0xe40
> +#define PHB_INB_ERR_LOG_1 0xe48
> +#define PHB_INB_ERR_STATUS_MASK 0xe50
> +#define PHB_INB_ERR1_STATUS_MASK 0xe58
> +
> +/* Performance monitor & Debug registers */
> +#define PHB_TRACE_CONTROL 0xf80
> +#define PHB_PERFMON_CONFIG 0xf88
> +#define PHB_PERFMON_CTR0 0xf90
> +#define PHB_PERFMON_CTR1 0xf98
> +#define PHB_PERFMON_CTR2 0xfa0
> +#define PHB_PERFMON_CTR3 0xfa8
> +#define PHB_HOTPLUG_OVERRIDE 0xfb0
> +#define PHB_HPOVR_FORCE_RESAMPLE PPC_BIT(9)
> +#define PHB_HPOVR_PRESENCE_A PPC_BIT(10)
> +#define PHB_HPOVR_PRESENCE_B PPC_BIT(11)
> +#define PHB_HPOVR_LINK_ACTIVE PPC_BIT(12)
> +#define PHB_HPOVR_LINK_BIFURCATED PPC_BIT(13)
> +#define PHB_HPOVR_LINK_LANE_SWAPPED PPC_BIT(14)
> +
> +/*
> + * IODA2 on-chip tables
> + */
> +
> +#define IODA2_TBL_LIST 1
> +#define IODA2_TBL_LXIVT 2
> +#define IODA2_TBL_IVC_CAM 3
> +#define IODA2_TBL_RBA 4
> +#define IODA2_TBL_RCAM 5
> +#define IODA2_TBL_MRT 6
> +#define IODA2_TBL_PESTA 7
> +#define IODA2_TBL_PESTB 8
> +#define IODA2_TBL_TVT 9
> +#define IODA2_TBL_TCAM 10
> +#define IODA2_TBL_TDR 11
> +#define IODA2_TBL_M64BT 16
> +#define IODA2_TBL_M32DT 17
> +#define IODA2_TBL_PEEV 20
> +
> +/* LXIVT */
> +#define IODA2_LXIVT_SERVER_MASK PPC_BITMASK(8, 23)
> +#define IODA2_LXIVT_SERVER_LSH PPC_BITLSHIFT(23)
> +#define IODA2_LXIVT_PRIORITY_MASK PPC_BITMASK(24, 31)
> +#define IODA2_LXIVT_PRIORITY_LSH PPC_BITLSHIFT(31)
> +#define IODA2_LXIVT_NODE_ID_MASK PPC_BITMASK(56, 63)
> +#define IODA2_LXIVT_NODE_ID_LSH PPC_BITLSHIFT(63)
> +
> +/* IVT */
> +#define IODA2_IVT_SERVER_MASK PPC_BITMASK(0, 23)
> +#define IODA2_IVT_SERVER_LSH PPC_BITLSHIFT(23)
> +#define IODA2_IVT_PRIORITY_MASK PPC_BITMASK(24, 31)
> +#define IODA2_IVT_PRIORITY_LSH PPC_BITLSHIFT(31)
> +#define IODA2_IVT_GEN_MASK PPC_BITMASK(37, 38)
> +#define IODA2_IVT_GEN_LSH PPC_BITLSHIFT(38)
> +#define IODA2_IVT_P_MASK PPC_BITMASK(39, 39)
> +#define IODA2_IVT_P_LSH PPC_BITLSHIFT(39)
> +#define IODA2_IVT_Q_MASK PPC_BITMASK(47, 47)
> +#define IODA2_IVT_Q_LSH PPC_BITLSHIFT(47)
> +#define IODA2_IVT_PE_MASK PPC_BITMASK(48, 63)
> +#define IODA2_IVT_PE_LSH PPC_BITLSHIFT(63)
> +
> +/* TVT */
> +#define IODA2_TVT_TABLE_ADDR_MASK PPC_BITMASK(0, 47)
> +#define IODA2_TVT_TABLE_ADDR_LSH PPC_BITLSHIFT(47)
> +#define IODA2_TVT_NUM_LEVELS_MASK PPC_BITMASK(48, 50)
> +#define IODA2_TVT_NUM_LEVELS_LSH PPC_BITLSHIFT(50)
> +#define IODA2_TVE_1_LEVEL 0
> +#define IODA2_TVE_2_LEVELS 1
> +#define IODA2_TVE_3_LEVELS 2
> +#define IODA2_TVE_4_LEVELS 3
> +#define IODA2_TVE_5_LEVELS 4
> +#define IODA2_TVT_TCE_TABLE_SIZE_MASK PPC_BITMASK(51, 55)
> +#define IODA2_TVT_TCE_TABLE_SIZE_LSH PPC_BITLSHIFT(55)
> +#define IODA2_TVT_IO_PSIZE_MASK PPC_BITMASK(59, 63)
> +#define IODA2_TVT_IO_PSIZE_LSH PPC_BITLSHIFT(63)
> +
> +/* PESTA */
> +#define IODA2_PESTA_MMIO_FROZEN PPC_BIT(0)
> +
> +/* PESTB */
> +#define IODA2_PESTB_DMA_STOPPED PPC_BIT(0)
> +
> +/* M32DT */
> +#define IODA2_M32DT_PE_MASK PPC_BITMASK(8, 15)
> +#define IODA2_M32DT_PE_LSH PPC_BITLSHIFT(15)
> +
> +/* M64BT */
> +#define IODA2_M64BT_ENABLE PPC_BIT(0)
> +#define IODA2_M64BT_SINGLE_PE PPC_BIT(1)
> +#define IODA2_M64BT_BASE_MASK PPC_BITMASK(2, 31)
> +#define IODA2_M64BT_BASE_LSH PPC_BITLSHIFT(31)
> +#define IODA2_M64BT_MASK_MASK PPC_BITMASK(34, 63)
> +#define IODA2_M64BT_MASK_LSH PPC_BITLSHIFT(63)
> +#define IODA2_M64BT_SINGLE_BASE_MASK PPC_BITMASK(2, 26)
> +#define IODA2_M64BT_SINGLE_BASE_LSH PPC_BITLSHIFT(26)
> +#define IODA2_M64BT_PE_HI_MASK PPC_BITMASK(27, 31)
> +#define IODA2_M64BT_PE_HI_LSH PPC_BITLSHIFT(31)
> +#define IODA2_M64BT_SINGLE_MASK_MASK PPC_BITMASK(34, 58)
> +#define IODA2_M64BT_SINGLE_MASK_LSH PPC_BITLSHIFT(58)
> +#define IODA2_M64BT_PE_LOW_MASK PPC_BITMASK(59, 63)
> +#define IODA2_M64BT_PE_LOW_LSH PPC_BITLSHIFT(63)
> +
> +/*
> + * IODA2 in-memory tables
> + */
> +
> +/* PEST
> + *
> + * 2x8 bytes entries, PEST0 and PEST1
> + */
> +
> +#define IODA2_PEST0_MMIO_CAUSE PPC_BIT(2)
> +#define IODA2_PEST0_CFG_READ PPC_BIT(3)
> +#define IODA2_PEST0_CFG_WRITE PPC_BIT(4)
> +#define IODA2_PEST0_TTYPE_MASK PPC_BITMASK(5, 7)
> +#define IODA2_PEST0_TTYPE_LSH PPC_BITLSHIFT(7)
> +#define PEST_TTYPE_DMA_WRITE 0
> +#define PEST_TTYPE_MSI 1
> +#define PEST_TTYPE_DMA_READ 2
> +#define PEST_TTYPE_DMA_READ_RESP 3
> +#define PEST_TTYPE_MMIO_LOAD 4
> +#define PEST_TTYPE_MMIO_STORE 5
> +#define PEST_TTYPE_OTHER 7
> +#define IODA2_PEST0_CA_RETURN PPC_BIT(8)
> +#define IODA2_PEST0_UTL_RTOS_TIMEOUT PPC_BIT(8) /* Same bit as CA return */
> +#define IODA2_PEST0_UR_RETURN PPC_BIT(9)
> +#define IODA2_PEST0_UTL_NONFATAL PPC_BIT(10)
> +#define IODA2_PEST0_UTL_FATAL PPC_BIT(11)
> +#define IODA2_PEST0_PARITY_UE PPC_BIT(13)
> +#define IODA2_PEST0_UTL_CORRECTABLE PPC_BIT(14)
> +#define IODA2_PEST0_UTL_INTERRUPT PPC_BIT(15)
> +#define IODA2_PEST0_MMIO_XLATE PPC_BIT(16)
> +#define IODA2_PEST0_IODA2_ERROR PPC_BIT(16) /* Same bit as MMIO xlate */
> +#define IODA2_PEST0_TCE_PAGE_FAULT PPC_BIT(18)
> +#define IODA2_PEST0_TCE_ACCESS_FAULT PPC_BIT(19)
> +#define IODA2_PEST0_DMA_RESP_TIMEOUT PPC_BIT(20)
> +#define IODA2_PEST0_AIB_SIZE_INVALID PPC_BIT(21)
> +#define IODA2_PEST0_LEM_BIT_MASK PPC_BITMASK(26, 31)
> +#define IODA2_PEST0_LEM_BIT_LSH PPC_BITLSHIFT(31)
> +#define IODA2_PEST0_RID_MASK PPC_BITMASK(32, 47)
> +#define IODA2_PEST0_RID_LSH PPC_BITLSHIFT(47)
> +#define IODA2_PEST0_MSI_DATA_MASK PPC_BITMASK(48, 63)
> +#define IODA2_PEST0_MSI_DATA_LSH PPC_BITLSHIFT(63)
> +
> +#define IODA2_PEST1_FAIL_ADDR_MASK PPC_BITMASK(3, 63)
> +#define IODA2_PEST1_FAIL_ADDR_LSH PPC_BITLSHIFT(63)
> +
> +
> +#endif /* PCI_HOST_PNV_PHB3_REGS_H */
> diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
> index b70a13bd4175..b6feff140cb0 100644
> --- a/include/hw/ppc/pnv.h
> +++ b/include/hw/ppc/pnv.h
> @@ -25,6 +25,8 @@
> #include "hw/ppc/pnv_psi.h"
> #include "hw/ppc/pnv_occ.h"
>
> +typedef struct PnvPhb3State PnvPhb3State;
> +
> #define TYPE_PNV_CHIP "powernv-chip"
> #define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP)
> #define PNV_CHIP_CLASS(klass) \
> @@ -61,6 +63,10 @@ typedef struct PnvChip {
> PnvLpcController lpc;
> PnvPsi psi;
> PnvOCC occ;
> +
> + uint32_t num_phbs;
> +#define PNV_MAX_CHIP_PHB 4
> + PnvPhb3State *phbs[PNV_MAX_CHIP_PHB];
> } PnvChip;
>
> typedef struct PnvChipClass {
> diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h
> index 3757b2cab94b..731c2fff26e2 100644
> --- a/include/hw/ppc/pnv_xscom.h
> +++ b/include/hw/ppc/pnv_xscom.h
> @@ -66,6 +66,15 @@ typedef struct PnvXScomInterfaceClass {
> #define PNV_XSCOM_OCC_BASE 0x0066000
> #define PNV_XSCOM_OCC_SIZE 0x6000
>
> +#define PNV_XSCOM_PBCQ_NEST_BASE 0x2012000
> +#define PNV_XSCOM_PBCQ_NEST_SIZE 0x46
> +
> +#define PNV_XSCOM_PBCQ_PCI_BASE 0x9012000
> +#define PNV_XSCOM_PBCQ_PCI_SIZE 0x15
> +
> +#define PNV_XSCOM_PBCQ_SPCI_BASE 0x9013c00
> +#define PNV_XSCOM_PBCQ_SPCI_SIZE 0x5
> +
> extern void pnv_xscom_realize(PnvChip *chip, Error **errp);
> extern int pnv_xscom_populate(PnvChip *chip, void *fdt, int offset);
>
> diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h
> index e6699c917e24..eeee5abd86f5 100644
> --- a/include/hw/ppc/xics.h
> +++ b/include/hw/ppc/xics.h
> @@ -190,6 +190,7 @@ void icp_set_mfrr(ICPState *icp, uint8_t mfrr);
> uint32_t icp_accept(ICPState *ss);
> uint32_t icp_ipoll(ICPState *ss, uint32_t *mfrr);
> void icp_eoi(ICPState *icp, uint32_t xirr);
> +void icp_irq(ICSState *ics, int server, int nr, uint8_t priority);
>
> void ics_simple_write_xive(ICSState *ics, int nr, int server,
> uint8_t priority, uint8_t saved_priority);
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 66+ messages in thread* Re: [Qemu-devel] [PATCH 20/21] ppc/pnv: Add model for Power8 PHB3 PCIe Host bridge
2017-04-10 8:14 ` David Gibson
@ 2017-04-11 3:05 ` Benjamin Herrenschmidt
2017-04-11 6:06 ` David Gibson
2017-04-11 16:03 ` Cédric Le Goater
2017-04-11 16:35 ` Cédric Le Goater
1 sibling, 2 replies; 66+ messages in thread
From: Benjamin Herrenschmidt @ 2017-04-11 3:05 UTC (permalink / raw)
To: David Gibson, Cédric Le Goater
Cc: qemu-ppc, qemu-devel, Marcel Apfelbaum, Michael S. Tsirkin
On Mon, 2017-04-10 at 18:14 +1000, David Gibson wrote:
> > + switch (size) {
> > + case 1:
> > + break;
> > + case 2:
> > + val = bswap16(val);
>
> An unconditional bswap() seems unlikely to be correct. What's the
> purpose of thise?
Though it is :-) I *think* ... I did test with both LE and BE hosts I
believe but Cedric can double check.
>From memory it comes from the fact that the PHB register space is
declared to be big endian since 99% of it actually is.
However the CONFIG_DATA register used to issue config space accesses is
"special" and expect little endian accesses.
However because the whole region is marked BE, qemu will have done
the necessary swapping for BE, which thus needs to be undone for
that specific register unconditionally:
- BE host will not swap the value, so we get the LE value written by
the guest which needs to be swapped to BE.
- LE host will have swapped the value as if it was BE except it isn't
so we need to re-swap it.
IE. Another option would be to create a specific memory region just for
that one register but it's easier to just unconditionally swap.
> > + break;
> > + case 4:
> > + val = bswap32(val);
> > + break;
>
> No 64-bit config registers?
No, they don't exist. (Which is also why an assert isn't a good
idea as other registers do support 64-bit accesses).
Ben.
^ permalink raw reply [flat|nested] 66+ messages in thread* Re: [Qemu-devel] [PATCH 20/21] ppc/pnv: Add model for Power8 PHB3 PCIe Host bridge
2017-04-11 3:05 ` Benjamin Herrenschmidt
@ 2017-04-11 6:06 ` David Gibson
2017-04-11 16:03 ` Cédric Le Goater
1 sibling, 0 replies; 66+ messages in thread
From: David Gibson @ 2017-04-11 6:06 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: Cédric Le Goater, qemu-ppc, qemu-devel, Marcel Apfelbaum,
Michael S. Tsirkin
[-- Attachment #1: Type: text/plain, Size: 1886 bytes --]
On Tue, Apr 11, 2017 at 01:05:51PM +1000, Benjamin Herrenschmidt wrote:
> On Mon, 2017-04-10 at 18:14 +1000, David Gibson wrote:
> > > + switch (size) {
> > > + case 1:
> > > + break;
> > > + case 2:
> > > + val = bswap16(val);
> >
> > An unconditional bswap() seems unlikely to be correct. What's the
> > purpose of thise?
>
> Though it is :-) I *think* ... I did test with both LE and BE hosts I
> believe but Cedric can double check.
>
> >From memory it comes from the fact that the PHB register space is
> declared to be big endian since 99% of it actually is.
>
> However the CONFIG_DATA register used to issue config space accesses is
> "special" and expect little endian accesses.
>
> However because the whole region is marked BE, qemu will have done
> the necessary swapping for BE, which thus needs to be undone for
> that specific register unconditionally:
>
> - BE host will not swap the value, so we get the LE value written by
> the guest which needs to be swapped to BE.
>
> - LE host will have swapped the value as if it was BE except it isn't
> so we need to re-swap it.
>
> IE. Another option would be to create a specific memory region just for
> that one register but it's easier to just unconditionally swap.
Ok, that makes sense. A comment saying that this one register is LE
whereas most are BE would be helpful.
> > > + break;
> > > + case 4:
> > > + val = bswap32(val);
> > > + break;
> >
> > No 64-bit config registers?
>
> No, they don't exist. (Which is also why an assert isn't a good
> idea as other registers do support 64-bit accesses).
Ah, ok.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 66+ messages in thread* Re: [Qemu-devel] [PATCH 20/21] ppc/pnv: Add model for Power8 PHB3 PCIe Host bridge
2017-04-11 3:05 ` Benjamin Herrenschmidt
2017-04-11 6:06 ` David Gibson
@ 2017-04-11 16:03 ` Cédric Le Goater
1 sibling, 0 replies; 66+ messages in thread
From: Cédric Le Goater @ 2017-04-11 16:03 UTC (permalink / raw)
To: Benjamin Herrenschmidt, David Gibson
Cc: qemu-ppc, qemu-devel, Marcel Apfelbaum, Michael S. Tsirkin
On 04/11/2017 05:05 AM, Benjamin Herrenschmidt wrote:
> On Mon, 2017-04-10 at 18:14 +1000, David Gibson wrote:
>>> + switch (size) {
>>> + case 1:
>>> + break;
>>> + case 2:
>>> + val = bswap16(val);
>>
>> An unconditional bswap() seems unlikely to be correct. What's the
>> purpose of thise?
>
> Though it is :-) I *think* ... I did test with both LE and BE hosts I
> believe but Cedric can double check.
Yeah that works. I ran a PowerNV guest under a Pseries BE guest under
a PowerNV P8 host. Network was running on the final guest so I suppose
that's enough to check the PCI layer.
>
> From memory it comes from the fact that the PHB register space is
> declared to be big endian since 99% of it actually is.
>
> However the CONFIG_DATA register used to issue config space accesses is
> "special" and expect little endian accesses.
>
> However because the whole region is marked BE, qemu will have done
> the necessary swapping for BE, which thus needs to be undone for
> that specific register unconditionally:
>
> - BE host will not swap the value, so we get the LE value written by
> the guest which needs to be swapped to BE.
>
> - LE host will have swapped the value as if it was BE except it isn't
> so we need to re-swap it.
>
> IE. Another option would be to create a specific memory region just for
> that one register but it's easier to just unconditionally swap.
No that's fine. I will add some helper routines to explain what is
happening. I have had to do some thing similar with the Aspeed flash
controller tests when using the Command mode.
Thanks,
C.
>>> + break;
>>> + case 4:
>>> + val = bswap32(val);
>>> + break;
>>
>> No 64-bit config registers?
>
> No, they don't exist. (Which is also why an assert isn't a good
> idea as other registers do support 64-bit accesses).
>
> Ben.
>
^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [Qemu-devel] [PATCH 20/21] ppc/pnv: Add model for Power8 PHB3 PCIe Host bridge
2017-04-10 8:14 ` David Gibson
2017-04-11 3:05 ` Benjamin Herrenschmidt
@ 2017-04-11 16:35 ` Cédric Le Goater
1 sibling, 0 replies; 66+ messages in thread
From: Cédric Le Goater @ 2017-04-11 16:35 UTC (permalink / raw)
To: David Gibson
Cc: qemu-ppc, qemu-devel, Benjamin Herrenschmidt, Marcel Apfelbaum,
Michael S. Tsirkin
On 04/10/2017 10:14 AM, David Gibson wrote:
> +/* Copyright (c) 2013-2017, IBM Corporation.
> + *
> + * Licensed under the Apache License, Version 2.0 (the "License");
> + * you may not use this file except in compliance with the License.
> + * You may obtain a copy of the License at
> + *
> + * http://www.apache.org/licenses/LICENSE-2.0
> + *
> + * Unless required by applicable law or agreed to in writing, software
> + * distributed under the License is distributed on an "AS IS" BASIS,
> + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
> + * implied.
> + * See the License for the specific language governing permissions and
> + * limitations under the License.
> + */
> +
> +#ifndef PCI_HOST_PNV_PHB3_REGS_H
> +#define PCI_HOST_PNV_PHB3_REGS_H
> +
> +#define PPC_BIT(bit) (0x8000000000000000UL >> (bit))
> +#define PPC_BIT32(bit) (0x80000000UL >> (bit))
> +#define PPC_BIT8(bit) (0x80UL >> (bit))
> +#define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
> +#define PPC_BITMASK32(bs, be) ((PPC_BIT32(bs) - PPC_BIT32(be)) | \
> + PPC_BIT32(bs))
> +#define PPC_BITLSHIFT(be) (63 - (be))
> +#define PPC_BITLSHIFT32(be) (31 - (be))
These could probably be defined for all hw/ppc/ and target/ppc to use ?
C.
^ permalink raw reply [flat|nested] 66+ messages in thread
* [Qemu-devel] [PATCH 21/21] ppc/pnv: Create a default PCI layout
2017-04-05 12:41 [Qemu-devel] [PATCH 00/21] pnv: PSI, OCC, IPMI and PCI models Cédric Le Goater
` (19 preceding siblings ...)
2017-04-05 12:41 ` [Qemu-devel] [PATCH 20/21] ppc/pnv: Add model for Power8 PHB3 PCIe Host bridge Cédric Le Goater
@ 2017-04-05 12:41 ` Cédric Le Goater
2017-04-10 8:16 ` David Gibson
2017-04-11 11:10 ` [Qemu-devel] [Qemu-ppc] " Andrea Bolognani
20 siblings, 2 replies; 66+ messages in thread
From: Cédric Le Goater @ 2017-04-05 12:41 UTC (permalink / raw)
To: David Gibson
Cc: qemu-ppc, qemu-devel, Benjamin Herrenschmidt, Marcel Apfelbaum,
Michael S. Tsirkin, Cédric Le Goater
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This creates a legacy PCIe->PCI bridge under the PHB by default to which
a bunch of standard devices are attached. Currently:
- VGA (as specified by -vga)
- USB (with keyboard and mouse if graphcis is enabled)
- AHCI
- e1000
This gives us something close to a standard OpenPower platform.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
[clg: updated for qemu-2.9
reworked pnv_create_pci_legacy_bridge() ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/pnv.c | 111 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 111 insertions(+)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index db6e078edcea..766e6cf4bc12 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -48,6 +48,10 @@
#include "hw/pci/pci_bridge.h"
#include "hw/pci/msi.h"
#include "hw/pci-host/pnv_phb3.h"
+#include "hw/usb.h"
+#include "hw/ide/pci.h"
+#include "hw/ide/ahci.h"
+#include "net/net.h"
#include <libfdt.h>
@@ -573,6 +577,87 @@ static ISABus *pnv_isa_create(PnvChip *chip)
return isa_bus;
}
+
+/* Returns whether we want to use VGA or not */
+static int pnv_vga_init(PCIBus *pci_bus)
+{
+ switch (vga_interface_type) {
+ case VGA_NONE:
+ return false;
+ case VGA_DEVICE:
+ return true;
+ case VGA_STD:
+ case VGA_VIRTIO:
+ return pci_vga_init(pci_bus) != NULL;
+ default:
+ fprintf(stderr, "This vga model is not supported,"
+ "currently it only supports -vga std\n");
+ exit(0);
+ }
+}
+
+static void pnv_nic_init(PCIBus *pci_bus)
+{
+ int i;
+
+ for (i = 0; i < nb_nics; i++) {
+ NICInfo *nd = &nd_table[i];
+ DeviceState *dev;
+ PCIDevice *pdev;
+ Error *err = NULL;
+
+ pdev = pci_create(pci_bus, -1, "e1000");
+ dev = &pdev->qdev;
+ qdev_set_nic_properties(dev, nd);
+ object_property_set_bool(OBJECT(dev), true, "realized", &err);
+ if (err) {
+ error_report_err(err);
+ object_unparent(OBJECT(dev));
+ exit(1);
+ }
+ }
+}
+
+#define MAX_SATA_PORTS 6
+
+static void pnv_storage_init(PCIBus *pci_bus)
+{
+ DriveInfo *hd[MAX_SATA_PORTS];
+ PCIDevice *ahci;
+
+ /* Add an AHCI device. We use an ICH9 since that's all we have
+ * at hand for PCI AHCI but it shouldn't really matter
+ */
+ ahci = pci_create_simple(pci_bus, -1, "ich9-ahci");
+ g_assert(MAX_SATA_PORTS == ICH_AHCI(ahci)->ahci.ports);
+ ide_drive_get(hd, ICH_AHCI(ahci)->ahci.ports);
+ ahci_ide_create_devs(ahci, hd);
+}
+
+static PCIBus *pnv_create_pci_legacy_bridge(PnvPhb3State *phb,
+ uint8_t chassis_nr)
+{
+ PCIDevice *dev;
+ PCIHostState *pcih = PCI_HOST_BRIDGE(phb);
+ PCIDevice *pdev;
+ PCIBus *parent;
+
+ /* Add root complex */
+ pdev = pci_create_multifunction(pcih->bus, 0, false, TYPE_PNV_PHB3_RC);
+ qdev_prop_set_uint8(&pdev->qdev, "chassis", phb->chip_id * 4 + phb->phb_id);
+ qdev_prop_set_uint16(&pdev->qdev, "slot", 1);
+ qdev_init_nofail(&pdev->qdev);
+
+ /* Setup bus for that chip */
+ parent = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
+
+ dev = pci_create_multifunction(parent, 0, false, "pci-bridge");
+ qdev_prop_set_uint8(&dev->qdev, "chassis_nr", chassis_nr);
+ dev->qdev.id = "pci";
+ qdev_init_nofail(&dev->qdev);
+ return pci_bridge_get_sec_bus(PCI_BRIDGE(dev));
+}
+
static void ppc_powernv_init(MachineState *machine)
{
PnvMachineState *pnv = POWERNV_MACHINE(machine);
@@ -581,6 +666,8 @@ static void ppc_powernv_init(MachineState *machine)
long fw_size;
int i;
char *chip_typename;
+ PCIBus *pbus;
+ bool has_gfx = false;
/* allocate RAM */
if (machine->ram_size < (1 * G_BYTE)) {
@@ -682,6 +769,30 @@ static void ppc_powernv_init(MachineState *machine)
* host to powerdown */
pnv->powerdown_notifier.notify = pnv_powerdown_notify;
qemu_register_powerdown_notifier(&pnv->powerdown_notifier);
+
+ /* Add a PCI switch */
+ pbus = pnv_create_pci_legacy_bridge(pnv->chips[0]->phbs[0], 128);
+
+ /* Graphics & USB */
+ if (pnv_vga_init(pbus)) {
+ has_gfx = true;
+ machine->usb |= defaults_enabled() && !machine->usb_disabled;
+ }
+ if (machine->usb) {
+ pci_create_simple(pbus, -1, "nec-usb-xhci");
+ if (has_gfx) {
+ USBBus *usb_bus = usb_bus_find(-1);
+
+ usb_create_simple(usb_bus, "usb-kbd");
+ usb_create_simple(usb_bus, "usb-mouse");
+ }
+ }
+
+ /* Add NIC */
+ pnv_nic_init(pbus);
+
+ /* Add storage */
+ pnv_storage_init(pbus);
}
/*
--
2.7.4
^ permalink raw reply related [flat|nested] 66+ messages in thread* Re: [Qemu-devel] [PATCH 21/21] ppc/pnv: Create a default PCI layout
2017-04-05 12:41 ` [Qemu-devel] [PATCH 21/21] ppc/pnv: Create a default PCI layout Cédric Le Goater
@ 2017-04-10 8:16 ` David Gibson
2017-04-11 11:10 ` [Qemu-devel] [Qemu-ppc] " Andrea Bolognani
1 sibling, 0 replies; 66+ messages in thread
From: David Gibson @ 2017-04-10 8:16 UTC (permalink / raw)
To: Cédric Le Goater
Cc: qemu-ppc, qemu-devel, Benjamin Herrenschmidt, Marcel Apfelbaum,
Michael S. Tsirkin
[-- Attachment #1: Type: text/plain, Size: 5727 bytes --]
On Wed, Apr 05, 2017 at 02:41:46PM +0200, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>
> This creates a legacy PCIe->PCI bridge under the PHB by default to which
> a bunch of standard devices are attached. Currently:
>
> - VGA (as specified by -vga)
> - USB (with keyboard and mouse if graphcis is enabled)
> - AHCI
> - e1000
>
> This gives us something close to a standard OpenPower platform.
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> [clg: updated for qemu-2.9
> reworked pnv_create_pci_legacy_bridge() ]
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Apart from one nit below.
> ---
> hw/ppc/pnv.c | 111 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 111 insertions(+)
>
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index db6e078edcea..766e6cf4bc12 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -48,6 +48,10 @@
> #include "hw/pci/pci_bridge.h"
> #include "hw/pci/msi.h"
> #include "hw/pci-host/pnv_phb3.h"
> +#include "hw/usb.h"
> +#include "hw/ide/pci.h"
> +#include "hw/ide/ahci.h"
> +#include "net/net.h"
>
> #include <libfdt.h>
>
> @@ -573,6 +577,87 @@ static ISABus *pnv_isa_create(PnvChip *chip)
> return isa_bus;
> }
>
> +
> +/* Returns whether we want to use VGA or not */
> +static int pnv_vga_init(PCIBus *pci_bus)
> +{
> + switch (vga_interface_type) {
> + case VGA_NONE:
> + return false;
> + case VGA_DEVICE:
> + return true;
> + case VGA_STD:
> + case VGA_VIRTIO:
> + return pci_vga_init(pci_bus) != NULL;
> + default:
> + fprintf(stderr, "This vga model is not supported,"
> + "currently it only supports -vga std\n");
This message doesn't appear to be entirely accurate, since virtio-vga
is apparently supported above as well. Also this should probably be
an error_report().
> + exit(0);
> + }
> +}
> +
> +static void pnv_nic_init(PCIBus *pci_bus)
> +{
> + int i;
> +
> + for (i = 0; i < nb_nics; i++) {
> + NICInfo *nd = &nd_table[i];
> + DeviceState *dev;
> + PCIDevice *pdev;
> + Error *err = NULL;
> +
> + pdev = pci_create(pci_bus, -1, "e1000");
> + dev = &pdev->qdev;
> + qdev_set_nic_properties(dev, nd);
> + object_property_set_bool(OBJECT(dev), true, "realized", &err);
> + if (err) {
> + error_report_err(err);
> + object_unparent(OBJECT(dev));
> + exit(1);
> + }
> + }
> +}
> +
> +#define MAX_SATA_PORTS 6
> +
> +static void pnv_storage_init(PCIBus *pci_bus)
> +{
> + DriveInfo *hd[MAX_SATA_PORTS];
> + PCIDevice *ahci;
> +
> + /* Add an AHCI device. We use an ICH9 since that's all we have
> + * at hand for PCI AHCI but it shouldn't really matter
> + */
> + ahci = pci_create_simple(pci_bus, -1, "ich9-ahci");
> + g_assert(MAX_SATA_PORTS == ICH_AHCI(ahci)->ahci.ports);
> + ide_drive_get(hd, ICH_AHCI(ahci)->ahci.ports);
> + ahci_ide_create_devs(ahci, hd);
> +}
> +
> +static PCIBus *pnv_create_pci_legacy_bridge(PnvPhb3State *phb,
> + uint8_t chassis_nr)
> +{
> + PCIDevice *dev;
> + PCIHostState *pcih = PCI_HOST_BRIDGE(phb);
> + PCIDevice *pdev;
> + PCIBus *parent;
> +
> + /* Add root complex */
> + pdev = pci_create_multifunction(pcih->bus, 0, false, TYPE_PNV_PHB3_RC);
> + qdev_prop_set_uint8(&pdev->qdev, "chassis", phb->chip_id * 4 + phb->phb_id);
> + qdev_prop_set_uint16(&pdev->qdev, "slot", 1);
> + qdev_init_nofail(&pdev->qdev);
> +
> + /* Setup bus for that chip */
> + parent = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
> +
> + dev = pci_create_multifunction(parent, 0, false, "pci-bridge");
> + qdev_prop_set_uint8(&dev->qdev, "chassis_nr", chassis_nr);
> + dev->qdev.id = "pci";
> + qdev_init_nofail(&dev->qdev);
> + return pci_bridge_get_sec_bus(PCI_BRIDGE(dev));
> +}
> +
> static void ppc_powernv_init(MachineState *machine)
> {
> PnvMachineState *pnv = POWERNV_MACHINE(machine);
> @@ -581,6 +666,8 @@ static void ppc_powernv_init(MachineState *machine)
> long fw_size;
> int i;
> char *chip_typename;
> + PCIBus *pbus;
> + bool has_gfx = false;
>
> /* allocate RAM */
> if (machine->ram_size < (1 * G_BYTE)) {
> @@ -682,6 +769,30 @@ static void ppc_powernv_init(MachineState *machine)
> * host to powerdown */
> pnv->powerdown_notifier.notify = pnv_powerdown_notify;
> qemu_register_powerdown_notifier(&pnv->powerdown_notifier);
> +
> + /* Add a PCI switch */
> + pbus = pnv_create_pci_legacy_bridge(pnv->chips[0]->phbs[0], 128);
> +
> + /* Graphics & USB */
> + if (pnv_vga_init(pbus)) {
> + has_gfx = true;
> + machine->usb |= defaults_enabled() && !machine->usb_disabled;
> + }
> + if (machine->usb) {
> + pci_create_simple(pbus, -1, "nec-usb-xhci");
> + if (has_gfx) {
> + USBBus *usb_bus = usb_bus_find(-1);
> +
> + usb_create_simple(usb_bus, "usb-kbd");
> + usb_create_simple(usb_bus, "usb-mouse");
> + }
> + }
> +
> + /* Add NIC */
> + pnv_nic_init(pbus);
> +
> + /* Add storage */
> + pnv_storage_init(pbus);
> }
>
> /*
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 66+ messages in thread* Re: [Qemu-devel] [Qemu-ppc] [PATCH 21/21] ppc/pnv: Create a default PCI layout
2017-04-05 12:41 ` [Qemu-devel] [PATCH 21/21] ppc/pnv: Create a default PCI layout Cédric Le Goater
2017-04-10 8:16 ` David Gibson
@ 2017-04-11 11:10 ` Andrea Bolognani
2017-04-11 16:50 ` Cédric Le Goater
1 sibling, 1 reply; 66+ messages in thread
From: Andrea Bolognani @ 2017-04-11 11:10 UTC (permalink / raw)
To: Cédric Le Goater, David Gibson
Cc: Michael S. Tsirkin, qemu-devel, qemu-ppc, Marcel Apfelbaum
On Wed, 2017-04-05 at 14:41 +0200, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>
> This creates a legacy PCIe->PCI bridge under the PHB by default to which
> a bunch of standard devices are attached. Currently:
>
> - VGA (as specified by -vga)
> - USB (with keyboard and mouse if graphcis is enabled)
> - AHCI
> - e1000
>
> This gives us something close to a standard OpenPower platform.
These bridges and devices are not added when -nodefaults
is in use, right?
--
Andrea Bolognani / Red Hat / Virtualization
^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [Qemu-devel] [Qemu-ppc] [PATCH 21/21] ppc/pnv: Create a default PCI layout
2017-04-11 11:10 ` [Qemu-devel] [Qemu-ppc] " Andrea Bolognani
@ 2017-04-11 16:50 ` Cédric Le Goater
2017-04-12 8:02 ` Andrea Bolognani
0 siblings, 1 reply; 66+ messages in thread
From: Cédric Le Goater @ 2017-04-11 16:50 UTC (permalink / raw)
To: Andrea Bolognani, David Gibson
Cc: Michael S. Tsirkin, qemu-devel, qemu-ppc, Marcel Apfelbaum
On 04/11/2017 01:10 PM, Andrea Bolognani wrote:
> On Wed, 2017-04-05 at 14:41 +0200, Cédric Le Goater wrote:
>> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>>
>> This creates a legacy PCIe->PCI bridge under the PHB by default to which
>> a bunch of standard devices are attached. Currently:
>>
>> - VGA (as specified by -vga)
>> - USB (with keyboard and mouse if graphcis is enabled)
>> - AHCI
>> - e1000
>>
>> This gives us something close to a standard OpenPower platform.
>
> These bridges and devices are not added when -nodefaults
> is in use, right?
I haven't checked that yet but I will.
Thanks,
C.
^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [Qemu-devel] [Qemu-ppc] [PATCH 21/21] ppc/pnv: Create a default PCI layout
2017-04-11 16:50 ` Cédric Le Goater
@ 2017-04-12 8:02 ` Andrea Bolognani
2017-04-12 9:01 ` Cédric Le Goater
0 siblings, 1 reply; 66+ messages in thread
From: Andrea Bolognani @ 2017-04-12 8:02 UTC (permalink / raw)
To: Cédric Le Goater, David Gibson
Cc: Michael S. Tsirkin, qemu-devel, qemu-ppc, Marcel Apfelbaum
On Tue, 2017-04-11 at 18:50 +0200, Cédric Le Goater wrote:
> > These bridges and devices are not added when -nodefaults
> > is in use, right?
>
> I haven't checked that yet but I will.
Thanks. This is very important for libvirt, where we need
to have full control of the guest's hardware.
--
Andrea Bolognani / Red Hat / Virtualization
^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [Qemu-devel] [Qemu-ppc] [PATCH 21/21] ppc/pnv: Create a default PCI layout
2017-04-12 8:02 ` Andrea Bolognani
@ 2017-04-12 9:01 ` Cédric Le Goater
0 siblings, 0 replies; 66+ messages in thread
From: Cédric Le Goater @ 2017-04-12 9:01 UTC (permalink / raw)
To: Andrea Bolognani, David Gibson
Cc: Michael S. Tsirkin, qemu-devel, qemu-ppc, Marcel Apfelbaum
On 04/12/2017 10:02 AM, Andrea Bolognani wrote:
> On Tue, 2017-04-11 at 18:50 +0200, Cédric Le Goater wrote:
>>> These bridges and devices are not added when -nodefaults
>>> is in use, right?
>>
>> I haven't checked that yet but I will.
>
> Thanks. This is very important for libvirt, where we need
> to have full control of the guest's hardware.
OK. and so, this is not the case. This patch will need to be
a little more subtle to handle -nodefaults.
Thanks,
C.
^ permalink raw reply [flat|nested] 66+ messages in thread