Re: [PATCH v5 1/4] gpio: mvebu: Add limited PWM support

[Ralph Sennhauser <ralph.sennhauser@gmail.com>]

On Wed, 12 Apr 2017 19:11:21 +0200
Thierry Reding <thierry.reding@gmail.com> wrote:

> On Sun, Apr 09, 2017 at 08:09:27PM +0200, Ralph Sennhauser wrote:
> > From: Andrew Lunn <andrew@lunn.ch>
> > 
> > Armada 370/XP devices can 'blink' GPIO lines with a configurable on
> > and off period. This can be modelled as a PWM.
> > 
> > However, there are only two sets of PWM configuration registers for
> > all the GPIO lines. This driver simply allows a single GPIO line per
> > GPIO chip of 32 lines to be used as a PWM. Attempts to use more
> > return EBUSY.
> > 
> > Due to the interleaving of registers it is not simple to separate
> > the PWM driver from the GPIO driver. Thus the GPIO driver has been
> > extended with a PWM driver.
> > 
> > Signed-off-by: Andrew Lunn <andrew@lunn.ch>
> > URL: https://patchwork.ozlabs.org/patch/427287/
> > URL: https://patchwork.ozlabs.org/patch/427295/
> > [Ralph Sennhauser:
> >   * Port forward
> >   * Merge PWM portion into gpio-mvebu.c
> >   * Switch to atomic PWM API
> >   * Add new compatible string marvell,armada-370-xp-gpio
> >   * Update and merge documentation patch
> >   * Update MAINTAINERS]
> > Signed-off-by: Ralph Sennhauser <ralph.sennhauser@gmail.com>
> > Tested-by: Andrew Lunn <andrew@lunn.ch>
> > ---
> >  .../devicetree/bindings/gpio/gpio-mvebu.txt        |  32 ++
> >  MAINTAINERS                                        |   2 +
> >  drivers/gpio/gpio-mvebu.c                          | 324
> > ++++++++++++++++++++- 3 files changed, 346 insertions(+), 12
> > deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
> > b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt index
> > a6f3bec..fe49e9d 100644 ---
> > a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt +++
> > b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt @@ -38,6
> > +38,24 @@ Required properties:
> >  - #gpio-cells: Should be two. The first cell is the pin number. The
> >    second cell is reserved for flags, unused at the moment.
> >  
> > +Optional properties:
> > +
> > +In order to use the gpio lines in PWM mode, some additional
> > optional +properties are required. Only Armada 370 and XP support
> > these properties. +
> > +- compatible: Must contain "marvell,armada-370-xp-gpio"
> > +
> > +- reg: an additional register set is needed, for the GPIO Blink
> > +  Counter on/off registers.
> > +
> > +- reg-names: Must contain an entry "pwm" corresponding to the
> > +  additional register range needed for pwm operation.
> > +
> > +- #pwm-cells: Should be two. The first cell is the GPIO line
> > number. The
> > +  second cell is the period in nanoseconds.
> > +
> > +- clocks: Must be a phandle to the clock for the gpio controller.
> > +
> >  Example:
> >  
> >  		gpio0: gpio@d0018100 {
> > @@ -51,3 +69,17 @@ Example:
> >  			#interrupt-cells = <2>;
> >  			interrupts = <16>, <17>, <18>, <19>;
> >  		};
> > +
> > +		gpio1: gpio@18140 {
> > +			compatible = "marvell,armada-370-xp-gpio";
> > +			reg = <0x18140 0x40>, <0x181c8 0x08>;
> > +			reg-names = "gpio", "pwm";
> > +			ngpios = <17>;
> > +			gpio-controller;
> > +			#gpio-cells = <2>;
> > +			#pwm-cells = <2>;
> > +			interrupt-controller;
> > +			#interrupt-cells = <2>;
> > +			interrupts = <87>, <88>, <89>;
> > +			clocks = <&coreclk 0>;
> > +		};  
> 
> This is going to need an Acked-by from one of the device tree
> maintainers. Rob and devicetree@vger.kernel.org are on Cc, but I
> suspect nobody might look for the binding change "hidden" in this
> patch.
> 
> Maybe best to split this off into a separate patch, or explicitly ping
> Rob to look at this patch.

Hi Thierry,

Rob asked for the new compatible string so he did see it presumably. As
you prefer to have an ACK by him I'll see to getting one for the driver
(bindings part). The patch could be split but then one might want to
split it even further. Like this the first patch in the series is a nice
self contained package.

>
<snip/>
> 
> > +
> > +	mvpwm->clk_rate = clk_get_rate(mvchip->clk);
> > +	if (!mvpwm->clk_rate) {
> > +		dev_err(dev, "failed to get clock rate\n");
> > +		return -EINVAL;
> > +	}
> > +
> > +	mvpwm->chip.dev = dev;
> > +	mvpwm->chip.ops = &mvebu_pwm_ops;
> > +	mvpwm->chip.base = mvchip->chip.base;
> > +	mvpwm->chip.npwm = mvchip->chip.ngpio;  
> 
> I still would've done this differently. If you use this with a PWM
> user you have to hook it up via DT anyway, so it doesn't matter
> whether you specify the PWM index or the GPIO via some other
> property. The _only_ use-case where this might actually be an
> advantage is if you request a PWM via the sysfs interface.

Let me answer this in the other mail where you bring this up.

> 
<snip/>
> All of my comments are effectively of a bikeshed nature, so from a PWM
> perspective this is:
> 
> Acked-by: Thierry Reding <thierry.reding@gmail.com>

Thanks for the detailed review and the ACK. Will work on all the
mentioned bits for v6.

Ralph